bnx2x: tx_has_work should not wait for FW
[linux-2.6.git] / drivers / net / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2009 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>  /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/bitops.h>
35 #include <linux/irq.h>
36 #include <linux/delay.h>
37 #include <asm/byteorder.h>
38 #include <linux/time.h>
39 #include <linux/ethtool.h>
40 #include <linux/mii.h>
41 #include <linux/if_vlan.h>
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
51 #include <linux/io.h>
52
53 #include "bnx2x_reg.h"
54 #include "bnx2x_fw_defs.h"
55 #include "bnx2x_hsi.h"
56 #include "bnx2x_link.h"
57 #include "bnx2x.h"
58 #include "bnx2x_init.h"
59
60 #define DRV_MODULE_VERSION      "1.45.26"
61 #define DRV_MODULE_RELDATE      "2009/01/26"
62 #define BNX2X_BC_VER            0x040200
63
64 /* Time in jiffies before concluding the transmitter is hung */
65 #define TX_TIMEOUT              (5*HZ)
66
67 static char version[] __devinitdata =
68         "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
69         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70
71 MODULE_AUTHOR("Eliezer Tamir");
72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION);
75
76 static int disable_tpa;
77 static int use_inta;
78 static int poll;
79 static int debug;
80 static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
81 static int use_multi;
82
83 module_param(disable_tpa, int, 0);
84 module_param(use_inta, int, 0);
85 module_param(poll, int, 0);
86 module_param(debug, int, 0);
87 MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
88 MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
89 MODULE_PARM_DESC(poll, "use polling (for debug)");
90 MODULE_PARM_DESC(debug, "default debug msglevel");
91
92 #ifdef BNX2X_MULTI
93 module_param(use_multi, int, 0);
94 MODULE_PARM_DESC(use_multi, "use per-CPU queues");
95 #endif
96 static struct workqueue_struct *bnx2x_wq;
97
98 enum bnx2x_board_type {
99         BCM57710 = 0,
100         BCM57711 = 1,
101         BCM57711E = 2,
102 };
103
104 /* indexed by board_type, above */
105 static struct {
106         char *name;
107 } board_info[] __devinitdata = {
108         { "Broadcom NetXtreme II BCM57710 XGb" },
109         { "Broadcom NetXtreme II BCM57711 XGb" },
110         { "Broadcom NetXtreme II BCM57711E XGb" }
111 };
112
113
114 static const struct pci_device_id bnx2x_pci_tbl[] = {
115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
121         { 0 }
122 };
123
124 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
125
126 /****************************************************************************
127 * General service functions
128 ****************************************************************************/
129
130 /* used only at init
131  * locking is done by mcp
132  */
133 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
134 {
135         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
136         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
137         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
138                                PCICFG_VENDOR_ID_OFFSET);
139 }
140
141 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
142 {
143         u32 val;
144
145         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
146         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
147         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
148                                PCICFG_VENDOR_ID_OFFSET);
149
150         return val;
151 }
152
153 static const u32 dmae_reg_go_c[] = {
154         DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
155         DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
156         DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
157         DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
158 };
159
160 /* copy command into DMAE command memory and set DMAE command go */
161 static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
162                             int idx)
163 {
164         u32 cmd_offset;
165         int i;
166
167         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
168         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
169                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
170
171                 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
172                    idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
173         }
174         REG_WR(bp, dmae_reg_go_c[idx], 1);
175 }
176
177 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
178                       u32 len32)
179 {
180         struct dmae_command *dmae = &bp->init_dmae;
181         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
182         int cnt = 200;
183
184         if (!bp->dmae_ready) {
185                 u32 *data = bnx2x_sp(bp, wb_data[0]);
186
187                 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
188                    "  using indirect\n", dst_addr, len32);
189                 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
190                 return;
191         }
192
193         mutex_lock(&bp->dmae_mutex);
194
195         memset(dmae, 0, sizeof(struct dmae_command));
196
197         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
198                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
199                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
200 #ifdef __BIG_ENDIAN
201                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
202 #else
203                         DMAE_CMD_ENDIANITY_DW_SWAP |
204 #endif
205                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
206                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
207         dmae->src_addr_lo = U64_LO(dma_addr);
208         dmae->src_addr_hi = U64_HI(dma_addr);
209         dmae->dst_addr_lo = dst_addr >> 2;
210         dmae->dst_addr_hi = 0;
211         dmae->len = len32;
212         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
213         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
214         dmae->comp_val = DMAE_COMP_VAL;
215
216         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
217            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
218                     "dst_addr [%x:%08x (%08x)]\n"
219            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
220            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
221            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
222            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
223         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
224            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
225            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
226
227         *wb_comp = 0;
228
229         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
230
231         udelay(5);
232
233         while (*wb_comp != DMAE_COMP_VAL) {
234                 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
235
236                 if (!cnt) {
237                         BNX2X_ERR("dmae timeout!\n");
238                         break;
239                 }
240                 cnt--;
241                 /* adjust delay for emulation/FPGA */
242                 if (CHIP_REV_IS_SLOW(bp))
243                         msleep(100);
244                 else
245                         udelay(5);
246         }
247
248         mutex_unlock(&bp->dmae_mutex);
249 }
250
251 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
252 {
253         struct dmae_command *dmae = &bp->init_dmae;
254         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
255         int cnt = 200;
256
257         if (!bp->dmae_ready) {
258                 u32 *data = bnx2x_sp(bp, wb_data[0]);
259                 int i;
260
261                 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x  len32 %d)"
262                    "  using indirect\n", src_addr, len32);
263                 for (i = 0; i < len32; i++)
264                         data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
265                 return;
266         }
267
268         mutex_lock(&bp->dmae_mutex);
269
270         memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
271         memset(dmae, 0, sizeof(struct dmae_command));
272
273         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
274                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
275                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
276 #ifdef __BIG_ENDIAN
277                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
278 #else
279                         DMAE_CMD_ENDIANITY_DW_SWAP |
280 #endif
281                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
282                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
283         dmae->src_addr_lo = src_addr >> 2;
284         dmae->src_addr_hi = 0;
285         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
286         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
287         dmae->len = len32;
288         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
289         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
290         dmae->comp_val = DMAE_COMP_VAL;
291
292         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
293            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
294                     "dst_addr [%x:%08x (%08x)]\n"
295            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
296            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
297            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
298            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
299
300         *wb_comp = 0;
301
302         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
303
304         udelay(5);
305
306         while (*wb_comp != DMAE_COMP_VAL) {
307
308                 if (!cnt) {
309                         BNX2X_ERR("dmae timeout!\n");
310                         break;
311                 }
312                 cnt--;
313                 /* adjust delay for emulation/FPGA */
314                 if (CHIP_REV_IS_SLOW(bp))
315                         msleep(100);
316                 else
317                         udelay(5);
318         }
319         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
320            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
321            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
322
323         mutex_unlock(&bp->dmae_mutex);
324 }
325
326 /* used only for slowpath so not inlined */
327 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
328 {
329         u32 wb_write[2];
330
331         wb_write[0] = val_hi;
332         wb_write[1] = val_lo;
333         REG_WR_DMAE(bp, reg, wb_write, 2);
334 }
335
336 #ifdef USE_WB_RD
337 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
338 {
339         u32 wb_data[2];
340
341         REG_RD_DMAE(bp, reg, wb_data, 2);
342
343         return HILO_U64(wb_data[0], wb_data[1]);
344 }
345 #endif
346
347 static int bnx2x_mc_assert(struct bnx2x *bp)
348 {
349         char last_idx;
350         int i, rc = 0;
351         u32 row0, row1, row2, row3;
352
353         /* XSTORM */
354         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
355                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
356         if (last_idx)
357                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
358
359         /* print the asserts */
360         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
361
362                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
363                               XSTORM_ASSERT_LIST_OFFSET(i));
364                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
365                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
366                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
367                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
368                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
369                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
370
371                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
372                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
373                                   " 0x%08x 0x%08x 0x%08x\n",
374                                   i, row3, row2, row1, row0);
375                         rc++;
376                 } else {
377                         break;
378                 }
379         }
380
381         /* TSTORM */
382         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
383                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
384         if (last_idx)
385                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
386
387         /* print the asserts */
388         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
389
390                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
391                               TSTORM_ASSERT_LIST_OFFSET(i));
392                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
393                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
394                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
395                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
396                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
397                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
398
399                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
400                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
401                                   " 0x%08x 0x%08x 0x%08x\n",
402                                   i, row3, row2, row1, row0);
403                         rc++;
404                 } else {
405                         break;
406                 }
407         }
408
409         /* CSTORM */
410         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
411                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
412         if (last_idx)
413                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
414
415         /* print the asserts */
416         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
417
418                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
419                               CSTORM_ASSERT_LIST_OFFSET(i));
420                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
421                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
422                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
423                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
424                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
425                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
426
427                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
428                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
429                                   " 0x%08x 0x%08x 0x%08x\n",
430                                   i, row3, row2, row1, row0);
431                         rc++;
432                 } else {
433                         break;
434                 }
435         }
436
437         /* USTORM */
438         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
439                            USTORM_ASSERT_LIST_INDEX_OFFSET);
440         if (last_idx)
441                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
442
443         /* print the asserts */
444         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
445
446                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
447                               USTORM_ASSERT_LIST_OFFSET(i));
448                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
449                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
450                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
451                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
452                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
453                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
454
455                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
456                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
457                                   " 0x%08x 0x%08x 0x%08x\n",
458                                   i, row3, row2, row1, row0);
459                         rc++;
460                 } else {
461                         break;
462                 }
463         }
464
465         return rc;
466 }
467
468 static void bnx2x_fw_dump(struct bnx2x *bp)
469 {
470         u32 mark, offset;
471         u32 data[9];
472         int word;
473
474         mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
475         mark = ((mark + 0x3) & ~0x3);
476         printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
477
478         for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
479                 for (word = 0; word < 8; word++)
480                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
481                                                   offset + 4*word));
482                 data[8] = 0x0;
483                 printk(KERN_CONT "%s", (char *)data);
484         }
485         for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
486                 for (word = 0; word < 8; word++)
487                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
488                                                   offset + 4*word));
489                 data[8] = 0x0;
490                 printk(KERN_CONT "%s", (char *)data);
491         }
492         printk("\n" KERN_ERR PFX "end of fw dump\n");
493 }
494
495 static void bnx2x_panic_dump(struct bnx2x *bp)
496 {
497         int i;
498         u16 j, start, end;
499
500         bp->stats_state = STATS_STATE_DISABLED;
501         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
502
503         BNX2X_ERR("begin crash dump -----------------\n");
504
505         for_each_queue(bp, i) {
506                 struct bnx2x_fastpath *fp = &bp->fp[i];
507                 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
508
509                 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
510                           "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)\n",
511                           i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
512                           fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
513                 BNX2X_ERR("          rx_bd_prod(%x)  rx_bd_cons(%x)"
514                           "  *rx_bd_cons_sb(%x)  rx_comp_prod(%x)"
515                           "  rx_comp_cons(%x)  *rx_cons_sb(%x)\n",
516                           fp->rx_bd_prod, fp->rx_bd_cons,
517                           le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
518                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
519                 BNX2X_ERR("          rx_sge_prod(%x)  last_max_sge(%x)"
520                           "  fp_c_idx(%x)  *sb_c_idx(%x)  fp_u_idx(%x)"
521                           "  *sb_u_idx(%x)  bd data(%x,%x)\n",
522                           fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx,
523                           fp->status_blk->c_status_block.status_block_index,
524                           fp->fp_u_idx,
525                           fp->status_blk->u_status_block.status_block_index,
526                           hw_prods->packets_prod, hw_prods->bds_prod);
527
528                 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
529                 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
530                 for (j = start; j < end; j++) {
531                         struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
532
533                         BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
534                                   sw_bd->skb, sw_bd->first_bd);
535                 }
536
537                 start = TX_BD(fp->tx_bd_cons - 10);
538                 end = TX_BD(fp->tx_bd_cons + 254);
539                 for (j = start; j < end; j++) {
540                         u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
541
542                         BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
543                                   j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
544                 }
545
546                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
547                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
548                 for (j = start; j < end; j++) {
549                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
550                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
551
552                         BNX2X_ERR("rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
553                                   j, rx_bd[1], rx_bd[0], sw_bd->skb);
554                 }
555
556                 start = RX_SGE(fp->rx_sge_prod);
557                 end = RX_SGE(fp->last_max_sge);
558                 for (j = start; j < end; j++) {
559                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
560                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
561
562                         BNX2X_ERR("rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
563                                   j, rx_sge[1], rx_sge[0], sw_page->page);
564                 }
565
566                 start = RCQ_BD(fp->rx_comp_cons - 10);
567                 end = RCQ_BD(fp->rx_comp_cons + 503);
568                 for (j = start; j < end; j++) {
569                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
570
571                         BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
572                                   j, cqe[0], cqe[1], cqe[2], cqe[3]);
573                 }
574         }
575
576         BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
577                   "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
578                   "  spq_prod_idx(%u)\n",
579                   bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
580                   bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
581
582         bnx2x_fw_dump(bp);
583         bnx2x_mc_assert(bp);
584         BNX2X_ERR("end crash dump -----------------\n");
585 }
586
587 static void bnx2x_int_enable(struct bnx2x *bp)
588 {
589         int port = BP_PORT(bp);
590         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
591         u32 val = REG_RD(bp, addr);
592         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
593
594         if (msix) {
595                 val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
596                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
597                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
598         } else {
599                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
600                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
601                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
602                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
603
604                 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",
605                    val, port, addr, msix);
606
607                 REG_WR(bp, addr, val);
608
609                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
610         }
611
612         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",
613            val, port, addr, msix);
614
615         REG_WR(bp, addr, val);
616
617         if (CHIP_IS_E1H(bp)) {
618                 /* init leading/trailing edge */
619                 if (IS_E1HMF(bp)) {
620                         val = (0xfe0f | (1 << (BP_E1HVN(bp) + 4)));
621                         if (bp->port.pmf)
622                                 /* enable nig attention */
623                                 val |= 0x0100;
624                 } else
625                         val = 0xffff;
626
627                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
628                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
629         }
630 }
631
632 static void bnx2x_int_disable(struct bnx2x *bp)
633 {
634         int port = BP_PORT(bp);
635         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
636         u32 val = REG_RD(bp, addr);
637
638         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
639                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
640                  HC_CONFIG_0_REG_INT_LINE_EN_0 |
641                  HC_CONFIG_0_REG_ATTN_BIT_EN_0);
642
643         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
644            val, port, addr);
645
646         REG_WR(bp, addr, val);
647         if (REG_RD(bp, addr) != val)
648                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
649 }
650
651 static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
652 {
653         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
654         int i;
655
656         /* disable interrupt handling */
657         atomic_inc(&bp->intr_sem);
658         if (disable_hw)
659                 /* prevent the HW from sending interrupts */
660                 bnx2x_int_disable(bp);
661
662         /* make sure all ISRs are done */
663         if (msix) {
664                 for_each_queue(bp, i)
665                         synchronize_irq(bp->msix_table[i].vector);
666
667                 /* one more for the Slow Path IRQ */
668                 synchronize_irq(bp->msix_table[i].vector);
669         } else
670                 synchronize_irq(bp->pdev->irq);
671
672         /* make sure sp_task is not running */
673         cancel_delayed_work(&bp->sp_task);
674         flush_workqueue(bnx2x_wq);
675 }
676
677 /* fast path */
678
679 /*
680  * General service functions
681  */
682
683 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
684                                 u8 storm, u16 index, u8 op, u8 update)
685 {
686         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
687                        COMMAND_REG_INT_ACK);
688         struct igu_ack_register igu_ack;
689
690         igu_ack.status_block_index = index;
691         igu_ack.sb_id_and_flags =
692                         ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
693                          (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
694                          (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
695                          (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
696
697         DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
698            (*(u32 *)&igu_ack), hc_addr);
699         REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
700 }
701
702 static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
703 {
704         struct host_status_block *fpsb = fp->status_blk;
705         u16 rc = 0;
706
707         barrier(); /* status block is written to by the chip */
708         if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
709                 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
710                 rc |= 1;
711         }
712         if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
713                 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
714                 rc |= 2;
715         }
716         return rc;
717 }
718
719 static u16 bnx2x_ack_int(struct bnx2x *bp)
720 {
721         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
722                        COMMAND_REG_SIMD_MASK);
723         u32 result = REG_RD(bp, hc_addr);
724
725         DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
726            result, hc_addr);
727
728         return result;
729 }
730
731
732 /*
733  * fast path service functions
734  */
735
736 static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
737 {
738         u16 tx_cons_sb;
739
740         /* Tell compiler that status block fields can change */
741         barrier();
742         tx_cons_sb = le16_to_cpu(*fp->tx_cons_sb);
743         return (fp->tx_pkt_cons != tx_cons_sb);
744 }
745
746 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
747 {
748         /* Tell compiler that consumer and producer can change */
749         barrier();
750         return (fp->tx_pkt_prod != fp->tx_pkt_cons);
751
752 }
753
754 /* free skb in the packet ring at pos idx
755  * return idx of last bd freed
756  */
757 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
758                              u16 idx)
759 {
760         struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
761         struct eth_tx_bd *tx_bd;
762         struct sk_buff *skb = tx_buf->skb;
763         u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
764         int nbd;
765
766         DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
767            idx, tx_buf, skb);
768
769         /* unmap first bd */
770         DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
771         tx_bd = &fp->tx_desc_ring[bd_idx];
772         pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
773                          BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
774
775         nbd = le16_to_cpu(tx_bd->nbd) - 1;
776         new_cons = nbd + tx_buf->first_bd;
777 #ifdef BNX2X_STOP_ON_ERROR
778         if (nbd > (MAX_SKB_FRAGS + 2)) {
779                 BNX2X_ERR("BAD nbd!\n");
780                 bnx2x_panic();
781         }
782 #endif
783
784         /* Skip a parse bd and the TSO split header bd
785            since they have no mapping */
786         if (nbd)
787                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
788
789         if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
790                                            ETH_TX_BD_FLAGS_TCP_CSUM |
791                                            ETH_TX_BD_FLAGS_SW_LSO)) {
792                 if (--nbd)
793                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
794                 tx_bd = &fp->tx_desc_ring[bd_idx];
795                 /* is this a TSO split header bd? */
796                 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
797                         if (--nbd)
798                                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
799                 }
800         }
801
802         /* now free frags */
803         while (nbd > 0) {
804
805                 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
806                 tx_bd = &fp->tx_desc_ring[bd_idx];
807                 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
808                                BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
809                 if (--nbd)
810                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
811         }
812
813         /* release skb */
814         WARN_ON(!skb);
815         dev_kfree_skb(skb);
816         tx_buf->first_bd = 0;
817         tx_buf->skb = NULL;
818
819         return new_cons;
820 }
821
822 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
823 {
824         s16 used;
825         u16 prod;
826         u16 cons;
827
828         barrier(); /* Tell compiler that prod and cons can change */
829         prod = fp->tx_bd_prod;
830         cons = fp->tx_bd_cons;
831
832         /* NUM_TX_RINGS = number of "next-page" entries
833            It will be used as a threshold */
834         used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
835
836 #ifdef BNX2X_STOP_ON_ERROR
837         WARN_ON(used < 0);
838         WARN_ON(used > fp->bp->tx_ring_size);
839         WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
840 #endif
841
842         return (s16)(fp->bp->tx_ring_size) - used;
843 }
844
845 static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
846 {
847         struct bnx2x *bp = fp->bp;
848         u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
849         int done = 0;
850
851 #ifdef BNX2X_STOP_ON_ERROR
852         if (unlikely(bp->panic))
853                 return;
854 #endif
855
856         hw_cons = le16_to_cpu(*fp->tx_cons_sb);
857         sw_cons = fp->tx_pkt_cons;
858
859         while (sw_cons != hw_cons) {
860                 u16 pkt_cons;
861
862                 pkt_cons = TX_BD(sw_cons);
863
864                 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
865
866                 DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %u\n",
867                    hw_cons, sw_cons, pkt_cons);
868
869 /*              if (NEXT_TX_IDX(sw_cons) != hw_cons) {
870                         rmb();
871                         prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
872                 }
873 */
874                 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
875                 sw_cons++;
876                 done++;
877
878                 if (done == work)
879                         break;
880         }
881
882         fp->tx_pkt_cons = sw_cons;
883         fp->tx_bd_cons = bd_cons;
884
885         /* Need to make the tx_cons update visible to start_xmit()
886          * before checking for netif_queue_stopped().  Without the
887          * memory barrier, there is a small possibility that start_xmit()
888          * will miss it and cause the queue to be stopped forever.
889          */
890         smp_mb();
891
892         /* TBD need a thresh? */
893         if (unlikely(netif_queue_stopped(bp->dev))) {
894
895                 netif_tx_lock(bp->dev);
896
897                 if (netif_queue_stopped(bp->dev) &&
898                     (bp->state == BNX2X_STATE_OPEN) &&
899                     (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
900                         netif_wake_queue(bp->dev);
901
902                 netif_tx_unlock(bp->dev);
903         }
904 }
905
906
907 static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
908                            union eth_rx_cqe *rr_cqe)
909 {
910         struct bnx2x *bp = fp->bp;
911         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
912         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
913
914         DP(BNX2X_MSG_SP,
915            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
916            FP_IDX(fp), cid, command, bp->state,
917            rr_cqe->ramrod_cqe.ramrod_type);
918
919         bp->spq_left++;
920
921         if (FP_IDX(fp)) {
922                 switch (command | fp->state) {
923                 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
924                                                 BNX2X_FP_STATE_OPENING):
925                         DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
926                            cid);
927                         fp->state = BNX2X_FP_STATE_OPEN;
928                         break;
929
930                 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
931                         DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
932                            cid);
933                         fp->state = BNX2X_FP_STATE_HALTED;
934                         break;
935
936                 default:
937                         BNX2X_ERR("unexpected MC reply (%d)  "
938                                   "fp->state is %x\n", command, fp->state);
939                         break;
940                 }
941                 mb(); /* force bnx2x_wait_ramrod() to see the change */
942                 return;
943         }
944
945         switch (command | bp->state) {
946         case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
947                 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
948                 bp->state = BNX2X_STATE_OPEN;
949                 break;
950
951         case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
952                 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
953                 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
954                 fp->state = BNX2X_FP_STATE_HALTED;
955                 break;
956
957         case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
958                 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
959                 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
960                 break;
961
962
963         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
964         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
965                 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
966                 bp->set_mac_pending = 0;
967                 break;
968
969         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
970                 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
971                 break;
972
973         default:
974                 BNX2X_ERR("unexpected MC reply (%d)  bp->state is %x\n",
975                           command, bp->state);
976                 break;
977         }
978         mb(); /* force bnx2x_wait_ramrod() to see the change */
979 }
980
981 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
982                                      struct bnx2x_fastpath *fp, u16 index)
983 {
984         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
985         struct page *page = sw_buf->page;
986         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
987
988         /* Skip "next page" elements */
989         if (!page)
990                 return;
991
992         pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
993                        SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
994         __free_pages(page, PAGES_PER_SGE_SHIFT);
995
996         sw_buf->page = NULL;
997         sge->addr_hi = 0;
998         sge->addr_lo = 0;
999 }
1000
1001 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1002                                            struct bnx2x_fastpath *fp, int last)
1003 {
1004         int i;
1005
1006         for (i = 0; i < last; i++)
1007                 bnx2x_free_rx_sge(bp, fp, i);
1008 }
1009
1010 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
1011                                      struct bnx2x_fastpath *fp, u16 index)
1012 {
1013         struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
1014         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1015         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1016         dma_addr_t mapping;
1017
1018         if (unlikely(page == NULL))
1019                 return -ENOMEM;
1020
1021         mapping = pci_map_page(bp->pdev, page, 0, SGE_PAGE_SIZE*PAGES_PER_SGE,
1022                                PCI_DMA_FROMDEVICE);
1023         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1024                 __free_pages(page, PAGES_PER_SGE_SHIFT);
1025                 return -ENOMEM;
1026         }
1027
1028         sw_buf->page = page;
1029         pci_unmap_addr_set(sw_buf, mapping, mapping);
1030
1031         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1032         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1033
1034         return 0;
1035 }
1036
1037 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1038                                      struct bnx2x_fastpath *fp, u16 index)
1039 {
1040         struct sk_buff *skb;
1041         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1042         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1043         dma_addr_t mapping;
1044
1045         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1046         if (unlikely(skb == NULL))
1047                 return -ENOMEM;
1048
1049         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_size,
1050                                  PCI_DMA_FROMDEVICE);
1051         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1052                 dev_kfree_skb(skb);
1053                 return -ENOMEM;
1054         }
1055
1056         rx_buf->skb = skb;
1057         pci_unmap_addr_set(rx_buf, mapping, mapping);
1058
1059         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1060         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1061
1062         return 0;
1063 }
1064
1065 /* note that we are not allocating a new skb,
1066  * we are just moving one from cons to prod
1067  * we are not creating a new mapping,
1068  * so there is no need to check for dma_mapping_error().
1069  */
1070 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1071                                struct sk_buff *skb, u16 cons, u16 prod)
1072 {
1073         struct bnx2x *bp = fp->bp;
1074         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1075         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1076         struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1077         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1078
1079         pci_dma_sync_single_for_device(bp->pdev,
1080                                        pci_unmap_addr(cons_rx_buf, mapping),
1081                                        bp->rx_offset + RX_COPY_THRESH,
1082                                        PCI_DMA_FROMDEVICE);
1083
1084         prod_rx_buf->skb = cons_rx_buf->skb;
1085         pci_unmap_addr_set(prod_rx_buf, mapping,
1086                            pci_unmap_addr(cons_rx_buf, mapping));
1087         *prod_bd = *cons_bd;
1088 }
1089
1090 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1091                                              u16 idx)
1092 {
1093         u16 last_max = fp->last_max_sge;
1094
1095         if (SUB_S16(idx, last_max) > 0)
1096                 fp->last_max_sge = idx;
1097 }
1098
1099 static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1100 {
1101         int i, j;
1102
1103         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1104                 int idx = RX_SGE_CNT * i - 1;
1105
1106                 for (j = 0; j < 2; j++) {
1107                         SGE_MASK_CLEAR_BIT(fp, idx);
1108                         idx--;
1109                 }
1110         }
1111 }
1112
1113 static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1114                                   struct eth_fast_path_rx_cqe *fp_cqe)
1115 {
1116         struct bnx2x *bp = fp->bp;
1117         u16 sge_len = SGE_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
1118                                      le16_to_cpu(fp_cqe->len_on_bd)) >>
1119                       SGE_PAGE_SHIFT;
1120         u16 last_max, last_elem, first_elem;
1121         u16 delta = 0;
1122         u16 i;
1123
1124         if (!sge_len)
1125                 return;
1126
1127         /* First mark all used pages */
1128         for (i = 0; i < sge_len; i++)
1129                 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1130
1131         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1132            sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1133
1134         /* Here we assume that the last SGE index is the biggest */
1135         prefetch((void *)(fp->sge_mask));
1136         bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1137
1138         last_max = RX_SGE(fp->last_max_sge);
1139         last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1140         first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1141
1142         /* If ring is not full */
1143         if (last_elem + 1 != first_elem)
1144                 last_elem++;
1145
1146         /* Now update the prod */
1147         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1148                 if (likely(fp->sge_mask[i]))
1149                         break;
1150
1151                 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1152                 delta += RX_SGE_MASK_ELEM_SZ;
1153         }
1154
1155         if (delta > 0) {
1156                 fp->rx_sge_prod += delta;
1157                 /* clear page-end entries */
1158                 bnx2x_clear_sge_mask_next_elems(fp);
1159         }
1160
1161         DP(NETIF_MSG_RX_STATUS,
1162            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
1163            fp->last_max_sge, fp->rx_sge_prod);
1164 }
1165
1166 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1167 {
1168         /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1169         memset(fp->sge_mask, 0xff,
1170                (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1171
1172         /* Clear the two last indices in the page to 1:
1173            these are the indices that correspond to the "next" element,
1174            hence will never be indicated and should be removed from
1175            the calculations. */
1176         bnx2x_clear_sge_mask_next_elems(fp);
1177 }
1178
1179 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1180                             struct sk_buff *skb, u16 cons, u16 prod)
1181 {
1182         struct bnx2x *bp = fp->bp;
1183         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1184         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1185         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1186         dma_addr_t mapping;
1187
1188         /* move empty skb from pool to prod and map it */
1189         prod_rx_buf->skb = fp->tpa_pool[queue].skb;
1190         mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
1191                                  bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1192         pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
1193
1194         /* move partial skb from cons to pool (don't unmap yet) */
1195         fp->tpa_pool[queue] = *cons_rx_buf;
1196
1197         /* mark bin state as start - print error if current state != stop */
1198         if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1199                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1200
1201         fp->tpa_state[queue] = BNX2X_TPA_START;
1202
1203         /* point prod_bd to new skb */
1204         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1205         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1206
1207 #ifdef BNX2X_STOP_ON_ERROR
1208         fp->tpa_queue_used |= (1 << queue);
1209 #ifdef __powerpc64__
1210         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1211 #else
1212         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1213 #endif
1214            fp->tpa_queue_used);
1215 #endif
1216 }
1217
1218 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1219                                struct sk_buff *skb,
1220                                struct eth_fast_path_rx_cqe *fp_cqe,
1221                                u16 cqe_idx)
1222 {
1223         struct sw_rx_page *rx_pg, old_rx_pg;
1224         u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1225         u32 i, frag_len, frag_size, pages;
1226         int err;
1227         int j;
1228
1229         frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
1230         pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
1231
1232         /* This is needed in order to enable forwarding support */
1233         if (frag_size)
1234                 skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
1235                                                max(frag_size, (u32)len_on_bd));
1236
1237 #ifdef BNX2X_STOP_ON_ERROR
1238         if (pages >
1239             min((u32)8, (u32)MAX_SKB_FRAGS) * SGE_PAGE_SIZE * PAGES_PER_SGE) {
1240                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1241                           pages, cqe_idx);
1242                 BNX2X_ERR("fp_cqe->pkt_len = %d  fp_cqe->len_on_bd = %d\n",
1243                           fp_cqe->pkt_len, len_on_bd);
1244                 bnx2x_panic();
1245                 return -EINVAL;
1246         }
1247 #endif
1248
1249         /* Run through the SGL and compose the fragmented skb */
1250         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1251                 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1252
1253                 /* FW gives the indices of the SGE as if the ring is an array
1254                    (meaning that "next" element will consume 2 indices) */
1255                 frag_len = min(frag_size, (u32)(SGE_PAGE_SIZE*PAGES_PER_SGE));
1256                 rx_pg = &fp->rx_page_ring[sge_idx];
1257                 old_rx_pg = *rx_pg;
1258
1259                 /* If we fail to allocate a substitute page, we simply stop
1260                    where we are and drop the whole packet */
1261                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1262                 if (unlikely(err)) {
1263                         bp->eth_stats.rx_skb_alloc_failed++;
1264                         return err;
1265                 }
1266
1267                 /* Unmap the page as we r going to pass it to the stack */
1268                 pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
1269                               SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1270
1271                 /* Add one frag and update the appropriate fields in the skb */
1272                 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1273
1274                 skb->data_len += frag_len;
1275                 skb->truesize += frag_len;
1276                 skb->len += frag_len;
1277
1278                 frag_size -= frag_len;
1279         }
1280
1281         return 0;
1282 }
1283
1284 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1285                            u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1286                            u16 cqe_idx)
1287 {
1288         struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1289         struct sk_buff *skb = rx_buf->skb;
1290         /* alloc new skb */
1291         struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1292
1293         /* Unmap skb in the pool anyway, as we are going to change
1294            pool entry status to BNX2X_TPA_STOP even if new skb allocation
1295            fails. */
1296         pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1297                          bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1298
1299         if (likely(new_skb)) {
1300                 /* fix ip xsum and give it to the stack */
1301                 /* (no need to map the new skb) */
1302 #ifdef BCM_VLAN
1303                 int is_vlan_cqe =
1304                         (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1305                          PARSING_FLAGS_VLAN);
1306                 int is_not_hwaccel_vlan_cqe =
1307                         (is_vlan_cqe && (!(bp->flags & HW_VLAN_RX_FLAG)));
1308 #endif
1309
1310                 prefetch(skb);
1311                 prefetch(((char *)(skb)) + 128);
1312
1313 #ifdef BNX2X_STOP_ON_ERROR
1314                 if (pad + len > bp->rx_buf_size) {
1315                         BNX2X_ERR("skb_put is about to fail...  "
1316                                   "pad %d  len %d  rx_buf_size %d\n",
1317                                   pad, len, bp->rx_buf_size);
1318                         bnx2x_panic();
1319                         return;
1320                 }
1321 #endif
1322
1323                 skb_reserve(skb, pad);
1324                 skb_put(skb, len);
1325
1326                 skb->protocol = eth_type_trans(skb, bp->dev);
1327                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1328
1329                 {
1330                         struct iphdr *iph;
1331
1332                         iph = (struct iphdr *)skb->data;
1333 #ifdef BCM_VLAN
1334                         /* If there is no Rx VLAN offloading -
1335                            take VLAN tag into an account */
1336                         if (unlikely(is_not_hwaccel_vlan_cqe))
1337                                 iph = (struct iphdr *)((u8 *)iph + VLAN_HLEN);
1338 #endif
1339                         iph->check = 0;
1340                         iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1341                 }
1342
1343                 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1344                                          &cqe->fast_path_cqe, cqe_idx)) {
1345 #ifdef BCM_VLAN
1346                         if ((bp->vlgrp != NULL) && is_vlan_cqe &&
1347                             (!is_not_hwaccel_vlan_cqe))
1348                                 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1349                                                 le16_to_cpu(cqe->fast_path_cqe.
1350                                                             vlan_tag));
1351                         else
1352 #endif
1353                                 netif_receive_skb(skb);
1354                 } else {
1355                         DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1356                            " - dropping packet!\n");
1357                         dev_kfree_skb(skb);
1358                 }
1359
1360
1361                 /* put new skb in bin */
1362                 fp->tpa_pool[queue].skb = new_skb;
1363
1364         } else {
1365                 /* else drop the packet and keep the buffer in the bin */
1366                 DP(NETIF_MSG_RX_STATUS,
1367                    "Failed to allocate new skb - dropping packet!\n");
1368                 bp->eth_stats.rx_skb_alloc_failed++;
1369         }
1370
1371         fp->tpa_state[queue] = BNX2X_TPA_STOP;
1372 }
1373
1374 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1375                                         struct bnx2x_fastpath *fp,
1376                                         u16 bd_prod, u16 rx_comp_prod,
1377                                         u16 rx_sge_prod)
1378 {
1379         struct tstorm_eth_rx_producers rx_prods = {0};
1380         int i;
1381
1382         /* Update producers */
1383         rx_prods.bd_prod = bd_prod;
1384         rx_prods.cqe_prod = rx_comp_prod;
1385         rx_prods.sge_prod = rx_sge_prod;
1386
1387         /*
1388          * Make sure that the BD and SGE data is updated before updating the
1389          * producers since FW might read the BD/SGE right after the producer
1390          * is updated.
1391          * This is only applicable for weak-ordered memory model archs such
1392          * as IA-64. The following barrier is also mandatory since FW will
1393          * assumes BDs must have buffers.
1394          */
1395         wmb();
1396
1397         for (i = 0; i < sizeof(struct tstorm_eth_rx_producers)/4; i++)
1398                 REG_WR(bp, BAR_TSTRORM_INTMEM +
1399                        TSTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
1400                        ((u32 *)&rx_prods)[i]);
1401
1402         mmiowb(); /* keep prod updates ordered */
1403
1404         DP(NETIF_MSG_RX_STATUS,
1405            "Wrote: bd_prod %u  cqe_prod %u  sge_prod %u\n",
1406            bd_prod, rx_comp_prod, rx_sge_prod);
1407 }
1408
1409 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1410 {
1411         struct bnx2x *bp = fp->bp;
1412         u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1413         u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1414         int rx_pkt = 0;
1415
1416 #ifdef BNX2X_STOP_ON_ERROR
1417         if (unlikely(bp->panic))
1418                 return 0;
1419 #endif
1420
1421         /* CQ "next element" is of the size of the regular element,
1422            that's why it's ok here */
1423         hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1424         if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1425                 hw_comp_cons++;
1426
1427         bd_cons = fp->rx_bd_cons;
1428         bd_prod = fp->rx_bd_prod;
1429         bd_prod_fw = bd_prod;
1430         sw_comp_cons = fp->rx_comp_cons;
1431         sw_comp_prod = fp->rx_comp_prod;
1432
1433         /* Memory barrier necessary as speculative reads of the rx
1434          * buffer can be ahead of the index in the status block
1435          */
1436         rmb();
1437
1438         DP(NETIF_MSG_RX_STATUS,
1439            "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
1440            FP_IDX(fp), hw_comp_cons, sw_comp_cons);
1441
1442         while (sw_comp_cons != hw_comp_cons) {
1443                 struct sw_rx_bd *rx_buf = NULL;
1444                 struct sk_buff *skb;
1445                 union eth_rx_cqe *cqe;
1446                 u8 cqe_fp_flags;
1447                 u16 len, pad;
1448
1449                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1450                 bd_prod = RX_BD(bd_prod);
1451                 bd_cons = RX_BD(bd_cons);
1452
1453                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1454                 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1455
1456                 DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
1457                    "  queue %x  vlan %x  len %u\n", CQE_TYPE(cqe_fp_flags),
1458                    cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1459                    le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
1460                    le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1461                    le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1462
1463                 /* is this a slowpath msg? */
1464                 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
1465                         bnx2x_sp_event(fp, cqe);
1466                         goto next_cqe;
1467
1468                 /* this is an rx packet */
1469                 } else {
1470                         rx_buf = &fp->rx_buf_ring[bd_cons];
1471                         skb = rx_buf->skb;
1472                         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1473                         pad = cqe->fast_path_cqe.placement_offset;
1474
1475                         /* If CQE is marked both TPA_START and TPA_END
1476                            it is a non-TPA CQE */
1477                         if ((!fp->disable_tpa) &&
1478                             (TPA_TYPE(cqe_fp_flags) !=
1479                                         (TPA_TYPE_START | TPA_TYPE_END))) {
1480                                 u16 queue = cqe->fast_path_cqe.queue_index;
1481
1482                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1483                                         DP(NETIF_MSG_RX_STATUS,
1484                                            "calling tpa_start on queue %d\n",
1485                                            queue);
1486
1487                                         bnx2x_tpa_start(fp, queue, skb,
1488                                                         bd_cons, bd_prod);
1489                                         goto next_rx;
1490                                 }
1491
1492                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1493                                         DP(NETIF_MSG_RX_STATUS,
1494                                            "calling tpa_stop on queue %d\n",
1495                                            queue);
1496
1497                                         if (!BNX2X_RX_SUM_FIX(cqe))
1498                                                 BNX2X_ERR("STOP on none TCP "
1499                                                           "data\n");
1500
1501                                         /* This is a size of the linear data
1502                                            on this skb */
1503                                         len = le16_to_cpu(cqe->fast_path_cqe.
1504                                                                 len_on_bd);
1505                                         bnx2x_tpa_stop(bp, fp, queue, pad,
1506                                                     len, cqe, comp_ring_cons);
1507 #ifdef BNX2X_STOP_ON_ERROR
1508                                         if (bp->panic)
1509                                                 return -EINVAL;
1510 #endif
1511
1512                                         bnx2x_update_sge_prod(fp,
1513                                                         &cqe->fast_path_cqe);
1514                                         goto next_cqe;
1515                                 }
1516                         }
1517
1518                         pci_dma_sync_single_for_device(bp->pdev,
1519                                         pci_unmap_addr(rx_buf, mapping),
1520                                                        pad + RX_COPY_THRESH,
1521                                                        PCI_DMA_FROMDEVICE);
1522                         prefetch(skb);
1523                         prefetch(((char *)(skb)) + 128);
1524
1525                         /* is this an error packet? */
1526                         if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1527                                 DP(NETIF_MSG_RX_ERR,
1528                                    "ERROR  flags %x  rx packet %u\n",
1529                                    cqe_fp_flags, sw_comp_cons);
1530                                 bp->eth_stats.rx_err_discard_pkt++;
1531                                 goto reuse_rx;
1532                         }
1533
1534                         /* Since we don't have a jumbo ring
1535                          * copy small packets if mtu > 1500
1536                          */
1537                         if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1538                             (len <= RX_COPY_THRESH)) {
1539                                 struct sk_buff *new_skb;
1540
1541                                 new_skb = netdev_alloc_skb(bp->dev,
1542                                                            len + pad);
1543                                 if (new_skb == NULL) {
1544                                         DP(NETIF_MSG_RX_ERR,
1545                                            "ERROR  packet dropped "
1546                                            "because of alloc failure\n");
1547                                         bp->eth_stats.rx_skb_alloc_failed++;
1548                                         goto reuse_rx;
1549                                 }
1550
1551                                 /* aligned copy */
1552                                 skb_copy_from_linear_data_offset(skb, pad,
1553                                                     new_skb->data + pad, len);
1554                                 skb_reserve(new_skb, pad);
1555                                 skb_put(new_skb, len);
1556
1557                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1558
1559                                 skb = new_skb;
1560
1561                         } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
1562                                 pci_unmap_single(bp->pdev,
1563                                         pci_unmap_addr(rx_buf, mapping),
1564                                                  bp->rx_buf_size,
1565                                                  PCI_DMA_FROMDEVICE);
1566                                 skb_reserve(skb, pad);
1567                                 skb_put(skb, len);
1568
1569                         } else {
1570                                 DP(NETIF_MSG_RX_ERR,
1571                                    "ERROR  packet dropped because "
1572                                    "of alloc failure\n");
1573                                 bp->eth_stats.rx_skb_alloc_failed++;
1574 reuse_rx:
1575                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1576                                 goto next_rx;
1577                         }
1578
1579                         skb->protocol = eth_type_trans(skb, bp->dev);
1580
1581                         skb->ip_summed = CHECKSUM_NONE;
1582                         if (bp->rx_csum) {
1583                                 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1584                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1585                                 else
1586                                         bp->eth_stats.hw_csum_err++;
1587                         }
1588                 }
1589
1590 #ifdef BCM_VLAN
1591                 if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) &&
1592                     (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1593                      PARSING_FLAGS_VLAN))
1594                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1595                                 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1596                 else
1597 #endif
1598                         netif_receive_skb(skb);
1599
1600
1601 next_rx:
1602                 rx_buf->skb = NULL;
1603
1604                 bd_cons = NEXT_RX_IDX(bd_cons);
1605                 bd_prod = NEXT_RX_IDX(bd_prod);
1606                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1607                 rx_pkt++;
1608 next_cqe:
1609                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1610                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1611
1612                 if (rx_pkt == budget)
1613                         break;
1614         } /* while */
1615
1616         fp->rx_bd_cons = bd_cons;
1617         fp->rx_bd_prod = bd_prod_fw;
1618         fp->rx_comp_cons = sw_comp_cons;
1619         fp->rx_comp_prod = sw_comp_prod;
1620
1621         /* Update producers */
1622         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1623                              fp->rx_sge_prod);
1624
1625         fp->rx_pkt += rx_pkt;
1626         fp->rx_calls++;
1627
1628         return rx_pkt;
1629 }
1630
1631 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1632 {
1633         struct bnx2x_fastpath *fp = fp_cookie;
1634         struct bnx2x *bp = fp->bp;
1635         int index = FP_IDX(fp);
1636
1637         /* Return here if interrupt is disabled */
1638         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1639                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1640                 return IRQ_HANDLED;
1641         }
1642
1643         DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1644            index, FP_SB_ID(fp));
1645         bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
1646
1647 #ifdef BNX2X_STOP_ON_ERROR
1648         if (unlikely(bp->panic))
1649                 return IRQ_HANDLED;
1650 #endif
1651
1652         prefetch(fp->rx_cons_sb);
1653         prefetch(fp->tx_cons_sb);
1654         prefetch(&fp->status_blk->c_status_block.status_block_index);
1655         prefetch(&fp->status_blk->u_status_block.status_block_index);
1656
1657         netif_rx_schedule(&bnx2x_fp(bp, index, napi));
1658
1659         return IRQ_HANDLED;
1660 }
1661
1662 static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1663 {
1664         struct net_device *dev = dev_instance;
1665         struct bnx2x *bp = netdev_priv(dev);
1666         u16 status = bnx2x_ack_int(bp);
1667         u16 mask;
1668
1669         /* Return here if interrupt is shared and it's not for us */
1670         if (unlikely(status == 0)) {
1671                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1672                 return IRQ_NONE;
1673         }
1674         DP(NETIF_MSG_INTR, "got an interrupt  status %u\n", status);
1675
1676         /* Return here if interrupt is disabled */
1677         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1678                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1679                 return IRQ_HANDLED;
1680         }
1681
1682 #ifdef BNX2X_STOP_ON_ERROR
1683         if (unlikely(bp->panic))
1684                 return IRQ_HANDLED;
1685 #endif
1686
1687         mask = 0x2 << bp->fp[0].sb_id;
1688         if (status & mask) {
1689                 struct bnx2x_fastpath *fp = &bp->fp[0];
1690
1691                 prefetch(fp->rx_cons_sb);
1692                 prefetch(fp->tx_cons_sb);
1693                 prefetch(&fp->status_blk->c_status_block.status_block_index);
1694                 prefetch(&fp->status_blk->u_status_block.status_block_index);
1695
1696                 netif_rx_schedule(&bnx2x_fp(bp, 0, napi));
1697
1698                 status &= ~mask;
1699         }
1700
1701
1702         if (unlikely(status & 0x1)) {
1703                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1704
1705                 status &= ~0x1;
1706                 if (!status)
1707                         return IRQ_HANDLED;
1708         }
1709
1710         if (status)
1711                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1712                    status);
1713
1714         return IRQ_HANDLED;
1715 }
1716
1717 /* end of fast path */
1718
1719 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1720
1721 /* Link */
1722
1723 /*
1724  * General service functions
1725  */
1726
1727 static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1728 {
1729         u32 lock_status;
1730         u32 resource_bit = (1 << resource);
1731         int func = BP_FUNC(bp);
1732         u32 hw_lock_control_reg;
1733         int cnt;
1734
1735         /* Validating that the resource is within range */
1736         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1737                 DP(NETIF_MSG_HW,
1738                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1739                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1740                 return -EINVAL;
1741         }
1742
1743         if (func <= 5) {
1744                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1745         } else {
1746                 hw_lock_control_reg =
1747                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1748         }
1749
1750         /* Validating that the resource is not already taken */
1751         lock_status = REG_RD(bp, hw_lock_control_reg);
1752         if (lock_status & resource_bit) {
1753                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1754                    lock_status, resource_bit);
1755                 return -EEXIST;
1756         }
1757
1758         /* Try for 5 second every 5ms */
1759         for (cnt = 0; cnt < 1000; cnt++) {
1760                 /* Try to acquire the lock */
1761                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1762                 lock_status = REG_RD(bp, hw_lock_control_reg);
1763                 if (lock_status & resource_bit)
1764                         return 0;
1765
1766                 msleep(5);
1767         }
1768         DP(NETIF_MSG_HW, "Timeout\n");
1769         return -EAGAIN;
1770 }
1771
1772 static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1773 {
1774         u32 lock_status;
1775         u32 resource_bit = (1 << resource);
1776         int func = BP_FUNC(bp);
1777         u32 hw_lock_control_reg;
1778
1779         /* Validating that the resource is within range */
1780         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1781                 DP(NETIF_MSG_HW,
1782                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1783                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1784                 return -EINVAL;
1785         }
1786
1787         if (func <= 5) {
1788                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1789         } else {
1790                 hw_lock_control_reg =
1791                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1792         }
1793
1794         /* Validating that the resource is currently taken */
1795         lock_status = REG_RD(bp, hw_lock_control_reg);
1796         if (!(lock_status & resource_bit)) {
1797                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1798                    lock_status, resource_bit);
1799                 return -EFAULT;
1800         }
1801
1802         REG_WR(bp, hw_lock_control_reg, resource_bit);
1803         return 0;
1804 }
1805
1806 /* HW Lock for shared dual port PHYs */
1807 static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1808 {
1809         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1810
1811         mutex_lock(&bp->port.phy_mutex);
1812
1813         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1814             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1815                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1816 }
1817
1818 static void bnx2x_release_phy_lock(struct bnx2x *bp)
1819 {
1820         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1821
1822         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1823             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1824                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1825
1826         mutex_unlock(&bp->port.phy_mutex);
1827 }
1828
1829 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1830 {
1831         /* The GPIO should be swapped if swap register is set and active */
1832         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1833                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1834         int gpio_shift = gpio_num +
1835                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1836         u32 gpio_mask = (1 << gpio_shift);
1837         u32 gpio_reg;
1838
1839         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1840                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1841                 return -EINVAL;
1842         }
1843
1844         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1845         /* read GPIO and mask except the float bits */
1846         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1847
1848         switch (mode) {
1849         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1850                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1851                    gpio_num, gpio_shift);
1852                 /* clear FLOAT and set CLR */
1853                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1854                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1855                 break;
1856
1857         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1858                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1859                    gpio_num, gpio_shift);
1860                 /* clear FLOAT and set SET */
1861                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1862                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1863                 break;
1864
1865         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1866                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1867                    gpio_num, gpio_shift);
1868                 /* set FLOAT */
1869                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1870                 break;
1871
1872         default:
1873                 break;
1874         }
1875
1876         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1877         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1878
1879         return 0;
1880 }
1881
1882 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1883 {
1884         u32 spio_mask = (1 << spio_num);
1885         u32 spio_reg;
1886
1887         if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1888             (spio_num > MISC_REGISTERS_SPIO_7)) {
1889                 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1890                 return -EINVAL;
1891         }
1892
1893         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1894         /* read SPIO and mask except the float bits */
1895         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1896
1897         switch (mode) {
1898         case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1899                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1900                 /* clear FLOAT and set CLR */
1901                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1902                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1903                 break;
1904
1905         case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1906                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1907                 /* clear FLOAT and set SET */
1908                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1909                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1910                 break;
1911
1912         case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1913                 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1914                 /* set FLOAT */
1915                 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1916                 break;
1917
1918         default:
1919                 break;
1920         }
1921
1922         REG_WR(bp, MISC_REG_SPIO, spio_reg);
1923         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1924
1925         return 0;
1926 }
1927
1928 static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1929 {
1930         switch (bp->link_vars.ieee_fc &
1931                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1932         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1933                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1934                                           ADVERTISED_Pause);
1935                 break;
1936         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1937                 bp->port.advertising |= (ADVERTISED_Asym_Pause |
1938                                          ADVERTISED_Pause);
1939                 break;
1940         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1941                 bp->port.advertising |= ADVERTISED_Asym_Pause;
1942                 break;
1943         default:
1944                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1945                                           ADVERTISED_Pause);
1946                 break;
1947         }
1948 }
1949
1950 static void bnx2x_link_report(struct bnx2x *bp)
1951 {
1952         if (bp->link_vars.link_up) {
1953                 if (bp->state == BNX2X_STATE_OPEN)
1954                         netif_carrier_on(bp->dev);
1955                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
1956
1957                 printk("%d Mbps ", bp->link_vars.line_speed);
1958
1959                 if (bp->link_vars.duplex == DUPLEX_FULL)
1960                         printk("full duplex");
1961                 else
1962                         printk("half duplex");
1963
1964                 if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
1965                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
1966                                 printk(", receive ");
1967                                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1968                                         printk("& transmit ");
1969                         } else {
1970                                 printk(", transmit ");
1971                         }
1972                         printk("flow control ON");
1973                 }
1974                 printk("\n");
1975
1976         } else { /* link_down */
1977                 netif_carrier_off(bp->dev);
1978                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
1979         }
1980 }
1981
1982 static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1983 {
1984         if (!BP_NOMCP(bp)) {
1985                 u8 rc;
1986
1987                 /* Initialize link parameters structure variables */
1988                 /* It is recommended to turn off RX FC for jumbo frames
1989                    for better performance */
1990                 if (IS_E1HMF(bp))
1991                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1992                 else if (bp->dev->mtu > 5000)
1993                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1994                 else
1995                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1996
1997                 bnx2x_acquire_phy_lock(bp);
1998                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1999                 bnx2x_release_phy_lock(bp);
2000
2001                 bnx2x_calc_fc_adv(bp);
2002
2003                 if (bp->link_vars.link_up)
2004                         bnx2x_link_report(bp);
2005
2006
2007                 return rc;
2008         }
2009         BNX2X_ERR("Bootcode is missing -not initializing link\n");
2010         return -EINVAL;
2011 }
2012
2013 static void bnx2x_link_set(struct bnx2x *bp)
2014 {
2015         if (!BP_NOMCP(bp)) {
2016                 bnx2x_acquire_phy_lock(bp);
2017                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2018                 bnx2x_release_phy_lock(bp);
2019
2020                 bnx2x_calc_fc_adv(bp);
2021         } else
2022                 BNX2X_ERR("Bootcode is missing -not setting link\n");
2023 }
2024
2025 static void bnx2x__link_reset(struct bnx2x *bp)
2026 {
2027         if (!BP_NOMCP(bp)) {
2028                 bnx2x_acquire_phy_lock(bp);
2029                 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
2030                 bnx2x_release_phy_lock(bp);
2031         } else
2032                 BNX2X_ERR("Bootcode is missing -not resetting link\n");
2033 }
2034
2035 static u8 bnx2x_link_test(struct bnx2x *bp)
2036 {
2037         u8 rc;
2038
2039         bnx2x_acquire_phy_lock(bp);
2040         rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
2041         bnx2x_release_phy_lock(bp);
2042
2043         return rc;
2044 }
2045
2046 /* Calculates the sum of vn_min_rates.
2047    It's needed for further normalizing of the min_rates.
2048
2049    Returns:
2050      sum of vn_min_rates
2051        or
2052      0 - if all the min_rates are 0.
2053      In the later case fairness algorithm should be deactivated.
2054      If not all min_rates are zero then those that are zeroes will
2055      be set to 1.
2056  */
2057 static u32 bnx2x_calc_vn_wsum(struct bnx2x *bp)
2058 {
2059         int i, port = BP_PORT(bp);
2060         u32 wsum = 0;
2061         int all_zero = 1;
2062
2063         for (i = 0; i < E1HVN_MAX; i++) {
2064                 u32 vn_cfg =
2065                         SHMEM_RD(bp, mf_cfg.func_mf_config[2*i + port].config);
2066                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2067                                      FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2068                 if (!(vn_cfg & FUNC_MF_CFG_FUNC_HIDE)) {
2069                         /* If min rate is zero - set it to 1 */
2070                         if (!vn_min_rate)
2071                                 vn_min_rate = DEF_MIN_RATE;
2072                         else
2073                                 all_zero = 0;
2074
2075                         wsum += vn_min_rate;
2076                 }
2077         }
2078
2079         /* ... only if all min rates are zeros - disable FAIRNESS */
2080         if (all_zero)
2081                 return 0;
2082
2083         return wsum;
2084 }
2085
2086 static void bnx2x_init_port_minmax(struct bnx2x *bp,
2087                                    int en_fness,
2088                                    u16 port_rate,
2089                                    struct cmng_struct_per_port *m_cmng_port)
2090 {
2091         u32 r_param = port_rate / 8;
2092         int port = BP_PORT(bp);
2093         int i;
2094
2095         memset(m_cmng_port, 0, sizeof(struct cmng_struct_per_port));
2096
2097         /* Enable minmax only if we are in e1hmf mode */
2098         if (IS_E1HMF(bp)) {
2099                 u32 fair_periodic_timeout_usec;
2100                 u32 t_fair;
2101
2102                 /* Enable rate shaping and fairness */
2103                 m_cmng_port->flags.cmng_vn_enable = 1;
2104                 m_cmng_port->flags.fairness_enable = en_fness ? 1 : 0;
2105                 m_cmng_port->flags.rate_shaping_enable = 1;
2106
2107                 if (!en_fness)
2108                         DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2109                            "  fairness will be disabled\n");
2110
2111                 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2112                 m_cmng_port->rs_vars.rs_periodic_timeout =
2113                                                 RS_PERIODIC_TIMEOUT_USEC / 4;
2114
2115                 /* this is the threshold below which no timer arming will occur
2116                    1.25 coefficient is for the threshold to be a little bigger
2117                    than the real time, to compensate for timer in-accuracy */
2118                 m_cmng_port->rs_vars.rs_threshold =
2119                                 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2120
2121                 /* resolution of fairness timer */
2122                 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2123                 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2124                 t_fair = T_FAIR_COEF / port_rate;
2125
2126                 /* this is the threshold below which we won't arm
2127                    the timer anymore */
2128                 m_cmng_port->fair_vars.fair_threshold = QM_ARB_BYTES;
2129
2130                 /* we multiply by 1e3/8 to get bytes/msec.
2131                    We don't want the credits to pass a credit
2132                    of the T_FAIR*FAIR_MEM (algorithm resolution) */
2133                 m_cmng_port->fair_vars.upper_bound =
2134                                                 r_param * t_fair * FAIR_MEM;
2135                 /* since each tick is 4 usec */
2136                 m_cmng_port->fair_vars.fairness_timeout =
2137                                                 fair_periodic_timeout_usec / 4;
2138
2139         } else {
2140                 /* Disable rate shaping and fairness */
2141                 m_cmng_port->flags.cmng_vn_enable = 0;
2142                 m_cmng_port->flags.fairness_enable = 0;
2143                 m_cmng_port->flags.rate_shaping_enable = 0;
2144
2145                 DP(NETIF_MSG_IFUP,
2146                    "Single function mode  minmax will be disabled\n");
2147         }
2148
2149         /* Store it to internal memory */
2150         for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
2151                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2152                        XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
2153                        ((u32 *)(m_cmng_port))[i]);
2154 }
2155
2156 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
2157                                    u32 wsum, u16 port_rate,
2158                                  struct cmng_struct_per_port *m_cmng_port)
2159 {
2160         struct rate_shaping_vars_per_vn m_rs_vn;
2161         struct fairness_vars_per_vn m_fair_vn;
2162         u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2163         u16 vn_min_rate, vn_max_rate;
2164         int i;
2165
2166         /* If function is hidden - set min and max to zeroes */
2167         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2168                 vn_min_rate = 0;
2169                 vn_max_rate = 0;
2170
2171         } else {
2172                 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2173                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2174                 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2175                    if current min rate is zero - set it to 1.
2176                    This is a requirement of the algorithm. */
2177                 if ((vn_min_rate == 0) && wsum)
2178                         vn_min_rate = DEF_MIN_RATE;
2179                 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2180                                 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2181         }
2182
2183         DP(NETIF_MSG_IFUP, "func %d: vn_min_rate=%d  vn_max_rate=%d  "
2184            "wsum=%d\n", func, vn_min_rate, vn_max_rate, wsum);
2185
2186         memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2187         memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2188
2189         /* global vn counter - maximal Mbps for this vn */
2190         m_rs_vn.vn_counter.rate = vn_max_rate;
2191
2192         /* quota - number of bytes transmitted in this period */
2193         m_rs_vn.vn_counter.quota =
2194                                 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2195
2196 #ifdef BNX2X_PER_PROT_QOS
2197         /* per protocol counter */
2198         for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) {
2199                 /* maximal Mbps for this protocol */
2200                 m_rs_vn.protocol_counters[protocol].rate =
2201                                                 protocol_max_rate[protocol];
2202                 /* the quota in each timer period -
2203                    number of bytes transmitted in this period */
2204                 m_rs_vn.protocol_counters[protocol].quota =
2205                         (u32)(rs_periodic_timeout_usec *
2206                           ((double)m_rs_vn.
2207                                    protocol_counters[protocol].rate/8));
2208         }
2209 #endif
2210
2211         if (wsum) {
2212                 /* credit for each period of the fairness algorithm:
2213                    number of bytes in T_FAIR (the vn share the port rate).
2214                    wsum should not be larger than 10000, thus
2215                    T_FAIR_COEF / (8 * wsum) will always be grater than zero */
2216                 m_fair_vn.vn_credit_delta =
2217                         max((u64)(vn_min_rate * (T_FAIR_COEF / (8 * wsum))),
2218                             (u64)(m_cmng_port->fair_vars.fair_threshold * 2));
2219                 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2220                    m_fair_vn.vn_credit_delta);
2221         }
2222
2223 #ifdef BNX2X_PER_PROT_QOS
2224         do {
2225                 u32 protocolWeightSum = 0;
2226
2227                 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++)
2228                         protocolWeightSum +=
2229                                         drvInit.protocol_min_rate[protocol];
2230                 /* per protocol counter -
2231                    NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */
2232                 if (protocolWeightSum > 0) {
2233                         for (protocol = 0;
2234                              protocol < NUM_OF_PROTOCOLS; protocol++)
2235                                 /* credit for each period of the
2236                                    fairness algorithm - number of bytes in
2237                                    T_FAIR (the protocol share the vn rate) */
2238                                 m_fair_vn.protocol_credit_delta[protocol] =
2239                                         (u32)((vn_min_rate / 8) * t_fair *
2240                                         protocol_min_rate / protocolWeightSum);
2241                 }
2242         } while (0);
2243 #endif
2244
2245         /* Store it to internal memory */
2246         for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2247                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2248                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2249                        ((u32 *)(&m_rs_vn))[i]);
2250
2251         for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2252                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2253                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2254                        ((u32 *)(&m_fair_vn))[i]);
2255 }
2256
2257 /* This function is called upon link interrupt */
2258 static void bnx2x_link_attn(struct bnx2x *bp)
2259 {
2260         int vn;
2261
2262         /* Make sure that we are synced with the current statistics */
2263         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2264
2265         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2266
2267         if (bp->link_vars.link_up) {
2268
2269                 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2270                         struct host_port_stats *pstats;
2271
2272                         pstats = bnx2x_sp(bp, port_stats);
2273                         /* reset old bmac stats */
2274                         memset(&(pstats->mac_stx[0]), 0,
2275                                sizeof(struct mac_stx));
2276                 }
2277                 if ((bp->state == BNX2X_STATE_OPEN) ||
2278                     (bp->state == BNX2X_STATE_DISABLED))
2279                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2280         }
2281
2282         /* indicate link status */
2283         bnx2x_link_report(bp);
2284
2285         if (IS_E1HMF(bp)) {
2286                 int func;
2287
2288                 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2289                         if (vn == BP_E1HVN(bp))
2290                                 continue;
2291
2292                         func = ((vn << 1) | BP_PORT(bp));
2293
2294                         /* Set the attention towards other drivers
2295                            on the same port */
2296                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2297                                (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2298                 }
2299         }
2300
2301         if (CHIP_IS_E1H(bp) && (bp->link_vars.line_speed > 0)) {
2302                 struct cmng_struct_per_port m_cmng_port;
2303                 u32 wsum;
2304                 int port = BP_PORT(bp);
2305
2306                 /* Init RATE SHAPING and FAIRNESS contexts */
2307                 wsum = bnx2x_calc_vn_wsum(bp);
2308                 bnx2x_init_port_minmax(bp, (int)wsum,
2309                                         bp->link_vars.line_speed,
2310                                         &m_cmng_port);
2311                 if (IS_E1HMF(bp))
2312                         for (vn = VN_0; vn < E1HVN_MAX; vn++)
2313                                 bnx2x_init_vn_minmax(bp, 2*vn + port,
2314                                         wsum, bp->link_vars.line_speed,
2315                                                      &m_cmng_port);
2316         }
2317 }
2318
2319 static void bnx2x__link_status_update(struct bnx2x *bp)
2320 {
2321         if (bp->state != BNX2X_STATE_OPEN)
2322                 return;
2323
2324         bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2325
2326         if (bp->link_vars.link_up)
2327                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2328         else
2329                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2330
2331         /* indicate link status */
2332         bnx2x_link_report(bp);
2333 }
2334
2335 static void bnx2x_pmf_update(struct bnx2x *bp)
2336 {
2337         int port = BP_PORT(bp);
2338         u32 val;
2339
2340         bp->port.pmf = 1;
2341         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2342
2343         /* enable nig attention */
2344         val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2345         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2346         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2347
2348         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2349 }
2350
2351 /* end of Link */
2352
2353 /* slow path */
2354
2355 /*
2356  * General service functions
2357  */
2358
2359 /* the slow path queue is odd since completions arrive on the fastpath ring */
2360 static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2361                          u32 data_hi, u32 data_lo, int common)
2362 {
2363         int func = BP_FUNC(bp);
2364
2365         DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2366            "SPQE (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
2367            (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2368            (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2369            HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2370
2371 #ifdef BNX2X_STOP_ON_ERROR
2372         if (unlikely(bp->panic))
2373                 return -EIO;
2374 #endif
2375
2376         spin_lock_bh(&bp->spq_lock);
2377
2378         if (!bp->spq_left) {
2379                 BNX2X_ERR("BUG! SPQ ring full!\n");
2380                 spin_unlock_bh(&bp->spq_lock);
2381                 bnx2x_panic();
2382                 return -EBUSY;
2383         }
2384
2385         /* CID needs port number to be encoded int it */
2386         bp->spq_prod_bd->hdr.conn_and_cmd_data =
2387                         cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2388                                      HW_CID(bp, cid)));
2389         bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
2390         if (common)
2391                 bp->spq_prod_bd->hdr.type |=
2392                         cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2393
2394         bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2395         bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
2396
2397         bp->spq_left--;
2398
2399         if (bp->spq_prod_bd == bp->spq_last_bd) {
2400                 bp->spq_prod_bd = bp->spq;
2401                 bp->spq_prod_idx = 0;
2402                 DP(NETIF_MSG_TIMER, "end of spq\n");
2403
2404         } else {
2405                 bp->spq_prod_bd++;
2406                 bp->spq_prod_idx++;
2407         }
2408
2409         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2410                bp->spq_prod_idx);
2411
2412         spin_unlock_bh(&bp->spq_lock);
2413         return 0;
2414 }
2415
2416 /* acquire split MCP access lock register */
2417 static int bnx2x_acquire_alr(struct bnx2x *bp)
2418 {
2419         u32 i, j, val;
2420         int rc = 0;
2421
2422         might_sleep();
2423         i = 100;
2424         for (j = 0; j < i*10; j++) {
2425                 val = (1UL << 31);
2426                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2427                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2428                 if (val & (1L << 31))
2429                         break;
2430
2431                 msleep(5);
2432         }
2433         if (!(val & (1L << 31))) {
2434                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2435                 rc = -EBUSY;
2436         }
2437
2438         return rc;
2439 }
2440
2441 /* release split MCP access lock register */
2442 static void bnx2x_release_alr(struct bnx2x *bp)
2443 {
2444         u32 val = 0;
2445
2446         REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2447 }
2448
2449 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2450 {
2451         struct host_def_status_block *def_sb = bp->def_status_blk;
2452         u16 rc = 0;
2453
2454         barrier(); /* status block is written to by the chip */
2455         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2456                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2457                 rc |= 1;
2458         }
2459         if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2460                 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2461                 rc |= 2;
2462         }
2463         if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2464                 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2465                 rc |= 4;
2466         }
2467         if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2468                 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2469                 rc |= 8;
2470         }
2471         if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2472                 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2473                 rc |= 16;
2474         }
2475         return rc;
2476 }
2477
2478 /*
2479  * slow path service functions
2480  */
2481
2482 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2483 {
2484         int port = BP_PORT(bp);
2485         u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2486                        COMMAND_REG_ATTN_BITS_SET);
2487         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2488                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
2489         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2490                                        NIG_REG_MASK_INTERRUPT_PORT0;
2491         u32 aeu_mask;
2492
2493         if (bp->attn_state & asserted)
2494                 BNX2X_ERR("IGU ERROR\n");
2495
2496         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2497         aeu_mask = REG_RD(bp, aeu_addr);
2498
2499         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
2500            aeu_mask, asserted);
2501         aeu_mask &= ~(asserted & 0xff);
2502         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2503
2504         REG_WR(bp, aeu_addr, aeu_mask);
2505         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2506
2507         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2508         bp->attn_state |= asserted;
2509         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2510
2511         if (asserted & ATTN_HARD_WIRED_MASK) {
2512                 if (asserted & ATTN_NIG_FOR_FUNC) {
2513
2514                         bnx2x_acquire_phy_lock(bp);
2515
2516                         /* save nig interrupt mask */
2517                         bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
2518                         REG_WR(bp, nig_int_mask_addr, 0);
2519
2520                         bnx2x_link_attn(bp);
2521
2522                         /* handle unicore attn? */
2523                 }
2524                 if (asserted & ATTN_SW_TIMER_4_FUNC)
2525                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2526
2527                 if (asserted & GPIO_2_FUNC)
2528                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2529
2530                 if (asserted & GPIO_3_FUNC)
2531                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2532
2533                 if (asserted & GPIO_4_FUNC)
2534                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2535
2536                 if (port == 0) {
2537                         if (asserted & ATTN_GENERAL_ATTN_1) {
2538                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2539                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2540                         }
2541                         if (asserted & ATTN_GENERAL_ATTN_2) {
2542                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2543                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2544                         }
2545                         if (asserted & ATTN_GENERAL_ATTN_3) {
2546                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2547                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2548                         }
2549                 } else {
2550                         if (asserted & ATTN_GENERAL_ATTN_4) {
2551                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2552                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2553                         }
2554                         if (asserted & ATTN_GENERAL_ATTN_5) {
2555                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2556                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2557                         }
2558                         if (asserted & ATTN_GENERAL_ATTN_6) {
2559                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2560                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2561                         }
2562                 }
2563
2564         } /* if hardwired */
2565
2566         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2567            asserted, hc_addr);
2568         REG_WR(bp, hc_addr, asserted);
2569
2570         /* now set back the mask */
2571         if (asserted & ATTN_NIG_FOR_FUNC) {
2572                 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
2573                 bnx2x_release_phy_lock(bp);
2574         }
2575 }
2576
2577 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2578 {
2579         int port = BP_PORT(bp);
2580         int reg_offset;
2581         u32 val;
2582
2583         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2584                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2585
2586         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2587
2588                 val = REG_RD(bp, reg_offset);
2589                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2590                 REG_WR(bp, reg_offset, val);
2591
2592                 BNX2X_ERR("SPIO5 hw attention\n");
2593
2594                 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
2595                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
2596                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2597                         /* Fan failure attention */
2598
2599                         /* The PHY reset is controlled by GPIO 1 */
2600                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2601                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2602                         /* Low power mode is controlled by GPIO 2 */
2603                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2604                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2605                         /* mark the failure */
2606                         bp->link_params.ext_phy_config &=
2607                                         ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2608                         bp->link_params.ext_phy_config |=
2609                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2610                         SHMEM_WR(bp,
2611                                  dev_info.port_hw_config[port].
2612                                                         external_phy_config,
2613                                  bp->link_params.ext_phy_config);
2614                         /* log the failure */
2615                         printk(KERN_ERR PFX "Fan Failure on Network"
2616                                " Controller %s has caused the driver to"
2617                                " shutdown the card to prevent permanent"
2618                                " damage.  Please contact Dell Support for"
2619                                " assistance\n", bp->dev->name);
2620                         break;
2621
2622                 default:
2623                         break;
2624                 }
2625         }
2626
2627         if (attn & HW_INTERRUT_ASSERT_SET_0) {
2628
2629                 val = REG_RD(bp, reg_offset);
2630                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2631                 REG_WR(bp, reg_offset, val);
2632
2633                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2634                           (attn & HW_INTERRUT_ASSERT_SET_0));
2635                 bnx2x_panic();
2636         }
2637 }
2638
2639 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2640 {
2641         u32 val;
2642
2643         if (attn & BNX2X_DOORQ_ASSERT) {
2644
2645                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2646                 BNX2X_ERR("DB hw attention 0x%x\n", val);
2647                 /* DORQ discard attention */
2648                 if (val & 0x2)
2649                         BNX2X_ERR("FATAL error from DORQ\n");
2650         }
2651
2652         if (attn & HW_INTERRUT_ASSERT_SET_1) {
2653
2654                 int port = BP_PORT(bp);
2655                 int reg_offset;
2656
2657                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2658                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2659
2660                 val = REG_RD(bp, reg_offset);
2661                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2662                 REG_WR(bp, reg_offset, val);
2663
2664                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2665                           (attn & HW_INTERRUT_ASSERT_SET_1));
2666                 bnx2x_panic();
2667         }
2668 }
2669
2670 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2671 {
2672         u32 val;
2673
2674         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
2675
2676                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
2677                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
2678                 /* CFC error attention */
2679                 if (val & 0x2)
2680                         BNX2X_ERR("FATAL error from CFC\n");
2681         }
2682
2683         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
2684
2685                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
2686                 BNX2X_ERR("PXP hw attention 0x%x\n", val);
2687                 /* RQ_USDMDP_FIFO_OVERFLOW */
2688                 if (val & 0x18000)
2689                         BNX2X_ERR("FATAL error from PXP\n");
2690         }
2691
2692         if (attn & HW_INTERRUT_ASSERT_SET_2) {
2693
2694                 int port = BP_PORT(bp);
2695                 int reg_offset;
2696
2697                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
2698                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
2699
2700                 val = REG_RD(bp, reg_offset);
2701                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
2702                 REG_WR(bp, reg_offset, val);
2703
2704                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2705                           (attn & HW_INTERRUT_ASSERT_SET_2));
2706                 bnx2x_panic();
2707         }
2708 }
2709
2710 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2711 {
2712         u32 val;
2713
2714         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
2715
2716                 if (attn & BNX2X_PMF_LINK_ASSERT) {
2717                         int func = BP_FUNC(bp);
2718
2719                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2720                         bnx2x__link_status_update(bp);
2721                         if (SHMEM_RD(bp, func_mb[func].drv_status) &
2722                                                         DRV_STATUS_PMF)
2723                                 bnx2x_pmf_update(bp);
2724
2725                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2726
2727                         BNX2X_ERR("MC assert!\n");
2728                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
2729                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
2730                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
2731                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
2732                         bnx2x_panic();
2733
2734                 } else if (attn & BNX2X_MCP_ASSERT) {
2735
2736                         BNX2X_ERR("MCP assert!\n");
2737                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
2738                         bnx2x_fw_dump(bp);
2739
2740                 } else
2741                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
2742         }
2743
2744         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2745                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2746                 if (attn & BNX2X_GRC_TIMEOUT) {
2747                         val = CHIP_IS_E1H(bp) ?
2748                                 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
2749                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
2750                 }
2751                 if (attn & BNX2X_GRC_RSV) {
2752                         val = CHIP_IS_E1H(bp) ?
2753                                 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
2754                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
2755                 }
2756                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
2757         }
2758 }
2759
2760 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2761 {
2762         struct attn_route attn;
2763         struct attn_route group_mask;
2764         int port = BP_PORT(bp);
2765         int index;
2766         u32 reg_addr;
2767         u32 val;
2768         u32 aeu_mask;
2769
2770         /* need to take HW lock because MCP or other port might also
2771            try to handle this event */
2772         bnx2x_acquire_alr(bp);
2773
2774         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2775         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2776         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2777         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2778         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
2779            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
2780
2781         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2782                 if (deasserted & (1 << index)) {
2783                         group_mask = bp->attn_group[index];
2784
2785                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
2786                            index, group_mask.sig[0], group_mask.sig[1],
2787                            group_mask.sig[2], group_mask.sig[3]);
2788
2789                         bnx2x_attn_int_deasserted3(bp,
2790                                         attn.sig[3] & group_mask.sig[3]);
2791                         bnx2x_attn_int_deasserted1(bp,
2792                                         attn.sig[1] & group_mask.sig[1]);
2793                         bnx2x_attn_int_deasserted2(bp,
2794                                         attn.sig[2] & group_mask.sig[2]);
2795                         bnx2x_attn_int_deasserted0(bp,
2796                                         attn.sig[0] & group_mask.sig[0]);
2797
2798                         if ((attn.sig[0] & group_mask.sig[0] &
2799                                                 HW_PRTY_ASSERT_SET_0) ||
2800                             (attn.sig[1] & group_mask.sig[1] &
2801                                                 HW_PRTY_ASSERT_SET_1) ||
2802                             (attn.sig[2] & group_mask.sig[2] &
2803                                                 HW_PRTY_ASSERT_SET_2))
2804                                 BNX2X_ERR("FATAL HW block parity attention\n");
2805                 }
2806         }
2807
2808         bnx2x_release_alr(bp);
2809
2810         reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2811
2812         val = ~deasserted;
2813         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2814            val, reg_addr);
2815         REG_WR(bp, reg_addr, val);
2816
2817         if (~bp->attn_state & deasserted)
2818                 BNX2X_ERR("IGU ERROR\n");
2819
2820         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2821                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
2822
2823         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2824         aeu_mask = REG_RD(bp, reg_addr);
2825
2826         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
2827            aeu_mask, deasserted);
2828         aeu_mask |= (deasserted & 0xff);
2829         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2830
2831         REG_WR(bp, reg_addr, aeu_mask);
2832         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2833
2834         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2835         bp->attn_state &= ~deasserted;
2836         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2837 }
2838
2839 static void bnx2x_attn_int(struct bnx2x *bp)
2840 {
2841         /* read local copy of bits */
2842         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
2843                                                                 attn_bits);
2844         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
2845                                                                 attn_bits_ack);
2846         u32 attn_state = bp->attn_state;
2847
2848         /* look for changed bits */
2849         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
2850         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
2851
2852         DP(NETIF_MSG_HW,
2853            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
2854            attn_bits, attn_ack, asserted, deasserted);
2855
2856         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
2857                 BNX2X_ERR("BAD attention state\n");
2858
2859         /* handle bits that were raised */
2860         if (asserted)
2861                 bnx2x_attn_int_asserted(bp, asserted);
2862
2863         if (deasserted)
2864                 bnx2x_attn_int_deasserted(bp, deasserted);
2865 }
2866
2867 static void bnx2x_sp_task(struct work_struct *work)
2868 {
2869         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
2870         u16 status;
2871
2872
2873         /* Return here if interrupt is disabled */
2874         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2875                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2876                 return;
2877         }
2878
2879         status = bnx2x_update_dsb_idx(bp);
2880 /*      if (status == 0)                                     */
2881 /*              BNX2X_ERR("spurious slowpath interrupt!\n"); */
2882
2883         DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
2884
2885         /* HW attentions */
2886         if (status & 0x1)
2887                 bnx2x_attn_int(bp);
2888
2889         /* CStorm events: query_stats, port delete ramrod */
2890         if (status & 0x2)
2891                 bp->stats_pending = 0;
2892
2893         bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
2894                      IGU_INT_NOP, 1);
2895         bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2896                      IGU_INT_NOP, 1);
2897         bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2898                      IGU_INT_NOP, 1);
2899         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2900                      IGU_INT_NOP, 1);
2901         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2902                      IGU_INT_ENABLE, 1);
2903
2904 }
2905
2906 static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2907 {
2908         struct net_device *dev = dev_instance;
2909         struct bnx2x *bp = netdev_priv(dev);
2910
2911         /* Return here if interrupt is disabled */
2912         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2913                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2914                 return IRQ_HANDLED;
2915         }
2916
2917         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
2918
2919 #ifdef BNX2X_STOP_ON_ERROR
2920         if (unlikely(bp->panic))
2921                 return IRQ_HANDLED;
2922 #endif
2923
2924         queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
2925
2926         return IRQ_HANDLED;
2927 }
2928
2929 /* end of slow path */
2930
2931 /* Statistics */
2932
2933 /****************************************************************************
2934 * Macros
2935 ****************************************************************************/
2936
2937 /* sum[hi:lo] += add[hi:lo] */
2938 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2939         do { \
2940                 s_lo += a_lo; \
2941                 s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
2942         } while (0)
2943
2944 /* difference = minuend - subtrahend */
2945 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2946         do { \
2947                 if (m_lo < s_lo) { \
2948                         /* underflow */ \
2949                         d_hi = m_hi - s_hi; \
2950                         if (d_hi > 0) { \
2951                                 /* we can 'loan' 1 */ \
2952                                 d_hi--; \
2953                                 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2954                         } else { \
2955                                 /* m_hi <= s_hi */ \
2956                                 d_hi = 0; \
2957                                 d_lo = 0; \
2958                         } \
2959                 } else { \
2960                         /* m_lo >= s_lo */ \
2961                         if (m_hi < s_hi) { \
2962                                 d_hi = 0; \
2963                                 d_lo = 0; \
2964                         } else { \
2965                                 /* m_hi >= s_hi */ \
2966                                 d_hi = m_hi - s_hi; \
2967                                 d_lo = m_lo - s_lo; \
2968                         } \
2969                 } \
2970         } while (0)
2971
2972 #define UPDATE_STAT64(s, t) \
2973         do { \
2974                 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
2975                         diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
2976                 pstats->mac_stx[0].t##_hi = new->s##_hi; \
2977                 pstats->mac_stx[0].t##_lo = new->s##_lo; \
2978                 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
2979                        pstats->mac_stx[1].t##_lo, diff.lo); \
2980         } while (0)
2981
2982 #define UPDATE_STAT64_NIG(s, t) \
2983         do { \
2984                 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
2985                         diff.lo, new->s##_lo, old->s##_lo); \
2986                 ADD_64(estats->t##_hi, diff.hi, \
2987                        estats->t##_lo, diff.lo); \
2988         } while (0)
2989
2990 /* sum[hi:lo] += add */
2991 #define ADD_EXTEND_64(s_hi, s_lo, a) \
2992         do { \
2993                 s_lo += a; \
2994                 s_hi += (s_lo < a) ? 1 : 0; \
2995         } while (0)
2996
2997 #define UPDATE_EXTEND_STAT(s) \
2998         do { \
2999                 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
3000                               pstats->mac_stx[1].s##_lo, \
3001                               new->s); \
3002         } while (0)
3003
3004 #define UPDATE_EXTEND_TSTAT(s, t) \
3005         do { \
3006                 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
3007                 old_tclient->s = le32_to_cpu(tclient->s); \
3008                 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
3009         } while (0)
3010
3011 #define UPDATE_EXTEND_XSTAT(s, t) \
3012         do { \
3013                 diff = le32_to_cpu(xclient->s) - old_xclient->s; \
3014                 old_xclient->s = le32_to_cpu(xclient->s); \
3015                 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
3016         } while (0)
3017
3018 /*
3019  * General service functions
3020  */
3021
3022 static inline long bnx2x_hilo(u32 *hiref)
3023 {
3024         u32 lo = *(hiref + 1);
3025 #if (BITS_PER_LONG == 64)
3026         u32 hi = *hiref;
3027
3028         return HILO_U64(hi, lo);
3029 #else
3030         return lo;
3031 #endif
3032 }
3033
3034 /*
3035  * Init service functions
3036  */
3037
3038 static void bnx2x_storm_stats_post(struct bnx2x *bp)
3039 {
3040         if (!bp->stats_pending) {
3041                 struct eth_query_ramrod_data ramrod_data = {0};
3042                 int rc;
3043
3044                 ramrod_data.drv_counter = bp->stats_counter++;
3045                 ramrod_data.collect_port_1b = bp->port.pmf ? 1 : 0;
3046                 ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp));
3047
3048                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
3049                                    ((u32 *)&ramrod_data)[1],
3050                                    ((u32 *)&ramrod_data)[0], 0);
3051                 if (rc == 0) {
3052                         /* stats ramrod has it's own slot on the spq */
3053                         bp->spq_left++;
3054                         bp->stats_pending = 1;
3055                 }
3056         }
3057 }
3058
3059 static void bnx2x_stats_init(struct bnx2x *bp)
3060 {
3061         int port = BP_PORT(bp);
3062
3063         bp->executer_idx = 0;
3064         bp->stats_counter = 0;
3065
3066         /* port stats */
3067         if (!BP_NOMCP(bp))
3068                 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
3069         else
3070                 bp->port.port_stx = 0;
3071         DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
3072
3073         memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3074         bp->port.old_nig_stats.brb_discard =
3075                         REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3076         bp->port.old_nig_stats.brb_truncate =
3077                         REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3078         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3079                     &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3080         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
3081                     &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
3082
3083         /* function stats */
3084         memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3085         memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
3086         memset(&bp->old_xclient, 0, sizeof(struct xstorm_per_client_stats));
3087         memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
3088
3089         bp->stats_state = STATS_STATE_DISABLED;
3090         if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
3091                 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3092 }
3093
3094 static void bnx2x_hw_stats_post(struct bnx2x *bp)
3095 {
3096         struct dmae_command *dmae = &bp->stats_dmae;
3097         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3098
3099         *stats_comp = DMAE_COMP_VAL;
3100
3101         /* loader */
3102         if (bp->executer_idx) {
3103                 int loader_idx = PMF_DMAE_C(bp);
3104
3105                 memset(dmae, 0, sizeof(struct dmae_command));
3106
3107                 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3108                                 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3109                                 DMAE_CMD_DST_RESET |
3110 #ifdef __BIG_ENDIAN
3111                                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3112 #else
3113                                 DMAE_CMD_ENDIANITY_DW_SWAP |
3114 #endif
3115                                 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3116                                                DMAE_CMD_PORT_0) |
3117                                 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3118                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3119                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3120                 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3121                                      sizeof(struct dmae_command) *
3122                                      (loader_idx + 1)) >> 2;
3123                 dmae->dst_addr_hi = 0;
3124                 dmae->len = sizeof(struct dmae_command) >> 2;
3125                 if (CHIP_IS_E1(bp))
3126                         dmae->len--;
3127                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3128                 dmae->comp_addr_hi = 0;
3129                 dmae->comp_val = 1;
3130
3131                 *stats_comp = 0;
3132                 bnx2x_post_dmae(bp, dmae, loader_idx);
3133
3134         } else if (bp->func_stx) {
3135                 *stats_comp = 0;
3136                 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3137         }
3138 }
3139
3140 static int bnx2x_stats_comp(struct bnx2x *bp)
3141 {
3142         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3143         int cnt = 10;
3144
3145         might_sleep();
3146         while (*stats_comp != DMAE_COMP_VAL) {
3147                 if (!cnt) {
3148                         BNX2X_ERR("timeout waiting for stats finished\n");
3149                         break;
3150                 }
3151                 cnt--;
3152                 msleep(1);
3153         }
3154         return 1;
3155 }
3156
3157 /*
3158  * Statistics service functions
3159  */
3160
3161 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3162 {
3163         struct dmae_command *dmae;
3164         u32 opcode;
3165         int loader_idx = PMF_DMAE_C(bp);
3166         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3167
3168         /* sanity */
3169         if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3170                 BNX2X_ERR("BUG!\n");
3171                 return;
3172         }
3173
3174         bp->executer_idx = 0;
3175
3176         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3177                   DMAE_CMD_C_ENABLE |
3178                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3179 #ifdef __BIG_ENDIAN
3180                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3181 #else
3182                   DMAE_CMD_ENDIANITY_DW_SWAP |
3183 #endif
3184                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3185                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3186
3187         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3188         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3189         dmae->src_addr_lo = bp->port.port_stx >> 2;
3190         dmae->src_addr_hi = 0;
3191         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3192         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3193         dmae->len = DMAE_LEN32_RD_MAX;
3194         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3195         dmae->comp_addr_hi = 0;
3196         dmae->comp_val = 1;
3197
3198         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3199         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3200         dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3201         dmae->src_addr_hi = 0;
3202         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3203                                    DMAE_LEN32_RD_MAX * 4);
3204         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3205                                    DMAE_LEN32_RD_MAX * 4);
3206         dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3207         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3208         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3209         dmae->comp_val = DMAE_COMP_VAL;
3210
3211         *stats_comp = 0;
3212         bnx2x_hw_stats_post(bp);
3213         bnx2x_stats_comp(bp);
3214 }
3215
3216 static void bnx2x_port_stats_init(struct bnx2x *bp)
3217 {
3218         struct dmae_command *dmae;
3219         int port = BP_PORT(bp);
3220         int vn = BP_E1HVN(bp);
3221         u32 opcode;
3222         int loader_idx = PMF_DMAE_C(bp);
3223         u32 mac_addr;
3224         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3225
3226         /* sanity */
3227         if (!bp->link_vars.link_up || !bp->port.pmf) {
3228                 BNX2X_ERR("BUG!\n");
3229                 return;
3230         }
3231
3232         bp->executer_idx = 0;
3233
3234         /* MCP */
3235         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3236                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3237                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3238 #ifdef __BIG_ENDIAN
3239                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3240 #else
3241                   DMAE_CMD_ENDIANITY_DW_SWAP |
3242 #endif
3243                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3244                   (vn << DMAE_CMD_E1HVN_SHIFT));
3245
3246         if (bp->port.port_stx) {
3247
3248                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3249                 dmae->opcode = opcode;
3250                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3251                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3252                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3253                 dmae->dst_addr_hi = 0;
3254                 dmae->len = sizeof(struct host_port_stats) >> 2;
3255                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3256                 dmae->comp_addr_hi = 0;
3257                 dmae->comp_val = 1;
3258         }
3259
3260         if (bp->func_stx) {
3261
3262                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3263                 dmae->opcode = opcode;
3264                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3265                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3266                 dmae->dst_addr_lo = bp->func_stx >> 2;
3267                 dmae->dst_addr_hi = 0;
3268                 dmae->len = sizeof(struct host_func_stats) >> 2;
3269                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3270                 dmae->comp_addr_hi = 0;
3271                 dmae->comp_val = 1;
3272         }
3273
3274         /* MAC */
3275         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3276                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3277                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3278 #ifdef __BIG_ENDIAN
3279                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3280 #else
3281                   DMAE_CMD_ENDIANITY_DW_SWAP |
3282 #endif
3283                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3284                   (vn << DMAE_CMD_E1HVN_SHIFT));
3285
3286         if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
3287
3288                 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3289                                    NIG_REG_INGRESS_BMAC0_MEM);
3290
3291                 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3292                    BIGMAC_REGISTER_TX_STAT_GTBYT */
3293                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3294                 dmae->opcode = opcode;
3295                 dmae->src_addr_lo = (mac_addr +
3296                                      BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3297                 dmae->src_addr_hi = 0;
3298                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3299                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3300                 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3301                              BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3302                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3303                 dmae->comp_addr_hi = 0;
3304                 dmae->comp_val = 1;
3305
3306                 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3307                    BIGMAC_REGISTER_RX_STAT_GRIPJ */
3308                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3309                 dmae->opcode = opcode;
3310                 dmae->src_addr_lo = (mac_addr +
3311                                      BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3312                 dmae->src_addr_hi = 0;
3313                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3314                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3315                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3316                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3317                 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3318                              BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3319                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3320                 dmae->comp_addr_hi = 0;
3321                 dmae->comp_val = 1;
3322
3323         } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
3324
3325                 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3326
3327                 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3328                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3329                 dmae->opcode = opcode;
3330                 dmae->src_addr_lo = (mac_addr +
3331                                      EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3332                 dmae->src_addr_hi = 0;
3333                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3334                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3335                 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3336                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3337                 dmae->comp_addr_hi = 0;
3338                 dmae->comp_val = 1;
3339
3340                 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3341                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3342                 dmae->opcode = opcode;
3343                 dmae->src_addr_lo = (mac_addr +
3344                                      EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3345                 dmae->src_addr_hi = 0;
3346                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3347                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3348                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3349                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3350                 dmae->len = 1;
3351                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3352                 dmae->comp_addr_hi = 0;
3353                 dmae->comp_val = 1;
3354
3355                 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3356                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3357                 dmae->opcode = opcode;
3358                 dmae->src_addr_lo = (mac_addr +
3359                                      EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3360                 dmae->src_addr_hi = 0;
3361                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3362                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3363                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3364                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3365                 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3366                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3367                 dmae->comp_addr_hi = 0;
3368                 dmae->comp_val = 1;
3369         }
3370
3371         /* NIG */
3372         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3373         dmae->opcode = opcode;
3374         dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3375                                     NIG_REG_STAT0_BRB_DISCARD) >> 2;
3376         dmae->src_addr_hi = 0;
3377         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
3378         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
3379         dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
3380         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3381         dmae->comp_addr_hi = 0;
3382         dmae->comp_val = 1;
3383
3384         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3385         dmae->opcode = opcode;
3386         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
3387                                     NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
3388         dmae->src_addr_hi = 0;
3389         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3390                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3391         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3392                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3393         dmae->len = (2*sizeof(u32)) >> 2;
3394         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3395         dmae->comp_addr_hi = 0;
3396         dmae->comp_val = 1;
3397
3398         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3399         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3400                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3401                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3402 #ifdef __BIG_ENDIAN
3403                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3404 #else
3405                         DMAE_CMD_ENDIANITY_DW_SWAP |
3406 #endif
3407                         (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3408                         (vn << DMAE_CMD_E1HVN_SHIFT));
3409         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
3410                                     NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
3411         dmae->src_addr_hi = 0;
3412         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3413                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3414         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3415                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3416         dmae->len = (2*sizeof(u32)) >> 2;
3417         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3418         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3419         dmae->comp_val = DMAE_COMP_VAL;
3420
3421         *stats_comp = 0;
3422 }
3423
3424 static void bnx2x_func_stats_init(struct bnx2x *bp)
3425 {
3426         struct dmae_command *dmae = &bp->stats_dmae;
3427         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3428
3429         /* sanity */
3430         if (!bp->func_stx) {
3431                 BNX2X_ERR("BUG!\n");
3432                 return;
3433         }
3434
3435         bp->executer_idx = 0;
3436         memset(dmae, 0, sizeof(struct dmae_command));
3437
3438         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3439                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3440                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3441 #ifdef __BIG_ENDIAN
3442                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3443 #else
3444                         DMAE_CMD_ENDIANITY_DW_SWAP |
3445 #endif
3446                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3447                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3448         dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3449         dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3450         dmae->dst_addr_lo = bp->func_stx >> 2;
3451         dmae->dst_addr_hi = 0;
3452         dmae->len = sizeof(struct host_func_stats) >> 2;
3453         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3454         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3455         dmae->comp_val = DMAE_COMP_VAL;
3456
3457         *stats_comp = 0;
3458 }
3459
3460 static void bnx2x_stats_start(struct bnx2x *bp)
3461 {
3462         if (bp->port.pmf)
3463                 bnx2x_port_stats_init(bp);
3464
3465         else if (bp->func_stx)
3466                 bnx2x_func_stats_init(bp);
3467
3468         bnx2x_hw_stats_post(bp);
3469         bnx2x_storm_stats_post(bp);
3470 }
3471
3472 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
3473 {
3474         bnx2x_stats_comp(bp);
3475         bnx2x_stats_pmf_update(bp);
3476         bnx2x_stats_start(bp);
3477 }
3478
3479 static void bnx2x_stats_restart(struct bnx2x *bp)
3480 {
3481         bnx2x_stats_comp(bp);
3482         bnx2x_stats_start(bp);
3483 }
3484
3485 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3486 {
3487         struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
3488         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3489         struct regpair diff;
3490
3491         UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
3492         UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
3493         UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
3494         UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3495         UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3496         UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3497         UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3498         UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3499         UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived);
3500         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
3501         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
3502         UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
3503         UPDATE_STAT64(tx_stat_gt127,
3504                                 tx_stat_etherstatspkts65octetsto127octets);
3505         UPDATE_STAT64(tx_stat_gt255,
3506                                 tx_stat_etherstatspkts128octetsto255octets);
3507         UPDATE_STAT64(tx_stat_gt511,
3508                                 tx_stat_etherstatspkts256octetsto511octets);
3509         UPDATE_STAT64(tx_stat_gt1023,
3510                                 tx_stat_etherstatspkts512octetsto1023octets);
3511         UPDATE_STAT64(tx_stat_gt1518,
3512                                 tx_stat_etherstatspkts1024octetsto1522octets);
3513         UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
3514         UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
3515         UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
3516         UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
3517         UPDATE_STAT64(tx_stat_gterr,
3518                                 tx_stat_dot3statsinternalmactransmiterrors);
3519         UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
3520 }
3521
3522 static void bnx2x_emac_stats_update(struct bnx2x *bp)
3523 {
3524         struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
3525         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3526
3527         UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
3528         UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
3529         UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
3530         UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
3531         UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
3532         UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
3533         UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
3534         UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
3535         UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
3536         UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
3537         UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
3538         UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
3539         UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
3540         UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
3541         UPDATE_EXTEND_STAT(tx_stat_outxonsent);
3542         UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
3543         UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
3544         UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
3545         UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
3546         UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
3547         UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
3548         UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
3549         UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
3550         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
3551         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
3552         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
3553         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
3554         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
3555         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
3556         UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
3557         UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
3558 }
3559
3560 static int bnx2x_hw_stats_update(struct bnx2x *bp)
3561 {
3562         struct nig_stats *new = bnx2x_sp(bp, nig_stats);
3563         struct nig_stats *old = &(bp->port.old_nig_stats);
3564         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3565         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3566         struct regpair diff;
3567
3568         if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
3569                 bnx2x_bmac_stats_update(bp);
3570
3571         else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
3572                 bnx2x_emac_stats_update(bp);
3573
3574         else { /* unreached */
3575                 BNX2X_ERR("stats updated by dmae but no MAC active\n");
3576                 return -1;
3577         }
3578
3579         ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3580                       new->brb_discard - old->brb_discard);
3581         ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3582                       new->brb_truncate - old->brb_truncate);
3583
3584         UPDATE_STAT64_NIG(egress_mac_pkt0,
3585                                         etherstatspkts1024octetsto1522octets);
3586         UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
3587
3588         memcpy(old, new, sizeof(struct nig_stats));
3589
3590         memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
3591                sizeof(struct mac_stx));
3592         estats->brb_drop_hi = pstats->brb_drop_hi;
3593         estats->brb_drop_lo = pstats->brb_drop_lo;
3594
3595         pstats->host_port_stats_start = ++pstats->host_port_stats_end;
3596
3597         return 0;
3598 }
3599
3600 static int bnx2x_storm_stats_update(struct bnx2x *bp)
3601 {
3602         struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
3603         int cl_id = BP_CL_ID(bp);
3604         struct tstorm_per_port_stats *tport =
3605                                 &stats->tstorm_common.port_statistics;
3606         struct tstorm_per_client_stats *tclient =
3607                         &stats->tstorm_common.client_statistics[cl_id];
3608         struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3609         struct xstorm_per_client_stats *xclient =
3610                         &stats->xstorm_common.client_statistics[cl_id];
3611         struct xstorm_per_client_stats *old_xclient = &bp->old_xclient;
3612         struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
3613         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3614         u32 diff;
3615
3616         /* are storm stats valid? */
3617         if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
3618                                                         bp->stats_counter) {
3619                 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
3620                    "  tstorm counter (%d) != stats_counter (%d)\n",
3621                    tclient->stats_counter, bp->stats_counter);
3622                 return -1;
3623         }
3624         if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
3625                                                         bp->stats_counter) {
3626                 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
3627                    "  xstorm counter (%d) != stats_counter (%d)\n",
3628                    xclient->stats_counter, bp->stats_counter);
3629                 return -2;
3630         }
3631
3632         fstats->total_bytes_received_hi =
3633         fstats->valid_bytes_received_hi =
3634                                 le32_to_cpu(tclient->total_rcv_bytes.hi);
3635         fstats->total_bytes_received_lo =
3636         fstats->valid_bytes_received_lo =
3637                                 le32_to_cpu(tclient->total_rcv_bytes.lo);
3638
3639         estats->error_bytes_received_hi =
3640                                 le32_to_cpu(tclient->rcv_error_bytes.hi);
3641         estats->error_bytes_received_lo =
3642                                 le32_to_cpu(tclient->rcv_error_bytes.lo);
3643         ADD_64(estats->error_bytes_received_hi,
3644                estats->rx_stat_ifhcinbadoctets_hi,
3645                estats->error_bytes_received_lo,
3646                estats->rx_stat_ifhcinbadoctets_lo);
3647
3648         ADD_64(fstats->total_bytes_received_hi,
3649                estats->error_bytes_received_hi,
3650                fstats->total_bytes_received_lo,
3651                estats->error_bytes_received_lo);
3652
3653         UPDATE_EXTEND_TSTAT(rcv_unicast_pkts, total_unicast_packets_received);
3654         UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
3655                                 total_multicast_packets_received);
3656         UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
3657                                 total_broadcast_packets_received);
3658
3659         fstats->total_bytes_transmitted_hi =
3660                                 le32_to_cpu(xclient->total_sent_bytes.hi);
3661         fstats->total_bytes_transmitted_lo =
3662                                 le32_to_cpu(xclient->total_sent_bytes.lo);
3663
3664         UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
3665                                 total_unicast_packets_transmitted);
3666         UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
3667                                 total_multicast_packets_transmitted);
3668         UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
3669                                 total_broadcast_packets_transmitted);
3670
3671         memcpy(estats, &(fstats->total_bytes_received_hi),
3672                sizeof(struct host_func_stats) - 2*sizeof(u32));
3673
3674         estats->mac_filter_discard = le32_to_cpu(tport->mac_filter_discard);
3675         estats->xxoverflow_discard = le32_to_cpu(tport->xxoverflow_discard);
3676         estats->brb_truncate_discard =
3677                                 le32_to_cpu(tport->brb_truncate_discard);
3678         estats->mac_discard = le32_to_cpu(tport->mac_discard);
3679
3680         old_tclient->rcv_unicast_bytes.hi =
3681                                 le32_to_cpu(tclient->rcv_unicast_bytes.hi);
3682         old_tclient->rcv_unicast_bytes.lo =
3683                                 le32_to_cpu(tclient->rcv_unicast_bytes.lo);
3684         old_tclient->rcv_broadcast_bytes.hi =
3685                                 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
3686         old_tclient->rcv_broadcast_bytes.lo =
3687                                 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
3688         old_tclient->rcv_multicast_bytes.hi =
3689                                 le32_to_cpu(tclient->rcv_multicast_bytes.hi);
3690         old_tclient->rcv_multicast_bytes.lo =
3691                                 le32_to_cpu(tclient->rcv_multicast_bytes.lo);
3692         old_tclient->total_rcv_pkts = le32_to_cpu(tclient->total_rcv_pkts);
3693
3694         old_tclient->checksum_discard = le32_to_cpu(tclient->checksum_discard);
3695         old_tclient->packets_too_big_discard =
3696                                 le32_to_cpu(tclient->packets_too_big_discard);
3697         estats->no_buff_discard =
3698         old_tclient->no_buff_discard = le32_to_cpu(tclient->no_buff_discard);
3699         old_tclient->ttl0_discard = le32_to_cpu(tclient->ttl0_discard);
3700
3701         old_xclient->total_sent_pkts = le32_to_cpu(xclient->total_sent_pkts);
3702         old_xclient->unicast_bytes_sent.hi =
3703                                 le32_to_cpu(xclient->unicast_bytes_sent.hi);
3704         old_xclient->unicast_bytes_sent.lo =
3705                                 le32_to_cpu(xclient->unicast_bytes_sent.lo);
3706         old_xclient->multicast_bytes_sent.hi =
3707                                 le32_to_cpu(xclient->multicast_bytes_sent.hi);
3708         old_xclient->multicast_bytes_sent.lo =
3709                                 le32_to_cpu(xclient->multicast_bytes_sent.lo);
3710         old_xclient->broadcast_bytes_sent.hi =
3711                                 le32_to_cpu(xclient->broadcast_bytes_sent.hi);
3712         old_xclient->broadcast_bytes_sent.lo =
3713                                 le32_to_cpu(xclient->broadcast_bytes_sent.lo);
3714
3715         fstats->host_func_stats_start = ++fstats->host_func_stats_end;
3716
3717         return 0;
3718 }
3719
3720 static void bnx2x_net_stats_update(struct bnx2x *bp)
3721 {
3722         struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3723         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3724         struct net_device_stats *nstats = &bp->dev->stats;
3725
3726         nstats->rx_packets =
3727                 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
3728                 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
3729                 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
3730
3731         nstats->tx_packets =
3732                 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
3733                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
3734                 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
3735
3736         nstats->rx_bytes = bnx2x_hilo(&estats->valid_bytes_received_hi);
3737
3738         nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
3739
3740         nstats->rx_dropped = old_tclient->checksum_discard +
3741                              estats->mac_discard;
3742         nstats->tx_dropped = 0;
3743
3744         nstats->multicast =
3745                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
3746
3747         nstats->collisions =
3748                         estats->tx_stat_dot3statssinglecollisionframes_lo +
3749                         estats->tx_stat_dot3statsmultiplecollisionframes_lo +
3750                         estats->tx_stat_dot3statslatecollisions_lo +
3751                         estats->tx_stat_dot3statsexcessivecollisions_lo;
3752
3753         estats->jabber_packets_received =
3754                                 old_tclient->packets_too_big_discard +
3755                                 estats->rx_stat_dot3statsframestoolong_lo;
3756
3757         nstats->rx_length_errors =
3758                                 estats->rx_stat_etherstatsundersizepkts_lo +
3759                                 estats->jabber_packets_received;
3760         nstats->rx_over_errors = estats->brb_drop_lo + estats->brb_truncate_lo;
3761         nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo;
3762         nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo;
3763         nstats->rx_fifo_errors = old_tclient->no_buff_discard;
3764         nstats->rx_missed_errors = estats->xxoverflow_discard;
3765
3766         nstats->rx_errors = nstats->rx_length_errors +
3767                             nstats->rx_over_errors +
3768                             nstats->rx_crc_errors +
3769                             nstats->rx_frame_errors +
3770                             nstats->rx_fifo_errors +
3771                             nstats->rx_missed_errors;
3772
3773         nstats->tx_aborted_errors =
3774                         estats->tx_stat_dot3statslatecollisions_lo +
3775                         estats->tx_stat_dot3statsexcessivecollisions_lo;
3776         nstats->tx_carrier_errors = estats->rx_stat_falsecarriererrors_lo;
3777         nstats->tx_fifo_errors = 0;
3778         nstats->tx_heartbeat_errors = 0;
3779         nstats->tx_window_errors = 0;
3780
3781         nstats->tx_errors = nstats->tx_aborted_errors +
3782                             nstats->tx_carrier_errors;
3783 }
3784
3785 static void bnx2x_stats_update(struct bnx2x *bp)
3786 {
3787         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3788         int update = 0;
3789
3790         if (*stats_comp != DMAE_COMP_VAL)
3791                 return;
3792
3793         if (bp->port.pmf)
3794                 update = (bnx2x_hw_stats_update(bp) == 0);
3795
3796         update |= (bnx2x_storm_stats_update(bp) == 0);
3797
3798         if (update)
3799                 bnx2x_net_stats_update(bp);
3800
3801         else {
3802                 if (bp->stats_pending) {
3803                         bp->stats_pending++;
3804                         if (bp->stats_pending == 3) {
3805                                 BNX2X_ERR("stats not updated for 3 times\n");
3806                                 bnx2x_panic();
3807                                 return;
3808                         }
3809                 }
3810         }
3811
3812         if (bp->msglevel & NETIF_MSG_TIMER) {
3813                 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3814                 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3815                 struct net_device_stats *nstats = &bp->dev->stats;
3816                 int i;
3817
3818                 printk(KERN_DEBUG "%s:\n", bp->dev->name);
3819                 printk(KERN_DEBUG "  tx avail (%4x)  tx hc idx (%x)"
3820                                   "  tx pkt (%lx)\n",
3821                        bnx2x_tx_avail(bp->fp),
3822                        le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
3823                 printk(KERN_DEBUG "  rx usage (%4x)  rx hc idx (%x)"
3824                                   "  rx pkt (%lx)\n",
3825                        (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
3826                              bp->fp->rx_comp_cons),
3827                        le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3828                 printk(KERN_DEBUG "  %s (Xoff events %u)  brb drops %u\n",
3829                        netif_queue_stopped(bp->dev) ? "Xoff" : "Xon",
3830                        estats->driver_xoff, estats->brb_drop_lo);
3831                 printk(KERN_DEBUG "tstats: checksum_discard %u  "
3832                         "packets_too_big_discard %u  no_buff_discard %u  "
3833                         "mac_discard %u  mac_filter_discard %u  "
3834                         "xxovrflow_discard %u  brb_truncate_discard %u  "
3835                         "ttl0_discard %u\n",
3836                        old_tclient->checksum_discard,
3837                        old_tclient->packets_too_big_discard,
3838                        old_tclient->no_buff_discard, estats->mac_discard,
3839                        estats->mac_filter_discard, estats->xxoverflow_discard,
3840                        estats->brb_truncate_discard,
3841                        old_tclient->ttl0_discard);
3842
3843                 for_each_queue(bp, i) {
3844                         printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
3845                                bnx2x_fp(bp, i, tx_pkt),
3846                                bnx2x_fp(bp, i, rx_pkt),
3847                                bnx2x_fp(bp, i, rx_calls));
3848                 }
3849         }
3850
3851         bnx2x_hw_stats_post(bp);
3852         bnx2x_storm_stats_post(bp);
3853 }
3854
3855 static void bnx2x_port_stats_stop(struct bnx2x *bp)
3856 {
3857         struct dmae_command *dmae;
3858         u32 opcode;
3859         int loader_idx = PMF_DMAE_C(bp);
3860         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3861
3862         bp->executer_idx = 0;
3863
3864         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3865                   DMAE_CMD_C_ENABLE |
3866                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3867 #ifdef __BIG_ENDIAN
3868                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3869 #else
3870                   DMAE_CMD_ENDIANITY_DW_SWAP |
3871 #endif
3872                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3873                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3874
3875         if (bp->port.port_stx) {
3876
3877                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3878                 if (bp->func_stx)
3879                         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3880                 else
3881                         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3882                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3883                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3884                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3885                 dmae->dst_addr_hi = 0;
3886                 dmae->len = sizeof(struct host_port_stats) >> 2;
3887                 if (bp->func_stx) {
3888                         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3889                         dmae->comp_addr_hi = 0;
3890                         dmae->comp_val = 1;
3891                 } else {
3892                         dmae->comp_addr_lo =
3893                                 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3894                         dmae->comp_addr_hi =
3895                                 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3896                         dmae->comp_val = DMAE_COMP_VAL;
3897
3898                         *stats_comp = 0;
3899                 }
3900         }
3901
3902         if (bp->func_stx) {
3903
3904                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3905                 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3906                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3907                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3908                 dmae->dst_addr_lo = bp->func_stx >> 2;
3909                 dmae->dst_addr_hi = 0;
3910                 dmae->len = sizeof(struct host_func_stats) >> 2;
3911                 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3912                 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3913                 dmae->comp_val = DMAE_COMP_VAL;
3914
3915                 *stats_comp = 0;
3916         }
3917 }
3918
3919 static void bnx2x_stats_stop(struct bnx2x *bp)
3920 {
3921         int update = 0;
3922
3923         bnx2x_stats_comp(bp);
3924
3925         if (bp->port.pmf)
3926                 update = (bnx2x_hw_stats_update(bp) == 0);
3927
3928         update |= (bnx2x_storm_stats_update(bp) == 0);
3929
3930         if (update) {
3931                 bnx2x_net_stats_update(bp);
3932
3933                 if (bp->port.pmf)
3934                         bnx2x_port_stats_stop(bp);
3935
3936                 bnx2x_hw_stats_post(bp);
3937                 bnx2x_stats_comp(bp);
3938         }
3939 }
3940
3941 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
3942 {
3943 }
3944
3945 static const struct {
3946         void (*action)(struct bnx2x *bp);
3947         enum bnx2x_stats_state next_state;
3948 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
3949 /* state        event   */
3950 {
3951 /* DISABLED     PMF     */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
3952 /*              LINK_UP */ {bnx2x_stats_start,      STATS_STATE_ENABLED},
3953 /*              UPDATE  */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
3954 /*              STOP    */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
3955 },
3956 {
3957 /* ENABLED      PMF     */ {bnx2x_stats_pmf_start,  STATS_STATE_ENABLED},
3958 /*              LINK_UP */ {bnx2x_stats_restart,    STATS_STATE_ENABLED},
3959 /*              UPDATE  */ {bnx2x_stats_update,     STATS_STATE_ENABLED},
3960 /*              STOP    */ {bnx2x_stats_stop,       STATS_STATE_DISABLED}
3961 }
3962 };
3963
3964 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
3965 {
3966         enum bnx2x_stats_state state = bp->stats_state;
3967
3968         bnx2x_stats_stm[state][event].action(bp);
3969         bp->stats_state = bnx2x_stats_stm[state][event].next_state;
3970
3971         if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
3972                 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
3973                    state, event, bp->stats_state);
3974 }
3975
3976 static void bnx2x_timer(unsigned long data)
3977 {
3978         struct bnx2x *bp = (struct bnx2x *) data;
3979
3980         if (!netif_running(bp->dev))
3981                 return;
3982
3983         if (atomic_read(&bp->intr_sem) != 0)
3984                 goto timer_restart;
3985
3986         if (poll) {
3987                 struct bnx2x_fastpath *fp = &bp->fp[0];
3988                 int rc;
3989
3990                 bnx2x_tx_int(fp, 1000);
3991                 rc = bnx2x_rx_int(fp, 1000);
3992         }
3993
3994         if (!BP_NOMCP(bp)) {
3995                 int func = BP_FUNC(bp);
3996                 u32 drv_pulse;
3997                 u32 mcp_pulse;
3998
3999                 ++bp->fw_drv_pulse_wr_seq;
4000                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4001                 /* TBD - add SYSTEM_TIME */
4002                 drv_pulse = bp->fw_drv_pulse_wr_seq;
4003                 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
4004
4005                 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
4006                              MCP_PULSE_SEQ_MASK);
4007                 /* The delta between driver pulse and mcp response
4008                  * should be 1 (before mcp response) or 0 (after mcp response)
4009                  */
4010                 if ((drv_pulse != mcp_pulse) &&
4011                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4012                         /* someone lost a heartbeat... */
4013                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4014                                   drv_pulse, mcp_pulse);
4015                 }
4016         }
4017
4018         if ((bp->state == BNX2X_STATE_OPEN) ||
4019             (bp->state == BNX2X_STATE_DISABLED))
4020                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4021
4022 timer_restart:
4023         mod_timer(&bp->timer, jiffies + bp->current_interval);
4024 }
4025
4026 /* end of Statistics */
4027
4028 /* nic init */
4029
4030 /*
4031  * nic init service functions
4032  */
4033
4034 static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
4035 {
4036         int port = BP_PORT(bp);
4037
4038         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4039                         USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4040                         sizeof(struct ustorm_status_block)/4);
4041         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4042                         CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4043                         sizeof(struct cstorm_status_block)/4);
4044 }
4045
4046 static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4047                           dma_addr_t mapping, int sb_id)
4048 {
4049         int port = BP_PORT(bp);
4050         int func = BP_FUNC(bp);
4051         int index;
4052         u64 section;
4053
4054         /* USTORM */
4055         section = ((u64)mapping) + offsetof(struct host_status_block,
4056                                             u_status_block);
4057         sb->u_status_block.status_block_id = sb_id;
4058
4059         REG_WR(bp, BAR_USTRORM_INTMEM +
4060                USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4061         REG_WR(bp, BAR_USTRORM_INTMEM +
4062                ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4063                U64_HI(section));
4064         REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
4065                 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4066
4067         for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4068                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4069                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4070
4071         /* CSTORM */
4072         section = ((u64)mapping) + offsetof(struct host_status_block,
4073                                             c_status_block);
4074         sb->c_status_block.status_block_id = sb_id;
4075
4076         REG_WR(bp, BAR_CSTRORM_INTMEM +
4077                CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4078         REG_WR(bp, BAR_CSTRORM_INTMEM +
4079                ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4080                U64_HI(section));
4081         REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
4082                 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4083
4084         for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4085                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4086                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4087
4088         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4089 }
4090
4091 static void bnx2x_zero_def_sb(struct bnx2x *bp)
4092 {
4093         int func = BP_FUNC(bp);
4094
4095         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4096                         USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4097                         sizeof(struct ustorm_def_status_block)/4);
4098         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4099                         CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4100                         sizeof(struct cstorm_def_status_block)/4);
4101         bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
4102                         XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4103                         sizeof(struct xstorm_def_status_block)/4);
4104         bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4105                         TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4106                         sizeof(struct tstorm_def_status_block)/4);
4107 }
4108
4109 static void bnx2x_init_def_sb(struct bnx2x *bp,
4110                               struct host_def_status_block *def_sb,
4111                               dma_addr_t mapping, int sb_id)
4112 {
4113         int port = BP_PORT(bp);
4114         int func = BP_FUNC(bp);
4115         int index, val, reg_offset;
4116         u64 section;
4117
4118         /* ATTN */
4119         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4120                                             atten_status_block);
4121         def_sb->atten_status_block.status_block_id = sb_id;
4122
4123         bp->attn_state = 0;
4124
4125         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4126                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4127
4128         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4129                 bp->attn_group[index].sig[0] = REG_RD(bp,
4130                                                      reg_offset + 0x10*index);
4131                 bp->attn_group[index].sig[1] = REG_RD(bp,
4132                                                reg_offset + 0x4 + 0x10*index);
4133                 bp->attn_group[index].sig[2] = REG_RD(bp,
4134                                                reg_offset + 0x8 + 0x10*index);
4135                 bp->attn_group[index].sig[3] = REG_RD(bp,
4136                                                reg_offset + 0xc + 0x10*index);
4137         }
4138
4139         reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4140                              HC_REG_ATTN_MSG0_ADDR_L);
4141
4142         REG_WR(bp, reg_offset, U64_LO(section));
4143         REG_WR(bp, reg_offset + 4, U64_HI(section));
4144
4145         reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4146
4147         val = REG_RD(bp, reg_offset);
4148         val |= sb_id;
4149         REG_WR(bp, reg_offset, val);
4150
4151         /* USTORM */
4152         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4153                                             u_def_status_block);
4154         def_sb->u_def_status_block.status_block_id = sb_id;
4155
4156         REG_WR(bp, BAR_USTRORM_INTMEM +
4157                USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4158         REG_WR(bp, BAR_USTRORM_INTMEM +
4159                ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4160                U64_HI(section));
4161         REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4162                 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4163
4164         for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4165                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4166                          USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4167
4168         /* CSTORM */
4169         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4170                                             c_def_status_block);
4171         def_sb->c_def_status_block.status_block_id = sb_id;
4172
4173         REG_WR(bp, BAR_CSTRORM_INTMEM +
4174                CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4175         REG_WR(bp, BAR_CSTRORM_INTMEM +
4176                ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4177                U64_HI(section));
4178         REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4179                 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4180
4181         for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4182                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4183                          CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4184
4185         /* TSTORM */
4186         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4187                                             t_def_status_block);
4188         def_sb->t_def_status_block.status_block_id = sb_id;
4189
4190         REG_WR(bp, BAR_TSTRORM_INTMEM +
4191                TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4192         REG_WR(bp, BAR_TSTRORM_INTMEM +
4193                ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4194                U64_HI(section));
4195         REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4196                 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4197
4198         for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4199                 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4200                          TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4201
4202         /* XSTORM */
4203         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4204                                             x_def_status_block);
4205         def_sb->x_def_status_block.status_block_id = sb_id;
4206
4207         REG_WR(bp, BAR_XSTRORM_INTMEM +
4208                XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4209         REG_WR(bp, BAR_XSTRORM_INTMEM +
4210                ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4211                U64_HI(section));
4212         REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4213                 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4214
4215         for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4216                 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4217                          XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4218
4219         bp->stats_pending = 0;
4220         bp->set_mac_pending = 0;
4221
4222         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4223 }
4224
4225 static void bnx2x_update_coalesce(struct bnx2x *bp)
4226 {
4227         int port = BP_PORT(bp);
4228         int i;
4229
4230         for_each_queue(bp, i) {
4231                 int sb_id = bp->fp[i].sb_id;
4232
4233                 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4234                 REG_WR8(bp, BAR_USTRORM_INTMEM +
4235                         USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4236                                                     U_SB_ETH_RX_CQ_INDEX),
4237                         bp->rx_ticks/12);
4238                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4239                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4240                                                      U_SB_ETH_RX_CQ_INDEX),
4241                          bp->rx_ticks ? 0 : 1);
4242                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4243                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4244                                                      U_SB_ETH_RX_BD_INDEX),
4245                          bp->rx_ticks ? 0 : 1);
4246
4247                 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4248                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4249                         CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4250                                                     C_SB_ETH_TX_CQ_INDEX),
4251                         bp->tx_ticks/12);
4252                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4253                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4254                                                      C_SB_ETH_TX_CQ_INDEX),
4255                          bp->tx_ticks ? 0 : 1);
4256         }
4257 }
4258
4259 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4260                                        struct bnx2x_fastpath *fp, int last)
4261 {
4262         int i;
4263
4264         for (i = 0; i < last; i++) {
4265                 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
4266                 struct sk_buff *skb = rx_buf->skb;
4267
4268                 if (skb == NULL) {
4269                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
4270                         continue;
4271                 }
4272
4273                 if (fp->tpa_state[i] == BNX2X_TPA_START)
4274                         pci_unmap_single(bp->pdev,
4275                                          pci_unmap_addr(rx_buf, mapping),
4276                                          bp->rx_buf_size,
4277                                          PCI_DMA_FROMDEVICE);
4278
4279                 dev_kfree_skb(skb);
4280                 rx_buf->skb = NULL;
4281         }
4282 }
4283
4284 static void bnx2x_init_rx_rings(struct bnx2x *bp)
4285 {
4286         int func = BP_FUNC(bp);
4287         int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4288                                               ETH_MAX_AGGREGATION_QUEUES_E1H;
4289         u16 ring_prod, cqe_ring_prod;
4290         int i, j;
4291
4292         bp->rx_buf_size = bp->dev->mtu;
4293         bp->rx_buf_size += bp->rx_offset + ETH_OVREHEAD +
4294                 BCM_RX_ETH_PAYLOAD_ALIGN;
4295
4296         if (bp->flags & TPA_ENABLE_FLAG) {
4297                 DP(NETIF_MSG_IFUP,
4298                    "rx_buf_size %d  effective_mtu %d\n",
4299                    bp->rx_buf_size, bp->dev->mtu + ETH_OVREHEAD);
4300
4301                 for_each_queue(bp, j) {
4302                         struct bnx2x_fastpath *fp = &bp->fp[j];
4303
4304                         for (i = 0; i < max_agg_queues; i++) {
4305                                 fp->tpa_pool[i].skb =
4306                                    netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4307                                 if (!fp->tpa_pool[i].skb) {
4308                                         BNX2X_ERR("Failed to allocate TPA "
4309                                                   "skb pool for queue[%d] - "
4310                                                   "disabling TPA on this "
4311                                                   "queue!\n", j);
4312                                         bnx2x_free_tpa_pool(bp, fp, i);
4313                                         fp->disable_tpa = 1;
4314                                         break;
4315                                 }
4316                                 pci_unmap_addr_set((struct sw_rx_bd *)
4317                                                         &bp->fp->tpa_pool[i],
4318                                                    mapping, 0);
4319                                 fp->tpa_state[i] = BNX2X_TPA_STOP;
4320                         }
4321                 }
4322         }
4323
4324         for_each_queue(bp, j) {
4325                 struct bnx2x_fastpath *fp = &bp->fp[j];
4326
4327                 fp->rx_bd_cons = 0;
4328                 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4329                 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
4330
4331                 /* "next page" elements initialization */
4332                 /* SGE ring */
4333                 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
4334                         struct eth_rx_sge *sge;
4335
4336                         sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
4337                         sge->addr_hi =
4338                                 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
4339                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4340                         sge->addr_lo =
4341                                 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
4342                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4343                 }
4344
4345                 bnx2x_init_sge_ring_bit_mask(fp);
4346
4347                 /* RX BD ring */
4348                 for (i = 1; i <= NUM_RX_RINGS; i++) {
4349                         struct eth_rx_bd *rx_bd;
4350
4351                         rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4352                         rx_bd->addr_hi =
4353                                 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4354                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4355                         rx_bd->addr_lo =
4356                                 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4357                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4358                 }
4359
4360                 /* CQ ring */
4361                 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4362                         struct eth_rx_cqe_next_page *nextpg;
4363
4364                         nextpg = (struct eth_rx_cqe_next_page *)
4365                                 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4366                         nextpg->addr_hi =
4367                                 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4368                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4369                         nextpg->addr_lo =
4370                                 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4371                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4372                 }
4373
4374                 /* Allocate SGEs and initialize the ring elements */
4375                 for (i = 0, ring_prod = 0;
4376                      i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4377
4378                         if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
4379                                 BNX2X_ERR("was only able to allocate "
4380                                           "%d rx sges\n", i);
4381                                 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4382                                 /* Cleanup already allocated elements */
4383                                 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4384                                 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4385                                 fp->disable_tpa = 1;
4386                                 ring_prod = 0;
4387                                 break;
4388                         }
4389                         ring_prod = NEXT_SGE_IDX(ring_prod);
4390                 }
4391                 fp->rx_sge_prod = ring_prod;
4392
4393                 /* Allocate BDs and initialize BD ring */
4394                 fp->rx_comp_cons = 0;
4395                 cqe_ring_prod = ring_prod = 0;
4396                 for (i = 0; i < bp->rx_ring_size; i++) {
4397                         if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4398                                 BNX2X_ERR("was only able to allocate "
4399                                           "%d rx skbs\n", i);
4400                                 bp->eth_stats.rx_skb_alloc_failed++;
4401                                 break;
4402                         }
4403                         ring_prod = NEXT_RX_IDX(ring_prod);
4404                         cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4405                         WARN_ON(ring_prod <= i);
4406                 }
4407
4408                 fp->rx_bd_prod = ring_prod;
4409                 /* must not have more available CQEs than BDs */
4410                 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
4411                                        cqe_ring_prod);
4412                 fp->rx_pkt = fp->rx_calls = 0;
4413
4414                 /* Warning!
4415                  * this will generate an interrupt (to the TSTORM)
4416                  * must only be done after chip is initialized
4417                  */
4418                 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
4419                                      fp->rx_sge_prod);
4420                 if (j != 0)
4421                         continue;
4422
4423                 REG_WR(bp, BAR_USTRORM_INTMEM +
4424                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
4425                        U64_LO(fp->rx_comp_mapping));
4426                 REG_WR(bp, BAR_USTRORM_INTMEM +
4427                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
4428                        U64_HI(fp->rx_comp_mapping));
4429         }
4430 }
4431
4432 static void bnx2x_init_tx_ring(struct bnx2x *bp)
4433 {
4434         int i, j;
4435
4436         for_each_queue(bp, j) {
4437                 struct bnx2x_fastpath *fp = &bp->fp[j];
4438
4439                 for (i = 1; i <= NUM_TX_RINGS; i++) {
4440                         struct eth_tx_bd *tx_bd =
4441                                 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4442
4443                         tx_bd->addr_hi =
4444                                 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4445                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4446                         tx_bd->addr_lo =
4447                                 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4448                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4449                 }
4450
4451                 fp->tx_pkt_prod = 0;
4452                 fp->tx_pkt_cons = 0;
4453                 fp->tx_bd_prod = 0;
4454                 fp->tx_bd_cons = 0;
4455                 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4456                 fp->tx_pkt = 0;
4457         }
4458 }
4459
4460 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4461 {
4462         int func = BP_FUNC(bp);
4463
4464         spin_lock_init(&bp->spq_lock);
4465
4466         bp->spq_left = MAX_SPQ_PENDING;
4467         bp->spq_prod_idx = 0;
4468         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4469         bp->spq_prod_bd = bp->spq;
4470         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4471
4472         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4473                U64_LO(bp->spq_mapping));
4474         REG_WR(bp,
4475                XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
4476                U64_HI(bp->spq_mapping));
4477
4478         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
4479                bp->spq_prod_idx);
4480 }
4481
4482 static void bnx2x_init_context(struct bnx2x *bp)
4483 {
4484         int i;
4485
4486         for_each_queue(bp, i) {
4487                 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4488                 struct bnx2x_fastpath *fp = &bp->fp[i];
4489                 u8 sb_id = FP_SB_ID(fp);
4490
4491                 context->xstorm_st_context.tx_bd_page_base_hi =
4492                                                 U64_HI(fp->tx_desc_mapping);
4493                 context->xstorm_st_context.tx_bd_page_base_lo =
4494                                                 U64_LO(fp->tx_desc_mapping);
4495                 context->xstorm_st_context.db_data_addr_hi =
4496                                                 U64_HI(fp->tx_prods_mapping);
4497                 context->xstorm_st_context.db_data_addr_lo =
4498                                                 U64_LO(fp->tx_prods_mapping);
4499                 context->xstorm_st_context.statistics_data = (BP_CL_ID(bp) |
4500                                 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
4501
4502                 context->ustorm_st_context.common.sb_index_numbers =
4503                                                 BNX2X_RX_SB_INDEX_NUM;
4504                 context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
4505                 context->ustorm_st_context.common.status_block_id = sb_id;
4506                 context->ustorm_st_context.common.flags =
4507                         USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
4508                 context->ustorm_st_context.common.mc_alignment_size =
4509                         BCM_RX_ETH_PAYLOAD_ALIGN;
4510                 context->ustorm_st_context.common.bd_buff_size =
4511                                                 bp->rx_buf_size;
4512                 context->ustorm_st_context.common.bd_page_base_hi =
4513                                                 U64_HI(fp->rx_desc_mapping);
4514                 context->ustorm_st_context.common.bd_page_base_lo =
4515                                                 U64_LO(fp->rx_desc_mapping);
4516                 if (!fp->disable_tpa) {
4517                         context->ustorm_st_context.common.flags |=
4518                                 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
4519                                  USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
4520                         context->ustorm_st_context.common.sge_buff_size =
4521                                         (u16)(BCM_PAGE_SIZE*PAGES_PER_SGE);
4522                         context->ustorm_st_context.common.sge_page_base_hi =
4523                                                 U64_HI(fp->rx_sge_mapping);
4524                         context->ustorm_st_context.common.sge_page_base_lo =
4525                                                 U64_LO(fp->rx_sge_mapping);
4526                 }
4527
4528                 context->cstorm_st_context.sb_index_number =
4529                                                 C_SB_ETH_TX_CQ_INDEX;
4530                 context->cstorm_st_context.status_block_id = sb_id;
4531
4532                 context->xstorm_ag_context.cdu_reserved =
4533                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4534                                                CDU_REGION_NUMBER_XCM_AG,
4535                                                ETH_CONNECTION_TYPE);
4536                 context->ustorm_ag_context.cdu_usage =
4537                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4538                                                CDU_REGION_NUMBER_UCM_AG,
4539                                                ETH_CONNECTION_TYPE);
4540         }
4541 }
4542
4543 static void bnx2x_init_ind_table(struct bnx2x *bp)
4544 {
4545         int func = BP_FUNC(bp);
4546         int i;
4547
4548         if (!is_multi(bp))
4549                 return;
4550
4551         DP(NETIF_MSG_IFUP, "Initializing indirection table\n");
4552         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4553                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4554                         TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4555                         BP_CL_ID(bp) + (i % bp->num_queues));
4556 }
4557
4558 static void bnx2x_set_client_config(struct bnx2x *bp)
4559 {
4560         struct tstorm_eth_client_config tstorm_client = {0};
4561         int port = BP_PORT(bp);
4562         int i;
4563
4564         tstorm_client.mtu = bp->dev->mtu;
4565         tstorm_client.statistics_counter_id = BP_CL_ID(bp);
4566         tstorm_client.config_flags =
4567                                 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
4568 #ifdef BCM_VLAN
4569         if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
4570                 tstorm_client.config_flags |=
4571                                 TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;
4572                 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4573         }
4574 #endif
4575
4576         if (bp->flags & TPA_ENABLE_FLAG) {
4577                 tstorm_client.max_sges_for_packet =
4578                         SGE_PAGE_ALIGN(tstorm_client.mtu) >> SGE_PAGE_SHIFT;
4579                 tstorm_client.max_sges_for_packet =
4580                         ((tstorm_client.max_sges_for_packet +
4581                           PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
4582                         PAGES_PER_SGE_SHIFT;
4583
4584                 tstorm_client.config_flags |=
4585                                 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
4586         }
4587
4588         for_each_queue(bp, i) {
4589                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4590                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
4591                        ((u32 *)&tstorm_client)[0]);
4592                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4593                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
4594                        ((u32 *)&tstorm_client)[1]);
4595         }
4596
4597         DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
4598            ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
4599 }
4600
4601 static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4602 {
4603         struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4604         int mode = bp->rx_mode;
4605         int mask = (1 << BP_L_ID(bp));
4606         int func = BP_FUNC(bp);
4607         int i;
4608
4609         DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
4610
4611         switch (mode) {
4612         case BNX2X_RX_MODE_NONE: /* no Rx */
4613                 tstorm_mac_filter.ucast_drop_all = mask;
4614                 tstorm_mac_filter.mcast_drop_all = mask;
4615                 tstorm_mac_filter.bcast_drop_all = mask;
4616                 break;
4617         case BNX2X_RX_MODE_NORMAL:
4618                 tstorm_mac_filter.bcast_accept_all = mask;
4619                 break;
4620         case BNX2X_RX_MODE_ALLMULTI:
4621                 tstorm_mac_filter.mcast_accept_all = mask;
4622                 tstorm_mac_filter.bcast_accept_all = mask;
4623                 break;
4624         case BNX2X_RX_MODE_PROMISC:
4625                 tstorm_mac_filter.ucast_accept_all = mask;
4626                 tstorm_mac_filter.mcast_accept_all = mask;
4627                 tstorm_mac_filter.bcast_accept_all = mask;
4628                 break;
4629         default:
4630                 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4631                 break;
4632         }
4633
4634         for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4635                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4636                        TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
4637                        ((u32 *)&tstorm_mac_filter)[i]);
4638
4639 /*              DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4640                    ((u32 *)&tstorm_mac_filter)[i]); */
4641         }
4642
4643         if (mode != BNX2X_RX_MODE_NONE)
4644                 bnx2x_set_client_config(bp);
4645 }
4646
4647 static void bnx2x_init_internal_common(struct bnx2x *bp)
4648 {
4649         int i;
4650
4651         if (bp->flags & TPA_ENABLE_FLAG) {
4652                 struct tstorm_eth_tpa_exist tpa = {0};
4653
4654                 tpa.tpa_exist = 1;
4655
4656                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
4657                        ((u32 *)&tpa)[0]);
4658                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
4659                        ((u32 *)&tpa)[1]);
4660         }
4661
4662         /* Zero this manually as its initialization is
4663            currently missing in the initTool */
4664         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4665                 REG_WR(bp, BAR_USTRORM_INTMEM +
4666                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
4667 }
4668
4669 static void bnx2x_init_internal_port(struct bnx2x *bp)
4670 {
4671         int port = BP_PORT(bp);
4672
4673         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4674         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4675         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4676         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4677 }
4678
4679 static void bnx2x_init_internal_func(struct bnx2x *bp)
4680 {
4681         struct tstorm_eth_function_common_config tstorm_config = {0};
4682         struct stats_indication_flags stats_flags = {0};
4683         int port = BP_PORT(bp);
4684         int func = BP_FUNC(bp);
4685         int i;
4686         u16 max_agg_size;
4687
4688         if (is_multi(bp)) {
4689                 tstorm_config.config_flags = MULTI_FLAGS;
4690                 tstorm_config.rss_result_mask = MULTI_MASK;
4691         }
4692
4693         tstorm_config.leading_client_id = BP_L_ID(bp);
4694
4695         REG_WR(bp, BAR_TSTRORM_INTMEM +
4696                TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4697                (*(u32 *)&tstorm_config));
4698
4699         bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4700         bnx2x_set_storm_rx_mode(bp);
4701
4702         /* reset xstorm per client statistics */
4703         for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) {
4704                 REG_WR(bp, BAR_XSTRORM_INTMEM +
4705                        XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4706                        i*4, 0);
4707         }
4708         /* reset tstorm per client statistics */
4709         for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) {
4710                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4711                        TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4712                        i*4, 0);
4713         }
4714
4715         /* Init statistics related context */
4716         stats_flags.collect_eth = 1;
4717
4718         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4719                ((u32 *)&stats_flags)[0]);
4720         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4721                ((u32 *)&stats_flags)[1]);
4722
4723         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4724                ((u32 *)&stats_flags)[0]);
4725         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4726                ((u32 *)&stats_flags)[1]);
4727
4728         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4729                ((u32 *)&stats_flags)[0]);
4730         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4731                ((u32 *)&stats_flags)[1]);
4732
4733         REG_WR(bp, BAR_XSTRORM_INTMEM +
4734                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4735                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4736         REG_WR(bp, BAR_XSTRORM_INTMEM +
4737                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4738                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4739
4740         REG_WR(bp, BAR_TSTRORM_INTMEM +
4741                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4742                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4743         REG_WR(bp, BAR_TSTRORM_INTMEM +
4744                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4745                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4746
4747         if (CHIP_IS_E1H(bp)) {
4748                 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4749                         IS_E1HMF(bp));
4750                 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4751                         IS_E1HMF(bp));
4752                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4753                         IS_E1HMF(bp));
4754                 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4755                         IS_E1HMF(bp));
4756
4757                 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
4758                          bp->e1hov);
4759         }
4760
4761         /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
4762         max_agg_size =
4763                 min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) *
4764                           SGE_PAGE_SIZE * PAGES_PER_SGE),
4765                     (u32)0xffff);
4766         for_each_queue(bp, i) {
4767                 struct bnx2x_fastpath *fp = &bp->fp[i];
4768
4769                 REG_WR(bp, BAR_USTRORM_INTMEM +
4770                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
4771                        U64_LO(fp->rx_comp_mapping));
4772                 REG_WR(bp, BAR_USTRORM_INTMEM +
4773                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4774                        U64_HI(fp->rx_comp_mapping));
4775
4776                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4777                          USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4778                          max_agg_size);
4779         }
4780 }
4781
4782 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4783 {
4784         switch (load_code) {
4785         case FW_MSG_CODE_DRV_LOAD_COMMON:
4786                 bnx2x_init_internal_common(bp);
4787                 /* no break */
4788
4789         case FW_MSG_CODE_DRV_LOAD_PORT:
4790                 bnx2x_init_internal_port(bp);
4791                 /* no break */
4792
4793         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4794                 bnx2x_init_internal_func(bp);
4795                 break;
4796
4797         default:
4798                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4799                 break;
4800         }
4801 }
4802
4803 static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4804 {
4805         int i;
4806
4807         for_each_queue(bp, i) {
4808                 struct bnx2x_fastpath *fp = &bp->fp[i];
4809
4810                 fp->bp = bp;
4811                 fp->state = BNX2X_FP_STATE_CLOSED;
4812                 fp->index = i;
4813                 fp->cl_id = BP_L_ID(bp) + i;
4814                 fp->sb_id = fp->cl_id;
4815                 DP(NETIF_MSG_IFUP,
4816                    "bnx2x_init_sb(%p,%p) index %d  cl_id %d  sb %d\n",
4817                    bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
4818                 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
4819                               FP_SB_ID(fp));
4820                 bnx2x_update_fpsb_idx(fp);
4821         }
4822
4823         bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
4824                           DEF_SB_ID);
4825         bnx2x_update_dsb_idx(bp);
4826         bnx2x_update_coalesce(bp);
4827         bnx2x_init_rx_rings(bp);
4828         bnx2x_init_tx_ring(bp);
4829         bnx2x_init_sp_ring(bp);
4830         bnx2x_init_context(bp);
4831         bnx2x_init_internal(bp, load_code);
4832         bnx2x_init_ind_table(bp);
4833         bnx2x_stats_init(bp);
4834
4835         /* At this point, we are ready for interrupts */
4836         atomic_set(&bp->intr_sem, 0);
4837
4838         /* flush all before enabling interrupts */
4839         mb();
4840         mmiowb();
4841
4842         bnx2x_int_enable(bp);
4843 }
4844
4845 /* end of nic init */
4846
4847 /*
4848  * gzip service functions
4849  */
4850
4851 static int bnx2x_gunzip_init(struct bnx2x *bp)
4852 {
4853         bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
4854                                               &bp->gunzip_mapping);
4855         if (bp->gunzip_buf  == NULL)
4856                 goto gunzip_nomem1;
4857
4858         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4859         if (bp->strm  == NULL)
4860                 goto gunzip_nomem2;
4861
4862         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4863                                       GFP_KERNEL);
4864         if (bp->strm->workspace == NULL)
4865                 goto gunzip_nomem3;
4866
4867         return 0;
4868
4869 gunzip_nomem3:
4870         kfree(bp->strm);
4871         bp->strm = NULL;
4872
4873 gunzip_nomem2:
4874         pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4875                             bp->gunzip_mapping);
4876         bp->gunzip_buf = NULL;
4877
4878 gunzip_nomem1:
4879         printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
4880                " un-compression\n", bp->dev->name);
4881         return -ENOMEM;
4882 }
4883
4884 static void bnx2x_gunzip_end(struct bnx2x *bp)
4885 {
4886         kfree(bp->strm->workspace);
4887
4888         kfree(bp->strm);
4889         bp->strm = NULL;
4890
4891         if (bp->gunzip_buf) {
4892                 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4893                                     bp->gunzip_mapping);
4894                 bp->gunzip_buf = NULL;
4895         }
4896 }
4897
4898 static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
4899 {
4900         int n, rc;
4901
4902         /* check gzip header */
4903         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
4904                 return -EINVAL;
4905
4906         n = 10;
4907
4908 #define FNAME                           0x8
4909
4910         if (zbuf[3] & FNAME)
4911                 while ((zbuf[n++] != 0) && (n < len));
4912
4913         bp->strm->next_in = zbuf + n;
4914         bp->strm->avail_in = len - n;
4915         bp->strm->next_out = bp->gunzip_buf;
4916         bp->strm->avail_out = FW_BUF_SIZE;
4917
4918         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4919         if (rc != Z_OK)
4920                 return rc;
4921
4922         rc = zlib_inflate(bp->strm, Z_FINISH);
4923         if ((rc != Z_OK) && (rc != Z_STREAM_END))
4924                 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
4925                        bp->dev->name, bp->strm->msg);
4926
4927         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4928         if (bp->gunzip_outlen & 0x3)
4929                 printk(KERN_ERR PFX "%s: Firmware decompression error:"
4930                                     " gunzip_outlen (%d) not aligned\n",
4931                        bp->dev->name, bp->gunzip_outlen);
4932         bp->gunzip_outlen >>= 2;
4933
4934         zlib_inflateEnd(bp->strm);
4935
4936         if (rc == Z_STREAM_END)
4937                 return 0;
4938
4939         return rc;
4940 }
4941
4942 /* nic load/unload */
4943
4944 /*
4945  * General service functions
4946  */
4947
4948 /* send a NIG loopback debug packet */
4949 static void bnx2x_lb_pckt(struct bnx2x *bp)
4950 {
4951         u32 wb_write[3];
4952
4953         /* Ethernet source and destination addresses */
4954         wb_write[0] = 0x55555555;
4955         wb_write[1] = 0x55555555;
4956         wb_write[2] = 0x20;             /* SOP */
4957         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4958
4959         /* NON-IP protocol */
4960         wb_write[0] = 0x09000000;
4961         wb_write[1] = 0x55555555;
4962         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
4963         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4964 }
4965
4966 /* some of the internal memories
4967  * are not directly readable from the driver
4968  * to test them we send debug packets
4969  */
4970 static int bnx2x_int_mem_test(struct bnx2x *bp)
4971 {
4972         int factor;
4973         int count, i;
4974         u32 val = 0;
4975
4976         if (CHIP_REV_IS_FPGA(bp))
4977                 factor = 120;
4978         else if (CHIP_REV_IS_EMUL(bp))
4979                 factor = 200;
4980         else
4981                 factor = 1;
4982
4983         DP(NETIF_MSG_HW, "start part1\n");
4984
4985         /* Disable inputs of parser neighbor blocks */
4986         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4987         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4988         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4989         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4990
4991         /*  Write 0 to parser credits for CFC search request */
4992         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4993
4994         /* send Ethernet packet */
4995         bnx2x_lb_pckt(bp);
4996
4997         /* TODO do i reset NIG statistic? */
4998         /* Wait until NIG register shows 1 packet of size 0x10 */
4999         count = 1000 * factor;
5000         while (count) {
5001
5002                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5003                 val = *bnx2x_sp(bp, wb_data[0]);
5004                 if (val == 0x10)
5005                         break;
5006
5007                 msleep(10);
5008                 count--;
5009         }
5010         if (val != 0x10) {
5011                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5012                 return -1;
5013         }
5014
5015         /* Wait until PRS register shows 1 packet */
5016         count = 1000 * factor;
5017         while (count) {
5018                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5019                 if (val == 1)
5020                         break;
5021
5022                 msleep(10);
5023                 count--;
5024         }
5025         if (val != 0x1) {
5026                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5027                 return -2;
5028         }
5029
5030         /* Reset and init BRB, PRS */
5031         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5032         msleep(50);
5033         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5034         msleep(50);
5035         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5036         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5037
5038         DP(NETIF_MSG_HW, "part2\n");
5039
5040         /* Disable inputs of parser neighbor blocks */
5041         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5042         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5043         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5044         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5045
5046         /* Write 0 to parser credits for CFC search request */
5047         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5048
5049         /* send 10 Ethernet packets */
5050         for (i = 0; i < 10; i++)
5051                 bnx2x_lb_pckt(bp);
5052
5053         /* Wait until NIG register shows 10 + 1
5054            packets of size 11*0x10 = 0xb0 */
5055         count = 1000 * factor;
5056         while (count) {
5057
5058                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5059                 val = *bnx2x_sp(bp, wb_data[0]);
5060                 if (val == 0xb0)
5061                         break;
5062
5063                 msleep(10);
5064                 count--;
5065         }
5066         if (val != 0xb0) {
5067                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5068                 return -3;
5069         }
5070
5071         /* Wait until PRS register shows 2 packets */
5072         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5073         if (val != 2)
5074                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5075
5076         /* Write 1 to parser credits for CFC search request */
5077         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5078
5079         /* Wait until PRS register shows 3 packets */
5080         msleep(10 * factor);
5081         /* Wait until NIG register shows 1 packet of size 0x10 */
5082         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5083         if (val != 3)
5084                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5085
5086         /* clear NIG EOP FIFO */
5087         for (i = 0; i < 11; i++)
5088                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5089         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5090         if (val != 1) {
5091                 BNX2X_ERR("clear of NIG failed\n");
5092                 return -4;
5093         }
5094
5095         /* Reset and init BRB, PRS, NIG */
5096         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5097         msleep(50);
5098         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5099         msleep(50);
5100         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5101         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5102 #ifndef BCM_ISCSI
5103         /* set NIC mode */
5104         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5105 #endif
5106
5107         /* Enable inputs of parser neighbor blocks */
5108         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5109         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5110         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5111         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5112
5113         DP(NETIF_MSG_HW, "done\n");
5114
5115         return 0; /* OK */
5116 }
5117
5118 static void enable_blocks_attention(struct bnx2x *bp)
5119 {
5120         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5121         REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5122         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5123         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5124         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5125         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5126         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5127         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5128         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5129 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5130 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5131         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5132         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5133         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5134 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5135 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5136         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5137         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5138         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5139         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5140 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5141 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5142         if (CHIP_REV_IS_FPGA(bp))
5143                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5144         else
5145                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5146         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5147         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5148         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5149 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5150 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5151         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5152         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5153 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5154         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
5155 }
5156
5157
5158 static void bnx2x_reset_common(struct bnx2x *bp)
5159 {
5160         /* reset_common */
5161         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5162                0xd3ffff7f);
5163         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
5164 }
5165
5166 static int bnx2x_init_common(struct bnx2x *bp)
5167 {
5168         u32 val, i;
5169
5170         DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_FUNC(bp));
5171
5172         bnx2x_reset_common(bp);
5173         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5174         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5175
5176         bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
5177         if (CHIP_IS_E1H(bp))
5178                 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5179
5180         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5181         msleep(30);
5182         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5183
5184         bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
5185         if (CHIP_IS_E1(bp)) {
5186                 /* enable HW interrupt from PXP on USDM overflow
5187                    bit 16 on INT_MASK_0 */
5188                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5189         }
5190
5191         bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
5192         bnx2x_init_pxp(bp);
5193
5194 #ifdef __BIG_ENDIAN
5195         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5196         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5197         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5198         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5199         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5200
5201 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5202         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5203         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5204         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5205         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5206 #endif
5207
5208         REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5209 #ifdef BCM_ISCSI
5210         REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5211         REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5212         REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5213 #endif
5214
5215         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5216                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5217
5218         /* let the HW do it's magic ... */
5219         msleep(100);
5220         /* finish PXP init */
5221         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5222         if (val != 1) {
5223                 BNX2X_ERR("PXP2 CFG failed\n");
5224                 return -EBUSY;
5225         }
5226         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5227         if (val != 1) {
5228                 BNX2X_ERR("PXP2 RD_INIT failed\n");
5229                 return -EBUSY;
5230         }
5231
5232         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5233         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5234
5235         bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
5236
5237         /* clean the DMAE memory */
5238         bp->dmae_ready = 1;
5239         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5240
5241         bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
5242         bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
5243         bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
5244         bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
5245
5246         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5247         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5248         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5249         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5250
5251         bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5252         /* soft reset pulse */
5253         REG_WR(bp, QM_REG_SOFT_RESET, 1);
5254         REG_WR(bp, QM_REG_SOFT_RESET, 0);
5255
5256 #ifdef BCM_ISCSI
5257         bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
5258 #endif
5259
5260         bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
5261         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
5262         if (!CHIP_REV_IS_SLOW(bp)) {
5263                 /* enable hw interrupt from doorbell Q */
5264                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5265         }
5266
5267         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5268         if (CHIP_REV_IS_SLOW(bp)) {
5269                 /* fix for emulation and FPGA for no pause */
5270                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
5271                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
5272                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
5273                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
5274         }
5275
5276         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5277         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5278         /* set NIC mode */
5279         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5280         if (CHIP_IS_E1H(bp))
5281                 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5282
5283         bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
5284         bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
5285         bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5286         bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5287
5288         if (CHIP_IS_E1H(bp)) {
5289                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5290                                 STORM_INTMEM_SIZE_E1H/2);
5291                 bnx2x_init_fill(bp,
5292                                 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5293                                 0, STORM_INTMEM_SIZE_E1H/2);
5294                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5295                                 STORM_INTMEM_SIZE_E1H/2);
5296                 bnx2x_init_fill(bp,
5297                                 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5298                                 0, STORM_INTMEM_SIZE_E1H/2);
5299                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5300                                 STORM_INTMEM_SIZE_E1H/2);
5301                 bnx2x_init_fill(bp,
5302                                 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5303                                 0, STORM_INTMEM_SIZE_E1H/2);
5304                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5305                                 STORM_INTMEM_SIZE_E1H/2);
5306                 bnx2x_init_fill(bp,
5307                                 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5308                                 0, STORM_INTMEM_SIZE_E1H/2);
5309         } else { /* E1 */
5310                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5311                                 STORM_INTMEM_SIZE_E1);
5312                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5313                                 STORM_INTMEM_SIZE_E1);
5314                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5315                                 STORM_INTMEM_SIZE_E1);
5316                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5317                                 STORM_INTMEM_SIZE_E1);
5318         }
5319
5320         bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5321         bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
5322         bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
5323         bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
5324
5325         /* sync semi rtc */
5326         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5327                0x80000000);
5328         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5329                0x80000000);
5330
5331         bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
5332         bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
5333         bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
5334
5335         REG_WR(bp, SRC_REG_SOFT_RST, 1);
5336         for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5337                 REG_WR(bp, i, 0xc0cac01a);
5338                 /* TODO: replace with something meaningful */
5339         }
5340         if (CHIP_IS_E1H(bp))
5341                 bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
5342         REG_WR(bp, SRC_REG_SOFT_RST, 0);
5343
5344         if (sizeof(union cdu_context) != 1024)
5345                 /* we currently assume that a context is 1024 bytes */
5346                 printk(KERN_ALERT PFX "please adjust the size of"
5347                        " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5348
5349         bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
5350         val = (4 << 24) + (0 << 12) + 1024;
5351         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5352         if (CHIP_IS_E1(bp)) {
5353                 /* !!! fix pxp client crdit until excel update */
5354                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5355                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
5356         }
5357
5358         bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
5359         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5360
5361         bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
5362         bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
5363
5364         /* PXPCS COMMON comes here */
5365         /* Reset PCIE errors for debug */
5366         REG_WR(bp, 0x2814, 0xffffffff);
5367         REG_WR(bp, 0x3820, 0xffffffff);
5368
5369         /* EMAC0 COMMON comes here */
5370         /* EMAC1 COMMON comes here */
5371         /* DBU COMMON comes here */
5372         /* DBG COMMON comes here */
5373
5374         bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
5375         if (CHIP_IS_E1H(bp)) {
5376                 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
5377                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
5378         }
5379
5380         if (CHIP_REV_IS_SLOW(bp))
5381                 msleep(200);
5382
5383         /* finish CFC init */
5384         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5385         if (val != 1) {
5386                 BNX2X_ERR("CFC LL_INIT failed\n");
5387                 return -EBUSY;
5388         }
5389         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5390         if (val != 1) {
5391                 BNX2X_ERR("CFC AC_INIT failed\n");
5392                 return -EBUSY;
5393         }
5394         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5395         if (val != 1) {
5396                 BNX2X_ERR("CFC CAM_INIT failed\n");
5397                 return -EBUSY;
5398         }
5399         REG_WR(bp, CFC_REG_DEBUG0, 0);
5400
5401         /* read NIG statistic
5402            to see if this is our first up since powerup */
5403         bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5404         val = *bnx2x_sp(bp, wb_data[0]);
5405
5406         /* do internal memory self test */
5407         if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
5408                 BNX2X_ERR("internal mem self test failed\n");
5409                 return -EBUSY;
5410         }
5411
5412         switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5413         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
5414         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5415                 /* Fan failure is indicated by SPIO 5 */
5416                 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5417                                MISC_REGISTERS_SPIO_INPUT_HI_Z);
5418
5419                 /* set to active low mode */
5420                 val = REG_RD(bp, MISC_REG_SPIO_INT);
5421                 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5422                                         MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5423                 REG_WR(bp, MISC_REG_SPIO_INT, val);
5424
5425                 /* enable interrupt to signal the IGU */
5426                 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5427                 val |= (1 << MISC_REGISTERS_SPIO_5);
5428                 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5429                 break;
5430
5431         default:
5432                 break;
5433         }
5434
5435         /* clear PXP2 attentions */
5436         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5437
5438         enable_blocks_attention(bp);
5439
5440         if (!BP_NOMCP(bp)) {
5441                 bnx2x_acquire_phy_lock(bp);
5442                 bnx2x_common_init_phy(bp, bp->common.shmem_base);
5443                 bnx2x_release_phy_lock(bp);
5444         } else
5445                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5446
5447         return 0;
5448 }
5449
5450 static int bnx2x_init_port(struct bnx2x *bp)
5451 {
5452         int port = BP_PORT(bp);
5453         u32 val;
5454
5455         DP(BNX2X_MSG_MCP, "starting port init  port %x\n", port);
5456
5457         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5458
5459         /* Port PXP comes here */
5460         /* Port PXP2 comes here */
5461 #ifdef BCM_ISCSI
5462         /* Port0  1
5463          * Port1  385 */
5464         i++;
5465         wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5466         wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5467         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5468         REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5469
5470         /* Port0  2
5471          * Port1  386 */
5472         i++;
5473         wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5474         wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5475         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5476         REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5477
5478         /* Port0  3
5479          * Port1  387 */
5480         i++;
5481         wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5482         wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5483         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5484         REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5485 #endif
5486         /* Port CMs come here */
5487
5488         /* Port QM comes here */
5489 #ifdef BCM_ISCSI
5490         REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5491         REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5492
5493         bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
5494                              func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
5495 #endif
5496         /* Port DQ comes here */
5497         /* Port BRB1 comes here */
5498         /* Port PRS comes here */
5499         /* Port TSDM comes here */
5500         /* Port CSDM comes here */
5501         /* Port USDM comes here */
5502         /* Port XSDM comes here */
5503         bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
5504                              port ? TSEM_PORT1_END : TSEM_PORT0_END);
5505         bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
5506                              port ? USEM_PORT1_END : USEM_PORT0_END);
5507         bnx2x_init_block(bp, port ? CSEM_PORT1_START : CSEM_PORT0_START,
5508                              port ? CSEM_PORT1_END : CSEM_PORT0_END);
5509         bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
5510                              port ? XSEM_PORT1_END : XSEM_PORT0_END);
5511         /* Port UPB comes here */
5512         /* Port XPB comes here */
5513
5514         bnx2x_init_block(bp, port ? PBF_PORT1_START : PBF_PORT0_START,
5515                              port ? PBF_PORT1_END : PBF_PORT0_END);
5516
5517         /* configure PBF to work without PAUSE mtu 9000 */
5518         REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5519
5520         /* update threshold */
5521         REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5522         /* update init credit */
5523         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5524
5525         /* probe changes */
5526         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5527         msleep(5);
5528         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5529
5530 #ifdef BCM_ISCSI
5531         /* tell the searcher where the T2 table is */
5532         REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);
5533
5534         wb_write[0] = U64_LO(bp->t2_mapping);
5535         wb_write[1] = U64_HI(bp->t2_mapping);
5536         REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
5537         wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
5538         wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
5539         REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
5540
5541         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
5542         /* Port SRCH comes here */
5543 #endif
5544         /* Port CDU comes here */
5545         /* Port CFC comes here */
5546
5547         if (CHIP_IS_E1(bp)) {
5548                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5549                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5550         }
5551         bnx2x_init_block(bp, port ? HC_PORT1_START : HC_PORT0_START,
5552                              port ? HC_PORT1_END : HC_PORT0_END);
5553
5554         bnx2x_init_block(bp, port ? MISC_AEU_PORT1_START :
5555                                     MISC_AEU_PORT0_START,
5556                              port ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END);
5557         /* init aeu_mask_attn_func_0/1:
5558          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5559          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5560          *             bits 4-7 are used for "per vn group attention" */
5561         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
5562                (IS_E1HMF(bp) ? 0xF7 : 0x7));
5563
5564         /* Port PXPCS comes here */
5565         /* Port EMAC0 comes here */
5566         /* Port EMAC1 comes here */
5567         /* Port DBU comes here */
5568         /* Port DBG comes here */
5569         bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START,
5570                              port ? NIG_PORT1_END : NIG_PORT0_END);
5571
5572         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5573
5574         if (CHIP_IS_E1H(bp)) {
5575                 u32 wsum;
5576                 struct cmng_struct_per_port m_cmng_port;
5577                 int vn;
5578
5579                 /* 0x2 disable e1hov, 0x1 enable */
5580                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5581                        (IS_E1HMF(bp) ? 0x1 : 0x2));
5582
5583                 /* Init RATE SHAPING and FAIRNESS contexts.
5584                    Initialize as if there is 10G link. */
5585                 wsum = bnx2x_calc_vn_wsum(bp);
5586                 bnx2x_init_port_minmax(bp, (int)wsum, 10000, &m_cmng_port);
5587                 if (IS_E1HMF(bp))
5588                         for (vn = VN_0; vn < E1HVN_MAX; vn++)
5589                                 bnx2x_init_vn_minmax(bp, 2*vn + port,
5590                                         wsum, 10000, &m_cmng_port);
5591         }
5592
5593         /* Port MCP comes here */
5594         /* Port DMAE comes here */
5595
5596         switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5597         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
5598         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5599                 /* add SPIO 5 to group 0 */
5600                 val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5601                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5602                 REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val);
5603                 break;
5604
5605         default:
5606                 break;
5607         }
5608
5609         bnx2x__link_reset(bp);
5610
5611         return 0;
5612 }
5613
5614 #define ILT_PER_FUNC            (768/2)
5615 #define FUNC_ILT_BASE(func)     (func * ILT_PER_FUNC)
5616 /* the phys address is shifted right 12 bits and has an added
5617    1=valid bit added to the 53rd bit
5618    then since this is a wide register(TM)
5619    we split it into two 32 bit writes
5620  */
5621 #define ONCHIP_ADDR1(x)         ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
5622 #define ONCHIP_ADDR2(x)         ((u32)((1 << 20) | ((u64)x >> 44)))
5623 #define PXP_ONE_ILT(x)          (((x) << 10) | x)
5624 #define PXP_ILT_RANGE(f, l)     (((l) << 10) | f)
5625
5626 #define CNIC_ILT_LINES          0
5627
5628 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5629 {
5630         int reg;
5631
5632         if (CHIP_IS_E1H(bp))
5633                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5634         else /* E1 */
5635                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5636
5637         bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5638 }
5639
5640 static int bnx2x_init_func(struct bnx2x *bp)
5641 {
5642         int port = BP_PORT(bp);
5643         int func = BP_FUNC(bp);
5644         int i;
5645
5646         DP(BNX2X_MSG_MCP, "starting func init  func %x\n", func);
5647
5648         i = FUNC_ILT_BASE(func);
5649
5650         bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
5651         if (CHIP_IS_E1H(bp)) {
5652                 REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
5653                 REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
5654         } else /* E1 */
5655                 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
5656                        PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
5657
5658
5659         if (CHIP_IS_E1H(bp)) {
5660                 for (i = 0; i < 9; i++)
5661                         bnx2x_init_block(bp,
5662                                          cm_start[func][i], cm_end[func][i]);
5663
5664                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5665                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
5666         }
5667
5668         /* HC init per function */
5669         if (CHIP_IS_E1H(bp)) {
5670                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5671
5672                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5673                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5674         }
5675         bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]);
5676
5677         if (CHIP_IS_E1H(bp))
5678                 REG_WR(bp, HC_REG_FUNC_NUM_P0 + port*4, func);
5679
5680         /* Reset PCIE errors for debug */
5681         REG_WR(bp, 0x2114, 0xffffffff);
5682         REG_WR(bp, 0x2120, 0xffffffff);
5683
5684         return 0;
5685 }
5686
5687 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5688 {
5689         int i, rc = 0;
5690
5691         DP(BNX2X_MSG_MCP, "function %d  load_code %x\n",
5692            BP_FUNC(bp), load_code);
5693
5694         bp->dmae_ready = 0;
5695         mutex_init(&bp->dmae_mutex);
5696         bnx2x_gunzip_init(bp);
5697
5698         switch (load_code) {
5699         case FW_MSG_CODE_DRV_LOAD_COMMON:
5700                 rc = bnx2x_init_common(bp);
5701                 if (rc)
5702                         goto init_hw_err;
5703                 /* no break */
5704
5705         case FW_MSG_CODE_DRV_LOAD_PORT:
5706                 bp->dmae_ready = 1;
5707                 rc = bnx2x_init_port(bp);
5708                 if (rc)
5709                         goto init_hw_err;
5710                 /* no break */
5711
5712         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5713                 bp->dmae_ready = 1;
5714                 rc = bnx2x_init_func(bp);
5715                 if (rc)
5716                         goto init_hw_err;
5717                 break;
5718
5719         default:
5720                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5721                 break;
5722         }
5723
5724         if (!BP_NOMCP(bp)) {
5725                 int func = BP_FUNC(bp);
5726
5727                 bp->fw_drv_pulse_wr_seq =
5728                                 (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
5729                                  DRV_PULSE_SEQ_MASK);
5730                 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
5731                 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x  func_stx 0x%x\n",
5732                    bp->fw_drv_pulse_wr_seq, bp->func_stx);
5733         } else
5734                 bp->func_stx = 0;
5735
5736         /* this needs to be done before gunzip end */
5737         bnx2x_zero_def_sb(bp);
5738         for_each_queue(bp, i)
5739                 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
5740
5741 init_hw_err:
5742         bnx2x_gunzip_end(bp);
5743
5744         return rc;
5745 }
5746
5747 /* send the MCP a request, block until there is a reply */
5748 static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5749 {
5750         int func = BP_FUNC(bp);
5751         u32 seq = ++bp->fw_seq;
5752         u32 rc = 0;
5753         u32 cnt = 1;
5754         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
5755
5756         SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
5757         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
5758
5759         do {
5760                 /* let the FW do it's magic ... */
5761                 msleep(delay);
5762
5763                 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
5764
5765                 /* Give the FW up to 2 second (200*10ms) */
5766         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
5767
5768         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
5769            cnt*delay, rc, seq);
5770
5771         /* is this a reply to our command? */
5772         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
5773                 rc &= FW_MSG_CODE_MASK;
5774
5775         } else {
5776                 /* FW BUG! */
5777                 BNX2X_ERR("FW failed to respond!\n");
5778                 bnx2x_fw_dump(bp);
5779                 rc = 0;
5780         }
5781
5782         return rc;
5783 }
5784
5785 static void bnx2x_free_mem(struct bnx2x *bp)
5786 {
5787
5788 #define BNX2X_PCI_FREE(x, y, size) \
5789         do { \
5790                 if (x) { \
5791                         pci_free_consistent(bp->pde