bnx2x: System-page alignment
[linux-2.6.git] / drivers / net / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2009 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>  /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/bitops.h>
35 #include <linux/irq.h>
36 #include <linux/delay.h>
37 #include <asm/byteorder.h>
38 #include <linux/time.h>
39 #include <linux/ethtool.h>
40 #include <linux/mii.h>
41 #include <linux/if_vlan.h>
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
51 #include <linux/io.h>
52
53 #include "bnx2x_reg.h"
54 #include "bnx2x_fw_defs.h"
55 #include "bnx2x_hsi.h"
56 #include "bnx2x_link.h"
57 #include "bnx2x.h"
58 #include "bnx2x_init.h"
59
60 #define DRV_MODULE_VERSION      "1.45.26"
61 #define DRV_MODULE_RELDATE      "2009/01/26"
62 #define BNX2X_BC_VER            0x040200
63
64 /* Time in jiffies before concluding the transmitter is hung */
65 #define TX_TIMEOUT              (5*HZ)
66
67 static char version[] __devinitdata =
68         "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
69         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70
71 MODULE_AUTHOR("Eliezer Tamir");
72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION);
75
76 static int multi_mode = 1;
77 module_param(multi_mode, int, 0);
78
79 static int disable_tpa;
80 static int poll;
81 static int debug;
82 static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
83
84 module_param(disable_tpa, int, 0);
85
86 static int int_mode;
87 module_param(int_mode, int, 0);
88 MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)");
89
90 module_param(poll, int, 0);
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
93 MODULE_PARM_DESC(poll, "use polling (for debug)");
94 MODULE_PARM_DESC(debug, "default debug msglevel");
95
96 static struct workqueue_struct *bnx2x_wq;
97
98 enum bnx2x_board_type {
99         BCM57710 = 0,
100         BCM57711 = 1,
101         BCM57711E = 2,
102 };
103
104 /* indexed by board_type, above */
105 static struct {
106         char *name;
107 } board_info[] __devinitdata = {
108         { "Broadcom NetXtreme II BCM57710 XGb" },
109         { "Broadcom NetXtreme II BCM57711 XGb" },
110         { "Broadcom NetXtreme II BCM57711E XGb" }
111 };
112
113
114 static const struct pci_device_id bnx2x_pci_tbl[] = {
115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
121         { 0 }
122 };
123
124 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
125
126 /****************************************************************************
127 * General service functions
128 ****************************************************************************/
129
130 /* used only at init
131  * locking is done by mcp
132  */
133 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
134 {
135         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
136         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
137         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
138                                PCICFG_VENDOR_ID_OFFSET);
139 }
140
141 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
142 {
143         u32 val;
144
145         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
146         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
147         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
148                                PCICFG_VENDOR_ID_OFFSET);
149
150         return val;
151 }
152
153 static const u32 dmae_reg_go_c[] = {
154         DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
155         DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
156         DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
157         DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
158 };
159
160 /* copy command into DMAE command memory and set DMAE command go */
161 static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
162                             int idx)
163 {
164         u32 cmd_offset;
165         int i;
166
167         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
168         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
169                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
170
171                 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
172                    idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
173         }
174         REG_WR(bp, dmae_reg_go_c[idx], 1);
175 }
176
177 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
178                       u32 len32)
179 {
180         struct dmae_command *dmae = &bp->init_dmae;
181         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
182         int cnt = 200;
183
184         if (!bp->dmae_ready) {
185                 u32 *data = bnx2x_sp(bp, wb_data[0]);
186
187                 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
188                    "  using indirect\n", dst_addr, len32);
189                 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
190                 return;
191         }
192
193         mutex_lock(&bp->dmae_mutex);
194
195         memset(dmae, 0, sizeof(struct dmae_command));
196
197         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
198                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
199                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
200 #ifdef __BIG_ENDIAN
201                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
202 #else
203                         DMAE_CMD_ENDIANITY_DW_SWAP |
204 #endif
205                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
206                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
207         dmae->src_addr_lo = U64_LO(dma_addr);
208         dmae->src_addr_hi = U64_HI(dma_addr);
209         dmae->dst_addr_lo = dst_addr >> 2;
210         dmae->dst_addr_hi = 0;
211         dmae->len = len32;
212         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
213         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
214         dmae->comp_val = DMAE_COMP_VAL;
215
216         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
217            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
218                     "dst_addr [%x:%08x (%08x)]\n"
219            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
220            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
221            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
222            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
223         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
224            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
225            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
226
227         *wb_comp = 0;
228
229         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
230
231         udelay(5);
232
233         while (*wb_comp != DMAE_COMP_VAL) {
234                 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
235
236                 if (!cnt) {
237                         BNX2X_ERR("dmae timeout!\n");
238                         break;
239                 }
240                 cnt--;
241                 /* adjust delay for emulation/FPGA */
242                 if (CHIP_REV_IS_SLOW(bp))
243                         msleep(100);
244                 else
245                         udelay(5);
246         }
247
248         mutex_unlock(&bp->dmae_mutex);
249 }
250
251 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
252 {
253         struct dmae_command *dmae = &bp->init_dmae;
254         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
255         int cnt = 200;
256
257         if (!bp->dmae_ready) {
258                 u32 *data = bnx2x_sp(bp, wb_data[0]);
259                 int i;
260
261                 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x  len32 %d)"
262                    "  using indirect\n", src_addr, len32);
263                 for (i = 0; i < len32; i++)
264                         data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
265                 return;
266         }
267
268         mutex_lock(&bp->dmae_mutex);
269
270         memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
271         memset(dmae, 0, sizeof(struct dmae_command));
272
273         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
274                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
275                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
276 #ifdef __BIG_ENDIAN
277                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
278 #else
279                         DMAE_CMD_ENDIANITY_DW_SWAP |
280 #endif
281                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
282                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
283         dmae->src_addr_lo = src_addr >> 2;
284         dmae->src_addr_hi = 0;
285         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
286         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
287         dmae->len = len32;
288         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
289         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
290         dmae->comp_val = DMAE_COMP_VAL;
291
292         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
293            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
294                     "dst_addr [%x:%08x (%08x)]\n"
295            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
296            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
297            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
298            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
299
300         *wb_comp = 0;
301
302         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
303
304         udelay(5);
305
306         while (*wb_comp != DMAE_COMP_VAL) {
307
308                 if (!cnt) {
309                         BNX2X_ERR("dmae timeout!\n");
310                         break;
311                 }
312                 cnt--;
313                 /* adjust delay for emulation/FPGA */
314                 if (CHIP_REV_IS_SLOW(bp))
315                         msleep(100);
316                 else
317                         udelay(5);
318         }
319         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
320            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
321            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
322
323         mutex_unlock(&bp->dmae_mutex);
324 }
325
326 /* used only for slowpath so not inlined */
327 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
328 {
329         u32 wb_write[2];
330
331         wb_write[0] = val_hi;
332         wb_write[1] = val_lo;
333         REG_WR_DMAE(bp, reg, wb_write, 2);
334 }
335
336 #ifdef USE_WB_RD
337 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
338 {
339         u32 wb_data[2];
340
341         REG_RD_DMAE(bp, reg, wb_data, 2);
342
343         return HILO_U64(wb_data[0], wb_data[1]);
344 }
345 #endif
346
347 static int bnx2x_mc_assert(struct bnx2x *bp)
348 {
349         char last_idx;
350         int i, rc = 0;
351         u32 row0, row1, row2, row3;
352
353         /* XSTORM */
354         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
355                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
356         if (last_idx)
357                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
358
359         /* print the asserts */
360         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
361
362                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
363                               XSTORM_ASSERT_LIST_OFFSET(i));
364                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
365                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
366                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
367                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
368                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
369                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
370
371                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
372                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
373                                   " 0x%08x 0x%08x 0x%08x\n",
374                                   i, row3, row2, row1, row0);
375                         rc++;
376                 } else {
377                         break;
378                 }
379         }
380
381         /* TSTORM */
382         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
383                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
384         if (last_idx)
385                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
386
387         /* print the asserts */
388         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
389
390                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
391                               TSTORM_ASSERT_LIST_OFFSET(i));
392                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
393                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
394                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
395                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
396                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
397                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
398
399                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
400                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
401                                   " 0x%08x 0x%08x 0x%08x\n",
402                                   i, row3, row2, row1, row0);
403                         rc++;
404                 } else {
405                         break;
406                 }
407         }
408
409         /* CSTORM */
410         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
411                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
412         if (last_idx)
413                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
414
415         /* print the asserts */
416         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
417
418                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
419                               CSTORM_ASSERT_LIST_OFFSET(i));
420                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
421                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
422                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
423                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
424                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
425                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
426
427                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
428                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
429                                   " 0x%08x 0x%08x 0x%08x\n",
430                                   i, row3, row2, row1, row0);
431                         rc++;
432                 } else {
433                         break;
434                 }
435         }
436
437         /* USTORM */
438         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
439                            USTORM_ASSERT_LIST_INDEX_OFFSET);
440         if (last_idx)
441                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
442
443         /* print the asserts */
444         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
445
446                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
447                               USTORM_ASSERT_LIST_OFFSET(i));
448                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
449                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
450                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
451                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
452                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
453                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
454
455                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
456                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
457                                   " 0x%08x 0x%08x 0x%08x\n",
458                                   i, row3, row2, row1, row0);
459                         rc++;
460                 } else {
461                         break;
462                 }
463         }
464
465         return rc;
466 }
467
468 static void bnx2x_fw_dump(struct bnx2x *bp)
469 {
470         u32 mark, offset;
471         u32 data[9];
472         int word;
473
474         mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
475         mark = ((mark + 0x3) & ~0x3);
476         printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
477
478         for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
479                 for (word = 0; word < 8; word++)
480                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
481                                                   offset + 4*word));
482                 data[8] = 0x0;
483                 printk(KERN_CONT "%s", (char *)data);
484         }
485         for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
486                 for (word = 0; word < 8; word++)
487                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
488                                                   offset + 4*word));
489                 data[8] = 0x0;
490                 printk(KERN_CONT "%s", (char *)data);
491         }
492         printk("\n" KERN_ERR PFX "end of fw dump\n");
493 }
494
495 static void bnx2x_panic_dump(struct bnx2x *bp)
496 {
497         int i;
498         u16 j, start, end;
499
500         bp->stats_state = STATS_STATE_DISABLED;
501         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
502
503         BNX2X_ERR("begin crash dump -----------------\n");
504
505         for_each_queue(bp, i) {
506                 struct bnx2x_fastpath *fp = &bp->fp[i];
507                 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
508
509                 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
510                           "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)\n",
511                           i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
512                           fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
513                 BNX2X_ERR("          rx_bd_prod(%x)  rx_bd_cons(%x)"
514                           "  *rx_bd_cons_sb(%x)  rx_comp_prod(%x)"
515                           "  rx_comp_cons(%x)  *rx_cons_sb(%x)\n",
516                           fp->rx_bd_prod, fp->rx_bd_cons,
517                           le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
518                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
519                 BNX2X_ERR("          rx_sge_prod(%x)  last_max_sge(%x)"
520                           "  fp_c_idx(%x)  *sb_c_idx(%x)  fp_u_idx(%x)"
521                           "  *sb_u_idx(%x)  bd data(%x,%x)\n",
522                           fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx,
523                           fp->status_blk->c_status_block.status_block_index,
524                           fp->fp_u_idx,
525                           fp->status_blk->u_status_block.status_block_index,
526                           hw_prods->packets_prod, hw_prods->bds_prod);
527
528                 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
529                 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
530                 for (j = start; j < end; j++) {
531                         struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
532
533                         BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
534                                   sw_bd->skb, sw_bd->first_bd);
535                 }
536
537                 start = TX_BD(fp->tx_bd_cons - 10);
538                 end = TX_BD(fp->tx_bd_cons + 254);
539                 for (j = start; j < end; j++) {
540                         u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
541
542                         BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
543                                   j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
544                 }
545
546                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
547                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
548                 for (j = start; j < end; j++) {
549                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
550                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
551
552                         BNX2X_ERR("rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
553                                   j, rx_bd[1], rx_bd[0], sw_bd->skb);
554                 }
555
556                 start = RX_SGE(fp->rx_sge_prod);
557                 end = RX_SGE(fp->last_max_sge);
558                 for (j = start; j < end; j++) {
559                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
560                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
561
562                         BNX2X_ERR("rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
563                                   j, rx_sge[1], rx_sge[0], sw_page->page);
564                 }
565
566                 start = RCQ_BD(fp->rx_comp_cons - 10);
567                 end = RCQ_BD(fp->rx_comp_cons + 503);
568                 for (j = start; j < end; j++) {
569                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
570
571                         BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
572                                   j, cqe[0], cqe[1], cqe[2], cqe[3]);
573                 }
574         }
575
576         BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
577                   "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
578                   "  spq_prod_idx(%u)\n",
579                   bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
580                   bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
581
582         bnx2x_fw_dump(bp);
583         bnx2x_mc_assert(bp);
584         BNX2X_ERR("end crash dump -----------------\n");
585 }
586
587 static void bnx2x_int_enable(struct bnx2x *bp)
588 {
589         int port = BP_PORT(bp);
590         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
591         u32 val = REG_RD(bp, addr);
592         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
593         int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
594
595         if (msix) {
596                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
597                          HC_CONFIG_0_REG_INT_LINE_EN_0);
598                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
599                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
600         } else if (msi) {
601                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
602                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
603                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
604                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
605         } else {
606                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
607                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
608                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
609                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
610
611                 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
612                    val, port, addr);
613
614                 REG_WR(bp, addr, val);
615
616                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
617         }
618
619         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  mode %s\n",
620            val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
621
622         REG_WR(bp, addr, val);
623
624         if (CHIP_IS_E1H(bp)) {
625                 /* init leading/trailing edge */
626                 if (IS_E1HMF(bp)) {
627                         val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
628                         if (bp->port.pmf)
629                                 /* enable nig attention */
630                                 val |= 0x0100;
631                 } else
632                         val = 0xffff;
633
634                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
635                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
636         }
637 }
638
639 static void bnx2x_int_disable(struct bnx2x *bp)
640 {
641         int port = BP_PORT(bp);
642         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
643         u32 val = REG_RD(bp, addr);
644
645         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
646                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
647                  HC_CONFIG_0_REG_INT_LINE_EN_0 |
648                  HC_CONFIG_0_REG_ATTN_BIT_EN_0);
649
650         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
651            val, port, addr);
652
653         /* flush all outstanding writes */
654         mmiowb();
655
656         REG_WR(bp, addr, val);
657         if (REG_RD(bp, addr) != val)
658                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
659 }
660
661 static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
662 {
663         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
664         int i, offset;
665
666         /* disable interrupt handling */
667         atomic_inc(&bp->intr_sem);
668         if (disable_hw)
669                 /* prevent the HW from sending interrupts */
670                 bnx2x_int_disable(bp);
671
672         /* make sure all ISRs are done */
673         if (msix) {
674                 synchronize_irq(bp->msix_table[0].vector);
675                 offset = 1;
676                 for_each_queue(bp, i)
677                         synchronize_irq(bp->msix_table[i + offset].vector);
678         } else
679                 synchronize_irq(bp->pdev->irq);
680
681         /* make sure sp_task is not running */
682         cancel_delayed_work(&bp->sp_task);
683         flush_workqueue(bnx2x_wq);
684 }
685
686 /* fast path */
687
688 /*
689  * General service functions
690  */
691
692 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
693                                 u8 storm, u16 index, u8 op, u8 update)
694 {
695         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
696                        COMMAND_REG_INT_ACK);
697         struct igu_ack_register igu_ack;
698
699         igu_ack.status_block_index = index;
700         igu_ack.sb_id_and_flags =
701                         ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
702                          (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
703                          (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
704                          (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
705
706         DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
707            (*(u32 *)&igu_ack), hc_addr);
708         REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
709 }
710
711 static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
712 {
713         struct host_status_block *fpsb = fp->status_blk;
714         u16 rc = 0;
715
716         barrier(); /* status block is written to by the chip */
717         if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
718                 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
719                 rc |= 1;
720         }
721         if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
722                 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
723                 rc |= 2;
724         }
725         return rc;
726 }
727
728 static u16 bnx2x_ack_int(struct bnx2x *bp)
729 {
730         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
731                        COMMAND_REG_SIMD_MASK);
732         u32 result = REG_RD(bp, hc_addr);
733
734         DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
735            result, hc_addr);
736
737         return result;
738 }
739
740
741 /*
742  * fast path service functions
743  */
744
745 static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
746 {
747         u16 tx_cons_sb;
748
749         /* Tell compiler that status block fields can change */
750         barrier();
751         tx_cons_sb = le16_to_cpu(*fp->tx_cons_sb);
752         return (fp->tx_pkt_cons != tx_cons_sb);
753 }
754
755 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
756 {
757         /* Tell compiler that consumer and producer can change */
758         barrier();
759         return (fp->tx_pkt_prod != fp->tx_pkt_cons);
760
761 }
762
763 /* free skb in the packet ring at pos idx
764  * return idx of last bd freed
765  */
766 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
767                              u16 idx)
768 {
769         struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
770         struct eth_tx_bd *tx_bd;
771         struct sk_buff *skb = tx_buf->skb;
772         u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
773         int nbd;
774
775         DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
776            idx, tx_buf, skb);
777
778         /* unmap first bd */
779         DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
780         tx_bd = &fp->tx_desc_ring[bd_idx];
781         pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
782                          BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
783
784         nbd = le16_to_cpu(tx_bd->nbd) - 1;
785         new_cons = nbd + tx_buf->first_bd;
786 #ifdef BNX2X_STOP_ON_ERROR
787         if (nbd > (MAX_SKB_FRAGS + 2)) {
788                 BNX2X_ERR("BAD nbd!\n");
789                 bnx2x_panic();
790         }
791 #endif
792
793         /* Skip a parse bd and the TSO split header bd
794            since they have no mapping */
795         if (nbd)
796                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
797
798         if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
799                                            ETH_TX_BD_FLAGS_TCP_CSUM |
800                                            ETH_TX_BD_FLAGS_SW_LSO)) {
801                 if (--nbd)
802                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
803                 tx_bd = &fp->tx_desc_ring[bd_idx];
804                 /* is this a TSO split header bd? */
805                 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
806                         if (--nbd)
807                                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
808                 }
809         }
810
811         /* now free frags */
812         while (nbd > 0) {
813
814                 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
815                 tx_bd = &fp->tx_desc_ring[bd_idx];
816                 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
817                                BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
818                 if (--nbd)
819                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
820         }
821
822         /* release skb */
823         WARN_ON(!skb);
824         dev_kfree_skb(skb);
825         tx_buf->first_bd = 0;
826         tx_buf->skb = NULL;
827
828         return new_cons;
829 }
830
831 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
832 {
833         s16 used;
834         u16 prod;
835         u16 cons;
836
837         barrier(); /* Tell compiler that prod and cons can change */
838         prod = fp->tx_bd_prod;
839         cons = fp->tx_bd_cons;
840
841         /* NUM_TX_RINGS = number of "next-page" entries
842            It will be used as a threshold */
843         used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
844
845 #ifdef BNX2X_STOP_ON_ERROR
846         WARN_ON(used < 0);
847         WARN_ON(used > fp->bp->tx_ring_size);
848         WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
849 #endif
850
851         return (s16)(fp->bp->tx_ring_size) - used;
852 }
853
854 static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
855 {
856         struct bnx2x *bp = fp->bp;
857         struct netdev_queue *txq;
858         u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
859         int done = 0;
860
861 #ifdef BNX2X_STOP_ON_ERROR
862         if (unlikely(bp->panic))
863                 return;
864 #endif
865
866         txq = netdev_get_tx_queue(bp->dev, fp->index);
867         hw_cons = le16_to_cpu(*fp->tx_cons_sb);
868         sw_cons = fp->tx_pkt_cons;
869
870         while (sw_cons != hw_cons) {
871                 u16 pkt_cons;
872
873                 pkt_cons = TX_BD(sw_cons);
874
875                 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
876
877                 DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %u\n",
878                    hw_cons, sw_cons, pkt_cons);
879
880 /*              if (NEXT_TX_IDX(sw_cons) != hw_cons) {
881                         rmb();
882                         prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
883                 }
884 */
885                 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
886                 sw_cons++;
887                 done++;
888
889                 if (done == work)
890                         break;
891         }
892
893         fp->tx_pkt_cons = sw_cons;
894         fp->tx_bd_cons = bd_cons;
895
896         /* Need to make the tx_bd_cons update visible to start_xmit()
897          * before checking for netif_tx_queue_stopped().  Without the
898          * memory barrier, there is a small possibility that start_xmit()
899          * will miss it and cause the queue to be stopped forever.
900          */
901         smp_mb();
902
903         /* TBD need a thresh? */
904         if (unlikely(netif_tx_queue_stopped(txq))) {
905
906                 __netif_tx_lock(txq, smp_processor_id());
907
908                 if ((netif_tx_queue_stopped(txq)) &&
909                     (bp->state == BNX2X_STATE_OPEN) &&
910                     (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
911                         netif_tx_wake_queue(txq);
912
913                 __netif_tx_unlock(txq);
914         }
915 }
916
917
918 static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
919                            union eth_rx_cqe *rr_cqe)
920 {
921         struct bnx2x *bp = fp->bp;
922         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
923         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
924
925         DP(BNX2X_MSG_SP,
926            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
927            FP_IDX(fp), cid, command, bp->state,
928            rr_cqe->ramrod_cqe.ramrod_type);
929
930         bp->spq_left++;
931
932         if (FP_IDX(fp)) {
933                 switch (command | fp->state) {
934                 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
935                                                 BNX2X_FP_STATE_OPENING):
936                         DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
937                            cid);
938                         fp->state = BNX2X_FP_STATE_OPEN;
939                         break;
940
941                 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
942                         DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
943                            cid);
944                         fp->state = BNX2X_FP_STATE_HALTED;
945                         break;
946
947                 default:
948                         BNX2X_ERR("unexpected MC reply (%d)  "
949                                   "fp->state is %x\n", command, fp->state);
950                         break;
951                 }
952                 mb(); /* force bnx2x_wait_ramrod() to see the change */
953                 return;
954         }
955
956         switch (command | bp->state) {
957         case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
958                 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
959                 bp->state = BNX2X_STATE_OPEN;
960                 break;
961
962         case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
963                 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
964                 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
965                 fp->state = BNX2X_FP_STATE_HALTED;
966                 break;
967
968         case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
969                 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
970                 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
971                 break;
972
973
974         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
975         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
976                 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
977                 bp->set_mac_pending = 0;
978                 break;
979
980         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
981                 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
982                 break;
983
984         default:
985                 BNX2X_ERR("unexpected MC reply (%d)  bp->state is %x\n",
986                           command, bp->state);
987                 break;
988         }
989         mb(); /* force bnx2x_wait_ramrod() to see the change */
990 }
991
992 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
993                                      struct bnx2x_fastpath *fp, u16 index)
994 {
995         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
996         struct page *page = sw_buf->page;
997         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
998
999         /* Skip "next page" elements */
1000         if (!page)
1001                 return;
1002
1003         pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
1004                        SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1005         __free_pages(page, PAGES_PER_SGE_SHIFT);
1006
1007         sw_buf->page = NULL;
1008         sge->addr_hi = 0;
1009         sge->addr_lo = 0;
1010 }
1011
1012 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1013                                            struct bnx2x_fastpath *fp, int last)
1014 {
1015         int i;
1016
1017         for (i = 0; i < last; i++)
1018                 bnx2x_free_rx_sge(bp, fp, i);
1019 }
1020
1021 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
1022                                      struct bnx2x_fastpath *fp, u16 index)
1023 {
1024         struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
1025         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1026         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1027         dma_addr_t mapping;
1028
1029         if (unlikely(page == NULL))
1030                 return -ENOMEM;
1031
1032         mapping = pci_map_page(bp->pdev, page, 0, SGE_PAGE_SIZE*PAGES_PER_SGE,
1033                                PCI_DMA_FROMDEVICE);
1034         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1035                 __free_pages(page, PAGES_PER_SGE_SHIFT);
1036                 return -ENOMEM;
1037         }
1038
1039         sw_buf->page = page;
1040         pci_unmap_addr_set(sw_buf, mapping, mapping);
1041
1042         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1043         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1044
1045         return 0;
1046 }
1047
1048 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1049                                      struct bnx2x_fastpath *fp, u16 index)
1050 {
1051         struct sk_buff *skb;
1052         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1053         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1054         dma_addr_t mapping;
1055
1056         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1057         if (unlikely(skb == NULL))
1058                 return -ENOMEM;
1059
1060         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_size,
1061                                  PCI_DMA_FROMDEVICE);
1062         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1063                 dev_kfree_skb(skb);
1064                 return -ENOMEM;
1065         }
1066
1067         rx_buf->skb = skb;
1068         pci_unmap_addr_set(rx_buf, mapping, mapping);
1069
1070         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1071         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1072
1073         return 0;
1074 }
1075
1076 /* note that we are not allocating a new skb,
1077  * we are just moving one from cons to prod
1078  * we are not creating a new mapping,
1079  * so there is no need to check for dma_mapping_error().
1080  */
1081 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1082                                struct sk_buff *skb, u16 cons, u16 prod)
1083 {
1084         struct bnx2x *bp = fp->bp;
1085         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1086         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1087         struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1088         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1089
1090         pci_dma_sync_single_for_device(bp->pdev,
1091                                        pci_unmap_addr(cons_rx_buf, mapping),
1092                                        bp->rx_offset + RX_COPY_THRESH,
1093                                        PCI_DMA_FROMDEVICE);
1094
1095         prod_rx_buf->skb = cons_rx_buf->skb;
1096         pci_unmap_addr_set(prod_rx_buf, mapping,
1097                            pci_unmap_addr(cons_rx_buf, mapping));
1098         *prod_bd = *cons_bd;
1099 }
1100
1101 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1102                                              u16 idx)
1103 {
1104         u16 last_max = fp->last_max_sge;
1105
1106         if (SUB_S16(idx, last_max) > 0)
1107                 fp->last_max_sge = idx;
1108 }
1109
1110 static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1111 {
1112         int i, j;
1113
1114         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1115                 int idx = RX_SGE_CNT * i - 1;
1116
1117                 for (j = 0; j < 2; j++) {
1118                         SGE_MASK_CLEAR_BIT(fp, idx);
1119                         idx--;
1120                 }
1121         }
1122 }
1123
1124 static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1125                                   struct eth_fast_path_rx_cqe *fp_cqe)
1126 {
1127         struct bnx2x *bp = fp->bp;
1128         u16 sge_len = SGE_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
1129                                      le16_to_cpu(fp_cqe->len_on_bd)) >>
1130                       SGE_PAGE_SHIFT;
1131         u16 last_max, last_elem, first_elem;
1132         u16 delta = 0;
1133         u16 i;
1134
1135         if (!sge_len)
1136                 return;
1137
1138         /* First mark all used pages */
1139         for (i = 0; i < sge_len; i++)
1140                 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1141
1142         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1143            sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1144
1145         /* Here we assume that the last SGE index is the biggest */
1146         prefetch((void *)(fp->sge_mask));
1147         bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1148
1149         last_max = RX_SGE(fp->last_max_sge);
1150         last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1151         first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1152
1153         /* If ring is not full */
1154         if (last_elem + 1 != first_elem)
1155                 last_elem++;
1156
1157         /* Now update the prod */
1158         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1159                 if (likely(fp->sge_mask[i]))
1160                         break;
1161
1162                 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1163                 delta += RX_SGE_MASK_ELEM_SZ;
1164         }
1165
1166         if (delta > 0) {
1167                 fp->rx_sge_prod += delta;
1168                 /* clear page-end entries */
1169                 bnx2x_clear_sge_mask_next_elems(fp);
1170         }
1171
1172         DP(NETIF_MSG_RX_STATUS,
1173            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
1174            fp->last_max_sge, fp->rx_sge_prod);
1175 }
1176
1177 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1178 {
1179         /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1180         memset(fp->sge_mask, 0xff,
1181                (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1182
1183         /* Clear the two last indices in the page to 1:
1184            these are the indices that correspond to the "next" element,
1185            hence will never be indicated and should be removed from
1186            the calculations. */
1187         bnx2x_clear_sge_mask_next_elems(fp);
1188 }
1189
1190 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1191                             struct sk_buff *skb, u16 cons, u16 prod)
1192 {
1193         struct bnx2x *bp = fp->bp;
1194         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1195         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1196         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1197         dma_addr_t mapping;
1198
1199         /* move empty skb from pool to prod and map it */
1200         prod_rx_buf->skb = fp->tpa_pool[queue].skb;
1201         mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
1202                                  bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1203         pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
1204
1205         /* move partial skb from cons to pool (don't unmap yet) */
1206         fp->tpa_pool[queue] = *cons_rx_buf;
1207
1208         /* mark bin state as start - print error if current state != stop */
1209         if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1210                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1211
1212         fp->tpa_state[queue] = BNX2X_TPA_START;
1213
1214         /* point prod_bd to new skb */
1215         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1216         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1217
1218 #ifdef BNX2X_STOP_ON_ERROR
1219         fp->tpa_queue_used |= (1 << queue);
1220 #ifdef __powerpc64__
1221         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1222 #else
1223         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1224 #endif
1225            fp->tpa_queue_used);
1226 #endif
1227 }
1228
1229 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1230                                struct sk_buff *skb,
1231                                struct eth_fast_path_rx_cqe *fp_cqe,
1232                                u16 cqe_idx)
1233 {
1234         struct sw_rx_page *rx_pg, old_rx_pg;
1235         u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1236         u32 i, frag_len, frag_size, pages;
1237         int err;
1238         int j;
1239
1240         frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
1241         pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
1242
1243         /* This is needed in order to enable forwarding support */
1244         if (frag_size)
1245                 skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
1246                                                max(frag_size, (u32)len_on_bd));
1247
1248 #ifdef BNX2X_STOP_ON_ERROR
1249         if (pages >
1250             min((u32)8, (u32)MAX_SKB_FRAGS) * SGE_PAGE_SIZE * PAGES_PER_SGE) {
1251                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1252                           pages, cqe_idx);
1253                 BNX2X_ERR("fp_cqe->pkt_len = %d  fp_cqe->len_on_bd = %d\n",
1254                           fp_cqe->pkt_len, len_on_bd);
1255                 bnx2x_panic();
1256                 return -EINVAL;
1257         }
1258 #endif
1259
1260         /* Run through the SGL and compose the fragmented skb */
1261         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1262                 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1263
1264                 /* FW gives the indices of the SGE as if the ring is an array
1265                    (meaning that "next" element will consume 2 indices) */
1266                 frag_len = min(frag_size, (u32)(SGE_PAGE_SIZE*PAGES_PER_SGE));
1267                 rx_pg = &fp->rx_page_ring[sge_idx];
1268                 old_rx_pg = *rx_pg;
1269
1270                 /* If we fail to allocate a substitute page, we simply stop
1271                    where we are and drop the whole packet */
1272                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1273                 if (unlikely(err)) {
1274                         bp->eth_stats.rx_skb_alloc_failed++;
1275                         return err;
1276                 }
1277
1278                 /* Unmap the page as we r going to pass it to the stack */
1279                 pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
1280                               SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1281
1282                 /* Add one frag and update the appropriate fields in the skb */
1283                 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1284
1285                 skb->data_len += frag_len;
1286                 skb->truesize += frag_len;
1287                 skb->len += frag_len;
1288
1289                 frag_size -= frag_len;
1290         }
1291
1292         return 0;
1293 }
1294
1295 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1296                            u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1297                            u16 cqe_idx)
1298 {
1299         struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1300         struct sk_buff *skb = rx_buf->skb;
1301         /* alloc new skb */
1302         struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1303
1304         /* Unmap skb in the pool anyway, as we are going to change
1305            pool entry status to BNX2X_TPA_STOP even if new skb allocation
1306            fails. */
1307         pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1308                          bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1309
1310         if (likely(new_skb)) {
1311                 /* fix ip xsum and give it to the stack */
1312                 /* (no need to map the new skb) */
1313 #ifdef BCM_VLAN
1314                 int is_vlan_cqe =
1315                         (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1316                          PARSING_FLAGS_VLAN);
1317                 int is_not_hwaccel_vlan_cqe =
1318                         (is_vlan_cqe && (!(bp->flags & HW_VLAN_RX_FLAG)));
1319 #endif
1320
1321                 prefetch(skb);
1322                 prefetch(((char *)(skb)) + 128);
1323
1324 #ifdef BNX2X_STOP_ON_ERROR
1325                 if (pad + len > bp->rx_buf_size) {
1326                         BNX2X_ERR("skb_put is about to fail...  "
1327                                   "pad %d  len %d  rx_buf_size %d\n",
1328                                   pad, len, bp->rx_buf_size);
1329                         bnx2x_panic();
1330                         return;
1331                 }
1332 #endif
1333
1334                 skb_reserve(skb, pad);
1335                 skb_put(skb, len);
1336
1337                 skb->protocol = eth_type_trans(skb, bp->dev);
1338                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1339                 skb_record_rx_queue(skb, queue);
1340
1341                 {
1342                         struct iphdr *iph;
1343
1344                         iph = (struct iphdr *)skb->data;
1345 #ifdef BCM_VLAN
1346                         /* If there is no Rx VLAN offloading -
1347                            take VLAN tag into an account */
1348                         if (unlikely(is_not_hwaccel_vlan_cqe))
1349                                 iph = (struct iphdr *)((u8 *)iph + VLAN_HLEN);
1350 #endif
1351                         iph->check = 0;
1352                         iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1353                 }
1354
1355                 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1356                                          &cqe->fast_path_cqe, cqe_idx)) {
1357 #ifdef BCM_VLAN
1358                         if ((bp->vlgrp != NULL) && is_vlan_cqe &&
1359                             (!is_not_hwaccel_vlan_cqe))
1360                                 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1361                                                 le16_to_cpu(cqe->fast_path_cqe.
1362                                                             vlan_tag));
1363                         else
1364 #endif
1365                                 netif_receive_skb(skb);
1366                 } else {
1367                         DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1368                            " - dropping packet!\n");
1369                         dev_kfree_skb(skb);
1370                 }
1371
1372
1373                 /* put new skb in bin */
1374                 fp->tpa_pool[queue].skb = new_skb;
1375
1376         } else {
1377                 /* else drop the packet and keep the buffer in the bin */
1378                 DP(NETIF_MSG_RX_STATUS,
1379                    "Failed to allocate new skb - dropping packet!\n");
1380                 bp->eth_stats.rx_skb_alloc_failed++;
1381         }
1382
1383         fp->tpa_state[queue] = BNX2X_TPA_STOP;
1384 }
1385
1386 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1387                                         struct bnx2x_fastpath *fp,
1388                                         u16 bd_prod, u16 rx_comp_prod,
1389                                         u16 rx_sge_prod)
1390 {
1391         struct ustorm_eth_rx_producers rx_prods = {0};
1392         int i;
1393
1394         /* Update producers */
1395         rx_prods.bd_prod = bd_prod;
1396         rx_prods.cqe_prod = rx_comp_prod;
1397         rx_prods.sge_prod = rx_sge_prod;
1398
1399         /*
1400          * Make sure that the BD and SGE data is updated before updating the
1401          * producers since FW might read the BD/SGE right after the producer
1402          * is updated.
1403          * This is only applicable for weak-ordered memory model archs such
1404          * as IA-64. The following barrier is also mandatory since FW will
1405          * assumes BDs must have buffers.
1406          */
1407         wmb();
1408
1409         for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
1410                 REG_WR(bp, BAR_USTRORM_INTMEM +
1411                        USTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
1412                        ((u32 *)&rx_prods)[i]);
1413
1414         mmiowb(); /* keep prod updates ordered */
1415
1416         DP(NETIF_MSG_RX_STATUS,
1417            "queue[%d]:  wrote  bd_prod %u  cqe_prod %u  sge_prod %u\n",
1418            fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
1419 }
1420
1421 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1422 {
1423         struct bnx2x *bp = fp->bp;
1424         u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1425         u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1426         int rx_pkt = 0;
1427
1428 #ifdef BNX2X_STOP_ON_ERROR
1429         if (unlikely(bp->panic))
1430                 return 0;
1431 #endif
1432
1433         /* CQ "next element" is of the size of the regular element,
1434            that's why it's ok here */
1435         hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1436         if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1437                 hw_comp_cons++;
1438
1439         bd_cons = fp->rx_bd_cons;
1440         bd_prod = fp->rx_bd_prod;
1441         bd_prod_fw = bd_prod;
1442         sw_comp_cons = fp->rx_comp_cons;
1443         sw_comp_prod = fp->rx_comp_prod;
1444
1445         /* Memory barrier necessary as speculative reads of the rx
1446          * buffer can be ahead of the index in the status block
1447          */
1448         rmb();
1449
1450         DP(NETIF_MSG_RX_STATUS,
1451            "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
1452            FP_IDX(fp), hw_comp_cons, sw_comp_cons);
1453
1454         while (sw_comp_cons != hw_comp_cons) {
1455                 struct sw_rx_bd *rx_buf = NULL;
1456                 struct sk_buff *skb;
1457                 union eth_rx_cqe *cqe;
1458                 u8 cqe_fp_flags;
1459                 u16 len, pad;
1460
1461                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1462                 bd_prod = RX_BD(bd_prod);
1463                 bd_cons = RX_BD(bd_cons);
1464
1465                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1466                 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1467
1468                 DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
1469                    "  queue %x  vlan %x  len %u\n", CQE_TYPE(cqe_fp_flags),
1470                    cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1471                    le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
1472                    le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1473                    le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1474
1475                 /* is this a slowpath msg? */
1476                 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
1477                         bnx2x_sp_event(fp, cqe);
1478                         goto next_cqe;
1479
1480                 /* this is an rx packet */
1481                 } else {
1482                         rx_buf = &fp->rx_buf_ring[bd_cons];
1483                         skb = rx_buf->skb;
1484                         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1485                         pad = cqe->fast_path_cqe.placement_offset;
1486
1487                         /* If CQE is marked both TPA_START and TPA_END
1488                            it is a non-TPA CQE */
1489                         if ((!fp->disable_tpa) &&
1490                             (TPA_TYPE(cqe_fp_flags) !=
1491                                         (TPA_TYPE_START | TPA_TYPE_END))) {
1492                                 u16 queue = cqe->fast_path_cqe.queue_index;
1493
1494                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1495                                         DP(NETIF_MSG_RX_STATUS,
1496                                            "calling tpa_start on queue %d\n",
1497                                            queue);
1498
1499                                         bnx2x_tpa_start(fp, queue, skb,
1500                                                         bd_cons, bd_prod);
1501                                         goto next_rx;
1502                                 }
1503
1504                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1505                                         DP(NETIF_MSG_RX_STATUS,
1506                                            "calling tpa_stop on queue %d\n",
1507                                            queue);
1508
1509                                         if (!BNX2X_RX_SUM_FIX(cqe))
1510                                                 BNX2X_ERR("STOP on none TCP "
1511                                                           "data\n");
1512
1513                                         /* This is a size of the linear data
1514                                            on this skb */
1515                                         len = le16_to_cpu(cqe->fast_path_cqe.
1516                                                                 len_on_bd);
1517                                         bnx2x_tpa_stop(bp, fp, queue, pad,
1518                                                     len, cqe, comp_ring_cons);
1519 #ifdef BNX2X_STOP_ON_ERROR
1520                                         if (bp->panic)
1521                                                 return -EINVAL;
1522 #endif
1523
1524                                         bnx2x_update_sge_prod(fp,
1525                                                         &cqe->fast_path_cqe);
1526                                         goto next_cqe;
1527                                 }
1528                         }
1529
1530                         pci_dma_sync_single_for_device(bp->pdev,
1531                                         pci_unmap_addr(rx_buf, mapping),
1532                                                        pad + RX_COPY_THRESH,
1533                                                        PCI_DMA_FROMDEVICE);
1534                         prefetch(skb);
1535                         prefetch(((char *)(skb)) + 128);
1536
1537                         /* is this an error packet? */
1538                         if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1539                                 DP(NETIF_MSG_RX_ERR,
1540                                    "ERROR  flags %x  rx packet %u\n",
1541                                    cqe_fp_flags, sw_comp_cons);
1542                                 bp->eth_stats.rx_err_discard_pkt++;
1543                                 goto reuse_rx;
1544                         }
1545
1546                         /* Since we don't have a jumbo ring
1547                          * copy small packets if mtu > 1500
1548                          */
1549                         if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1550                             (len <= RX_COPY_THRESH)) {
1551                                 struct sk_buff *new_skb;
1552
1553                                 new_skb = netdev_alloc_skb(bp->dev,
1554                                                            len + pad);
1555                                 if (new_skb == NULL) {
1556                                         DP(NETIF_MSG_RX_ERR,
1557                                            "ERROR  packet dropped "
1558                                            "because of alloc failure\n");
1559                                         bp->eth_stats.rx_skb_alloc_failed++;
1560                                         goto reuse_rx;
1561                                 }
1562
1563                                 /* aligned copy */
1564                                 skb_copy_from_linear_data_offset(skb, pad,
1565                                                     new_skb->data + pad, len);
1566                                 skb_reserve(new_skb, pad);
1567                                 skb_put(new_skb, len);
1568
1569                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1570
1571                                 skb = new_skb;
1572
1573                         } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
1574                                 pci_unmap_single(bp->pdev,
1575                                         pci_unmap_addr(rx_buf, mapping),
1576                                                  bp->rx_buf_size,
1577                                                  PCI_DMA_FROMDEVICE);
1578                                 skb_reserve(skb, pad);
1579                                 skb_put(skb, len);
1580
1581                         } else {
1582                                 DP(NETIF_MSG_RX_ERR,
1583                                    "ERROR  packet dropped because "
1584                                    "of alloc failure\n");
1585                                 bp->eth_stats.rx_skb_alloc_failed++;
1586 reuse_rx:
1587                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1588                                 goto next_rx;
1589                         }
1590
1591                         skb->protocol = eth_type_trans(skb, bp->dev);
1592
1593                         skb->ip_summed = CHECKSUM_NONE;
1594                         if (bp->rx_csum) {
1595                                 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1596                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1597                                 else
1598                                         bp->eth_stats.hw_csum_err++;
1599                         }
1600                 }
1601
1602 #ifdef BCM_VLAN
1603                 if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) &&
1604                     (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1605                      PARSING_FLAGS_VLAN))
1606                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1607                                 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1608                 else
1609 #endif
1610                         netif_receive_skb(skb);
1611
1612
1613 next_rx:
1614                 rx_buf->skb = NULL;
1615
1616                 bd_cons = NEXT_RX_IDX(bd_cons);
1617                 bd_prod = NEXT_RX_IDX(bd_prod);
1618                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1619                 rx_pkt++;
1620 next_cqe:
1621                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1622                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1623
1624                 if (rx_pkt == budget)
1625                         break;
1626         } /* while */
1627
1628         fp->rx_bd_cons = bd_cons;
1629         fp->rx_bd_prod = bd_prod_fw;
1630         fp->rx_comp_cons = sw_comp_cons;
1631         fp->rx_comp_prod = sw_comp_prod;
1632
1633         /* Update producers */
1634         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1635                              fp->rx_sge_prod);
1636
1637         fp->rx_pkt += rx_pkt;
1638         fp->rx_calls++;
1639
1640         return rx_pkt;
1641 }
1642
1643 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1644 {
1645         struct bnx2x_fastpath *fp = fp_cookie;
1646         struct bnx2x *bp = fp->bp;
1647         int index = FP_IDX(fp);
1648
1649         /* Return here if interrupt is disabled */
1650         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1651                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1652                 return IRQ_HANDLED;
1653         }
1654
1655         DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1656            index, FP_SB_ID(fp));
1657         bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
1658
1659 #ifdef BNX2X_STOP_ON_ERROR
1660         if (unlikely(bp->panic))
1661                 return IRQ_HANDLED;
1662 #endif
1663
1664         prefetch(fp->rx_cons_sb);
1665         prefetch(fp->tx_cons_sb);
1666         prefetch(&fp->status_blk->c_status_block.status_block_index);
1667         prefetch(&fp->status_blk->u_status_block.status_block_index);
1668
1669         napi_schedule(&bnx2x_fp(bp, index, napi));
1670
1671         return IRQ_HANDLED;
1672 }
1673
1674 static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1675 {
1676         struct bnx2x *bp = netdev_priv(dev_instance);
1677         u16 status = bnx2x_ack_int(bp);
1678         u16 mask;
1679
1680         /* Return here if interrupt is shared and it's not for us */
1681         if (unlikely(status == 0)) {
1682                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1683                 return IRQ_NONE;
1684         }
1685         DP(NETIF_MSG_INTR, "got an interrupt  status %u\n", status);
1686
1687         /* Return here if interrupt is disabled */
1688         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1689                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1690                 return IRQ_HANDLED;
1691         }
1692
1693 #ifdef BNX2X_STOP_ON_ERROR
1694         if (unlikely(bp->panic))
1695                 return IRQ_HANDLED;
1696 #endif
1697
1698         mask = 0x2 << bp->fp[0].sb_id;
1699         if (status & mask) {
1700                 struct bnx2x_fastpath *fp = &bp->fp[0];
1701
1702                 prefetch(fp->rx_cons_sb);
1703                 prefetch(fp->tx_cons_sb);
1704                 prefetch(&fp->status_blk->c_status_block.status_block_index);
1705                 prefetch(&fp->status_blk->u_status_block.status_block_index);
1706
1707                 napi_schedule(&bnx2x_fp(bp, 0, napi));
1708
1709                 status &= ~mask;
1710         }
1711
1712
1713         if (unlikely(status & 0x1)) {
1714                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1715
1716                 status &= ~0x1;
1717                 if (!status)
1718                         return IRQ_HANDLED;
1719         }
1720
1721         if (status)
1722                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1723                    status);
1724
1725         return IRQ_HANDLED;
1726 }
1727
1728 /* end of fast path */
1729
1730 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1731
1732 /* Link */
1733
1734 /*
1735  * General service functions
1736  */
1737
1738 static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1739 {
1740         u32 lock_status;
1741         u32 resource_bit = (1 << resource);
1742         int func = BP_FUNC(bp);
1743         u32 hw_lock_control_reg;
1744         int cnt;
1745
1746         /* Validating that the resource is within range */
1747         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1748                 DP(NETIF_MSG_HW,
1749                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1750                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1751                 return -EINVAL;
1752         }
1753
1754         if (func <= 5) {
1755                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1756         } else {
1757                 hw_lock_control_reg =
1758                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1759         }
1760
1761         /* Validating that the resource is not already taken */
1762         lock_status = REG_RD(bp, hw_lock_control_reg);
1763         if (lock_status & resource_bit) {
1764                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1765                    lock_status, resource_bit);
1766                 return -EEXIST;
1767         }
1768
1769         /* Try for 5 second every 5ms */
1770         for (cnt = 0; cnt < 1000; cnt++) {
1771                 /* Try to acquire the lock */
1772                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1773                 lock_status = REG_RD(bp, hw_lock_control_reg);
1774                 if (lock_status & resource_bit)
1775                         return 0;
1776
1777                 msleep(5);
1778         }
1779         DP(NETIF_MSG_HW, "Timeout\n");
1780         return -EAGAIN;
1781 }
1782
1783 static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1784 {
1785         u32 lock_status;
1786         u32 resource_bit = (1 << resource);
1787         int func = BP_FUNC(bp);
1788         u32 hw_lock_control_reg;
1789
1790         /* Validating that the resource is within range */
1791         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1792                 DP(NETIF_MSG_HW,
1793                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1794                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1795                 return -EINVAL;
1796         }
1797
1798         if (func <= 5) {
1799                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1800         } else {
1801                 hw_lock_control_reg =
1802                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1803         }
1804
1805         /* Validating that the resource is currently taken */
1806         lock_status = REG_RD(bp, hw_lock_control_reg);
1807         if (!(lock_status & resource_bit)) {
1808                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1809                    lock_status, resource_bit);
1810                 return -EFAULT;
1811         }
1812
1813         REG_WR(bp, hw_lock_control_reg, resource_bit);
1814         return 0;
1815 }
1816
1817 /* HW Lock for shared dual port PHYs */
1818 static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1819 {
1820         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1821
1822         mutex_lock(&bp->port.phy_mutex);
1823
1824         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1825             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1826                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1827 }
1828
1829 static void bnx2x_release_phy_lock(struct bnx2x *bp)
1830 {
1831         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1832
1833         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1834             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1835                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1836
1837         mutex_unlock(&bp->port.phy_mutex);
1838 }
1839
1840 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1841 {
1842         /* The GPIO should be swapped if swap register is set and active */
1843         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1844                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1845         int gpio_shift = gpio_num +
1846                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1847         u32 gpio_mask = (1 << gpio_shift);
1848         u32 gpio_reg;
1849
1850         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1851                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1852                 return -EINVAL;
1853         }
1854
1855         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1856         /* read GPIO and mask except the float bits */
1857         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1858
1859         switch (mode) {
1860         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1861                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1862                    gpio_num, gpio_shift);
1863                 /* clear FLOAT and set CLR */
1864                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1865                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1866                 break;
1867
1868         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1869                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1870                    gpio_num, gpio_shift);
1871                 /* clear FLOAT and set SET */
1872                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1873                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1874                 break;
1875
1876         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1877                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1878                    gpio_num, gpio_shift);
1879                 /* set FLOAT */
1880                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1881                 break;
1882
1883         default:
1884                 break;
1885         }
1886
1887         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1888         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1889
1890         return 0;
1891 }
1892
1893 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1894 {
1895         u32 spio_mask = (1 << spio_num);
1896         u32 spio_reg;
1897
1898         if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1899             (spio_num > MISC_REGISTERS_SPIO_7)) {
1900                 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1901                 return -EINVAL;
1902         }
1903
1904         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1905         /* read SPIO and mask except the float bits */
1906         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1907
1908         switch (mode) {
1909         case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1910                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1911                 /* clear FLOAT and set CLR */
1912                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1913                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1914                 break;
1915
1916         case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1917                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1918                 /* clear FLOAT and set SET */
1919                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1920                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1921                 break;
1922
1923         case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1924                 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1925                 /* set FLOAT */
1926                 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1927                 break;
1928
1929         default:
1930                 break;
1931         }
1932
1933         REG_WR(bp, MISC_REG_SPIO, spio_reg);
1934         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1935
1936         return 0;
1937 }
1938
1939 static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1940 {
1941         switch (bp->link_vars.ieee_fc &
1942                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1943         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1944                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1945                                           ADVERTISED_Pause);
1946                 break;
1947         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1948                 bp->port.advertising |= (ADVERTISED_Asym_Pause |
1949                                          ADVERTISED_Pause);
1950                 break;
1951         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1952                 bp->port.advertising |= ADVERTISED_Asym_Pause;
1953                 break;
1954         default:
1955                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1956                                           ADVERTISED_Pause);
1957                 break;
1958         }
1959 }
1960
1961 static void bnx2x_link_report(struct bnx2x *bp)
1962 {
1963         if (bp->link_vars.link_up) {
1964                 if (bp->state == BNX2X_STATE_OPEN)
1965                         netif_carrier_on(bp->dev);
1966                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
1967
1968                 printk("%d Mbps ", bp->link_vars.line_speed);
1969
1970                 if (bp->link_vars.duplex == DUPLEX_FULL)
1971                         printk("full duplex");
1972                 else
1973                         printk("half duplex");
1974
1975                 if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
1976                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
1977                                 printk(", receive ");
1978                                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1979                                         printk("& transmit ");
1980                         } else {
1981                                 printk(", transmit ");
1982                         }
1983                         printk("flow control ON");
1984                 }
1985                 printk("\n");
1986
1987         } else { /* link_down */
1988                 netif_carrier_off(bp->dev);
1989                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
1990         }
1991 }
1992
1993 static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1994 {
1995         if (!BP_NOMCP(bp)) {
1996                 u8 rc;
1997
1998                 /* Initialize link parameters structure variables */
1999                 /* It is recommended to turn off RX FC for jumbo frames
2000                    for better performance */
2001                 if (IS_E1HMF(bp))
2002                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2003                 else if (bp->dev->mtu > 5000)
2004                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2005                 else
2006                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2007
2008                 bnx2x_acquire_phy_lock(bp);
2009                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2010                 bnx2x_release_phy_lock(bp);
2011
2012                 bnx2x_calc_fc_adv(bp);
2013
2014                 if (bp->link_vars.link_up)
2015                         bnx2x_link_report(bp);
2016
2017
2018                 return rc;
2019         }
2020         BNX2X_ERR("Bootcode is missing -not initializing link\n");
2021         return -EINVAL;
2022 }
2023
2024 static void bnx2x_link_set(struct bnx2x *bp)
2025 {
2026         if (!BP_NOMCP(bp)) {
2027                 bnx2x_acquire_phy_lock(bp);
2028                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2029                 bnx2x_release_phy_lock(bp);
2030
2031                 bnx2x_calc_fc_adv(bp);
2032         } else
2033                 BNX2X_ERR("Bootcode is missing -not setting link\n");
2034 }
2035
2036 static void bnx2x__link_reset(struct bnx2x *bp)
2037 {
2038         if (!BP_NOMCP(bp)) {
2039                 bnx2x_acquire_phy_lock(bp);
2040                 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
2041                 bnx2x_release_phy_lock(bp);
2042         } else
2043                 BNX2X_ERR("Bootcode is missing -not resetting link\n");
2044 }
2045
2046 static u8 bnx2x_link_test(struct bnx2x *bp)
2047 {
2048         u8 rc;
2049
2050         bnx2x_acquire_phy_lock(bp);
2051         rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
2052         bnx2x_release_phy_lock(bp);
2053
2054         return rc;
2055 }
2056
2057 /* Calculates the sum of vn_min_rates.
2058    It's needed for further normalizing of the min_rates.
2059
2060    Returns:
2061      sum of vn_min_rates
2062        or
2063      0 - if all the min_rates are 0.
2064      In the later case fairness algorithm should be deactivated.
2065      If not all min_rates are zero then those that are zeroes will
2066      be set to 1.
2067  */
2068 static u32 bnx2x_calc_vn_wsum(struct bnx2x *bp)
2069 {
2070         int i, port = BP_PORT(bp);
2071         u32 wsum = 0;
2072         int all_zero = 1;
2073
2074         for (i = 0; i < E1HVN_MAX; i++) {
2075                 u32 vn_cfg =
2076                         SHMEM_RD(bp, mf_cfg.func_mf_config[2*i + port].config);
2077                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2078                                      FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2079                 if (!(vn_cfg & FUNC_MF_CFG_FUNC_HIDE)) {
2080                         /* If min rate is zero - set it to 1 */
2081                         if (!vn_min_rate)
2082                                 vn_min_rate = DEF_MIN_RATE;
2083                         else
2084                                 all_zero = 0;
2085
2086                         wsum += vn_min_rate;
2087                 }
2088         }
2089
2090         /* ... only if all min rates are zeros - disable FAIRNESS */
2091         if (all_zero)
2092                 return 0;
2093
2094         return wsum;
2095 }
2096
2097 static void bnx2x_init_port_minmax(struct bnx2x *bp,
2098                                    int en_fness,
2099                                    u16 port_rate,
2100                                    struct cmng_struct_per_port *m_cmng_port)
2101 {
2102         u32 r_param = port_rate / 8;
2103         int port = BP_PORT(bp);
2104         int i;
2105
2106         memset(m_cmng_port, 0, sizeof(struct cmng_struct_per_port));
2107
2108         /* Enable minmax only if we are in e1hmf mode */
2109         if (IS_E1HMF(bp)) {
2110                 u32 fair_periodic_timeout_usec;
2111                 u32 t_fair;
2112
2113                 /* Enable rate shaping and fairness */
2114                 m_cmng_port->flags.cmng_vn_enable = 1;
2115                 m_cmng_port->flags.fairness_enable = en_fness ? 1 : 0;
2116                 m_cmng_port->flags.rate_shaping_enable = 1;
2117
2118                 if (!en_fness)
2119                         DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2120                            "  fairness will be disabled\n");
2121
2122                 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2123                 m_cmng_port->rs_vars.rs_periodic_timeout =
2124                                                 RS_PERIODIC_TIMEOUT_USEC / 4;
2125
2126                 /* this is the threshold below which no timer arming will occur
2127                    1.25 coefficient is for the threshold to be a little bigger
2128                    than the real time, to compensate for timer in-accuracy */
2129                 m_cmng_port->rs_vars.rs_threshold =
2130                                 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2131
2132                 /* resolution of fairness timer */
2133                 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2134                 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2135                 t_fair = T_FAIR_COEF / port_rate;
2136
2137                 /* this is the threshold below which we won't arm
2138                    the timer anymore */
2139                 m_cmng_port->fair_vars.fair_threshold = QM_ARB_BYTES;
2140
2141                 /* we multiply by 1e3/8 to get bytes/msec.
2142                    We don't want the credits to pass a credit
2143                    of the T_FAIR*FAIR_MEM (algorithm resolution) */
2144                 m_cmng_port->fair_vars.upper_bound =
2145                                                 r_param * t_fair * FAIR_MEM;
2146                 /* since each tick is 4 usec */
2147                 m_cmng_port->fair_vars.fairness_timeout =
2148                                                 fair_periodic_timeout_usec / 4;
2149
2150         } else {
2151                 /* Disable rate shaping and fairness */
2152                 m_cmng_port->flags.cmng_vn_enable = 0;
2153                 m_cmng_port->flags.fairness_enable = 0;
2154                 m_cmng_port->flags.rate_shaping_enable = 0;
2155
2156                 DP(NETIF_MSG_IFUP,
2157                    "Single function mode  minmax will be disabled\n");
2158         }
2159
2160         /* Store it to internal memory */
2161         for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
2162                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2163                        XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
2164                        ((u32 *)(m_cmng_port))[i]);
2165 }
2166
2167 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
2168                                    u32 wsum, u16 port_rate,
2169                                  struct cmng_struct_per_port *m_cmng_port)
2170 {
2171         struct rate_shaping_vars_per_vn m_rs_vn;
2172         struct fairness_vars_per_vn m_fair_vn;
2173         u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2174         u16 vn_min_rate, vn_max_rate;
2175         int i;
2176
2177         /* If function is hidden - set min and max to zeroes */
2178         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2179                 vn_min_rate = 0;
2180                 vn_max_rate = 0;
2181
2182         } else {
2183                 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2184                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2185                 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2186                    if current min rate is zero - set it to 1.
2187                    This is a requirement of the algorithm. */
2188                 if ((vn_min_rate == 0) && wsum)
2189                         vn_min_rate = DEF_MIN_RATE;
2190                 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2191                                 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2192         }
2193
2194         DP(NETIF_MSG_IFUP, "func %d: vn_min_rate=%d  vn_max_rate=%d  "
2195            "wsum=%d\n", func, vn_min_rate, vn_max_rate, wsum);
2196
2197         memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2198         memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2199
2200         /* global vn counter - maximal Mbps for this vn */
2201         m_rs_vn.vn_counter.rate = vn_max_rate;
2202
2203         /* quota - number of bytes transmitted in this period */
2204         m_rs_vn.vn_counter.quota =
2205                                 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2206
2207 #ifdef BNX2X_PER_PROT_QOS
2208         /* per protocol counter */
2209         for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) {
2210                 /* maximal Mbps for this protocol */
2211                 m_rs_vn.protocol_counters[protocol].rate =
2212                                                 protocol_max_rate[protocol];
2213                 /* the quota in each timer period -
2214                    number of bytes transmitted in this period */
2215                 m_rs_vn.protocol_counters[protocol].quota =
2216                         (u32)(rs_periodic_timeout_usec *
2217                           ((double)m_rs_vn.
2218                                    protocol_counters[protocol].rate/8));
2219         }
2220 #endif
2221
2222         if (wsum) {
2223                 /* credit for each period of the fairness algorithm:
2224                    number of bytes in T_FAIR (the vn share the port rate).
2225                    wsum should not be larger than 10000, thus
2226                    T_FAIR_COEF / (8 * wsum) will always be grater than zero */
2227                 m_fair_vn.vn_credit_delta =
2228                         max((u64)(vn_min_rate * (T_FAIR_COEF / (8 * wsum))),
2229                             (u64)(m_cmng_port->fair_vars.fair_threshold * 2));
2230                 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2231                    m_fair_vn.vn_credit_delta);
2232         }
2233
2234 #ifdef BNX2X_PER_PROT_QOS
2235         do {
2236                 u32 protocolWeightSum = 0;
2237
2238                 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++)
2239                         protocolWeightSum +=
2240                                         drvInit.protocol_min_rate[protocol];
2241                 /* per protocol counter -
2242                    NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */
2243                 if (protocolWeightSum > 0) {
2244                         for (protocol = 0;
2245                              protocol < NUM_OF_PROTOCOLS; protocol++)
2246                                 /* credit for each period of the
2247                                    fairness algorithm - number of bytes in
2248                                    T_FAIR (the protocol share the vn rate) */
2249                                 m_fair_vn.protocol_credit_delta[protocol] =
2250                                         (u32)((vn_min_rate / 8) * t_fair *
2251                                         protocol_min_rate / protocolWeightSum);
2252                 }
2253         } while (0);
2254 #endif
2255
2256         /* Store it to internal memory */
2257         for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2258                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2259                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2260                        ((u32 *)(&m_rs_vn))[i]);
2261
2262         for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2263                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2264                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2265                        ((u32 *)(&m_fair_vn))[i]);
2266 }
2267
2268 /* This function is called upon link interrupt */
2269 static void bnx2x_link_attn(struct bnx2x *bp)
2270 {
2271         int vn;
2272
2273         /* Make sure that we are synced with the current statistics */
2274         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2275
2276         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2277
2278         if (bp->link_vars.link_up) {
2279
2280                 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2281                         struct host_port_stats *pstats;
2282
2283                         pstats = bnx2x_sp(bp, port_stats);
2284                         /* reset old bmac stats */
2285                         memset(&(pstats->mac_stx[0]), 0,
2286                                sizeof(struct mac_stx));
2287                 }
2288                 if ((bp->state == BNX2X_STATE_OPEN) ||
2289                     (bp->state == BNX2X_STATE_DISABLED))
2290                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2291         }
2292
2293         /* indicate link status */
2294         bnx2x_link_report(bp);
2295
2296         if (IS_E1HMF(bp)) {
2297                 int func;
2298
2299                 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2300                         if (vn == BP_E1HVN(bp))
2301                                 continue;
2302
2303                         func = ((vn << 1) | BP_PORT(bp));
2304
2305                         /* Set the attention towards other drivers
2306                            on the same port */
2307                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2308                                (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2309                 }
2310         }
2311
2312         if (CHIP_IS_E1H(bp) && (bp->link_vars.line_speed > 0)) {
2313                 struct cmng_struct_per_port m_cmng_port;
2314                 u32 wsum;
2315                 int port = BP_PORT(bp);
2316
2317                 /* Init RATE SHAPING and FAIRNESS contexts */
2318                 wsum = bnx2x_calc_vn_wsum(bp);
2319                 bnx2x_init_port_minmax(bp, (int)wsum,
2320                                         bp->link_vars.line_speed,
2321                                         &m_cmng_port);
2322                 if (IS_E1HMF(bp))
2323                         for (vn = VN_0; vn < E1HVN_MAX; vn++)
2324                                 bnx2x_init_vn_minmax(bp, 2*vn + port,
2325                                         wsum, bp->link_vars.line_speed,
2326                                                      &m_cmng_port);
2327         }
2328 }
2329
2330 static void bnx2x__link_status_update(struct bnx2x *bp)
2331 {
2332         if (bp->state != BNX2X_STATE_OPEN)
2333                 return;
2334
2335         bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2336
2337         if (bp->link_vars.link_up)
2338                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2339         else
2340                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2341
2342         /* indicate link status */
2343         bnx2x_link_report(bp);
2344 }
2345
2346 static void bnx2x_pmf_update(struct bnx2x *bp)
2347 {
2348         int port = BP_PORT(bp);
2349         u32 val;
2350
2351         bp->port.pmf = 1;
2352         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2353
2354         /* enable nig attention */
2355         val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2356         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2357         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2358
2359         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2360 }
2361
2362 /* end of Link */
2363
2364 /* slow path */
2365
2366 /*
2367  * General service functions
2368  */
2369
2370 /* the slow path queue is odd since completions arrive on the fastpath ring */
2371 static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2372                          u32 data_hi, u32 data_lo, int common)
2373 {
2374         int func = BP_FUNC(bp);
2375
2376         DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2377            "SPQE (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
2378            (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2379            (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2380            HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2381
2382 #ifdef BNX2X_STOP_ON_ERROR
2383         if (unlikely(bp->panic))
2384                 return -EIO;
2385 #endif
2386
2387         spin_lock_bh(&bp->spq_lock);
2388
2389         if (!bp->spq_left) {
2390                 BNX2X_ERR("BUG! SPQ ring full!\n");
2391                 spin_unlock_bh(&bp->spq_lock);
2392                 bnx2x_panic();
2393                 return -EBUSY;
2394         }
2395
2396         /* CID needs port number to be encoded int it */
2397         bp->spq_prod_bd->hdr.conn_and_cmd_data =
2398                         cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2399                                      HW_CID(bp, cid)));
2400         bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
2401         if (common)
2402                 bp->spq_prod_bd->hdr.type |=
2403                         cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2404
2405         bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2406         bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
2407
2408         bp->spq_left--;
2409
2410         if (bp->spq_prod_bd == bp->spq_last_bd) {
2411                 bp->spq_prod_bd = bp->spq;
2412                 bp->spq_prod_idx = 0;
2413                 DP(NETIF_MSG_TIMER, "end of spq\n");
2414
2415         } else {
2416                 bp->spq_prod_bd++;
2417                 bp->spq_prod_idx++;
2418         }
2419
2420         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2421                bp->spq_prod_idx);
2422
2423         spin_unlock_bh(&bp->spq_lock);
2424         return 0;
2425 }
2426
2427 /* acquire split MCP access lock register */
2428 static int bnx2x_acquire_alr(struct bnx2x *bp)
2429 {
2430         u32 i, j, val;
2431         int rc = 0;
2432
2433         might_sleep();
2434         i = 100;
2435         for (j = 0; j < i*10; j++) {
2436                 val = (1UL << 31);
2437                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2438                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2439                 if (val & (1L << 31))
2440                         break;
2441
2442                 msleep(5);
2443         }
2444         if (!(val & (1L << 31))) {
2445                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2446                 rc = -EBUSY;
2447         }
2448
2449         return rc;
2450 }
2451
2452 /* release split MCP access lock register */
2453 static void bnx2x_release_alr(struct bnx2x *bp)
2454 {
2455         u32 val = 0;
2456
2457         REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2458 }
2459
2460 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2461 {
2462         struct host_def_status_block *def_sb = bp->def_status_blk;
2463         u16 rc = 0;
2464
2465         barrier(); /* status block is written to by the chip */
2466         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2467                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2468                 rc |= 1;
2469         }
2470         if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2471                 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2472                 rc |= 2;
2473         }
2474         if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2475                 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2476                 rc |= 4;
2477         }
2478         if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2479                 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2480                 rc |= 8;
2481         }
2482         if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2483                 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2484                 rc |= 16;
2485         }
2486         return rc;
2487 }
2488
2489 /*
2490  * slow path service functions
2491  */
2492
2493 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2494 {
2495         int port = BP_PORT(bp);
2496         u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2497                        COMMAND_REG_ATTN_BITS_SET);
2498         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2499                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
2500         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2501                                        NIG_REG_MASK_INTERRUPT_PORT0;
2502         u32 aeu_mask;
2503
2504         if (bp->attn_state & asserted)
2505                 BNX2X_ERR("IGU ERROR\n");
2506
2507         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2508         aeu_mask = REG_RD(bp, aeu_addr);
2509
2510         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
2511            aeu_mask, asserted);
2512         aeu_mask &= ~(asserted & 0xff);
2513         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2514
2515         REG_WR(bp, aeu_addr, aeu_mask);
2516         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2517
2518         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2519         bp->attn_state |= asserted;
2520         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2521
2522         if (asserted & ATTN_HARD_WIRED_MASK) {
2523                 if (asserted & ATTN_NIG_FOR_FUNC) {
2524
2525                         bnx2x_acquire_phy_lock(bp);
2526
2527                         /* save nig interrupt mask */
2528                         bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
2529                         REG_WR(bp, nig_int_mask_addr, 0);
2530
2531                         bnx2x_link_attn(bp);
2532
2533                         /* handle unicore attn? */
2534                 }
2535                 if (asserted & ATTN_SW_TIMER_4_FUNC)
2536                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2537
2538                 if (asserted & GPIO_2_FUNC)
2539                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2540
2541                 if (asserted & GPIO_3_FUNC)
2542                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2543
2544                 if (asserted & GPIO_4_FUNC)
2545                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2546
2547                 if (port == 0) {
2548                         if (asserted & ATTN_GENERAL_ATTN_1) {
2549                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2550                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2551                         }
2552                         if (asserted & ATTN_GENERAL_ATTN_2) {
2553                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2554                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2555                         }
2556                         if (asserted & ATTN_GENERAL_ATTN_3) {
2557                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2558                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2559                         }
2560                 } else {
2561                         if (asserted & ATTN_GENERAL_ATTN_4) {
2562                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2563                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2564                         }
2565                         if (asserted & ATTN_GENERAL_ATTN_5) {
2566                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2567                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2568                         }
2569                         if (asserted & ATTN_GENERAL_ATTN_6) {
2570                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2571                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2572                         }
2573                 }
2574
2575         } /* if hardwired */
2576
2577         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2578            asserted, hc_addr);
2579         REG_WR(bp, hc_addr, asserted);
2580
2581         /* now set back the mask */
2582         if (asserted & ATTN_NIG_FOR_FUNC) {
2583                 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
2584                 bnx2x_release_phy_lock(bp);
2585         }
2586 }
2587
2588 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2589 {
2590         int port = BP_PORT(bp);
2591         int reg_offset;
2592         u32 val;
2593
2594         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2595                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2596
2597         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2598
2599                 val = REG_RD(bp, reg_offset);
2600                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2601                 REG_WR(bp, reg_offset, val);
2602
2603                 BNX2X_ERR("SPIO5 hw attention\n");
2604
2605                 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
2606                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
2607                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2608                         /* Fan failure attention */
2609
2610                         /* The PHY reset is controlled by GPIO 1 */
2611                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2612                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2613                         /* Low power mode is controlled by GPIO 2 */
2614                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2615                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2616                         /* mark the failure */
2617                         bp->link_params.ext_phy_config &=
2618                                         ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2619                         bp->link_params.ext_phy_config |=
2620                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2621                         SHMEM_WR(bp,
2622                                  dev_info.port_hw_config[port].
2623                                                         external_phy_config,
2624                                  bp->link_params.ext_phy_config);
2625                         /* log the failure */
2626                         printk(KERN_ERR PFX "Fan Failure on Network"
2627                                " Controller %s has caused the driver to"
2628                                " shutdown the card to prevent permanent"
2629                                " damage.  Please contact Dell Support for"
2630                                " assistance\n", bp->dev->name);
2631                         break;
2632
2633                 default:
2634                         break;
2635                 }
2636         }
2637
2638         if (attn & HW_INTERRUT_ASSERT_SET_0) {
2639
2640                 val = REG_RD(bp, reg_offset);
2641                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2642                 REG_WR(bp, reg_offset, val);
2643
2644                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2645                           (attn & HW_INTERRUT_ASSERT_SET_0));
2646                 bnx2x_panic();
2647         }
2648 }
2649
2650 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2651 {
2652         u32 val;
2653
2654         if (attn & BNX2X_DOORQ_ASSERT) {
2655
2656                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2657                 BNX2X_ERR("DB hw attention 0x%x\n", val);
2658                 /* DORQ discard attention */
2659                 if (val & 0x2)
2660                         BNX2X_ERR("FATAL error from DORQ\n");
2661         }
2662
2663         if (attn & HW_INTERRUT_ASSERT_SET_1) {
2664
2665                 int port = BP_PORT(bp);
2666                 int reg_offset;
2667
2668                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2669                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2670
2671                 val = REG_RD(bp, reg_offset);
2672                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2673                 REG_WR(bp, reg_offset, val);
2674
2675                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2676                           (attn & HW_INTERRUT_ASSERT_SET_1));
2677                 bnx2x_panic();
2678         }
2679 }
2680
2681 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2682 {
2683         u32 val;
2684
2685         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
2686
2687                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
2688                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
2689                 /* CFC error attention */
2690                 if (val & 0x2)
2691                         BNX2X_ERR("FATAL error from CFC\n");
2692         }
2693
2694         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
2695
2696                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
2697                 BNX2X_ERR("PXP hw attention 0x%x\n", val);
2698                 /* RQ_USDMDP_FIFO_OVERFLOW */
2699                 if (val & 0x18000)
2700                         BNX2X_ERR("FATAL error from PXP\n");
2701         }
2702
2703         if (attn & HW_INTERRUT_ASSERT_SET_2) {
2704
2705                 int port = BP_PORT(bp);
2706                 int reg_offset;
2707
2708                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
2709                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
2710
2711                 val = REG_RD(bp, reg_offset);
2712                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
2713                 REG_WR(bp, reg_offset, val);
2714
2715                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2716                           (attn & HW_INTERRUT_ASSERT_SET_2));
2717                 bnx2x_panic();
2718         }
2719 }
2720
2721 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2722 {
2723         u32 val;
2724
2725         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
2726
2727                 if (attn & BNX2X_PMF_LINK_ASSERT) {
2728                         int func = BP_FUNC(bp);
2729
2730                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2731                         bnx2x__link_status_update(bp);
2732                         if (SHMEM_RD(bp, func_mb[func].drv_status) &
2733                                                         DRV_STATUS_PMF)
2734                                 bnx2x_pmf_update(bp);
2735
2736                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2737
2738                         BNX2X_ERR("MC assert!\n");
2739                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
2740                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
2741                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
2742                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
2743                         bnx2x_panic();
2744
2745                 } else if (attn & BNX2X_MCP_ASSERT) {
2746
2747                         BNX2X_ERR("MCP assert!\n");
2748                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
2749                         bnx2x_fw_dump(bp);
2750
2751                 } else
2752                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
2753         }
2754
2755         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2756                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2757                 if (attn & BNX2X_GRC_TIMEOUT) {
2758                         val = CHIP_IS_E1H(bp) ?
2759                                 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
2760                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
2761                 }
2762                 if (attn & BNX2X_GRC_RSV) {
2763                         val = CHIP_IS_E1H(bp) ?
2764                                 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
2765                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
2766                 }
2767                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
2768         }
2769 }
2770
2771 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2772 {
2773         struct attn_route attn;
2774         struct attn_route group_mask;
2775         int port = BP_PORT(bp);
2776         int index;
2777         u32 reg_addr;
2778         u32 val;
2779         u32 aeu_mask;
2780
2781         /* need to take HW lock because MCP or other port might also
2782            try to handle this event */
2783         bnx2x_acquire_alr(bp);
2784
2785         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2786         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2787         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2788         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2789         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
2790            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
2791
2792         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2793                 if (deasserted & (1 << index)) {
2794                         group_mask = bp->attn_group[index];
2795
2796                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
2797                            index, group_mask.sig[0], group_mask.sig[1],
2798                            group_mask.sig[2], group_mask.sig[3]);
2799
2800                         bnx2x_attn_int_deasserted3(bp,
2801                                         attn.sig[3] & group_mask.sig[3]);
2802                         bnx2x_attn_int_deasserted1(bp,
2803                                         attn.sig[1] & group_mask.sig[1]);
2804                         bnx2x_attn_int_deasserted2(bp,
2805                                         attn.sig[2] & group_mask.sig[2]);
2806                         bnx2x_attn_int_deasserted0(bp,
2807                                         attn.sig[0] & group_mask.sig[0]);
2808
2809                         if ((attn.sig[0] & group_mask.sig[0] &
2810                                                 HW_PRTY_ASSERT_SET_0) ||
2811                             (attn.sig[1] & group_mask.sig[1] &
2812                                                 HW_PRTY_ASSERT_SET_1) ||
2813                             (attn.sig[2] & group_mask.sig[2] &
2814                                                 HW_PRTY_ASSERT_SET_2))
2815                                 BNX2X_ERR("FATAL HW block parity attention\n");
2816                 }
2817         }
2818
2819         bnx2x_release_alr(bp);
2820
2821         reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2822
2823         val = ~deasserted;
2824         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2825            val, reg_addr);
2826         REG_WR(bp, reg_addr, val);
2827
2828         if (~bp->attn_state & deasserted)
2829                 BNX2X_ERR("IGU ERROR\n");
2830
2831         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2832                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
2833
2834         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2835         aeu_mask = REG_RD(bp, reg_addr);
2836
2837         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
2838            aeu_mask, deasserted);
2839         aeu_mask |= (deasserted & 0xff);
2840         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2841
2842         REG_WR(bp, reg_addr, aeu_mask);
2843         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2844
2845         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2846         bp->attn_state &= ~deasserted;
2847         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2848 }
2849
2850 static void bnx2x_attn_int(struct bnx2x *bp)
2851 {
2852         /* read local copy of bits */
2853         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
2854                                                                 attn_bits);
2855         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
2856                                                                 attn_bits_ack);
2857         u32 attn_state = bp->attn_state;
2858
2859         /* look for changed bits */
2860         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
2861         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
2862
2863         DP(NETIF_MSG_HW,
2864            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
2865            attn_bits, attn_ack, asserted, deasserted);
2866
2867         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
2868                 BNX2X_ERR("BAD attention state\n");
2869
2870         /* handle bits that were raised */
2871         if (asserted)
2872                 bnx2x_attn_int_asserted(bp, asserted);
2873
2874         if (deasserted)
2875                 bnx2x_attn_int_deasserted(bp, deasserted);
2876 }
2877
2878 static void bnx2x_sp_task(struct work_struct *work)
2879 {
2880         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
2881         u16 status;
2882
2883
2884         /* Return here if interrupt is disabled */
2885         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2886                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2887                 return;
2888         }
2889
2890         status = bnx2x_update_dsb_idx(bp);
2891 /*      if (status == 0)                                     */
2892 /*              BNX2X_ERR("spurious slowpath interrupt!\n"); */
2893
2894         DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
2895
2896         /* HW attentions */
2897         if (status & 0x1)
2898                 bnx2x_attn_int(bp);
2899
2900         /* CStorm events: query_stats, port delete ramrod */
2901         if (status & 0x2)
2902                 bp->stats_pending = 0;
2903
2904         bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
2905                      IGU_INT_NOP, 1);
2906         bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2907                      IGU_INT_NOP, 1);
2908         bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2909                      IGU_INT_NOP, 1);
2910         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2911                      IGU_INT_NOP, 1);
2912         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2913                      IGU_INT_ENABLE, 1);
2914
2915 }
2916
2917 static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2918 {
2919         struct net_device *dev = dev_instance;
2920         struct bnx2x *bp = netdev_priv(dev);
2921
2922         /* Return here if interrupt is disabled */
2923         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2924                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2925                 return IRQ_HANDLED;
2926         }
2927
2928         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
2929
2930 #ifdef BNX2X_STOP_ON_ERROR
2931         if (unlikely(bp->panic))
2932                 return IRQ_HANDLED;
2933 #endif
2934
2935         queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
2936
2937         return IRQ_HANDLED;
2938 }
2939
2940 /* end of slow path */
2941
2942 /* Statistics */
2943
2944 /****************************************************************************
2945 * Macros
2946 ****************************************************************************/
2947
2948 /* sum[hi:lo] += add[hi:lo] */
2949 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2950         do { \
2951                 s_lo += a_lo; \
2952                 s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
2953         } while (0)
2954
2955 /* difference = minuend - subtrahend */
2956 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2957         do { \
2958                 if (m_lo < s_lo) { \
2959                         /* underflow */ \
2960                         d_hi = m_hi - s_hi; \
2961                         if (d_hi > 0) { \
2962                                 /* we can 'loan' 1 */ \
2963                                 d_hi--; \
2964                                 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2965                         } else { \
2966                                 /* m_hi <= s_hi */ \
2967                                 d_hi = 0; \
2968                                 d_lo = 0; \
2969                         } \
2970                 } else { \
2971                         /* m_lo >= s_lo */ \
2972                         if (m_hi < s_hi) { \
2973                                 d_hi = 0; \
2974                                 d_lo = 0; \
2975                         } else { \
2976                                 /* m_hi >= s_hi */ \
2977                                 d_hi = m_hi - s_hi; \
2978                                 d_lo = m_lo - s_lo; \
2979                         } \
2980                 } \
2981         } while (0)
2982
2983 #define UPDATE_STAT64(s, t) \
2984         do { \
2985                 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
2986                         diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
2987                 pstats->mac_stx[0].t##_hi = new->s##_hi; \
2988                 pstats->mac_stx[0].t##_lo = new->s##_lo; \
2989                 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
2990                        pstats->mac_stx[1].t##_lo, diff.lo); \
2991         } while (0)
2992
2993 #define UPDATE_STAT64_NIG(s, t) \
2994         do { \
2995                 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
2996                         diff.lo, new->s##_lo, old->s##_lo); \
2997                 ADD_64(estats->t##_hi, diff.hi, \
2998                        estats->t##_lo, diff.lo); \
2999         } while (0)
3000
3001 /* sum[hi:lo] += add */
3002 #define ADD_EXTEND_64(s_hi, s_lo, a) \
3003         do { \
3004                 s_lo += a; \
3005                 s_hi += (s_lo < a) ? 1 : 0; \
3006         } while (0)
3007
3008 #define UPDATE_EXTEND_STAT(s) \
3009         do { \
3010                 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
3011                               pstats->mac_stx[1].s##_lo, \
3012                               new->s); \
3013         } while (0)
3014
3015 #define UPDATE_EXTEND_TSTAT(s, t) \
3016         do { \
3017                 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
3018                 old_tclient->s = le32_to_cpu(tclient->s); \
3019                 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
3020         } while (0)
3021
3022 #define UPDATE_EXTEND_XSTAT(s, t) \
3023         do { \
3024                 diff = le32_to_cpu(xclient->s) - old_xclient->s; \
3025                 old_xclient->s = le32_to_cpu(xclient->s); \
3026                 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
3027         } while (0)
3028
3029 /*
3030  * General service functions
3031  */
3032
3033 static inline long bnx2x_hilo(u32 *hiref)
3034 {
3035         u32 lo = *(hiref + 1);
3036 #if (BITS_PER_LONG == 64)
3037         u32 hi = *hiref;
3038
3039         return HILO_U64(hi, lo);
3040 #else
3041         return lo;
3042 #endif
3043 }
3044
3045 /*
3046  * Init service functions
3047  */
3048
3049 static void bnx2x_storm_stats_post(struct bnx2x *bp)
3050 {
3051         if (!bp->stats_pending) {
3052                 struct eth_query_ramrod_data ramrod_data = {0};
3053                 int rc;
3054
3055                 ramrod_data.drv_counter = bp->stats_counter++;
3056                 ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
3057                 ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp));
3058
3059                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
3060                                    ((u32 *)&ramrod_data)[1],
3061                                    ((u32 *)&ramrod_data)[0], 0);
3062                 if (rc == 0) {
3063                         /* stats ramrod has it's own slot on the spq */
3064                         bp->spq_left++;
3065                         bp->stats_pending = 1;
3066                 }
3067         }
3068 }
3069
3070 static void bnx2x_stats_init(struct bnx2x *bp)
3071 {
3072         int port = BP_PORT(bp);
3073
3074         bp->executer_idx = 0;
3075         bp->stats_counter = 0;
3076
3077         /* port stats */
3078         if (!BP_NOMCP(bp))
3079                 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
3080         else
3081                 bp->port.port_stx = 0;
3082         DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
3083
3084         memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3085         bp->port.old_nig_stats.brb_discard =
3086                         REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3087         bp->port.old_nig_stats.brb_truncate =
3088                         REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3089         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3090                     &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3091         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
3092                     &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
3093
3094         /* function stats */
3095         memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3096         memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
3097         memset(&bp->old_xclient, 0, sizeof(struct xstorm_per_client_stats));
3098         memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
3099
3100         bp->stats_state = STATS_STATE_DISABLED;
3101         if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
3102                 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3103 }
3104
3105 static void bnx2x_hw_stats_post(struct bnx2x *bp)
3106 {
3107         struct dmae_command *dmae = &bp->stats_dmae;
3108         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3109
3110         *stats_comp = DMAE_COMP_VAL;
3111
3112         /* loader */
3113         if (bp->executer_idx) {
3114                 int loader_idx = PMF_DMAE_C(bp);
3115
3116                 memset(dmae, 0, sizeof(struct dmae_command));
3117
3118                 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3119                                 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3120                                 DMAE_CMD_DST_RESET |
3121 #ifdef __BIG_ENDIAN
3122                                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3123 #else
3124                                 DMAE_CMD_ENDIANITY_DW_SWAP |
3125 #endif
3126                                 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3127                                                DMAE_CMD_PORT_0) |
3128                                 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3129                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3130                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3131                 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3132                                      sizeof(struct dmae_command) *
3133                                      (loader_idx + 1)) >> 2;
3134                 dmae->dst_addr_hi = 0;
3135                 dmae->len = sizeof(struct dmae_command) >> 2;
3136                 if (CHIP_IS_E1(bp))
3137                         dmae->len--;
3138                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3139                 dmae->comp_addr_hi = 0;
3140                 dmae->comp_val = 1;
3141
3142                 *stats_comp = 0;
3143                 bnx2x_post_dmae(bp, dmae, loader_idx);
3144
3145         } else if (bp->func_stx) {
3146                 *stats_comp = 0;
3147                 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3148         }
3149 }
3150
3151 static int bnx2x_stats_comp(struct bnx2x *bp)
3152 {
3153         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3154         int cnt = 10;
3155
3156         might_sleep();
3157         while (*stats_comp != DMAE_COMP_VAL) {
3158                 if (!cnt) {
3159                         BNX2X_ERR("timeout waiting for stats finished\n");
3160                         break;
3161                 }
3162                 cnt--;
3163                 msleep(1);
3164         }
3165         return 1;
3166 }
3167
3168 /*
3169  * Statistics service functions
3170  */
3171
3172 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3173 {
3174         struct dmae_command *dmae;
3175         u32 opcode;
3176         int loader_idx = PMF_DMAE_C(bp);
3177         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3178
3179         /* sanity */
3180         if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3181                 BNX2X_ERR("BUG!\n");
3182                 return;
3183         }
3184
3185         bp->executer_idx = 0;
3186
3187         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3188                   DMAE_CMD_C_ENABLE |
3189                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3190 #ifdef __BIG_ENDIAN
3191                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3192 #else
3193                   DMAE_CMD_ENDIANITY_DW_SWAP |
3194 #endif
3195                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3196                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3197
3198         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3199         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3200         dmae->src_addr_lo = bp->port.port_stx >> 2;
3201         dmae->src_addr_hi = 0;
3202         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3203         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3204         dmae->len = DMAE_LEN32_RD_MAX;
3205         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3206         dmae->comp_addr_hi = 0;
3207         dmae->comp_val = 1;
3208
3209         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3210         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3211         dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3212         dmae->src_addr_hi = 0;
3213         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3214                                    DMAE_LEN32_RD_MAX * 4);
3215         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3216                                    DMAE_LEN32_RD_MAX * 4);
3217         dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3218         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3219         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3220         dmae->comp_val = DMAE_COMP_VAL;
3221
3222         *stats_comp = 0;
3223         bnx2x_hw_stats_post(bp);
3224         bnx2x_stats_comp(bp);
3225 }
3226
3227 static void bnx2x_port_stats_init(struct bnx2x *bp)
3228 {
3229         struct dmae_command *dmae;
3230         int port = BP_PORT(bp);
3231         int vn = BP_E1HVN(bp);
3232         u32 opcode;
3233         int loader_idx = PMF_DMAE_C(bp);
3234         u32 mac_addr;
3235         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3236
3237         /* sanity */
3238         if (!bp->link_vars.link_up || !bp->port.pmf) {
3239                 BNX2X_ERR("BUG!\n");
3240                 return;
3241         }
3242
3243         bp->executer_idx = 0;
3244
3245         /* MCP */
3246         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3247                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3248                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3249 #ifdef __BIG_ENDIAN
3250                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3251 #else
3252                   DMAE_CMD_ENDIANITY_DW_SWAP |
3253 #endif
3254                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3255                   (vn << DMAE_CMD_E1HVN_SHIFT));
3256
3257         if (bp->port.port_stx) {
3258
3259                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3260                 dmae->opcode = opcode;
3261                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3262                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3263                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3264                 dmae->dst_addr_hi = 0;
3265                 dmae->len = sizeof(struct host_port_stats) >> 2;
3266                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3267                 dmae->comp_addr_hi = 0;
3268                 dmae->comp_val = 1;
3269         }
3270
3271         if (bp->func_stx) {
3272
3273                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3274                 dmae->opcode = opcode;
3275                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3276                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3277                 dmae->dst_addr_lo = bp->func_stx >> 2;
3278                 dmae->dst_addr_hi = 0;
3279                 dmae->len = sizeof(struct host_func_stats) >> 2;
3280                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3281                 dmae->comp_addr_hi = 0;
3282                 dmae->comp_val = 1;
3283         }
3284
3285         /* MAC */
3286         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3287                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3288                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3289 #ifdef __BIG_ENDIAN
3290                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3291 #else
3292                   DMAE_CMD_ENDIANITY_DW_SWAP |
3293 #endif
3294                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3295                   (vn << DMAE_CMD_E1HVN_SHIFT));
3296
3297         if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
3298
3299                 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3300                                    NIG_REG_INGRESS_BMAC0_MEM);
3301
3302                 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3303                    BIGMAC_REGISTER_TX_STAT_GTBYT */
3304                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3305                 dmae->opcode = opcode;
3306                 dmae->src_addr_lo = (mac_addr +
3307                                      BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3308                 dmae->src_addr_hi = 0;
3309                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3310                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3311                 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3312                              BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3313                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3314                 dmae->comp_addr_hi = 0;
3315                 dmae->comp_val = 1;
3316
3317                 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3318                    BIGMAC_REGISTER_RX_STAT_GRIPJ */
3319                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3320                 dmae->opcode = opcode;
3321                 dmae->src_addr_lo = (mac_addr +
3322                                      BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3323                 dmae->src_addr_hi = 0;
3324                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3325                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3326                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3327                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3328                 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3329                              BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3330                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3331                 dmae->comp_addr_hi = 0;
3332                 dmae->comp_val = 1;
3333
3334         } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
3335
3336                 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3337
3338                 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3339                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3340                 dmae->opcode = opcode;
3341                 dmae->src_addr_lo = (mac_addr +
3342                                      EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3343                 dmae->src_addr_hi = 0;
3344                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3345                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3346                 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3347                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3348                 dmae->comp_addr_hi = 0;
3349                 dmae->comp_val = 1;
3350
3351                 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3352                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3353                 dmae->opcode = opcode;
3354                 dmae->src_addr_lo = (mac_addr +
3355                                      EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3356                 dmae->src_addr_hi = 0;
3357                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3358                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3359                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3360                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3361                 dmae->len = 1;
3362                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3363                 dmae->comp_addr_hi = 0;
3364                 dmae->comp_val = 1;
3365
3366                 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3367                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3368                 dmae->opcode = opcode;
3369                 dmae->src_addr_lo = (mac_addr +
3370                                      EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3371                 dmae->src_addr_hi = 0;
3372                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3373                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3374                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3375                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3376                 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3377                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3378                 dmae->comp_addr_hi = 0;
3379                 dmae->comp_val = 1;
3380         }
3381
3382         /* NIG */
3383         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3384         dmae->opcode = opcode;
3385         dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3386                                     NIG_REG_STAT0_BRB_DISCARD) >> 2;
3387         dmae->src_addr_hi = 0;
3388         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
3389         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
3390         dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
3391         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3392         dmae->comp_addr_hi = 0;
3393         dmae->comp_val = 1;
3394
3395         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3396         dmae->opcode = opcode;
3397         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
3398                                     NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
3399         dmae->src_addr_hi = 0;
3400         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3401                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3402         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3403                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3404         dmae->len = (2*sizeof(u32)) >> 2;
3405         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3406         dmae->comp_addr_hi = 0;
3407         dmae->comp_val = 1;
3408
3409         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3410         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3411                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3412                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3413 #ifdef __BIG_ENDIAN
3414                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3415 #else
3416                         DMAE_CMD_ENDIANITY_DW_SWAP |
3417 #endif
3418                         (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3419                         (vn << DMAE_CMD_E1HVN_SHIFT));
3420         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
3421                                     NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
3422         dmae->src_addr_hi = 0;
3423         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3424                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3425         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3426                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3427         dmae->len = (2*sizeof(u32)) >> 2;
3428         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3429         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3430         dmae->comp_val = DMAE_COMP_VAL;
3431
3432         *stats_comp = 0;
3433 }
3434
3435 static void bnx2x_func_stats_init(struct bnx2x *bp)
3436 {
3437         struct dmae_command *dmae = &bp->stats_dmae;
3438         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3439
3440         /* sanity */
3441         if (!bp->func_stx) {
3442                 BNX2X_ERR("BUG!\n");
3443                 return;
3444         }
3445
3446         bp->executer_idx = 0;
3447         memset(dmae, 0, sizeof(struct dmae_command));
3448
3449         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3450                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3451                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3452 #ifdef __BIG_ENDIAN
3453                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3454 #else
3455                         DMAE_CMD_ENDIANITY_DW_SWAP |
3456 #endif
3457                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3458                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3459         dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3460         dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3461         dmae->dst_addr_lo = bp->func_stx >> 2;
3462         dmae->dst_addr_hi = 0;
3463         dmae->len = sizeof(struct host_func_stats) >> 2;
3464         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3465         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3466         dmae->comp_val = DMAE_COMP_VAL;
3467
3468         *stats_comp = 0;
3469 }
3470
3471 static void bnx2x_stats_start(struct bnx2x *bp)
3472 {
3473         if (bp->port.pmf)
3474                 bnx2x_port_stats_init(bp);
3475
3476         else if (bp->func_stx)
3477                 bnx2x_func_stats_init(bp);
3478
3479         bnx2x_hw_stats_post(bp);
3480         bnx2x_storm_stats_post(bp);
3481 }
3482
3483 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
3484 {
3485         bnx2x_stats_comp(bp);
3486         bnx2x_stats_pmf_update(bp);
3487         bnx2x_stats_start(bp);
3488 }
3489
3490 static void bnx2x_stats_restart(struct bnx2x *bp)
3491 {
3492         bnx2x_stats_comp(bp);
3493         bnx2x_stats_start(bp);
3494 }
3495
3496 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3497 {
3498         struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
3499         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3500         struct regpair diff;
3501
3502         UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
3503         UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
3504         UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
3505         UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3506         UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3507         UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3508         UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3509         UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3510         UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived);
3511         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
3512         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
3513         UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
3514         UPDATE_STAT64(tx_stat_gt127,
3515                                 tx_stat_etherstatspkts65octetsto127octets);
3516         UPDATE_STAT64(tx_stat_gt255,
3517                                 tx_stat_etherstatspkts128octetsto255octets);
3518         UPDATE_STAT64(tx_stat_gt511,
3519                                 tx_stat_etherstatspkts256octetsto511octets);
3520         UPDATE_STAT64(tx_stat_gt1023,
3521                                 tx_stat_etherstatspkts512octetsto1023octets);
3522         UPDATE_STAT64(tx_stat_gt1518,
3523                                 tx_stat_etherstatspkts1024octetsto1522octets);
3524         UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
3525         UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
3526         UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
3527         UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
3528         UPDATE_STAT64(tx_stat_gterr,
3529                                 tx_stat_dot3statsinternalmactransmiterrors);
3530         UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
3531 }
3532
3533 static void bnx2x_emac_stats_update(struct bnx2x *bp)
3534 {
3535         struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
3536         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3537
3538         UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
3539         UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
3540         UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
3541         UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
3542         UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
3543         UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
3544         UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
3545         UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
3546         UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
3547         UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
3548         UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
3549         UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
3550         UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
3551         UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
3552         UPDATE_EXTEND_STAT(tx_stat_outxonsent);
3553         UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
3554         UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
3555         UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
3556         UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
3557         UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
3558         UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
3559         UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
3560         UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
3561         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
3562         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
3563         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
3564         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
3565         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
3566         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
3567         UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
3568         UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
3569 }
3570
3571 static int bnx2x_hw_stats_update(struct bnx2x *bp)
3572 {
3573         struct nig_stats *new = bnx2x_sp(bp, nig_stats);
3574         struct nig_stats *old = &(bp->port.old_nig_stats);
3575         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3576         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3577         struct regpair diff;
3578
3579         if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
3580                 bnx2x_bmac_stats_update(bp);
3581
3582         else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
3583                 bnx2x_emac_stats_update(bp);
3584
3585         else { /* unreached */
3586                 BNX2X_ERR("stats updated by dmae but no MAC active\n");
3587                 return -1;
3588         }
3589
3590         ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3591                       new->brb_discard - old->brb_discard);
3592         ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3593                       new->brb_truncate - old->brb_truncate);
3594
3595         UPDATE_STAT64_NIG(egress_mac_pkt0,
3596                                         etherstatspkts1024octetsto1522octets);
3597         UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
3598
3599         memcpy(old, new, sizeof(struct nig_stats));
3600
3601         memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
3602                sizeof(struct mac_stx));
3603         estats->brb_drop_hi = pstats->brb_drop_hi;
3604         estats->brb_drop_lo = pstats->brb_drop_lo;
3605
3606         pstats->host_port_stats_start = ++pstats->host_port_stats_end;
3607
3608         return 0;
3609 }
3610
3611 static int bnx2x_storm_stats_update(struct bnx2x *bp)
3612 {
3613         struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
3614         int cl_id = BP_CL_ID(bp);
3615         struct tstorm_per_port_stats *tport =
3616                                 &stats->tstorm_common.port_statistics;
3617         struct tstorm_per_client_stats *tclient =
3618                         &stats->tstorm_common.client_statistics[cl_id];
3619         struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3620         struct xstorm_per_client_stats *xclient =
3621                         &stats->xstorm_common.client_statistics[cl_id];
3622         struct xstorm_per_client_stats *old_xclient = &bp->old_xclient;
3623         struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
3624         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3625         u32 diff;
3626
3627         /* are storm stats valid? */
3628         if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
3629                                                         bp->stats_counter) {
3630                 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
3631                    "  tstorm counter (%d) != stats_counter (%d)\n",
3632                    tclient->stats_counter, bp->stats_counter);
3633                 return -1;
3634         }
3635         if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
3636                                                         bp->stats_counter) {
3637                 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
3638                    "  xstorm counter (%d) != stats_counter (%d)\n",
3639                    xclient->stats_counter, bp->stats_counter);
3640                 return -2;
3641         }
3642
3643         fstats->total_bytes_received_hi =
3644         fstats->valid_bytes_received_hi =
3645                                 le32_to_cpu(tclient->total_rcv_bytes.hi);
3646         fstats->total_bytes_received_lo =
3647         fstats->valid_bytes_received_lo =
3648                                 le32_to_cpu(tclient->total_rcv_bytes.lo);
3649
3650         estats->error_bytes_received_hi =
3651                                 le32_to_cpu(tclient->rcv_error_bytes.hi);
3652         estats->error_bytes_received_lo =
3653                                 le32_to_cpu(tclient->rcv_error_bytes.lo);
3654         ADD_64(estats->error_bytes_received_hi,
3655                estats->rx_stat_ifhcinbadoctets_hi,
3656                estats->error_bytes_received_lo,
3657                estats->rx_stat_ifhcinbadoctets_lo);
3658
3659         ADD_64(fstats->total_bytes_received_hi,
3660                estats->error_bytes_received_hi,
3661                fstats->total_bytes_received_lo,
3662                estats->error_bytes_received_lo);
3663
3664         UPDATE_EXTEND_TSTAT(rcv_unicast_pkts, total_unicast_packets_received);
3665         UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
3666                                 total_multicast_packets_received);
3667         UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
3668                                 total_broadcast_packets_received);
3669
3670         fstats->total_bytes_transmitted_hi =
3671                                 le32_to_cpu(xclient->total_sent_bytes.hi);
3672         fstats->total_bytes_transmitted_lo =
3673                                 le32_to_cpu(xclient->total_sent_bytes.lo);
3674
3675         UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
3676                                 total_unicast_packets_transmitted);
3677         UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
3678                                 total_multicast_packets_transmitted);
3679         UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
3680                                 total_broadcast_packets_transmitted);
3681
3682         memcpy(estats, &(fstats->total_bytes_received_hi),
3683                sizeof(struct host_func_stats) - 2*sizeof(u32));
3684
3685         estats->mac_filter_discard = le32_to_cpu(tport->mac_filter_discard);
3686         estats->xxoverflow_discard = le32_to_cpu(tport->xxoverflow_discard);
3687         estats->brb_truncate_discard =
3688                                 le32_to_cpu(tport->brb_truncate_discard);
3689         estats->mac_discard = le32_to_cpu(tport->mac_discard);
3690
3691         old_tclient->rcv_unicast_bytes.hi =
3692                                 le32_to_cpu(tclient->rcv_unicast_bytes.hi);
3693         old_tclient->rcv_unicast_bytes.lo =
3694                                 le32_to_cpu(tclient->rcv_unicast_bytes.lo);
3695         old_tclient->rcv_broadcast_bytes.hi =
3696                                 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
3697         old_tclient->rcv_broadcast_bytes.lo =
3698                                 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
3699         old_tclient->rcv_multicast_bytes.hi =
3700                                 le32_to_cpu(tclient->rcv_multicast_bytes.hi);
3701         old_tclient->rcv_multicast_bytes.lo =
3702                                 le32_to_cpu(tclient->rcv_multicast_bytes.lo);
3703         old_tclient->total_rcv_pkts = le32_to_cpu(tclient->total_rcv_pkts);
3704
3705         old_tclient->checksum_discard = le32_to_cpu(tclient->checksum_discard);
3706         old_tclient->packets_too_big_discard =
3707                                 le32_to_cpu(tclient->packets_too_big_discard);
3708         estats->no_buff_discard =
3709         old_tclient->no_buff_discard = le32_to_cpu(tclient->no_buff_discard);
3710         old_tclient->ttl0_discard = le32_to_cpu(tclient->ttl0_discard);
3711
3712         old_xclient->total_sent_pkts = le32_to_cpu(xclient->total_sent_pkts);
3713         old_xclient->unicast_bytes_sent.hi =
3714                                 le32_to_cpu(xclient->unicast_bytes_sent.hi);
3715         old_xclient->unicast_bytes_sent.lo =
3716                                 le32_to_cpu(xclient->unicast_bytes_sent.lo);
3717         old_xclient->multicast_bytes_sent.hi =
3718                                 le32_to_cpu(xclient->multicast_bytes_sent.hi);
3719         old_xclient->multicast_bytes_sent.lo =
3720                                 le32_to_cpu(xclient->multicast_bytes_sent.lo);
3721         old_xclient->broadcast_bytes_sent.hi =
3722                                 le32_to_cpu(xclient->broadcast_bytes_sent.hi);
3723         old_xclient->broadcast_bytes_sent.lo =
3724                                 le32_to_cpu(xclient->broadcast_bytes_sent.lo);
3725
3726         fstats->host_func_stats_start = ++fstats->host_func_stats_end;
3727
3728         return 0;
3729 }
3730
3731 static void bnx2x_net_stats_update(struct bnx2x *bp)
3732 {
3733         struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3734         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3735         struct net_device_stats *nstats = &bp->dev->stats;
3736
3737         nstats->rx_packets =
3738                 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
3739                 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
3740                 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
3741
3742         nstats->tx_packets =
3743                 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
3744                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
3745                 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
3746
3747         nstats->rx_bytes = bnx2x_hilo(&estats->valid_bytes_received_hi);
3748
3749         nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
3750
3751         nstats->rx_dropped = old_tclient->checksum_discard +
3752                              estats->mac_discard;
3753         nstats->tx_dropped = 0;
3754
3755         nstats->multicast =
3756                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
3757
3758         nstats->collisions =
3759                         estats->tx_stat_dot3statssinglecollisionframes_lo +
3760                         estats->tx_stat_dot3statsmultiplecollisionframes_lo +
3761                         estats->tx_stat_dot3statslatecollisions_lo +
3762                         estats->tx_stat_dot3statsexcessivecollisions_lo;
3763
3764         estats->jabber_packets_received =
3765                                 old_tclient->packets_too_big_discard +
3766                                 estats->rx_stat_dot3statsframestoolong_lo;
3767
3768         nstats->rx_length_errors =
3769                                 estats->rx_stat_etherstatsundersizepkts_lo +
3770                                 estats->jabber_packets_received;
3771         nstats->rx_over_errors = estats->brb_drop_lo + estats->brb_truncate_lo;
3772         nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo;
3773         nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo;
3774         nstats->rx_fifo_errors = old_tclient->no_buff_discard;
3775         nstats->rx_missed_errors = estats->xxoverflow_discard;
3776
3777         nstats->rx_errors = nstats->rx_length_errors +
3778                             nstats->rx_over_errors +
3779                             nstats->rx_crc_errors +
3780                             nstats->rx_frame_errors +
3781                             nstats->rx_fifo_errors +
3782                             nstats->rx_missed_errors;
3783
3784         nstats->tx_aborted_errors =
3785                         estats->tx_stat_dot3statslatecollisions_lo +
3786                         estats->tx_stat_dot3statsexcessivecollisions_lo;
3787         nstats->tx_carrier_errors = estats->rx_stat_falsecarriererrors_lo;
3788         nstats->tx_fifo_errors = 0;
3789         nstats->tx_heartbeat_errors = 0;
3790         nstats->tx_window_errors = 0;
3791
3792         nstats->tx_errors = nstats->tx_aborted_errors +
3793                             nstats->tx_carrier_errors;
3794 }
3795
3796 static void bnx2x_stats_update(struct bnx2x *bp)
3797 {
3798         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3799         int update = 0;
3800
3801         if (*stats_comp != DMAE_COMP_VAL)
3802                 return;
3803
3804         if (bp->port.pmf)
3805                 update = (bnx2x_hw_stats_update(bp) == 0);
3806
3807         update |= (bnx2x_storm_stats_update(bp) == 0);
3808
3809         if (update)
3810                 bnx2x_net_stats_update(bp);
3811
3812         else {
3813                 if (bp->stats_pending) {
3814                         bp->stats_pending++;
3815                         if (bp->stats_pending == 3) {
3816                                 BNX2X_ERR("stats not updated for 3 times\n");
3817                                 bnx2x_panic();
3818                                 return;
3819                         }
3820                 }
3821         }
3822
3823         if (bp->msglevel & NETIF_MSG_TIMER) {
3824                 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3825                 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3826                 struct net_device_stats *nstats = &bp->dev->stats;
3827                 int i;
3828
3829                 printk(KERN_DEBUG "%s:\n", bp->dev->name);
3830                 printk(KERN_DEBUG "  tx avail (%4x)  tx hc idx (%x)"
3831                                   "  tx pkt (%lx)\n",
3832                        bnx2x_tx_avail(bp->fp),
3833                        le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
3834                 printk(KERN_DEBUG "  rx usage (%4x)  rx hc idx (%x)"
3835                                   "  rx pkt (%lx)\n",
3836                        (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
3837                              bp->fp->rx_comp_cons),
3838                        le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3839                 printk(KERN_DEBUG "  %s (Xoff events %u)  brb drops %u\n",
3840                        netif_queue_stopped(bp->dev) ? "Xoff" : "Xon",
3841                        estats->driver_xoff, estats->brb_drop_lo);
3842                 printk(KERN_DEBUG "tstats: checksum_discard %u  "
3843                         "packets_too_big_discard %u  no_buff_discard %u  "
3844                         "mac_discard %u  mac_filter_discard %u  "
3845                         "xxovrflow_discard %u  brb_truncate_discard %u  "
3846                         "ttl0_discard %u\n",
3847                        old_tclient->checksum_discard,
3848                        old_tclient->packets_too_big_discard,
3849                        old_tclient->no_buff_discard, estats->mac_discard,
3850                        estats->mac_filter_discard, estats->xxoverflow_discard,
3851                        estats->brb_truncate_discard,
3852                        old_tclient->ttl0_discard);
3853
3854                 for_each_queue(bp, i) {
3855                         printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
3856                                bnx2x_fp(bp, i, tx_pkt),
3857                                bnx2x_fp(bp, i, rx_pkt),
3858                                bnx2x_fp(bp, i, rx_calls));
3859                 }
3860         }
3861
3862         bnx2x_hw_stats_post(bp);
3863         bnx2x_storm_stats_post(bp);
3864 }
3865
3866 static void bnx2x_port_stats_stop(struct bnx2x *bp)
3867 {
3868         struct dmae_command *dmae;
3869         u32 opcode;
3870         int loader_idx = PMF_DMAE_C(bp);
3871         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3872
3873         bp->executer_idx = 0;
3874
3875         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3876                   DMAE_CMD_C_ENABLE |
3877                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3878 #ifdef __BIG_ENDIAN
3879                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3880 #else
3881                   DMAE_CMD_ENDIANITY_DW_SWAP |
3882 #endif
3883                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3884                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3885
3886         if (bp->port.port_stx) {
3887
3888                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3889                 if (bp->func_stx)
3890                         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3891                 else
3892                         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3893                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3894                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3895                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3896                 dmae->dst_addr_hi = 0;
3897                 dmae->len = sizeof(struct host_port_stats) >> 2;
3898                 if (bp->func_stx) {
3899                         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3900                         dmae->comp_addr_hi = 0;
3901                         dmae->comp_val = 1;
3902                 } else {
3903                         dmae->comp_addr_lo =
3904                                 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3905                         dmae->comp_addr_hi =
3906                                 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3907                         dmae->comp_val = DMAE_COMP_VAL;
3908
3909                         *stats_comp = 0;
3910                 }
3911         }
3912
3913         if (bp->func_stx) {
3914
3915                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3916                 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3917                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3918                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3919                 dmae->dst_addr_lo = bp->func_stx >> 2;
3920                 dmae->dst_addr_hi = 0;
3921                 dmae->len = sizeof(struct host_func_stats) >> 2;
3922                 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3923                 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3924                 dmae->comp_val = DMAE_COMP_VAL;
3925
3926                 *stats_comp = 0;
3927         }
3928 }
3929
3930 static void bnx2x_stats_stop(struct bnx2x *bp)
3931 {
3932         int update = 0;
3933
3934         bnx2x_stats_comp(bp);
3935
3936         if (bp->port.pmf)
3937                 update = (bnx2x_hw_stats_update(bp) == 0);
3938
3939         update |= (bnx2x_storm_stats_update(bp) == 0);
3940
3941         if (update) {
3942                 bnx2x_net_stats_update(bp);
3943
3944                 if (bp->port.pmf)
3945                         bnx2x_port_stats_stop(bp);
3946
3947                 bnx2x_hw_stats_post(bp);
3948                 bnx2x_stats_comp(bp);
3949         }
3950 }
3951
3952 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
3953 {
3954 }
3955
3956 static const struct {
3957         void (*action)(struct bnx2x *bp);
3958         enum bnx2x_stats_state next_state;
3959 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
3960 /* state        event   */
3961 {
3962 /* DISABLED     PMF     */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
3963 /*              LINK_UP */ {bnx2x_stats_start,      STATS_STATE_ENABLED},
3964 /*              UPDATE  */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
3965 /*              STOP    */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
3966 },
3967 {
3968 /* ENABLED      PMF     */ {bnx2x_stats_pmf_start,  STATS_STATE_ENABLED},
3969 /*              LINK_UP */ {bnx2x_stats_restart,    STATS_STATE_ENABLED},
3970 /*              UPDATE  */ {bnx2x_stats_update,     STATS_STATE_ENABLED},
3971 /*              STOP    */ {bnx2x_stats_stop,       STATS_STATE_DISABLED}
3972 }
3973 };
3974
3975 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
3976 {
3977         enum bnx2x_stats_state state = bp->stats_state;
3978
3979         bnx2x_stats_stm[state][event].action(bp);
3980         bp->stats_state = bnx2x_stats_stm[state][event].next_state;
3981
3982         if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
3983                 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
3984                    state, event, bp->stats_state);
3985 }
3986
3987 static void bnx2x_timer(unsigned long data)
3988 {
3989         struct bnx2x *bp = (struct bnx2x *) data;
3990
3991         if (!netif_running(bp->dev))
3992                 return;
3993
3994         if (atomic_read(&bp->intr_sem) != 0)
3995                 goto timer_restart;
3996
3997         if (poll) {
3998                 struct bnx2x_fastpath *fp = &bp->fp[0];
3999                 int rc;
4000
4001                 bnx2x_tx_int(fp, 1000);
4002                 rc = bnx2x_rx_int(fp, 1000);
4003         }
4004
4005         if (!BP_NOMCP(bp)) {
4006                 int func = BP_FUNC(bp);
4007                 u32 drv_pulse;
4008                 u32 mcp_pulse;
4009
4010                 ++bp->fw_drv_pulse_wr_seq;
4011                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4012                 /* TBD - add SYSTEM_TIME */
4013                 drv_pulse = bp->fw_drv_pulse_wr_seq;
4014                 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
4015
4016                 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
4017                              MCP_PULSE_SEQ_MASK);
4018                 /* The delta between driver pulse and mcp response
4019                  * should be 1 (before mcp response) or 0 (after mcp response)
4020                  */
4021                 if ((drv_pulse != mcp_pulse) &&
4022                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4023                         /* someone lost a heartbeat... */
4024                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4025                                   drv_pulse, mcp_pulse);
4026                 }
4027         }
4028
4029         if ((bp->state == BNX2X_STATE_OPEN) ||
4030             (bp->state == BNX2X_STATE_DISABLED))
4031                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4032
4033 timer_restart:
4034         mod_timer(&bp->timer, jiffies + bp->current_interval);
4035 }
4036
4037 /* end of Statistics */
4038
4039 /* nic init */
4040
4041 /*
4042  * nic init service functions
4043  */
4044
4045 static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
4046 {
4047         int port = BP_PORT(bp);
4048
4049         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4050                         USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4051                         sizeof(struct ustorm_status_block)/4);
4052         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4053                         CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4054                         sizeof(struct cstorm_status_block)/4);
4055 }
4056
4057 static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4058                           dma_addr_t mapping, int sb_id)
4059 {
4060         int port = BP_PORT(bp);
4061         int func = BP_FUNC(bp);
4062         int index;
4063         u64 section;
4064
4065         /* USTORM */
4066         section = ((u64)mapping) + offsetof(struct host_status_block,
4067                                             u_status_block);
4068         sb->u_status_block.status_block_id = sb_id;
4069
4070         REG_WR(bp, BAR_USTRORM_INTMEM +
4071                USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4072         REG_WR(bp, BAR_USTRORM_INTMEM +
4073                ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4074                U64_HI(section));
4075         REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
4076                 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4077
4078         for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4079                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4080                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4081
4082         /* CSTORM */
4083         section = ((u64)mapping) + offsetof(struct host_status_block,
4084                                             c_status_block);
4085         sb->c_status_block.status_block_id = sb_id;
4086
4087         REG_WR(bp, BAR_CSTRORM_INTMEM +
4088                CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4089         REG_WR(bp, BAR_CSTRORM_INTMEM +
4090                ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4091                U64_HI(section));
4092         REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
4093                 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4094
4095         for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4096                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4097                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4098
4099         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4100 }
4101
4102 static void bnx2x_zero_def_sb(struct bnx2x *bp)
4103 {
4104         int func = BP_FUNC(bp);
4105
4106         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4107                         USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4108                         sizeof(struct ustorm_def_status_block)/4);
4109         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4110                         CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4111                         sizeof(struct cstorm_def_status_block)/4);
4112         bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
4113                         XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4114                         sizeof(struct xstorm_def_status_block)/4);
4115         bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4116                         TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4117                         sizeof(struct tstorm_def_status_block)/4);
4118 }
4119
4120 static void bnx2x_init_def_sb(struct bnx2x *bp,
4121                               struct host_def_status_block *def_sb,
4122                               dma_addr_t mapping, int sb_id)
4123 {
4124         int port = BP_PORT(bp);
4125         int func = BP_FUNC(bp);
4126         int index, val, reg_offset;
4127         u64 section;
4128
4129         /* ATTN */
4130         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4131                                             atten_status_block);
4132         def_sb->atten_status_block.status_block_id = sb_id;
4133
4134         bp->attn_state = 0;
4135
4136         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4137                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4138
4139         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4140                 bp->attn_group[index].sig[0] = REG_RD(bp,
4141                                                      reg_offset + 0x10*index);
4142                 bp->attn_group[index].sig[1] = REG_RD(bp,
4143                                                reg_offset + 0x4 + 0x10*index);
4144                 bp->attn_group[index].sig[2] = REG_RD(bp,
4145                                                reg_offset + 0x8 + 0x10*index);
4146                 bp->attn_group[index].sig[3] = REG_RD(bp,
4147                                                reg_offset + 0xc + 0x10*index);
4148         }
4149
4150         reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4151                              HC_REG_ATTN_MSG0_ADDR_L);
4152
4153         REG_WR(bp, reg_offset, U64_LO(section));
4154         REG_WR(bp, reg_offset + 4, U64_HI(section));
4155
4156         reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4157
4158         val = REG_RD(bp, reg_offset);
4159         val |= sb_id;
4160         REG_WR(bp, reg_offset, val);
4161
4162         /* USTORM */
4163         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4164                                             u_def_status_block);
4165         def_sb->u_def_status_block.status_block_id = sb_id;
4166
4167         REG_WR(bp, BAR_USTRORM_INTMEM +
4168                USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4169         REG_WR(bp, BAR_USTRORM_INTMEM +
4170                ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4171                U64_HI(section));
4172         REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4173                 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4174
4175         for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4176                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4177                          USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4178
4179         /* CSTORM */
4180         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4181                                             c_def_status_block);
4182         def_sb->c_def_status_block.status_block_id = sb_id;
4183
4184         REG_WR(bp, BAR_CSTRORM_INTMEM +
4185                CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4186         REG_WR(bp, BAR_CSTRORM_INTMEM +
4187                ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4188                U64_HI(section));
4189         REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4190                 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4191
4192         for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4193                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4194                          CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4195
4196         /* TSTORM */
4197         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4198                                             t_def_status_block);
4199         def_sb->t_def_status_block.status_block_id = sb_id;
4200
4201         REG_WR(bp, BAR_TSTRORM_INTMEM +
4202                TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4203         REG_WR(bp, BAR_TSTRORM_INTMEM +
4204                ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4205                U64_HI(section));
4206         REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4207                 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4208
4209         for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4210                 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4211                          TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4212
4213         /* XSTORM */
4214         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4215                                             x_def_status_block);
4216         def_sb->x_def_status_block.status_block_id = sb_id;
4217
4218         REG_WR(bp, BAR_XSTRORM_INTMEM +
4219                XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4220         REG_WR(bp, BAR_XSTRORM_INTMEM +
4221                ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4222                U64_HI(section));
4223         REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4224                 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4225
4226         for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4227                 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4228                          XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4229
4230         bp->stats_pending = 0;
4231         bp->set_mac_pending = 0;
4232
4233         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4234 }
4235
4236 static void bnx2x_update_coalesce(struct bnx2x *bp)
4237 {
4238         int port = BP_PORT(bp);
4239         int i;
4240
4241         for_each_queue(bp, i) {
4242                 int sb_id = bp->fp[i].sb_id;
4243
4244                 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4245                 REG_WR8(bp, BAR_USTRORM_INTMEM +
4246                         USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4247                                                     U_SB_ETH_RX_CQ_INDEX),
4248                         bp->rx_ticks/12);
4249                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4250                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4251                                                      U_SB_ETH_RX_CQ_INDEX),
4252                          bp->rx_ticks ? 0 : 1);
4253
4254                 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4255                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4256                         CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4257                                                     C_SB_ETH_TX_CQ_INDEX),
4258                         bp->tx_ticks/12);
4259                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4260                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4261                                                      C_SB_ETH_TX_CQ_INDEX),
4262                          bp->tx_ticks ? 0 : 1);
4263         }
4264 }
4265
4266 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4267                                        struct bnx2x_fastpath *fp, int last)
4268 {
4269         int i;
4270
4271         for (i = 0; i < last; i++) {
4272                 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
4273                 struct sk_buff *skb = rx_buf->skb;
4274
4275                 if (skb == NULL) {
4276                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
4277                         continue;
4278                 }
4279
4280                 if (fp->tpa_state[i] == BNX2X_TPA_START)
4281                         pci_unmap_single(bp->pdev,
4282                                          pci_unmap_addr(rx_buf, mapping),
4283                                          bp->rx_buf_size,
4284                                          PCI_DMA_FROMDEVICE);
4285
4286                 dev_kfree_skb(skb);
4287                 rx_buf->skb = NULL;
4288         }
4289 }
4290
4291 static void bnx2x_init_rx_rings(struct bnx2x *bp)
4292 {
4293         int func = BP_FUNC(bp);
4294         int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4295                                               ETH_MAX_AGGREGATION_QUEUES_E1H;
4296         u16 ring_prod, cqe_ring_prod;
4297         int i, j;
4298
4299         bp->rx_buf_size += bp->rx_offset + ETH_OVREHEAD + BNX2X_RX_ALIGN;
4300         DP(NETIF_MSG_IFUP,
4301            "mtu %d  rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size);
4302
4303         if (bp->flags & TPA_ENABLE_FLAG) {
4304
4305                 for_each_rx_queue(bp, j) {
4306                         struct bnx2x_fastpath *fp = &bp->fp[j];
4307
4308                         for (i = 0; i < max_agg_queues; i++) {
4309                                 fp->tpa_pool[i].skb =
4310                                    netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4311                                 if (!fp->tpa_pool[i].skb) {
4312                                         BNX2X_ERR("Failed to allocate TPA "
4313                                                   "skb pool for queue[%d] - "
4314                                                   "disabling TPA on this "
4315                                                   "queue!\n", j);
4316                                         bnx2x_free_tpa_pool(bp, fp, i);
4317                                         fp->disable_tpa = 1;
4318                                         break;
4319                                 }
4320                                 pci_unmap_addr_set((struct sw_rx_bd *)
4321                                                         &bp->fp->tpa_pool[i],
4322                                                    mapping, 0);
4323                                 fp->tpa_state[i] = BNX2X_TPA_STOP;
4324                         }
4325                 }
4326         }
4327
4328         for_each_rx_queue(bp, j) {
4329                 struct bnx2x_fastpath *fp = &bp->fp[j];
4330
4331                 fp->rx_bd_cons = 0;
4332                 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4333                 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
4334
4335                 /* "next page" elements initialization */
4336                 /* SGE ring */
4337                 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
4338                         struct eth_rx_sge *sge;
4339
4340                         sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
4341                         sge->addr_hi =
4342                                 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
4343                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4344                         sge->addr_lo =
4345                                 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
4346                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4347                 }
4348
4349                 bnx2x_init_sge_ring_bit_mask(fp);
4350
4351                 /* RX BD ring */
4352                 for (i = 1; i <= NUM_RX_RINGS; i++) {
4353                         struct eth_rx_bd *rx_bd;
4354
4355                         rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4356                         rx_bd->addr_hi =
4357                                 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4358                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4359                         rx_bd->addr_lo =
4360                                 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4361                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4362                 }
4363
4364                 /* CQ ring */
4365                 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4366                         struct eth_rx_cqe_next_page *nextpg;
4367
4368                         nextpg = (struct eth_rx_cqe_next_page *)
4369                                 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4370                         nextpg->addr_hi =
4371                                 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4372                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4373                         nextpg->addr_lo =
4374                                 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4375                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4376                 }
4377
4378                 /* Allocate SGEs and initialize the ring elements */
4379                 for (i = 0, ring_prod = 0;
4380                      i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4381
4382                         if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
4383                                 BNX2X_ERR("was only able to allocate "
4384                                           "%d rx sges\n", i);
4385                                 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4386                                 /* Cleanup already allocated elements */
4387                                 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4388                                 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4389                                 fp->disable_tpa = 1;
4390                                 ring_prod = 0;
4391                                 break;
4392                         }
4393                         ring_prod = NEXT_SGE_IDX(ring_prod);
4394                 }
4395                 fp->rx_sge_prod = ring_prod;
4396
4397                 /* Allocate BDs and initialize BD ring */
4398                 fp->rx_comp_cons = 0;
4399                 cqe_ring_prod = ring_prod = 0;
4400                 for (i = 0; i < bp->rx_ring_size; i++) {
4401                         if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4402                                 BNX2X_ERR("was only able to allocate "
4403                                           "%d rx skbs\n", i);
4404                                 bp->eth_stats.rx_skb_alloc_failed++;
4405                                 break;
4406                         }
4407                         ring_prod = NEXT_RX_IDX(ring_prod);
4408                         cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4409                         WARN_ON(ring_prod <= i);
4410                 }
4411
4412                 fp->rx_bd_prod = ring_prod;
4413                 /* must not have more available CQEs than BDs */
4414                 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
4415                                        cqe_ring_prod);
4416                 fp->rx_pkt = fp->rx_calls = 0;
4417
4418                 /* Warning!
4419                  * this will generate an interrupt (to the TSTORM)
4420                  * must only be done after chip is initialized
4421                  */
4422                 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
4423                                      fp->rx_sge_prod);
4424                 if (j != 0)
4425                         continue;
4426
4427                 REG_WR(bp, BAR_USTRORM_INTMEM +
4428                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
4429                        U64_LO(fp->rx_comp_mapping));
4430                 REG_WR(bp, BAR_USTRORM_INTMEM +
4431                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
4432                        U64_HI(fp->rx_comp_mapping));
4433         }
4434 }
4435
4436 static void bnx2x_init_tx_ring(struct bnx2x *bp)
4437 {
4438         int i, j;
4439
4440         for_each_tx_queue(bp, j) {
4441                 struct bnx2x_fastpath *fp = &bp->fp[j];
4442
4443                 for (i = 1; i <= NUM_TX_RINGS; i++) {
4444                         struct eth_tx_bd *tx_bd =
4445                                 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4446
4447                         tx_bd->addr_hi =
4448                                 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4449                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4450                         tx_bd->addr_lo =
4451                                 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4452                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4453                 }
4454
4455                 fp->tx_pkt_prod = 0;
4456                 fp->tx_pkt_cons = 0;
4457                 fp->tx_bd_prod = 0;
4458                 fp->tx_bd_cons = 0;
4459                 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4460                 fp->tx_pkt = 0;
4461         }
4462 }
4463
4464 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4465 {
4466         int func = BP_FUNC(bp);
4467
4468         spin_lock_init(&bp->spq_lock);
4469
4470         bp->spq_left = MAX_SPQ_PENDING;
4471         bp->spq_prod_idx = 0;
4472         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4473         bp->spq_prod_bd = bp->spq;
4474         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4475
4476         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4477                U64_LO(bp->spq_mapping));
4478         REG_WR(bp,
4479                XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
4480                U64_HI(bp->spq_mapping));
4481
4482         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
4483                bp->spq_prod_idx);
4484 }
4485
4486 static void bnx2x_init_context(struct bnx2x *bp)
4487 {
4488         int i;
4489
4490         for_each_queue(bp, i) {
4491                 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4492                 struct bnx2x_fastpath *fp = &bp->fp[i];
4493                 u8 sb_id = FP_SB_ID(fp);
4494
4495                 context->ustorm_st_context.common.sb_index_numbers =
4496                                                 BNX2X_RX_SB_INDEX_NUM;
4497                 context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
4498                 context->ustorm_st_context.common.status_block_id = sb_id;
4499                 context->ustorm_st_context.common.flags =
4500                         USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
4501                 context->ustorm_st_context.common.mc_alignment_log_size =
4502                                                 BNX2X_RX_ALIGN_SHIFT;
4503                 context->ustorm_st_context.common.bd_buff_size =
4504                                                 bp->rx_buf_size;
4505                 context->ustorm_st_context.common.bd_page_base_hi =
4506                                                 U64_HI(fp->rx_desc_mapping);
4507                 context->ustorm_st_context.common.bd_page_base_lo =
4508                                                 U64_LO(fp->rx_desc_mapping);
4509                 if (!fp->disable_tpa) {
4510                         context->ustorm_st_context.common.flags |=
4511                                 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
4512                                  USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
4513                         context->ustorm_st_context.common.sge_buff_size =
4514                                 (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
4515                                          (u32)0xffff);
4516                         context->ustorm_st_context.common.sge_page_base_hi =
4517                                                 U64_HI(fp->rx_sge_mapping);
4518                         context->ustorm_st_context.common.sge_page_base_lo =
4519                                                 U64_LO(fp->rx_sge_mapping);
4520                 }
4521
4522                 context->ustorm_ag_context.cdu_usage =
4523                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4524                                                CDU_REGION_NUMBER_UCM_AG,
4525                                                ETH_CONNECTION_TYPE);
4526
4527                 context->xstorm_st_context.tx_bd_page_base_hi =
4528                                                 U64_HI(fp->tx_desc_mapping);
4529                 context->xstorm_st_context.tx_bd_page_base_lo =
4530                                                 U64_LO(fp->tx_desc_mapping);
4531                 context->xstorm_st_context.db_data_addr_hi =
4532                                                 U64_HI(fp->tx_prods_mapping);
4533                 context->xstorm_st_context.db_data_addr_lo =
4534                                                 U64_LO(fp->tx_prods_mapping);
4535                 context->xstorm_st_context.statistics_data = (fp->cl_id |
4536                                 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
4537                 context->cstorm_st_context.sb_index_number =
4538                                                 C_SB_ETH_TX_CQ_INDEX;
4539                 context->cstorm_st_context.status_block_id = sb_id;
4540
4541                 context->xstorm_ag_context.cdu_reserved =
4542                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4543                                                CDU_REGION_NUMBER_XCM_AG,
4544                                                ETH_CONNECTION_TYPE);
4545         }
4546 }
4547
4548 static void bnx2x_init_ind_table(struct bnx2x *bp)
4549 {
4550         int func = BP_FUNC(bp);
4551         int i;
4552
4553         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4554                 return;
4555
4556         DP(NETIF_MSG_IFUP,
4557            "Initializing indirection table  multi_mode %d\n", bp->multi_mode);
4558         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4559                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4560                         TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4561                         BP_CL_ID(bp) + (i % bp->num_rx_queues));
4562 }
4563
4564 static void bnx2x_set_client_config(struct bnx2x *bp)
4565 {
4566         struct tstorm_eth_client_config tstorm_client = {0};
4567         int port = BP_PORT(bp);
4568         int i;
4569
4570         tstorm_client.mtu = bp->dev->mtu;
4571         tstorm_client.statistics_counter_id = BP_CL_ID(bp);
4572         tstorm_client.config_flags =
4573                                 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
4574 #ifdef BCM_VLAN
4575         if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
4576                 tstorm_client.config_flags |=
4577                                 TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
4578                 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4579         }
4580 #endif
4581
4582         if (bp->flags & TPA_ENABLE_FLAG) {
4583                 tstorm_client.max_sges_for_packet =
4584                         SGE_PAGE_ALIGN(tstorm_client.mtu) >> SGE_PAGE_SHIFT;
4585                 tstorm_client.max_sges_for_packet =
4586                         ((tstorm_client.max_sges_for_packet +
4587                           PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
4588                         PAGES_PER_SGE_SHIFT;
4589
4590                 tstorm_client.config_flags |=
4591                                 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
4592         }
4593
4594         for_each_queue(bp, i) {
4595                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4596                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
4597                        ((u32 *)&tstorm_client)[0]);
4598                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4599                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
4600                        ((u32 *)&tstorm_client)[1]);
4601         }
4602
4603         DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
4604            ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
4605 }
4606
4607 static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4608 {
4609         struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4610         int mode = bp->rx_mode;
4611         int mask = (1 << BP_L_ID(bp));
4612         int func = BP_FUNC(bp);
4613         int i;
4614
4615         DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
4616
4617         switch (mode) {
4618         case BNX2X_RX_MODE_NONE: /* no Rx */
4619                 tstorm_mac_filter.ucast_drop_all = mask;
4620                 tstorm_mac_filter.mcast_drop_all = mask;
4621                 tstorm_mac_filter.bcast_drop_all = mask;
4622                 break;
4623         case BNX2X_RX_MODE_NORMAL:
4624                 tstorm_mac_filter.bcast_accept_all = mask;
4625                 break;
4626         case BNX2X_RX_MODE_ALLMULTI:
4627                 tstorm_mac_filter.mcast_accept_all = mask;
4628                 tstorm_mac_filter.bcast_accept_all = mask;
4629                 break;
4630         case BNX2X_RX_MODE_PROMISC:
4631                 tstorm_mac_filter.ucast_accept_all = mask;
4632                 tstorm_mac_filter.mcast_accept_all = mask;
4633                 tstorm_mac_filter.bcast_accept_all = mask;
4634                 break;
4635         default:
4636                 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4637                 break;
4638         }
4639
4640         for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4641                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4642                        TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
4643                        ((u32 *)&tstorm_mac_filter)[i]);
4644
4645 /*              DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4646                    ((u32 *)&tstorm_mac_filter)[i]); */
4647         }
4648
4649         if (mode != BNX2X_RX_MODE_NONE)
4650                 bnx2x_set_client_config(bp);
4651 }
4652
4653 static void bnx2x_init_internal_common(struct bnx2x *bp)
4654 {
4655         int i;
4656
4657         if (bp->flags & TPA_ENABLE_FLAG) {
4658                 struct tstorm_eth_tpa_exist tpa = {0};
4659
4660                 tpa.tpa_exist = 1;
4661
4662                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
4663                        ((u32 *)&tpa)[0]);
4664                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
4665                        ((u32 *)&tpa)[1]);
4666         }
4667
4668         /* Zero this manually as its initialization is
4669            currently missing in the initTool */
4670         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4671                 REG_WR(bp, BAR_USTRORM_INTMEM +
4672                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
4673 }
4674
4675 static void bnx2x_init_internal_port(struct bnx2x *bp)
4676 {
4677         int port = BP_PORT(bp);
4678
4679         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4680         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4681         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4682         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4683 }
4684
4685 static void bnx2x_init_internal_func(struct bnx2x *bp)
4686 {
4687         struct tstorm_eth_function_common_config tstorm_config = {0};
4688         struct stats_indication_flags stats_flags = {0};
4689         int port = BP_PORT(bp);
4690         int func = BP_FUNC(bp);
4691         int i;
4692         u16 max_agg_size;
4693
4694         if (is_multi(bp)) {
4695                 tstorm_config.config_flags = MULTI_FLAGS(bp);
4696                 tstorm_config.rss_result_mask = MULTI_MASK;
4697         }
4698         if (IS_E1HMF(bp))
4699                 tstorm_config.config_flags |=
4700                                 TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
4701
4702         tstorm_config.leading_client_id = BP_L_ID(bp);
4703
4704         REG_WR(bp, BAR_TSTRORM_INTMEM +
4705                TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4706                (*(u32 *)&tstorm_config));
4707
4708         bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4709         bnx2x_set_storm_rx_mode(bp);
4710
4711         /* reset xstorm per client statistics */
4712         for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) {
4713                 REG_WR(bp, BAR_XSTRORM_INTMEM +
4714                        XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4715                        i*4, 0);
4716         }
4717         /* reset tstorm per client statistics */
4718         for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) {
4719                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4720                        TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4721                        i*4, 0);
4722         }
4723
4724         /* Init statistics related context */
4725         stats_flags.collect_eth = 1;
4726
4727         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4728                ((u32 *)&stats_flags)[0]);
4729         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4730                ((u32 *)&stats_flags)[1]);
4731
4732         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4733                ((u32 *)&stats_flags)[0]);
4734         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4735                ((u32 *)&stats_flags)[1]);
4736
4737         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4738                ((u32 *)&stats_flags)[0]);
4739         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4740                ((u32 *)&stats_flags)[1]);
4741
4742         REG_WR(bp, BAR_XSTRORM_INTMEM +
4743                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4744                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4745         REG_WR(bp, BAR_XSTRORM_INTMEM +
4746                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4747                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4748
4749         REG_WR(bp, BAR_TSTRORM_INTMEM +
4750                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4751                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4752         REG_WR(bp, BAR_TSTRORM_INTMEM +
4753                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4754                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4755
4756         if (CHIP_IS_E1H(bp)) {
4757                 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4758                         IS_E1HMF(bp));
4759                 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4760                         IS_E1HMF(bp));
4761                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4762                         IS_E1HMF(bp));
4763                 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4764                         IS_E1HMF(bp));
4765
4766                 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
4767                          bp->e1hov);
4768         }
4769
4770         /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
4771         max_agg_size =
4772                 min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) *
4773                           SGE_PAGE_SIZE * PAGES_PER_SGE),
4774                     (u32)0xffff);
4775         for_each_rx_queue(bp, i) {
4776                 struct bnx2x_fastpath *fp = &bp->fp[i];
4777
4778                 REG_WR(bp, BAR_USTRORM_INTMEM +
4779                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
4780                        U64_LO(fp->rx_comp_mapping));
4781                 REG_WR(bp, BAR_USTRORM_INTMEM +
4782                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4783                        U64_HI(fp->rx_comp_mapping));
4784
4785                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4786                          USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4787                          max_agg_size);
4788         }
4789 }
4790
4791 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4792 {
4793         switch (load_code) {
4794         case FW_MSG_CODE_DRV_LOAD_COMMON:
4795                 bnx2x_init_internal_common(bp);
4796                 /* no break */
4797
4798         case FW_MSG_CODE_DRV_LOAD_PORT:
4799                 bnx2x_init_internal_port(bp);
4800                 /* no break */
4801
4802         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4803                 bnx2x_init_internal_func(bp);
4804                 break;
4805
4806         default:
4807                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4808                 break;
4809         }
4810 }
4811
4812 static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4813 {
4814         int i;
4815
4816         for_each_queue(bp, i) {
4817                 struct bnx2x_fastpath *fp = &bp->fp[i];
4818
4819                 fp->bp = bp;
4820                 fp->state = BNX2X_FP_STATE_CLOSED;
4821                 fp->index = i;
4822                 fp->cl_id = BP_L_ID(bp) + i;
4823                 fp->sb_id = fp->cl_id;
4824                 DP(NETIF_MSG_IFUP,
4825                    "bnx2x_init_sb(%p,%p) index %d  cl_id %d  sb %d\n",
4826                    bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
4827                 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
4828                               FP_SB_ID(fp));
4829                 bnx2x_update_fpsb_idx(fp);
4830         }
4831
4832         bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
4833                           DEF_SB_ID);
4834         bnx2x_update_dsb_idx(bp);
4835         bnx2x_update_coalesce(bp);
4836         bnx2x_init_rx_rings(bp);
4837         bnx2x_init_tx_ring(bp);
4838         bnx2x_init_sp_ring(bp);
4839         bnx2x_init_context(bp);
4840         bnx2x_init_internal(bp, load_code);
4841         bnx2x_init_ind_table(bp);
4842         bnx2x_stats_init(bp);
4843
4844         /* At this point, we are ready for interrupts */
4845         atomic_set(&bp->intr_sem, 0);
4846
4847         /* flush all before enabling interrupts */
4848         mb();
4849         mmiowb();
4850
4851         bnx2x_int_enable(bp);
4852 }
4853
4854 /* end of nic init */
4855
4856 /*
4857  * gzip service functions
4858  */
4859
4860 static int bnx2x_gunzip_init(struct bnx2x *bp)
4861 {
4862         bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
4863                                               &bp->gunzip_mapping);
4864         if (bp->gunzip_buf  == NULL)
4865                 goto gunzip_nomem1;
4866
4867         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4868         if (bp->strm  == NULL)
4869                 goto gunzip_nomem2;
4870
4871         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4872                                       GFP_KERNEL);
4873         if (bp->strm->workspace == NULL)
4874                 goto gunzip_nomem3;
4875
4876         return 0;
4877
4878 gunzip_nomem3:
4879         kfree(bp->strm);
4880         bp->strm = NULL;
4881
4882 gunzip_nomem2:
4883         pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4884                             bp->gunzip_mapping);
4885         bp->gunzip_buf = NULL;
4886
4887 gunzip_nomem1:
4888         printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
4889                " un-compression\n", bp->dev->name);
4890         return -ENOMEM;
4891 }
4892
4893 static void bnx2x_gunzip_end(struct bnx2x *bp)
4894 {
4895         kfree(bp->strm->workspace);
4896
4897         kfree(bp->strm);
4898         bp->strm = NULL;
4899
4900         if (bp->gunzip_buf) {
4901                 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4902                                     bp->gunzip_mapping);
4903                 bp->gunzip_buf = NULL;
4904         }
4905 }
4906
4907 static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
4908 {
4909         int n, rc;
4910
4911         /* check gzip header */
4912         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
4913                 return -EINVAL;
4914
4915         n = 10;
4916
4917 #define FNAME                           0x8
4918
4919         if (zbuf[3] & FNAME)
4920                 while ((zbuf[n++] != 0) && (n < len));
4921
4922         bp->strm->next_in = zbuf + n;
4923         bp->strm->avail_in = len - n;
4924         bp->strm->next_out = bp->gunzip_buf;
4925         bp->strm->avail_out = FW_BUF_SIZE;
4926
4927         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4928         if (rc != Z_OK)
4929                 return rc;
4930
4931         rc = zlib_inflate(bp->strm, Z_FINISH);
4932         if ((rc != Z_OK) && (rc != Z_STREAM_END))
4933                 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
4934                        bp->dev->name, bp->strm->msg);
4935
4936         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4937         if (bp->gunzip_outlen & 0x3)
4938                 printk(KERN_ERR PFX "%s: Firmware decompression error:"
4939                                     " gunzip_outlen (%d) not aligned\n",
4940                        bp->dev->name, bp->gunzip_outlen);
4941         bp->gunzip_outlen >>= 2;
4942
4943         zlib_inflateEnd(bp->strm);
4944
4945         if (rc == Z_STREAM_END)
4946                 return 0;
4947
4948         return rc;
4949 }
4950
4951 /* nic load/unload */
4952
4953 /*
4954  * General service functions
4955  */
4956
4957 /* send a NIG loopback debug packet */
4958 static void bnx2x_lb_pckt(struct bnx2x *bp)
4959 {
4960         u32 wb_write[3];
4961
4962         /* Ethernet source and destination addresses */
4963         wb_write[0] = 0x55555555;
4964         wb_write[1] = 0x55555555;
4965         wb_write[2] = 0x20;             /* SOP */
4966         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4967
4968         /* NON-IP protocol */
4969         wb_write[0] = 0x09000000;
4970         wb_write[1] = 0x55555555;
4971         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
4972         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4973 }
4974
4975 /* some of the internal memories
4976  * are not directly readable from the driver
4977  * to test them we send debug packets
4978  */
4979 static int bnx2x_int_mem_test(struct bnx2x *bp)
4980 {
4981         int factor;
4982         int count, i;
4983         u32 val = 0;
4984
4985         if (CHIP_REV_IS_FPGA(bp))
4986                 factor = 120;
4987         else if (CHIP_REV_IS_EMUL(bp))
4988                 factor = 200;
4989         else
4990                 factor = 1;
4991
4992         DP(NETIF_MSG_HW, "start part1\n");
4993
4994         /* Disable inputs of parser neighbor blocks */
4995         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4996         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4997         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4998         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4999
5000         /*  Write 0 to parser credits for CFC search request */
5001         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5002
5003         /* send Ethernet packet */
5004         bnx2x_lb_pckt(bp);
5005
5006         /* TODO do i reset NIG statistic? */
5007         /* Wait until NIG register shows 1 packet of size 0x10 */
5008         count = 1000 * factor;
5009         while (count) {
5010
5011                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5012                 val = *bnx2x_sp(bp, wb_data[0]);
5013                 if (val == 0x10)
5014                         break;
5015
5016                 msleep(10);
5017                 count--;
5018         }
5019         if (val != 0x10) {
5020                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5021                 return -1;
5022         }
5023
5024         /* Wait until PRS register shows 1 packet */
5025         count = 1000 * factor;
5026         while (count) {
5027                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5028                 if (val == 1)
5029                         break;
5030
5031                 msleep(10);
5032                 count--;
5033         }
5034         if (val != 0x1) {
5035                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5036                 return -2;
5037         }
5038
5039         /* Reset and init BRB, PRS */
5040         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5041         msleep(50);
5042         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5043         msleep(50);
5044         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5045         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5046
5047         DP(NETIF_MSG_HW, "part2\n");
5048
5049         /* Disable inputs of parser neighbor blocks */
5050         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5051         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5052         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5053         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5054
5055         /* Write 0 to parser credits for CFC search request */
5056         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5057
5058         /* send 10 Ethernet packets */
5059         for (i = 0; i < 10; i++)
5060                 bnx2x_lb_pckt(bp);
5061
5062         /* Wait until NIG register shows 10 + 1
5063            packets of size 11*0x10 = 0xb0 */
5064         count = 1000 * factor;
5065         while (count) {
5066
5067                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5068                 val = *bnx2x_sp(bp, wb_data[0]);
5069                 if (val == 0xb0)
5070                         break;
5071
5072                 msleep(10);
5073                 count--;
5074         }
5075         if (val != 0xb0) {
5076                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5077                 return -3;
5078         }
5079
5080         /* Wait until PRS register shows 2 packets */
5081         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5082         if (val != 2)
5083                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5084
5085         /* Write 1 to parser credits for CFC search request */
5086         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5087
5088         /* Wait until PRS register shows 3 packets */
5089         msleep(10 * factor);
5090         /* Wait until NIG register shows 1 packet of size 0x10 */
5091         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5092         if (val != 3)
5093                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5094
5095         /* clear NIG EOP FIFO */
5096         for (i = 0; i < 11; i++)
5097                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5098         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5099         if (val != 1) {
5100                 BNX2X_ERR("clear of NIG failed\n");
5101                 return -4;
5102         }
5103
5104         /* Reset and init BRB, PRS, NIG */
5105         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5106         msleep(50);
5107         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5108         msleep(50);
5109         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5110         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5111 #ifndef BCM_ISCSI
5112         /* set NIC mode */
5113         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5114 #endif
5115
5116         /* Enable inputs of parser neighbor blocks */
5117         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5118         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5119         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5120         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5121
5122         DP(NETIF_MSG_HW, "done\n");
5123
5124         return 0; /* OK */
5125 }
5126
5127 static void enable_blocks_attention(struct bnx2x *bp)
5128 {
5129         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5130         REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5131         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5132         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5133         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5134         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5135         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5136         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5137         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5138 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5139 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5140         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5141         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5142         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5143 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5144 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5145         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5146         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5147         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5148         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5149 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5150 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5151         if (CHIP_REV_IS_FPGA(bp))
5152                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5153         else
5154                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5155         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5156         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5157         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5158 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5159 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5160         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5161         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5162 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5163         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
5164 }
5165
5166
5167 static void bnx2x_reset_common(struct bnx2x *bp)
5168 {
5169         /* reset_common */
5170         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5171                0xd3ffff7f);
5172         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
5173 }
5174
5175 static int bnx2x_init_common(struct bnx2x *bp)
5176 {
5177         u32 val, i;
5178
5179         DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_FUNC(bp));
5180
5181         bnx2x_reset_common(bp);
5182         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5183         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5184
5185         bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
5186         if (CHIP_IS_E1H(bp))
5187                 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5188
5189         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5190         msleep(30);
5191         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5192
5193         bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
5194         if (CHIP_IS_E1(bp)) {
5195                 /* enable HW interrupt from PXP on USDM overflow
5196                    bit 16 on INT_MASK_0 */
5197                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5198         }
5199
5200         bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
5201         bnx2x_init_pxp(bp);
5202
5203 #ifdef __BIG_ENDIAN
5204         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5205         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5206         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5207         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5208         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5209         /* make sure this value is 0 */
5210         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5211
5212 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5213         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5214         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5215         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5216         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5217 #endif
5218
5219         REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5220 #ifdef BCM_ISCSI
5221         REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5222         REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5223         REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5224 #endif
5225
5226         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5227                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5228
5229         /* let the HW do it's magic ... */
5230         msleep(100);
5231         /* finish PXP init */
5232         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5233         if (val != 1) {
5234                 BNX2X_ERR("PXP2 CFG failed\n");
5235                 return -EBUSY;
5236         }
5237         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5238         if (val != 1) {
5239                 BNX2X_ERR("PXP2 RD_INIT failed\n");
5240                 return -EBUSY;
5241         }
5242
5243         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5244         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5245
5246         bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
5247
5248         /* clean the DMAE memory */
5249         bp->dmae_ready = 1;
5250         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5251
5252         bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
5253         bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
5254         bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
5255         bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
5256
5257         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5258         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5259         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5260         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5261
5262         bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5263         /* soft reset pulse */
5264         REG_WR(bp, QM_REG_SOFT_RESET, 1);
5265         REG_WR(bp, QM_REG_SOFT_RESET, 0);
5266
5267 #ifdef BCM_ISCSI
5268         bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
5269 #endif
5270
5271         bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
5272         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
5273         if (!CHIP_REV_IS_SLOW(bp)) {
5274                 /* enable hw interrupt from doorbell Q */
5275                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5276         }
5277
5278         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5279         if (CHIP_REV_IS_SLOW(bp)) {
5280                 /* fix for emulation and FPGA for no pause */
5281                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
5282                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
5283                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
5284                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
5285         }
5286
5287         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5288         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5289         /* set NIC mode */
5290         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5291         if (CHIP_IS_E1H(bp))
5292                 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5293
5294         bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
5295         bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
5296         bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5297         bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5298
5299         if (CHIP_IS_E1H(bp)) {
5300                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5301                                 STORM_INTMEM_SIZE_E1H/2);
5302                 bnx2x_init_fill(bp,
5303                                 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5304                                 0, STORM_INTMEM_SIZE_E1H/2);
5305                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5306                                 STORM_INTMEM_SIZE_E1H/2);
5307                 bnx2x_init_fill(bp,
5308                                 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5309                                 0, STORM_INTMEM_SIZE_E1H/2);
5310                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5311                                 STORM_INTMEM_SIZE_E1H/2);
5312                 bnx2x_init_fill(bp,
5313                                 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5314                                 0, STORM_INTMEM_SIZE_E1H/2);
5315                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5316                                 STORM_INTMEM_SIZE_E1H/2);
5317                 bnx2x_init_fill(bp,
5318                                 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5319                                 0, STORM_INTMEM_SIZE_E1H/2);
5320         } else { /* E1 */
5321                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5322                                 STORM_INTMEM_SIZE_E1);
5323                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5324                                 STORM_INTMEM_SIZE_E1);
5325                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5326                                 STORM_INTMEM_SIZE_E1);
5327                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5328                                 STORM_INTMEM_SIZE_E1);
5329         }
5330
5331         bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5332         bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
5333         bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
5334         bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
5335
5336         /* sync semi rtc */
5337         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5338                0x80000000);
5339         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5340                0x80000000);
5341
5342         bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
5343         bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
5344         bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
5345
5346         REG_WR(bp, SRC_REG_SOFT_RST, 1);
5347         for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5348                 REG_WR(bp, i, 0xc0cac01a);
5349                 /* TODO: replace with something meaningful */
5350         }
5351         bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
5352         REG_WR(bp, SRC_REG_SOFT_RST, 0);
5353
5354         if (sizeof(union cdu_context) != 1024)
5355                 /* we currently assume that a context is 1024 bytes */
5356                 printk(KERN_ALERT PFX "please adjust the size of"
5357                        " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5358
5359         bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
5360         val = (4 << 24) + (0 << 12) + 1024;
5361         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5362         if (CHIP_IS_E1(bp)) {
5363                 /* !!! fix pxp client crdit until excel update */
5364                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5365                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
5366         }
5367
5368         bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
5369         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5370         /* enable context validation interrupt from CFC */
5371         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5372
5373         /* set the thresholds to prevent CFC/CDU race */
5374         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5375
5376         bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
5377         bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
5378
5379         /* PXPCS COMMON comes here */
5380         /* Reset PCIE errors for debug */
5381         REG_WR(bp, 0x2814, 0xffffffff);
5382         REG_WR(bp, 0x3820, 0xffffffff);
5383
5384         /* EMAC0 COMMON comes here */
5385         /* EMAC1 COMMON comes here */
5386         /* DBU COMMON comes here */
5387         /* DBG COMMON comes here */
5388
5389         bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
5390         if (CHIP_IS_E1H(bp)) {
5391                 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
5392                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
5393         }
5394
5395         if (CHIP_REV_IS_SLOW(bp))
5396                 msleep(200);
5397
5398         /* finish CFC init */
5399         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5400         if (val != 1) {
5401                 BNX2X_ERR("CFC LL_INIT failed\n");
5402                 return -EBUSY;
5403         }
5404         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5405         if (val != 1) {
5406                 BNX2X_ERR("CFC AC_INIT failed\n");
5407                 return -EBUSY;
5408         }
5409         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5410         if (val != 1) {
5411                 BNX2X_ERR("CFC CAM_INIT failed\n");
5412                 return -EBUSY;
5413         }
5414         REG_WR(bp, CFC_REG_DEBUG0, 0);
5415
5416         /* read NIG statistic
5417            to see if this is our first up since powerup */
5418         bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5419         val = *bnx2x_sp(bp, wb_data[0]);
5420
5421         /* do internal memory self test */
5422         if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
5423                 BNX2X_ERR("internal mem self test failed\n");
5424                 return -EBUSY;
5425         }
5426
5427         switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5428         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
5429         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5430                 /* Fan failure is indicated by SPIO 5 */
5431                 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5432                                MISC_REGISTERS_SPIO_INPUT_HI_Z);
5433
5434                 /* set to active low mode */
5435                 val = REG_RD(bp, MISC_REG_SPIO_INT);
5436                 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5437                                         MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5438                 REG_WR(bp, MISC_REG_SPIO_INT, val);
5439
5440                 /* enable interrupt to signal the IGU */
5441                 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5442                 val |= (1 << MISC_REGISTERS_SPIO_5);
5443                 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5444                 break;
5445
5446         default:
5447                 break;
5448         }
5449
5450         /* clear PXP2 attentions */
5451         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5452
5453         enable_blocks_attention(bp);
5454
5455         if (!BP_NOMCP(bp)) {
5456                 bnx2x_acquire_phy_lock(bp);
5457                 bnx2x_common_init_phy(bp, bp->common.shmem_base);
5458                 bnx2x_release_phy_lock(bp);
5459         } else
5460                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5461
5462         return 0;
5463 }
5464
5465 static int bnx2x_init_port(struct bnx2x *bp)
5466 {
5467         int port = BP_PORT(bp);
5468         u32 val;
5469
5470         DP(BNX2X_MSG_MCP, "starting port init  port %x\n", port);
5471
5472         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5473
5474         /* Port PXP comes here */
5475         /* Port PXP2 comes here */
5476 #ifdef BCM_ISCSI
5477         /* Port0  1
5478          * Port1  385 */
5479         i++;
5480         wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5481         wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5482         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5483         REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5484
5485         /* Port0  2
5486          * Port1  386 */
5487         i++;
5488         wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5489         wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5490         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5491         REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5492
5493         /* Port0  3
5494          * Port1  387 */
5495         i++;
5496         wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5497         wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5498         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5499         REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5500 #endif
5501         /* Port CMs come here */
5502         bnx2x_init_block(bp, (port ? XCM_PORT1_START : XCM_PORT0_START),
5503                              (port ? XCM_PORT1_END : XCM_PORT0_END));
5504
5505         /* Port QM comes here */
5506 #ifdef BCM_ISCSI
5507         REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5508         REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5509
5510         bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
5511                              func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
5512 #endif
5513         /* Port DQ comes here */
5514         /* Port BRB1 comes here */
5515         /* Port PRS comes here */
5516         /* Port TSDM comes here */
5517         /* Port CSDM comes here */
5518         /* Port USDM comes here */
5519         /* Port XSDM comes here */
5520         bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
5521                              port ? TSEM_PORT1_END : TSEM_PORT0_END);
5522         bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
5523                              port ? USEM_PORT1_END : USEM_PORT0_END);
5524         bnx2x_init_block(bp, port ? CSEM_PORT1_START : CSEM_PORT0_START,
5525                              port ? CSEM_PORT1_END : CSEM_PORT0_END);
5526         bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
5527                              port ? XSEM_PORT1_END : XSEM_PORT0_END);
5528         /* Port UPB comes here */
5529         /* Port XPB comes here */
5530
5531         bnx2x_init_block(bp, port ? PBF_PORT1_START : PBF_PORT0_START,
5532                              port ? PBF_PORT1_END : PBF_PORT0_END);
5533
5534         /* configure PBF to work without PAUSE mtu 9000 */
5535         REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5536
5537         /* update threshold */
5538         REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5539         /* update init credit */
5540         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5541
5542         /* probe changes */
5543         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5544         msleep(5);
5545         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5546
5547 #ifdef BCM_ISCSI
5548         /* tell the searcher where the T2 table is */
5549         REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);
5550
5551         wb_write[0] = U64_LO(bp->t2_mapping);
5552         wb_write[1] = U64_HI(bp->t2_mapping);
5553         REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
5554         wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
5555         wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
5556         REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
5557
5558         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
5559         /* Port SRCH comes here */
5560 #endif
5561         /* Port CDU comes here */
5562         /* Port CFC comes here */
5563
5564         if (CHIP_IS_E1(bp)) {
5565                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5566                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5567         }
5568         bnx2x_init_block(bp, port ? HC_PORT1_START : HC_PORT0_START,
5569                              port ? HC_PORT1_END : HC_PORT0_END);
5570
5571         bnx2x_init_block(bp, port ? MISC_AEU_PORT1_START :
5572                                     MISC_AEU_PORT0_START,
5573                              port ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END);
5574         /* init aeu_mask_attn_func_0/1:
5575          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5576          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5577          *             bits 4-7 are used for "per vn group attention" */
5578         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
5579                (IS_E1HMF(bp) ? 0xF7 : 0x7));
5580
5581         /* Port PXPCS comes here */
5582         /* Port EMAC0 comes here */
5583         /* Port EMAC1 comes here */
5584         /* Port DBU comes here */
5585         /* Port DBG comes here */
5586         bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START,
5587                              port ? NIG_PORT1_END : NIG_PORT0_END);
5588
5589         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5590
5591         if (CHIP_IS_E1H(bp)) {
5592                 u32 wsum;
5593                 struct cmng_struct_per_port m_cmng_port;
5594                 int vn;
5595
5596                 /* 0x2 disable e1hov, 0x1 enable */
5597                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5598                        (IS_E1HMF(bp) ? 0x1 : 0x2));
5599
5600                 /* Init RATE SHAPING and FAIRNESS contexts.
5601                    Initialize as if there is 10G link. */
5602                 wsum = bnx2x_calc_vn_wsum(bp);
5603                 bnx2x_init_port_minmax(bp, (int)wsum, 10000, &m_cmng_port);
5604                 if (IS_E1HMF(bp))
5605                         for (vn = VN_0; vn < E1HVN_MAX; vn++)
5606                                 bnx2x_init_vn_minmax(bp, 2*vn + port,
5607                                         wsum, 10000, &m_cmng_port);
5608         }
5609
5610         /* Port MCP comes here */
5611         /* Port DMAE comes here */
5612
5613         switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5614         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
5615         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5616                 /* add SPIO 5 to group 0 */
5617                 val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5618                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5619                 REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val);
5620                 break;
5621
5622         default:
5623                 break;
5624         }
5625
5626         bnx2x__link_reset(bp);
5627
5628         return 0;
5629 }
5630
5631 #define ILT_PER_FUNC            (768/2)
5632 #define FUNC_ILT_BASE(func)     (func * ILT_PER_FUNC)
5633 /* the phys address is shifted right 12 bits and has an added
5634    1=valid bit added to the 53rd bit
5635    then since this is a wide register(TM)
5636    we split it into two 32 bit writes
5637  */
5638 #define ONCHIP_ADDR1(x)         ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
5639 #define ONCHIP_ADDR2(x)         ((u32)((1 << 20) | ((u64)x >> 44)))
5640 #define PXP_ONE_ILT(x)          (((x) << 10) | x)
5641 #define PXP_ILT_RANGE(f, l)     (((l) << 10) | f)
5642
5643 #define CNIC_ILT_LINES          0
5644
5645 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5646 {
5647         int reg;
5648
5649         if (CHIP_IS_E1H(bp))
5650                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5651         else /* E1 */
5652                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5653
5654         bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5655 }
5656
5657 static int bnx2x_init_func(struct bnx2x *bp)
5658 {
5659         int port = BP_PORT(bp);
5660         int func = BP_FUNC(bp);
5661         u32 addr, val;
5662         int i;
5663
5664         DP(BNX2X_MSG_MCP, "starting func init  func %x\n", func);
5665
5666         /* set MSI reconfigure capability */
5667         addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5668         val = REG_RD(bp, addr);
5669         val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5670         REG_WR(bp, addr, val);
5671
5672         i = FUNC_ILT_BASE(func);
5673
5674         bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
5675         if (CHIP_IS_E1H(bp)) {
5676                 REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
5677                 REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
5678         } else /* E1 */
5679                 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
5680                        PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
5681
5682
5683         if (CHIP_IS_E1H(bp)) {
5684                 for (i = 0; i < 9; i++)
5685                         bnx2x_init_block(bp,
5686                                          cm_start[func][i], cm_end[func][i]);
5687
5688                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5689                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
5690         }
5691
5692         /* HC init per function */
5693         if (CHIP_IS_E1H(bp)) {
5694                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5695
5696                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5697                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5698         }
5699         bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]);
5700
5701         /* Reset PCIE errors for debug */
5702         REG_WR(bp, 0x2114, 0xffffffff);
5703         REG_WR(bp, 0x2120, 0xffffffff);
5704
5705         return 0;
5706 }
5707
5708 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5709 {
5710         int i, rc = 0;
5711
5712         DP(BNX2X_MSG_MCP, "function %d  load_code %x\n",
5713            BP_FUNC(bp), load_code);
5714
5715         bp->dmae_ready = 0;
5716         mutex_init(&bp->dmae_mutex);
5717         bnx2x_gunzip_init(bp);
5718
5719         switch (load_code) {
5720         case FW_MSG_CODE_DRV_LOAD_COMMON:
5721                 rc = bnx2x_init_common(bp);
5722                 if (rc)
5723                         goto init_hw_err;
5724                 /* no break */
5725
5726         case FW_MSG_CODE_DRV_LOAD_PORT:
5727                 bp->dmae_ready = 1;
5728                 rc = bnx2x_init_port(bp);
5729                 if (rc)
5730                         goto init_hw_err;
5731                 /* no break */
5732
5733         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5734                 bp->dmae_ready = 1;
5735                 rc = bnx2x_init_func(bp);
5736                 if (rc)
5737                         goto init_hw_err;
5738                 break;
5739
5740         default:
5741                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5742                 break;
5743         }
5744
5745         if (!BP_NOMCP(bp)) {
5746                 int func = BP_FUNC(bp);
5747
5748                 bp->fw_drv_pulse_wr_seq =
5749                                 (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
5750                                  DRV_PULSE_SEQ_MASK);
5751                 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
5752                 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x  func_stx 0x%x\n",
5753                    bp->fw_drv_pulse_wr_seq, bp->func_stx);
5754         } else
5755                 bp->func_stx = 0;
5756
5757         /* this needs to be done before gunzip end */
5758         bnx2x_zero_def_sb(bp);
5759         for_each_queue(bp, i)
5760                 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
5761
5762 init_hw_err:
5763         bnx2x_gunzip_end(bp);
5764
5765         return rc;
5766 }
5767
5768 /* send the MCP a request, block until there is a reply */
5769 static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5770 {
5771         int func = BP_FUNC(bp);
5772         u32 seq = ++bp->fw_seq;
5773         u32 rc = 0;
5774         u32 cnt = 1;
5775         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
5776
5777         SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
5778         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
5779
5780         do {
5781                 /* let the FW do it's magic ... */
5782                 msleep(delay);
5783
5784                 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
5785
5786                 /* Give the FW up to 2 sec