bnx2x: Flow control enhancement
[linux-2.6.git] / drivers / net / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2009 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>  /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/bitops.h>
35 #include <linux/irq.h>
36 #include <linux/delay.h>
37 #include <asm/byteorder.h>
38 #include <linux/time.h>
39 #include <linux/ethtool.h>
40 #include <linux/mii.h>
41 #include <linux/if_vlan.h>
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
51 #include <linux/io.h>
52
53 #include "bnx2x_reg.h"
54 #include "bnx2x_fw_defs.h"
55 #include "bnx2x_hsi.h"
56 #include "bnx2x_link.h"
57 #include "bnx2x.h"
58 #include "bnx2x_init.h"
59
60 #define DRV_MODULE_VERSION      "1.45.26"
61 #define DRV_MODULE_RELDATE      "2009/01/26"
62 #define BNX2X_BC_VER            0x040200
63
64 /* Time in jiffies before concluding the transmitter is hung */
65 #define TX_TIMEOUT              (5*HZ)
66
67 static char version[] __devinitdata =
68         "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
69         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70
71 MODULE_AUTHOR("Eliezer Tamir");
72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION);
75
76 static int multi_mode = 1;
77 module_param(multi_mode, int, 0);
78
79 static int disable_tpa;
80 static int poll;
81 static int debug;
82 static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
83
84 module_param(disable_tpa, int, 0);
85
86 static int int_mode;
87 module_param(int_mode, int, 0);
88 MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)");
89
90 module_param(poll, int, 0);
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
93 MODULE_PARM_DESC(poll, "use polling (for debug)");
94 MODULE_PARM_DESC(debug, "default debug msglevel");
95
96 static struct workqueue_struct *bnx2x_wq;
97
98 enum bnx2x_board_type {
99         BCM57710 = 0,
100         BCM57711 = 1,
101         BCM57711E = 2,
102 };
103
104 /* indexed by board_type, above */
105 static struct {
106         char *name;
107 } board_info[] __devinitdata = {
108         { "Broadcom NetXtreme II BCM57710 XGb" },
109         { "Broadcom NetXtreme II BCM57711 XGb" },
110         { "Broadcom NetXtreme II BCM57711E XGb" }
111 };
112
113
114 static const struct pci_device_id bnx2x_pci_tbl[] = {
115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
121         { 0 }
122 };
123
124 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
125
126 /****************************************************************************
127 * General service functions
128 ****************************************************************************/
129
130 /* used only at init
131  * locking is done by mcp
132  */
133 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
134 {
135         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
136         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
137         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
138                                PCICFG_VENDOR_ID_OFFSET);
139 }
140
141 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
142 {
143         u32 val;
144
145         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
146         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
147         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
148                                PCICFG_VENDOR_ID_OFFSET);
149
150         return val;
151 }
152
153 static const u32 dmae_reg_go_c[] = {
154         DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
155         DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
156         DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
157         DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
158 };
159
160 /* copy command into DMAE command memory and set DMAE command go */
161 static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
162                             int idx)
163 {
164         u32 cmd_offset;
165         int i;
166
167         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
168         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
169                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
170
171                 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
172                    idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
173         }
174         REG_WR(bp, dmae_reg_go_c[idx], 1);
175 }
176
177 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
178                       u32 len32)
179 {
180         struct dmae_command *dmae = &bp->init_dmae;
181         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
182         int cnt = 200;
183
184         if (!bp->dmae_ready) {
185                 u32 *data = bnx2x_sp(bp, wb_data[0]);
186
187                 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
188                    "  using indirect\n", dst_addr, len32);
189                 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
190                 return;
191         }
192
193         mutex_lock(&bp->dmae_mutex);
194
195         memset(dmae, 0, sizeof(struct dmae_command));
196
197         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
198                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
199                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
200 #ifdef __BIG_ENDIAN
201                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
202 #else
203                         DMAE_CMD_ENDIANITY_DW_SWAP |
204 #endif
205                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
206                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
207         dmae->src_addr_lo = U64_LO(dma_addr);
208         dmae->src_addr_hi = U64_HI(dma_addr);
209         dmae->dst_addr_lo = dst_addr >> 2;
210         dmae->dst_addr_hi = 0;
211         dmae->len = len32;
212         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
213         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
214         dmae->comp_val = DMAE_COMP_VAL;
215
216         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
217            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
218                     "dst_addr [%x:%08x (%08x)]\n"
219            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
220            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
221            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
222            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
223         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
224            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
225            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
226
227         *wb_comp = 0;
228
229         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
230
231         udelay(5);
232
233         while (*wb_comp != DMAE_COMP_VAL) {
234                 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
235
236                 if (!cnt) {
237                         BNX2X_ERR("dmae timeout!\n");
238                         break;
239                 }
240                 cnt--;
241                 /* adjust delay for emulation/FPGA */
242                 if (CHIP_REV_IS_SLOW(bp))
243                         msleep(100);
244                 else
245                         udelay(5);
246         }
247
248         mutex_unlock(&bp->dmae_mutex);
249 }
250
251 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
252 {
253         struct dmae_command *dmae = &bp->init_dmae;
254         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
255         int cnt = 200;
256
257         if (!bp->dmae_ready) {
258                 u32 *data = bnx2x_sp(bp, wb_data[0]);
259                 int i;
260
261                 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x  len32 %d)"
262                    "  using indirect\n", src_addr, len32);
263                 for (i = 0; i < len32; i++)
264                         data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
265                 return;
266         }
267
268         mutex_lock(&bp->dmae_mutex);
269
270         memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
271         memset(dmae, 0, sizeof(struct dmae_command));
272
273         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
274                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
275                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
276 #ifdef __BIG_ENDIAN
277                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
278 #else
279                         DMAE_CMD_ENDIANITY_DW_SWAP |
280 #endif
281                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
282                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
283         dmae->src_addr_lo = src_addr >> 2;
284         dmae->src_addr_hi = 0;
285         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
286         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
287         dmae->len = len32;
288         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
289         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
290         dmae->comp_val = DMAE_COMP_VAL;
291
292         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
293            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
294                     "dst_addr [%x:%08x (%08x)]\n"
295            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
296            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
297            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
298            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
299
300         *wb_comp = 0;
301
302         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
303
304         udelay(5);
305
306         while (*wb_comp != DMAE_COMP_VAL) {
307
308                 if (!cnt) {
309                         BNX2X_ERR("dmae timeout!\n");
310                         break;
311                 }
312                 cnt--;
313                 /* adjust delay for emulation/FPGA */
314                 if (CHIP_REV_IS_SLOW(bp))
315                         msleep(100);
316                 else
317                         udelay(5);
318         }
319         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
320            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
321            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
322
323         mutex_unlock(&bp->dmae_mutex);
324 }
325
326 /* used only for slowpath so not inlined */
327 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
328 {
329         u32 wb_write[2];
330
331         wb_write[0] = val_hi;
332         wb_write[1] = val_lo;
333         REG_WR_DMAE(bp, reg, wb_write, 2);
334 }
335
336 #ifdef USE_WB_RD
337 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
338 {
339         u32 wb_data[2];
340
341         REG_RD_DMAE(bp, reg, wb_data, 2);
342
343         return HILO_U64(wb_data[0], wb_data[1]);
344 }
345 #endif
346
347 static int bnx2x_mc_assert(struct bnx2x *bp)
348 {
349         char last_idx;
350         int i, rc = 0;
351         u32 row0, row1, row2, row3;
352
353         /* XSTORM */
354         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
355                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
356         if (last_idx)
357                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
358
359         /* print the asserts */
360         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
361
362                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
363                               XSTORM_ASSERT_LIST_OFFSET(i));
364                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
365                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
366                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
367                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
368                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
369                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
370
371                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
372                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
373                                   " 0x%08x 0x%08x 0x%08x\n",
374                                   i, row3, row2, row1, row0);
375                         rc++;
376                 } else {
377                         break;
378                 }
379         }
380
381         /* TSTORM */
382         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
383                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
384         if (last_idx)
385                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
386
387         /* print the asserts */
388         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
389
390                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
391                               TSTORM_ASSERT_LIST_OFFSET(i));
392                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
393                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
394                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
395                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
396                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
397                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
398
399                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
400                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
401                                   " 0x%08x 0x%08x 0x%08x\n",
402                                   i, row3, row2, row1, row0);
403                         rc++;
404                 } else {
405                         break;
406                 }
407         }
408
409         /* CSTORM */
410         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
411                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
412         if (last_idx)
413                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
414
415         /* print the asserts */
416         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
417
418                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
419                               CSTORM_ASSERT_LIST_OFFSET(i));
420                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
421                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
422                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
423                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
424                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
425                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
426
427                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
428                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
429                                   " 0x%08x 0x%08x 0x%08x\n",
430                                   i, row3, row2, row1, row0);
431                         rc++;
432                 } else {
433                         break;
434                 }
435         }
436
437         /* USTORM */
438         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
439                            USTORM_ASSERT_LIST_INDEX_OFFSET);
440         if (last_idx)
441                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
442
443         /* print the asserts */
444         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
445
446                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
447                               USTORM_ASSERT_LIST_OFFSET(i));
448                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
449                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
450                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
451                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
452                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
453                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
454
455                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
456                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
457                                   " 0x%08x 0x%08x 0x%08x\n",
458                                   i, row3, row2, row1, row0);
459                         rc++;
460                 } else {
461                         break;
462                 }
463         }
464
465         return rc;
466 }
467
468 static void bnx2x_fw_dump(struct bnx2x *bp)
469 {
470         u32 mark, offset;
471         u32 data[9];
472         int word;
473
474         mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
475         mark = ((mark + 0x3) & ~0x3);
476         printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
477
478         for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
479                 for (word = 0; word < 8; word++)
480                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
481                                                   offset + 4*word));
482                 data[8] = 0x0;
483                 printk(KERN_CONT "%s", (char *)data);
484         }
485         for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
486                 for (word = 0; word < 8; word++)
487                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
488                                                   offset + 4*word));
489                 data[8] = 0x0;
490                 printk(KERN_CONT "%s", (char *)data);
491         }
492         printk("\n" KERN_ERR PFX "end of fw dump\n");
493 }
494
495 static void bnx2x_panic_dump(struct bnx2x *bp)
496 {
497         int i;
498         u16 j, start, end;
499
500         bp->stats_state = STATS_STATE_DISABLED;
501         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
502
503         BNX2X_ERR("begin crash dump -----------------\n");
504
505         for_each_queue(bp, i) {
506                 struct bnx2x_fastpath *fp = &bp->fp[i];
507                 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
508
509                 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
510                           "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)\n",
511                           i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
512                           fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
513                 BNX2X_ERR("          rx_bd_prod(%x)  rx_bd_cons(%x)"
514                           "  *rx_bd_cons_sb(%x)  rx_comp_prod(%x)"
515                           "  rx_comp_cons(%x)  *rx_cons_sb(%x)\n",
516                           fp->rx_bd_prod, fp->rx_bd_cons,
517                           le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
518                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
519                 BNX2X_ERR("          rx_sge_prod(%x)  last_max_sge(%x)"
520                           "  fp_c_idx(%x)  *sb_c_idx(%x)  fp_u_idx(%x)"
521                           "  *sb_u_idx(%x)  bd data(%x,%x)\n",
522                           fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx,
523                           fp->status_blk->c_status_block.status_block_index,
524                           fp->fp_u_idx,
525                           fp->status_blk->u_status_block.status_block_index,
526                           hw_prods->packets_prod, hw_prods->bds_prod);
527
528                 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
529                 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
530                 for (j = start; j < end; j++) {
531                         struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
532
533                         BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
534                                   sw_bd->skb, sw_bd->first_bd);
535                 }
536
537                 start = TX_BD(fp->tx_bd_cons - 10);
538                 end = TX_BD(fp->tx_bd_cons + 254);
539                 for (j = start; j < end; j++) {
540                         u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
541
542                         BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
543                                   j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
544                 }
545
546                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
547                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
548                 for (j = start; j < end; j++) {
549                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
550                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
551
552                         BNX2X_ERR("rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
553                                   j, rx_bd[1], rx_bd[0], sw_bd->skb);
554                 }
555
556                 start = RX_SGE(fp->rx_sge_prod);
557                 end = RX_SGE(fp->last_max_sge);
558                 for (j = start; j < end; j++) {
559                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
560                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
561
562                         BNX2X_ERR("rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
563                                   j, rx_sge[1], rx_sge[0], sw_page->page);
564                 }
565
566                 start = RCQ_BD(fp->rx_comp_cons - 10);
567                 end = RCQ_BD(fp->rx_comp_cons + 503);
568                 for (j = start; j < end; j++) {
569                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
570
571                         BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
572                                   j, cqe[0], cqe[1], cqe[2], cqe[3]);
573                 }
574         }
575
576         BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
577                   "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
578                   "  spq_prod_idx(%u)\n",
579                   bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
580                   bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
581
582         bnx2x_fw_dump(bp);
583         bnx2x_mc_assert(bp);
584         BNX2X_ERR("end crash dump -----------------\n");
585 }
586
587 static void bnx2x_int_enable(struct bnx2x *bp)
588 {
589         int port = BP_PORT(bp);
590         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
591         u32 val = REG_RD(bp, addr);
592         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
593         int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
594
595         if (msix) {
596                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
597                          HC_CONFIG_0_REG_INT_LINE_EN_0);
598                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
599                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
600         } else if (msi) {
601                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
602                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
603                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
604                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
605         } else {
606                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
607                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
608                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
609                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
610
611                 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
612                    val, port, addr);
613
614                 REG_WR(bp, addr, val);
615
616                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
617         }
618
619         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  mode %s\n",
620            val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
621
622         REG_WR(bp, addr, val);
623
624         if (CHIP_IS_E1H(bp)) {
625                 /* init leading/trailing edge */
626                 if (IS_E1HMF(bp)) {
627                         val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
628                         if (bp->port.pmf)
629                                 /* enable nig attention */
630                                 val |= 0x0100;
631                 } else
632                         val = 0xffff;
633
634                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
635                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
636         }
637 }
638
639 static void bnx2x_int_disable(struct bnx2x *bp)
640 {
641         int port = BP_PORT(bp);
642         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
643         u32 val = REG_RD(bp, addr);
644
645         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
646                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
647                  HC_CONFIG_0_REG_INT_LINE_EN_0 |
648                  HC_CONFIG_0_REG_ATTN_BIT_EN_0);
649
650         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
651            val, port, addr);
652
653         /* flush all outstanding writes */
654         mmiowb();
655
656         REG_WR(bp, addr, val);
657         if (REG_RD(bp, addr) != val)
658                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
659 }
660
661 static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
662 {
663         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
664         int i, offset;
665
666         /* disable interrupt handling */
667         atomic_inc(&bp->intr_sem);
668         if (disable_hw)
669                 /* prevent the HW from sending interrupts */
670                 bnx2x_int_disable(bp);
671
672         /* make sure all ISRs are done */
673         if (msix) {
674                 synchronize_irq(bp->msix_table[0].vector);
675                 offset = 1;
676                 for_each_queue(bp, i)
677                         synchronize_irq(bp->msix_table[i + offset].vector);
678         } else
679                 synchronize_irq(bp->pdev->irq);
680
681         /* make sure sp_task is not running */
682         cancel_delayed_work(&bp->sp_task);
683         flush_workqueue(bnx2x_wq);
684 }
685
686 /* fast path */
687
688 /*
689  * General service functions
690  */
691
692 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
693                                 u8 storm, u16 index, u8 op, u8 update)
694 {
695         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
696                        COMMAND_REG_INT_ACK);
697         struct igu_ack_register igu_ack;
698
699         igu_ack.status_block_index = index;
700         igu_ack.sb_id_and_flags =
701                         ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
702                          (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
703                          (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
704                          (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
705
706         DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
707            (*(u32 *)&igu_ack), hc_addr);
708         REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
709 }
710
711 static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
712 {
713         struct host_status_block *fpsb = fp->status_blk;
714         u16 rc = 0;
715
716         barrier(); /* status block is written to by the chip */
717         if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
718                 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
719                 rc |= 1;
720         }
721         if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
722                 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
723                 rc |= 2;
724         }
725         return rc;
726 }
727
728 static u16 bnx2x_ack_int(struct bnx2x *bp)
729 {
730         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
731                        COMMAND_REG_SIMD_MASK);
732         u32 result = REG_RD(bp, hc_addr);
733
734         DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
735            result, hc_addr);
736
737         return result;
738 }
739
740
741 /*
742  * fast path service functions
743  */
744
745 static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
746 {
747         u16 tx_cons_sb;
748
749         /* Tell compiler that status block fields can change */
750         barrier();
751         tx_cons_sb = le16_to_cpu(*fp->tx_cons_sb);
752         return (fp->tx_pkt_cons != tx_cons_sb);
753 }
754
755 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
756 {
757         /* Tell compiler that consumer and producer can change */
758         barrier();
759         return (fp->tx_pkt_prod != fp->tx_pkt_cons);
760
761 }
762
763 /* free skb in the packet ring at pos idx
764  * return idx of last bd freed
765  */
766 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
767                              u16 idx)
768 {
769         struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
770         struct eth_tx_bd *tx_bd;
771         struct sk_buff *skb = tx_buf->skb;
772         u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
773         int nbd;
774
775         DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
776            idx, tx_buf, skb);
777
778         /* unmap first bd */
779         DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
780         tx_bd = &fp->tx_desc_ring[bd_idx];
781         pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
782                          BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
783
784         nbd = le16_to_cpu(tx_bd->nbd) - 1;
785         new_cons = nbd + tx_buf->first_bd;
786 #ifdef BNX2X_STOP_ON_ERROR
787         if (nbd > (MAX_SKB_FRAGS + 2)) {
788                 BNX2X_ERR("BAD nbd!\n");
789                 bnx2x_panic();
790         }
791 #endif
792
793         /* Skip a parse bd and the TSO split header bd
794            since they have no mapping */
795         if (nbd)
796                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
797
798         if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
799                                            ETH_TX_BD_FLAGS_TCP_CSUM |
800                                            ETH_TX_BD_FLAGS_SW_LSO)) {
801                 if (--nbd)
802                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
803                 tx_bd = &fp->tx_desc_ring[bd_idx];
804                 /* is this a TSO split header bd? */
805                 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
806                         if (--nbd)
807                                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
808                 }
809         }
810
811         /* now free frags */
812         while (nbd > 0) {
813
814                 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
815                 tx_bd = &fp->tx_desc_ring[bd_idx];
816                 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
817                                BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
818                 if (--nbd)
819                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
820         }
821
822         /* release skb */
823         WARN_ON(!skb);
824         dev_kfree_skb(skb);
825         tx_buf->first_bd = 0;
826         tx_buf->skb = NULL;
827
828         return new_cons;
829 }
830
831 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
832 {
833         s16 used;
834         u16 prod;
835         u16 cons;
836
837         barrier(); /* Tell compiler that prod and cons can change */
838         prod = fp->tx_bd_prod;
839         cons = fp->tx_bd_cons;
840
841         /* NUM_TX_RINGS = number of "next-page" entries
842            It will be used as a threshold */
843         used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
844
845 #ifdef BNX2X_STOP_ON_ERROR
846         WARN_ON(used < 0);
847         WARN_ON(used > fp->bp->tx_ring_size);
848         WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
849 #endif
850
851         return (s16)(fp->bp->tx_ring_size) - used;
852 }
853
854 static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
855 {
856         struct bnx2x *bp = fp->bp;
857         struct netdev_queue *txq;
858         u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
859         int done = 0;
860
861 #ifdef BNX2X_STOP_ON_ERROR
862         if (unlikely(bp->panic))
863                 return;
864 #endif
865
866         txq = netdev_get_tx_queue(bp->dev, fp->index);
867         hw_cons = le16_to_cpu(*fp->tx_cons_sb);
868         sw_cons = fp->tx_pkt_cons;
869
870         while (sw_cons != hw_cons) {
871                 u16 pkt_cons;
872
873                 pkt_cons = TX_BD(sw_cons);
874
875                 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
876
877                 DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %u\n",
878                    hw_cons, sw_cons, pkt_cons);
879
880 /*              if (NEXT_TX_IDX(sw_cons) != hw_cons) {
881                         rmb();
882                         prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
883                 }
884 */
885                 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
886                 sw_cons++;
887                 done++;
888
889                 if (done == work)
890                         break;
891         }
892
893         fp->tx_pkt_cons = sw_cons;
894         fp->tx_bd_cons = bd_cons;
895
896         /* Need to make the tx_bd_cons update visible to start_xmit()
897          * before checking for netif_tx_queue_stopped().  Without the
898          * memory barrier, there is a small possibility that start_xmit()
899          * will miss it and cause the queue to be stopped forever.
900          */
901         smp_mb();
902
903         /* TBD need a thresh? */
904         if (unlikely(netif_tx_queue_stopped(txq))) {
905
906                 __netif_tx_lock(txq, smp_processor_id());
907
908                 if ((netif_tx_queue_stopped(txq)) &&
909                     (bp->state == BNX2X_STATE_OPEN) &&
910                     (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
911                         netif_tx_wake_queue(txq);
912
913                 __netif_tx_unlock(txq);
914         }
915 }
916
917
918 static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
919                            union eth_rx_cqe *rr_cqe)
920 {
921         struct bnx2x *bp = fp->bp;
922         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
923         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
924
925         DP(BNX2X_MSG_SP,
926            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
927            FP_IDX(fp), cid, command, bp->state,
928            rr_cqe->ramrod_cqe.ramrod_type);
929
930         bp->spq_left++;
931
932         if (FP_IDX(fp)) {
933                 switch (command | fp->state) {
934                 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
935                                                 BNX2X_FP_STATE_OPENING):
936                         DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
937                            cid);
938                         fp->state = BNX2X_FP_STATE_OPEN;
939                         break;
940
941                 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
942                         DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
943                            cid);
944                         fp->state = BNX2X_FP_STATE_HALTED;
945                         break;
946
947                 default:
948                         BNX2X_ERR("unexpected MC reply (%d)  "
949                                   "fp->state is %x\n", command, fp->state);
950                         break;
951                 }
952                 mb(); /* force bnx2x_wait_ramrod() to see the change */
953                 return;
954         }
955
956         switch (command | bp->state) {
957         case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
958                 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
959                 bp->state = BNX2X_STATE_OPEN;
960                 break;
961
962         case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
963                 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
964                 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
965                 fp->state = BNX2X_FP_STATE_HALTED;
966                 break;
967
968         case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
969                 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
970                 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
971                 break;
972
973
974         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
975         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
976                 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
977                 bp->set_mac_pending = 0;
978                 break;
979
980         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
981                 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
982                 break;
983
984         default:
985                 BNX2X_ERR("unexpected MC reply (%d)  bp->state is %x\n",
986                           command, bp->state);
987                 break;
988         }
989         mb(); /* force bnx2x_wait_ramrod() to see the change */
990 }
991
992 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
993                                      struct bnx2x_fastpath *fp, u16 index)
994 {
995         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
996         struct page *page = sw_buf->page;
997         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
998
999         /* Skip "next page" elements */
1000         if (!page)
1001                 return;
1002
1003         pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
1004                        SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1005         __free_pages(page, PAGES_PER_SGE_SHIFT);
1006
1007         sw_buf->page = NULL;
1008         sge->addr_hi = 0;
1009         sge->addr_lo = 0;
1010 }
1011
1012 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1013                                            struct bnx2x_fastpath *fp, int last)
1014 {
1015         int i;
1016
1017         for (i = 0; i < last; i++)
1018                 bnx2x_free_rx_sge(bp, fp, i);
1019 }
1020
1021 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
1022                                      struct bnx2x_fastpath *fp, u16 index)
1023 {
1024         struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
1025         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1026         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1027         dma_addr_t mapping;
1028
1029         if (unlikely(page == NULL))
1030                 return -ENOMEM;
1031
1032         mapping = pci_map_page(bp->pdev, page, 0, SGE_PAGE_SIZE*PAGES_PER_SGE,
1033                                PCI_DMA_FROMDEVICE);
1034         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1035                 __free_pages(page, PAGES_PER_SGE_SHIFT);
1036                 return -ENOMEM;
1037         }
1038
1039         sw_buf->page = page;
1040         pci_unmap_addr_set(sw_buf, mapping, mapping);
1041
1042         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1043         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1044
1045         return 0;
1046 }
1047
1048 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1049                                      struct bnx2x_fastpath *fp, u16 index)
1050 {
1051         struct sk_buff *skb;
1052         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1053         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1054         dma_addr_t mapping;
1055
1056         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1057         if (unlikely(skb == NULL))
1058                 return -ENOMEM;
1059
1060         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_size,
1061                                  PCI_DMA_FROMDEVICE);
1062         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1063                 dev_kfree_skb(skb);
1064                 return -ENOMEM;
1065         }
1066
1067         rx_buf->skb = skb;
1068         pci_unmap_addr_set(rx_buf, mapping, mapping);
1069
1070         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1071         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1072
1073         return 0;
1074 }
1075
1076 /* note that we are not allocating a new skb,
1077  * we are just moving one from cons to prod
1078  * we are not creating a new mapping,
1079  * so there is no need to check for dma_mapping_error().
1080  */
1081 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1082                                struct sk_buff *skb, u16 cons, u16 prod)
1083 {
1084         struct bnx2x *bp = fp->bp;
1085         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1086         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1087         struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1088         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1089
1090         pci_dma_sync_single_for_device(bp->pdev,
1091                                        pci_unmap_addr(cons_rx_buf, mapping),
1092                                        bp->rx_offset + RX_COPY_THRESH,
1093                                        PCI_DMA_FROMDEVICE);
1094
1095         prod_rx_buf->skb = cons_rx_buf->skb;
1096         pci_unmap_addr_set(prod_rx_buf, mapping,
1097                            pci_unmap_addr(cons_rx_buf, mapping));
1098         *prod_bd = *cons_bd;
1099 }
1100
1101 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1102                                              u16 idx)
1103 {
1104         u16 last_max = fp->last_max_sge;
1105
1106         if (SUB_S16(idx, last_max) > 0)
1107                 fp->last_max_sge = idx;
1108 }
1109
1110 static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1111 {
1112         int i, j;
1113
1114         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1115                 int idx = RX_SGE_CNT * i - 1;
1116
1117                 for (j = 0; j < 2; j++) {
1118                         SGE_MASK_CLEAR_BIT(fp, idx);
1119                         idx--;
1120                 }
1121         }
1122 }
1123
1124 static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1125                                   struct eth_fast_path_rx_cqe *fp_cqe)
1126 {
1127         struct bnx2x *bp = fp->bp;
1128         u16 sge_len = SGE_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
1129                                      le16_to_cpu(fp_cqe->len_on_bd)) >>
1130                       SGE_PAGE_SHIFT;
1131         u16 last_max, last_elem, first_elem;
1132         u16 delta = 0;
1133         u16 i;
1134
1135         if (!sge_len)
1136                 return;
1137
1138         /* First mark all used pages */
1139         for (i = 0; i < sge_len; i++)
1140                 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1141
1142         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1143            sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1144
1145         /* Here we assume that the last SGE index is the biggest */
1146         prefetch((void *)(fp->sge_mask));
1147         bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1148
1149         last_max = RX_SGE(fp->last_max_sge);
1150         last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1151         first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1152
1153         /* If ring is not full */
1154         if (last_elem + 1 != first_elem)
1155                 last_elem++;
1156
1157         /* Now update the prod */
1158         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1159                 if (likely(fp->sge_mask[i]))
1160                         break;
1161
1162                 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1163                 delta += RX_SGE_MASK_ELEM_SZ;
1164         }
1165
1166         if (delta > 0) {
1167                 fp->rx_sge_prod += delta;
1168                 /* clear page-end entries */
1169                 bnx2x_clear_sge_mask_next_elems(fp);
1170         }
1171
1172         DP(NETIF_MSG_RX_STATUS,
1173            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
1174            fp->last_max_sge, fp->rx_sge_prod);
1175 }
1176
1177 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1178 {
1179         /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1180         memset(fp->sge_mask, 0xff,
1181                (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1182
1183         /* Clear the two last indices in the page to 1:
1184            these are the indices that correspond to the "next" element,
1185            hence will never be indicated and should be removed from
1186            the calculations. */
1187         bnx2x_clear_sge_mask_next_elems(fp);
1188 }
1189
1190 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1191                             struct sk_buff *skb, u16 cons, u16 prod)
1192 {
1193         struct bnx2x *bp = fp->bp;
1194         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1195         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1196         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1197         dma_addr_t mapping;
1198
1199         /* move empty skb from pool to prod and map it */
1200         prod_rx_buf->skb = fp->tpa_pool[queue].skb;
1201         mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
1202                                  bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1203         pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
1204
1205         /* move partial skb from cons to pool (don't unmap yet) */
1206         fp->tpa_pool[queue] = *cons_rx_buf;
1207
1208         /* mark bin state as start - print error if current state != stop */
1209         if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1210                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1211
1212         fp->tpa_state[queue] = BNX2X_TPA_START;
1213
1214         /* point prod_bd to new skb */
1215         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1216         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1217
1218 #ifdef BNX2X_STOP_ON_ERROR
1219         fp->tpa_queue_used |= (1 << queue);
1220 #ifdef __powerpc64__
1221         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1222 #else
1223         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1224 #endif
1225            fp->tpa_queue_used);
1226 #endif
1227 }
1228
1229 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1230                                struct sk_buff *skb,
1231                                struct eth_fast_path_rx_cqe *fp_cqe,
1232                                u16 cqe_idx)
1233 {
1234         struct sw_rx_page *rx_pg, old_rx_pg;
1235         u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1236         u32 i, frag_len, frag_size, pages;
1237         int err;
1238         int j;
1239
1240         frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
1241         pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
1242
1243         /* This is needed in order to enable forwarding support */
1244         if (frag_size)
1245                 skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
1246                                                max(frag_size, (u32)len_on_bd));
1247
1248 #ifdef BNX2X_STOP_ON_ERROR
1249         if (pages >
1250             min((u32)8, (u32)MAX_SKB_FRAGS) * SGE_PAGE_SIZE * PAGES_PER_SGE) {
1251                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1252                           pages, cqe_idx);
1253                 BNX2X_ERR("fp_cqe->pkt_len = %d  fp_cqe->len_on_bd = %d\n",
1254                           fp_cqe->pkt_len, len_on_bd);
1255                 bnx2x_panic();
1256                 return -EINVAL;
1257         }
1258 #endif
1259
1260         /* Run through the SGL and compose the fragmented skb */
1261         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1262                 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1263
1264                 /* FW gives the indices of the SGE as if the ring is an array
1265                    (meaning that "next" element will consume 2 indices) */
1266                 frag_len = min(frag_size, (u32)(SGE_PAGE_SIZE*PAGES_PER_SGE));
1267                 rx_pg = &fp->rx_page_ring[sge_idx];
1268                 old_rx_pg = *rx_pg;
1269
1270                 /* If we fail to allocate a substitute page, we simply stop
1271                    where we are and drop the whole packet */
1272                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1273                 if (unlikely(err)) {
1274                         fp->eth_q_stats.rx_skb_alloc_failed++;
1275                         return err;
1276                 }
1277
1278                 /* Unmap the page as we r going to pass it to the stack */
1279                 pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
1280                               SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1281
1282                 /* Add one frag and update the appropriate fields in the skb */
1283                 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1284
1285                 skb->data_len += frag_len;
1286                 skb->truesize += frag_len;
1287                 skb->len += frag_len;
1288
1289                 frag_size -= frag_len;
1290         }
1291
1292         return 0;
1293 }
1294
1295 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1296                            u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1297                            u16 cqe_idx)
1298 {
1299         struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1300         struct sk_buff *skb = rx_buf->skb;
1301         /* alloc new skb */
1302         struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1303
1304         /* Unmap skb in the pool anyway, as we are going to change
1305            pool entry status to BNX2X_TPA_STOP even if new skb allocation
1306            fails. */
1307         pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1308                          bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1309
1310         if (likely(new_skb)) {
1311                 /* fix ip xsum and give it to the stack */
1312                 /* (no need to map the new skb) */
1313 #ifdef BCM_VLAN
1314                 int is_vlan_cqe =
1315                         (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1316                          PARSING_FLAGS_VLAN);
1317                 int is_not_hwaccel_vlan_cqe =
1318                         (is_vlan_cqe && (!(bp->flags & HW_VLAN_RX_FLAG)));
1319 #endif
1320
1321                 prefetch(skb);
1322                 prefetch(((char *)(skb)) + 128);
1323
1324 #ifdef BNX2X_STOP_ON_ERROR
1325                 if (pad + len > bp->rx_buf_size) {
1326                         BNX2X_ERR("skb_put is about to fail...  "
1327                                   "pad %d  len %d  rx_buf_size %d\n",
1328                                   pad, len, bp->rx_buf_size);
1329                         bnx2x_panic();
1330                         return;
1331                 }
1332 #endif
1333
1334                 skb_reserve(skb, pad);
1335                 skb_put(skb, len);
1336
1337                 skb->protocol = eth_type_trans(skb, bp->dev);
1338                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1339
1340                 {
1341                         struct iphdr *iph;
1342
1343                         iph = (struct iphdr *)skb->data;
1344 #ifdef BCM_VLAN
1345                         /* If there is no Rx VLAN offloading -
1346                            take VLAN tag into an account */
1347                         if (unlikely(is_not_hwaccel_vlan_cqe))
1348                                 iph = (struct iphdr *)((u8 *)iph + VLAN_HLEN);
1349 #endif
1350                         iph->check = 0;
1351                         iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1352                 }
1353
1354                 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1355                                          &cqe->fast_path_cqe, cqe_idx)) {
1356 #ifdef BCM_VLAN
1357                         if ((bp->vlgrp != NULL) && is_vlan_cqe &&
1358                             (!is_not_hwaccel_vlan_cqe))
1359                                 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1360                                                 le16_to_cpu(cqe->fast_path_cqe.
1361                                                             vlan_tag));
1362                         else
1363 #endif
1364                                 netif_receive_skb(skb);
1365                 } else {
1366                         DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1367                            " - dropping packet!\n");
1368                         dev_kfree_skb(skb);
1369                 }
1370
1371
1372                 /* put new skb in bin */
1373                 fp->tpa_pool[queue].skb = new_skb;
1374
1375         } else {
1376                 /* else drop the packet and keep the buffer in the bin */
1377                 DP(NETIF_MSG_RX_STATUS,
1378                    "Failed to allocate new skb - dropping packet!\n");
1379                 fp->eth_q_stats.rx_skb_alloc_failed++;
1380         }
1381
1382         fp->tpa_state[queue] = BNX2X_TPA_STOP;
1383 }
1384
1385 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1386                                         struct bnx2x_fastpath *fp,
1387                                         u16 bd_prod, u16 rx_comp_prod,
1388                                         u16 rx_sge_prod)
1389 {
1390         struct ustorm_eth_rx_producers rx_prods = {0};
1391         int i;
1392
1393         /* Update producers */
1394         rx_prods.bd_prod = bd_prod;
1395         rx_prods.cqe_prod = rx_comp_prod;
1396         rx_prods.sge_prod = rx_sge_prod;
1397
1398         /*
1399          * Make sure that the BD and SGE data is updated before updating the
1400          * producers since FW might read the BD/SGE right after the producer
1401          * is updated.
1402          * This is only applicable for weak-ordered memory model archs such
1403          * as IA-64. The following barrier is also mandatory since FW will
1404          * assumes BDs must have buffers.
1405          */
1406         wmb();
1407
1408         for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
1409                 REG_WR(bp, BAR_USTRORM_INTMEM +
1410                        USTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
1411                        ((u32 *)&rx_prods)[i]);
1412
1413         mmiowb(); /* keep prod updates ordered */
1414
1415         DP(NETIF_MSG_RX_STATUS,
1416            "queue[%d]:  wrote  bd_prod %u  cqe_prod %u  sge_prod %u\n",
1417            fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
1418 }
1419
1420 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1421 {
1422         struct bnx2x *bp = fp->bp;
1423         u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1424         u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1425         int rx_pkt = 0;
1426
1427 #ifdef BNX2X_STOP_ON_ERROR
1428         if (unlikely(bp->panic))
1429                 return 0;
1430 #endif
1431
1432         /* CQ "next element" is of the size of the regular element,
1433            that's why it's ok here */
1434         hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1435         if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1436                 hw_comp_cons++;
1437
1438         bd_cons = fp->rx_bd_cons;
1439         bd_prod = fp->rx_bd_prod;
1440         bd_prod_fw = bd_prod;
1441         sw_comp_cons = fp->rx_comp_cons;
1442         sw_comp_prod = fp->rx_comp_prod;
1443
1444         /* Memory barrier necessary as speculative reads of the rx
1445          * buffer can be ahead of the index in the status block
1446          */
1447         rmb();
1448
1449         DP(NETIF_MSG_RX_STATUS,
1450            "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
1451            FP_IDX(fp), hw_comp_cons, sw_comp_cons);
1452
1453         while (sw_comp_cons != hw_comp_cons) {
1454                 struct sw_rx_bd *rx_buf = NULL;
1455                 struct sk_buff *skb;
1456                 union eth_rx_cqe *cqe;
1457                 u8 cqe_fp_flags;
1458                 u16 len, pad;
1459
1460                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1461                 bd_prod = RX_BD(bd_prod);
1462                 bd_cons = RX_BD(bd_cons);
1463
1464                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1465                 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1466
1467                 DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
1468                    "  queue %x  vlan %x  len %u\n", CQE_TYPE(cqe_fp_flags),
1469                    cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1470                    le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
1471                    le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1472                    le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1473
1474                 /* is this a slowpath msg? */
1475                 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
1476                         bnx2x_sp_event(fp, cqe);
1477                         goto next_cqe;
1478
1479                 /* this is an rx packet */
1480                 } else {
1481                         rx_buf = &fp->rx_buf_ring[bd_cons];
1482                         skb = rx_buf->skb;
1483                         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1484                         pad = cqe->fast_path_cqe.placement_offset;
1485
1486                         /* If CQE is marked both TPA_START and TPA_END
1487                            it is a non-TPA CQE */
1488                         if ((!fp->disable_tpa) &&
1489                             (TPA_TYPE(cqe_fp_flags) !=
1490                                         (TPA_TYPE_START | TPA_TYPE_END))) {
1491                                 u16 queue = cqe->fast_path_cqe.queue_index;
1492
1493                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1494                                         DP(NETIF_MSG_RX_STATUS,
1495                                            "calling tpa_start on queue %d\n",
1496                                            queue);
1497
1498                                         bnx2x_tpa_start(fp, queue, skb,
1499                                                         bd_cons, bd_prod);
1500                                         goto next_rx;
1501                                 }
1502
1503                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1504                                         DP(NETIF_MSG_RX_STATUS,
1505                                            "calling tpa_stop on queue %d\n",
1506                                            queue);
1507
1508                                         if (!BNX2X_RX_SUM_FIX(cqe))
1509                                                 BNX2X_ERR("STOP on none TCP "
1510                                                           "data\n");
1511
1512                                         /* This is a size of the linear data
1513                                            on this skb */
1514                                         len = le16_to_cpu(cqe->fast_path_cqe.
1515                                                                 len_on_bd);
1516                                         bnx2x_tpa_stop(bp, fp, queue, pad,
1517                                                     len, cqe, comp_ring_cons);
1518 #ifdef BNX2X_STOP_ON_ERROR
1519                                         if (bp->panic)
1520                                                 return -EINVAL;
1521 #endif
1522
1523                                         bnx2x_update_sge_prod(fp,
1524                                                         &cqe->fast_path_cqe);
1525                                         goto next_cqe;
1526                                 }
1527                         }
1528
1529                         pci_dma_sync_single_for_device(bp->pdev,
1530                                         pci_unmap_addr(rx_buf, mapping),
1531                                                        pad + RX_COPY_THRESH,
1532                                                        PCI_DMA_FROMDEVICE);
1533                         prefetch(skb);
1534                         prefetch(((char *)(skb)) + 128);
1535
1536                         /* is this an error packet? */
1537                         if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1538                                 DP(NETIF_MSG_RX_ERR,
1539                                    "ERROR  flags %x  rx packet %u\n",
1540                                    cqe_fp_flags, sw_comp_cons);
1541                                 fp->eth_q_stats.rx_err_discard_pkt++;
1542                                 goto reuse_rx;
1543                         }
1544
1545                         /* Since we don't have a jumbo ring
1546                          * copy small packets if mtu > 1500
1547                          */
1548                         if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1549                             (len <= RX_COPY_THRESH)) {
1550                                 struct sk_buff *new_skb;
1551
1552                                 new_skb = netdev_alloc_skb(bp->dev,
1553                                                            len + pad);
1554                                 if (new_skb == NULL) {
1555                                         DP(NETIF_MSG_RX_ERR,
1556                                            "ERROR  packet dropped "
1557                                            "because of alloc failure\n");
1558                                         fp->eth_q_stats.rx_skb_alloc_failed++;
1559                                         goto reuse_rx;
1560                                 }
1561
1562                                 /* aligned copy */
1563                                 skb_copy_from_linear_data_offset(skb, pad,
1564                                                     new_skb->data + pad, len);
1565                                 skb_reserve(new_skb, pad);
1566                                 skb_put(new_skb, len);
1567
1568                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1569
1570                                 skb = new_skb;
1571
1572                         } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
1573                                 pci_unmap_single(bp->pdev,
1574                                         pci_unmap_addr(rx_buf, mapping),
1575                                                  bp->rx_buf_size,
1576                                                  PCI_DMA_FROMDEVICE);
1577                                 skb_reserve(skb, pad);
1578                                 skb_put(skb, len);
1579
1580                         } else {
1581                                 DP(NETIF_MSG_RX_ERR,
1582                                    "ERROR  packet dropped because "
1583                                    "of alloc failure\n");
1584                                 fp->eth_q_stats.rx_skb_alloc_failed++;
1585 reuse_rx:
1586                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1587                                 goto next_rx;
1588                         }
1589
1590                         skb->protocol = eth_type_trans(skb, bp->dev);
1591
1592                         skb->ip_summed = CHECKSUM_NONE;
1593                         if (bp->rx_csum) {
1594                                 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1595                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1596                                 else
1597                                         fp->eth_q_stats.hw_csum_err++;
1598                         }
1599                 }
1600
1601                 skb_record_rx_queue(skb, fp->index);
1602 #ifdef BCM_VLAN
1603                 if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) &&
1604                     (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1605                      PARSING_FLAGS_VLAN))
1606                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1607                                 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1608                 else
1609 #endif
1610                         netif_receive_skb(skb);
1611
1612
1613 next_rx:
1614                 rx_buf->skb = NULL;
1615
1616                 bd_cons = NEXT_RX_IDX(bd_cons);
1617                 bd_prod = NEXT_RX_IDX(bd_prod);
1618                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1619                 rx_pkt++;
1620 next_cqe:
1621                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1622                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1623
1624                 if (rx_pkt == budget)
1625                         break;
1626         } /* while */
1627
1628         fp->rx_bd_cons = bd_cons;
1629         fp->rx_bd_prod = bd_prod_fw;
1630         fp->rx_comp_cons = sw_comp_cons;
1631         fp->rx_comp_prod = sw_comp_prod;
1632
1633         /* Update producers */
1634         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1635                              fp->rx_sge_prod);
1636
1637         fp->rx_pkt += rx_pkt;
1638         fp->rx_calls++;
1639
1640         return rx_pkt;
1641 }
1642
1643 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1644 {
1645         struct bnx2x_fastpath *fp = fp_cookie;
1646         struct bnx2x *bp = fp->bp;
1647         int index = FP_IDX(fp);
1648
1649         /* Return here if interrupt is disabled */
1650         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1651                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1652                 return IRQ_HANDLED;
1653         }
1654
1655         DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1656            index, FP_SB_ID(fp));
1657         bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
1658
1659 #ifdef BNX2X_STOP_ON_ERROR
1660         if (unlikely(bp->panic))
1661                 return IRQ_HANDLED;
1662 #endif
1663
1664         prefetch(fp->rx_cons_sb);
1665         prefetch(fp->tx_cons_sb);
1666         prefetch(&fp->status_blk->c_status_block.status_block_index);
1667         prefetch(&fp->status_blk->u_status_block.status_block_index);
1668
1669         napi_schedule(&bnx2x_fp(bp, index, napi));
1670
1671         return IRQ_HANDLED;
1672 }
1673
1674 static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1675 {
1676         struct bnx2x *bp = netdev_priv(dev_instance);
1677         u16 status = bnx2x_ack_int(bp);
1678         u16 mask;
1679
1680         /* Return here if interrupt is shared and it's not for us */
1681         if (unlikely(status == 0)) {
1682                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1683                 return IRQ_NONE;
1684         }
1685         DP(NETIF_MSG_INTR, "got an interrupt  status %u\n", status);
1686
1687         /* Return here if interrupt is disabled */
1688         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1689                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1690                 return IRQ_HANDLED;
1691         }
1692
1693 #ifdef BNX2X_STOP_ON_ERROR
1694         if (unlikely(bp->panic))
1695                 return IRQ_HANDLED;
1696 #endif
1697
1698         mask = 0x2 << bp->fp[0].sb_id;
1699         if (status & mask) {
1700                 struct bnx2x_fastpath *fp = &bp->fp[0];
1701
1702                 prefetch(fp->rx_cons_sb);
1703                 prefetch(fp->tx_cons_sb);
1704                 prefetch(&fp->status_blk->c_status_block.status_block_index);
1705                 prefetch(&fp->status_blk->u_status_block.status_block_index);
1706
1707                 napi_schedule(&bnx2x_fp(bp, 0, napi));
1708
1709                 status &= ~mask;
1710         }
1711
1712
1713         if (unlikely(status & 0x1)) {
1714                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1715
1716                 status &= ~0x1;
1717                 if (!status)
1718                         return IRQ_HANDLED;
1719         }
1720
1721         if (status)
1722                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1723                    status);
1724
1725         return IRQ_HANDLED;
1726 }
1727
1728 /* end of fast path */
1729
1730 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1731
1732 /* Link */
1733
1734 /*
1735  * General service functions
1736  */
1737
1738 static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1739 {
1740         u32 lock_status;
1741         u32 resource_bit = (1 << resource);
1742         int func = BP_FUNC(bp);
1743         u32 hw_lock_control_reg;
1744         int cnt;
1745
1746         /* Validating that the resource is within range */
1747         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1748                 DP(NETIF_MSG_HW,
1749                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1750                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1751                 return -EINVAL;
1752         }
1753
1754         if (func <= 5) {
1755                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1756         } else {
1757                 hw_lock_control_reg =
1758                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1759         }
1760
1761         /* Validating that the resource is not already taken */
1762         lock_status = REG_RD(bp, hw_lock_control_reg);
1763         if (lock_status & resource_bit) {
1764                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1765                    lock_status, resource_bit);
1766                 return -EEXIST;
1767         }
1768
1769         /* Try for 5 second every 5ms */
1770         for (cnt = 0; cnt < 1000; cnt++) {
1771                 /* Try to acquire the lock */
1772                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1773                 lock_status = REG_RD(bp, hw_lock_control_reg);
1774                 if (lock_status & resource_bit)
1775                         return 0;
1776
1777                 msleep(5);
1778         }
1779         DP(NETIF_MSG_HW, "Timeout\n");
1780         return -EAGAIN;
1781 }
1782
1783 static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1784 {
1785         u32 lock_status;
1786         u32 resource_bit = (1 << resource);
1787         int func = BP_FUNC(bp);
1788         u32 hw_lock_control_reg;
1789
1790         /* Validating that the resource is within range */
1791         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1792                 DP(NETIF_MSG_HW,
1793                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1794                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1795                 return -EINVAL;
1796         }
1797
1798         if (func <= 5) {
1799                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1800         } else {
1801                 hw_lock_control_reg =
1802                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1803         }
1804
1805         /* Validating that the resource is currently taken */
1806         lock_status = REG_RD(bp, hw_lock_control_reg);
1807         if (!(lock_status & resource_bit)) {
1808                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1809                    lock_status, resource_bit);
1810                 return -EFAULT;
1811         }
1812
1813         REG_WR(bp, hw_lock_control_reg, resource_bit);
1814         return 0;
1815 }
1816
1817 /* HW Lock for shared dual port PHYs */
1818 static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1819 {
1820         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1821
1822         mutex_lock(&bp->port.phy_mutex);
1823
1824         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1825             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1826                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1827 }
1828
1829 static void bnx2x_release_phy_lock(struct bnx2x *bp)
1830 {
1831         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1832
1833         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1834             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1835                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1836
1837         mutex_unlock(&bp->port.phy_mutex);
1838 }
1839
1840 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1841 {
1842         /* The GPIO should be swapped if swap register is set and active */
1843         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1844                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1845         int gpio_shift = gpio_num +
1846                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1847         u32 gpio_mask = (1 << gpio_shift);
1848         u32 gpio_reg;
1849
1850         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1851                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1852                 return -EINVAL;
1853         }
1854
1855         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1856         /* read GPIO and mask except the float bits */
1857         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1858
1859         switch (mode) {
1860         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1861                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1862                    gpio_num, gpio_shift);
1863                 /* clear FLOAT and set CLR */
1864                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1865                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1866                 break;
1867
1868         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1869                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1870                    gpio_num, gpio_shift);
1871                 /* clear FLOAT and set SET */
1872                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1873                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1874                 break;
1875
1876         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1877                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1878                    gpio_num, gpio_shift);
1879                 /* set FLOAT */
1880                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1881                 break;
1882
1883         default:
1884                 break;
1885         }
1886
1887         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1888         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1889
1890         return 0;
1891 }
1892
1893 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1894 {
1895         u32 spio_mask = (1 << spio_num);
1896         u32 spio_reg;
1897
1898         if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1899             (spio_num > MISC_REGISTERS_SPIO_7)) {
1900                 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1901                 return -EINVAL;
1902         }
1903
1904         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1905         /* read SPIO and mask except the float bits */
1906         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1907
1908         switch (mode) {
1909         case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1910                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1911                 /* clear FLOAT and set CLR */
1912                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1913                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1914                 break;
1915
1916         case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1917                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1918                 /* clear FLOAT and set SET */
1919                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1920                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1921                 break;
1922
1923         case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1924                 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1925                 /* set FLOAT */
1926                 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1927                 break;
1928
1929         default:
1930                 break;
1931         }
1932
1933         REG_WR(bp, MISC_REG_SPIO, spio_reg);
1934         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1935
1936         return 0;
1937 }
1938
1939 static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1940 {
1941         switch (bp->link_vars.ieee_fc &
1942                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1943         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1944                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1945                                           ADVERTISED_Pause);
1946                 break;
1947         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1948                 bp->port.advertising |= (ADVERTISED_Asym_Pause |
1949                                          ADVERTISED_Pause);
1950                 break;
1951         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1952                 bp->port.advertising |= ADVERTISED_Asym_Pause;
1953                 break;
1954         default:
1955                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1956                                           ADVERTISED_Pause);
1957                 break;
1958         }
1959 }
1960
1961 static void bnx2x_link_report(struct bnx2x *bp)
1962 {
1963         if (bp->link_vars.link_up) {
1964                 if (bp->state == BNX2X_STATE_OPEN)
1965                         netif_carrier_on(bp->dev);
1966                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
1967
1968                 printk("%d Mbps ", bp->link_vars.line_speed);
1969
1970                 if (bp->link_vars.duplex == DUPLEX_FULL)
1971                         printk("full duplex");
1972                 else
1973                         printk("half duplex");
1974
1975                 if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
1976                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
1977                                 printk(", receive ");
1978                                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1979                                         printk("& transmit ");
1980                         } else {
1981                                 printk(", transmit ");
1982                         }
1983                         printk("flow control ON");
1984                 }
1985                 printk("\n");
1986
1987         } else { /* link_down */
1988                 netif_carrier_off(bp->dev);
1989                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
1990         }
1991 }
1992
1993 static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1994 {
1995         if (!BP_NOMCP(bp)) {
1996                 u8 rc;
1997
1998                 /* Initialize link parameters structure variables */
1999                 /* It is recommended to turn off RX FC for jumbo frames
2000                    for better performance */
2001                 if (IS_E1HMF(bp))
2002                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2003                 else if (bp->dev->mtu > 5000)
2004                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2005                 else
2006                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2007
2008                 bnx2x_acquire_phy_lock(bp);
2009                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2010                 bnx2x_release_phy_lock(bp);
2011
2012                 bnx2x_calc_fc_adv(bp);
2013
2014                 if (bp->link_vars.link_up)
2015                         bnx2x_link_report(bp);
2016
2017
2018                 return rc;
2019         }
2020         BNX2X_ERR("Bootcode is missing -not initializing link\n");
2021         return -EINVAL;
2022 }
2023
2024 static void bnx2x_link_set(struct bnx2x *bp)
2025 {
2026         if (!BP_NOMCP(bp)) {
2027                 bnx2x_acquire_phy_lock(bp);
2028                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2029                 bnx2x_release_phy_lock(bp);
2030
2031                 bnx2x_calc_fc_adv(bp);
2032         } else
2033                 BNX2X_ERR("Bootcode is missing -not setting link\n");
2034 }
2035
2036 static void bnx2x__link_reset(struct bnx2x *bp)
2037 {
2038         if (!BP_NOMCP(bp)) {
2039                 bnx2x_acquire_phy_lock(bp);
2040                 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
2041                 bnx2x_release_phy_lock(bp);
2042         } else
2043                 BNX2X_ERR("Bootcode is missing -not resetting link\n");
2044 }
2045
2046 static u8 bnx2x_link_test(struct bnx2x *bp)
2047 {
2048         u8 rc;
2049
2050         bnx2x_acquire_phy_lock(bp);
2051         rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
2052         bnx2x_release_phy_lock(bp);
2053
2054         return rc;
2055 }
2056
2057 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2058 {
2059         u32 r_param = bp->link_vars.line_speed / 8;
2060         u32 fair_periodic_timeout_usec;
2061         u32 t_fair;
2062
2063         memset(&(bp->cmng.rs_vars), 0,
2064                sizeof(struct rate_shaping_vars_per_port));
2065         memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2066
2067         /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2068         bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2069
2070         /* this is the threshold below which no timer arming will occur
2071            1.25 coefficient is for the threshold to be a little bigger
2072            than the real time, to compensate for timer in-accuracy */
2073         bp->cmng.rs_vars.rs_threshold =
2074                                 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2075
2076         /* resolution of fairness timer */
2077         fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2078         /* for 10G it is 1000usec. for 1G it is 10000usec. */
2079         t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2080
2081         /* this is the threshold below which we won't arm the timer anymore */
2082         bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2083
2084         /* we multiply by 1e3/8 to get bytes/msec.
2085            We don't want the credits to pass a credit
2086            of the t_fair*FAIR_MEM (algorithm resolution) */
2087         bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2088         /* since each tick is 4 usec */
2089         bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2090 }
2091
2092 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
2093 {
2094         struct rate_shaping_vars_per_vn m_rs_vn;
2095         struct fairness_vars_per_vn m_fair_vn;
2096         u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2097         u16 vn_min_rate, vn_max_rate;
2098         int i;
2099
2100         /* If function is hidden - set min and max to zeroes */
2101         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2102                 vn_min_rate = 0;
2103                 vn_max_rate = 0;
2104
2105         } else {
2106                 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2107                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2108                 /* If fairness is enabled (not all min rates are zeroes) and
2109                    if current min rate is zero - set it to 1.
2110                    This is a requirement of the algorithm. */
2111                 if (bp->vn_weight_sum && (vn_min_rate == 0))
2112                         vn_min_rate = DEF_MIN_RATE;
2113                 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2114                                 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2115         }
2116
2117         DP(NETIF_MSG_IFUP,
2118            "func %d: vn_min_rate=%d  vn_max_rate=%d  vn_weight_sum=%d\n",
2119            func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2120
2121         memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2122         memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2123
2124         /* global vn counter - maximal Mbps for this vn */
2125         m_rs_vn.vn_counter.rate = vn_max_rate;
2126
2127         /* quota - number of bytes transmitted in this period */
2128         m_rs_vn.vn_counter.quota =
2129                                 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2130
2131         if (bp->vn_weight_sum) {
2132                 /* credit for each period of the fairness algorithm:
2133                    number of bytes in T_FAIR (the vn share the port rate).
2134                    vn_weight_sum should not be larger than 10000, thus
2135                    T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2136                    than zero */
2137                 m_fair_vn.vn_credit_delta =
2138                         max((u32)(vn_min_rate * (T_FAIR_COEF /
2139                                                  (8 * bp->vn_weight_sum))),
2140                             (u32)(bp->cmng.fair_vars.fair_threshold * 2));
2141                 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2142                    m_fair_vn.vn_credit_delta);
2143         }
2144
2145         /* Store it to internal memory */
2146         for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2147                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2148                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2149                        ((u32 *)(&m_rs_vn))[i]);
2150
2151         for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2152                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2153                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2154                        ((u32 *)(&m_fair_vn))[i]);
2155 }
2156
2157
2158 /* This function is called upon link interrupt */
2159 static void bnx2x_link_attn(struct bnx2x *bp)
2160 {
2161         /* Make sure that we are synced with the current statistics */
2162         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2163
2164         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2165
2166         if (bp->link_vars.link_up) {
2167
2168                 /* dropless flow control */
2169                 if (CHIP_IS_E1H(bp)) {
2170                         int port = BP_PORT(bp);
2171                         u32 pause_enabled = 0;
2172
2173                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2174                                 pause_enabled = 1;
2175
2176                         REG_WR(bp, BAR_USTRORM_INTMEM +
2177                                USTORM_PAUSE_ENABLED_OFFSET(port),
2178                                pause_enabled);
2179                 }
2180
2181                 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2182                         struct host_port_stats *pstats;
2183
2184                         pstats = bnx2x_sp(bp, port_stats);
2185                         /* reset old bmac stats */
2186                         memset(&(pstats->mac_stx[0]), 0,
2187                                sizeof(struct mac_stx));
2188                 }
2189                 if ((bp->state == BNX2X_STATE_OPEN) ||
2190                     (bp->state == BNX2X_STATE_DISABLED))
2191                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2192         }
2193
2194         /* indicate link status */
2195         bnx2x_link_report(bp);
2196
2197         if (IS_E1HMF(bp)) {
2198                 int port = BP_PORT(bp);
2199                 int func;
2200                 int vn;
2201
2202                 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2203                         if (vn == BP_E1HVN(bp))
2204                                 continue;
2205
2206                         func = ((vn << 1) | port);
2207
2208                         /* Set the attention towards other drivers
2209                            on the same port */
2210                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2211                                (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2212                 }
2213
2214                 if (bp->link_vars.link_up) {
2215                         int i;
2216
2217                         /* Init rate shaping and fairness contexts */
2218                         bnx2x_init_port_minmax(bp);
2219
2220                         for (vn = VN_0; vn < E1HVN_MAX; vn++)
2221                                 bnx2x_init_vn_minmax(bp, 2*vn + port);
2222
2223                         /* Store it to internal memory */
2224                         for (i = 0;
2225                              i < sizeof(struct cmng_struct_per_port) / 4; i++)
2226                                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2227                                   XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
2228                                        ((u32 *)(&bp->cmng))[i]);
2229                 }
2230         }
2231 }
2232
2233 static void bnx2x__link_status_update(struct bnx2x *bp)
2234 {
2235         if (bp->state != BNX2X_STATE_OPEN)
2236                 return;
2237
2238         bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2239
2240         if (bp->link_vars.link_up)
2241                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2242         else
2243                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2244
2245         /* indicate link status */
2246         bnx2x_link_report(bp);
2247 }
2248
2249 static void bnx2x_pmf_update(struct bnx2x *bp)
2250 {
2251         int port = BP_PORT(bp);
2252         u32 val;
2253
2254         bp->port.pmf = 1;
2255         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2256
2257         /* enable nig attention */
2258         val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2259         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2260         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2261
2262         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2263 }
2264
2265 /* end of Link */
2266
2267 /* slow path */
2268
2269 /*
2270  * General service functions
2271  */
2272
2273 /* the slow path queue is odd since completions arrive on the fastpath ring */
2274 static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2275                          u32 data_hi, u32 data_lo, int common)
2276 {
2277         int func = BP_FUNC(bp);
2278
2279         DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2280            "SPQE (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
2281            (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2282            (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2283            HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2284
2285 #ifdef BNX2X_STOP_ON_ERROR
2286         if (unlikely(bp->panic))
2287                 return -EIO;
2288 #endif
2289
2290         spin_lock_bh(&bp->spq_lock);
2291
2292         if (!bp->spq_left) {
2293                 BNX2X_ERR("BUG! SPQ ring full!\n");
2294                 spin_unlock_bh(&bp->spq_lock);
2295                 bnx2x_panic();
2296                 return -EBUSY;
2297         }
2298
2299         /* CID needs port number to be encoded int it */
2300         bp->spq_prod_bd->hdr.conn_and_cmd_data =
2301                         cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2302                                      HW_CID(bp, cid)));
2303         bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
2304         if (common)
2305                 bp->spq_prod_bd->hdr.type |=
2306                         cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2307
2308         bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2309         bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
2310
2311         bp->spq_left--;
2312
2313         if (bp->spq_prod_bd == bp->spq_last_bd) {
2314                 bp->spq_prod_bd = bp->spq;
2315                 bp->spq_prod_idx = 0;
2316                 DP(NETIF_MSG_TIMER, "end of spq\n");
2317
2318         } else {
2319                 bp->spq_prod_bd++;
2320                 bp->spq_prod_idx++;
2321         }
2322
2323         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2324                bp->spq_prod_idx);
2325
2326         spin_unlock_bh(&bp->spq_lock);
2327         return 0;
2328 }
2329
2330 /* acquire split MCP access lock register */
2331 static int bnx2x_acquire_alr(struct bnx2x *bp)
2332 {
2333         u32 i, j, val;
2334         int rc = 0;
2335
2336         might_sleep();
2337         i = 100;
2338         for (j = 0; j < i*10; j++) {
2339                 val = (1UL << 31);
2340                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2341                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2342                 if (val & (1L << 31))
2343                         break;
2344
2345                 msleep(5);
2346         }
2347         if (!(val & (1L << 31))) {
2348                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2349                 rc = -EBUSY;
2350         }
2351
2352         return rc;
2353 }
2354
2355 /* release split MCP access lock register */
2356 static void bnx2x_release_alr(struct bnx2x *bp)
2357 {
2358         u32 val = 0;
2359
2360         REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2361 }
2362
2363 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2364 {
2365         struct host_def_status_block *def_sb = bp->def_status_blk;
2366         u16 rc = 0;
2367
2368         barrier(); /* status block is written to by the chip */
2369         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2370                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2371                 rc |= 1;
2372         }
2373         if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2374                 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2375                 rc |= 2;
2376         }
2377         if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2378                 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2379                 rc |= 4;
2380         }
2381         if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2382                 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2383                 rc |= 8;
2384         }
2385         if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2386                 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2387                 rc |= 16;
2388         }
2389         return rc;
2390 }
2391
2392 /*
2393  * slow path service functions
2394  */
2395
2396 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2397 {
2398         int port = BP_PORT(bp);
2399         u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2400                        COMMAND_REG_ATTN_BITS_SET);
2401         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2402                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
2403         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2404                                        NIG_REG_MASK_INTERRUPT_PORT0;
2405         u32 aeu_mask;
2406
2407         if (bp->attn_state & asserted)
2408                 BNX2X_ERR("IGU ERROR\n");
2409
2410         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2411         aeu_mask = REG_RD(bp, aeu_addr);
2412
2413         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
2414            aeu_mask, asserted);
2415         aeu_mask &= ~(asserted & 0xff);
2416         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2417
2418         REG_WR(bp, aeu_addr, aeu_mask);
2419         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2420
2421         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2422         bp->attn_state |= asserted;
2423         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2424
2425         if (asserted & ATTN_HARD_WIRED_MASK) {
2426                 if (asserted & ATTN_NIG_FOR_FUNC) {
2427
2428                         bnx2x_acquire_phy_lock(bp);
2429
2430                         /* save nig interrupt mask */
2431                         bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
2432                         REG_WR(bp, nig_int_mask_addr, 0);
2433
2434                         bnx2x_link_attn(bp);
2435
2436                         /* handle unicore attn? */
2437                 }
2438                 if (asserted & ATTN_SW_TIMER_4_FUNC)
2439                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2440
2441                 if (asserted & GPIO_2_FUNC)
2442                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2443
2444                 if (asserted & GPIO_3_FUNC)
2445                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2446
2447                 if (asserted & GPIO_4_FUNC)
2448                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2449
2450                 if (port == 0) {
2451                         if (asserted & ATTN_GENERAL_ATTN_1) {
2452                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2453                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2454                         }
2455                         if (asserted & ATTN_GENERAL_ATTN_2) {
2456                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2457                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2458                         }
2459                         if (asserted & ATTN_GENERAL_ATTN_3) {
2460                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2461                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2462                         }
2463                 } else {
2464                         if (asserted & ATTN_GENERAL_ATTN_4) {
2465                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2466                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2467                         }
2468                         if (asserted & ATTN_GENERAL_ATTN_5) {
2469                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2470                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2471                         }
2472                         if (asserted & ATTN_GENERAL_ATTN_6) {
2473                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2474                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2475                         }
2476                 }
2477
2478         } /* if hardwired */
2479
2480         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2481            asserted, hc_addr);
2482         REG_WR(bp, hc_addr, asserted);
2483
2484         /* now set back the mask */
2485         if (asserted & ATTN_NIG_FOR_FUNC) {
2486                 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
2487                 bnx2x_release_phy_lock(bp);
2488         }
2489 }
2490
2491 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2492 {
2493         int port = BP_PORT(bp);
2494         int reg_offset;
2495         u32 val;
2496
2497         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2498                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2499
2500         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2501
2502                 val = REG_RD(bp, reg_offset);
2503                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2504                 REG_WR(bp, reg_offset, val);
2505
2506                 BNX2X_ERR("SPIO5 hw attention\n");
2507
2508                 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
2509                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
2510                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2511                         /* Fan failure attention */
2512
2513                         /* The PHY reset is controlled by GPIO 1 */
2514                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2515                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2516                         /* Low power mode is controlled by GPIO 2 */
2517                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2518                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2519                         /* mark the failure */
2520                         bp->link_params.ext_phy_config &=
2521                                         ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2522                         bp->link_params.ext_phy_config |=
2523                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2524                         SHMEM_WR(bp,
2525                                  dev_info.port_hw_config[port].
2526                                                         external_phy_config,
2527                                  bp->link_params.ext_phy_config);
2528                         /* log the failure */
2529                         printk(KERN_ERR PFX "Fan Failure on Network"
2530                                " Controller %s has caused the driver to"
2531                                " shutdown the card to prevent permanent"
2532                                " damage.  Please contact Dell Support for"
2533                                " assistance\n", bp->dev->name);
2534                         break;
2535
2536                 default:
2537                         break;
2538                 }
2539         }
2540
2541         if (attn & HW_INTERRUT_ASSERT_SET_0) {
2542
2543                 val = REG_RD(bp, reg_offset);
2544                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2545                 REG_WR(bp, reg_offset, val);
2546
2547                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2548                           (attn & HW_INTERRUT_ASSERT_SET_0));
2549                 bnx2x_panic();
2550         }
2551 }
2552
2553 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2554 {
2555         u32 val;
2556
2557         if (attn & BNX2X_DOORQ_ASSERT) {
2558
2559                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2560                 BNX2X_ERR("DB hw attention 0x%x\n", val);
2561                 /* DORQ discard attention */
2562                 if (val & 0x2)
2563                         BNX2X_ERR("FATAL error from DORQ\n");
2564         }
2565
2566         if (attn & HW_INTERRUT_ASSERT_SET_1) {
2567
2568                 int port = BP_PORT(bp);
2569                 int reg_offset;
2570
2571                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2572                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2573
2574                 val = REG_RD(bp, reg_offset);
2575                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2576                 REG_WR(bp, reg_offset, val);
2577
2578                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2579                           (attn & HW_INTERRUT_ASSERT_SET_1));
2580                 bnx2x_panic();
2581         }
2582 }
2583
2584 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2585 {
2586         u32 val;
2587
2588         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
2589
2590                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
2591                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
2592                 /* CFC error attention */
2593                 if (val & 0x2)
2594                         BNX2X_ERR("FATAL error from CFC\n");
2595         }
2596
2597         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
2598
2599                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
2600                 BNX2X_ERR("PXP hw attention 0x%x\n", val);
2601                 /* RQ_USDMDP_FIFO_OVERFLOW */
2602                 if (val & 0x18000)
2603                         BNX2X_ERR("FATAL error from PXP\n");
2604         }
2605
2606         if (attn & HW_INTERRUT_ASSERT_SET_2) {
2607
2608                 int port = BP_PORT(bp);
2609                 int reg_offset;
2610
2611                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
2612                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
2613
2614                 val = REG_RD(bp, reg_offset);
2615                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
2616                 REG_WR(bp, reg_offset, val);
2617
2618                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2619                           (attn & HW_INTERRUT_ASSERT_SET_2));
2620                 bnx2x_panic();
2621         }
2622 }
2623
2624 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2625 {
2626         u32 val;
2627
2628         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
2629
2630                 if (attn & BNX2X_PMF_LINK_ASSERT) {
2631                         int func = BP_FUNC(bp);
2632
2633                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2634                         bnx2x__link_status_update(bp);
2635                         if (SHMEM_RD(bp, func_mb[func].drv_status) &
2636                                                         DRV_STATUS_PMF)
2637                                 bnx2x_pmf_update(bp);
2638
2639                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2640
2641                         BNX2X_ERR("MC assert!\n");
2642                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
2643                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
2644                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
2645                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
2646                         bnx2x_panic();
2647
2648                 } else if (attn & BNX2X_MCP_ASSERT) {
2649
2650                         BNX2X_ERR("MCP assert!\n");
2651                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
2652                         bnx2x_fw_dump(bp);
2653
2654                 } else
2655                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
2656         }
2657
2658         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2659                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2660                 if (attn & BNX2X_GRC_TIMEOUT) {
2661                         val = CHIP_IS_E1H(bp) ?
2662                                 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
2663                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
2664                 }
2665                 if (attn & BNX2X_GRC_RSV) {
2666                         val = CHIP_IS_E1H(bp) ?
2667                                 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
2668                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
2669                 }
2670                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
2671         }
2672 }
2673
2674 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2675 {
2676         struct attn_route attn;
2677         struct attn_route group_mask;
2678         int port = BP_PORT(bp);
2679         int index;
2680         u32 reg_addr;
2681         u32 val;
2682         u32 aeu_mask;
2683
2684         /* need to take HW lock because MCP or other port might also
2685            try to handle this event */
2686         bnx2x_acquire_alr(bp);
2687
2688         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2689         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2690         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2691         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2692         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
2693            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
2694
2695         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2696                 if (deasserted & (1 << index)) {
2697                         group_mask = bp->attn_group[index];
2698
2699                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
2700                            index, group_mask.sig[0], group_mask.sig[1],
2701                            group_mask.sig[2], group_mask.sig[3]);
2702
2703                         bnx2x_attn_int_deasserted3(bp,
2704                                         attn.sig[3] & group_mask.sig[3]);
2705                         bnx2x_attn_int_deasserted1(bp,
2706                                         attn.sig[1] & group_mask.sig[1]);
2707                         bnx2x_attn_int_deasserted2(bp,
2708                                         attn.sig[2] & group_mask.sig[2]);
2709                         bnx2x_attn_int_deasserted0(bp,
2710                                         attn.sig[0] & group_mask.sig[0]);
2711
2712                         if ((attn.sig[0] & group_mask.sig[0] &
2713                                                 HW_PRTY_ASSERT_SET_0) ||
2714                             (attn.sig[1] & group_mask.sig[1] &
2715                                                 HW_PRTY_ASSERT_SET_1) ||
2716                             (attn.sig[2] & group_mask.sig[2] &
2717                                                 HW_PRTY_ASSERT_SET_2))
2718                                 BNX2X_ERR("FATAL HW block parity attention\n");
2719                 }
2720         }
2721
2722         bnx2x_release_alr(bp);
2723
2724         reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2725
2726         val = ~deasserted;
2727         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2728            val, reg_addr);
2729         REG_WR(bp, reg_addr, val);
2730
2731         if (~bp->attn_state & deasserted)
2732                 BNX2X_ERR("IGU ERROR\n");
2733
2734         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2735                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
2736
2737         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2738         aeu_mask = REG_RD(bp, reg_addr);
2739
2740         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
2741            aeu_mask, deasserted);
2742         aeu_mask |= (deasserted & 0xff);
2743         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2744
2745         REG_WR(bp, reg_addr, aeu_mask);
2746         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2747
2748         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2749         bp->attn_state &= ~deasserted;
2750         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2751 }
2752
2753 static void bnx2x_attn_int(struct bnx2x *bp)
2754 {
2755         /* read local copy of bits */
2756         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
2757                                                                 attn_bits);
2758         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
2759                                                                 attn_bits_ack);
2760         u32 attn_state = bp->attn_state;
2761
2762         /* look for changed bits */
2763         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
2764         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
2765
2766         DP(NETIF_MSG_HW,
2767            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
2768            attn_bits, attn_ack, asserted, deasserted);
2769
2770         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
2771                 BNX2X_ERR("BAD attention state\n");
2772
2773         /* handle bits that were raised */
2774         if (asserted)
2775                 bnx2x_attn_int_asserted(bp, asserted);
2776
2777         if (deasserted)
2778                 bnx2x_attn_int_deasserted(bp, deasserted);
2779 }
2780
2781 static void bnx2x_sp_task(struct work_struct *work)
2782 {
2783         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
2784         u16 status;
2785
2786
2787         /* Return here if interrupt is disabled */
2788         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2789                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2790                 return;
2791         }
2792
2793         status = bnx2x_update_dsb_idx(bp);
2794 /*      if (status == 0)                                     */
2795 /*              BNX2X_ERR("spurious slowpath interrupt!\n"); */
2796
2797         DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
2798
2799         /* HW attentions */
2800         if (status & 0x1)
2801                 bnx2x_attn_int(bp);
2802
2803         bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
2804                      IGU_INT_NOP, 1);
2805         bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2806                      IGU_INT_NOP, 1);
2807         bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2808                      IGU_INT_NOP, 1);
2809         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2810                      IGU_INT_NOP, 1);
2811         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2812                      IGU_INT_ENABLE, 1);
2813
2814 }
2815
2816 static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2817 {
2818         struct net_device *dev = dev_instance;
2819         struct bnx2x *bp = netdev_priv(dev);
2820
2821         /* Return here if interrupt is disabled */
2822         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2823                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2824                 return IRQ_HANDLED;
2825         }
2826
2827         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
2828
2829 #ifdef BNX2X_STOP_ON_ERROR
2830         if (unlikely(bp->panic))
2831                 return IRQ_HANDLED;
2832 #endif
2833
2834         queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
2835
2836         return IRQ_HANDLED;
2837 }
2838
2839 /* end of slow path */
2840
2841 /* Statistics */
2842
2843 /****************************************************************************
2844 * Macros
2845 ****************************************************************************/
2846
2847 /* sum[hi:lo] += add[hi:lo] */
2848 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2849         do { \
2850                 s_lo += a_lo; \
2851                 s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
2852         } while (0)
2853
2854 /* difference = minuend - subtrahend */
2855 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2856         do { \
2857                 if (m_lo < s_lo) { \
2858                         /* underflow */ \
2859                         d_hi = m_hi - s_hi; \
2860                         if (d_hi > 0) { \
2861                                 /* we can 'loan' 1 */ \
2862                                 d_hi--; \
2863                                 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2864                         } else { \
2865                                 /* m_hi <= s_hi */ \
2866                                 d_hi = 0; \
2867                                 d_lo = 0; \
2868                         } \
2869                 } else { \
2870                         /* m_lo >= s_lo */ \
2871                         if (m_hi < s_hi) { \
2872                                 d_hi = 0; \
2873                                 d_lo = 0; \
2874                         } else { \
2875                                 /* m_hi >= s_hi */ \
2876                                 d_hi = m_hi - s_hi; \
2877                                 d_lo = m_lo - s_lo; \
2878                         } \
2879                 } \
2880         } while (0)
2881
2882 #define UPDATE_STAT64(s, t) \
2883         do { \
2884                 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
2885                         diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
2886                 pstats->mac_stx[0].t##_hi = new->s##_hi; \
2887                 pstats->mac_stx[0].t##_lo = new->s##_lo; \
2888                 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
2889                        pstats->mac_stx[1].t##_lo, diff.lo); \
2890         } while (0)
2891
2892 #define UPDATE_STAT64_NIG(s, t) \
2893         do { \
2894                 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
2895                         diff.lo, new->s##_lo, old->s##_lo); \
2896                 ADD_64(estats->t##_hi, diff.hi, \
2897                        estats->t##_lo, diff.lo); \
2898         } while (0)
2899
2900 /* sum[hi:lo] += add */
2901 #define ADD_EXTEND_64(s_hi, s_lo, a) \
2902         do { \
2903                 s_lo += a; \
2904                 s_hi += (s_lo < a) ? 1 : 0; \
2905         } while (0)
2906
2907 #define UPDATE_EXTEND_STAT(s) \
2908         do { \
2909                 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
2910                               pstats->mac_stx[1].s##_lo, \
2911                               new->s); \
2912         } while (0)
2913
2914 #define UPDATE_EXTEND_TSTAT(s, t) \
2915         do { \
2916                 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
2917                 old_tclient->s = le32_to_cpu(tclient->s); \
2918                 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
2919         } while (0)
2920
2921 #define UPDATE_EXTEND_USTAT(s, t) \
2922         do { \
2923                 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
2924                 old_uclient->s = uclient->s; \
2925                 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
2926         } while (0)
2927
2928 #define UPDATE_EXTEND_XSTAT(s, t) \
2929         do { \
2930                 diff = le32_to_cpu(xclient->s) - old_xclient->s; \
2931                 old_xclient->s = le32_to_cpu(xclient->s); \
2932                 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
2933         } while (0)
2934
2935 /* minuend -= subtrahend */
2936 #define SUB_64(m_hi, s_hi, m_lo, s_lo) \
2937         do { \
2938                 DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
2939         } while (0)
2940
2941 /* minuend[hi:lo] -= subtrahend */
2942 #define SUB_EXTEND_64(m_hi, m_lo, s) \
2943         do { \
2944                 SUB_64(m_hi, 0, m_lo, s); \
2945         } while (0)
2946
2947 #define SUB_EXTEND_USTAT(s, t) \
2948         do { \
2949                 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
2950                 SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
2951         } while (0)
2952
2953 /*
2954  * General service functions
2955  */
2956
2957 static inline long bnx2x_hilo(u32 *hiref)
2958 {
2959         u32 lo = *(hiref + 1);
2960 #if (BITS_PER_LONG == 64)
2961         u32 hi = *hiref;
2962
2963         return HILO_U64(hi, lo);
2964 #else
2965         return lo;
2966 #endif
2967 }
2968
2969 /*
2970  * Init service functions
2971  */
2972
2973 static void bnx2x_storm_stats_post(struct bnx2x *bp)
2974 {
2975         if (!bp->stats_pending) {
2976                 struct eth_query_ramrod_data ramrod_data = {0};
2977                 int i, rc;
2978
2979                 ramrod_data.drv_counter = bp->stats_counter++;
2980                 ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
2981                 for_each_queue(bp, i)
2982                         ramrod_data.ctr_id_vector |= (1 << bp->fp[i].cl_id);
2983
2984                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
2985                                    ((u32 *)&ramrod_data)[1],
2986                                    ((u32 *)&ramrod_data)[0], 0);
2987                 if (rc == 0) {
2988                         /* stats ramrod has it's own slot on the spq */
2989                         bp->spq_left++;
2990                         bp->stats_pending = 1;
2991                 }
2992         }
2993 }
2994
2995 static void bnx2x_stats_init(struct bnx2x *bp)
2996 {
2997         int port = BP_PORT(bp);
2998         int i;
2999
3000         bp->stats_pending = 0;
3001         bp->executer_idx = 0;
3002         bp->stats_counter = 0;
3003
3004         /* port stats */
3005         if (!BP_NOMCP(bp))
3006                 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
3007         else
3008                 bp->port.port_stx = 0;
3009         DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
3010
3011         memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3012         bp->port.old_nig_stats.brb_discard =
3013                         REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3014         bp->port.old_nig_stats.brb_truncate =
3015                         REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3016         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3017                     &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3018         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
3019                     &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
3020
3021         /* function stats */
3022         for_each_queue(bp, i) {
3023                 struct bnx2x_fastpath *fp = &bp->fp[i];
3024
3025                 memset(&fp->old_tclient, 0,
3026                        sizeof(struct tstorm_per_client_stats));
3027                 memset(&fp->old_uclient, 0,
3028                        sizeof(struct ustorm_per_client_stats));
3029                 memset(&fp->old_xclient, 0,
3030                        sizeof(struct xstorm_per_client_stats));
3031                 memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
3032         }
3033
3034         memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3035         memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
3036
3037         bp->stats_state = STATS_STATE_DISABLED;
3038         if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
3039                 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3040 }
3041
3042 static void bnx2x_hw_stats_post(struct bnx2x *bp)
3043 {
3044         struct dmae_command *dmae = &bp->stats_dmae;
3045         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3046
3047         *stats_comp = DMAE_COMP_VAL;
3048         if (CHIP_REV_IS_SLOW(bp))
3049                 return;
3050
3051         /* loader */
3052         if (bp->executer_idx) {
3053                 int loader_idx = PMF_DMAE_C(bp);
3054
3055                 memset(dmae, 0, sizeof(struct dmae_command));
3056
3057                 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3058                                 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3059                                 DMAE_CMD_DST_RESET |
3060 #ifdef __BIG_ENDIAN
3061                                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3062 #else
3063                                 DMAE_CMD_ENDIANITY_DW_SWAP |
3064 #endif
3065                                 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3066                                                DMAE_CMD_PORT_0) |
3067                                 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3068                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3069                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3070                 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3071                                      sizeof(struct dmae_command) *
3072                                      (loader_idx + 1)) >> 2;
3073                 dmae->dst_addr_hi = 0;
3074                 dmae->len = sizeof(struct dmae_command) >> 2;
3075                 if (CHIP_IS_E1(bp))
3076                         dmae->len--;
3077                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3078                 dmae->comp_addr_hi = 0;
3079                 dmae->comp_val = 1;
3080
3081                 *stats_comp = 0;
3082                 bnx2x_post_dmae(bp, dmae, loader_idx);
3083
3084         } else if (bp->func_stx) {
3085                 *stats_comp = 0;
3086                 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3087         }
3088 }
3089
3090 static int bnx2x_stats_comp(struct bnx2x *bp)
3091 {
3092         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3093         int cnt = 10;
3094
3095         might_sleep();
3096         while (*stats_comp != DMAE_COMP_VAL) {
3097                 if (!cnt) {
3098                         BNX2X_ERR("timeout waiting for stats finished\n");
3099                         break;
3100                 }
3101                 cnt--;
3102                 msleep(1);
3103         }
3104         return 1;
3105 }
3106
3107 /*
3108  * Statistics service functions
3109  */
3110
3111 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3112 {
3113         struct dmae_command *dmae;
3114         u32 opcode;
3115         int loader_idx = PMF_DMAE_C(bp);
3116         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3117
3118         /* sanity */
3119         if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3120                 BNX2X_ERR("BUG!\n");
3121                 return;
3122         }
3123
3124         bp->executer_idx = 0;
3125
3126         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3127                   DMAE_CMD_C_ENABLE |
3128                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3129 #ifdef __BIG_ENDIAN
3130                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3131 #else
3132                   DMAE_CMD_ENDIANITY_DW_SWAP |
3133 #endif
3134                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3135                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3136
3137         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3138         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3139         dmae->src_addr_lo = bp->port.port_stx >> 2;
3140         dmae->src_addr_hi = 0;
3141         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3142         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3143         dmae->len = DMAE_LEN32_RD_MAX;
3144         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3145         dmae->comp_addr_hi = 0;
3146         dmae->comp_val = 1;
3147
3148         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3149         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3150         dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3151         dmae->src_addr_hi = 0;
3152         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3153                                    DMAE_LEN32_RD_MAX * 4);
3154         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3155                                    DMAE_LEN32_RD_MAX * 4);
3156         dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3157         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3158         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3159         dmae->comp_val = DMAE_COMP_VAL;
3160
3161         *stats_comp = 0;
3162         bnx2x_hw_stats_post(bp);
3163         bnx2x_stats_comp(bp);
3164 }
3165
3166 static void bnx2x_port_stats_init(struct bnx2x *bp)
3167 {
3168         struct dmae_command *dmae;
3169         int port = BP_PORT(bp);
3170         int vn = BP_E1HVN(bp);
3171         u32 opcode;
3172         int loader_idx = PMF_DMAE_C(bp);
3173         u32 mac_addr;
3174         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3175
3176         /* sanity */
3177         if (!bp->link_vars.link_up || !bp->port.pmf) {
3178                 BNX2X_ERR("BUG!\n");
3179                 return;
3180         }
3181
3182         bp->executer_idx = 0;
3183
3184         /* MCP */
3185         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3186                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3187                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3188 #ifdef __BIG_ENDIAN
3189                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3190 #else
3191                   DMAE_CMD_ENDIANITY_DW_SWAP |
3192 #endif
3193                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3194                   (vn << DMAE_CMD_E1HVN_SHIFT));
3195
3196         if (bp->port.port_stx) {
3197
3198                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3199                 dmae->opcode = opcode;
3200                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3201                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3202                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3203                 dmae->dst_addr_hi = 0;
3204                 dmae->len = sizeof(struct host_port_stats) >> 2;
3205                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3206                 dmae->comp_addr_hi = 0;
3207                 dmae->comp_val = 1;
3208         }
3209
3210         if (bp->func_stx) {
3211
3212                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3213                 dmae->opcode = opcode;
3214                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3215                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3216                 dmae->dst_addr_lo = bp->func_stx >> 2;
3217                 dmae->dst_addr_hi = 0;
3218                 dmae->len = sizeof(struct host_func_stats) >> 2;
3219                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3220                 dmae->comp_addr_hi = 0;
3221                 dmae->comp_val = 1;
3222         }
3223
3224         /* MAC */
3225         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3226                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3227                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3228 #ifdef __BIG_ENDIAN
3229                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3230 #else
3231                   DMAE_CMD_ENDIANITY_DW_SWAP |
3232 #endif
3233                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3234                   (vn << DMAE_CMD_E1HVN_SHIFT));
3235
3236         if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
3237
3238                 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3239                                    NIG_REG_INGRESS_BMAC0_MEM);
3240
3241                 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3242                    BIGMAC_REGISTER_TX_STAT_GTBYT */
3243                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3244                 dmae->opcode = opcode;
3245                 dmae->src_addr_lo = (mac_addr +
3246                                      BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3247                 dmae->src_addr_hi = 0;
3248                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3249                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3250                 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3251                              BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3252                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3253                 dmae->comp_addr_hi = 0;
3254                 dmae->comp_val = 1;
3255
3256                 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3257                    BIGMAC_REGISTER_RX_STAT_GRIPJ */
3258                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3259                 dmae->opcode = opcode;
3260                 dmae->src_addr_lo = (mac_addr +
3261                                      BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3262                 dmae->src_addr_hi = 0;
3263                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3264                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3265                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3266                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3267                 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3268                              BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3269                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3270                 dmae->comp_addr_hi = 0;
3271                 dmae->comp_val = 1;
3272
3273         } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
3274
3275                 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3276
3277                 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3278                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3279                 dmae->opcode = opcode;
3280                 dmae->src_addr_lo = (mac_addr +
3281                                      EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3282                 dmae->src_addr_hi = 0;
3283                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3284                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3285                 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3286                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3287                 dmae->comp_addr_hi = 0;
3288                 dmae->comp_val = 1;
3289
3290                 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3291                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3292                 dmae->opcode = opcode;
3293                 dmae->src_addr_lo = (mac_addr +
3294                                      EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3295                 dmae->src_addr_hi = 0;
3296                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3297                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3298                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3299                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3300                 dmae->len = 1;
3301                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3302                 dmae->comp_addr_hi = 0;
3303                 dmae->comp_val = 1;
3304
3305                 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3306                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3307                 dmae->opcode = opcode;
3308                 dmae->src_addr_lo = (mac_addr +
3309                                      EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3310                 dmae->src_addr_hi = 0;
3311                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3312                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3313                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3314                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3315                 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3316                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3317                 dmae->comp_addr_hi = 0;
3318                 dmae->comp_val = 1;
3319         }
3320
3321         /* NIG */
3322         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3323         dmae->opcode = opcode;
3324         dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3325                                     NIG_REG_STAT0_BRB_DISCARD) >> 2;
3326         dmae->src_addr_hi = 0;
3327         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
3328         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
3329         dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
3330         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3331         dmae->comp_addr_hi = 0;
3332         dmae->comp_val = 1;
3333
3334         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3335         dmae->opcode = opcode;
3336         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
3337                                     NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
3338         dmae->src_addr_hi = 0;
3339         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3340                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3341         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3342                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3343         dmae->len = (2*sizeof(u32)) >> 2;
3344         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3345         dmae->comp_addr_hi = 0;
3346         dmae->comp_val = 1;
3347
3348         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3349         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3350                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3351                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3352 #ifdef __BIG_ENDIAN
3353                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3354 #else
3355                         DMAE_CMD_ENDIANITY_DW_SWAP |
3356 #endif
3357                         (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3358                         (vn << DMAE_CMD_E1HVN_SHIFT));
3359         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
3360                                     NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
3361         dmae->src_addr_hi = 0;
3362         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3363                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3364         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3365                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3366         dmae->len = (2*sizeof(u32)) >> 2;
3367         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3368         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3369         dmae->comp_val = DMAE_COMP_VAL;
3370
3371         *stats_comp = 0;
3372 }
3373
3374 static void bnx2x_func_stats_init(struct bnx2x *bp)
3375 {
3376         struct dmae_command *dmae = &bp->stats_dmae;
3377         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3378
3379         /* sanity */
3380         if (!bp->func_stx) {
3381                 BNX2X_ERR("BUG!\n");
3382                 return;
3383         }
3384
3385         bp->executer_idx = 0;
3386         memset(dmae, 0, sizeof(struct dmae_command));
3387
3388         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3389                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3390                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3391 #ifdef __BIG_ENDIAN
3392                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3393 #else
3394                         DMAE_CMD_ENDIANITY_DW_SWAP |
3395 #endif
3396                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3397                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3398         dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3399         dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3400         dmae->dst_addr_lo = bp->func_stx >> 2;
3401         dmae->dst_addr_hi = 0;
3402         dmae->len = sizeof(struct host_func_stats) >> 2;
3403         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3404         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3405         dmae->comp_val = DMAE_COMP_VAL;
3406
3407         *stats_comp = 0;
3408 }
3409
3410 static void bnx2x_stats_start(struct bnx2x *bp)
3411 {
3412         if (bp->port.pmf)
3413                 bnx2x_port_stats_init(bp);
3414
3415         else if (bp->func_stx)
3416                 bnx2x_func_stats_init(bp);
3417
3418         bnx2x_hw_stats_post(bp);
3419         bnx2x_storm_stats_post(bp);
3420 }
3421
3422 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
3423 {
3424         bnx2x_stats_comp(bp);
3425         bnx2x_stats_pmf_update(bp);
3426         bnx2x_stats_start(bp);
3427 }
3428
3429 static void bnx2x_stats_restart(struct bnx2x *bp)
3430 {
3431         bnx2x_stats_comp(bp);
3432         bnx2x_stats_start(bp);
3433 }
3434
3435 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3436 {
3437         struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
3438         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3439         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3440         struct regpair diff;
3441
3442         UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
3443         UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
3444         UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
3445         UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3446         UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3447         UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3448         UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3449         UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3450         UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf);
3451         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
3452         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
3453         UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
3454         UPDATE_STAT64(tx_stat_gt127,
3455                                 tx_stat_etherstatspkts65octetsto127octets);
3456         UPDATE_STAT64(tx_stat_gt255,
3457                                 tx_stat_etherstatspkts128octetsto255octets);
3458         UPDATE_STAT64(tx_stat_gt511,
3459                                 tx_stat_etherstatspkts256octetsto511octets);
3460         UPDATE_STAT64(tx_stat_gt1023,
3461                                 tx_stat_etherstatspkts512octetsto1023octets);
3462         UPDATE_STAT64(tx_stat_gt1518,
3463                                 tx_stat_etherstatspkts1024octetsto1522octets);
3464         UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
3465         UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
3466         UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
3467         UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
3468         UPDATE_STAT64(tx_stat_gterr,
3469                                 tx_stat_dot3statsinternalmactransmiterrors);
3470         UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
3471
3472         estats->pause_frames_received_hi =
3473                                 pstats->mac_stx[1].rx_stat_bmac_xpf_hi;
3474         estats->pause_frames_received_lo =
3475                                 pstats->mac_stx[1].rx_stat_bmac_xpf_lo;
3476
3477         estats->pause_frames_sent_hi =
3478                                 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
3479         estats->pause_frames_sent_lo =
3480                                 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
3481 }
3482
3483 static void bnx2x_emac_stats_update(struct bnx2x *bp)
3484 {
3485         struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
3486         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3487         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3488
3489         UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
3490         UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
3491         UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
3492         UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
3493         UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
3494         UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
3495         UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
3496         UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
3497         UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
3498         UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
3499         UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
3500         UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
3501         UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
3502         UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
3503         UPDATE_EXTEND_STAT(tx_stat_outxonsent);
3504         UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
3505         UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
3506         UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
3507         UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
3508         UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
3509         UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
3510         UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
3511         UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
3512         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
3513         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
3514         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
3515         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
3516         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
3517         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
3518         UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
3519         UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
3520
3521         estats->pause_frames_received_hi =
3522                         pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
3523         estats->pause_frames_received_lo =
3524                         pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
3525         ADD_64(estats->pause_frames_received_hi,
3526                pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
3527                estats->pause_frames_received_lo,
3528                pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
3529
3530         estats->pause_frames_sent_hi =
3531                         pstats->mac_stx[1].tx_stat_outxonsent_hi;
3532         estats->pause_frames_sent_lo =
3533                         pstats->mac_stx[1].tx_stat_outxonsent_lo;
3534         ADD_64(estats->pause_frames_sent_hi,
3535                pstats->mac_stx[1].tx_stat_outxoffsent_hi,
3536                estats->pause_frames_sent_lo,
3537                pstats->mac_stx[1].tx_stat_outxoffsent_lo);
3538 }
3539
3540 static int bnx2x_hw_stats_update(struct bnx2x *bp)
3541 {
3542         struct nig_stats *new = bnx2x_sp(bp, nig_stats);
3543         struct nig_stats *old = &(bp->port.old_nig_stats);
3544         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3545         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3546         struct regpair diff;
3547         u32 nig_timer_max;
3548
3549         if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
3550                 bnx2x_bmac_stats_update(bp);
3551
3552         else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
3553                 bnx2x_emac_stats_update(bp);
3554
3555         else { /* unreached */
3556                 BNX2X_ERR("stats updated by dmae but no MAC active\n");
3557                 return -1;
3558         }
3559
3560         ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3561                       new->brb_discard - old->brb_discard);
3562         ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3563                       new->brb_truncate - old->brb_truncate);
3564
3565         UPDATE_STAT64_NIG(egress_mac_pkt0,
3566                                         etherstatspkts1024octetsto1522octets);
3567         UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
3568
3569         memcpy(old, new, sizeof(struct nig_stats));
3570
3571         memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
3572                sizeof(struct mac_stx));
3573         estats->brb_drop_hi = pstats->brb_drop_hi;
3574         estats->brb_drop_lo = pstats->brb_drop_lo;
3575
3576         pstats->host_port_stats_start = ++pstats->host_port_stats_end;
3577
3578         nig_timer_max = SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
3579         if (nig_timer_max != estats->nig_timer_max) {
3580                 estats->nig_timer_max = nig_timer_max;
3581                 BNX2X_ERR("NIG timer max (%u)\n", estats->nig_timer_max);
3582         }
3583
3584         return 0;
3585 }
3586
3587 static int bnx2x_storm_stats_update(struct bnx2x *bp)
3588 {
3589         struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
3590         struct tstorm_per_port_stats *tport =
3591                                         &stats->tstorm_common.port_statistics;
3592         struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
3593         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3594         int i;
3595
3596         memset(&(fstats->total_bytes_received_hi), 0,
3597                sizeof(struct host_func_stats) - 2*sizeof(u32));
3598         estats->error_bytes_received_hi = 0;
3599         estats->error_bytes_received_lo = 0;
3600         estats->etherstatsoverrsizepkts_hi = 0;
3601         estats->etherstatsoverrsizepkts_lo = 0;
3602         estats->no_buff_discard_hi = 0;
3603         estats->no_buff_discard_lo = 0;
3604
3605         for_each_queue(bp, i) {
3606                 struct bnx2x_fastpath *fp = &bp->fp[i];
3607                 int cl_id = fp->cl_id;
3608                 struct tstorm_per_client_stats *tclient =
3609                                 &stats->tstorm_common.client_statistics[cl_id];
3610                 struct tstorm_per_client_stats *old_tclient = &fp->old_tclient;
3611                 struct ustorm_per_client_stats *uclient =
3612                                 &stats->ustorm_common.client_statistics[cl_id];
3613                 struct ustorm_per_client_stats *old_uclient = &fp->old_uclient;
3614                 struct xstorm_per_client_stats *xclient =
3615                                 &stats->xstorm_common.client_statistics[cl_id];
3616                 struct xstorm_per_client_stats *old_xclient = &fp->old_xclient;
3617                 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
3618                 u32 diff;
3619
3620                 /* are storm stats valid? */
3621                 if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
3622                                                         bp->stats_counter) {
3623                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by xstorm"
3624                            "  xstorm counter (%d) != stats_counter (%d)\n",
3625                            i, xclient->stats_counter, bp->stats_counter);
3626                         return -1;
3627                 }
3628                 if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
3629                                                         bp->stats_counter) {
3630                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by tstorm"
3631                            "  tstorm counter (%d) != stats_counter (%d)\n",
3632                            i, tclient->stats_counter, bp->stats_counter);
3633                         return -2;
3634                 }
3635                 if ((u16)(le16_to_cpu(uclient->stats_counter) + 1) !=
3636                                                         bp->stats_counter) {
3637                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by ustorm"
3638                            "  ustorm counter (%d) != stats_counter (%d)\n",
3639                            i, uclient->stats_counter, bp->stats_counter);
3640                         return -4;
3641                 }
3642
3643                 qstats->total_bytes_received_hi =
3644                 qstats->valid_bytes_received_hi =
3645                                 le32_to_cpu(tclient->total_rcv_bytes.hi);
3646                 qstats->total_bytes_received_lo =
3647                 qstats->valid_bytes_received_lo =
3648                                 le32_to_cpu(tclient->total_rcv_bytes.lo);
3649
3650                 qstats->error_bytes_received_hi =
3651                                 le32_to_cpu(tclient->rcv_error_bytes.hi);
3652                 qstats->error_bytes_received_lo =
3653                                 le32_to_cpu(tclient->rcv_error_bytes.lo);
3654
3655                 ADD_64(qstats->total_bytes_received_hi,
3656                        qstats->error_bytes_received_hi,
3657                        qstats->total_bytes_received_lo,
3658                        qstats->error_bytes_received_lo);
3659
3660                 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
3661                                         total_unicast_packets_received);
3662                 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
3663                                         total_multicast_packets_received);
3664                 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
3665                                         total_broadcast_packets_received);
3666                 UPDATE_EXTEND_TSTAT(packets_too_big_discard,
3667                                         etherstatsoverrsizepkts);
3668                 UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
3669
3670                 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
3671                                         total_unicast_packets_received);
3672                 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
3673                                         total_multicast_packets_received);
3674                 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
3675                                         total_broadcast_packets_received);
3676                 UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
3677                 UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
3678                 UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
3679
3680                 qstats->total_bytes_transmitted_hi =
3681                                 le32_to_cpu(xclient->total_sent_bytes.hi);
3682                 qstats->total_bytes_transmitted_lo =
3683                                 le32_to_cpu(xclient->total_sent_bytes.lo);
3684
3685                 UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
3686                                         total_unicast_packets_transmitted);
3687                 UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
3688                                         total_multicast_packets_transmitted);
3689                 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
3690                                         total_broadcast_packets_transmitted);
3691
3692                 old_tclient->checksum_discard = tclient->checksum_discard;
3693                 old_tclient->ttl0_discard = tclient->ttl0_discard;
3694
3695                 ADD_64(fstats->total_bytes_received_hi,
3696                        qstats->total_bytes_received_hi,
3697                        fstats->total_bytes_received_lo,
3698                        qstats->total_bytes_received_lo);
3699                 ADD_64(fstats->total_bytes_transmitted_hi,
3700                        qstats->total_bytes_transmitted_hi,
3701                        fstats->total_bytes_transmitted_lo,
3702                        qstats->total_bytes_transmitted_lo);
3703                 ADD_64(fstats->total_unicast_packets_received_hi,
3704                        qstats->total_unicast_packets_received_hi,
3705                        fstats->total_unicast_packets_received_lo,
3706                        qstats->total_unicast_packets_received_lo);
3707                 ADD_64(fstats->total_multicast_packets_received_hi,
3708                        qstats->total_multicast_packets_received_hi,
3709                        fstats->total_multicast_packets_received_lo,
3710                        qstats->total_multicast_packets_received_lo);
3711                 ADD_64(fstats->total_broadcast_packets_received_hi,
3712                        qstats->total_broadcast_packets_received_hi,
3713                        fstats->total_broadcast_packets_received_lo,
3714                        qstats->total_broadcast_packets_received_lo);
3715                 ADD_64(fstats->total_unicast_packets_transmitted_hi,
3716                        qstats->total_unicast_packets_transmitted_hi,
3717                        fstats->total_unicast_packets_transmitted_lo,
3718                        qstats->total_unicast_packets_transmitted_lo);
3719                 ADD_64(fstats->total_multicast_packets_transmitted_hi,
3720                        qstats->total_multicast_packets_transmitted_hi,
3721                        fstats->total_multicast_packets_transmitted_lo,
3722                        qstats->total_multicast_packets_transmitted_lo);
3723                 ADD_64(fstats->total_broadcast_packets_transmitted_hi,
3724                        qstats->total_broadcast_packets_transmitted_hi,
3725                        fstats->total_broadcast_packets_transmitted_lo,
3726                        qstats->total_broadcast_packets_transmitted_lo);
3727                 ADD_64(fstats->valid_bytes_received_hi,
3728                        qstats->valid_bytes_received_hi,
3729                        fstats->valid_bytes_received_lo,
3730                        qstats->valid_bytes_received_lo);
3731
3732                 ADD_64(estats->error_bytes_received_hi,
3733                        qstats->error_bytes_received_hi,
3734                        estats->error_bytes_received_lo,
3735                        qstats->error_bytes_received_lo);
3736                 ADD_64(estats->etherstatsoverrsizepkts_hi,
3737                        qstats->etherstatsoverrsizepkts_hi,
3738                        estats->etherstatsoverrsizepkts_lo,
3739                        qstats->etherstatsoverrsizepkts_lo);
3740                 ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
3741                        estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
3742         }
3743
3744         ADD_64(fstats->total_bytes_received_hi,
3745                estats->rx_stat_ifhcinbadoctets_hi,
3746                fstats->total_bytes_received_lo,
3747                estats->rx_stat_ifhcinbadoctets_lo);
3748
3749         memcpy(estats, &(fstats->total_bytes_received_hi),
3750                sizeof(struct host_func_stats) - 2*sizeof(u32));
3751
3752         ADD_64(estats->etherstatsoverrsizepkts_hi,
3753                estats->rx_stat_dot3statsframestoolong_hi,
3754                estats->etherstatsoverrsizepkts_lo,
3755                estats->rx_stat_dot3statsframestoolong_lo);
3756         ADD_64(estats->error_bytes_received_hi,
3757                estats->rx_stat_ifhcinbadoctets_hi,
3758                estats->error_bytes_received_lo,
3759                estats->rx_stat_ifhcinbadoctets_lo);
3760
3761         if (bp->port.pmf) {
3762                 estats->mac_filter_discard =
3763                                 le32_to_cpu(tport->mac_filter_discard);
3764                 estats->xxoverflow_discard =
3765                                 le32_to_cpu(tport->xxoverflow_discard);
3766                 estats->brb_truncate_discard =
3767                                 le32_to_cpu(tport->brb_truncate_discard);
3768                 estats->mac_discard = le32_to_cpu(tport->mac_discard);
3769         }
3770
3771         fstats->host_func_stats_start = ++fstats->host_func_stats_end;
3772
3773         bp->stats_pending = 0;
3774
3775         return 0;
3776 }
3777
3778 static void bnx2x_net_stats_update(struct bnx2x *bp)
3779 {
3780         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3781         struct net_device_stats *nstats = &bp->dev->stats;
3782         int i;
3783
3784         nstats->rx_packets =
3785                 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
3786                 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
3787                 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
3788
3789         nstats->tx_packets =
3790                 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
3791                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
3792                 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
3793
3794         nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
3795
3796         nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
3797
3798         nstats->rx_dropped = estats->mac_discard;
3799         for_each_queue(bp, i)
3800                 nstats->rx_dropped +=
3801                         le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
3802
3803         nstats->tx_dropped = 0;
3804
3805         nstats->multicast =
3806                 bnx2x_hilo(&estats->total_multicast_packets_received_hi);
3807
3808         nstats->collisions =
3809                 bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
3810
3811         nstats->rx_length_errors =
3812                 bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
3813                 bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
3814         nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
3815                                  bnx2x_hilo(&estats->brb_truncate_hi);
3816         nstats->rx_crc_errors =
3817                 bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
3818         nstats->rx_frame_errors =
3819                 bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
3820         nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
3821         nstats->rx_missed_errors = estats->xxoverflow_discard;
3822
3823         nstats->rx_errors = nstats->rx_length_errors +
3824                             nstats->rx_over_errors +
3825                             nstats->rx_crc_errors +
3826                             nstats->rx_frame_errors +
3827                             nstats->rx_fifo_errors +
3828                             nstats->rx_missed_errors;
3829
3830         nstats->tx_aborted_errors =
3831                 bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
3832                 bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
3833         nstats->tx_carrier_errors =
3834                 bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
3835         nstats->tx_fifo_errors = 0;
3836         nstats->tx_heartbeat_errors = 0;
3837         nstats->tx_window_errors = 0;
3838
3839         nstats->tx_errors = nstats->tx_aborted_errors +
3840                             nstats->tx_carrier_errors +
3841             bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
3842 }
3843
3844 static void bnx2x_drv_stats_update(struct bnx2x *bp)
3845 {
3846         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3847         int i;
3848
3849         estats->driver_xoff = 0;
3850         estats->rx_err_discard_pkt = 0;
3851         estats->rx_skb_alloc_failed = 0;
3852         estats->hw_csum_err = 0;
3853         for_each_queue(bp, i) {
3854                 struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
3855
3856                 estats->driver_xoff += qstats->driver_xoff;
3857                 estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
3858                 estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
3859                 estats->hw_csum_err += qstats->hw_csum_err;
3860         }
3861 }
3862
3863 static void bnx2x_stats_update(struct bnx2x *bp)
3864 {
3865         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3866
3867         if (*stats_comp != DMAE_COMP_VAL)
3868                 return;
3869
3870         if (bp->port.pmf)
3871                 bnx2x_hw_stats_update(bp);
3872
3873         if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
3874                 BNX2X_ERR("storm stats were not updated for 3 times\n");
3875                 bnx2x_panic();
3876                 return;
3877         }
3878
3879         bnx2x_net_stats_update(bp);
3880         bnx2x_drv_stats_update(bp);
3881
3882         if (bp->msglevel & NETIF_MSG_TIMER) {
3883                 struct tstorm_per_client_stats *old_tclient =
3884                                                         &bp->fp->old_tclient;
3885                 struct bnx2x_eth_q_stats *qstats = &bp->fp->eth_q_stats;
3886                 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3887                 struct net_device_stats *nstats = &bp->dev->stats;
3888                 int i;
3889
3890                 printk(KERN_DEBUG "%s:\n", bp->dev->name);
3891                 printk(KERN_DEBUG "  tx avail (%4x)  tx hc idx (%x)"
3892                                   "  tx pkt (%lx)\n",
3893                        bnx2x_tx_avail(bp->fp),
3894                        le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
3895                 printk(KERN_DEBUG "  rx usage (%4x)  rx hc idx (%x)"
3896                                   "  rx pkt (%lx)\n",
3897                        (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
3898                              bp->fp->rx_comp_cons),
3899                        le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3900                 printk(KERN_DEBUG "  %s (Xoff events %u)  brb drops %u  "
3901                                   "brb truncate %u\n",
3902                        (netif_queue_stopped(bp->dev) ? "Xoff" : "Xon"),
3903                        qstats->driver_xoff,
3904                        estats->brb_drop_lo, estats->brb_truncate_lo);
3905                 printk(KERN_DEBUG "tstats: checksum_discard %u  "
3906                         "packets_too_big_discard %lu  no_buff_discard %lu  "
3907                         "mac_discard %u  mac_filter_discard %u  "
3908                         "xxovrflow_discard %u  brb_truncate_discard %u  "
3909                         "ttl0_discard %u\n",
3910                        old_tclient->checksum_discard,
3911                        bnx2x_hilo(&qstats->etherstatsoverrsizepkts_hi),
3912                        bnx2x_hilo(&qstats->no_buff_discard_hi),
3913                        estats->mac_discard, estats->mac_filter_discard,
3914                        estats->xxoverflow_discard, estats->brb_truncate_discard,
3915                        old_tclient->ttl0_discard);
3916
3917                 for_each_queue(bp, i) {
3918                         printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
3919                                bnx2x_fp(bp, i, tx_pkt),
3920                                bnx2x_fp(bp, i, rx_pkt),
3921                                bnx2x_fp(bp, i, rx_calls));
3922                 }
3923         }
3924
3925         bnx2x_hw_stats_post(bp);
3926         bnx2x_storm_stats_post(bp);
3927 }
3928
3929 static void bnx2x_port_stats_stop(struct bnx2x *bp)
3930 {
3931         struct dmae_command *dmae;
3932         u32 opcode;
3933         int loader_idx = PMF_DMAE_C(bp);
3934         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3935
3936         bp->executer_idx = 0;
3937
3938         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3939                   DMAE_CMD_C_ENABLE |
3940                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3941 #ifdef __BIG_ENDIAN
3942                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3943 #else
3944                   DMAE_CMD_ENDIANITY_DW_SWAP |
3945 #endif
3946                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3947                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3948
3949         if (bp->port.port_stx) {
3950
3951                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3952                 if (bp->func_stx)
3953                         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3954                 else
3955                         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3956                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3957                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3958                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3959                 dmae->dst_addr_hi = 0;
3960                 dmae->len = sizeof(struct host_port_stats) >> 2;
3961                 if (bp->func_stx) {
3962                         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3963                         dmae->comp_addr_hi = 0;
3964                         dmae->comp_val = 1;
3965                 } else {
3966                         dmae->comp_addr_lo =
3967                                 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3968                         dmae->comp_addr_hi =
3969                                 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3970                         dmae->comp_val = DMAE_COMP_VAL;
3971
3972                         *stats_comp = 0;
3973                 }
3974         }
3975
3976         if (bp->func_stx) {
3977
3978                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3979                 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3980                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3981                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3982                 dmae->dst_addr_lo = bp->func_stx >> 2;
3983                 dmae->dst_addr_hi = 0;
3984                 dmae->len = sizeof(struct host_func_stats) >> 2;
3985                 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3986                 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3987                 dmae->comp_val = DMAE_COMP_VAL;
3988
3989                 *stats_comp = 0;
3990         }
3991 }
3992
3993 static void bnx2x_stats_stop(struct bnx2x *bp)
3994 {
3995         int update = 0;
3996
3997         bnx2x_stats_comp(bp);
3998
3999         if (bp->port.pmf)
4000                 update = (bnx2x_hw_stats_update(bp) == 0);
4001
4002         update |= (bnx2x_storm_stats_update(bp) == 0);
4003
4004         if (update) {
4005                 bnx2x_net_stats_update(bp);
4006
4007                 if (bp->port.pmf)
4008                         bnx2x_port_stats_stop(bp);
4009
4010                 bnx2x_hw_stats_post(bp);
4011                 bnx2x_stats_comp(bp);
4012         }
4013 }
4014
4015 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
4016 {
4017 }
4018
4019 static const struct {
4020         void (*action)(struct bnx2x *bp);
4021         enum bnx2x_stats_state next_state;
4022 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
4023 /* state        event   */
4024 {
4025 /* DISABLED     PMF     */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
4026 /*              LINK_UP */ {bnx2x_stats_start,      STATS_STATE_ENABLED},
4027 /*              UPDATE  */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
4028 /*              STOP    */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
4029 },
4030 {
4031 /* ENABLED      PMF     */ {bnx2x_stats_pmf_start,  STATS_STATE_ENABLED},
4032 /*              LINK_UP */ {bnx2x_stats_restart,    STATS_STATE_ENABLED},
4033 /*              UPDATE  */ {bnx2x_stats_update,     STATS_STATE_ENABLED},
4034 /*              STOP    */ {bnx2x_stats_stop,       STATS_STATE_DISABLED}
4035 }
4036 };
4037
4038 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
4039 {
4040         enum bnx2x_stats_state state = bp->stats_state;
4041
4042         bnx2x_stats_stm[state][event].action(bp);
4043         bp->stats_state = bnx2x_stats_stm[state][event].next_state;
4044
4045         if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
4046                 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
4047                    state, event, bp->stats_state);
4048 }
4049
4050 static void bnx2x_timer(unsigned long data)
4051 {
4052         struct bnx2x *bp = (struct bnx2x *) data;
4053
4054         if (!netif_running(bp->dev))
4055                 return;
4056
4057         if (atomic_read(&bp->intr_sem) != 0)
4058                 goto timer_restart;
4059
4060         if (poll) {
4061                 struct bnx2x_fastpath *fp = &bp->fp[0];
4062                 int rc;
4063
4064                 bnx2x_tx_int(fp, 1000);
4065                 rc = bnx2x_rx_int(fp, 1000);
4066         }
4067
4068         if (!BP_NOMCP(bp)) {
4069                 int func = BP_FUNC(bp);
4070                 u32 drv_pulse;
4071                 u32 mcp_pulse;
4072
4073                 ++bp->fw_drv_pulse_wr_seq;
4074                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4075                 /* TBD - add SYSTEM_TIME */
4076                 drv_pulse = bp->fw_drv_pulse_wr_seq;
4077                 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
4078
4079                 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
4080                              MCP_PULSE_SEQ_MASK);
4081                 /* The delta between driver pulse and mcp response
4082                  * should be 1 (before mcp response) or 0 (after mcp response)
4083                  */
4084                 if ((drv_pulse != mcp_pulse) &&
4085                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4086                         /* someone lost a heartbeat... */
4087                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4088                                   drv_pulse, mcp_pulse);
4089                 }
4090         }
4091
4092         if ((bp->state == BNX2X_STATE_OPEN) ||
4093             (bp->state == BNX2X_STATE_DISABLED))
4094                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4095
4096 timer_restart:
4097         mod_timer(&bp->timer, jiffies + bp->current_interval);
4098 }
4099
4100 /* end of Statistics */
4101
4102 /* nic init */
4103
4104 /*
4105  * nic init service functions
4106  */
4107
4108 static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
4109 {
4110         int port = BP_PORT(bp);
4111
4112         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4113                         USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4114                         sizeof(struct ustorm_status_block)/4);
4115         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4116                         CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4117                         sizeof(struct cstorm_status_block)/4);
4118 }
4119
4120 static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4121                           dma_addr_t mapping, int sb_id)
4122 {
4123         int port = BP_PORT(bp);
4124         int func = BP_FUNC(bp);
4125         int index;
4126         u64 section;
4127
4128         /* USTORM */
4129         section = ((u64)mapping) + offsetof(struct host_status_block,
4130                                             u_status_block);
4131         sb->u_status_block.status_block_id = sb_id;
4132
4133         REG_WR(bp, BAR_USTRORM_INTMEM +
4134                USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4135         REG_WR(bp, BAR_USTRORM_INTMEM +
4136                ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4137                U64_HI(section));
4138         REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
4139                 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4140
4141         for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4142                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4143                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4144
4145         /* CSTORM */
4146         section = ((u64)mapping) + offsetof(struct host_status_block,
4147                                             c_status_block);
4148         sb->c_status_block.status_block_id = sb_id;
4149
4150         REG_WR(bp, BAR_CSTRORM_INTMEM +
4151                CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4152         REG_WR(bp, BAR_CSTRORM_INTMEM +
4153                ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4154                U64_HI(section));
4155         REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
4156                 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4157
4158         for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4159                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4160                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4161
4162         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4163 }
4164
4165 static void bnx2x_zero_def_sb(struct bnx2x *bp)
4166 {
4167         int func = BP_FUNC(bp);
4168
4169         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4170                         USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4171                         sizeof(struct ustorm_def_status_block)/4);
4172         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4173                         CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4174                         sizeof(struct cstorm_def_status_block)/4);
4175         bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
4176                         XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4177                         sizeof(struct xstorm_def_status_block)/4);
4178         bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4179                         TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4180                         sizeof(struct tstorm_def_status_block)/4);
4181 }
4182
4183 static void bnx2x_init_def_sb(struct bnx2x *bp,
4184                               struct host_def_status_block *def_sb,
4185                               dma_addr_t mapping, int sb_id)
4186 {
4187         int port = BP_PORT(bp);
4188         int func = BP_FUNC(bp);
4189         int index, val, reg_offset;
4190         u64 section;
4191
4192         /* ATTN */
4193         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4194                                             atten_status_block);
4195         def_sb->atten_status_block.status_block_id = sb_id;
4196
4197         bp->attn_state = 0;
4198
4199         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4200                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4201
4202         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4203                 bp->attn_group[index].sig[0] = REG_RD(bp,
4204                                                      reg_offset + 0x10*index);
4205                 bp->attn_group[index].sig[1] = REG_RD(bp,
4206                                                reg_offset + 0x4 + 0x10*index);
4207                 bp->attn_group[index].sig[2] = REG_RD(bp,
4208                                                reg_offset + 0x8 + 0x10*index);
4209                 bp->attn_group[index].sig[3] = REG_RD(bp,
4210                                                reg_offset + 0xc + 0x10*index);
4211         }
4212
4213         reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4214                              HC_REG_ATTN_MSG0_ADDR_L);
4215
4216         REG_WR(bp, reg_offset, U64_LO(section));
4217         REG_WR(bp, reg_offset + 4, U64_HI(section));
4218
4219         reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4220
4221         val = REG_RD(bp, reg_offset);
4222         val |= sb_id;
4223         REG_WR(bp, reg_offset, val);
4224
4225         /* USTORM */
4226         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4227                                             u_def_status_block);
4228         def_sb->u_def_status_block.status_block_id = sb_id;
4229
4230         REG_WR(bp, BAR_USTRORM_INTMEM +
4231                USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4232         REG_WR(bp, BAR_USTRORM_INTMEM +
4233                ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4234                U64_HI(section));
4235         REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4236                 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4237
4238         for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4239                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4240                          USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4241
4242         /* CSTORM */
4243         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4244                                             c_def_status_block);
4245         def_sb->c_def_status_block.status_block_id = sb_id;
4246
4247         REG_WR(bp, BAR_CSTRORM_INTMEM +
4248                CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4249         REG_WR(bp, BAR_CSTRORM_INTMEM +
4250                ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4251                U64_HI(section));
4252         REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4253                 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4254
4255         for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4256                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4257                          CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4258
4259         /* TSTORM */
4260         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4261                                             t_def_status_block);
4262         def_sb->t_def_status_block.status_block_id = sb_id;
4263
4264         REG_WR(bp, BAR_TSTRORM_INTMEM +
4265                TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4266         REG_WR(bp, BAR_TSTRORM_INTMEM +
4267                ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4268                U64_HI(section));
4269         REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4270                 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4271
4272         for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4273                 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4274                          TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4275
4276         /* XSTORM */
4277         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4278                                             x_def_status_block);
4279         def_sb->x_def_status_block.status_block_id = sb_id;
4280
4281         REG_WR(bp, BAR_XSTRORM_INTMEM +
4282                XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4283         REG_WR(bp, BAR_XSTRORM_INTMEM +
4284                ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4285                U64_HI(section));
4286         REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4287                 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4288
4289         for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4290                 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4291                          XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4292
4293         bp->stats_pending = 0;
4294         bp->set_mac_pending = 0;
4295
4296         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4297 }
4298
4299 static void bnx2x_update_coalesce(struct bnx2x *bp)
4300 {
4301         int port = BP_PORT(bp);
4302         int i;
4303
4304         for_each_queue(bp, i) {
4305                 int sb_id = bp->fp[i].sb_id;
4306
4307                 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4308                 REG_WR8(bp, BAR_USTRORM_INTMEM +
4309                         USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4310                                                     U_SB_ETH_RX_CQ_INDEX),
4311                         bp->rx_ticks/12);
4312                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4313                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4314                                                      U_SB_ETH_RX_CQ_INDEX),
4315                          bp->rx_ticks ? 0 : 1);
4316
4317                 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4318                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4319                         CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4320                                                     C_SB_ETH_TX_CQ_INDEX),
4321                         bp->tx_ticks/12);
4322                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4323                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4324                                                      C_SB_ETH_TX_CQ_INDEX),
4325                          bp->tx_ticks ? 0 : 1);
4326         }
4327 }
4328
4329 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4330                                        struct bnx2x_fastpath *fp, int last)
4331 {
4332         int i;
4333
4334         for (i = 0; i < last; i++) {
4335                 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
4336                 struct sk_buff *skb = rx_buf->skb;
4337
4338                 if (skb == NULL) {
4339                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
4340                         continue;
4341                 }
4342
4343                 if (fp->tpa_state[i] == BNX2X_TPA_START)
4344                         pci_unmap_single(bp->pdev,
4345                                          pci_unmap_addr(rx_buf, mapping),
4346                                          bp->rx_buf_size,
4347                                          PCI_DMA_FROMDEVICE);
4348
4349                 dev_kfree_skb(skb);
4350                 rx_buf->skb = NULL;
4351         }
4352 }
4353
4354 static void bnx2x_init_rx_rings(struct bnx2x *bp)
4355 {
4356         int func = BP_FUNC(bp);
4357         int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4358                                               ETH_MAX_AGGREGATION_QUEUES_E1H;
4359         u16 ring_prod, cqe_ring_prod;
4360         int i, j;
4361
4362         bp->rx_buf_size += bp->rx_offset + ETH_OVREHEAD + BNX2X_RX_ALIGN;
4363         DP(NETIF_MSG_IFUP,
4364            "mtu %d  rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size);
4365
4366         if (bp->flags & TPA_ENABLE_FLAG) {
4367
4368                 for_each_rx_queue(bp, j) {
4369                         struct bnx2x_fastpath *fp = &bp->fp[j];
4370
4371                         for (i = 0; i < max_agg_queues; i++) {
4372                                 fp->tpa_pool[i].skb =
4373                                    netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4374                                 if (!fp->tpa_pool[i].skb) {
4375                                         BNX2X_ERR("Failed to allocate TPA "
4376                                                   "skb pool for queue[%d] - "
4377                                                   "disabling TPA on this "
4378                                                   "queue!\n", j);
4379                                         bnx2x_free_tpa_pool(bp, fp, i);
4380                                         fp->disable_tpa = 1;
4381                                         break;
4382                                 }
4383                                 pci_unmap_addr_set((struct sw_rx_bd *)
4384                                                         &bp->fp->tpa_pool[i],
4385                                                    mapping, 0);
4386                                 fp->tpa_state[i] = BNX2X_TPA_STOP;
4387                         }
4388                 }
4389         }
4390
4391         for_each_rx_queue(bp, j) {
4392                 struct bnx2x_fastpath *fp = &bp->fp[j];
4393
4394                 fp->rx_bd_cons = 0;
4395                 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4396                 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
4397
4398                 /* "next page" elements initialization */
4399                 /* SGE ring */
4400                 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
4401                         struct eth_rx_sge *sge;
4402
4403                         sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
4404                         sge->addr_hi =
4405                                 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
4406                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4407                         sge->addr_lo =
4408                                 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
4409                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4410                 }
4411
4412                 bnx2x_init_sge_ring_bit_mask(fp);
4413
4414                 /* RX BD ring */
4415                 for (i = 1; i <= NUM_RX_RINGS; i++) {
4416                         struct eth_rx_bd *rx_bd;
4417
4418                         rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4419                         rx_bd->addr_hi =
4420                                 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4421                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4422                         rx_bd->addr_lo =
4423                                 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4424                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4425                 }
4426
4427                 /* CQ ring */
4428                 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4429                         struct eth_rx_cqe_next_page *nextpg;
4430
4431                         nextpg = (struct eth_rx_cqe_next_page *)
4432                                 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4433                         nextpg->addr_hi =
4434                                 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4435                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4436                         nextpg->addr_lo =
4437                                 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4438                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4439                 }
4440
4441                 /* Allocate SGEs and initialize the ring elements */
4442                 for (i = 0, ring_prod = 0;
4443                      i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4444
4445                         if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
4446                                 BNX2X_ERR("was only able to allocate "
4447                                           "%d rx sges\n", i);
4448                                 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4449                                 /* Cleanup already allocated elements */
4450                                 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4451                                 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4452                                 fp->disable_tpa = 1;
4453                                 ring_prod = 0;
4454                                 break;
4455                         }
4456                         ring_prod = NEXT_SGE_IDX(ring_prod);
4457                 }
4458                 fp->rx_sge_prod = ring_prod;
4459
4460                 /* Allocate BDs and initialize BD ring */
4461                 fp->rx_comp_cons = 0;
4462                 cqe_ring_prod = ring_prod = 0;
4463                 for (i = 0; i < bp->rx_ring_size; i++) {
4464                         if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4465                                 BNX2X_ERR("was only able to allocate "
4466                                           "%d rx skbs on queue[%d]\n", i, j);
4467                                 fp->eth_q_stats.rx_skb_alloc_failed++;
4468                                 break;
4469                         }
4470                         ring_prod = NEXT_RX_IDX(ring_prod);
4471                         cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4472                         WARN_ON(ring_prod <= i);
4473                 }
4474
4475                 fp->rx_bd_prod = ring_prod;
4476                 /* must not have more available CQEs than BDs */
4477                 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
4478                                        cqe_ring_prod);
4479                 fp->rx_pkt = fp->rx_calls = 0;
4480
4481                 /* Warning!
4482                  * this will generate an interrupt (to the TSTORM)
4483                  * must only be done after chip is initialized
4484                  */
4485                 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
4486                                      fp->rx_sge_prod);
4487                 if (j != 0)
4488                         continue;
4489
4490                 REG_WR(bp, BAR_USTRORM_INTMEM +
4491                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
4492                        U64_LO(fp->rx_comp_mapping));
4493                 REG_WR(bp, BAR_USTRORM_INTMEM +
4494                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
4495                        U64_HI(fp->rx_comp_mapping));
4496         }
4497 }
4498
4499 static void bnx2x_init_tx_ring(struct bnx2x *bp)
4500 {
4501         int i, j;
4502
4503         for_each_tx_queue(bp, j) {
4504                 struct bnx2x_fastpath *fp = &bp->fp[j];
4505
4506                 for (i = 1; i <= NUM_TX_RINGS; i++) {
4507                         struct eth_tx_bd *tx_bd =
4508                                 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4509
4510                         tx_bd->addr_hi =
4511                                 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4512                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4513                         tx_bd->addr_lo =
4514                                 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4515                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4516                 }
4517
4518                 fp->tx_pkt_prod = 0;
4519                 fp->tx_pkt_cons = 0;
4520                 fp->tx_bd_prod = 0;
4521                 fp->tx_bd_cons = 0;
4522                 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4523                 fp->tx_pkt = 0;
4524         }
4525 }
4526
4527 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4528 {
4529         int func = BP_FUNC(bp);
4530
4531         spin_lock_init(&bp->spq_lock);
4532
4533         bp->spq_left = MAX_SPQ_PENDING;
4534         bp->spq_prod_idx = 0;
4535         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4536         bp->spq_prod_bd = bp->spq;
4537         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4538
4539         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4540                U64_LO(bp->spq_mapping));
4541         REG_WR(bp,
4542                XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
4543                U64_HI(bp->spq_mapping));
4544
4545         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
4546                bp->spq_prod_idx);
4547 }
4548
4549 static void bnx2x_init_context(struct bnx2x *bp)
4550 {
4551         int i;
4552
4553         for_each_queue(bp, i) {
4554                 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4555                 struct bnx2x_fastpath *fp = &bp->fp[i];
4556                 u8 cl_id = fp->cl_id;
4557                 u8 sb_id = FP_SB_ID(fp);
4558
4559                 context->ustorm_st_context.common.sb_index_numbers =
4560                                                 BNX2X_RX_SB_INDEX_NUM;
4561                 context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
4562                 context->ustorm_st_context.common.status_block_id = sb_id;
4563                 context->ustorm_st_context.common.flags =
4564                         (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT |
4565                          USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS);
4566                 context->ustorm_st_context.common.statistics_counter_id =
4567                                                 cl_id;
4568                 context->ustorm_st_context.common.mc_alignment_log_size =
4569                                                 BNX2X_RX_ALIGN_SHIFT;
4570                 context->ustorm_st_context.common.bd_buff_size =
4571                                                 bp->rx_buf_size;
4572                 context->ustorm_st_context.common.bd_page_base_hi =
4573                                                 U64_HI(fp->rx_desc_mapping);
4574                 context->ustorm_st_context.common.bd_page_base_lo =
4575                                                 U64_LO(fp->rx_desc_mapping);
4576                 if (!fp->disable_tpa) {
4577                         context->ustorm_st_context.common.flags |=
4578                                 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
4579                                  USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
4580                         context->ustorm_st_context.common.sge_buff_size =
4581                                 (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
4582                                          (u32)0xffff);
4583                         context->ustorm_st_context.common.sge_page_base_hi =
4584                                                 U64_HI(fp->rx_sge_mapping);
4585                         context->ustorm_st_context.common.sge_page_base_lo =
4586                                                 U64_LO(fp->rx_sge_mapping);
4587                 }
4588
4589                 context->ustorm_ag_context.cdu_usage =
4590                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4591                                                CDU_REGION_NUMBER_UCM_AG,
4592                                                ETH_CONNECTION_TYPE);
4593
4594                 context->xstorm_st_context.tx_bd_page_base_hi =
4595                                                 U64_HI(fp->tx_desc_mapping);
4596                 context->xstorm_st_context.tx_bd_page_base_lo =
4597                                                 U64_LO(fp->tx_desc_mapping);
4598                 context->xstorm_st_context.db_data_addr_hi =
4599                                                 U64_HI(fp->tx_prods_mapping);
4600                 context->xstorm_st_context.db_data_addr_lo =
4601                                                 U64_LO(fp->tx_prods_mapping);
4602                 context->xstorm_st_context.statistics_data = (fp->cl_id |
4603                                 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
4604                 context->cstorm_st_context.sb_index_number =
4605                                                 C_SB_ETH_TX_CQ_INDEX;
4606                 context->cstorm_st_context.status_block_id = sb_id;
4607
4608                 context->xstorm_ag_context.cdu_reserved =
4609                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4610                                                CDU_REGION_NUMBER_XCM_AG,
4611                                                ETH_CONNECTION_TYPE);
4612         }
4613 }
4614
4615 static void bnx2x_init_ind_table(struct bnx2x *bp)
4616 {
4617         int func = BP_FUNC(bp);
4618         int i;
4619
4620         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4621                 return;
4622
4623         DP(NETIF_MSG_IFUP,
4624            "Initializing indirection table  multi_mode %d\n", bp->multi_mode);
4625         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4626                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4627                         TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4628                         BP_CL_ID(bp) + (i % bp->num_rx_queues));
4629 }
4630
4631 static void bnx2x_set_client_config(struct bnx2x *bp)
4632 {
4633         struct tstorm_eth_client_config tstorm_client = {0};
4634         int port = BP_PORT(bp);
4635         int i;
4636
4637         tstorm_client.mtu = bp->dev->mtu;
4638         tstorm_client.config_flags =
4639                                 (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
4640                                  TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
4641 #ifdef BCM_VLAN
4642         if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
4643                 tstorm_client.config_flags |=
4644                                 TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
4645                 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4646         }
4647 #endif
4648
4649         if (bp->flags & TPA_ENABLE_FLAG) {
4650                 tstorm_client.max_sges_for_packet =
4651                         SGE_PAGE_ALIGN(tstorm_client.mtu) >> SGE_PAGE_SHIFT;
4652                 tstorm_client.max_sges_for_packet =
4653                         ((tstorm_client.max_sges_for_packet +
4654                           PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
4655                         PAGES_PER_SGE_SHIFT;
4656
4657                 tstorm_client.config_flags |=
4658                                 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
4659         }
4660
4661         for_each_queue(bp, i) {
4662                 tstorm_client.statistics_counter_id = bp->fp[i].cl_id;
4663
4664                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4665                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
4666                        ((u32 *)&tstorm_client)[0]);
4667                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4668                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
4669                        ((u32 *)&tstorm_client)[1]);
4670         }
4671
4672         DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
4673            ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
4674 }
4675
4676 static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4677 {
4678         struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4679         int mode = bp->rx_mode;
4680         int mask = (1 << BP_L_ID(bp));
4681         int func = BP_FUNC(bp);
4682         int i;
4683
4684         DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
4685
4686         switch (mode) {
4687         case BNX2X_RX_MODE_NONE: /* no Rx */
4688                 tstorm_mac_filter.ucast_drop_all = mask;
4689                 tstorm_mac_filter.mcast_drop_all = mask;
4690                 tstorm_mac_filter.bcast_drop_all = mask;
4691                 break;
4692         case BNX2X_RX_MODE_NORMAL:
4693                 tstorm_mac_filter.bcast_accept_all = mask;
4694                 break;
4695         case BNX2X_RX_MODE_ALLMULTI:
4696                 tstorm_mac_filter.mcast_accept_all = mask;
4697                 tstorm_mac_filter.bcast_accept_all = mask;
4698                 break;
4699         case BNX2X_RX_MODE_PROMISC:
4700                 tstorm_mac_filter.ucast_accept_all = mask;
4701                 tstorm_mac_filter.mcast_accept_all = mask;
4702                 tstorm_mac_filter.bcast_accept_all = mask;
4703                 break;
4704         default:
4705                 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4706                 break;
4707         }
4708
4709         for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4710                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4711                        TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
4712                        ((u32 *)&tstorm_mac_filter)[i]);
4713
4714 /*              DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4715                    ((u32 *)&tstorm_mac_filter)[i]); */
4716         }
4717
4718         if (mode != BNX2X_RX_MODE_NONE)
4719                 bnx2x_set_client_config(bp);
4720 }
4721
4722 static void bnx2x_init_internal_common(struct bnx2x *bp)
4723 {
4724         int i;
4725
4726         if (bp->flags & TPA_ENABLE_FLAG) {
4727                 struct tstorm_eth_tpa_exist tpa = {0};
4728
4729                 tpa.tpa_exist = 1;
4730
4731                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
4732                        ((u32 *)&tpa)[0]);
4733                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
4734                        ((u32 *)&tpa)[1]);
4735         }
4736
4737         /* Zero this manually as its initialization is
4738            currently missing in the initTool */
4739         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4740                 REG_WR(bp, BAR_USTRORM_INTMEM +
4741                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
4742 }
4743
4744 static void bnx2x_init_internal_port(struct bnx2x *bp)
4745 {
4746         int port = BP_PORT(bp);
4747
4748         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4749         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4750         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4751         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4752 }
4753
4754 /* Calculates the sum of vn_min_rates.
4755    It's needed for further normalizing of the min_rates.
4756    Returns:
4757      sum of vn_min_rates.
4758        or
4759      0 - if all the min_rates are 0.
4760      In the later case fainess algorithm should be deactivated.
4761      If not all min_rates are zero then those that are zeroes will be set to 1.
4762  */
4763 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
4764 {
4765         int all_zero = 1;
4766         int port = BP_PORT(bp);
4767         int vn;
4768
4769         bp->vn_weight_sum = 0;
4770         for (vn = VN_0; vn < E1HVN_MAX; vn++) {
4771                 int func = 2*vn + port;
4772                 u32 vn_cfg =
4773                         SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
4774                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
4775                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
4776
4777                 /* Skip hidden vns */
4778                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
4779                         continue;
4780
4781                 /* If min rate is zero - set it to 1 */
4782                 if (!vn_min_rate)
4783                         vn_min_rate = DEF_MIN_RATE;
4784                 else
4785                         all_zero = 0;
4786
4787                 bp->vn_weight_sum += vn_min_rate;
4788         }
4789
4790         /* ... only if all min rates are zeros - disable fairness */
4791         if (all_zero)
4792                 bp->vn_weight_sum = 0;
4793 }
4794
4795 static void bnx2x_init_internal_func(struct bnx2x *bp)
4796 {
4797         struct tstorm_eth_function_common_config tstorm_config = {0};
4798         struct stats_indication_flags stats_flags = {0};
4799         int port = BP_PORT(bp);
4800         int func = BP_FUNC(bp);
4801         int i, j;
4802         u32 offset;
4803         u16 max_agg_size;
4804
4805         if (is_multi(bp)) {
4806                 tstorm_config.config_flags = MULTI_FLAGS(bp);
4807                 tstorm_config.rss_result_mask = MULTI_MASK;
4808         }
4809         if (IS_E1HMF(bp))
4810                 tstorm_config.config_flags |=
4811                                 TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
4812
4813         tstorm_config.leading_client_id = BP_L_ID(bp);
4814
4815         REG_WR(bp, BAR_TSTRORM_INTMEM +
4816                TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4817                (*(u32 *)&tstorm_config));
4818
4819         bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4820         bnx2x_set_storm_rx_mode(bp);
4821
4822         for_each_queue(bp, i) {
4823                 u8 cl_id = bp->fp[i].cl_id;
4824
4825                 /* reset xstorm per client statistics */
4826                 offset = BAR_XSTRORM_INTMEM +
4827                          XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
4828                 for (j = 0;
4829                      j < sizeof(struct xstorm_per_client_stats) / 4; j++)
4830                         REG_WR(bp, offset + j*4, 0);
4831
4832                 /* reset tstorm per client statistics */
4833                 offset = BAR_TSTRORM_INTMEM +
4834                          TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
4835                 for (j = 0;
4836                      j < sizeof(struct tstorm_per_client_stats) / 4; j++)
4837                         REG_WR(bp, offset + j*4, 0);
4838
4839                 /* reset ustorm per client statistics */
4840                 offset = BAR_USTRORM_INTMEM +
4841                          USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
4842                 for (j = 0;
4843                      j < sizeof(struct ustorm_per_client_stats) / 4; j++)
4844                         REG_WR(bp, offset + j*4, 0);
4845         }
4846
4847         /* Init statistics related context */
4848         stats_flags.collect_eth = 1;
4849
4850         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4851                ((u32 *)&stats_flags)[0]);
4852         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4853                ((u32 *)&stats_flags)[1]);
4854
4855         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4856                ((u32 *)&stats_flags)[0]);
4857         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4858                ((u32 *)&stats_flags)[1]);
4859
4860         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
4861                ((u32 *)&stats_flags)[0]);
4862         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
4863                ((u32 *)&stats_flags)[1]);
4864
4865         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4866                ((u32 *)&stats_flags)[0]);
4867         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4868                ((u32 *)&stats_flags)[1]);
4869
4870         REG_WR(bp, BAR_XSTRORM_INTMEM +
4871                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4872                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4873         REG_WR(bp, BAR_XSTRORM_INTMEM +
4874                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4875                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4876
4877         REG_WR(bp, BAR_TSTRORM_INTMEM +
4878                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4879                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4880         REG_WR(bp, BAR_TSTRORM_INTMEM +
4881                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4882                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4883
4884         REG_WR(bp, BAR_USTRORM_INTMEM +
4885                USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4886                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4887         REG_WR(bp, BAR_USTRORM_INTMEM +
4888                USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4889                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4890
4891         if (CHIP_IS_E1H(bp)) {
4892                 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4893                         IS_E1HMF(bp));
4894                 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4895                         IS_E1HMF(bp));
4896                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4897                         IS_E1HMF(bp));
4898                 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4899                         IS_E1HMF(bp));
4900
4901                 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
4902                          bp->e1hov);
4903         }
4904
4905         /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
4906         max_agg_size =
4907                 min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) *
4908                           SGE_PAGE_SIZE * PAGES_PER_SGE),
4909                     (u32)0xffff);
4910         for_each_rx_queue(bp, i) {
4911                 struct bnx2x_fastpath *fp = &bp->fp[i];
4912
4913                 REG_WR(bp, BAR_USTRORM_INTMEM +
4914                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
4915                        U64_LO(fp->rx_comp_mapping));
4916                 REG_WR(bp, BAR_USTRORM_INTMEM +
4917                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4918                        U64_HI(fp->rx_comp_mapping));
4919
4920                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4921                          USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4922                          max_agg_size);
4923         }
4924
4925         /* dropless flow control */
4926         if (CHIP_IS_E1H(bp)) {
4927                 struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};
4928
4929                 rx_pause.bd_thr_low = 250;
4930                 rx_pause.cqe_thr_low = 250;
4931                 rx_pause.cos = 1;
4932                 rx_pause.sge_thr_low = 0;
4933                 rx_pause.bd_thr_high = 350;
4934                 rx_pause.cqe_thr_high = 350;
4935                 rx_pause.sge_thr_high = 0;
4936
4937                 for_each_rx_queue(bp, i) {
4938                         struct bnx2x_fastpath *fp = &bp->fp[i];
4939
4940                         if (!fp->disable_tpa) {
4941                                 rx_pause.sge_thr_low = 150;
4942                                 rx_pause.sge_thr_high = 250;
4943                         }
4944
4945
4946                         offset = BAR_USTRORM_INTMEM +
4947                                  USTORM_ETH_RING_PAUSE_DATA_OFFSET(port,
4948                                                                    fp->cl_id);
4949                         for (j = 0;
4950                              j < sizeof(struct ustorm_eth_rx_pause_data_e1h)/4;
4951                              j++)
4952                                 REG_WR(bp, offset + j*4,
4953                                        ((u32 *)&rx_pause)[j]);
4954                 }
4955         }
4956
4957         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
4958
4959         /* Init rate shaping and fairness contexts */
4960         if (IS_E1HMF(bp)) {
4961                 int vn;
4962
4963                 /* During init there is no active link
4964                    Until link is up, set link rate to 10Gbps */
4965                 bp->link_vars.line_speed = SPEED_10000;
4966                 bnx2x_init_port_minmax(bp);
4967
4968                 bnx2x_calc_vn_weight_sum(bp);
4969
4970                 for (vn = VN_0; vn < E1HVN_MAX; vn++)
4971                         bnx2x_init_vn_minmax(bp, 2*vn + port);
4972
4973                 /* Enable rate shaping and fairness */
4974                 bp->cmng.flags.cmng_enables =
4975                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
4976                 if (bp->vn_weight_sum)
4977                         bp->cmng.flags.cmng_enables |=
4978                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
4979                 else
4980                         DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
4981                            "  fairness will be disabled\n");
4982         } else {
4983                 /* rate shaping and fairness are disabled */
4984                 DP(NETIF_MSG_IFUP,
4985                    "single function mode  minmax will be disabled\n");
4986         }
4987
4988
4989         /* Store it to internal memory */
4990         if (bp->port.pmf)
4991                 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
4992                         REG_WR(bp, BAR_XSTRORM_INTMEM +
4993                                XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
4994                                ((u32 *)(&bp->cmng))[i]);
4995 }
4996
4997 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4998 {
4999         switch (load_code) {
5000         case FW_MSG_CODE_DRV_LOAD_COMMON:
5001                 bnx2x_init_internal_common(bp);
5002                 /* no break */
5003
5004         case FW_MSG_CODE_DRV_LOAD_PORT:
5005                 bnx2x_init_internal_port(bp);
5006                 /* no break */
5007
5008         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5009                 bnx2x_init_internal_func(bp);
5010                 break;
5011
5012         default:
5013                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5014                 break;
5015         }
5016 }
5017
5018 static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5019 {
5020         int i;
5021
5022         for_each_queue(bp, i) {
5023                 struct bnx2x_fastpath *fp = &bp->fp[i];
5024
5025                 fp->bp = bp;
5026                 fp->state = BNX2X_FP_STATE_CLOSED;
5027                 fp->index = i;
5028                 fp->cl_id = BP_L_ID(bp) + i;
5029                 fp->sb_id = fp->cl_id;
5030                 DP(NETIF_MSG_IFUP,
5031                    "bnx2x_init_sb(%p,%p) index %d  cl_id %d  sb %d\n",
5032                    bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
5033                 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
5034                               FP_SB_ID(fp));
5035                 bnx2x_update_fpsb_idx(fp);
5036         }
5037
5038         bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
5039                           DEF_SB_ID);
5040         bnx2x_update_dsb_idx(bp);
5041         bnx2x_update_coalesce(bp);
5042         bnx2x_init_rx_rings(bp);
5043         bnx2x_init_tx_ring(bp);
5044         bnx2x_init_sp_ring(bp);
5045         bnx2x_init_context(bp);
5046         bnx2x_init_internal(bp, load_code);
5047         bnx2x_init_ind_table(bp);
5048         bnx2x_stats_init(bp);
5049
5050         /* At this point, we are ready for interrupts */
5051         atomic_set(&bp->intr_sem, 0);
5052
5053         /* flush all before enabling interrupts */
5054         mb();
5055         mmiowb();
5056
5057         bnx2x_int_enable(bp);
5058 }
5059
5060 /* end of nic init */
5061
5062 /*
5063  * gzip service functions
5064  */
5065
5066 static int bnx2x_gunzip_init(struct bnx2x *bp)
5067 {
5068         bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
5069                                               &bp->gunzip_mapping);
5070         if (bp->gunzip_buf  == NULL)
5071                 goto gunzip_nomem1;
5072
5073         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5074         if (bp->strm  == NULL)
5075                 goto gunzip_nomem2;
5076
5077         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
5078                                       GFP_KERNEL);
5079         if (bp->strm->workspace == NULL)
5080                 goto gunzip_nomem3;
5081
5082         return 0;
5083
5084 gunzip_nomem3:
5085         kfree(bp->strm);
5086         bp->strm = NULL;
5087
5088 gunzip_nomem2:
5089         pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
5090                             bp->gunzip_mapping);
5091         bp->gunzip_buf = NULL;
5092
5093 gunzip_nomem1:
5094         printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
5095                " un-compression\n", bp->dev->name);
5096         return -ENOMEM;
5097 }
5098
5099 static void bnx2x_gunzip_end(struct bnx2x *bp)
5100 {
5101         kfree(bp->strm->workspace);
5102
5103         kfree(bp->strm);
5104         bp->strm = NULL;
5105
5106         if (bp->gunzip_buf) {
5107                 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
5108                                     bp->gunzip_mapping);
5109                 bp->gunzip_buf = NULL;
5110         }
5111 }
5112
5113 static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
5114 {
5115         int n, rc;
5116
5117         /* check gzip header */
5118         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
5119                 return -EINVAL;
5120
5121         n = 10;
5122
5123 #define FNAME                           0x8
5124
5125         if (zbuf[3] & FNAME)
5126                 while ((zbuf[n++] != 0) && (n < len));
5127
5128         bp->strm->next_in = zbuf + n;
5129         bp->strm->avail_in = len - n;
5130         bp->strm->next_out = bp->gunzip_buf;
5131         bp->strm->avail_out = FW_BUF_SIZE;
5132
5133         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5134         if (rc != Z_OK)
5135                 return rc;
5136
5137         rc = zlib_inflate(bp->strm, Z_FINISH);
5138         if ((rc != Z_OK) && (rc != Z_STREAM_END))
5139                 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
5140                        bp->dev->name, bp->strm->msg);
5141
5142         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5143         if (bp->gunzip_outlen & 0x3)
5144                 printk(KERN_ERR PFX "%s: Firmware decompression error:"
5145                                     " gunzip_outlen (%d) not aligned\n",
5146                        bp->dev->name, bp->gunzip_outlen);
5147         bp->gunzip_outlen >>= 2;
5148
5149         zlib_inflateEnd(bp->strm);
5150
5151         if (rc == Z_STREAM_END)
5152                 return 0;
5153
5154         return rc;
5155 }
5156
5157 /* nic load/unload */
5158
5159 /*
5160  * General service functions
5161  */
5162
5163 /* send a NIG loopback debug packet */
5164 static void bnx2x_lb_pckt(struct bnx2x *bp)
5165 {
5166         u32 wb_write[3];
5167
5168         /* Ethernet source and destination addresses */
5169         wb_write[0] = 0x55555555;
5170         wb_write[1] = 0x55555555;
5171         wb_write[2] = 0x20;             /* SOP */
5172         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5173
5174         /* NON-IP protocol */
5175         wb_write[0] = 0x09000000;
5176         wb_write[1] = 0x55555555;
5177         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
5178         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5179 }
5180
5181 /* some of the internal memories
5182  * are not directly readable from the driver
5183  * to test them we send debug packets
5184  */
5185 static int bnx2x_int_mem_test(struct bnx2x *bp)
5186 {
5187         int factor;
5188         int count, i;
5189         u32 val = 0;
5190
5191         if (CHIP_REV_IS_FPGA(bp))
5192                 factor = 120;
5193         else if (CHIP_REV_IS_EMUL(bp))
5194                 factor = 200;
5195         else
5196                 factor = 1;
5197
5198         DP(NETIF_MSG_HW, "start part1\n");
5199
5200         /* Disable inputs of parser neighbor blocks */
5201         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5202         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5203         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5204         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5205
5206         /*  Write 0 to parser credits for CFC search request */
5207         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5208
5209         /* send Ethernet packet */
5210         bnx2x_lb_pckt(bp);
5211
5212         /* TODO do i reset NIG statistic? */
5213         /* Wait until NIG register shows 1 packet of size 0x10 */
5214         count = 1000 * factor;
5215         while (count) {
5216
5217                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5218                 val = *bnx2x_sp(bp, wb_data[0]);
5219                 if (val == 0x10)
5220                         break;
5221
5222                 msleep(10);
5223                 count--;
5224         }
5225         if (val != 0x10) {
5226                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5227                 return -1;
5228         }
5229
5230         /* Wait until PRS register shows 1 packet */
5231         count = 1000 * factor;
5232         while (count) {
5233                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5234                 if (val == 1)
5235                         break;
5236
5237                 msleep(10);
5238                 count--;
5239         }
5240         if (val != 0x1) {
5241                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5242                 return -2;
5243         }
5244
5245         /* Reset and init BRB, PRS */
5246         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5247         msleep(50);
5248         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5249         msleep(50);
5250         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5251         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5252
5253         DP(NETIF_MSG_HW, "part2\n");
5254
5255         /* Disable inputs of parser neighbor blocks */
5256         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5257         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5258         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5259         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5260
5261         /* Write 0 to parser credits for CFC search request */
5262         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5263
5264         /* send 10 Ethernet packets */
5265         for (i = 0; i < 10; i++)
5266                 bnx2x_lb_pckt(bp);
5267
5268         /* Wait until NIG register shows 10 + 1
5269            packets of size 11*0x10 = 0xb0 */
5270         count = 1000 * factor;
5271         while (count) {
5272
5273                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5274                 val = *bnx2x_sp(bp, wb_data[0]);
5275                 if (val == 0xb0)
5276                         break;
5277
5278                 msleep(10);
5279                 count--;
5280         }
5281         if (val != 0xb0) {
5282                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5283                 return -3;
5284         }
5285
5286         /* Wait until PRS register shows 2 packets */
5287         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5288         if (val != 2)
5289                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5290
5291         /* Write 1 to parser credits for CFC search request */
5292         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5293
5294         /* Wait until PRS register shows 3 packets */
5295         msleep(10 * factor);
5296         /* Wait until NIG register shows 1 packet of size 0x10 */
5297         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5298         if (val != 3)
5299                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5300
5301         /* clear NIG EOP FIFO */
5302         for (i = 0; i < 11; i++)
5303                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5304         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5305         if (val != 1) {
5306                 BNX2X_ERR("clear of NIG failed\n");
5307                 return -4;
5308         }
5309
5310         /* Reset and init BRB, PRS, NIG */
5311         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5312         msleep(50);
5313         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5314         msleep(50);
5315         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5316         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5317 #ifndef BCM_ISCSI
5318         /* set NIC mode */
5319         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5320 #endif
5321
5322         /* Enable inputs of parser neighbor blocks */
5323         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5324         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5325         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5326         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5327
5328         DP(NETIF_MSG_HW, "done\n");
5329
5330         return 0; /* OK */
5331 }
5332
5333 static void enable_blocks_attention(struct bnx2x *bp)
5334 {
5335         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5336         REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5337         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5338         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5339         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5340         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5341         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5342         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5343         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5344 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5345 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5346         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5347         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5348         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5349 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5350 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5351         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5352         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5353         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5354         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5355 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5356 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5357         if (CHIP_REV_IS_FPGA(bp))
5358                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5359         else
5360                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5361         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5362         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5363         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5364 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5365 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5366         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5367         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5368 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5369         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
5370 }
5371
5372
5373 static void bnx2x_reset_common(struct bnx2x *bp)
5374 {
5375         /* reset_common */
5376         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5377                0xd3ffff7f);
5378         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
5379 }
5380
5381 static int bnx2x_init_common(struct bnx2x *bp)
5382 {
5383         u32 val, i;
5384
5385         DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_FUNC(bp));
5386
5387         bnx2x_reset_common(bp);
5388         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5389         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5390
5391         bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
5392         if (CHIP_IS_E1H(bp))
5393                 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5394
5395         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5396         msleep(30);
5397         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5398
5399         bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
5400         if (CHIP_IS_E1(bp)) {
5401                 /* enable HW interrupt from PXP on USDM overflow
5402                    bit 16 on INT_MASK_0 */
5403                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5404         }
5405
5406         bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
5407         bnx2x_init_pxp(bp);
5408
5409 #ifdef __BIG_ENDIAN
5410         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5411         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5412         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5413         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5414         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5415         /* make sure this value is 0 */
5416         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5417
5418 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5419         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5420         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5421         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5422         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5423 #endif
5424
5425         REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5426 #ifdef BCM_ISCSI
5427         REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5428         REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5429         REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5430 #endif
5431
5432         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5433                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5434
5435         /* let the HW do it's magic ... */
5436         msleep(100);
5437         /* finish PXP init */
5438         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5439         if (val != 1) {
5440                 BNX2X_ERR("PXP2 CFG failed\n");
5441                 return -EBUSY;
5442         }
5443         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5444         if (val != 1) {
5445                 BNX2X_ERR("PXP2 RD_INIT failed\n");
5446                 return -EBUSY;
5447         }
5448
5449         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5450         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5451
5452         bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
5453
5454         /* clean the DMAE memory */
5455         bp->dmae_ready = 1;
5456         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5457
5458         bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
5459         bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
5460         bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
5461         bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
5462
5463         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5464         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5465         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5466         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5467
5468         bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5469         /* soft reset pulse */
5470         REG_WR(bp, QM_REG_SOFT_RESET, 1);
5471         REG_WR(bp, QM_REG_SOFT_RESET, 0);
5472
5473 #ifdef BCM_ISCSI
5474         bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
5475 #endif
5476
5477         bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
5478         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
5479         if (!CHIP_REV_IS_SLOW(bp)) {
5480                 /* enable hw interrupt from doorbell Q */
5481                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5482         }
5483
5484         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5485         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5486         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5487         /* set NIC mode */
5488         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5489         if (CHIP_IS_E1H(bp))
5490                 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5491
5492         bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
5493         bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
5494         bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5495         bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5496
5497         if (CHIP_IS_E1H(bp)) {
5498                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5499                                 STORM_INTMEM_SIZE_E1H/2);
5500                 bnx2x_init_fill(bp,
5501                                 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5502                                 0, STORM_INTMEM_SIZE_E1H/2);
5503                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5504                                 STORM_INTMEM_SIZE_E1H/2);
5505                 bnx2x_init_fill(bp,
5506                                 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5507                                 0, STORM_INTMEM_SIZE_E1H/2);
5508                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5509                                 STORM_INTMEM_SIZE_E1H/2);
5510                 bnx2x_init_fill(bp,
5511                                 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5512                                 0, STORM_INTMEM_SIZE_E1H/2);
5513                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5514                                 STORM_INTMEM_SIZE_E1H/2);
5515                 bnx2x_init_fill(bp,
5516                                 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5517                                 0, STORM_INTMEM_SIZE_E1H/2);
5518         } else { /* E1 */
5519                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5520                                 STORM_INTMEM_SIZE_E1);
5521                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5522                                 STORM_INTMEM_SIZE_E1);
5523                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5524                                 STORM_INTMEM_SIZE_E1);
5525                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5526                                 STORM_INTMEM_SIZE_E1);
5527         }
5528
5529         bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5530         bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
5531         bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
5532         bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
5533
5534         /* sync semi rtc */
5535         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5536                0x80000000);
5537         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5538                0x80000000);
5539
5540         bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
5541         bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
5542         bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
5543
5544         REG_WR(bp, SRC_REG_SOFT_RST, 1);
5545         for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5546                 REG_WR(bp, i, 0xc0cac01a);
5547                 /* TODO: replace with something meaningful */
5548         }
5549         bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
5550         REG_WR(bp, SRC_REG_SOFT_RST, 0);
5551
5552         if (sizeof(union cdu_context) != 1024)
5553                 /* we currently assume that a context is 1024 bytes */
5554                 printk(KERN_ALERT PFX "please adjust the size of"
5555                        " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5556
5557         bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
5558         val = (4 << 24) + (0 << 12) + 1024;
5559         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5560         if (CHIP_IS_E1(bp)) {
5561                 /* !!! fix pxp client crdit until excel update */
5562                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5563                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
5564         }
5565
5566         bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
5567         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5568         /* enable context validation interrupt from CFC */
5569         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5570
5571         /* set the thresholds to prevent CFC/CDU race */
5572         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5573
5574         bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
5575         bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
5576
5577         /* PXPCS COMMON comes here */
5578         /* Reset PCIE errors for debug */
5579         REG_WR(bp, 0x2814, 0xffffffff);
5580         REG_WR(bp, 0x3820, 0xffffffff);
5581
5582         /* EMAC0 COMMON comes here */
5583         /* EMAC1 COMMON comes here */
5584         /* DBU COMMON comes here */
5585         /* DBG COMMON comes here */
5586
5587         bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
5588         if (CHIP_IS_E1H(bp)) {
5589                 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
5590                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
5591         }
5592
5593         if (CHIP_REV_IS_SLOW(bp))
5594                 msleep(200);
5595
5596         /* finish CFC init */
5597         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5598         if (val != 1) {
5599                 BNX2X_ERR("CFC LL_INIT failed\n");
5600                 return -EBUSY;
5601         }
5602         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5603         if (val != 1) {
5604                 BNX2X_ERR("CFC AC_INIT failed\n");
5605                 return -EBUSY;
5606         }
5607         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5608         if (val != 1) {
5609                 BNX2X_ERR("CFC CAM_INIT failed\n");
5610                 return -EBUSY;
5611         }
5612         REG_WR(bp, CFC_REG_DEBUG0, 0);
5613
5614         /* read NIG statistic
5615            to see if this is our first up since powerup */
5616         bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5617         val = *bnx2x_sp(bp, wb_data[0]);
5618
5619         /* do internal memory self test */
5620         if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
5621                 BNX2X_ERR("internal mem self test failed\n");
5622                 return -EBUSY;
5623         }
5624
5625         switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5626         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
5627         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5628                 /* Fan failure is indicated by SPIO 5 */
5629                 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5630                                MISC_REGISTERS_SPIO_INPUT_HI_Z);
5631
5632                 /* set to active low mode */
5633                 val = REG_RD(bp, MISC_REG_SPIO_INT);
5634                 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5635                                         MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5636                 REG_WR(bp, MISC_REG_SPIO_INT, val);
5637
5638                 /* enable interrupt to signal the IGU */
5639                 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5640                 val |= (1 << MISC_REGISTERS_SPIO_5);
5641                 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5642                 break;
5643
5644         default:
5645                 break;
5646         }
5647
5648         /* clear PXP2 attentions */
5649         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5650
5651         enable_blocks_attention(bp);
5652
5653         if (!BP_NOMCP(bp)) {
5654                 bnx2x_acquire_phy_lock(bp);
5655                 bnx2x_common_init_phy(bp, bp->common.shmem_base);
5656                 bnx2x_release_phy_lock(bp);
5657         } else
5658                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5659
5660         return 0;
5661 }
5662
5663 static int bnx2x_init_port(struct bnx2x *bp)
5664 {
5665         int port = BP_PORT(bp);
5666         u32 low, high;
5667         u32 val;
5668
5669         DP(BNX2X_MSG_MCP, "starting port init  port %x\n", port);
5670
5671         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5672
5673         /* Port PXP comes here */
5674         /* Port PXP2 comes here */
5675 #ifdef BCM_ISCSI
5676         /* Port0  1
5677          * Port1  385 */
5678         i++;
5679         wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5680         wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5681         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5682         REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5683
5684         /* Port0  2
5685          * Port1  386 */
5686         i++;
5687         wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5688         wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5689         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5690         REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5691
5692         /* Port0  3
5693          * Port1  387 */
5694         i++;
5695         wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5696         wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5697         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5698         REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5699 #endif
5700         /* Port CMs come here */
5701         bnx2x_init_block(bp, (port ? XCM_PORT1_START : XCM_PORT0_START),
5702                              (port ? XCM_PORT1_END : XCM_PORT0_END));
5703
5704         /* Port QM comes here */
5705 #ifdef BCM_ISCSI
5706         REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5707         REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5708
5709         bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
5710                              func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
5711 #endif
5712         /* Port DQ comes here */
5713
5714         bnx2x_init_block(bp, (port ? BRB1_PORT1_START : BRB1_PORT0_START),
5715                              (port ? BRB1_PORT1_END : BRB1_PORT0_END));
5716         if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) {
5717                 /* no pause for emulation and FPGA */
5718                 low = 0;
5719                 high = 513;
5720         } else {
5721                 if (IS_E1HMF(bp))
5722                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5723                 else if (bp->dev->mtu > 4096) {
5724                         if (bp->flags & ONE_PORT_FLAG)
5725                                 low = 160;
5726                         else {
5727                                 val = bp->dev->mtu;
5728                                 /* (24*1024 + val*4)/256 */
5729                                 low = 96 + (val/64) + ((val % 64) ? 1 : 0);
5730                         }
5731                 } else
5732                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5733                 high = low + 56;        /* 14*1024/256 */
5734         }
5735         REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5736         REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
5737
5738
5739         /* Port PRS comes here */
5740         /* Port TSDM comes here */
5741         /* Port CSDM comes here */
5742         /* Port USDM comes here */
5743         /* Port XSDM comes here *