bnx2x: Per queue statistics
[linux-2.6.git] / drivers / net / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2009 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>  /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/bitops.h>
35 #include <linux/irq.h>
36 #include <linux/delay.h>
37 #include <asm/byteorder.h>
38 #include <linux/time.h>
39 #include <linux/ethtool.h>
40 #include <linux/mii.h>
41 #include <linux/if_vlan.h>
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
51 #include <linux/io.h>
52
53 #include "bnx2x_reg.h"
54 #include "bnx2x_fw_defs.h"
55 #include "bnx2x_hsi.h"
56 #include "bnx2x_link.h"
57 #include "bnx2x.h"
58 #include "bnx2x_init.h"
59
60 #define DRV_MODULE_VERSION      "1.45.26"
61 #define DRV_MODULE_RELDATE      "2009/01/26"
62 #define BNX2X_BC_VER            0x040200
63
64 /* Time in jiffies before concluding the transmitter is hung */
65 #define TX_TIMEOUT              (5*HZ)
66
67 static char version[] __devinitdata =
68         "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
69         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70
71 MODULE_AUTHOR("Eliezer Tamir");
72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION);
75
76 static int multi_mode = 1;
77 module_param(multi_mode, int, 0);
78
79 static int disable_tpa;
80 static int poll;
81 static int debug;
82 static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
83
84 module_param(disable_tpa, int, 0);
85
86 static int int_mode;
87 module_param(int_mode, int, 0);
88 MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)");
89
90 module_param(poll, int, 0);
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
93 MODULE_PARM_DESC(poll, "use polling (for debug)");
94 MODULE_PARM_DESC(debug, "default debug msglevel");
95
96 static struct workqueue_struct *bnx2x_wq;
97
98 enum bnx2x_board_type {
99         BCM57710 = 0,
100         BCM57711 = 1,
101         BCM57711E = 2,
102 };
103
104 /* indexed by board_type, above */
105 static struct {
106         char *name;
107 } board_info[] __devinitdata = {
108         { "Broadcom NetXtreme II BCM57710 XGb" },
109         { "Broadcom NetXtreme II BCM57711 XGb" },
110         { "Broadcom NetXtreme II BCM57711E XGb" }
111 };
112
113
114 static const struct pci_device_id bnx2x_pci_tbl[] = {
115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
121         { 0 }
122 };
123
124 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
125
126 /****************************************************************************
127 * General service functions
128 ****************************************************************************/
129
130 /* used only at init
131  * locking is done by mcp
132  */
133 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
134 {
135         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
136         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
137         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
138                                PCICFG_VENDOR_ID_OFFSET);
139 }
140
141 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
142 {
143         u32 val;
144
145         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
146         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
147         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
148                                PCICFG_VENDOR_ID_OFFSET);
149
150         return val;
151 }
152
153 static const u32 dmae_reg_go_c[] = {
154         DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
155         DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
156         DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
157         DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
158 };
159
160 /* copy command into DMAE command memory and set DMAE command go */
161 static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
162                             int idx)
163 {
164         u32 cmd_offset;
165         int i;
166
167         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
168         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
169                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
170
171                 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
172                    idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
173         }
174         REG_WR(bp, dmae_reg_go_c[idx], 1);
175 }
176
177 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
178                       u32 len32)
179 {
180         struct dmae_command *dmae = &bp->init_dmae;
181         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
182         int cnt = 200;
183
184         if (!bp->dmae_ready) {
185                 u32 *data = bnx2x_sp(bp, wb_data[0]);
186
187                 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
188                    "  using indirect\n", dst_addr, len32);
189                 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
190                 return;
191         }
192
193         mutex_lock(&bp->dmae_mutex);
194
195         memset(dmae, 0, sizeof(struct dmae_command));
196
197         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
198                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
199                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
200 #ifdef __BIG_ENDIAN
201                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
202 #else
203                         DMAE_CMD_ENDIANITY_DW_SWAP |
204 #endif
205                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
206                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
207         dmae->src_addr_lo = U64_LO(dma_addr);
208         dmae->src_addr_hi = U64_HI(dma_addr);
209         dmae->dst_addr_lo = dst_addr >> 2;
210         dmae->dst_addr_hi = 0;
211         dmae->len = len32;
212         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
213         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
214         dmae->comp_val = DMAE_COMP_VAL;
215
216         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
217            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
218                     "dst_addr [%x:%08x (%08x)]\n"
219            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
220            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
221            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
222            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
223         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
224            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
225            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
226
227         *wb_comp = 0;
228
229         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
230
231         udelay(5);
232
233         while (*wb_comp != DMAE_COMP_VAL) {
234                 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
235
236                 if (!cnt) {
237                         BNX2X_ERR("dmae timeout!\n");
238                         break;
239                 }
240                 cnt--;
241                 /* adjust delay for emulation/FPGA */
242                 if (CHIP_REV_IS_SLOW(bp))
243                         msleep(100);
244                 else
245                         udelay(5);
246         }
247
248         mutex_unlock(&bp->dmae_mutex);
249 }
250
251 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
252 {
253         struct dmae_command *dmae = &bp->init_dmae;
254         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
255         int cnt = 200;
256
257         if (!bp->dmae_ready) {
258                 u32 *data = bnx2x_sp(bp, wb_data[0]);
259                 int i;
260
261                 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x  len32 %d)"
262                    "  using indirect\n", src_addr, len32);
263                 for (i = 0; i < len32; i++)
264                         data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
265                 return;
266         }
267
268         mutex_lock(&bp->dmae_mutex);
269
270         memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
271         memset(dmae, 0, sizeof(struct dmae_command));
272
273         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
274                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
275                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
276 #ifdef __BIG_ENDIAN
277                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
278 #else
279                         DMAE_CMD_ENDIANITY_DW_SWAP |
280 #endif
281                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
282                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
283         dmae->src_addr_lo = src_addr >> 2;
284         dmae->src_addr_hi = 0;
285         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
286         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
287         dmae->len = len32;
288         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
289         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
290         dmae->comp_val = DMAE_COMP_VAL;
291
292         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
293            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
294                     "dst_addr [%x:%08x (%08x)]\n"
295            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
296            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
297            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
298            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
299
300         *wb_comp = 0;
301
302         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
303
304         udelay(5);
305
306         while (*wb_comp != DMAE_COMP_VAL) {
307
308                 if (!cnt) {
309                         BNX2X_ERR("dmae timeout!\n");
310                         break;
311                 }
312                 cnt--;
313                 /* adjust delay for emulation/FPGA */
314                 if (CHIP_REV_IS_SLOW(bp))
315                         msleep(100);
316                 else
317                         udelay(5);
318         }
319         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
320            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
321            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
322
323         mutex_unlock(&bp->dmae_mutex);
324 }
325
326 /* used only for slowpath so not inlined */
327 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
328 {
329         u32 wb_write[2];
330
331         wb_write[0] = val_hi;
332         wb_write[1] = val_lo;
333         REG_WR_DMAE(bp, reg, wb_write, 2);
334 }
335
336 #ifdef USE_WB_RD
337 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
338 {
339         u32 wb_data[2];
340
341         REG_RD_DMAE(bp, reg, wb_data, 2);
342
343         return HILO_U64(wb_data[0], wb_data[1]);
344 }
345 #endif
346
347 static int bnx2x_mc_assert(struct bnx2x *bp)
348 {
349         char last_idx;
350         int i, rc = 0;
351         u32 row0, row1, row2, row3;
352
353         /* XSTORM */
354         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
355                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
356         if (last_idx)
357                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
358
359         /* print the asserts */
360         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
361
362                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
363                               XSTORM_ASSERT_LIST_OFFSET(i));
364                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
365                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
366                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
367                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
368                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
369                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
370
371                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
372                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
373                                   " 0x%08x 0x%08x 0x%08x\n",
374                                   i, row3, row2, row1, row0);
375                         rc++;
376                 } else {
377                         break;
378                 }
379         }
380
381         /* TSTORM */
382         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
383                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
384         if (last_idx)
385                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
386
387         /* print the asserts */
388         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
389
390                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
391                               TSTORM_ASSERT_LIST_OFFSET(i));
392                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
393                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
394                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
395                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
396                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
397                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
398
399                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
400                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
401                                   " 0x%08x 0x%08x 0x%08x\n",
402                                   i, row3, row2, row1, row0);
403                         rc++;
404                 } else {
405                         break;
406                 }
407         }
408
409         /* CSTORM */
410         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
411                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
412         if (last_idx)
413                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
414
415         /* print the asserts */
416         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
417
418                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
419                               CSTORM_ASSERT_LIST_OFFSET(i));
420                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
421                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
422                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
423                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
424                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
425                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
426
427                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
428                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
429                                   " 0x%08x 0x%08x 0x%08x\n",
430                                   i, row3, row2, row1, row0);
431                         rc++;
432                 } else {
433                         break;
434                 }
435         }
436
437         /* USTORM */
438         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
439                            USTORM_ASSERT_LIST_INDEX_OFFSET);
440         if (last_idx)
441                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
442
443         /* print the asserts */
444         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
445
446                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
447                               USTORM_ASSERT_LIST_OFFSET(i));
448                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
449                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
450                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
451                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
452                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
453                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
454
455                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
456                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
457                                   " 0x%08x 0x%08x 0x%08x\n",
458                                   i, row3, row2, row1, row0);
459                         rc++;
460                 } else {
461                         break;
462                 }
463         }
464
465         return rc;
466 }
467
468 static void bnx2x_fw_dump(struct bnx2x *bp)
469 {
470         u32 mark, offset;
471         u32 data[9];
472         int word;
473
474         mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
475         mark = ((mark + 0x3) & ~0x3);
476         printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
477
478         for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
479                 for (word = 0; word < 8; word++)
480                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
481                                                   offset + 4*word));
482                 data[8] = 0x0;
483                 printk(KERN_CONT "%s", (char *)data);
484         }
485         for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
486                 for (word = 0; word < 8; word++)
487                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
488                                                   offset + 4*word));
489                 data[8] = 0x0;
490                 printk(KERN_CONT "%s", (char *)data);
491         }
492         printk("\n" KERN_ERR PFX "end of fw dump\n");
493 }
494
495 static void bnx2x_panic_dump(struct bnx2x *bp)
496 {
497         int i;
498         u16 j, start, end;
499
500         bp->stats_state = STATS_STATE_DISABLED;
501         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
502
503         BNX2X_ERR("begin crash dump -----------------\n");
504
505         for_each_queue(bp, i) {
506                 struct bnx2x_fastpath *fp = &bp->fp[i];
507                 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
508
509                 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
510                           "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)\n",
511                           i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
512                           fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
513                 BNX2X_ERR("          rx_bd_prod(%x)  rx_bd_cons(%x)"
514                           "  *rx_bd_cons_sb(%x)  rx_comp_prod(%x)"
515                           "  rx_comp_cons(%x)  *rx_cons_sb(%x)\n",
516                           fp->rx_bd_prod, fp->rx_bd_cons,
517                           le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
518                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
519                 BNX2X_ERR("          rx_sge_prod(%x)  last_max_sge(%x)"
520                           "  fp_c_idx(%x)  *sb_c_idx(%x)  fp_u_idx(%x)"
521                           "  *sb_u_idx(%x)  bd data(%x,%x)\n",
522                           fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx,
523                           fp->status_blk->c_status_block.status_block_index,
524                           fp->fp_u_idx,
525                           fp->status_blk->u_status_block.status_block_index,
526                           hw_prods->packets_prod, hw_prods->bds_prod);
527
528                 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
529                 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
530                 for (j = start; j < end; j++) {
531                         struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
532
533                         BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
534                                   sw_bd->skb, sw_bd->first_bd);
535                 }
536
537                 start = TX_BD(fp->tx_bd_cons - 10);
538                 end = TX_BD(fp->tx_bd_cons + 254);
539                 for (j = start; j < end; j++) {
540                         u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
541
542                         BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
543                                   j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
544                 }
545
546                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
547                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
548                 for (j = start; j < end; j++) {
549                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
550                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
551
552                         BNX2X_ERR("rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
553                                   j, rx_bd[1], rx_bd[0], sw_bd->skb);
554                 }
555
556                 start = RX_SGE(fp->rx_sge_prod);
557                 end = RX_SGE(fp->last_max_sge);
558                 for (j = start; j < end; j++) {
559                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
560                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
561
562                         BNX2X_ERR("rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
563                                   j, rx_sge[1], rx_sge[0], sw_page->page);
564                 }
565
566                 start = RCQ_BD(fp->rx_comp_cons - 10);
567                 end = RCQ_BD(fp->rx_comp_cons + 503);
568                 for (j = start; j < end; j++) {
569                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
570
571                         BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
572                                   j, cqe[0], cqe[1], cqe[2], cqe[3]);
573                 }
574         }
575
576         BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
577                   "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
578                   "  spq_prod_idx(%u)\n",
579                   bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
580                   bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
581
582         bnx2x_fw_dump(bp);
583         bnx2x_mc_assert(bp);
584         BNX2X_ERR("end crash dump -----------------\n");
585 }
586
587 static void bnx2x_int_enable(struct bnx2x *bp)
588 {
589         int port = BP_PORT(bp);
590         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
591         u32 val = REG_RD(bp, addr);
592         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
593         int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
594
595         if (msix) {
596                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
597                          HC_CONFIG_0_REG_INT_LINE_EN_0);
598                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
599                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
600         } else if (msi) {
601                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
602                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
603                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
604                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
605         } else {
606                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
607                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
608                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
609                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
610
611                 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
612                    val, port, addr);
613
614                 REG_WR(bp, addr, val);
615
616                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
617         }
618
619         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  mode %s\n",
620            val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
621
622         REG_WR(bp, addr, val);
623
624         if (CHIP_IS_E1H(bp)) {
625                 /* init leading/trailing edge */
626                 if (IS_E1HMF(bp)) {
627                         val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
628                         if (bp->port.pmf)
629                                 /* enable nig attention */
630                                 val |= 0x0100;
631                 } else
632                         val = 0xffff;
633
634                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
635                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
636         }
637 }
638
639 static void bnx2x_int_disable(struct bnx2x *bp)
640 {
641         int port = BP_PORT(bp);
642         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
643         u32 val = REG_RD(bp, addr);
644
645         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
646                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
647                  HC_CONFIG_0_REG_INT_LINE_EN_0 |
648                  HC_CONFIG_0_REG_ATTN_BIT_EN_0);
649
650         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
651            val, port, addr);
652
653         /* flush all outstanding writes */
654         mmiowb();
655
656         REG_WR(bp, addr, val);
657         if (REG_RD(bp, addr) != val)
658                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
659 }
660
661 static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
662 {
663         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
664         int i, offset;
665
666         /* disable interrupt handling */
667         atomic_inc(&bp->intr_sem);
668         if (disable_hw)
669                 /* prevent the HW from sending interrupts */
670                 bnx2x_int_disable(bp);
671
672         /* make sure all ISRs are done */
673         if (msix) {
674                 synchronize_irq(bp->msix_table[0].vector);
675                 offset = 1;
676                 for_each_queue(bp, i)
677                         synchronize_irq(bp->msix_table[i + offset].vector);
678         } else
679                 synchronize_irq(bp->pdev->irq);
680
681         /* make sure sp_task is not running */
682         cancel_delayed_work(&bp->sp_task);
683         flush_workqueue(bnx2x_wq);
684 }
685
686 /* fast path */
687
688 /*
689  * General service functions
690  */
691
692 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
693                                 u8 storm, u16 index, u8 op, u8 update)
694 {
695         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
696                        COMMAND_REG_INT_ACK);
697         struct igu_ack_register igu_ack;
698
699         igu_ack.status_block_index = index;
700         igu_ack.sb_id_and_flags =
701                         ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
702                          (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
703                          (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
704                          (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
705
706         DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
707            (*(u32 *)&igu_ack), hc_addr);
708         REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
709 }
710
711 static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
712 {
713         struct host_status_block *fpsb = fp->status_blk;
714         u16 rc = 0;
715
716         barrier(); /* status block is written to by the chip */
717         if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
718                 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
719                 rc |= 1;
720         }
721         if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
722                 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
723                 rc |= 2;
724         }
725         return rc;
726 }
727
728 static u16 bnx2x_ack_int(struct bnx2x *bp)
729 {
730         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
731                        COMMAND_REG_SIMD_MASK);
732         u32 result = REG_RD(bp, hc_addr);
733
734         DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
735            result, hc_addr);
736
737         return result;
738 }
739
740
741 /*
742  * fast path service functions
743  */
744
745 static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
746 {
747         u16 tx_cons_sb;
748
749         /* Tell compiler that status block fields can change */
750         barrier();
751         tx_cons_sb = le16_to_cpu(*fp->tx_cons_sb);
752         return (fp->tx_pkt_cons != tx_cons_sb);
753 }
754
755 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
756 {
757         /* Tell compiler that consumer and producer can change */
758         barrier();
759         return (fp->tx_pkt_prod != fp->tx_pkt_cons);
760
761 }
762
763 /* free skb in the packet ring at pos idx
764  * return idx of last bd freed
765  */
766 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
767                              u16 idx)
768 {
769         struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
770         struct eth_tx_bd *tx_bd;
771         struct sk_buff *skb = tx_buf->skb;
772         u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
773         int nbd;
774
775         DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
776            idx, tx_buf, skb);
777
778         /* unmap first bd */
779         DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
780         tx_bd = &fp->tx_desc_ring[bd_idx];
781         pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
782                          BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
783
784         nbd = le16_to_cpu(tx_bd->nbd) - 1;
785         new_cons = nbd + tx_buf->first_bd;
786 #ifdef BNX2X_STOP_ON_ERROR
787         if (nbd > (MAX_SKB_FRAGS + 2)) {
788                 BNX2X_ERR("BAD nbd!\n");
789                 bnx2x_panic();
790         }
791 #endif
792
793         /* Skip a parse bd and the TSO split header bd
794            since they have no mapping */
795         if (nbd)
796                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
797
798         if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
799                                            ETH_TX_BD_FLAGS_TCP_CSUM |
800                                            ETH_TX_BD_FLAGS_SW_LSO)) {
801                 if (--nbd)
802                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
803                 tx_bd = &fp->tx_desc_ring[bd_idx];
804                 /* is this a TSO split header bd? */
805                 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
806                         if (--nbd)
807                                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
808                 }
809         }
810
811         /* now free frags */
812         while (nbd > 0) {
813
814                 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
815                 tx_bd = &fp->tx_desc_ring[bd_idx];
816                 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
817                                BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
818                 if (--nbd)
819                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
820         }
821
822         /* release skb */
823         WARN_ON(!skb);
824         dev_kfree_skb(skb);
825         tx_buf->first_bd = 0;
826         tx_buf->skb = NULL;
827
828         return new_cons;
829 }
830
831 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
832 {
833         s16 used;
834         u16 prod;
835         u16 cons;
836
837         barrier(); /* Tell compiler that prod and cons can change */
838         prod = fp->tx_bd_prod;
839         cons = fp->tx_bd_cons;
840
841         /* NUM_TX_RINGS = number of "next-page" entries
842            It will be used as a threshold */
843         used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
844
845 #ifdef BNX2X_STOP_ON_ERROR
846         WARN_ON(used < 0);
847         WARN_ON(used > fp->bp->tx_ring_size);
848         WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
849 #endif
850
851         return (s16)(fp->bp->tx_ring_size) - used;
852 }
853
854 static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
855 {
856         struct bnx2x *bp = fp->bp;
857         struct netdev_queue *txq;
858         u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
859         int done = 0;
860
861 #ifdef BNX2X_STOP_ON_ERROR
862         if (unlikely(bp->panic))
863                 return;
864 #endif
865
866         txq = netdev_get_tx_queue(bp->dev, fp->index);
867         hw_cons = le16_to_cpu(*fp->tx_cons_sb);
868         sw_cons = fp->tx_pkt_cons;
869
870         while (sw_cons != hw_cons) {
871                 u16 pkt_cons;
872
873                 pkt_cons = TX_BD(sw_cons);
874
875                 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
876
877                 DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %u\n",
878                    hw_cons, sw_cons, pkt_cons);
879
880 /*              if (NEXT_TX_IDX(sw_cons) != hw_cons) {
881                         rmb();
882                         prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
883                 }
884 */
885                 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
886                 sw_cons++;
887                 done++;
888
889                 if (done == work)
890                         break;
891         }
892
893         fp->tx_pkt_cons = sw_cons;
894         fp->tx_bd_cons = bd_cons;
895
896         /* Need to make the tx_bd_cons update visible to start_xmit()
897          * before checking for netif_tx_queue_stopped().  Without the
898          * memory barrier, there is a small possibility that start_xmit()
899          * will miss it and cause the queue to be stopped forever.
900          */
901         smp_mb();
902
903         /* TBD need a thresh? */
904         if (unlikely(netif_tx_queue_stopped(txq))) {
905
906                 __netif_tx_lock(txq, smp_processor_id());
907
908                 if ((netif_tx_queue_stopped(txq)) &&
909                     (bp->state == BNX2X_STATE_OPEN) &&
910                     (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
911                         netif_tx_wake_queue(txq);
912
913                 __netif_tx_unlock(txq);
914         }
915 }
916
917
918 static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
919                            union eth_rx_cqe *rr_cqe)
920 {
921         struct bnx2x *bp = fp->bp;
922         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
923         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
924
925         DP(BNX2X_MSG_SP,
926            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
927            FP_IDX(fp), cid, command, bp->state,
928            rr_cqe->ramrod_cqe.ramrod_type);
929
930         bp->spq_left++;
931
932         if (FP_IDX(fp)) {
933                 switch (command | fp->state) {
934                 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
935                                                 BNX2X_FP_STATE_OPENING):
936                         DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
937                            cid);
938                         fp->state = BNX2X_FP_STATE_OPEN;
939                         break;
940
941                 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
942                         DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
943                            cid);
944                         fp->state = BNX2X_FP_STATE_HALTED;
945                         break;
946
947                 default:
948                         BNX2X_ERR("unexpected MC reply (%d)  "
949                                   "fp->state is %x\n", command, fp->state);
950                         break;
951                 }
952                 mb(); /* force bnx2x_wait_ramrod() to see the change */
953                 return;
954         }
955
956         switch (command | bp->state) {
957         case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
958                 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
959                 bp->state = BNX2X_STATE_OPEN;
960                 break;
961
962         case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
963                 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
964                 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
965                 fp->state = BNX2X_FP_STATE_HALTED;
966                 break;
967
968         case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
969                 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
970                 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
971                 break;
972
973
974         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
975         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
976                 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
977                 bp->set_mac_pending = 0;
978                 break;
979
980         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
981                 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
982                 break;
983
984         default:
985                 BNX2X_ERR("unexpected MC reply (%d)  bp->state is %x\n",
986                           command, bp->state);
987                 break;
988         }
989         mb(); /* force bnx2x_wait_ramrod() to see the change */
990 }
991
992 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
993                                      struct bnx2x_fastpath *fp, u16 index)
994 {
995         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
996         struct page *page = sw_buf->page;
997         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
998
999         /* Skip "next page" elements */
1000         if (!page)
1001                 return;
1002
1003         pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
1004                        SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1005         __free_pages(page, PAGES_PER_SGE_SHIFT);
1006
1007         sw_buf->page = NULL;
1008         sge->addr_hi = 0;
1009         sge->addr_lo = 0;
1010 }
1011
1012 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1013                                            struct bnx2x_fastpath *fp, int last)
1014 {
1015         int i;
1016
1017         for (i = 0; i < last; i++)
1018                 bnx2x_free_rx_sge(bp, fp, i);
1019 }
1020
1021 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
1022                                      struct bnx2x_fastpath *fp, u16 index)
1023 {
1024         struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
1025         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1026         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1027         dma_addr_t mapping;
1028
1029         if (unlikely(page == NULL))
1030                 return -ENOMEM;
1031
1032         mapping = pci_map_page(bp->pdev, page, 0, SGE_PAGE_SIZE*PAGES_PER_SGE,
1033                                PCI_DMA_FROMDEVICE);
1034         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1035                 __free_pages(page, PAGES_PER_SGE_SHIFT);
1036                 return -ENOMEM;
1037         }
1038
1039         sw_buf->page = page;
1040         pci_unmap_addr_set(sw_buf, mapping, mapping);
1041
1042         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1043         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1044
1045         return 0;
1046 }
1047
1048 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1049                                      struct bnx2x_fastpath *fp, u16 index)
1050 {
1051         struct sk_buff *skb;
1052         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1053         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1054         dma_addr_t mapping;
1055
1056         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1057         if (unlikely(skb == NULL))
1058                 return -ENOMEM;
1059
1060         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_size,
1061                                  PCI_DMA_FROMDEVICE);
1062         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1063                 dev_kfree_skb(skb);
1064                 return -ENOMEM;
1065         }
1066
1067         rx_buf->skb = skb;
1068         pci_unmap_addr_set(rx_buf, mapping, mapping);
1069
1070         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1071         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1072
1073         return 0;
1074 }
1075
1076 /* note that we are not allocating a new skb,
1077  * we are just moving one from cons to prod
1078  * we are not creating a new mapping,
1079  * so there is no need to check for dma_mapping_error().
1080  */
1081 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1082                                struct sk_buff *skb, u16 cons, u16 prod)
1083 {
1084         struct bnx2x *bp = fp->bp;
1085         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1086         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1087         struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1088         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1089
1090         pci_dma_sync_single_for_device(bp->pdev,
1091                                        pci_unmap_addr(cons_rx_buf, mapping),
1092                                        bp->rx_offset + RX_COPY_THRESH,
1093                                        PCI_DMA_FROMDEVICE);
1094
1095         prod_rx_buf->skb = cons_rx_buf->skb;
1096         pci_unmap_addr_set(prod_rx_buf, mapping,
1097                            pci_unmap_addr(cons_rx_buf, mapping));
1098         *prod_bd = *cons_bd;
1099 }
1100
1101 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1102                                              u16 idx)
1103 {
1104         u16 last_max = fp->last_max_sge;
1105
1106         if (SUB_S16(idx, last_max) > 0)
1107                 fp->last_max_sge = idx;
1108 }
1109
1110 static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1111 {
1112         int i, j;
1113
1114         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1115                 int idx = RX_SGE_CNT * i - 1;
1116
1117                 for (j = 0; j < 2; j++) {
1118                         SGE_MASK_CLEAR_BIT(fp, idx);
1119                         idx--;
1120                 }
1121         }
1122 }
1123
1124 static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1125                                   struct eth_fast_path_rx_cqe *fp_cqe)
1126 {
1127         struct bnx2x *bp = fp->bp;
1128         u16 sge_len = SGE_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
1129                                      le16_to_cpu(fp_cqe->len_on_bd)) >>
1130                       SGE_PAGE_SHIFT;
1131         u16 last_max, last_elem, first_elem;
1132         u16 delta = 0;
1133         u16 i;
1134
1135         if (!sge_len)
1136                 return;
1137
1138         /* First mark all used pages */
1139         for (i = 0; i < sge_len; i++)
1140                 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1141
1142         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1143            sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1144
1145         /* Here we assume that the last SGE index is the biggest */
1146         prefetch((void *)(fp->sge_mask));
1147         bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1148
1149         last_max = RX_SGE(fp->last_max_sge);
1150         last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1151         first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1152
1153         /* If ring is not full */
1154         if (last_elem + 1 != first_elem)
1155                 last_elem++;
1156
1157         /* Now update the prod */
1158         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1159                 if (likely(fp->sge_mask[i]))
1160                         break;
1161
1162                 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1163                 delta += RX_SGE_MASK_ELEM_SZ;
1164         }
1165
1166         if (delta > 0) {
1167                 fp->rx_sge_prod += delta;
1168                 /* clear page-end entries */
1169                 bnx2x_clear_sge_mask_next_elems(fp);
1170         }
1171
1172         DP(NETIF_MSG_RX_STATUS,
1173            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
1174            fp->last_max_sge, fp->rx_sge_prod);
1175 }
1176
1177 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1178 {
1179         /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1180         memset(fp->sge_mask, 0xff,
1181                (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1182
1183         /* Clear the two last indices in the page to 1:
1184            these are the indices that correspond to the "next" element,
1185            hence will never be indicated and should be removed from
1186            the calculations. */
1187         bnx2x_clear_sge_mask_next_elems(fp);
1188 }
1189
1190 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1191                             struct sk_buff *skb, u16 cons, u16 prod)
1192 {
1193         struct bnx2x *bp = fp->bp;
1194         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1195         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1196         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1197         dma_addr_t mapping;
1198
1199         /* move empty skb from pool to prod and map it */
1200         prod_rx_buf->skb = fp->tpa_pool[queue].skb;
1201         mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
1202                                  bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1203         pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
1204
1205         /* move partial skb from cons to pool (don't unmap yet) */
1206         fp->tpa_pool[queue] = *cons_rx_buf;
1207
1208         /* mark bin state as start - print error if current state != stop */
1209         if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1210                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1211
1212         fp->tpa_state[queue] = BNX2X_TPA_START;
1213
1214         /* point prod_bd to new skb */
1215         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1216         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1217
1218 #ifdef BNX2X_STOP_ON_ERROR
1219         fp->tpa_queue_used |= (1 << queue);
1220 #ifdef __powerpc64__
1221         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1222 #else
1223         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1224 #endif
1225            fp->tpa_queue_used);
1226 #endif
1227 }
1228
1229 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1230                                struct sk_buff *skb,
1231                                struct eth_fast_path_rx_cqe *fp_cqe,
1232                                u16 cqe_idx)
1233 {
1234         struct sw_rx_page *rx_pg, old_rx_pg;
1235         u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1236         u32 i, frag_len, frag_size, pages;
1237         int err;
1238         int j;
1239
1240         frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
1241         pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
1242
1243         /* This is needed in order to enable forwarding support */
1244         if (frag_size)
1245                 skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
1246                                                max(frag_size, (u32)len_on_bd));
1247
1248 #ifdef BNX2X_STOP_ON_ERROR
1249         if (pages >
1250             min((u32)8, (u32)MAX_SKB_FRAGS) * SGE_PAGE_SIZE * PAGES_PER_SGE) {
1251                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1252                           pages, cqe_idx);
1253                 BNX2X_ERR("fp_cqe->pkt_len = %d  fp_cqe->len_on_bd = %d\n",
1254                           fp_cqe->pkt_len, len_on_bd);
1255                 bnx2x_panic();
1256                 return -EINVAL;
1257         }
1258 #endif
1259
1260         /* Run through the SGL and compose the fragmented skb */
1261         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1262                 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1263
1264                 /* FW gives the indices of the SGE as if the ring is an array
1265                    (meaning that "next" element will consume 2 indices) */
1266                 frag_len = min(frag_size, (u32)(SGE_PAGE_SIZE*PAGES_PER_SGE));
1267                 rx_pg = &fp->rx_page_ring[sge_idx];
1268                 old_rx_pg = *rx_pg;
1269
1270                 /* If we fail to allocate a substitute page, we simply stop
1271                    where we are and drop the whole packet */
1272                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1273                 if (unlikely(err)) {
1274                         fp->eth_q_stats.rx_skb_alloc_failed++;
1275                         return err;
1276                 }
1277
1278                 /* Unmap the page as we r going to pass it to the stack */
1279                 pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
1280                               SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1281
1282                 /* Add one frag and update the appropriate fields in the skb */
1283                 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1284
1285                 skb->data_len += frag_len;
1286                 skb->truesize += frag_len;
1287                 skb->len += frag_len;
1288
1289                 frag_size -= frag_len;
1290         }
1291
1292         return 0;
1293 }
1294
1295 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1296                            u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1297                            u16 cqe_idx)
1298 {
1299         struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1300         struct sk_buff *skb = rx_buf->skb;
1301         /* alloc new skb */
1302         struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1303
1304         /* Unmap skb in the pool anyway, as we are going to change
1305            pool entry status to BNX2X_TPA_STOP even if new skb allocation
1306            fails. */
1307         pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1308                          bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1309
1310         if (likely(new_skb)) {
1311                 /* fix ip xsum and give it to the stack */
1312                 /* (no need to map the new skb) */
1313 #ifdef BCM_VLAN
1314                 int is_vlan_cqe =
1315                         (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1316                          PARSING_FLAGS_VLAN);
1317                 int is_not_hwaccel_vlan_cqe =
1318                         (is_vlan_cqe && (!(bp->flags & HW_VLAN_RX_FLAG)));
1319 #endif
1320
1321                 prefetch(skb);
1322                 prefetch(((char *)(skb)) + 128);
1323
1324 #ifdef BNX2X_STOP_ON_ERROR
1325                 if (pad + len > bp->rx_buf_size) {
1326                         BNX2X_ERR("skb_put is about to fail...  "
1327                                   "pad %d  len %d  rx_buf_size %d\n",
1328                                   pad, len, bp->rx_buf_size);
1329                         bnx2x_panic();
1330                         return;
1331                 }
1332 #endif
1333
1334                 skb_reserve(skb, pad);
1335                 skb_put(skb, len);
1336
1337                 skb->protocol = eth_type_trans(skb, bp->dev);
1338                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1339                 skb_record_rx_queue(skb, queue);
1340
1341                 {
1342                         struct iphdr *iph;
1343
1344                         iph = (struct iphdr *)skb->data;
1345 #ifdef BCM_VLAN
1346                         /* If there is no Rx VLAN offloading -
1347                            take VLAN tag into an account */
1348                         if (unlikely(is_not_hwaccel_vlan_cqe))
1349                                 iph = (struct iphdr *)((u8 *)iph + VLAN_HLEN);
1350 #endif
1351                         iph->check = 0;
1352                         iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1353                 }
1354
1355                 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1356                                          &cqe->fast_path_cqe, cqe_idx)) {
1357 #ifdef BCM_VLAN
1358                         if ((bp->vlgrp != NULL) && is_vlan_cqe &&
1359                             (!is_not_hwaccel_vlan_cqe))
1360                                 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1361                                                 le16_to_cpu(cqe->fast_path_cqe.
1362                                                             vlan_tag));
1363                         else
1364 #endif
1365                                 netif_receive_skb(skb);
1366                 } else {
1367                         DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1368                            " - dropping packet!\n");
1369                         dev_kfree_skb(skb);
1370                 }
1371
1372
1373                 /* put new skb in bin */
1374                 fp->tpa_pool[queue].skb = new_skb;
1375
1376         } else {
1377                 /* else drop the packet and keep the buffer in the bin */
1378                 DP(NETIF_MSG_RX_STATUS,
1379                    "Failed to allocate new skb - dropping packet!\n");
1380                 fp->eth_q_stats.rx_skb_alloc_failed++;
1381         }
1382
1383         fp->tpa_state[queue] = BNX2X_TPA_STOP;
1384 }
1385
1386 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1387                                         struct bnx2x_fastpath *fp,
1388                                         u16 bd_prod, u16 rx_comp_prod,
1389                                         u16 rx_sge_prod)
1390 {
1391         struct ustorm_eth_rx_producers rx_prods = {0};
1392         int i;
1393
1394         /* Update producers */
1395         rx_prods.bd_prod = bd_prod;
1396         rx_prods.cqe_prod = rx_comp_prod;
1397         rx_prods.sge_prod = rx_sge_prod;
1398
1399         /*
1400          * Make sure that the BD and SGE data is updated before updating the
1401          * producers since FW might read the BD/SGE right after the producer
1402          * is updated.
1403          * This is only applicable for weak-ordered memory model archs such
1404          * as IA-64. The following barrier is also mandatory since FW will
1405          * assumes BDs must have buffers.
1406          */
1407         wmb();
1408
1409         for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
1410                 REG_WR(bp, BAR_USTRORM_INTMEM +
1411                        USTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
1412                        ((u32 *)&rx_prods)[i]);
1413
1414         mmiowb(); /* keep prod updates ordered */
1415
1416         DP(NETIF_MSG_RX_STATUS,
1417            "queue[%d]:  wrote  bd_prod %u  cqe_prod %u  sge_prod %u\n",
1418            fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
1419 }
1420
1421 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1422 {
1423         struct bnx2x *bp = fp->bp;
1424         u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1425         u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1426         int rx_pkt = 0;
1427
1428 #ifdef BNX2X_STOP_ON_ERROR
1429         if (unlikely(bp->panic))
1430                 return 0;
1431 #endif
1432
1433         /* CQ "next element" is of the size of the regular element,
1434            that's why it's ok here */
1435         hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1436         if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1437                 hw_comp_cons++;
1438
1439         bd_cons = fp->rx_bd_cons;
1440         bd_prod = fp->rx_bd_prod;
1441         bd_prod_fw = bd_prod;
1442         sw_comp_cons = fp->rx_comp_cons;
1443         sw_comp_prod = fp->rx_comp_prod;
1444
1445         /* Memory barrier necessary as speculative reads of the rx
1446          * buffer can be ahead of the index in the status block
1447          */
1448         rmb();
1449
1450         DP(NETIF_MSG_RX_STATUS,
1451            "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
1452            FP_IDX(fp), hw_comp_cons, sw_comp_cons);
1453
1454         while (sw_comp_cons != hw_comp_cons) {
1455                 struct sw_rx_bd *rx_buf = NULL;
1456                 struct sk_buff *skb;
1457                 union eth_rx_cqe *cqe;
1458                 u8 cqe_fp_flags;
1459                 u16 len, pad;
1460
1461                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1462                 bd_prod = RX_BD(bd_prod);
1463                 bd_cons = RX_BD(bd_cons);
1464
1465                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1466                 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1467
1468                 DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
1469                    "  queue %x  vlan %x  len %u\n", CQE_TYPE(cqe_fp_flags),
1470                    cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1471                    le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
1472                    le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1473                    le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1474
1475                 /* is this a slowpath msg? */
1476                 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
1477                         bnx2x_sp_event(fp, cqe);
1478                         goto next_cqe;
1479
1480                 /* this is an rx packet */
1481                 } else {
1482                         rx_buf = &fp->rx_buf_ring[bd_cons];
1483                         skb = rx_buf->skb;
1484                         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1485                         pad = cqe->fast_path_cqe.placement_offset;
1486
1487                         /* If CQE is marked both TPA_START and TPA_END
1488                            it is a non-TPA CQE */
1489                         if ((!fp->disable_tpa) &&
1490                             (TPA_TYPE(cqe_fp_flags) !=
1491                                         (TPA_TYPE_START | TPA_TYPE_END))) {
1492                                 u16 queue = cqe->fast_path_cqe.queue_index;
1493
1494                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1495                                         DP(NETIF_MSG_RX_STATUS,
1496                                            "calling tpa_start on queue %d\n",
1497                                            queue);
1498
1499                                         bnx2x_tpa_start(fp, queue, skb,
1500                                                         bd_cons, bd_prod);
1501                                         goto next_rx;
1502                                 }
1503
1504                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1505                                         DP(NETIF_MSG_RX_STATUS,
1506                                            "calling tpa_stop on queue %d\n",
1507                                            queue);
1508
1509                                         if (!BNX2X_RX_SUM_FIX(cqe))
1510                                                 BNX2X_ERR("STOP on none TCP "
1511                                                           "data\n");
1512
1513                                         /* This is a size of the linear data
1514                                            on this skb */
1515                                         len = le16_to_cpu(cqe->fast_path_cqe.
1516                                                                 len_on_bd);
1517                                         bnx2x_tpa_stop(bp, fp, queue, pad,
1518                                                     len, cqe, comp_ring_cons);
1519 #ifdef BNX2X_STOP_ON_ERROR
1520                                         if (bp->panic)
1521                                                 return -EINVAL;
1522 #endif
1523
1524                                         bnx2x_update_sge_prod(fp,
1525                                                         &cqe->fast_path_cqe);
1526                                         goto next_cqe;
1527                                 }
1528                         }
1529
1530                         pci_dma_sync_single_for_device(bp->pdev,
1531                                         pci_unmap_addr(rx_buf, mapping),
1532                                                        pad + RX_COPY_THRESH,
1533                                                        PCI_DMA_FROMDEVICE);
1534                         prefetch(skb);
1535                         prefetch(((char *)(skb)) + 128);
1536
1537                         /* is this an error packet? */
1538                         if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1539                                 DP(NETIF_MSG_RX_ERR,
1540                                    "ERROR  flags %x  rx packet %u\n",
1541                                    cqe_fp_flags, sw_comp_cons);
1542                                 fp->eth_q_stats.rx_err_discard_pkt++;
1543                                 goto reuse_rx;
1544                         }
1545
1546                         /* Since we don't have a jumbo ring
1547                          * copy small packets if mtu > 1500
1548                          */
1549                         if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1550                             (len <= RX_COPY_THRESH)) {
1551                                 struct sk_buff *new_skb;
1552
1553                                 new_skb = netdev_alloc_skb(bp->dev,
1554                                                            len + pad);
1555                                 if (new_skb == NULL) {
1556                                         DP(NETIF_MSG_RX_ERR,
1557                                            "ERROR  packet dropped "
1558                                            "because of alloc failure\n");
1559                                         fp->eth_q_stats.rx_skb_alloc_failed++;
1560                                         goto reuse_rx;
1561                                 }
1562
1563                                 /* aligned copy */
1564                                 skb_copy_from_linear_data_offset(skb, pad,
1565                                                     new_skb->data + pad, len);
1566                                 skb_reserve(new_skb, pad);
1567                                 skb_put(new_skb, len);
1568
1569                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1570
1571                                 skb = new_skb;
1572
1573                         } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
1574                                 pci_unmap_single(bp->pdev,
1575                                         pci_unmap_addr(rx_buf, mapping),
1576                                                  bp->rx_buf_size,
1577                                                  PCI_DMA_FROMDEVICE);
1578                                 skb_reserve(skb, pad);
1579                                 skb_put(skb, len);
1580
1581                         } else {
1582                                 DP(NETIF_MSG_RX_ERR,
1583                                    "ERROR  packet dropped because "
1584                                    "of alloc failure\n");
1585                                 fp->eth_q_stats.rx_skb_alloc_failed++;
1586 reuse_rx:
1587                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1588                                 goto next_rx;
1589                         }
1590
1591                         skb->protocol = eth_type_trans(skb, bp->dev);
1592
1593                         skb->ip_summed = CHECKSUM_NONE;
1594                         if (bp->rx_csum) {
1595                                 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1596                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1597                                 else
1598                                         fp->eth_q_stats.hw_csum_err++;
1599                         }
1600                 }
1601
1602 #ifdef BCM_VLAN
1603                 if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) &&
1604                     (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1605                      PARSING_FLAGS_VLAN))
1606                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1607                                 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1608                 else
1609 #endif
1610                         netif_receive_skb(skb);
1611
1612
1613 next_rx:
1614                 rx_buf->skb = NULL;
1615
1616                 bd_cons = NEXT_RX_IDX(bd_cons);
1617                 bd_prod = NEXT_RX_IDX(bd_prod);
1618                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1619                 rx_pkt++;
1620 next_cqe:
1621                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1622                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1623
1624                 if (rx_pkt == budget)
1625                         break;
1626         } /* while */
1627
1628         fp->rx_bd_cons = bd_cons;
1629         fp->rx_bd_prod = bd_prod_fw;
1630         fp->rx_comp_cons = sw_comp_cons;
1631         fp->rx_comp_prod = sw_comp_prod;
1632
1633         /* Update producers */
1634         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1635                              fp->rx_sge_prod);
1636
1637         fp->rx_pkt += rx_pkt;
1638         fp->rx_calls++;
1639
1640         return rx_pkt;
1641 }
1642
1643 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1644 {
1645         struct bnx2x_fastpath *fp = fp_cookie;
1646         struct bnx2x *bp = fp->bp;
1647         int index = FP_IDX(fp);
1648
1649         /* Return here if interrupt is disabled */
1650         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1651                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1652                 return IRQ_HANDLED;
1653         }
1654
1655         DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1656            index, FP_SB_ID(fp));
1657         bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
1658
1659 #ifdef BNX2X_STOP_ON_ERROR
1660         if (unlikely(bp->panic))
1661                 return IRQ_HANDLED;
1662 #endif
1663
1664         prefetch(fp->rx_cons_sb);
1665         prefetch(fp->tx_cons_sb);
1666         prefetch(&fp->status_blk->c_status_block.status_block_index);
1667         prefetch(&fp->status_blk->u_status_block.status_block_index);
1668
1669         napi_schedule(&bnx2x_fp(bp, index, napi));
1670
1671         return IRQ_HANDLED;
1672 }
1673
1674 static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1675 {
1676         struct bnx2x *bp = netdev_priv(dev_instance);
1677         u16 status = bnx2x_ack_int(bp);
1678         u16 mask;
1679
1680         /* Return here if interrupt is shared and it's not for us */
1681         if (unlikely(status == 0)) {
1682                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1683                 return IRQ_NONE;
1684         }
1685         DP(NETIF_MSG_INTR, "got an interrupt  status %u\n", status);
1686
1687         /* Return here if interrupt is disabled */
1688         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1689                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1690                 return IRQ_HANDLED;
1691         }
1692
1693 #ifdef BNX2X_STOP_ON_ERROR
1694         if (unlikely(bp->panic))
1695                 return IRQ_HANDLED;
1696 #endif
1697
1698         mask = 0x2 << bp->fp[0].sb_id;
1699         if (status & mask) {
1700                 struct bnx2x_fastpath *fp = &bp->fp[0];
1701
1702                 prefetch(fp->rx_cons_sb);
1703                 prefetch(fp->tx_cons_sb);
1704                 prefetch(&fp->status_blk->c_status_block.status_block_index);
1705                 prefetch(&fp->status_blk->u_status_block.status_block_index);
1706
1707                 napi_schedule(&bnx2x_fp(bp, 0, napi));
1708
1709                 status &= ~mask;
1710         }
1711
1712
1713         if (unlikely(status & 0x1)) {
1714                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1715
1716                 status &= ~0x1;
1717                 if (!status)
1718                         return IRQ_HANDLED;
1719         }
1720
1721         if (status)
1722                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1723                    status);
1724
1725         return IRQ_HANDLED;
1726 }
1727
1728 /* end of fast path */
1729
1730 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1731
1732 /* Link */
1733
1734 /*
1735  * General service functions
1736  */
1737
1738 static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1739 {
1740         u32 lock_status;
1741         u32 resource_bit = (1 << resource);
1742         int func = BP_FUNC(bp);
1743         u32 hw_lock_control_reg;
1744         int cnt;
1745
1746         /* Validating that the resource is within range */
1747         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1748                 DP(NETIF_MSG_HW,
1749                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1750                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1751                 return -EINVAL;
1752         }
1753
1754         if (func <= 5) {
1755                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1756         } else {
1757                 hw_lock_control_reg =
1758                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1759         }
1760
1761         /* Validating that the resource is not already taken */
1762         lock_status = REG_RD(bp, hw_lock_control_reg);
1763         if (lock_status & resource_bit) {
1764                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1765                    lock_status, resource_bit);
1766                 return -EEXIST;
1767         }
1768
1769         /* Try for 5 second every 5ms */
1770         for (cnt = 0; cnt < 1000; cnt++) {
1771                 /* Try to acquire the lock */
1772                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1773                 lock_status = REG_RD(bp, hw_lock_control_reg);
1774                 if (lock_status & resource_bit)
1775                         return 0;
1776
1777                 msleep(5);
1778         }
1779         DP(NETIF_MSG_HW, "Timeout\n");
1780         return -EAGAIN;
1781 }
1782
1783 static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1784 {
1785         u32 lock_status;
1786         u32 resource_bit = (1 << resource);
1787         int func = BP_FUNC(bp);
1788         u32 hw_lock_control_reg;
1789
1790         /* Validating that the resource is within range */
1791         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1792                 DP(NETIF_MSG_HW,
1793                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1794                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1795                 return -EINVAL;
1796         }
1797
1798         if (func <= 5) {
1799                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1800         } else {
1801                 hw_lock_control_reg =
1802                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1803         }
1804
1805         /* Validating that the resource is currently taken */
1806         lock_status = REG_RD(bp, hw_lock_control_reg);
1807         if (!(lock_status & resource_bit)) {
1808                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1809                    lock_status, resource_bit);
1810                 return -EFAULT;
1811         }
1812
1813         REG_WR(bp, hw_lock_control_reg, resource_bit);
1814         return 0;
1815 }
1816
1817 /* HW Lock for shared dual port PHYs */
1818 static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1819 {
1820         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1821
1822         mutex_lock(&bp->port.phy_mutex);
1823
1824         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1825             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1826                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1827 }
1828
1829 static void bnx2x_release_phy_lock(struct bnx2x *bp)
1830 {
1831         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1832
1833         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1834             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1835                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1836
1837         mutex_unlock(&bp->port.phy_mutex);
1838 }
1839
1840 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1841 {
1842         /* The GPIO should be swapped if swap register is set and active */
1843         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1844                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1845         int gpio_shift = gpio_num +
1846                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1847         u32 gpio_mask = (1 << gpio_shift);
1848         u32 gpio_reg;
1849
1850         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1851                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1852                 return -EINVAL;
1853         }
1854
1855         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1856         /* read GPIO and mask except the float bits */
1857         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1858
1859         switch (mode) {
1860         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1861                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1862                    gpio_num, gpio_shift);
1863                 /* clear FLOAT and set CLR */
1864                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1865                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1866                 break;
1867
1868         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1869                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1870                    gpio_num, gpio_shift);
1871                 /* clear FLOAT and set SET */
1872                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1873                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1874                 break;
1875
1876         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1877                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1878                    gpio_num, gpio_shift);
1879                 /* set FLOAT */
1880                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1881                 break;
1882
1883         default:
1884                 break;
1885         }
1886
1887         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1888         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1889
1890         return 0;
1891 }
1892
1893 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1894 {
1895         u32 spio_mask = (1 << spio_num);
1896         u32 spio_reg;
1897
1898         if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1899             (spio_num > MISC_REGISTERS_SPIO_7)) {
1900                 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1901                 return -EINVAL;
1902         }
1903
1904         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1905         /* read SPIO and mask except the float bits */
1906         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1907
1908         switch (mode) {
1909         case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1910                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1911                 /* clear FLOAT and set CLR */
1912                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1913                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1914                 break;
1915
1916         case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1917                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1918                 /* clear FLOAT and set SET */
1919                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1920                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1921                 break;
1922
1923         case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1924                 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1925                 /* set FLOAT */
1926                 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1927                 break;
1928
1929         default:
1930                 break;
1931         }
1932
1933         REG_WR(bp, MISC_REG_SPIO, spio_reg);
1934         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1935
1936         return 0;
1937 }
1938
1939 static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1940 {
1941         switch (bp->link_vars.ieee_fc &
1942                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1943         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1944                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1945                                           ADVERTISED_Pause);
1946                 break;
1947         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1948                 bp->port.advertising |= (ADVERTISED_Asym_Pause |
1949                                          ADVERTISED_Pause);
1950                 break;
1951         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1952                 bp->port.advertising |= ADVERTISED_Asym_Pause;
1953                 break;
1954         default:
1955                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1956                                           ADVERTISED_Pause);
1957                 break;
1958         }
1959 }
1960
1961 static void bnx2x_link_report(struct bnx2x *bp)
1962 {
1963         if (bp->link_vars.link_up) {
1964                 if (bp->state == BNX2X_STATE_OPEN)
1965                         netif_carrier_on(bp->dev);
1966                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
1967
1968                 printk("%d Mbps ", bp->link_vars.line_speed);
1969
1970                 if (bp->link_vars.duplex == DUPLEX_FULL)
1971                         printk("full duplex");
1972                 else
1973                         printk("half duplex");
1974
1975                 if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
1976                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
1977                                 printk(", receive ");
1978                                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1979                                         printk("& transmit ");
1980                         } else {
1981                                 printk(", transmit ");
1982                         }
1983                         printk("flow control ON");
1984                 }
1985                 printk("\n");
1986
1987         } else { /* link_down */
1988                 netif_carrier_off(bp->dev);
1989                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
1990         }
1991 }
1992
1993 static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1994 {
1995         if (!BP_NOMCP(bp)) {
1996                 u8 rc;
1997
1998                 /* Initialize link parameters structure variables */
1999                 /* It is recommended to turn off RX FC for jumbo frames
2000                    for better performance */
2001                 if (IS_E1HMF(bp))
2002                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2003                 else if (bp->dev->mtu > 5000)
2004                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2005                 else
2006                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2007
2008                 bnx2x_acquire_phy_lock(bp);
2009                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2010                 bnx2x_release_phy_lock(bp);
2011
2012                 bnx2x_calc_fc_adv(bp);
2013
2014                 if (bp->link_vars.link_up)
2015                         bnx2x_link_report(bp);
2016
2017
2018                 return rc;
2019         }
2020         BNX2X_ERR("Bootcode is missing -not initializing link\n");
2021         return -EINVAL;
2022 }
2023
2024 static void bnx2x_link_set(struct bnx2x *bp)
2025 {
2026         if (!BP_NOMCP(bp)) {
2027                 bnx2x_acquire_phy_lock(bp);
2028                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2029                 bnx2x_release_phy_lock(bp);
2030
2031                 bnx2x_calc_fc_adv(bp);
2032         } else
2033                 BNX2X_ERR("Bootcode is missing -not setting link\n");
2034 }
2035
2036 static void bnx2x__link_reset(struct bnx2x *bp)
2037 {
2038         if (!BP_NOMCP(bp)) {
2039                 bnx2x_acquire_phy_lock(bp);
2040                 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
2041                 bnx2x_release_phy_lock(bp);
2042         } else
2043                 BNX2X_ERR("Bootcode is missing -not resetting link\n");
2044 }
2045
2046 static u8 bnx2x_link_test(struct bnx2x *bp)
2047 {
2048         u8 rc;
2049
2050         bnx2x_acquire_phy_lock(bp);
2051         rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
2052         bnx2x_release_phy_lock(bp);
2053
2054         return rc;
2055 }
2056
2057 /* Calculates the sum of vn_min_rates.
2058    It's needed for further normalizing of the min_rates.
2059
2060    Returns:
2061      sum of vn_min_rates
2062        or
2063      0 - if all the min_rates are 0.
2064      In the later case fairness algorithm should be deactivated.
2065      If not all min_rates are zero then those that are zeroes will
2066      be set to 1.
2067  */
2068 static u32 bnx2x_calc_vn_wsum(struct bnx2x *bp)
2069 {
2070         int i, port = BP_PORT(bp);
2071         u32 wsum = 0;
2072         int all_zero = 1;
2073
2074         for (i = 0; i < E1HVN_MAX; i++) {
2075                 u32 vn_cfg =
2076                         SHMEM_RD(bp, mf_cfg.func_mf_config[2*i + port].config);
2077                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2078                                      FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2079                 if (!(vn_cfg & FUNC_MF_CFG_FUNC_HIDE)) {
2080                         /* If min rate is zero - set it to 1 */
2081                         if (!vn_min_rate)
2082                                 vn_min_rate = DEF_MIN_RATE;
2083                         else
2084                                 all_zero = 0;
2085
2086                         wsum += vn_min_rate;
2087                 }
2088         }
2089
2090         /* ... only if all min rates are zeros - disable FAIRNESS */
2091         if (all_zero)
2092                 return 0;
2093
2094         return wsum;
2095 }
2096
2097 static void bnx2x_init_port_minmax(struct bnx2x *bp,
2098                                    int en_fness,
2099                                    u16 port_rate,
2100                                    struct cmng_struct_per_port *m_cmng_port)
2101 {
2102         u32 r_param = port_rate / 8;
2103         int port = BP_PORT(bp);
2104         int i;
2105
2106         memset(m_cmng_port, 0, sizeof(struct cmng_struct_per_port));
2107
2108         /* Enable minmax only if we are in e1hmf mode */
2109         if (IS_E1HMF(bp)) {
2110                 u32 fair_periodic_timeout_usec;
2111                 u32 t_fair;
2112
2113                 /* Enable rate shaping and fairness */
2114                 m_cmng_port->flags.cmng_vn_enable = 1;
2115                 m_cmng_port->flags.fairness_enable = en_fness ? 1 : 0;
2116                 m_cmng_port->flags.rate_shaping_enable = 1;
2117
2118                 if (!en_fness)
2119                         DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2120                            "  fairness will be disabled\n");
2121
2122                 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2123                 m_cmng_port->rs_vars.rs_periodic_timeout =
2124                                                 RS_PERIODIC_TIMEOUT_USEC / 4;
2125
2126                 /* this is the threshold below which no timer arming will occur
2127                    1.25 coefficient is for the threshold to be a little bigger
2128                    than the real time, to compensate for timer in-accuracy */
2129                 m_cmng_port->rs_vars.rs_threshold =
2130                                 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2131
2132                 /* resolution of fairness timer */
2133                 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2134                 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2135                 t_fair = T_FAIR_COEF / port_rate;
2136
2137                 /* this is the threshold below which we won't arm
2138                    the timer anymore */
2139                 m_cmng_port->fair_vars.fair_threshold = QM_ARB_BYTES;
2140
2141                 /* we multiply by 1e3/8 to get bytes/msec.
2142                    We don't want the credits to pass a credit
2143                    of the T_FAIR*FAIR_MEM (algorithm resolution) */
2144                 m_cmng_port->fair_vars.upper_bound =
2145                                                 r_param * t_fair * FAIR_MEM;
2146                 /* since each tick is 4 usec */
2147                 m_cmng_port->fair_vars.fairness_timeout =
2148                                                 fair_periodic_timeout_usec / 4;
2149
2150         } else {
2151                 /* Disable rate shaping and fairness */
2152                 m_cmng_port->flags.cmng_vn_enable = 0;
2153                 m_cmng_port->flags.fairness_enable = 0;
2154                 m_cmng_port->flags.rate_shaping_enable = 0;
2155
2156                 DP(NETIF_MSG_IFUP,
2157                    "Single function mode  minmax will be disabled\n");
2158         }
2159
2160         /* Store it to internal memory */
2161         for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
2162                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2163                        XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
2164                        ((u32 *)(m_cmng_port))[i]);
2165 }
2166
2167 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
2168                                    u32 wsum, u16 port_rate,
2169                                  struct cmng_struct_per_port *m_cmng_port)
2170 {
2171         struct rate_shaping_vars_per_vn m_rs_vn;
2172         struct fairness_vars_per_vn m_fair_vn;
2173         u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2174         u16 vn_min_rate, vn_max_rate;
2175         int i;
2176
2177         /* If function is hidden - set min and max to zeroes */
2178         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2179                 vn_min_rate = 0;
2180                 vn_max_rate = 0;
2181
2182         } else {
2183                 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2184                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2185                 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2186                    if current min rate is zero - set it to 1.
2187                    This is a requirement of the algorithm. */
2188                 if ((vn_min_rate == 0) && wsum)
2189                         vn_min_rate = DEF_MIN_RATE;
2190                 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2191                                 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2192         }
2193
2194         DP(NETIF_MSG_IFUP, "func %d: vn_min_rate=%d  vn_max_rate=%d  "
2195            "wsum=%d\n", func, vn_min_rate, vn_max_rate, wsum);
2196
2197         memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2198         memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2199
2200         /* global vn counter - maximal Mbps for this vn */
2201         m_rs_vn.vn_counter.rate = vn_max_rate;
2202
2203         /* quota - number of bytes transmitted in this period */
2204         m_rs_vn.vn_counter.quota =
2205                                 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2206
2207 #ifdef BNX2X_PER_PROT_QOS
2208         /* per protocol counter */
2209         for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) {
2210                 /* maximal Mbps for this protocol */
2211                 m_rs_vn.protocol_counters[protocol].rate =
2212                                                 protocol_max_rate[protocol];
2213                 /* the quota in each timer period -
2214                    number of bytes transmitted in this period */
2215                 m_rs_vn.protocol_counters[protocol].quota =
2216                         (u32)(rs_periodic_timeout_usec *
2217                           ((double)m_rs_vn.
2218                                    protocol_counters[protocol].rate/8));
2219         }
2220 #endif
2221
2222         if (wsum) {
2223                 /* credit for each period of the fairness algorithm:
2224                    number of bytes in T_FAIR (the vn share the port rate).
2225                    wsum should not be larger than 10000, thus
2226                    T_FAIR_COEF / (8 * wsum) will always be grater than zero */
2227                 m_fair_vn.vn_credit_delta =
2228                         max((u64)(vn_min_rate * (T_FAIR_COEF / (8 * wsum))),
2229                             (u64)(m_cmng_port->fair_vars.fair_threshold * 2));
2230                 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2231                    m_fair_vn.vn_credit_delta);
2232         }
2233
2234 #ifdef BNX2X_PER_PROT_QOS
2235         do {
2236                 u32 protocolWeightSum = 0;
2237
2238                 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++)
2239                         protocolWeightSum +=
2240                                         drvInit.protocol_min_rate[protocol];
2241                 /* per protocol counter -
2242                    NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */
2243                 if (protocolWeightSum > 0) {
2244                         for (protocol = 0;
2245                              protocol < NUM_OF_PROTOCOLS; protocol++)
2246                                 /* credit for each period of the
2247                                    fairness algorithm - number of bytes in
2248                                    T_FAIR (the protocol share the vn rate) */
2249                                 m_fair_vn.protocol_credit_delta[protocol] =
2250                                         (u32)((vn_min_rate / 8) * t_fair *
2251                                         protocol_min_rate / protocolWeightSum);
2252                 }
2253         } while (0);
2254 #endif
2255
2256         /* Store it to internal memory */
2257         for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2258                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2259                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2260                        ((u32 *)(&m_rs_vn))[i]);
2261
2262         for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2263                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2264                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2265                        ((u32 *)(&m_fair_vn))[i]);
2266 }
2267
2268 /* This function is called upon link interrupt */
2269 static void bnx2x_link_attn(struct bnx2x *bp)
2270 {
2271         int vn;
2272
2273         /* Make sure that we are synced with the current statistics */
2274         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2275
2276         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2277
2278         if (bp->link_vars.link_up) {
2279
2280                 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2281                         struct host_port_stats *pstats;
2282
2283                         pstats = bnx2x_sp(bp, port_stats);
2284                         /* reset old bmac stats */
2285                         memset(&(pstats->mac_stx[0]), 0,
2286                                sizeof(struct mac_stx));
2287                 }
2288                 if ((bp->state == BNX2X_STATE_OPEN) ||
2289                     (bp->state == BNX2X_STATE_DISABLED))
2290                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2291         }
2292
2293         /* indicate link status */
2294         bnx2x_link_report(bp);
2295
2296         if (IS_E1HMF(bp)) {
2297                 int func;
2298
2299                 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2300                         if (vn == BP_E1HVN(bp))
2301                                 continue;
2302
2303                         func = ((vn << 1) | BP_PORT(bp));
2304
2305                         /* Set the attention towards other drivers
2306                            on the same port */
2307                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2308                                (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2309                 }
2310         }
2311
2312         if (CHIP_IS_E1H(bp) && (bp->link_vars.line_speed > 0)) {
2313                 struct cmng_struct_per_port m_cmng_port;
2314                 u32 wsum;
2315                 int port = BP_PORT(bp);
2316
2317                 /* Init RATE SHAPING and FAIRNESS contexts */
2318                 wsum = bnx2x_calc_vn_wsum(bp);
2319                 bnx2x_init_port_minmax(bp, (int)wsum,
2320                                         bp->link_vars.line_speed,
2321                                         &m_cmng_port);
2322                 if (IS_E1HMF(bp))
2323                         for (vn = VN_0; vn < E1HVN_MAX; vn++)
2324                                 bnx2x_init_vn_minmax(bp, 2*vn + port,
2325                                         wsum, bp->link_vars.line_speed,
2326                                                      &m_cmng_port);
2327         }
2328 }
2329
2330 static void bnx2x__link_status_update(struct bnx2x *bp)
2331 {
2332         if (bp->state != BNX2X_STATE_OPEN)
2333                 return;
2334
2335         bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2336
2337         if (bp->link_vars.link_up)
2338                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2339         else
2340                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2341
2342         /* indicate link status */
2343         bnx2x_link_report(bp);
2344 }
2345
2346 static void bnx2x_pmf_update(struct bnx2x *bp)
2347 {
2348         int port = BP_PORT(bp);
2349         u32 val;
2350
2351         bp->port.pmf = 1;
2352         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2353
2354         /* enable nig attention */
2355         val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2356         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2357         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2358
2359         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2360 }
2361
2362 /* end of Link */
2363
2364 /* slow path */
2365
2366 /*
2367  * General service functions
2368  */
2369
2370 /* the slow path queue is odd since completions arrive on the fastpath ring */
2371 static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2372                          u32 data_hi, u32 data_lo, int common)
2373 {
2374         int func = BP_FUNC(bp);
2375
2376         DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2377            "SPQE (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
2378            (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2379            (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2380            HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2381
2382 #ifdef BNX2X_STOP_ON_ERROR
2383         if (unlikely(bp->panic))
2384                 return -EIO;
2385 #endif
2386
2387         spin_lock_bh(&bp->spq_lock);
2388
2389         if (!bp->spq_left) {
2390                 BNX2X_ERR("BUG! SPQ ring full!\n");
2391                 spin_unlock_bh(&bp->spq_lock);
2392                 bnx2x_panic();
2393                 return -EBUSY;
2394         }
2395
2396         /* CID needs port number to be encoded int it */
2397         bp->spq_prod_bd->hdr.conn_and_cmd_data =
2398                         cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2399                                      HW_CID(bp, cid)));
2400         bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
2401         if (common)
2402                 bp->spq_prod_bd->hdr.type |=
2403                         cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2404
2405         bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2406         bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
2407
2408         bp->spq_left--;
2409
2410         if (bp->spq_prod_bd == bp->spq_last_bd) {
2411                 bp->spq_prod_bd = bp->spq;
2412                 bp->spq_prod_idx = 0;
2413                 DP(NETIF_MSG_TIMER, "end of spq\n");
2414
2415         } else {
2416                 bp->spq_prod_bd++;
2417                 bp->spq_prod_idx++;
2418         }
2419
2420         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2421                bp->spq_prod_idx);
2422
2423         spin_unlock_bh(&bp->spq_lock);
2424         return 0;
2425 }
2426
2427 /* acquire split MCP access lock register */
2428 static int bnx2x_acquire_alr(struct bnx2x *bp)
2429 {
2430         u32 i, j, val;
2431         int rc = 0;
2432
2433         might_sleep();
2434         i = 100;
2435         for (j = 0; j < i*10; j++) {
2436                 val = (1UL << 31);
2437                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2438                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2439                 if (val & (1L << 31))
2440                         break;
2441
2442                 msleep(5);
2443         }
2444         if (!(val & (1L << 31))) {
2445                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2446                 rc = -EBUSY;
2447         }
2448
2449         return rc;
2450 }
2451
2452 /* release split MCP access lock register */
2453 static void bnx2x_release_alr(struct bnx2x *bp)
2454 {
2455         u32 val = 0;
2456
2457         REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2458 }
2459
2460 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2461 {
2462         struct host_def_status_block *def_sb = bp->def_status_blk;
2463         u16 rc = 0;
2464
2465         barrier(); /* status block is written to by the chip */
2466         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2467                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2468                 rc |= 1;
2469         }
2470         if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2471                 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2472                 rc |= 2;
2473         }
2474         if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2475                 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2476                 rc |= 4;
2477         }
2478         if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2479                 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2480                 rc |= 8;
2481         }
2482         if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2483                 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2484                 rc |= 16;
2485         }
2486         return rc;
2487 }
2488
2489 /*
2490  * slow path service functions
2491  */
2492
2493 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2494 {
2495         int port = BP_PORT(bp);
2496         u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2497                        COMMAND_REG_ATTN_BITS_SET);
2498         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2499                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
2500         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2501                                        NIG_REG_MASK_INTERRUPT_PORT0;
2502         u32 aeu_mask;
2503
2504         if (bp->attn_state & asserted)
2505                 BNX2X_ERR("IGU ERROR\n");
2506
2507         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2508         aeu_mask = REG_RD(bp, aeu_addr);
2509
2510         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
2511            aeu_mask, asserted);
2512         aeu_mask &= ~(asserted & 0xff);
2513         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2514
2515         REG_WR(bp, aeu_addr, aeu_mask);
2516         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2517
2518         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2519         bp->attn_state |= asserted;
2520         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2521
2522         if (asserted & ATTN_HARD_WIRED_MASK) {
2523                 if (asserted & ATTN_NIG_FOR_FUNC) {
2524
2525                         bnx2x_acquire_phy_lock(bp);
2526
2527                         /* save nig interrupt mask */
2528                         bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
2529                         REG_WR(bp, nig_int_mask_addr, 0);
2530
2531                         bnx2x_link_attn(bp);
2532
2533                         /* handle unicore attn? */
2534                 }
2535                 if (asserted & ATTN_SW_TIMER_4_FUNC)
2536                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2537
2538                 if (asserted & GPIO_2_FUNC)
2539                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2540
2541                 if (asserted & GPIO_3_FUNC)
2542                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2543
2544                 if (asserted & GPIO_4_FUNC)
2545                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2546
2547                 if (port == 0) {
2548                         if (asserted & ATTN_GENERAL_ATTN_1) {
2549                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2550                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2551                         }
2552                         if (asserted & ATTN_GENERAL_ATTN_2) {
2553                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2554                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2555                         }
2556                         if (asserted & ATTN_GENERAL_ATTN_3) {
2557                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2558                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2559                         }
2560                 } else {
2561                         if (asserted & ATTN_GENERAL_ATTN_4) {
2562                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2563                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2564                         }
2565                         if (asserted & ATTN_GENERAL_ATTN_5) {
2566                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2567                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2568                         }
2569                         if (asserted & ATTN_GENERAL_ATTN_6) {
2570                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2571                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2572                         }
2573                 }
2574
2575         } /* if hardwired */
2576
2577         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2578            asserted, hc_addr);
2579         REG_WR(bp, hc_addr, asserted);
2580
2581         /* now set back the mask */
2582         if (asserted & ATTN_NIG_FOR_FUNC) {
2583                 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
2584                 bnx2x_release_phy_lock(bp);
2585         }
2586 }
2587
2588 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2589 {
2590         int port = BP_PORT(bp);
2591         int reg_offset;
2592         u32 val;
2593
2594         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2595                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2596
2597         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2598
2599                 val = REG_RD(bp, reg_offset);
2600                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2601                 REG_WR(bp, reg_offset, val);
2602
2603                 BNX2X_ERR("SPIO5 hw attention\n");
2604
2605                 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
2606                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
2607                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2608                         /* Fan failure attention */
2609
2610                         /* The PHY reset is controlled by GPIO 1 */
2611                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2612                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2613                         /* Low power mode is controlled by GPIO 2 */
2614                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2615                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2616                         /* mark the failure */
2617                         bp->link_params.ext_phy_config &=
2618                                         ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2619                         bp->link_params.ext_phy_config |=
2620                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2621                         SHMEM_WR(bp,
2622                                  dev_info.port_hw_config[port].
2623                                                         external_phy_config,
2624                                  bp->link_params.ext_phy_config);
2625                         /* log the failure */
2626                         printk(KERN_ERR PFX "Fan Failure on Network"
2627                                " Controller %s has caused the driver to"
2628                                " shutdown the card to prevent permanent"
2629                                " damage.  Please contact Dell Support for"
2630                                " assistance\n", bp->dev->name);
2631                         break;
2632
2633                 default:
2634                         break;
2635                 }
2636         }
2637
2638         if (attn & HW_INTERRUT_ASSERT_SET_0) {
2639
2640                 val = REG_RD(bp, reg_offset);
2641                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2642                 REG_WR(bp, reg_offset, val);
2643
2644                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2645                           (attn & HW_INTERRUT_ASSERT_SET_0));
2646                 bnx2x_panic();
2647         }
2648 }
2649
2650 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2651 {
2652         u32 val;
2653
2654         if (attn & BNX2X_DOORQ_ASSERT) {
2655
2656                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2657                 BNX2X_ERR("DB hw attention 0x%x\n", val);
2658                 /* DORQ discard attention */
2659                 if (val & 0x2)
2660                         BNX2X_ERR("FATAL error from DORQ\n");
2661         }
2662
2663         if (attn & HW_INTERRUT_ASSERT_SET_1) {
2664
2665                 int port = BP_PORT(bp);
2666                 int reg_offset;
2667
2668                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2669                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2670
2671                 val = REG_RD(bp, reg_offset);
2672                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2673                 REG_WR(bp, reg_offset, val);
2674
2675                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2676                           (attn & HW_INTERRUT_ASSERT_SET_1));
2677                 bnx2x_panic();
2678         }
2679 }
2680
2681 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2682 {
2683         u32 val;
2684
2685         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
2686
2687                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
2688                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
2689                 /* CFC error attention */
2690                 if (val & 0x2)
2691                         BNX2X_ERR("FATAL error from CFC\n");
2692         }
2693
2694         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
2695
2696                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
2697                 BNX2X_ERR("PXP hw attention 0x%x\n", val);
2698                 /* RQ_USDMDP_FIFO_OVERFLOW */
2699                 if (val & 0x18000)
2700                         BNX2X_ERR("FATAL error from PXP\n");
2701         }
2702
2703         if (attn & HW_INTERRUT_ASSERT_SET_2) {
2704
2705                 int port = BP_PORT(bp);
2706                 int reg_offset;
2707
2708                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
2709                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
2710
2711                 val = REG_RD(bp, reg_offset);
2712                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
2713                 REG_WR(bp, reg_offset, val);
2714
2715                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2716                           (attn & HW_INTERRUT_ASSERT_SET_2));
2717                 bnx2x_panic();
2718         }
2719 }
2720
2721 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2722 {
2723         u32 val;
2724
2725         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
2726
2727                 if (attn & BNX2X_PMF_LINK_ASSERT) {
2728                         int func = BP_FUNC(bp);
2729
2730                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2731                         bnx2x__link_status_update(bp);
2732                         if (SHMEM_RD(bp, func_mb[func].drv_status) &
2733                                                         DRV_STATUS_PMF)
2734                                 bnx2x_pmf_update(bp);
2735
2736                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2737
2738                         BNX2X_ERR("MC assert!\n");
2739                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
2740                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
2741                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
2742                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
2743                         bnx2x_panic();
2744
2745                 } else if (attn & BNX2X_MCP_ASSERT) {
2746
2747                         BNX2X_ERR("MCP assert!\n");
2748                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
2749                         bnx2x_fw_dump(bp);
2750
2751                 } else
2752                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
2753         }
2754
2755         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2756                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2757                 if (attn & BNX2X_GRC_TIMEOUT) {
2758                         val = CHIP_IS_E1H(bp) ?
2759                                 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
2760                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
2761                 }
2762                 if (attn & BNX2X_GRC_RSV) {
2763                         val = CHIP_IS_E1H(bp) ?
2764                                 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
2765                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
2766                 }
2767                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
2768         }
2769 }
2770
2771 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2772 {
2773         struct attn_route attn;
2774         struct attn_route group_mask;
2775         int port = BP_PORT(bp);
2776         int index;
2777         u32 reg_addr;
2778         u32 val;
2779         u32 aeu_mask;
2780
2781         /* need to take HW lock because MCP or other port might also
2782            try to handle this event */
2783         bnx2x_acquire_alr(bp);
2784
2785         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2786         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2787         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2788         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2789         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
2790            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
2791
2792         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2793                 if (deasserted & (1 << index)) {
2794                         group_mask = bp->attn_group[index];
2795
2796                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
2797                            index, group_mask.sig[0], group_mask.sig[1],
2798                            group_mask.sig[2], group_mask.sig[3]);
2799
2800                         bnx2x_attn_int_deasserted3(bp,
2801                                         attn.sig[3] & group_mask.sig[3]);
2802                         bnx2x_attn_int_deasserted1(bp,
2803                                         attn.sig[1] & group_mask.sig[1]);
2804                         bnx2x_attn_int_deasserted2(bp,
2805                                         attn.sig[2] & group_mask.sig[2]);
2806                         bnx2x_attn_int_deasserted0(bp,
2807                                         attn.sig[0] & group_mask.sig[0]);
2808
2809                         if ((attn.sig[0] & group_mask.sig[0] &
2810                                                 HW_PRTY_ASSERT_SET_0) ||
2811                             (attn.sig[1] & group_mask.sig[1] &
2812                                                 HW_PRTY_ASSERT_SET_1) ||
2813                             (attn.sig[2] & group_mask.sig[2] &
2814                                                 HW_PRTY_ASSERT_SET_2))
2815                                 BNX2X_ERR("FATAL HW block parity attention\n");
2816                 }
2817         }
2818
2819         bnx2x_release_alr(bp);
2820
2821         reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2822
2823         val = ~deasserted;
2824         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2825            val, reg_addr);
2826         REG_WR(bp, reg_addr, val);
2827
2828         if (~bp->attn_state & deasserted)
2829                 BNX2X_ERR("IGU ERROR\n");
2830
2831         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2832                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
2833
2834         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2835         aeu_mask = REG_RD(bp, reg_addr);
2836
2837         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
2838            aeu_mask, deasserted);
2839         aeu_mask |= (deasserted & 0xff);
2840         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2841
2842         REG_WR(bp, reg_addr, aeu_mask);
2843         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2844
2845         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2846         bp->attn_state &= ~deasserted;
2847         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2848 }
2849
2850 static void bnx2x_attn_int(struct bnx2x *bp)
2851 {
2852         /* read local copy of bits */
2853         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
2854                                                                 attn_bits);
2855         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
2856                                                                 attn_bits_ack);
2857         u32 attn_state = bp->attn_state;
2858
2859         /* look for changed bits */
2860         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
2861         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
2862
2863         DP(NETIF_MSG_HW,
2864            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
2865            attn_bits, attn_ack, asserted, deasserted);
2866
2867         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
2868                 BNX2X_ERR("BAD attention state\n");
2869
2870         /* handle bits that were raised */
2871         if (asserted)
2872                 bnx2x_attn_int_asserted(bp, asserted);
2873
2874         if (deasserted)
2875                 bnx2x_attn_int_deasserted(bp, deasserted);
2876 }
2877
2878 static void bnx2x_sp_task(struct work_struct *work)
2879 {
2880         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
2881         u16 status;
2882
2883
2884         /* Return here if interrupt is disabled */
2885         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2886                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2887                 return;
2888         }
2889
2890         status = bnx2x_update_dsb_idx(bp);
2891 /*      if (status == 0)                                     */
2892 /*              BNX2X_ERR("spurious slowpath interrupt!\n"); */
2893
2894         DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
2895
2896         /* HW attentions */
2897         if (status & 0x1)
2898                 bnx2x_attn_int(bp);
2899
2900         bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
2901                      IGU_INT_NOP, 1);
2902         bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2903                      IGU_INT_NOP, 1);
2904         bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2905                      IGU_INT_NOP, 1);
2906         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2907                      IGU_INT_NOP, 1);
2908         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2909                      IGU_INT_ENABLE, 1);
2910
2911 }
2912
2913 static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2914 {
2915         struct net_device *dev = dev_instance;
2916         struct bnx2x *bp = netdev_priv(dev);
2917
2918         /* Return here if interrupt is disabled */
2919         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2920                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2921                 return IRQ_HANDLED;
2922         }
2923
2924         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
2925
2926 #ifdef BNX2X_STOP_ON_ERROR
2927         if (unlikely(bp->panic))
2928                 return IRQ_HANDLED;
2929 #endif
2930
2931         queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
2932
2933         return IRQ_HANDLED;
2934 }
2935
2936 /* end of slow path */
2937
2938 /* Statistics */
2939
2940 /****************************************************************************
2941 * Macros
2942 ****************************************************************************/
2943
2944 /* sum[hi:lo] += add[hi:lo] */
2945 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2946         do { \
2947                 s_lo += a_lo; \
2948                 s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
2949         } while (0)
2950
2951 /* difference = minuend - subtrahend */
2952 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2953         do { \
2954                 if (m_lo < s_lo) { \
2955                         /* underflow */ \
2956                         d_hi = m_hi - s_hi; \
2957                         if (d_hi > 0) { \
2958                                 /* we can 'loan' 1 */ \
2959                                 d_hi--; \
2960                                 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2961                         } else { \
2962                                 /* m_hi <= s_hi */ \
2963                                 d_hi = 0; \
2964                                 d_lo = 0; \
2965                         } \
2966                 } else { \
2967                         /* m_lo >= s_lo */ \
2968                         if (m_hi < s_hi) { \
2969                                 d_hi = 0; \
2970                                 d_lo = 0; \
2971                         } else { \
2972                                 /* m_hi >= s_hi */ \
2973                                 d_hi = m_hi - s_hi; \
2974                                 d_lo = m_lo - s_lo; \
2975                         } \
2976                 } \
2977         } while (0)
2978
2979 #define UPDATE_STAT64(s, t) \
2980         do { \
2981                 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
2982                         diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
2983                 pstats->mac_stx[0].t##_hi = new->s##_hi; \
2984                 pstats->mac_stx[0].t##_lo = new->s##_lo; \
2985                 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
2986                        pstats->mac_stx[1].t##_lo, diff.lo); \
2987         } while (0)
2988
2989 #define UPDATE_STAT64_NIG(s, t) \
2990         do { \
2991                 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
2992                         diff.lo, new->s##_lo, old->s##_lo); \
2993                 ADD_64(estats->t##_hi, diff.hi, \
2994                        estats->t##_lo, diff.lo); \
2995         } while (0)
2996
2997 /* sum[hi:lo] += add */
2998 #define ADD_EXTEND_64(s_hi, s_lo, a) \
2999         do { \
3000                 s_lo += a; \
3001                 s_hi += (s_lo < a) ? 1 : 0; \
3002         } while (0)
3003
3004 #define UPDATE_EXTEND_STAT(s) \
3005         do { \
3006                 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
3007                               pstats->mac_stx[1].s##_lo, \
3008                               new->s); \
3009         } while (0)
3010
3011 #define UPDATE_EXTEND_TSTAT(s, t) \
3012         do { \
3013                 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
3014                 old_tclient->s = le32_to_cpu(tclient->s); \
3015                 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3016         } while (0)
3017
3018 #define UPDATE_EXTEND_USTAT(s, t) \
3019         do { \
3020                 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
3021                 old_uclient->s = uclient->s; \
3022                 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3023         } while (0)
3024
3025 #define UPDATE_EXTEND_XSTAT(s, t) \
3026         do { \
3027                 diff = le32_to_cpu(xclient->s) - old_xclient->s; \
3028                 old_xclient->s = le32_to_cpu(xclient->s); \
3029                 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3030         } while (0)
3031
3032 /* minuend -= subtrahend */
3033 #define SUB_64(m_hi, s_hi, m_lo, s_lo) \
3034         do { \
3035                 DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
3036         } while (0)
3037
3038 /* minuend[hi:lo] -= subtrahend */
3039 #define SUB_EXTEND_64(m_hi, m_lo, s) \
3040         do { \
3041                 SUB_64(m_hi, 0, m_lo, s); \
3042         } while (0)
3043
3044 #define SUB_EXTEND_USTAT(s, t) \
3045         do { \
3046                 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
3047                 SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3048         } while (0)
3049
3050 /*
3051  * General service functions
3052  */
3053
3054 static inline long bnx2x_hilo(u32 *hiref)
3055 {
3056         u32 lo = *(hiref + 1);
3057 #if (BITS_PER_LONG == 64)
3058         u32 hi = *hiref;
3059
3060         return HILO_U64(hi, lo);
3061 #else
3062         return lo;
3063 #endif
3064 }
3065
3066 /*
3067  * Init service functions
3068  */
3069
3070 static void bnx2x_storm_stats_post(struct bnx2x *bp)
3071 {
3072         if (!bp->stats_pending) {
3073                 struct eth_query_ramrod_data ramrod_data = {0};
3074                 int i, rc;
3075
3076                 ramrod_data.drv_counter = bp->stats_counter++;
3077                 ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
3078                 for_each_queue(bp, i)
3079                         ramrod_data.ctr_id_vector |= (1 << bp->fp[i].cl_id);
3080
3081                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
3082                                    ((u32 *)&ramrod_data)[1],
3083                                    ((u32 *)&ramrod_data)[0], 0);
3084                 if (rc == 0) {
3085                         /* stats ramrod has it's own slot on the spq */
3086                         bp->spq_left++;
3087                         bp->stats_pending = 1;
3088                 }
3089         }
3090 }
3091
3092 static void bnx2x_stats_init(struct bnx2x *bp)
3093 {
3094         int port = BP_PORT(bp);
3095         int i;
3096
3097         bp->stats_pending = 0;
3098         bp->executer_idx = 0;
3099         bp->stats_counter = 0;
3100
3101         /* port stats */
3102         if (!BP_NOMCP(bp))
3103                 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
3104         else
3105                 bp->port.port_stx = 0;
3106         DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
3107
3108         memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3109         bp->port.old_nig_stats.brb_discard =
3110                         REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3111         bp->port.old_nig_stats.brb_truncate =
3112                         REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3113         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3114                     &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3115         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
3116                     &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
3117
3118         /* function stats */
3119         for_each_queue(bp, i) {
3120                 struct bnx2x_fastpath *fp = &bp->fp[i];
3121
3122                 memset(&fp->old_tclient, 0,
3123                        sizeof(struct tstorm_per_client_stats));
3124                 memset(&fp->old_uclient, 0,
3125                        sizeof(struct ustorm_per_client_stats));
3126                 memset(&fp->old_xclient, 0,
3127                        sizeof(struct xstorm_per_client_stats));
3128                 memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
3129         }
3130
3131         memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3132         memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
3133
3134         bp->stats_state = STATS_STATE_DISABLED;
3135         if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
3136                 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3137 }
3138
3139 static void bnx2x_hw_stats_post(struct bnx2x *bp)
3140 {
3141         struct dmae_command *dmae = &bp->stats_dmae;
3142         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3143
3144         *stats_comp = DMAE_COMP_VAL;
3145         if (CHIP_REV_IS_SLOW(bp))
3146                 return;
3147
3148         /* loader */
3149         if (bp->executer_idx) {
3150                 int loader_idx = PMF_DMAE_C(bp);
3151
3152                 memset(dmae, 0, sizeof(struct dmae_command));
3153
3154                 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3155                                 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3156                                 DMAE_CMD_DST_RESET |
3157 #ifdef __BIG_ENDIAN
3158                                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3159 #else
3160                                 DMAE_CMD_ENDIANITY_DW_SWAP |
3161 #endif
3162                                 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3163                                                DMAE_CMD_PORT_0) |
3164                                 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3165                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3166                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3167                 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3168                                      sizeof(struct dmae_command) *
3169                                      (loader_idx + 1)) >> 2;
3170                 dmae->dst_addr_hi = 0;
3171                 dmae->len = sizeof(struct dmae_command) >> 2;
3172                 if (CHIP_IS_E1(bp))
3173                         dmae->len--;
3174                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3175                 dmae->comp_addr_hi = 0;
3176                 dmae->comp_val = 1;
3177
3178                 *stats_comp = 0;
3179                 bnx2x_post_dmae(bp, dmae, loader_idx);
3180
3181         } else if (bp->func_stx) {
3182                 *stats_comp = 0;
3183                 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3184         }
3185 }
3186
3187 static int bnx2x_stats_comp(struct bnx2x *bp)
3188 {
3189         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3190         int cnt = 10;
3191
3192         might_sleep();
3193         while (*stats_comp != DMAE_COMP_VAL) {
3194                 if (!cnt) {
3195                         BNX2X_ERR("timeout waiting for stats finished\n");
3196                         break;
3197                 }
3198                 cnt--;
3199                 msleep(1);
3200         }
3201         return 1;
3202 }
3203
3204 /*
3205  * Statistics service functions
3206  */
3207
3208 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3209 {
3210         struct dmae_command *dmae;
3211         u32 opcode;
3212         int loader_idx = PMF_DMAE_C(bp);
3213         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3214
3215         /* sanity */
3216         if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3217                 BNX2X_ERR("BUG!\n");
3218                 return;
3219         }
3220
3221         bp->executer_idx = 0;
3222
3223         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3224                   DMAE_CMD_C_ENABLE |
3225                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3226 #ifdef __BIG_ENDIAN
3227                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3228 #else
3229                   DMAE_CMD_ENDIANITY_DW_SWAP |
3230 #endif
3231                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3232                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3233
3234         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3235         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3236         dmae->src_addr_lo = bp->port.port_stx >> 2;
3237         dmae->src_addr_hi = 0;
3238         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3239         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3240         dmae->len = DMAE_LEN32_RD_MAX;
3241         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3242         dmae->comp_addr_hi = 0;
3243         dmae->comp_val = 1;
3244
3245         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3246         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3247         dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3248         dmae->src_addr_hi = 0;
3249         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3250                                    DMAE_LEN32_RD_MAX * 4);
3251         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3252                                    DMAE_LEN32_RD_MAX * 4);
3253         dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3254         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3255         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3256         dmae->comp_val = DMAE_COMP_VAL;
3257
3258         *stats_comp = 0;
3259         bnx2x_hw_stats_post(bp);
3260         bnx2x_stats_comp(bp);
3261 }
3262
3263 static void bnx2x_port_stats_init(struct bnx2x *bp)
3264 {
3265         struct dmae_command *dmae;
3266         int port = BP_PORT(bp);
3267         int vn = BP_E1HVN(bp);
3268         u32 opcode;
3269         int loader_idx = PMF_DMAE_C(bp);
3270         u32 mac_addr;
3271         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3272
3273         /* sanity */
3274         if (!bp->link_vars.link_up || !bp->port.pmf) {
3275                 BNX2X_ERR("BUG!\n");
3276                 return;
3277         }
3278
3279         bp->executer_idx = 0;
3280
3281         /* MCP */
3282         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3283                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3284                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3285 #ifdef __BIG_ENDIAN
3286                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3287 #else
3288                   DMAE_CMD_ENDIANITY_DW_SWAP |
3289 #endif
3290                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3291                   (vn << DMAE_CMD_E1HVN_SHIFT));
3292
3293         if (bp->port.port_stx) {
3294
3295                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3296                 dmae->opcode = opcode;
3297                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3298                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3299                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3300                 dmae->dst_addr_hi = 0;
3301                 dmae->len = sizeof(struct host_port_stats) >> 2;
3302                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3303                 dmae->comp_addr_hi = 0;
3304                 dmae->comp_val = 1;
3305         }
3306
3307         if (bp->func_stx) {
3308
3309                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3310                 dmae->opcode = opcode;
3311                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3312                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3313                 dmae->dst_addr_lo = bp->func_stx >> 2;
3314                 dmae->dst_addr_hi = 0;
3315                 dmae->len = sizeof(struct host_func_stats) >> 2;
3316                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3317                 dmae->comp_addr_hi = 0;
3318                 dmae->comp_val = 1;
3319         }
3320
3321         /* MAC */
3322         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3323                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3324                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3325 #ifdef __BIG_ENDIAN
3326                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3327 #else
3328                   DMAE_CMD_ENDIANITY_DW_SWAP |
3329 #endif
3330                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3331                   (vn << DMAE_CMD_E1HVN_SHIFT));
3332
3333         if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
3334
3335                 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3336                                    NIG_REG_INGRESS_BMAC0_MEM);
3337
3338                 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3339                    BIGMAC_REGISTER_TX_STAT_GTBYT */
3340                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3341                 dmae->opcode = opcode;
3342                 dmae->src_addr_lo = (mac_addr +
3343                                      BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3344                 dmae->src_addr_hi = 0;
3345                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3346                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3347                 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3348                              BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3349                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3350                 dmae->comp_addr_hi = 0;
3351                 dmae->comp_val = 1;
3352
3353                 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3354                    BIGMAC_REGISTER_RX_STAT_GRIPJ */
3355                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3356                 dmae->opcode = opcode;
3357                 dmae->src_addr_lo = (mac_addr +
3358                                      BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3359                 dmae->src_addr_hi = 0;
3360                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3361                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3362                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3363                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3364                 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3365                              BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3366                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3367                 dmae->comp_addr_hi = 0;
3368                 dmae->comp_val = 1;
3369
3370         } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
3371
3372                 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3373
3374                 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3375                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3376                 dmae->opcode = opcode;
3377                 dmae->src_addr_lo = (mac_addr +
3378                                      EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3379                 dmae->src_addr_hi = 0;
3380                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3381                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3382                 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3383                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3384                 dmae->comp_addr_hi = 0;
3385                 dmae->comp_val = 1;
3386
3387                 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3388                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3389                 dmae->opcode = opcode;
3390                 dmae->src_addr_lo = (mac_addr +
3391                                      EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3392                 dmae->src_addr_hi = 0;
3393                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3394                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3395                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3396                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3397                 dmae->len = 1;
3398                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3399                 dmae->comp_addr_hi = 0;
3400                 dmae->comp_val = 1;
3401
3402                 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3403                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3404                 dmae->opcode = opcode;
3405                 dmae->src_addr_lo = (mac_addr +
3406                                      EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3407                 dmae->src_addr_hi = 0;
3408                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3409                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3410                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3411                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3412                 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3413                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3414                 dmae->comp_addr_hi = 0;
3415                 dmae->comp_val = 1;
3416         }
3417
3418         /* NIG */
3419         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3420         dmae->opcode = opcode;
3421         dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3422                                     NIG_REG_STAT0_BRB_DISCARD) >> 2;
3423         dmae->src_addr_hi = 0;
3424         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
3425         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
3426         dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
3427         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3428         dmae->comp_addr_hi = 0;
3429         dmae->comp_val = 1;
3430
3431         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3432         dmae->opcode = opcode;
3433         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
3434                                     NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
3435         dmae->src_addr_hi = 0;
3436         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3437                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3438         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3439                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3440         dmae->len = (2*sizeof(u32)) >> 2;
3441         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3442         dmae->comp_addr_hi = 0;
3443         dmae->comp_val = 1;
3444
3445         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3446         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3447                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3448                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3449 #ifdef __BIG_ENDIAN
3450                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3451 #else
3452                         DMAE_CMD_ENDIANITY_DW_SWAP |
3453 #endif
3454                         (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3455                         (vn << DMAE_CMD_E1HVN_SHIFT));
3456         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
3457                                     NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
3458         dmae->src_addr_hi = 0;
3459         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3460                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3461         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3462                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3463         dmae->len = (2*sizeof(u32)) >> 2;
3464         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3465         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3466         dmae->comp_val = DMAE_COMP_VAL;
3467
3468         *stats_comp = 0;
3469 }
3470
3471 static void bnx2x_func_stats_init(struct bnx2x *bp)
3472 {
3473         struct dmae_command *dmae = &bp->stats_dmae;
3474         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3475
3476         /* sanity */
3477         if (!bp->func_stx) {
3478                 BNX2X_ERR("BUG!\n");
3479                 return;
3480         }
3481
3482         bp->executer_idx = 0;
3483         memset(dmae, 0, sizeof(struct dmae_command));
3484
3485         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3486                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3487                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3488 #ifdef __BIG_ENDIAN
3489                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3490 #else
3491                         DMAE_CMD_ENDIANITY_DW_SWAP |
3492 #endif
3493                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3494                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3495         dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3496         dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3497         dmae->dst_addr_lo = bp->func_stx >> 2;
3498         dmae->dst_addr_hi = 0;
3499         dmae->len = sizeof(struct host_func_stats) >> 2;
3500         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3501         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3502         dmae->comp_val = DMAE_COMP_VAL;
3503
3504         *stats_comp = 0;
3505 }
3506
3507 static void bnx2x_stats_start(struct bnx2x *bp)
3508 {
3509         if (bp->port.pmf)
3510                 bnx2x_port_stats_init(bp);
3511
3512         else if (bp->func_stx)
3513                 bnx2x_func_stats_init(bp);
3514
3515         bnx2x_hw_stats_post(bp);
3516         bnx2x_storm_stats_post(bp);
3517 }
3518
3519 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
3520 {
3521         bnx2x_stats_comp(bp);
3522         bnx2x_stats_pmf_update(bp);
3523         bnx2x_stats_start(bp);
3524 }
3525
3526 static void bnx2x_stats_restart(struct bnx2x *bp)
3527 {
3528         bnx2x_stats_comp(bp);
3529         bnx2x_stats_start(bp);
3530 }
3531
3532 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3533 {
3534         struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
3535         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3536         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3537         struct regpair diff;
3538
3539         UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
3540         UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
3541         UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
3542         UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3543         UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3544         UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3545         UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3546         UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3547         UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf);
3548         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
3549         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
3550         UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
3551         UPDATE_STAT64(tx_stat_gt127,
3552                                 tx_stat_etherstatspkts65octetsto127octets);
3553         UPDATE_STAT64(tx_stat_gt255,
3554                                 tx_stat_etherstatspkts128octetsto255octets);
3555         UPDATE_STAT64(tx_stat_gt511,
3556                                 tx_stat_etherstatspkts256octetsto511octets);
3557         UPDATE_STAT64(tx_stat_gt1023,
3558                                 tx_stat_etherstatspkts512octetsto1023octets);
3559         UPDATE_STAT64(tx_stat_gt1518,
3560                                 tx_stat_etherstatspkts1024octetsto1522octets);
3561         UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
3562         UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
3563         UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
3564         UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
3565         UPDATE_STAT64(tx_stat_gterr,
3566                                 tx_stat_dot3statsinternalmactransmiterrors);
3567         UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
3568
3569         estats->pause_frames_received_hi =
3570                                 pstats->mac_stx[1].rx_stat_bmac_xpf_hi;
3571         estats->pause_frames_received_lo =
3572                                 pstats->mac_stx[1].rx_stat_bmac_xpf_lo;
3573
3574         estats->pause_frames_sent_hi =
3575                                 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
3576         estats->pause_frames_sent_lo =
3577                                 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
3578 }
3579
3580 static void bnx2x_emac_stats_update(struct bnx2x *bp)
3581 {
3582         struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
3583         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3584         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3585
3586         UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
3587         UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
3588         UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
3589         UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
3590         UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
3591         UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
3592         UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
3593         UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
3594         UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
3595         UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
3596         UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
3597         UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
3598         UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
3599         UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
3600         UPDATE_EXTEND_STAT(tx_stat_outxonsent);
3601         UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
3602         UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
3603         UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
3604         UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
3605         UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
3606         UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
3607         UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
3608         UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
3609         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
3610         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
3611         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
3612         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
3613         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
3614         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
3615         UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
3616         UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
3617
3618         estats->pause_frames_received_hi =
3619                         pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
3620         estats->pause_frames_received_lo =
3621                         pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
3622         ADD_64(estats->pause_frames_received_hi,
3623                pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
3624                estats->pause_frames_received_lo,
3625                pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
3626
3627         estats->pause_frames_sent_hi =
3628                         pstats->mac_stx[1].tx_stat_outxonsent_hi;
3629         estats->pause_frames_sent_lo =
3630                         pstats->mac_stx[1].tx_stat_outxonsent_lo;
3631         ADD_64(estats->pause_frames_sent_hi,
3632                pstats->mac_stx[1].tx_stat_outxoffsent_hi,
3633                estats->pause_frames_sent_lo,
3634                pstats->mac_stx[1].tx_stat_outxoffsent_lo);
3635 }
3636
3637 static int bnx2x_hw_stats_update(struct bnx2x *bp)
3638 {
3639         struct nig_stats *new = bnx2x_sp(bp, nig_stats);
3640         struct nig_stats *old = &(bp->port.old_nig_stats);
3641         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3642         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3643         struct regpair diff;
3644         u32 nig_timer_max;
3645
3646         if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
3647                 bnx2x_bmac_stats_update(bp);
3648
3649         else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
3650                 bnx2x_emac_stats_update(bp);
3651
3652         else { /* unreached */
3653                 BNX2X_ERR("stats updated by dmae but no MAC active\n");
3654                 return -1;
3655         }
3656
3657         ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3658                       new->brb_discard - old->brb_discard);
3659         ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3660                       new->brb_truncate - old->brb_truncate);
3661
3662         UPDATE_STAT64_NIG(egress_mac_pkt0,
3663                                         etherstatspkts1024octetsto1522octets);
3664         UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
3665
3666         memcpy(old, new, sizeof(struct nig_stats));
3667
3668         memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
3669                sizeof(struct mac_stx));
3670         estats->brb_drop_hi = pstats->brb_drop_hi;
3671         estats->brb_drop_lo = pstats->brb_drop_lo;
3672
3673         pstats->host_port_stats_start = ++pstats->host_port_stats_end;
3674
3675         nig_timer_max = SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
3676         if (nig_timer_max != estats->nig_timer_max) {
3677                 estats->nig_timer_max = nig_timer_max;
3678                 BNX2X_ERR("NIG timer max (%u)\n", estats->nig_timer_max);
3679         }
3680
3681         return 0;
3682 }
3683
3684 static int bnx2x_storm_stats_update(struct bnx2x *bp)
3685 {
3686         struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
3687         struct tstorm_per_port_stats *tport =
3688                                         &stats->tstorm_common.port_statistics;
3689         struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
3690         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3691         int i;
3692
3693         memset(&(fstats->total_bytes_received_hi), 0,
3694                sizeof(struct host_func_stats) - 2*sizeof(u32));
3695         estats->error_bytes_received_hi = 0;
3696         estats->error_bytes_received_lo = 0;
3697         estats->etherstatsoverrsizepkts_hi = 0;
3698         estats->etherstatsoverrsizepkts_lo = 0;
3699         estats->no_buff_discard_hi = 0;
3700         estats->no_buff_discard_lo = 0;
3701
3702         for_each_queue(bp, i) {
3703                 struct bnx2x_fastpath *fp = &bp->fp[i];
3704                 int cl_id = fp->cl_id;
3705                 struct tstorm_per_client_stats *tclient =
3706                                 &stats->tstorm_common.client_statistics[cl_id];
3707                 struct tstorm_per_client_stats *old_tclient = &fp->old_tclient;
3708                 struct ustorm_per_client_stats *uclient =
3709                                 &stats->ustorm_common.client_statistics[cl_id];
3710                 struct ustorm_per_client_stats *old_uclient = &fp->old_uclient;
3711                 struct xstorm_per_client_stats *xclient =
3712                                 &stats->xstorm_common.client_statistics[cl_id];
3713                 struct xstorm_per_client_stats *old_xclient = &fp->old_xclient;
3714                 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
3715                 u32 diff;
3716
3717                 /* are storm stats valid? */
3718                 if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
3719                                                         bp->stats_counter) {
3720                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by xstorm"
3721                            "  xstorm counter (%d) != stats_counter (%d)\n",
3722                            i, xclient->stats_counter, bp->stats_counter);
3723                         return -1;
3724                 }
3725                 if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
3726                                                         bp->stats_counter) {
3727                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by tstorm"
3728                            "  tstorm counter (%d) != stats_counter (%d)\n",
3729                            i, tclient->stats_counter, bp->stats_counter);
3730                         return -2;
3731                 }
3732                 if ((u16)(le16_to_cpu(uclient->stats_counter) + 1) !=
3733                                                         bp->stats_counter) {
3734                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by ustorm"
3735                            "  ustorm counter (%d) != stats_counter (%d)\n",
3736                            i, uclient->stats_counter, bp->stats_counter);
3737                         return -4;
3738                 }
3739
3740                 qstats->total_bytes_received_hi =
3741                 qstats->valid_bytes_received_hi =
3742                                 le32_to_cpu(tclient->total_rcv_bytes.hi);
3743                 qstats->total_bytes_received_lo =
3744                 qstats->valid_bytes_received_lo =
3745                                 le32_to_cpu(tclient->total_rcv_bytes.lo);
3746
3747                 qstats->error_bytes_received_hi =
3748                                 le32_to_cpu(tclient->rcv_error_bytes.hi);
3749                 qstats->error_bytes_received_lo =
3750                                 le32_to_cpu(tclient->rcv_error_bytes.lo);
3751
3752                 ADD_64(qstats->total_bytes_received_hi,
3753                        qstats->error_bytes_received_hi,
3754                        qstats->total_bytes_received_lo,
3755                        qstats->error_bytes_received_lo);
3756
3757                 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
3758                                         total_unicast_packets_received);
3759                 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
3760                                         total_multicast_packets_received);
3761                 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
3762                                         total_broadcast_packets_received);
3763                 UPDATE_EXTEND_TSTAT(packets_too_big_discard,
3764                                         etherstatsoverrsizepkts);
3765                 UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
3766
3767                 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
3768                                         total_unicast_packets_received);
3769                 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
3770                                         total_multicast_packets_received);
3771                 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
3772                                         total_broadcast_packets_received);
3773                 UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
3774                 UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
3775                 UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
3776
3777                 qstats->total_bytes_transmitted_hi =
3778                                 le32_to_cpu(xclient->total_sent_bytes.hi);
3779                 qstats->total_bytes_transmitted_lo =
3780                                 le32_to_cpu(xclient->total_sent_bytes.lo);
3781
3782                 UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
3783                                         total_unicast_packets_transmitted);
3784                 UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
3785                                         total_multicast_packets_transmitted);
3786                 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
3787                                         total_broadcast_packets_transmitted);
3788
3789                 old_tclient->checksum_discard = tclient->checksum_discard;
3790                 old_tclient->ttl0_discard = tclient->ttl0_discard;
3791
3792                 ADD_64(fstats->total_bytes_received_hi,
3793                        qstats->total_bytes_received_hi,
3794                        fstats->total_bytes_received_lo,
3795                        qstats->total_bytes_received_lo);
3796                 ADD_64(fstats->total_bytes_transmitted_hi,
3797                        qstats->total_bytes_transmitted_hi,
3798                        fstats->total_bytes_transmitted_lo,
3799                        qstats->total_bytes_transmitted_lo);
3800                 ADD_64(fstats->total_unicast_packets_received_hi,
3801                        qstats->total_unicast_packets_received_hi,
3802                        fstats->total_unicast_packets_received_lo,
3803                        qstats->total_unicast_packets_received_lo);
3804                 ADD_64(fstats->total_multicast_packets_received_hi,
3805                        qstats->total_multicast_packets_received_hi,
3806                        fstats->total_multicast_packets_received_lo,
3807                        qstats->total_multicast_packets_received_lo);
3808                 ADD_64(fstats->total_broadcast_packets_received_hi,
3809                        qstats->total_broadcast_packets_received_hi,
3810                        fstats->total_broadcast_packets_received_lo,
3811                        qstats->total_broadcast_packets_received_lo);
3812                 ADD_64(fstats->total_unicast_packets_transmitted_hi,
3813                        qstats->total_unicast_packets_transmitted_hi,
3814                        fstats->total_unicast_packets_transmitted_lo,
3815                        qstats->total_unicast_packets_transmitted_lo);
3816                 ADD_64(fstats->total_multicast_packets_transmitted_hi,
3817                        qstats->total_multicast_packets_transmitted_hi,
3818                        fstats->total_multicast_packets_transmitted_lo,
3819                        qstats->total_multicast_packets_transmitted_lo);
3820                 ADD_64(fstats->total_broadcast_packets_transmitted_hi,
3821                        qstats->total_broadcast_packets_transmitted_hi,
3822                        fstats->total_broadcast_packets_transmitted_lo,
3823                        qstats->total_broadcast_packets_transmitted_lo);
3824                 ADD_64(fstats->valid_bytes_received_hi,
3825                        qstats->valid_bytes_received_hi,
3826                        fstats->valid_bytes_received_lo,
3827                        qstats->valid_bytes_received_lo);
3828
3829                 ADD_64(estats->error_bytes_received_hi,
3830                        qstats->error_bytes_received_hi,
3831                        estats->error_bytes_received_lo,
3832                        qstats->error_bytes_received_lo);
3833                 ADD_64(estats->etherstatsoverrsizepkts_hi,
3834                        qstats->etherstatsoverrsizepkts_hi,
3835                        estats->etherstatsoverrsizepkts_lo,
3836                        qstats->etherstatsoverrsizepkts_lo);
3837                 ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
3838                        estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
3839         }
3840
3841         ADD_64(fstats->total_bytes_received_hi,
3842                estats->rx_stat_ifhcinbadoctets_hi,
3843                fstats->total_bytes_received_lo,
3844                estats->rx_stat_ifhcinbadoctets_lo);
3845
3846         memcpy(estats, &(fstats->total_bytes_received_hi),
3847                sizeof(struct host_func_stats) - 2*sizeof(u32));
3848
3849         ADD_64(estats->etherstatsoverrsizepkts_hi,
3850                estats->rx_stat_dot3statsframestoolong_hi,
3851                estats->etherstatsoverrsizepkts_lo,
3852                estats->rx_stat_dot3statsframestoolong_lo);
3853         ADD_64(estats->error_bytes_received_hi,
3854                estats->rx_stat_ifhcinbadoctets_hi,
3855                estats->error_bytes_received_lo,
3856                estats->rx_stat_ifhcinbadoctets_lo);
3857
3858         if (bp->port.pmf) {
3859                 estats->mac_filter_discard =
3860                                 le32_to_cpu(tport->mac_filter_discard);
3861                 estats->xxoverflow_discard =
3862                                 le32_to_cpu(tport->xxoverflow_discard);
3863                 estats->brb_truncate_discard =
3864                                 le32_to_cpu(tport->brb_truncate_discard);
3865                 estats->mac_discard = le32_to_cpu(tport->mac_discard);
3866         }
3867
3868         fstats->host_func_stats_start = ++fstats->host_func_stats_end;
3869
3870         bp->stats_pending = 0;
3871
3872         return 0;
3873 }
3874
3875 static void bnx2x_net_stats_update(struct bnx2x *bp)
3876 {
3877         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3878         struct net_device_stats *nstats = &bp->dev->stats;
3879         int i;
3880
3881         nstats->rx_packets =
3882                 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
3883                 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
3884                 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
3885
3886         nstats->tx_packets =
3887                 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
3888                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
3889                 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
3890
3891         nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
3892
3893         nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
3894
3895         nstats->rx_dropped = estats->mac_discard;
3896         for_each_queue(bp, i)
3897                 nstats->rx_dropped +=
3898                         le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
3899
3900         nstats->tx_dropped = 0;
3901
3902         nstats->multicast =
3903                 bnx2x_hilo(&estats->total_multicast_packets_received_hi);
3904
3905         nstats->collisions =
3906                 bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
3907
3908         nstats->rx_length_errors =
3909                 bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
3910                 bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
3911         nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
3912                                  bnx2x_hilo(&estats->brb_truncate_hi);
3913         nstats->rx_crc_errors =
3914                 bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
3915         nstats->rx_frame_errors =
3916                 bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
3917         nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
3918         nstats->rx_missed_errors = estats->xxoverflow_discard;
3919
3920         nstats->rx_errors = nstats->rx_length_errors +
3921                             nstats->rx_over_errors +
3922                             nstats->rx_crc_errors +
3923                             nstats->rx_frame_errors +
3924                             nstats->rx_fifo_errors +
3925                             nstats->rx_missed_errors;
3926
3927         nstats->tx_aborted_errors =
3928                 bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
3929                 bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
3930         nstats->tx_carrier_errors =
3931                 bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
3932         nstats->tx_fifo_errors = 0;
3933         nstats->tx_heartbeat_errors = 0;
3934         nstats->tx_window_errors = 0;
3935
3936         nstats->tx_errors = nstats->tx_aborted_errors +
3937                             nstats->tx_carrier_errors +
3938             bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
3939 }
3940
3941 static void bnx2x_drv_stats_update(struct bnx2x *bp)
3942 {
3943         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3944         int i;
3945
3946         estats->driver_xoff = 0;
3947         estats->rx_err_discard_pkt = 0;
3948         estats->rx_skb_alloc_failed = 0;
3949         estats->hw_csum_err = 0;
3950         for_each_queue(bp, i) {
3951                 struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
3952
3953                 estats->driver_xoff += qstats->driver_xoff;
3954                 estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
3955                 estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
3956                 estats->hw_csum_err += qstats->hw_csum_err;
3957         }
3958 }
3959
3960 static void bnx2x_stats_update(struct bnx2x *bp)
3961 {
3962         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3963
3964         if (*stats_comp != DMAE_COMP_VAL)
3965                 return;
3966
3967         if (bp->port.pmf)
3968                 bnx2x_hw_stats_update(bp);
3969
3970         if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
3971                 BNX2X_ERR("storm stats were not updated for 3 times\n");
3972                 bnx2x_panic();
3973                 return;
3974         }
3975
3976         bnx2x_net_stats_update(bp);
3977         bnx2x_drv_stats_update(bp);
3978
3979         if (bp->msglevel & NETIF_MSG_TIMER) {
3980                 struct tstorm_per_client_stats *old_tclient =
3981                                                         &bp->fp->old_tclient;
3982                 struct bnx2x_eth_q_stats *qstats = &bp->fp->eth_q_stats;
3983                 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3984                 struct net_device_stats *nstats = &bp->dev->stats;
3985                 int i;
3986
3987                 printk(KERN_DEBUG "%s:\n", bp->dev->name);
3988                 printk(KERN_DEBUG "  tx avail (%4x)  tx hc idx (%x)"
3989                                   "  tx pkt (%lx)\n",
3990                        bnx2x_tx_avail(bp->fp),
3991                        le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
3992                 printk(KERN_DEBUG "  rx usage (%4x)  rx hc idx (%x)"
3993                                   "  rx pkt (%lx)\n",
3994                        (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
3995                              bp->fp->rx_comp_cons),
3996                        le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3997                 printk(KERN_DEBUG "  %s (Xoff events %u)  brb drops %u  "
3998                                   "brb truncate %u\n",
3999                        (netif_queue_stopped(bp->dev) ? "Xoff" : "Xon"),
4000                        qstats->driver_xoff,
4001                        estats->brb_drop_lo, estats->brb_truncate_lo);
4002                 printk(KERN_DEBUG "tstats: checksum_discard %u  "
4003                         "packets_too_big_discard %lu  no_buff_discard %lu  "
4004                         "mac_discard %u  mac_filter_discard %u  "
4005                         "xxovrflow_discard %u  brb_truncate_discard %u  "
4006                         "ttl0_discard %u\n",
4007                        old_tclient->checksum_discard,
4008                        bnx2x_hilo(&qstats->etherstatsoverrsizepkts_hi),
4009                        bnx2x_hilo(&qstats->no_buff_discard_hi),
4010                        estats->mac_discard, estats->mac_filter_discard,
4011                        estats->xxoverflow_discard, estats->brb_truncate_discard,
4012                        old_tclient->ttl0_discard);
4013
4014                 for_each_queue(bp, i) {
4015                         printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
4016                                bnx2x_fp(bp, i, tx_pkt),
4017                                bnx2x_fp(bp, i, rx_pkt),
4018                                bnx2x_fp(bp, i, rx_calls));
4019                 }
4020         }
4021
4022         bnx2x_hw_stats_post(bp);
4023         bnx2x_storm_stats_post(bp);
4024 }
4025
4026 static void bnx2x_port_stats_stop(struct bnx2x *bp)
4027 {
4028         struct dmae_command *dmae;
4029         u32 opcode;
4030         int loader_idx = PMF_DMAE_C(bp);
4031         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
4032
4033         bp->executer_idx = 0;
4034
4035         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
4036                   DMAE_CMD_C_ENABLE |
4037                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4038 #ifdef __BIG_ENDIAN
4039                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
4040 #else
4041                   DMAE_CMD_ENDIANITY_DW_SWAP |
4042 #endif
4043                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
4044                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
4045
4046         if (bp->port.port_stx) {
4047
4048                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4049                 if (bp->func_stx)
4050                         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
4051                 else
4052                         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
4053                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
4054                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
4055                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
4056                 dmae->dst_addr_hi = 0;
4057                 dmae->len = sizeof(struct host_port_stats) >> 2;
4058                 if (bp->func_stx) {
4059                         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4060                         dmae->comp_addr_hi = 0;
4061                         dmae->comp_val = 1;
4062                 } else {
4063                         dmae->comp_addr_lo =
4064                                 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4065                         dmae->comp_addr_hi =
4066                                 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4067                         dmae->comp_val = DMAE_COMP_VAL;
4068
4069                         *stats_comp = 0;
4070                 }
4071         }
4072
4073         if (bp->func_stx) {
4074
4075                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4076                 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
4077                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
4078                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
4079                 dmae->dst_addr_lo = bp->func_stx >> 2;
4080                 dmae->dst_addr_hi = 0;
4081                 dmae->len = sizeof(struct host_func_stats) >> 2;
4082                 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4083                 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4084                 dmae->comp_val = DMAE_COMP_VAL;
4085
4086                 *stats_comp = 0;
4087         }
4088 }
4089
4090 static void bnx2x_stats_stop(struct bnx2x *bp)
4091 {
4092         int update = 0;
4093
4094         bnx2x_stats_comp(bp);
4095
4096         if (bp->port.pmf)
4097                 update = (bnx2x_hw_stats_update(bp) == 0);
4098
4099         update |= (bnx2x_storm_stats_update(bp) == 0);
4100
4101         if (update) {
4102                 bnx2x_net_stats_update(bp);
4103
4104                 if (bp->port.pmf)
4105                         bnx2x_port_stats_stop(bp);
4106
4107                 bnx2x_hw_stats_post(bp);
4108                 bnx2x_stats_comp(bp);
4109         }
4110 }
4111
4112 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
4113 {
4114 }
4115
4116 static const struct {
4117         void (*action)(struct bnx2x *bp);
4118         enum bnx2x_stats_state next_state;
4119 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
4120 /* state        event   */
4121 {
4122 /* DISABLED     PMF     */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
4123 /*              LINK_UP */ {bnx2x_stats_start,      STATS_STATE_ENABLED},
4124 /*              UPDATE  */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
4125 /*              STOP    */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
4126 },
4127 {
4128 /* ENABLED      PMF     */ {bnx2x_stats_pmf_start,  STATS_STATE_ENABLED},
4129 /*              LINK_UP */ {bnx2x_stats_restart,    STATS_STATE_ENABLED},
4130 /*              UPDATE  */ {bnx2x_stats_update,     STATS_STATE_ENABLED},
4131 /*              STOP    */ {bnx2x_stats_stop,       STATS_STATE_DISABLED}
4132 }
4133 };
4134
4135 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
4136 {
4137         enum bnx2x_stats_state state = bp->stats_state;
4138
4139         bnx2x_stats_stm[state][event].action(bp);
4140         bp->stats_state = bnx2x_stats_stm[state][event].next_state;
4141
4142         if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
4143                 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
4144                    state, event, bp->stats_state);
4145 }
4146
4147 static void bnx2x_timer(unsigned long data)
4148 {
4149         struct bnx2x *bp = (struct bnx2x *) data;
4150
4151         if (!netif_running(bp->dev))
4152                 return;
4153
4154         if (atomic_read(&bp->intr_sem) != 0)
4155                 goto timer_restart;
4156
4157         if (poll) {
4158                 struct bnx2x_fastpath *fp = &bp->fp[0];
4159                 int rc;
4160
4161                 bnx2x_tx_int(fp, 1000);
4162                 rc = bnx2x_rx_int(fp, 1000);
4163         }
4164
4165         if (!BP_NOMCP(bp)) {
4166                 int func = BP_FUNC(bp);
4167                 u32 drv_pulse;
4168                 u32 mcp_pulse;
4169
4170                 ++bp->fw_drv_pulse_wr_seq;
4171                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4172                 /* TBD - add SYSTEM_TIME */
4173                 drv_pulse = bp->fw_drv_pulse_wr_seq;
4174                 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
4175
4176                 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
4177                              MCP_PULSE_SEQ_MASK);
4178                 /* The delta between driver pulse and mcp response
4179                  * should be 1 (before mcp response) or 0 (after mcp response)
4180                  */
4181                 if ((drv_pulse != mcp_pulse) &&
4182                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4183                         /* someone lost a heartbeat... */
4184                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4185                                   drv_pulse, mcp_pulse);
4186                 }
4187         }
4188
4189         if ((bp->state == BNX2X_STATE_OPEN) ||
4190             (bp->state == BNX2X_STATE_DISABLED))
4191                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4192
4193 timer_restart:
4194         mod_timer(&bp->timer, jiffies + bp->current_interval);
4195 }
4196
4197 /* end of Statistics */
4198
4199 /* nic init */
4200
4201 /*
4202  * nic init service functions
4203  */
4204
4205 static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
4206 {
4207         int port = BP_PORT(bp);
4208
4209         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4210                         USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4211                         sizeof(struct ustorm_status_block)/4);
4212         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4213                         CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4214                         sizeof(struct cstorm_status_block)/4);
4215 }
4216
4217 static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4218                           dma_addr_t mapping, int sb_id)
4219 {
4220         int port = BP_PORT(bp);
4221         int func = BP_FUNC(bp);
4222         int index;
4223         u64 section;
4224
4225         /* USTORM */
4226         section = ((u64)mapping) + offsetof(struct host_status_block,
4227                                             u_status_block);
4228         sb->u_status_block.status_block_id = sb_id;
4229
4230         REG_WR(bp, BAR_USTRORM_INTMEM +
4231                USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4232         REG_WR(bp, BAR_USTRORM_INTMEM +
4233                ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4234                U64_HI(section));
4235         REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
4236                 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4237
4238         for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4239                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4240                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4241
4242         /* CSTORM */
4243         section = ((u64)mapping) + offsetof(struct host_status_block,
4244                                             c_status_block);
4245         sb->c_status_block.status_block_id = sb_id;
4246
4247         REG_WR(bp, BAR_CSTRORM_INTMEM +
4248                CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4249         REG_WR(bp, BAR_CSTRORM_INTMEM +
4250                ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4251                U64_HI(section));
4252         REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
4253                 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4254
4255         for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4256                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4257                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4258
4259         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4260 }
4261
4262 static void bnx2x_zero_def_sb(struct bnx2x *bp)
4263 {
4264         int func = BP_FUNC(bp);
4265
4266         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4267                         USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4268                         sizeof(struct ustorm_def_status_block)/4);
4269         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4270                         CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4271                         sizeof(struct cstorm_def_status_block)/4);
4272         bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
4273                         XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4274                         sizeof(struct xstorm_def_status_block)/4);
4275         bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4276                         TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4277                         sizeof(struct tstorm_def_status_block)/4);
4278 }
4279
4280 static void bnx2x_init_def_sb(struct bnx2x *bp,
4281                               struct host_def_status_block *def_sb,
4282                               dma_addr_t mapping, int sb_id)
4283 {
4284         int port = BP_PORT(bp);
4285         int func = BP_FUNC(bp);
4286         int index, val, reg_offset;
4287         u64 section;
4288
4289         /* ATTN */
4290         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4291                                             atten_status_block);
4292         def_sb->atten_status_block.status_block_id = sb_id;
4293
4294         bp->attn_state = 0;
4295
4296         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4297                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4298
4299         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4300                 bp->attn_group[index].sig[0] = REG_RD(bp,
4301                                                      reg_offset + 0x10*index);
4302                 bp->attn_group[index].sig[1] = REG_RD(bp,
4303                                                reg_offset + 0x4 + 0x10*index);
4304                 bp->attn_group[index].sig[2] = REG_RD(bp,
4305                                                reg_offset + 0x8 + 0x10*index);
4306                 bp->attn_group[index].sig[3] = REG_RD(bp,
4307                                                reg_offset + 0xc + 0x10*index);
4308         }
4309
4310         reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4311                              HC_REG_ATTN_MSG0_ADDR_L);
4312
4313         REG_WR(bp, reg_offset, U64_LO(section));
4314         REG_WR(bp, reg_offset + 4, U64_HI(section));
4315
4316         reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4317
4318         val = REG_RD(bp, reg_offset);
4319         val |= sb_id;
4320         REG_WR(bp, reg_offset, val);
4321
4322         /* USTORM */
4323         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4324                                             u_def_status_block);
4325         def_sb->u_def_status_block.status_block_id = sb_id;
4326
4327         REG_WR(bp, BAR_USTRORM_INTMEM +
4328                USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4329         REG_WR(bp, BAR_USTRORM_INTMEM +
4330                ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4331                U64_HI(section));
4332         REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4333                 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4334
4335         for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4336                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4337                          USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4338
4339         /* CSTORM */
4340         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4341                                             c_def_status_block);
4342         def_sb->c_def_status_block.status_block_id = sb_id;
4343
4344         REG_WR(bp, BAR_CSTRORM_INTMEM +
4345                CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4346         REG_WR(bp, BAR_CSTRORM_INTMEM +
4347                ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4348                U64_HI(section));
4349         REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4350                 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4351
4352         for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4353                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4354                          CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4355
4356         /* TSTORM */
4357         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4358                                             t_def_status_block);
4359         def_sb->t_def_status_block.status_block_id = sb_id;
4360
4361         REG_WR(bp, BAR_TSTRORM_INTMEM +
4362                TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4363         REG_WR(bp, BAR_TSTRORM_INTMEM +
4364                ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4365                U64_HI(section));
4366         REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4367                 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4368
4369         for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4370                 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4371                          TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4372
4373         /* XSTORM */
4374         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4375                                             x_def_status_block);
4376         def_sb->x_def_status_block.status_block_id = sb_id;
4377
4378         REG_WR(bp, BAR_XSTRORM_INTMEM +
4379                XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4380         REG_WR(bp, BAR_XSTRORM_INTMEM +
4381                ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4382                U64_HI(section));
4383         REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4384                 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4385
4386         for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4387                 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4388                          XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4389
4390         bp->stats_pending = 0;
4391         bp->set_mac_pending = 0;
4392
4393         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4394 }
4395
4396 static void bnx2x_update_coalesce(struct bnx2x *bp)
4397 {
4398         int port = BP_PORT(bp);
4399         int i;
4400
4401         for_each_queue(bp, i) {
4402                 int sb_id = bp->fp[i].sb_id;
4403
4404                 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4405                 REG_WR8(bp, BAR_USTRORM_INTMEM +
4406                         USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4407                                                     U_SB_ETH_RX_CQ_INDEX),
4408                         bp->rx_ticks/12);
4409                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4410                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4411                                                      U_SB_ETH_RX_CQ_INDEX),
4412                          bp->rx_ticks ? 0 : 1);
4413
4414                 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4415                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4416                         CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4417                                                     C_SB_ETH_TX_CQ_INDEX),
4418                         bp->tx_ticks/12);
4419                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4420                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4421                                                      C_SB_ETH_TX_CQ_INDEX),
4422                          bp->tx_ticks ? 0 : 1);
4423         }
4424 }
4425
4426 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4427                                        struct bnx2x_fastpath *fp, int last)
4428 {
4429         int i;
4430
4431         for (i = 0; i < last; i++) {
4432                 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
4433                 struct sk_buff *skb = rx_buf->skb;
4434
4435                 if (skb == NULL) {
4436                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
4437                         continue;
4438                 }
4439
4440                 if (fp->tpa_state[i] == BNX2X_TPA_START)
4441                         pci_unmap_single(bp->pdev,
4442                                          pci_unmap_addr(rx_buf, mapping),
4443                                          bp->rx_buf_size,
4444                                          PCI_DMA_FROMDEVICE);
4445
4446                 dev_kfree_skb(skb);
4447                 rx_buf->skb = NULL;
4448         }
4449 }
4450
4451 static void bnx2x_init_rx_rings(struct bnx2x *bp)
4452 {
4453         int func = BP_FUNC(bp);
4454         int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4455                                               ETH_MAX_AGGREGATION_QUEUES_E1H;
4456         u16 ring_prod, cqe_ring_prod;
4457         int i, j;
4458
4459         bp->rx_buf_size += bp->rx_offset + ETH_OVREHEAD + BNX2X_RX_ALIGN;
4460         DP(NETIF_MSG_IFUP,
4461            "mtu %d  rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size);
4462
4463         if (bp->flags & TPA_ENABLE_FLAG) {
4464
4465                 for_each_rx_queue(bp, j) {
4466                         struct bnx2x_fastpath *fp = &bp->fp[j];
4467
4468                         for (i = 0; i < max_agg_queues; i++) {
4469                                 fp->tpa_pool[i].skb =
4470                                    netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4471                                 if (!fp->tpa_pool[i].skb) {
4472                                         BNX2X_ERR("Failed to allocate TPA "
4473                                                   "skb pool for queue[%d] - "
4474                                                   "disabling TPA on this "
4475                                                   "queue!\n", j);
4476                                         bnx2x_free_tpa_pool(bp, fp, i);
4477                                         fp->disable_tpa = 1;
4478                                         break;
4479                                 }
4480                                 pci_unmap_addr_set((struct sw_rx_bd *)
4481                                                         &bp->fp->tpa_pool[i],
4482                                                    mapping, 0);
4483                                 fp->tpa_state[i] = BNX2X_TPA_STOP;
4484                         }
4485                 }
4486         }
4487
4488         for_each_rx_queue(bp, j) {
4489                 struct bnx2x_fastpath *fp = &bp->fp[j];
4490
4491                 fp->rx_bd_cons = 0;
4492                 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4493                 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
4494
4495                 /* "next page" elements initialization */
4496                 /* SGE ring */
4497                 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
4498                         struct eth_rx_sge *sge;
4499
4500                         sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
4501                         sge->addr_hi =
4502                                 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
4503                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4504                         sge->addr_lo =
4505                                 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
4506                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4507                 }
4508
4509                 bnx2x_init_sge_ring_bit_mask(fp);
4510
4511                 /* RX BD ring */
4512                 for (i = 1; i <= NUM_RX_RINGS; i++) {
4513                         struct eth_rx_bd *rx_bd;
4514
4515                         rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4516                         rx_bd->addr_hi =
4517                                 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4518                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4519                         rx_bd->addr_lo =
4520                                 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4521                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4522                 }
4523
4524                 /* CQ ring */
4525                 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4526                         struct eth_rx_cqe_next_page *nextpg;
4527
4528                         nextpg = (struct eth_rx_cqe_next_page *)
4529                                 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4530                         nextpg->addr_hi =
4531                                 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4532                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4533                         nextpg->addr_lo =
4534                                 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4535                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4536                 }
4537
4538                 /* Allocate SGEs and initialize the ring elements */
4539                 for (i = 0, ring_prod = 0;
4540                      i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4541
4542                         if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
4543                                 BNX2X_ERR("was only able to allocate "
4544                                           "%d rx sges\n", i);
4545                                 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4546                                 /* Cleanup already allocated elements */
4547                                 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4548                                 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4549                                 fp->disable_tpa = 1;
4550                                 ring_prod = 0;
4551                                 break;
4552                         }
4553                         ring_prod = NEXT_SGE_IDX(ring_prod);
4554                 }
4555                 fp->rx_sge_prod = ring_prod;
4556
4557                 /* Allocate BDs and initialize BD ring */
4558                 fp->rx_comp_cons = 0;
4559                 cqe_ring_prod = ring_prod = 0;
4560                 for (i = 0; i < bp->rx_ring_size; i++) {
4561                         if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4562                                 BNX2X_ERR("was only able to allocate "
4563                                           "%d rx skbs on queue[%d]\n", i, j);
4564                                 fp->eth_q_stats.rx_skb_alloc_failed++;
4565                                 break;
4566                         }
4567                         ring_prod = NEXT_RX_IDX(ring_prod);
4568                         cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4569                         WARN_ON(ring_prod <= i);
4570                 }
4571
4572                 fp->rx_bd_prod = ring_prod;
4573                 /* must not have more available CQEs than BDs */
4574                 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
4575                                        cqe_ring_prod);
4576                 fp->rx_pkt = fp->rx_calls = 0;
4577
4578                 /* Warning!
4579                  * this will generate an interrupt (to the TSTORM)
4580                  * must only be done after chip is initialized
4581                  */
4582                 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
4583                                      fp->rx_sge_prod);
4584                 if (j != 0)
4585                         continue;
4586
4587                 REG_WR(bp, BAR_USTRORM_INTMEM +
4588                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
4589                        U64_LO(fp->rx_comp_mapping));
4590                 REG_WR(bp, BAR_USTRORM_INTMEM +
4591                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
4592                        U64_HI(fp->rx_comp_mapping));
4593         }
4594 }
4595
4596 static void bnx2x_init_tx_ring(struct bnx2x *bp)
4597 {
4598         int i, j;
4599
4600         for_each_tx_queue(bp, j) {
4601                 struct bnx2x_fastpath *fp = &bp->fp[j];
4602
4603                 for (i = 1; i <= NUM_TX_RINGS; i++) {
4604                         struct eth_tx_bd *tx_bd =
4605                                 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4606
4607                         tx_bd->addr_hi =
4608                                 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4609                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4610                         tx_bd->addr_lo =
4611                                 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4612                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4613                 }
4614
4615                 fp->tx_pkt_prod = 0;
4616                 fp->tx_pkt_cons = 0;
4617                 fp->tx_bd_prod = 0;
4618                 fp->tx_bd_cons = 0;
4619                 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4620                 fp->tx_pkt = 0;
4621         }
4622 }
4623
4624 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4625 {
4626         int func = BP_FUNC(bp);
4627
4628         spin_lock_init(&bp->spq_lock);
4629
4630         bp->spq_left = MAX_SPQ_PENDING;
4631         bp->spq_prod_idx = 0;
4632         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4633         bp->spq_prod_bd = bp->spq;
4634         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4635
4636         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4637                U64_LO(bp->spq_mapping));
4638         REG_WR(bp,
4639                XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
4640                U64_HI(bp->spq_mapping));
4641
4642         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
4643                bp->spq_prod_idx);
4644 }
4645
4646 static void bnx2x_init_context(struct bnx2x *bp)
4647 {
4648         int i;
4649
4650         for_each_queue(bp, i) {
4651                 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4652                 struct bnx2x_fastpath *fp = &bp->fp[i];
4653                 u8 cl_id = fp->cl_id;
4654                 u8 sb_id = FP_SB_ID(fp);
4655
4656                 context->ustorm_st_context.common.sb_index_numbers =
4657                                                 BNX2X_RX_SB_INDEX_NUM;
4658                 context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
4659                 context->ustorm_st_context.common.status_block_id = sb_id;
4660                 context->ustorm_st_context.common.flags =
4661                         (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT |
4662                          USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS);
4663                 context->ustorm_st_context.common.statistics_counter_id =
4664                                                 cl_id;
4665                 context->ustorm_st_context.common.mc_alignment_log_size =
4666                                                 BNX2X_RX_ALIGN_SHIFT;
4667                 context->ustorm_st_context.common.bd_buff_size =
4668                                                 bp->rx_buf_size;
4669                 context->ustorm_st_context.common.bd_page_base_hi =
4670                                                 U64_HI(fp->rx_desc_mapping);
4671                 context->ustorm_st_context.common.bd_page_base_lo =
4672                                                 U64_LO(fp->rx_desc_mapping);
4673                 if (!fp->disable_tpa) {
4674                         context->ustorm_st_context.common.flags |=
4675                                 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
4676                                  USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
4677                         context->ustorm_st_context.common.sge_buff_size =
4678                                 (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
4679                                          (u32)0xffff);
4680                         context->ustorm_st_context.common.sge_page_base_hi =
4681                                                 U64_HI(fp->rx_sge_mapping);
4682                         context->ustorm_st_context.common.sge_page_base_lo =
4683                                                 U64_LO(fp->rx_sge_mapping);
4684                 }
4685
4686                 context->ustorm_ag_context.cdu_usage =
4687                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4688                                                CDU_REGION_NUMBER_UCM_AG,
4689                                                ETH_CONNECTION_TYPE);
4690
4691                 context->xstorm_st_context.tx_bd_page_base_hi =
4692                                                 U64_HI(fp->tx_desc_mapping);
4693                 context->xstorm_st_context.tx_bd_page_base_lo =
4694                                                 U64_LO(fp->tx_desc_mapping);
4695                 context->xstorm_st_context.db_data_addr_hi =
4696                                                 U64_HI(fp->tx_prods_mapping);
4697                 context->xstorm_st_context.db_data_addr_lo =
4698                                                 U64_LO(fp->tx_prods_mapping);
4699                 context->xstorm_st_context.statistics_data = (fp->cl_id |
4700                                 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
4701                 context->cstorm_st_context.sb_index_number =
4702                                                 C_SB_ETH_TX_CQ_INDEX;
4703                 context->cstorm_st_context.status_block_id = sb_id;
4704
4705                 context->xstorm_ag_context.cdu_reserved =
4706                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4707                                                CDU_REGION_NUMBER_XCM_AG,
4708                                                ETH_CONNECTION_TYPE);
4709         }
4710 }
4711
4712 static void bnx2x_init_ind_table(struct bnx2x *bp)
4713 {
4714         int func = BP_FUNC(bp);
4715         int i;
4716
4717         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4718                 return;
4719
4720         DP(NETIF_MSG_IFUP,
4721            "Initializing indirection table  multi_mode %d\n", bp->multi_mode);
4722         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4723                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4724                         TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4725                         BP_CL_ID(bp) + (i % bp->num_rx_queues));
4726 }
4727
4728 static void bnx2x_set_client_config(struct bnx2x *bp)
4729 {
4730         struct tstorm_eth_client_config tstorm_client = {0};
4731         int port = BP_PORT(bp);
4732         int i;
4733
4734         tstorm_client.mtu = bp->dev->mtu;
4735         tstorm_client.config_flags =
4736                                 (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
4737                                  TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
4738 #ifdef BCM_VLAN
4739         if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
4740                 tstorm_client.config_flags |=
4741                                 TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
4742                 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4743         }
4744 #endif
4745
4746         if (bp->flags & TPA_ENABLE_FLAG) {
4747                 tstorm_client.max_sges_for_packet =
4748                         SGE_PAGE_ALIGN(tstorm_client.mtu) >> SGE_PAGE_SHIFT;
4749                 tstorm_client.max_sges_for_packet =
4750                         ((tstorm_client.max_sges_for_packet +
4751                           PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
4752                         PAGES_PER_SGE_SHIFT;
4753
4754                 tstorm_client.config_flags |=
4755                                 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
4756         }
4757
4758         for_each_queue(bp, i) {
4759                 tstorm_client.statistics_counter_id = bp->fp[i].cl_id;
4760
4761                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4762                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
4763                        ((u32 *)&tstorm_client)[0]);
4764                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4765                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
4766                        ((u32 *)&tstorm_client)[1]);
4767         }
4768
4769         DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
4770            ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
4771 }
4772
4773 static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4774 {
4775         struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4776         int mode = bp->rx_mode;
4777         int mask = (1 << BP_L_ID(bp));
4778         int func = BP_FUNC(bp);
4779         int i;
4780
4781         DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
4782
4783         switch (mode) {
4784         case BNX2X_RX_MODE_NONE: /* no Rx */
4785                 tstorm_mac_filter.ucast_drop_all = mask;
4786                 tstorm_mac_filter.mcast_drop_all = mask;
4787                 tstorm_mac_filter.bcast_drop_all = mask;
4788                 break;
4789         case BNX2X_RX_MODE_NORMAL:
4790                 tstorm_mac_filter.bcast_accept_all = mask;
4791                 break;
4792         case BNX2X_RX_MODE_ALLMULTI:
4793                 tstorm_mac_filter.mcast_accept_all = mask;
4794                 tstorm_mac_filter.bcast_accept_all = mask;
4795                 break;
4796         case BNX2X_RX_MODE_PROMISC:
4797                 tstorm_mac_filter.ucast_accept_all = mask;
4798                 tstorm_mac_filter.mcast_accept_all = mask;
4799                 tstorm_mac_filter.bcast_accept_all = mask;
4800                 break;
4801         default:
4802                 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4803                 break;
4804         }
4805
4806         for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4807                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4808                        TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
4809                        ((u32 *)&tstorm_mac_filter)[i]);
4810
4811 /*              DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4812                    ((u32 *)&tstorm_mac_filter)[i]); */
4813         }
4814
4815         if (mode != BNX2X_RX_MODE_NONE)
4816                 bnx2x_set_client_config(bp);
4817 }
4818
4819 static void bnx2x_init_internal_common(struct bnx2x *bp)
4820 {
4821         int i;
4822
4823         if (bp->flags & TPA_ENABLE_FLAG) {
4824                 struct tstorm_eth_tpa_exist tpa = {0};
4825
4826                 tpa.tpa_exist = 1;
4827
4828                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
4829                        ((u32 *)&tpa)[0]);
4830                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
4831                        ((u32 *)&tpa)[1]);
4832         }
4833
4834         /* Zero this manually as its initialization is
4835            currently missing in the initTool */
4836         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4837                 REG_WR(bp, BAR_USTRORM_INTMEM +
4838                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
4839 }
4840
4841 static void bnx2x_init_internal_port(struct bnx2x *bp)
4842 {
4843         int port = BP_PORT(bp);
4844
4845         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4846         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4847         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4848         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4849 }
4850
4851 static void bnx2x_init_internal_func(struct bnx2x *bp)
4852 {
4853         struct tstorm_eth_function_common_config tstorm_config = {0};
4854         struct stats_indication_flags stats_flags = {0};
4855         int port = BP_PORT(bp);
4856         int func = BP_FUNC(bp);
4857         int i, j;
4858         u32 offset;
4859         u16 max_agg_size;
4860
4861         if (is_multi(bp)) {
4862                 tstorm_config.config_flags = MULTI_FLAGS(bp);
4863                 tstorm_config.rss_result_mask = MULTI_MASK;
4864         }
4865         if (IS_E1HMF(bp))
4866                 tstorm_config.config_flags |=
4867                                 TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
4868
4869         tstorm_config.leading_client_id = BP_L_ID(bp);
4870
4871         REG_WR(bp, BAR_TSTRORM_INTMEM +
4872                TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4873                (*(u32 *)&tstorm_config));
4874
4875         bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4876         bnx2x_set_storm_rx_mode(bp);
4877
4878         for_each_queue(bp, i) {
4879                 u8 cl_id = bp->fp[i].cl_id;
4880
4881                 /* reset xstorm per client statistics */
4882                 offset = BAR_XSTRORM_INTMEM +
4883                          XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
4884                 for (j = 0;
4885                      j < sizeof(struct xstorm_per_client_stats) / 4; j++)
4886                         REG_WR(bp, offset + j*4, 0);
4887
4888                 /* reset tstorm per client statistics */
4889                 offset = BAR_TSTRORM_INTMEM +
4890                          TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
4891                 for (j = 0;
4892                      j < sizeof(struct tstorm_per_client_stats) / 4; j++)
4893                         REG_WR(bp, offset + j*4, 0);
4894
4895                 /* reset ustorm per client statistics */
4896                 offset = BAR_USTRORM_INTMEM +
4897                          USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
4898                 for (j = 0;
4899                      j < sizeof(struct ustorm_per_client_stats) / 4; j++)
4900                         REG_WR(bp, offset + j*4, 0);
4901         }
4902
4903         /* Init statistics related context */
4904         stats_flags.collect_eth = 1;
4905
4906         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4907                ((u32 *)&stats_flags)[0]);
4908         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4909                ((u32 *)&stats_flags)[1]);
4910
4911         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4912                ((u32 *)&stats_flags)[0]);
4913         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4914                ((u32 *)&stats_flags)[1]);
4915
4916         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
4917                ((u32 *)&stats_flags)[0]);
4918         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
4919                ((u32 *)&stats_flags)[1]);
4920
4921         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4922                ((u32 *)&stats_flags)[0]);
4923         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4924                ((u32 *)&stats_flags)[1]);
4925
4926         REG_WR(bp, BAR_XSTRORM_INTMEM +
4927                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4928                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4929         REG_WR(bp, BAR_XSTRORM_INTMEM +
4930                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4931                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4932
4933         REG_WR(bp, BAR_TSTRORM_INTMEM +
4934                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4935                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4936         REG_WR(bp, BAR_TSTRORM_INTMEM +
4937                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4938                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4939
4940         REG_WR(bp, BAR_USTRORM_INTMEM +
4941                USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4942                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4943         REG_WR(bp, BAR_USTRORM_INTMEM +
4944                USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4945                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4946
4947         if (CHIP_IS_E1H(bp)) {
4948                 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4949                         IS_E1HMF(bp));
4950                 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4951                         IS_E1HMF(bp));
4952                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4953                         IS_E1HMF(bp));
4954                 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4955                         IS_E1HMF(bp));
4956
4957                 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
4958                          bp->e1hov);
4959         }
4960
4961         /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
4962         max_agg_size =
4963                 min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) *
4964                           SGE_PAGE_SIZE * PAGES_PER_SGE),
4965                     (u32)0xffff);
4966         for_each_rx_queue(bp, i) {
4967                 struct bnx2x_fastpath *fp = &bp->fp[i];
4968
4969                 REG_WR(bp, BAR_USTRORM_INTMEM +
4970                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
4971                        U64_LO(fp->rx_comp_mapping));
4972                 REG_WR(bp, BAR_USTRORM_INTMEM +
4973                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4974                        U64_HI(fp->rx_comp_mapping));
4975
4976                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4977                          USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4978                          max_agg_size);
4979         }
4980 }
4981
4982 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4983 {
4984         switch (load_code) {
4985         case FW_MSG_CODE_DRV_LOAD_COMMON:
4986                 bnx2x_init_internal_common(bp);
4987                 /* no break */
4988
4989         case FW_MSG_CODE_DRV_LOAD_PORT:
4990                 bnx2x_init_internal_port(bp);
4991                 /* no break */
4992
4993         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4994                 bnx2x_init_internal_func(bp);
4995                 break;
4996
4997         default:
4998                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4999                 break;
5000         }
5001 }
5002
5003 static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5004 {
5005         int i;
5006
5007         for_each_queue(bp, i) {
5008                 struct bnx2x_fastpath *fp = &bp->fp[i];
5009
5010                 fp->bp = bp;
5011                 fp->state = BNX2X_FP_STATE_CLOSED;
5012                 fp->index = i;
5013                 fp->cl_id = BP_L_ID(bp) + i;
5014                 fp->sb_id = fp->cl_id;
5015                 DP(NETIF_MSG_IFUP,
5016                    "bnx2x_init_sb(%p,%p) index %d  cl_id %d  sb %d\n",
5017                    bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
5018                 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
5019                               FP_SB_ID(fp));
5020                 bnx2x_update_fpsb_idx(fp);
5021         }
5022
5023         bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
5024                           DEF_SB_ID);
5025         bnx2x_update_dsb_idx(bp);
5026         bnx2x_update_coalesce(bp);
5027         bnx2x_init_rx_rings(bp);
5028         bnx2x_init_tx_ring(bp);
5029         bnx2x_init_sp_ring(bp);
5030         bnx2x_init_context(bp);
5031         bnx2x_init_internal(bp, load_code);
5032         bnx2x_init_ind_table(bp);
5033         bnx2x_stats_init(bp);
5034
5035         /* At this point, we are ready for interrupts */
5036         atomic_set(&bp->intr_sem, 0);
5037
5038         /* flush all before enabling interrupts */
5039         mb();
5040         mmiowb();
5041
5042         bnx2x_int_enable(bp);
5043 }
5044
5045 /* end of nic init */
5046
5047 /*
5048  * gzip service functions
5049  */
5050
5051 static int bnx2x_gunzip_init(struct bnx2x *bp)
5052 {
5053         bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
5054                                               &bp->gunzip_mapping);
5055         if (bp->gunzip_buf  == NULL)
5056                 goto gunzip_nomem1;
5057
5058         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5059         if (bp->strm  == NULL)
5060                 goto gunzip_nomem2;
5061
5062         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
5063                                       GFP_KERNEL);
5064         if (bp->strm->workspace == NULL)
5065                 goto gunzip_nomem3;
5066
5067         return 0;
5068
5069 gunzip_nomem3:
5070         kfree(bp->strm);
5071         bp->strm = NULL;
5072
5073 gunzip_nomem2:
5074         pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
5075                             bp->gunzip_mapping);
5076         bp->gunzip_buf = NULL;
5077
5078 gunzip_nomem1:
5079         printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
5080                " un-compression\n", bp->dev->name);
5081         return -ENOMEM;
5082 }
5083
5084 static void bnx2x_gunzip_end(struct bnx2x *bp)
5085 {
5086         kfree(bp->strm->workspace);
5087
5088         kfree(bp->strm);
5089         bp->strm = NULL;
5090
5091         if (bp->gunzip_buf) {
5092                 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
5093                                     bp->gunzip_mapping);
5094                 bp->gunzip_buf = NULL;
5095         }
5096 }
5097
5098 static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
5099 {
5100         int n, rc;
5101
5102         /* check gzip header */
5103         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
5104                 return -EINVAL;
5105
5106         n = 10;
5107
5108 #define FNAME                           0x8
5109
5110         if (zbuf[3] & FNAME)
5111                 while ((zbuf[n++] != 0) && (n < len));
5112
5113         bp->strm->next_in = zbuf + n;
5114         bp->strm->avail_in = len - n;
5115         bp->strm->next_out = bp->gunzip_buf;
5116         bp->strm->avail_out = FW_BUF_SIZE;
5117
5118         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5119         if (rc != Z_OK)
5120                 return rc;
5121
5122         rc = zlib_inflate(bp->strm, Z_FINISH);
5123         if ((rc != Z_OK) && (rc != Z_STREAM_END))
5124                 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
5125                        bp->dev->name, bp->strm->msg);
5126
5127         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5128         if (bp->gunzip_outlen & 0x3)
5129                 printk(KERN_ERR PFX "%s: Firmware decompression error:"
5130                                     " gunzip_outlen (%d) not aligned\n",
5131                        bp->dev->name, bp->gunzip_outlen);
5132         bp->gunzip_outlen >>= 2;
5133
5134         zlib_inflateEnd(bp->strm);
5135
5136         if (rc == Z_STREAM_END)
5137                 return 0;
5138
5139         return rc;
5140 }
5141
5142 /* nic load/unload */
5143
5144 /*
5145  * General service functions
5146  */
5147
5148 /* send a NIG loopback debug packet */
5149 static void bnx2x_lb_pckt(struct bnx2x *bp)
5150 {
5151         u32 wb_write[3];
5152
5153         /* Ethernet source and destination addresses */
5154         wb_write[0] = 0x55555555;
5155         wb_write[1] = 0x55555555;
5156         wb_write[2] = 0x20;             /* SOP */
5157         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5158
5159         /* NON-IP protocol */
5160         wb_write[0] = 0x09000000;
5161         wb_write[1] = 0x55555555;
5162         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
5163         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5164 }
5165
5166 /* some of the internal memories
5167  * are not directly readable from the driver
5168  * to test them we send debug packets
5169  */
5170 static int bnx2x_int_mem_test(struct bnx2x *bp)
5171 {
5172         int factor;
5173         int count, i;
5174         u32 val = 0;
5175
5176         if (CHIP_REV_IS_FPGA(bp))
5177                 factor = 120;
5178         else if (CHIP_REV_IS_EMUL(bp))
5179                 factor = 200;
5180         else
5181                 factor = 1;
5182
5183         DP(NETIF_MSG_HW, "start part1\n");
5184
5185         /* Disable inputs of parser neighbor blocks */
5186         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5187         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5188         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5189         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5190
5191         /*  Write 0 to parser credits for CFC search request */
5192         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5193
5194         /* send Ethernet packet */
5195         bnx2x_lb_pckt(bp);
5196
5197         /* TODO do i reset NIG statistic? */
5198         /* Wait until NIG register shows 1 packet of size 0x10 */
5199         count = 1000 * factor;
5200         while (count) {
5201
5202                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5203                 val = *bnx2x_sp(bp, wb_data[0]);
5204                 if (val == 0x10)
5205                         break;
5206
5207                 msleep(10);
5208                 count--;
5209         }
5210         if (val != 0x10) {
5211                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5212                 return -1;
5213         }
5214
5215         /* Wait until PRS register shows 1 packet */
5216         count = 1000 * factor;
5217         while (count) {
5218                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5219                 if (val == 1)
5220                         break;
5221
5222                 msleep(10);
5223                 count--;
5224         }
5225         if (val != 0x1) {
5226                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5227                 return -2;
5228         }
5229
5230         /* Reset and init BRB, PRS */
5231         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5232         msleep(50);
5233         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5234         msleep(50);
5235         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5236         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5237
5238         DP(NETIF_MSG_HW, "part2\n");
5239
5240         /* Disable inputs of parser neighbor blocks */
5241         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5242         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5243         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5244         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5245
5246         /* Write 0 to parser credits for CFC search request */
5247         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5248
5249         /* send 10 Ethernet packets */
5250         for (i = 0; i < 10; i++)
5251                 bnx2x_lb_pckt(bp);
5252
5253         /* Wait until NIG register shows 10 + 1
5254            packets of size 11*0x10 = 0xb0 */
5255         count = 1000 * factor;
5256         while (count) {
5257
5258                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5259                 val = *bnx2x_sp(bp, wb_data[0]);
5260                 if (val == 0xb0)
5261                         break;
5262
5263                 msleep(10);
5264                 count--;
5265         }
5266         if (val != 0xb0) {
5267                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5268                 return -3;
5269         }
5270
5271         /* Wait until PRS register shows 2 packets */
5272         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5273         if (val != 2)
5274                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5275
5276         /* Write 1 to parser credits for CFC search request */
5277         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5278
5279         /* Wait until PRS register shows 3 packets */
5280         msleep(10 * factor);
5281         /* Wait until NIG register shows 1 packet of size 0x10 */
5282         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5283         if (val != 3)
5284                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5285
5286         /* clear NIG EOP FIFO */
5287         for (i = 0; i < 11; i++)
5288                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5289         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5290         if (val != 1) {
5291                 BNX2X_ERR("clear of NIG failed\n");
5292                 return -4;
5293         }
5294
5295         /* Reset and init BRB, PRS, NIG */
5296         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5297         msleep(50);
5298         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5299         msleep(50);
5300         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5301         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5302 #ifndef BCM_ISCSI
5303         /* set NIC mode */
5304         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5305 #endif
5306
5307         /* Enable inputs of parser neighbor blocks */
5308         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5309         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5310         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5311         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5312
5313         DP(NETIF_MSG_HW, "done\n");
5314
5315         return 0; /* OK */
5316 }
5317
5318 static void enable_blocks_attention(struct bnx2x *bp)
5319 {
5320         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5321         REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5322         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5323         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5324         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5325         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5326         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5327         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5328         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5329 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5330 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5331         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5332         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5333         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5334 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5335 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5336         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5337         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5338         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5339         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5340 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5341 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5342         if (CHIP_REV_IS_FPGA(bp))
5343                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5344         else
5345                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5346         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5347         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5348         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5349 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5350 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5351         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5352         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5353 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5354         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
5355 }
5356
5357
5358 static void bnx2x_reset_common(struct bnx2x *bp)
5359 {
5360         /* reset_common */
5361         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5362                0xd3ffff7f);
5363         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
5364 }
5365
5366 static int bnx2x_init_common(struct bnx2x *bp)
5367 {
5368         u32 val, i;
5369
5370         DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_FUNC(bp));
5371
5372         bnx2x_reset_common(bp);
5373         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5374         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5375
5376         bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
5377         if (CHIP_IS_E1H(bp))
5378                 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5379
5380         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5381         msleep(30);
5382         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5383
5384         bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
5385         if (CHIP_IS_E1(bp)) {
5386                 /* enable HW interrupt from PXP on USDM overflow
5387                    bit 16 on INT_MASK_0 */
5388                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5389         }
5390
5391         bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
5392         bnx2x_init_pxp(bp);
5393
5394 #ifdef __BIG_ENDIAN
5395         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5396         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5397         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5398         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5399         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5400         /* make sure this value is 0 */
5401         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5402
5403 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5404         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5405         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5406         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5407         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5408 #endif
5409
5410         REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5411 #ifdef BCM_ISCSI
5412         REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5413         REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5414         REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5415 #endif
5416
5417         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5418                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5419
5420         /* let the HW do it's magic ... */
5421         msleep(100);
5422         /* finish PXP init */
5423         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5424         if (val != 1) {
5425                 BNX2X_ERR("PXP2 CFG failed\n");
5426                 return -EBUSY;
5427         }
5428         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5429         if (val != 1) {
5430                 BNX2X_ERR("PXP2 RD_INIT failed\n");
5431                 return -EBUSY;
5432         }
5433
5434         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5435         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5436
5437         bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
5438
5439         /* clean the DMAE memory */
5440         bp->dmae_ready = 1;
5441         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5442
5443         bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
5444         bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
5445         bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
5446         bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
5447
5448         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5449         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5450         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5451         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5452
5453         bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5454         /* soft reset pulse */
5455         REG_WR(bp, QM_REG_SOFT_RESET, 1);
5456         REG_WR(bp, QM_REG_SOFT_RESET, 0);
5457
5458 #ifdef BCM_ISCSI
5459         bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
5460 #endif
5461
5462         bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
5463         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
5464         if (!CHIP_REV_IS_SLOW(bp)) {
5465                 /* enable hw interrupt from doorbell Q */
5466                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5467         }
5468
5469         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5470         if (CHIP_REV_IS_SLOW(bp)) {
5471                 /* fix for emulation and FPGA for no pause */
5472                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
5473                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
5474                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
5475                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
5476         }
5477
5478         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5479         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5480         /* set NIC mode */
5481         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5482         if (CHIP_IS_E1H(bp))
5483                 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5484
5485         bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
5486         bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
5487         bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5488         bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5489
5490         if (CHIP_IS_E1H(bp)) {
5491                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5492                                 STORM_INTMEM_SIZE_E1H/2);
5493                 bnx2x_init_fill(bp,
5494                                 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5495                                 0, STORM_INTMEM_SIZE_E1H/2);
5496                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5497                                 STORM_INTMEM_SIZE_E1H/2);
5498                 bnx2x_init_fill(bp,
5499                                 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5500                                 0, STORM_INTMEM_SIZE_E1H/2);
5501                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5502                                 STORM_INTMEM_SIZE_E1H/2);
5503                 bnx2x_init_fill(bp,
5504                                 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5505                                 0, STORM_INTMEM_SIZE_E1H/2);
5506                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5507                                 STORM_INTMEM_SIZE_E1H/2);
5508                 bnx2x_init_fill(bp,
5509                                 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5510                                 0, STORM_INTMEM_SIZE_E1H/2);
5511         } else { /* E1 */
5512                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5513                                 STORM_INTMEM_SIZE_E1);
5514                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5515                                 STORM_INTMEM_SIZE_E1);
5516                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5517                                 STORM_INTMEM_SIZE_E1);
5518                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5519                                 STORM_INTMEM_SIZE_E1);
5520         }
5521
5522         bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5523         bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
5524         bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
5525         bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
5526
5527         /* sync semi rtc */
5528         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5529                0x80000000);
5530         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5531                0x80000000);
5532
5533         bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
5534         bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
5535         bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
5536
5537         REG_WR(bp, SRC_REG_SOFT_RST, 1);
5538         for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5539                 REG_WR(bp, i, 0xc0cac01a);
5540                 /* TODO: replace with something meaningful */
5541         }
5542         bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
5543         REG_WR(bp, SRC_REG_SOFT_RST, 0);
5544
5545         if (sizeof(union cdu_context) != 1024)
5546                 /* we currently assume that a context is 1024 bytes */
5547                 printk(KERN_ALERT PFX "please adjust the size of"
5548                        " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5549
5550         bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
5551         val = (4 << 24) + (0 << 12) + 1024;
5552         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5553         if (CHIP_IS_E1(bp)) {
5554                 /* !!! fix pxp client crdit until excel update */
5555                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5556                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
5557         }
5558
5559         bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
5560         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5561         /* enable context validation interrupt from CFC */
5562         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5563
5564         /* set the thresholds to prevent CFC/CDU race */
5565         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5566
5567         bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
5568         bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
5569
5570         /* PXPCS COMMON comes here */
5571         /* Reset PCIE errors for debug */
5572         REG_WR(bp, 0x2814, 0xffffffff);
5573         REG_WR(bp, 0x3820, 0xffffffff);
5574
5575         /* EMAC0 COMMON comes here */
5576         /* EMAC1 COMMON comes here */
5577         /* DBU COMMON comes here */
5578         /* DBG COMMON comes here */
5579
5580         bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
5581         if (CHIP_IS_E1H(bp)) {
5582                 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
5583                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
5584         }
5585
5586         if (CHIP_REV_IS_SLOW(bp))
5587                 msleep(200);
5588
5589         /* finish CFC init */
5590         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5591         if (val != 1) {
5592                 BNX2X_ERR("CFC LL_INIT failed\n");
5593                 return -EBUSY;
5594         }
5595         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5596         if (val != 1) {
5597                 BNX2X_ERR("CFC AC_INIT failed\n");
5598                 return -EBUSY;
5599         }
5600         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5601         if (val != 1) {
5602                 BNX2X_ERR("CFC CAM_INIT failed\n");
5603                 return -EBUSY;
5604         }
5605         REG_WR(bp, CFC_REG_DEBUG0, 0);
5606
5607         /* read NIG statistic
5608            to see if this is our first up since powerup */
5609         bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5610         val = *bnx2x_sp(bp, wb_data[0]);
5611
5612         /* do internal memory self test */
5613         if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
5614                 BNX2X_ERR("internal mem self test failed\n");
5615                 return -EBUSY;
5616         }
5617
5618         switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5619         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
5620         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5621                 /* Fan failure is indicated by SPIO 5 */
5622                 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5623                                MISC_REGISTERS_SPIO_INPUT_HI_Z);
5624
5625                 /* set to active low mode */
5626                 val = REG_RD(bp, MISC_REG_SPIO_INT);
5627                 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5628                                         MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5629                 REG_WR(bp, MISC_REG_SPIO_INT, val);
5630
5631                 /* enable interrupt to signal the IGU */
5632                 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5633                 val |= (1 << MISC_REGISTERS_SPIO_5);
5634                 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5635                 break;
5636
5637         default:
5638                 break;
5639         }
5640
5641         /* clear PXP2 attentions */
5642         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5643
5644         enable_blocks_attention(bp);
5645
5646         if (!BP_NOMCP(bp)) {
5647                 bnx2x_acquire_phy_lock(bp);
5648                 bnx2x_common_init_phy(bp, bp->common.shmem_base);
5649                 bnx2x_release_phy_lock(bp);
5650         } else
5651                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5652
5653         return 0;
5654 }
5655
5656 static int bnx2x_init_port(struct bnx2x *bp)
5657 {
5658         int port = BP_PORT(bp);
5659         u32 val;
5660
5661         DP(BNX2X_MSG_MCP, "starting port init  port %x\n", port);
5662
5663         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5664
5665         /* Port PXP comes here */
5666         /* Port PXP2 comes here */
5667 #ifdef BCM_ISCSI
5668         /* Port0  1
5669          * Port1  385 */
5670         i++;
5671         wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5672         wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5673         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5674         REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5675
5676         /* Port0  2
5677          * Port1  386 */
5678         i++;
5679         wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5680         wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5681         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5682         REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5683
5684         /* Port0  3
5685          * Port1  387 */
5686         i++;
5687         wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5688         wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5689         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5690         REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5691 #endif
5692         /* Port CMs come here */
5693         bnx2x_init_block(bp, (port ? XCM_PORT1_START : XCM_PORT0_START),
5694                              (port ? XCM_PORT1_END : XCM_PORT0_END));
5695
5696         /* Port QM comes here */
5697 #ifdef BCM_ISCSI
5698         REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5699         REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5700
5701         bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
5702                              func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
5703 #endif
5704         /* Port DQ comes here */
5705         /* Port BRB1 comes here */
5706         /* Port PRS comes here */
5707         /* Port TSDM comes here */
5708         /* Port CSDM comes here */
5709         /* Port USDM comes here */
5710         /* Port XSDM comes here */
5711         bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
5712                              port ? TSEM_PORT1_END : TSEM_PORT0_END);
5713         bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
5714                              port ? USEM_PORT1_END : USEM_PORT0_END);
5715         bnx2x_init_block(bp, port ? CSEM_PORT1_START : CSEM_PORT0_START,
5716                              port ? CSEM_PORT1_END : CSEM_PORT0_END);
5717         bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
5718                              port ? XSEM_PORT1_END : XSEM_PORT0_END);
5719         /* Port UPB comes here */
5720         /* Port XPB comes here */
5721
5722         bnx2x_init_block(bp, port ? PBF_PORT1_START : PBF_PORT0_START,
5723                              port ? PBF_PORT1_END : PBF_PORT0_END);
5724
5725         /* configure PBF to work without PAUSE mtu 9000 */
5726         REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5727
5728         /* update threshold */
5729         REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5730         /* update init credit */
5731         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5732
5733         /* probe changes */
5734         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5735         msleep(5);
5736         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5737
5738