966b4a2de9622a8f10a6d0c2db442b430d8ce303
[linux-2.6.git] / drivers / net / bnx2x_hsi.h
1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2008 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9
10
11 #define PORT_0                          0
12 #define PORT_1                          1
13 #define PORT_MAX                        2
14
15 /****************************************************************************
16  * Shared HW configuration                                                  *
17  ****************************************************************************/
18 struct shared_hw_cfg {                                   /* NVRAM Offset */
19         /* Up to 16 bytes of NULL-terminated string */
20         u8  part_num[16];                                       /* 0x104 */
21
22         u32 config;                                             /* 0x114 */
23 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
24 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT            0
25 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V             0x00000000
26 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V             0x00000001
27 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
28
29 #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
30
31 #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
32
33 #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
34 #define SHARED_HW_CFG_MFW_SELECT_SHIFT              8
35         /* Whatever MFW found in NVM
36            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT            0x00000000
38 #define SHARED_HW_CFG_MFW_SELECT_NC_SI              0x00000100
39 #define SHARED_HW_CFG_MFW_SELECT_UMP                0x00000200
40 #define SHARED_HW_CFG_MFW_SELECT_IPMI               0x00000300
41         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
44         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
47         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
50
51 #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
52 #define SHARED_HW_CFG_LED_MODE_SHIFT                16
53 #define SHARED_HW_CFG_LED_MAC1                      0x00000000
54 #define SHARED_HW_CFG_LED_PHY1                      0x00010000
55 #define SHARED_HW_CFG_LED_PHY2                      0x00020000
56 #define SHARED_HW_CFG_LED_PHY3                      0x00030000
57 #define SHARED_HW_CFG_LED_MAC2                      0x00040000
58 #define SHARED_HW_CFG_LED_PHY4                      0x00050000
59 #define SHARED_HW_CFG_LED_PHY5                      0x00060000
60 #define SHARED_HW_CFG_LED_PHY6                      0x00070000
61 #define SHARED_HW_CFG_LED_MAC3                      0x00080000
62 #define SHARED_HW_CFG_LED_PHY7                      0x00090000
63 #define SHARED_HW_CFG_LED_PHY9                      0x000a0000
64 #define SHARED_HW_CFG_LED_PHY11                     0x000b0000
65 #define SHARED_HW_CFG_LED_MAC4                      0x000c0000
66 #define SHARED_HW_CFG_LED_PHY8                      0x000d0000
67
68 #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
69 #define SHARED_HW_CFG_AN_ENABLE_SHIFT               24
70 #define SHARED_HW_CFG_AN_ENABLE_CL37                0x01000000
71 #define SHARED_HW_CFG_AN_ENABLE_CL73                0x02000000
72 #define SHARED_HW_CFG_AN_ENABLE_BAM                 0x04000000
73 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
74 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY          0x20000000
76
77         u32 config2;                                            /* 0x118 */
78         /* one time auto detect grace period (in sec) */
79 #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
80 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT            0
81
82 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
83
84         /* The default value for the core clock is 250MHz and it is
85            achieved by setting the clock change to 4 */
86 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
87 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT            9
88
89 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ           0x00000000
90 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ           0x00001000
91
92 #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
93
94         u32 power_dissipated;                                   /* 0x11c */
95 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
96 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT           24
97
98 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
99 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT        16
100 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE      0x00000000
101 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT         0x00010000
102 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT        0x00020000
103 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT       0x00030000
104
105         u32 ump_nc_si_config;                                   /* 0x120 */
106 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
107 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT      0
108 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC        0x00000000
109 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY        0x00000001
110 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII        0x00000000
111 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII       0x00000002
112
113 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
114 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT      8
115
116 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
117 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
118 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
119 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
120
121         u32 board;                                              /* 0x124 */
122 #define SHARED_HW_CFG_BOARD_REV_MASK                0x00FF0000
123 #define SHARED_HW_CFG_BOARD_REV_SHIFT               16
124
125 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0F000000
126 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT         24
127
128 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xF0000000
129 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT         28
130
131         u32 reserved;                                           /* 0x128 */
132
133 };
134
135
136 /****************************************************************************
137  * Port HW configuration                                                    *
138  ****************************************************************************/
139 struct port_hw_cfg {                        /* port 0: 0x12c  port 1: 0x2bc */
140
141         u32 pci_id;
142 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
143 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
144
145         u32 pci_sub_id;
146 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
147 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
148
149         u32 power_dissipated;
150 #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
151 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT              24
152 #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
153 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT              16
154 #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
155 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT              8
156 #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
157 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT              0
158
159         u32 power_consumed;
160 #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
161 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT             24
162 #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
163 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT             16
164 #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
165 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT             8
166 #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
167 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT             0
168
169         u32 mac_upper;
170 #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
171 #define PORT_HW_CFG_UPPERMAC_SHIFT                  0
172         u32 mac_lower;
173
174         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
175         u32 iscsi_mac_lower;
176
177         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
178         u32 rdma_mac_lower;
179
180         u32 serdes_config;
181 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK           0x0000FFFF
182 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT          0
183
184 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK              0xFFFF0000
185 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT             16
186
187
188         u32 Reserved0[16];                                  /* 0x158 */
189
190         /*  for external PHY, or forced mode or during AN */
191         u16 xgxs_config_rx[4];                              /* 0x198 */
192
193         u16 xgxs_config_tx[4];                              /* 0x1A0 */
194
195         u32 Reserved1[64];                                  /* 0x1A8 */
196
197         u32 lane_config;
198 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
199 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT             0
200 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
201 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT          0
202 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
203 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT          8
204 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
205 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT      14
206         /* AN and forced */
207 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123          0x00001b1b
208         /* forced only */
209 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210          0x00001be4
210         /* forced only */
211 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120          0x0000d8d8
212         /* forced only */
213 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210          0x0000e4e4
214
215         u32 external_phy_config;
216 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
217 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT       24
218 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT      0x00000000
219 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
220 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
221
222 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
223 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT       16
224
225 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
226 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT         8
227 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT        0x00000000
228 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071       0x00000100
229 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072       0x00000200
230 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073       0x00000300
231 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705       0x00000400
232 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706       0x00000500
233 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726       0x00000600
234 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481       0x00000700
235 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101       0x00000800
236 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE       0x0000fd00
237 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN      0x0000ff00
238
239 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
240 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT         0
241
242         u32 speed_capability_mask;
243 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
244 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT       16
245 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
246 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
247 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
248 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
249 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G          0x00100000
250 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G        0x00200000
251 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G         0x00400000
252 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G         0x00800000
253 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G       0x01000000
254 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G         0x02000000
255 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G         0x04000000
256 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G         0x08000000
257 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
258
259 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
260 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT       0
261 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
262 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
263 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
264 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
265 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G          0x00000010
266 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G        0x00000020
267 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G         0x00000040
268 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G         0x00000080
269 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G       0x00000100
270 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G         0x00000200
271 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G         0x00000400
272 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G         0x00000800
273 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
274
275         u32 reserved[2];
276
277 };
278
279
280 /****************************************************************************
281  * Shared Feature configuration                                             *
282  ****************************************************************************/
283 struct shared_feat_cfg {                                 /* NVRAM Offset */
284
285         u32 config;                                             /* 0x450 */
286 #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
287
288         /*  Use the values from options 47 and 48 instead of the HW default
289           values */
290 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED     0x00000000
291 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED      0x00000002
292
293 #define SHARED_FEATURE_MF_MODE_DISABLED             0x00000100
294
295 };
296
297
298 /****************************************************************************
299  * Port Feature configuration                                               *
300  ****************************************************************************/
301 struct port_feat_cfg {                      /* port 0: 0x454  port 1: 0x4c8 */
302
303         u32 config;
304 #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
305 #define PORT_FEATURE_BAR1_SIZE_SHIFT                0
306 #define PORT_FEATURE_BAR1_SIZE_DISABLED             0x00000000
307 #define PORT_FEATURE_BAR1_SIZE_64K                  0x00000001
308 #define PORT_FEATURE_BAR1_SIZE_128K                 0x00000002
309 #define PORT_FEATURE_BAR1_SIZE_256K                 0x00000003
310 #define PORT_FEATURE_BAR1_SIZE_512K                 0x00000004
311 #define PORT_FEATURE_BAR1_SIZE_1M                   0x00000005
312 #define PORT_FEATURE_BAR1_SIZE_2M                   0x00000006
313 #define PORT_FEATURE_BAR1_SIZE_4M                   0x00000007
314 #define PORT_FEATURE_BAR1_SIZE_8M                   0x00000008
315 #define PORT_FEATURE_BAR1_SIZE_16M                  0x00000009
316 #define PORT_FEATURE_BAR1_SIZE_32M                  0x0000000a
317 #define PORT_FEATURE_BAR1_SIZE_64M                  0x0000000b
318 #define PORT_FEATURE_BAR1_SIZE_128M                 0x0000000c
319 #define PORT_FEATURE_BAR1_SIZE_256M                 0x0000000d
320 #define PORT_FEATURE_BAR1_SIZE_512M                 0x0000000e
321 #define PORT_FEATURE_BAR1_SIZE_1G                   0x0000000f
322 #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
323 #define PORT_FEATURE_BAR2_SIZE_SHIFT                4
324 #define PORT_FEATURE_BAR2_SIZE_DISABLED             0x00000000
325 #define PORT_FEATURE_BAR2_SIZE_64K                  0x00000010
326 #define PORT_FEATURE_BAR2_SIZE_128K                 0x00000020
327 #define PORT_FEATURE_BAR2_SIZE_256K                 0x00000030
328 #define PORT_FEATURE_BAR2_SIZE_512K                 0x00000040
329 #define PORT_FEATURE_BAR2_SIZE_1M                   0x00000050
330 #define PORT_FEATURE_BAR2_SIZE_2M                   0x00000060
331 #define PORT_FEATURE_BAR2_SIZE_4M                   0x00000070
332 #define PORT_FEATURE_BAR2_SIZE_8M                   0x00000080
333 #define PORT_FEATURE_BAR2_SIZE_16M                  0x00000090
334 #define PORT_FEATURE_BAR2_SIZE_32M                  0x000000a0
335 #define PORT_FEATURE_BAR2_SIZE_64M                  0x000000b0
336 #define PORT_FEATURE_BAR2_SIZE_128M                 0x000000c0
337 #define PORT_FEATURE_BAR2_SIZE_256M                 0x000000d0
338 #define PORT_FEATURE_BAR2_SIZE_512M                 0x000000e0
339 #define PORT_FEATURE_BAR2_SIZE_1G                   0x000000f0
340 #define PORT_FEATURE_EN_SIZE_MASK                   0x07000000
341 #define PORT_FEATURE_EN_SIZE_SHIFT                  24
342 #define PORT_FEATURE_WOL_ENABLED                    0x01000000
343 #define PORT_FEATURE_MBA_ENABLED                    0x02000000
344 #define PORT_FEATURE_MFW_ENABLED                    0x04000000
345
346         /*  Check the optic vendor via i2c before allowing it to be used by
347           SW */
348 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLED               0x00000000
349 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED                0x08000000
350
351         u32 wol_config;
352         /* Default is used when driver sets to "auto" mode */
353 #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
354 #define PORT_FEATURE_WOL_DEFAULT_SHIFT              0
355 #define PORT_FEATURE_WOL_DEFAULT_DISABLE            0x00000000
356 #define PORT_FEATURE_WOL_DEFAULT_MAGIC              0x00000001
357 #define PORT_FEATURE_WOL_DEFAULT_ACPI               0x00000002
358 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
359 #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
360 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
361 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
362
363         u32 mba_config;
364 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000003
365 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT      0
366 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0x00000000
367 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        0x00000001
368 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      0x00000002
369 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
370 #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
371 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
372 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
373 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S              0x00000000
374 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B              0x00000800
375 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
376 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT         12
377 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0x00000000
378 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K            0x00001000
379 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K            0x00002000
380 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K            0x00003000
381 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K           0x00004000
382 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K           0x00005000
383 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K           0x00006000
384 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K          0x00007000
385 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K          0x00008000
386 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K          0x00009000
387 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M            0x0000a000
388 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M            0x0000b000
389 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M            0x0000c000
390 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M            0x0000d000
391 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M           0x0000e000
392 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M           0x0000f000
393 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
394 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT          20
395 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
396 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT       24
397 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0x00000000
398 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x01000000
399 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x02000000
400 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x03000000
401 #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
402 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT           26
403 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO            0x00000000
404 #define PORT_FEATURE_MBA_LINK_SPEED_10HD            0x04000000
405 #define PORT_FEATURE_MBA_LINK_SPEED_10FD            0x08000000
406 #define PORT_FEATURE_MBA_LINK_SPEED_100HD           0x0c000000
407 #define PORT_FEATURE_MBA_LINK_SPEED_100FD           0x10000000
408 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS           0x14000000
409 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS         0x18000000
410 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4      0x1c000000
411 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4      0x20000000
412 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR       0x24000000
413 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS          0x28000000
414 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS        0x2c000000
415 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS          0x30000000
416 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS          0x34000000
417 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS          0x38000000
418
419         u32 bmc_config;
420 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT      0x00000000
421 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN           0x00000001
422
423         u32 mba_vlan_cfg;
424 #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
425 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT             0
426 #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
427
428         u32 resource_cfg;
429 #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
430 #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
431 #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
432 #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
433 #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
434
435         u32 smbus_config;
436         /* Obsolete */
437 #define PORT_FEATURE_SMBUS_EN                       0x00000001
438 #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
439 #define PORT_FEATURE_SMBUS_ADDR_SHIFT               1
440
441         u32 reserved1;
442
443         u32 link_config;    /* Used as HW defaults for the driver */
444 #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
445 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT         24
446         /* (forced) low speed switch (< 10G) */
447 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH           0x00000000
448         /* (forced) high speed switch (>= 10G) */
449 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH          0x01000000
450 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT         0x02000000
451 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
452
453 #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
454 #define PORT_FEATURE_LINK_SPEED_SHIFT               16
455 #define PORT_FEATURE_LINK_SPEED_AUTO                0x00000000
456 #define PORT_FEATURE_LINK_SPEED_10M_FULL            0x00010000
457 #define PORT_FEATURE_LINK_SPEED_10M_HALF            0x00020000
458 #define PORT_FEATURE_LINK_SPEED_100M_HALF           0x00030000
459 #define PORT_FEATURE_LINK_SPEED_100M_FULL           0x00040000
460 #define PORT_FEATURE_LINK_SPEED_1G                  0x00050000
461 #define PORT_FEATURE_LINK_SPEED_2_5G                0x00060000
462 #define PORT_FEATURE_LINK_SPEED_10G_CX4             0x00070000
463 #define PORT_FEATURE_LINK_SPEED_10G_KX4             0x00080000
464 #define PORT_FEATURE_LINK_SPEED_10G_KR              0x00090000
465 #define PORT_FEATURE_LINK_SPEED_12G                 0x000a0000
466 #define PORT_FEATURE_LINK_SPEED_12_5G               0x000b0000
467 #define PORT_FEATURE_LINK_SPEED_13G                 0x000c0000
468 #define PORT_FEATURE_LINK_SPEED_15G                 0x000d0000
469 #define PORT_FEATURE_LINK_SPEED_16G                 0x000e0000
470
471 #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
472 #define PORT_FEATURE_FLOW_CONTROL_SHIFT             8
473 #define PORT_FEATURE_FLOW_CONTROL_AUTO              0x00000000
474 #define PORT_FEATURE_FLOW_CONTROL_TX                0x00000100
475 #define PORT_FEATURE_FLOW_CONTROL_RX                0x00000200
476 #define PORT_FEATURE_FLOW_CONTROL_BOTH              0x00000300
477 #define PORT_FEATURE_FLOW_CONTROL_NONE              0x00000400
478
479         /* The default for MCP link configuration,
480            uses the same defines as link_config */
481         u32 mfw_wol_link_cfg;
482
483         u32 reserved[19];
484
485 };
486
487
488 /****************************************************************************
489  * Device Information                                                       *
490  ****************************************************************************/
491 struct shm_dev_info {                                               /* size */
492
493         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
494
495         struct shared_hw_cfg     shared_hw_config;                    /* 40 */
496
497         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
498
499         struct shared_feat_cfg   shared_feature_config;                /* 4 */
500
501         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
502
503 };
504
505
506 #define FUNC_0                          0
507 #define FUNC_1                          1
508 #define FUNC_2                          2
509 #define FUNC_3                          3
510 #define FUNC_4                          4
511 #define FUNC_5                          5
512 #define FUNC_6                          6
513 #define FUNC_7                          7
514 #define E1_FUNC_MAX                     2
515 #define E1H_FUNC_MAX                    8
516
517 #define VN_0                            0
518 #define VN_1                            1
519 #define VN_2                            2
520 #define VN_3                            3
521 #define E1VN_MAX                        1
522 #define E1HVN_MAX                       4
523
524
525 /* This value (in milliseconds) determines the frequency of the driver
526  * issuing the PULSE message code.  The firmware monitors this periodic
527  * pulse to determine when to switch to an OS-absent mode. */
528 #define DRV_PULSE_PERIOD_MS             250
529
530 /* This value (in milliseconds) determines how long the driver should
531  * wait for an acknowledgement from the firmware before timing out.  Once
532  * the firmware has timed out, the driver will assume there is no firmware
533  * running and there won't be any firmware-driver synchronization during a
534  * driver reset. */
535 #define FW_ACK_TIME_OUT_MS              5000
536
537 #define FW_ACK_POLL_TIME_MS             1
538
539 #define FW_ACK_NUM_OF_POLL      (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
540
541 /* LED Blink rate that will achieve ~15.9Hz */
542 #define LED_BLINK_RATE_VAL              480
543
544 /****************************************************************************
545  * Driver <-> FW Mailbox                                                    *
546  ****************************************************************************/
547 struct drv_port_mb {
548
549         u32 link_status;
550         /* Driver should update this field on any link change event */
551
552 #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
553 #define LINK_STATUS_LINK_UP                             0x00000001
554 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
555 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
556 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
557 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
558 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
559 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
560 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
561 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
562 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
563 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
564 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
565 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
566 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
567 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
568 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
569 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD             (11<<1)
570 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD             (11<<1)
571 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD           (12<<1)
572 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD           (12<<1)
573 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD             (13<<1)
574 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD             (13<<1)
575 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD             (14<<1)
576 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD             (14<<1)
577 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD             (15<<1)
578 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD             (15<<1)
579
580 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
581 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
582
583 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
584 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
585 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
586
587 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
588 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
589 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
590 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
591 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
592 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
593 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
594
595 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
596 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
597
598 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
599 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
600
601 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
602 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
603 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
604 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
605 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
606
607 #define LINK_STATUS_SERDES_LINK                         0x00100000
608
609 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
610 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
611 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
612 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE         0x01000000
613 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE       0x02000000
614 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE         0x04000000
615 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE         0x08000000
616 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE         0x10000000
617
618         u32 port_stx;
619
620         u32 stat_nig_timer;
621
622         /* MCP firmware does not use this field */
623         u32 ext_phy_fw_version;
624
625 };
626
627
628 struct drv_func_mb {
629
630         u32 drv_mb_header;
631 #define DRV_MSG_CODE_MASK                               0xffff0000
632 #define DRV_MSG_CODE_LOAD_REQ                           0x10000000
633 #define DRV_MSG_CODE_LOAD_DONE                          0x11000000
634 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN                  0x20000000
635 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS                 0x20010000
636 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP                 0x20020000
637 #define DRV_MSG_CODE_UNLOAD_DONE                        0x21000000
638 #define DRV_MSG_CODE_DIAG_ENTER_REQ                     0x50000000
639 #define DRV_MSG_CODE_DIAG_EXIT_REQ                      0x60000000
640 #define DRV_MSG_CODE_VALIDATE_KEY                       0x70000000
641 #define DRV_MSG_CODE_GET_CURR_KEY                       0x80000000
642 #define DRV_MSG_CODE_GET_UPGRADE_KEY                    0x81000000
643 #define DRV_MSG_CODE_GET_MANUF_KEY                      0x82000000
644 #define DRV_MSG_CODE_LOAD_L2B_PRAM                      0x90000000
645
646 #define BIOS_MSG_CODE_LIC_CHALLENGE                     0xff010000
647 #define BIOS_MSG_CODE_LIC_RESPONSE                      0xff020000
648 #define BIOS_MSG_CODE_VIRT_MAC_PRIM                     0xff030000
649 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI                    0xff040000
650
651 #define DRV_MSG_SEQ_NUMBER_MASK                         0x0000ffff
652
653         u32 drv_mb_param;
654
655         u32 fw_mb_header;
656 #define FW_MSG_CODE_MASK                                0xffff0000
657 #define FW_MSG_CODE_DRV_LOAD_COMMON                     0x10100000
658 #define FW_MSG_CODE_DRV_LOAD_PORT                       0x10110000
659 #define FW_MSG_CODE_DRV_LOAD_FUNCTION                   0x10120000
660 #define FW_MSG_CODE_DRV_LOAD_REFUSED                    0x10200000
661 #define FW_MSG_CODE_DRV_LOAD_DONE                       0x11100000
662 #define FW_MSG_CODE_DRV_UNLOAD_COMMON                   0x20100000
663 #define FW_MSG_CODE_DRV_UNLOAD_PORT                     0x20110000
664 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION                 0x20120000
665 #define FW_MSG_CODE_DRV_UNLOAD_DONE                     0x21100000
666 #define FW_MSG_CODE_DIAG_ENTER_DONE                     0x50100000
667 #define FW_MSG_CODE_DIAG_REFUSE                         0x50200000
668 #define FW_MSG_CODE_DIAG_EXIT_DONE                      0x60100000
669 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS                0x70100000
670 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE                0x70200000
671 #define FW_MSG_CODE_GET_KEY_DONE                        0x80100000
672 #define FW_MSG_CODE_NO_KEY                              0x80f00000
673 #define FW_MSG_CODE_LIC_INFO_NOT_READY                  0x80f80000
674 #define FW_MSG_CODE_L2B_PRAM_LOADED                     0x90100000
675 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE             0x90210000
676 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE             0x90220000
677 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE             0x90230000
678 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE             0x90240000
679
680 #define FW_MSG_CODE_LIC_CHALLENGE                       0xff010000
681 #define FW_MSG_CODE_LIC_RESPONSE                        0xff020000
682 #define FW_MSG_CODE_VIRT_MAC_PRIM                       0xff030000
683 #define FW_MSG_CODE_VIRT_MAC_ISCSI                      0xff040000
684
685 #define FW_MSG_SEQ_NUMBER_MASK                          0x0000ffff
686
687         u32 fw_mb_param;
688
689         u32 drv_pulse_mb;
690 #define DRV_PULSE_SEQ_MASK                              0x00007fff
691 #define DRV_PULSE_SYSTEM_TIME_MASK                      0xffff0000
692         /* The system time is in the format of
693          * (year-2001)*12*32 + month*32 + day. */
694 #define DRV_PULSE_ALWAYS_ALIVE                          0x00008000
695         /* Indicate to the firmware not to go into the
696          * OS-absent when it is not getting driver pulse.
697          * This is used for debugging as well for PXE(MBA). */
698
699         u32 mcp_pulse_mb;
700 #define MCP_PULSE_SEQ_MASK                              0x00007fff
701 #define MCP_PULSE_ALWAYS_ALIVE                          0x00008000
702         /* Indicates to the driver not to assert due to lack
703          * of MCP response */
704 #define MCP_EVENT_MASK                                  0xffff0000
705 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ                0x00010000
706
707         u32 iscsi_boot_signature;
708         u32 iscsi_boot_block_offset;
709
710         u32 drv_status;
711 #define DRV_STATUS_PMF                                  0x00000001
712
713         u32 virt_mac_upper;
714 #define VIRT_MAC_SIGN_MASK                              0xffff0000
715 #define VIRT_MAC_SIGNATURE                              0x564d0000
716         u32 virt_mac_lower;
717
718 };
719
720
721 /****************************************************************************
722  * Management firmware state                                                *
723  ****************************************************************************/
724 /* Allocate 440 bytes for management firmware */
725 #define MGMTFW_STATE_WORD_SIZE                              110
726
727 struct mgmtfw_state {
728         u32 opaque[MGMTFW_STATE_WORD_SIZE];
729 };
730
731
732 /****************************************************************************
733  * Multi-Function configuration                                             *
734  ****************************************************************************/
735 struct shared_mf_cfg {
736
737         u32 clp_mb;
738 #define SHARED_MF_CLP_SET_DEFAULT                   0x00000000
739         /* set by CLP */
740 #define SHARED_MF_CLP_EXIT                          0x00000001
741         /* set by MCP */
742 #define SHARED_MF_CLP_EXIT_DONE                     0x00010000
743
744 };
745
746 struct port_mf_cfg {
747
748         u32 dynamic_cfg;        /* device control channel */
749 #define PORT_MF_CFG_OUTER_VLAN_TAG_MASK             0x0000ffff
750 #define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT            0
751 #define PORT_MF_CFG_DYNAMIC_CFG_ENABLED             0x00010000
752 #define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT             0x00000000
753
754         u32 reserved[3];
755
756 };
757
758 struct func_mf_cfg {
759
760         u32 config;
761         /* E/R/I/D */
762         /* function 0 of each port cannot be hidden */
763 #define FUNC_MF_CFG_FUNC_HIDE                       0x00000001
764
765 #define FUNC_MF_CFG_PROTOCOL_MASK                   0x00000007
766 #define FUNC_MF_CFG_PROTOCOL_ETHERNET               0x00000002
767 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA     0x00000004
768 #define FUNC_MF_CFG_PROTOCOL_ISCSI                  0x00000006
769 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
770         FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
771
772 #define FUNC_MF_CFG_FUNC_DISABLED                   0x00000008
773
774         /* PRI */
775         /* 0 - low priority, 3 - high priority */
776 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK          0x00000300
777 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT         8
778 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT       0x00000000
779
780         /* MINBW, MAXBW */
781         /* value range - 0..100, increments in 100Mbps */
782 #define FUNC_MF_CFG_MIN_BW_MASK                     0x00ff0000
783 #define FUNC_MF_CFG_MIN_BW_SHIFT                    16
784 #define FUNC_MF_CFG_MIN_BW_DEFAULT                  0x00000000
785 #define FUNC_MF_CFG_MAX_BW_MASK                     0xff000000
786 #define FUNC_MF_CFG_MAX_BW_SHIFT                    24
787 #define FUNC_MF_CFG_MAX_BW_DEFAULT                  0x64000000
788
789         u32 mac_upper;          /* MAC */
790 #define FUNC_MF_CFG_UPPERMAC_MASK                   0x0000ffff
791 #define FUNC_MF_CFG_UPPERMAC_SHIFT                  0
792 #define FUNC_MF_CFG_UPPERMAC_DEFAULT                FUNC_MF_CFG_UPPERMAC_MASK
793         u32 mac_lower;
794 #define FUNC_MF_CFG_LOWERMAC_DEFAULT                0xffffffff
795
796         u32 e1hov_tag;  /* VNI */
797 #define FUNC_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
798 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT                 0
799 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT               FUNC_MF_CFG_E1HOV_TAG_MASK
800
801         u32 reserved[2];
802
803 };
804
805 struct mf_cfg {
806
807         struct shared_mf_cfg    shared_mf_config;
808         struct port_mf_cfg      port_mf_config[PORT_MAX];
809 #if defined(b710)
810         struct func_mf_cfg      func_mf_config[E1_FUNC_MAX];
811 #else
812         struct func_mf_cfg      func_mf_config[E1H_FUNC_MAX];
813 #endif
814
815 };
816
817
818 /****************************************************************************
819  * Shared Memory Region                                                     *
820  ****************************************************************************/
821 struct shmem_region {                          /*   SharedMem Offset (size) */
822
823         u32                     validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
824 #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
825 #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
826         /* validity bits */
827 #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
828 #define SHR_MEM_VALIDITY_MB                         0x00200000
829 #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
830 #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
831         /* One licensing bit should be set */
832 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
833 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
834 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
835 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
836         /* Active MFW */
837 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
838 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
839 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
840 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
841 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
842 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
843
844         struct shm_dev_info     dev_info;                /* 0x8     (0x438) */
845
846         u8                      reserved[52*PORT_MAX];
847
848         /* FW information (for internal FW use) */
849         u32                     fw_info_fio_offset;    /* 0x4a8       (0x4) */
850         struct mgmtfw_state     mgmtfw_state;          /* 0x4ac     (0x1b8) */
851
852         struct drv_port_mb      port_mb[PORT_MAX];     /* 0x664 (16*2=0x20) */
853         struct drv_func_mb      func_mb[E1H_FUNC_MAX];
854
855         struct mf_cfg           mf_cfg;
856
857 };                                                     /* 0x6dc */
858
859
860 struct emac_stats {
861     u32     rx_stat_ifhcinoctets;
862     u32     rx_stat_ifhcinbadoctets;
863     u32     rx_stat_etherstatsfragments;
864     u32     rx_stat_ifhcinucastpkts;
865     u32     rx_stat_ifhcinmulticastpkts;
866     u32     rx_stat_ifhcinbroadcastpkts;
867     u32     rx_stat_dot3statsfcserrors;
868     u32     rx_stat_dot3statsalignmenterrors;
869     u32     rx_stat_dot3statscarriersenseerrors;
870     u32     rx_stat_xonpauseframesreceived;
871     u32     rx_stat_xoffpauseframesreceived;
872     u32     rx_stat_maccontrolframesreceived;
873     u32     rx_stat_xoffstateentered;
874     u32     rx_stat_dot3statsframestoolong;
875     u32     rx_stat_etherstatsjabbers;
876     u32     rx_stat_etherstatsundersizepkts;
877     u32     rx_stat_etherstatspkts64octets;
878     u32     rx_stat_etherstatspkts65octetsto127octets;
879     u32     rx_stat_etherstatspkts128octetsto255octets;
880     u32     rx_stat_etherstatspkts256octetsto511octets;
881     u32     rx_stat_etherstatspkts512octetsto1023octets;
882     u32     rx_stat_etherstatspkts1024octetsto1522octets;
883     u32     rx_stat_etherstatspktsover1522octets;
884
885     u32     rx_stat_falsecarriererrors;
886
887     u32     tx_stat_ifhcoutoctets;
888     u32     tx_stat_ifhcoutbadoctets;
889     u32     tx_stat_etherstatscollisions;
890     u32     tx_stat_outxonsent;
891     u32     tx_stat_outxoffsent;
892     u32     tx_stat_flowcontroldone;
893     u32     tx_stat_dot3statssinglecollisionframes;
894     u32     tx_stat_dot3statsmultiplecollisionframes;
895     u32     tx_stat_dot3statsdeferredtransmissions;
896     u32     tx_stat_dot3statsexcessivecollisions;
897     u32     tx_stat_dot3statslatecollisions;
898     u32     tx_stat_ifhcoutucastpkts;
899     u32     tx_stat_ifhcoutmulticastpkts;
900     u32     tx_stat_ifhcoutbroadcastpkts;
901     u32     tx_stat_etherstatspkts64octets;
902     u32     tx_stat_etherstatspkts65octetsto127octets;
903     u32     tx_stat_etherstatspkts128octetsto255octets;
904     u32     tx_stat_etherstatspkts256octetsto511octets;
905     u32     tx_stat_etherstatspkts512octetsto1023octets;
906     u32     tx_stat_etherstatspkts1024octetsto1522octets;
907     u32     tx_stat_etherstatspktsover1522octets;
908     u32     tx_stat_dot3statsinternalmactransmiterrors;
909 };
910
911
912 struct bmac_stats {
913     u32     tx_stat_gtpkt_lo;
914     u32     tx_stat_gtpkt_hi;
915     u32     tx_stat_gtxpf_lo;
916     u32     tx_stat_gtxpf_hi;
917     u32     tx_stat_gtfcs_lo;
918     u32     tx_stat_gtfcs_hi;
919     u32     tx_stat_gtmca_lo;
920     u32     tx_stat_gtmca_hi;
921     u32     tx_stat_gtbca_lo;
922     u32     tx_stat_gtbca_hi;
923     u32     tx_stat_gtfrg_lo;
924     u32     tx_stat_gtfrg_hi;
925     u32     tx_stat_gtovr_lo;
926     u32     tx_stat_gtovr_hi;
927     u32     tx_stat_gt64_lo;
928     u32     tx_stat_gt64_hi;
929     u32     tx_stat_gt127_lo;
930     u32     tx_stat_gt127_hi;
931     u32     tx_stat_gt255_lo;
932     u32     tx_stat_gt255_hi;
933     u32     tx_stat_gt511_lo;
934     u32     tx_stat_gt511_hi;
935     u32     tx_stat_gt1023_lo;
936     u32     tx_stat_gt1023_hi;
937     u32     tx_stat_gt1518_lo;
938     u32     tx_stat_gt1518_hi;
939     u32     tx_stat_gt2047_lo;
940     u32     tx_stat_gt2047_hi;
941     u32     tx_stat_gt4095_lo;
942     u32     tx_stat_gt4095_hi;
943     u32     tx_stat_gt9216_lo;
944     u32     tx_stat_gt9216_hi;
945     u32     tx_stat_gt16383_lo;
946     u32     tx_stat_gt16383_hi;
947     u32     tx_stat_gtmax_lo;
948     u32     tx_stat_gtmax_hi;
949     u32     tx_stat_gtufl_lo;
950     u32     tx_stat_gtufl_hi;
951     u32     tx_stat_gterr_lo;
952     u32     tx_stat_gterr_hi;
953     u32     tx_stat_gtbyt_lo;
954     u32     tx_stat_gtbyt_hi;
955
956     u32     rx_stat_gr64_lo;
957     u32     rx_stat_gr64_hi;
958     u32     rx_stat_gr127_lo;
959     u32     rx_stat_gr127_hi;
960     u32     rx_stat_gr255_lo;
961     u32     rx_stat_gr255_hi;
962     u32     rx_stat_gr511_lo;
963     u32     rx_stat_gr511_hi;
964     u32     rx_stat_gr1023_lo;
965     u32     rx_stat_gr1023_hi;
966     u32     rx_stat_gr1518_lo;
967     u32     rx_stat_gr1518_hi;
968     u32     rx_stat_gr2047_lo;
969     u32     rx_stat_gr2047_hi;
970     u32     rx_stat_gr4095_lo;
971     u32     rx_stat_gr4095_hi;
972     u32     rx_stat_gr9216_lo;
973     u32     rx_stat_gr9216_hi;
974     u32     rx_stat_gr16383_lo;
975     u32     rx_stat_gr16383_hi;
976     u32     rx_stat_grmax_lo;
977     u32     rx_stat_grmax_hi;
978     u32     rx_stat_grpkt_lo;
979     u32     rx_stat_grpkt_hi;
980     u32     rx_stat_grfcs_lo;
981     u32     rx_stat_grfcs_hi;
982     u32     rx_stat_grmca_lo;
983     u32     rx_stat_grmca_hi;
984     u32     rx_stat_grbca_lo;
985     u32     rx_stat_grbca_hi;
986     u32     rx_stat_grxcf_lo;
987     u32     rx_stat_grxcf_hi;
988     u32     rx_stat_grxpf_lo;
989     u32     rx_stat_grxpf_hi;
990     u32     rx_stat_grxuo_lo;
991     u32     rx_stat_grxuo_hi;
992     u32     rx_stat_grjbr_lo;
993     u32     rx_stat_grjbr_hi;
994     u32     rx_stat_grovr_lo;
995     u32     rx_stat_grovr_hi;
996     u32     rx_stat_grflr_lo;
997     u32     rx_stat_grflr_hi;
998     u32     rx_stat_grmeg_lo;
999     u32     rx_stat_grmeg_hi;
1000     u32     rx_stat_grmeb_lo;
1001     u32     rx_stat_grmeb_hi;
1002     u32     rx_stat_grbyt_lo;
1003     u32     rx_stat_grbyt_hi;
1004     u32     rx_stat_grund_lo;
1005     u32     rx_stat_grund_hi;
1006     u32     rx_stat_grfrg_lo;
1007     u32     rx_stat_grfrg_hi;
1008     u32     rx_stat_grerb_lo;
1009     u32     rx_stat_grerb_hi;
1010     u32     rx_stat_grfre_lo;
1011     u32     rx_stat_grfre_hi;
1012     u32     rx_stat_gripj_lo;
1013     u32     rx_stat_gripj_hi;
1014 };
1015
1016
1017 union mac_stats {
1018     struct emac_stats   emac_stats;
1019     struct bmac_stats   bmac_stats;
1020 };
1021
1022
1023 struct mac_stx {
1024     /* in_bad_octets */
1025     u32     rx_stat_ifhcinbadoctets_hi;
1026     u32     rx_stat_ifhcinbadoctets_lo;
1027
1028     /* out_bad_octets */
1029     u32     tx_stat_ifhcoutbadoctets_hi;
1030     u32     tx_stat_ifhcoutbadoctets_lo;
1031
1032     /* crc_receive_errors */
1033     u32     rx_stat_dot3statsfcserrors_hi;
1034     u32     rx_stat_dot3statsfcserrors_lo;
1035     /* alignment_errors */
1036     u32     rx_stat_dot3statsalignmenterrors_hi;
1037     u32     rx_stat_dot3statsalignmenterrors_lo;
1038     /* carrier_sense_errors */
1039     u32     rx_stat_dot3statscarriersenseerrors_hi;
1040     u32     rx_stat_dot3statscarriersenseerrors_lo;
1041     /* false_carrier_detections */
1042     u32     rx_stat_falsecarriererrors_hi;
1043     u32     rx_stat_falsecarriererrors_lo;
1044
1045     /* runt_packets_received */
1046     u32     rx_stat_etherstatsundersizepkts_hi;
1047     u32     rx_stat_etherstatsundersizepkts_lo;
1048     /* jabber_packets_received */
1049     u32     rx_stat_dot3statsframestoolong_hi;
1050     u32     rx_stat_dot3statsframestoolong_lo;
1051
1052     /* error_runt_packets_received */
1053     u32     rx_stat_etherstatsfragments_hi;
1054     u32     rx_stat_etherstatsfragments_lo;
1055     /* error_jabber_packets_received */
1056     u32     rx_stat_etherstatsjabbers_hi;
1057     u32     rx_stat_etherstatsjabbers_lo;
1058
1059     /* control_frames_received */
1060     u32     rx_stat_maccontrolframesreceived_hi;
1061     u32     rx_stat_maccontrolframesreceived_lo;
1062     u32     rx_stat_bmac_xpf_hi;
1063     u32     rx_stat_bmac_xpf_lo;
1064     u32     rx_stat_bmac_xcf_hi;
1065     u32     rx_stat_bmac_xcf_lo;
1066
1067     /* xoff_state_entered */
1068     u32     rx_stat_xoffstateentered_hi;
1069     u32     rx_stat_xoffstateentered_lo;
1070     /* pause_xon_frames_received */
1071     u32     rx_stat_xonpauseframesreceived_hi;
1072     u32     rx_stat_xonpauseframesreceived_lo;
1073     /* pause_xoff_frames_received */
1074     u32     rx_stat_xoffpauseframesreceived_hi;
1075     u32     rx_stat_xoffpauseframesreceived_lo;
1076     /* pause_xon_frames_transmitted */
1077     u32     tx_stat_outxonsent_hi;
1078     u32     tx_stat_outxonsent_lo;
1079     /* pause_xoff_frames_transmitted */
1080     u32     tx_stat_outxoffsent_hi;
1081     u32     tx_stat_outxoffsent_lo;
1082     /* flow_control_done */
1083     u32     tx_stat_flowcontroldone_hi;
1084     u32     tx_stat_flowcontroldone_lo;
1085
1086     /* ether_stats_collisions */
1087     u32     tx_stat_etherstatscollisions_hi;
1088     u32     tx_stat_etherstatscollisions_lo;
1089     /* single_collision_transmit_frames */
1090     u32     tx_stat_dot3statssinglecollisionframes_hi;
1091     u32     tx_stat_dot3statssinglecollisionframes_lo;
1092     /* multiple_collision_transmit_frames */
1093     u32     tx_stat_dot3statsmultiplecollisionframes_hi;
1094     u32     tx_stat_dot3statsmultiplecollisionframes_lo;
1095     /* deferred_transmissions */
1096     u32     tx_stat_dot3statsdeferredtransmissions_hi;
1097     u32     tx_stat_dot3statsdeferredtransmissions_lo;
1098     /* excessive_collision_frames */
1099     u32     tx_stat_dot3statsexcessivecollisions_hi;
1100     u32     tx_stat_dot3statsexcessivecollisions_lo;
1101     /* late_collision_frames */
1102     u32     tx_stat_dot3statslatecollisions_hi;
1103     u32     tx_stat_dot3statslatecollisions_lo;
1104
1105     /* frames_transmitted_64_bytes */
1106     u32     tx_stat_etherstatspkts64octets_hi;
1107     u32     tx_stat_etherstatspkts64octets_lo;
1108     /* frames_transmitted_65_127_bytes */
1109     u32     tx_stat_etherstatspkts65octetsto127octets_hi;
1110     u32     tx_stat_etherstatspkts65octetsto127octets_lo;
1111     /* frames_transmitted_128_255_bytes */
1112     u32     tx_stat_etherstatspkts128octetsto255octets_hi;
1113     u32     tx_stat_etherstatspkts128octetsto255octets_lo;
1114     /* frames_transmitted_256_511_bytes */
1115     u32     tx_stat_etherstatspkts256octetsto511octets_hi;
1116     u32     tx_stat_etherstatspkts256octetsto511octets_lo;
1117     /* frames_transmitted_512_1023_bytes */
1118     u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
1119     u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
1120     /* frames_transmitted_1024_1522_bytes */
1121     u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
1122     u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
1123     /* frames_transmitted_1523_9022_bytes */
1124     u32     tx_stat_etherstatspktsover1522octets_hi;
1125     u32     tx_stat_etherstatspktsover1522octets_lo;
1126     u32     tx_stat_bmac_2047_hi;
1127     u32     tx_stat_bmac_2047_lo;
1128     u32     tx_stat_bmac_4095_hi;
1129     u32     tx_stat_bmac_4095_lo;
1130     u32     tx_stat_bmac_9216_hi;
1131     u32     tx_stat_bmac_9216_lo;
1132     u32     tx_stat_bmac_16383_hi;
1133     u32     tx_stat_bmac_16383_lo;
1134
1135     /* internal_mac_transmit_errors */
1136     u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
1137     u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
1138
1139     /* if_out_discards */
1140     u32     tx_stat_bmac_ufl_hi;
1141     u32     tx_stat_bmac_ufl_lo;
1142 };
1143
1144
1145 #define MAC_STX_IDX_MAX                     2
1146
1147 struct host_port_stats {
1148     u32            host_port_stats_start;
1149
1150     struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1151
1152     u32            brb_drop_hi;
1153     u32            brb_drop_lo;
1154
1155     u32            host_port_stats_end;
1156 };
1157
1158
1159 struct host_func_stats {
1160     u32     host_func_stats_start;
1161
1162     u32     total_bytes_received_hi;
1163     u32     total_bytes_received_lo;
1164
1165     u32     total_bytes_transmitted_hi;
1166     u32     total_bytes_transmitted_lo;
1167
1168     u32     total_unicast_packets_received_hi;
1169     u32     total_unicast_packets_received_lo;
1170
1171     u32     total_multicast_packets_received_hi;
1172     u32     total_multicast_packets_received_lo;
1173
1174     u32     total_broadcast_packets_received_hi;
1175     u32     total_broadcast_packets_received_lo;
1176
1177     u32     total_unicast_packets_transmitted_hi;
1178     u32     total_unicast_packets_transmitted_lo;
1179
1180     u32     total_multicast_packets_transmitted_hi;
1181     u32     total_multicast_packets_transmitted_lo;
1182
1183     u32     total_broadcast_packets_transmitted_hi;
1184     u32     total_broadcast_packets_transmitted_lo;
1185
1186     u32     valid_bytes_received_hi;
1187     u32     valid_bytes_received_lo;
1188
1189     u32     host_func_stats_end;
1190 };
1191
1192
1193 #define BCM_5710_FW_MAJOR_VERSION                       4
1194 #define BCM_5710_FW_MINOR_VERSION                       8
1195 #define BCM_5710_FW_REVISION_VERSION                    53
1196 #define BCM_5710_FW_ENGINEERING_VERSION                 0
1197 #define BCM_5710_FW_COMPILE_FLAGS                       1
1198
1199
1200 /*
1201  * attention bits
1202  */
1203 struct atten_def_status_block {
1204         __le32 attn_bits;
1205         __le32 attn_bits_ack;
1206         u8 status_block_id;
1207         u8 reserved0;
1208         __le16 attn_bits_index;
1209         __le32 reserved1;
1210 };
1211
1212
1213 /*
1214  * common data for all protocols
1215  */
1216 struct doorbell_hdr {
1217         u8 header;
1218 #define DOORBELL_HDR_RX (0x1<<0)
1219 #define DOORBELL_HDR_RX_SHIFT 0
1220 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1221 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1222 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1223 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1224 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1225 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1226 };
1227
1228 /*
1229  * doorbell message sent to the chip
1230  */
1231 struct doorbell {
1232 #if defined(__BIG_ENDIAN)
1233         u16 zero_fill2;
1234         u8 zero_fill1;
1235         struct doorbell_hdr header;
1236 #elif defined(__LITTLE_ENDIAN)
1237         struct doorbell_hdr header;
1238         u8 zero_fill1;
1239         u16 zero_fill2;
1240 #endif
1241 };
1242
1243
1244 /*
1245  * IGU driver acknowledgement register
1246  */
1247 struct igu_ack_register {
1248 #if defined(__BIG_ENDIAN)
1249         u16 sb_id_and_flags;
1250 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1251 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1252 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1253 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1254 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1255 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1256 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1257 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1258 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1259 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1260         u16 status_block_index;
1261 #elif defined(__LITTLE_ENDIAN)
1262         u16 status_block_index;
1263         u16 sb_id_and_flags;
1264 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1265 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1266 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1267 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1268 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1269 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1270 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1271 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1272 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1273 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1274 #endif
1275 };
1276
1277
1278 /*
1279  * Parser parsing flags field
1280  */
1281 struct parsing_flags {
1282         __le16 flags;
1283 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1284 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1285 #define PARSING_FLAGS_VLAN (0x1<<1)
1286 #define PARSING_FLAGS_VLAN_SHIFT 1
1287 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1288 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1289 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1290 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1291 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1292 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1293 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1294 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1295 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1296 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1297 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1298 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1299 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1300 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1301 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1302 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1303 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1304 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1305 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1306 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1307 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1308 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1309 };
1310
1311
1312 struct regpair {
1313         __le32 lo;
1314         __le32 hi;
1315 };
1316
1317
1318 /*
1319  * dmae command structure
1320  */
1321 struct dmae_command {
1322         u32 opcode;
1323 #define DMAE_COMMAND_SRC (0x1<<0)
1324 #define DMAE_COMMAND_SRC_SHIFT 0
1325 #define DMAE_COMMAND_DST (0x3<<1)
1326 #define DMAE_COMMAND_DST_SHIFT 1
1327 #define DMAE_COMMAND_C_DST (0x1<<3)
1328 #define DMAE_COMMAND_C_DST_SHIFT 3
1329 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1330 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1331 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1332 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1333 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1334 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1335 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1336 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1337 #define DMAE_COMMAND_PORT (0x1<<11)
1338 #define DMAE_COMMAND_PORT_SHIFT 11
1339 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1340 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1341 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1342 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1343 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1344 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1345 #define DMAE_COMMAND_E1HVN (0x3<<15)
1346 #define DMAE_COMMAND_E1HVN_SHIFT 15
1347 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1348 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1349         u32 src_addr_lo;
1350         u32 src_addr_hi;
1351         u32 dst_addr_lo;
1352         u32 dst_addr_hi;
1353 #if defined(__BIG_ENDIAN)
1354         u16 reserved1;
1355         u16 len;
1356 #elif defined(__LITTLE_ENDIAN)
1357         u16 len;
1358         u16 reserved1;
1359 #endif
1360         u32 comp_addr_lo;
1361         u32 comp_addr_hi;
1362         u32 comp_val;
1363         u32 crc32;
1364         u32 crc32_c;
1365 #if defined(__BIG_ENDIAN)
1366         u16 crc16_c;
1367         u16 crc16;
1368 #elif defined(__LITTLE_ENDIAN)
1369         u16 crc16;
1370         u16 crc16_c;
1371 #endif
1372 #if defined(__BIG_ENDIAN)
1373         u16 reserved2;
1374         u16 crc_t10;
1375 #elif defined(__LITTLE_ENDIAN)
1376         u16 crc_t10;
1377         u16 reserved2;
1378 #endif
1379 #if defined(__BIG_ENDIAN)
1380         u16 xsum8;
1381         u16 xsum16;
1382 #elif defined(__LITTLE_ENDIAN)
1383         u16 xsum16;
1384         u16 xsum8;
1385 #endif
1386 };
1387
1388
1389 struct double_regpair {
1390         u32 regpair0_lo;
1391         u32 regpair0_hi;
1392         u32 regpair1_lo;
1393         u32 regpair1_hi;
1394 };
1395
1396
1397 /*
1398  * The eth storm context of Ustorm (configuration part)
1399  */
1400 struct ustorm_eth_st_context_config {
1401 #if defined(__BIG_ENDIAN)
1402         u8 flags;
1403 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1404 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1405 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1406 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1407 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1408 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1409 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1410 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1411 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1412 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1413 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1414 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1415         u8 status_block_id;
1416         u8 clientId;
1417         u8 sb_index_numbers;
1418 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1419 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1420 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1421 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1422 #elif defined(__LITTLE_ENDIAN)
1423         u8 sb_index_numbers;
1424 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1425 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1426 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1427 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1428         u8 clientId;
1429         u8 status_block_id;
1430         u8 flags;
1431 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1432 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1433 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1434 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1435 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1436 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1437 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1438 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1439 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1440 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1441 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1442 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1443 #endif
1444 #if defined(__BIG_ENDIAN)
1445         u16 bd_buff_size;
1446         u8 statistics_counter_id;
1447         u8 mc_alignment_log_size;
1448 #elif defined(__LITTLE_ENDIAN)
1449         u8 mc_alignment_log_size;
1450         u8 statistics_counter_id;
1451         u16 bd_buff_size;
1452 #endif
1453 #if defined(__BIG_ENDIAN)
1454         u8 __local_sge_prod;
1455         u8 __local_bd_prod;
1456         u16 sge_buff_size;
1457 #elif defined(__LITTLE_ENDIAN)
1458         u16 sge_buff_size;
1459         u8 __local_bd_prod;
1460         u8 __local_sge_prod;
1461 #endif
1462         u32 reserved;
1463         u32 bd_page_base_lo;
1464         u32 bd_page_base_hi;
1465         u32 sge_page_base_lo;
1466         u32 sge_page_base_hi;
1467 };
1468
1469 /*
1470  * The eth Rx Buffer Descriptor
1471  */
1472 struct eth_rx_bd {
1473         __le32 addr_lo;
1474         __le32 addr_hi;
1475 };
1476
1477 /*
1478  * The eth Rx SGE Descriptor
1479  */
1480 struct eth_rx_sge {
1481         __le32 addr_lo;
1482         __le32 addr_hi;
1483 };
1484
1485 /*
1486  * Local BDs and SGEs rings (in ETH)
1487  */
1488 struct eth_local_rx_rings {
1489         struct eth_rx_bd __local_bd_ring[16];
1490         struct eth_rx_sge __local_sge_ring[12];
1491 };
1492
1493 /*
1494  * The eth storm context of Ustorm
1495  */
1496 struct ustorm_eth_st_context {
1497         struct ustorm_eth_st_context_config common;
1498         struct eth_local_rx_rings __rings;
1499 };
1500
1501 /*
1502  * The eth storm context of Tstorm
1503  */
1504 struct tstorm_eth_st_context {
1505         u32 __reserved0[28];
1506 };
1507
1508 /*
1509  * The eth aggregative context section of Xstorm
1510  */
1511 struct xstorm_eth_extra_ag_context_section {
1512 #if defined(__BIG_ENDIAN)
1513         u8 __tcp_agg_vars1;
1514         u8 __reserved50;
1515         u16 __mss;
1516 #elif defined(__LITTLE_ENDIAN)
1517         u16 __mss;
1518         u8 __reserved50;
1519         u8 __tcp_agg_vars1;
1520 #endif
1521         u32 __snd_nxt;
1522         u32 __tx_wnd;
1523         u32 __snd_una;
1524         u32 __reserved53;
1525 #if defined(__BIG_ENDIAN)
1526         u8 __agg_val8_th;
1527         u8 __agg_val8;
1528         u16 __tcp_agg_vars2;
1529 #elif defined(__LITTLE_ENDIAN)
1530         u16 __tcp_agg_vars2;
1531         u8 __agg_val8;
1532         u8 __agg_val8_th;
1533 #endif
1534         u32 __reserved58;
1535         u32 __reserved59;
1536         u32 __reserved60;
1537         u32 __reserved61;
1538 #if defined(__BIG_ENDIAN)
1539         u16 __agg_val7_th;
1540         u16 __agg_val7;
1541 #elif defined(__LITTLE_ENDIAN)
1542         u16 __agg_val7;
1543         u16 __agg_val7_th;
1544 #endif
1545 #if defined(__BIG_ENDIAN)
1546         u8 __tcp_agg_vars5;
1547         u8 __tcp_agg_vars4;
1548         u8 __tcp_agg_vars3;
1549         u8 __reserved62;
1550 #elif defined(__LITTLE_ENDIAN)
1551         u8 __reserved62;
1552         u8 __tcp_agg_vars3;
1553         u8 __tcp_agg_vars4;
1554         u8 __tcp_agg_vars5;
1555 #endif
1556         u32 __tcp_agg_vars6;
1557 #if defined(__BIG_ENDIAN)
1558         u16 __agg_misc6;
1559         u16 __tcp_agg_vars7;
1560 #elif defined(__LITTLE_ENDIAN)
1561         u16 __tcp_agg_vars7;
1562         u16 __agg_misc6;
1563 #endif
1564         u32 __agg_val10;
1565         u32 __agg_val10_th;
1566 #if defined(__BIG_ENDIAN)
1567         u16 __reserved3;
1568         u8 __reserved2;
1569         u8 __da_only_cnt;
1570 #elif defined(__LITTLE_ENDIAN)
1571         u8 __da_only_cnt;
1572         u8 __reserved2;
1573         u16 __reserved3;
1574 #endif
1575 };
1576
1577 /*
1578  * The eth aggregative context of Xstorm
1579  */
1580 struct xstorm_eth_ag_context {
1581 #if defined(__BIG_ENDIAN)
1582         u16 __bd_prod;
1583         u8 __agg_vars1;
1584         u8 __state;
1585 #elif defined(__LITTLE_ENDIAN)
1586         u8 __state;
1587         u8 __agg_vars1;
1588         u16 __bd_prod;
1589 #endif
1590 #if defined(__BIG_ENDIAN)
1591         u8 cdu_reserved;
1592         u8 __agg_vars4;
1593         u8 __agg_vars3;
1594         u8 __agg_vars2;
1595 #elif defined(__LITTLE_ENDIAN)
1596         u8 __agg_vars2;
1597         u8 __agg_vars3;
1598         u8 __agg_vars4;
1599         u8 cdu_reserved;
1600 #endif
1601         u32 __more_packets_to_send;
1602 #if defined(__BIG_ENDIAN)
1603         u16 __agg_vars5;
1604         u16 __agg_val4_th;
1605 #elif defined(__LITTLE_ENDIAN)
1606         u16 __agg_val4_th;
1607         u16 __agg_vars5;
1608 #endif
1609         struct xstorm_eth_extra_ag_context_section __extra_section;
1610 #if defined(__BIG_ENDIAN)
1611         u16 __agg_vars7;
1612         u8 __agg_val3_th;
1613         u8 __agg_vars6;
1614 #elif defined(__LITTLE_ENDIAN)
1615         u8 __agg_vars6;
1616         u8 __agg_val3_th;
1617         u16 __agg_vars7;
1618 #endif
1619 #if defined(__BIG_ENDIAN)
1620         u16 __agg_val11_th;
1621         u16 __agg_val11;
1622 #elif defined(__LITTLE_ENDIAN)
1623         u16 __agg_val11;
1624         u16 __agg_val11_th;
1625 #endif
1626 #if defined(__BIG_ENDIAN)
1627         u8 __reserved1;
1628         u8 __agg_val6_th;
1629         u16 __agg_val9;
1630 #elif defined(__LITTLE_ENDIAN)
1631         u16 __agg_val9;
1632         u8 __agg_val6_th;
1633         u8 __reserved1;
1634 #endif
1635 #if defined(__BIG_ENDIAN)
1636         u16 __agg_val2_th;
1637         u16 __agg_val2;
1638 #elif defined(__LITTLE_ENDIAN)
1639         u16 __agg_val2;
1640         u16 __agg_val2_th;
1641 #endif
1642         u32 __agg_vars8;
1643 #if defined(__BIG_ENDIAN)
1644         u16 __agg_misc0;
1645         u16 __agg_val4;
1646 #elif defined(__LITTLE_ENDIAN)
1647         u16 __agg_val4;
1648         u16 __agg_misc0;
1649 #endif
1650 #if defined(__BIG_ENDIAN)
1651         u8 __agg_val3;
1652         u8 __agg_val6;
1653         u8 __agg_val5_th;
1654         u8 __agg_val5;
1655 #elif defined(__LITTLE_ENDIAN)
1656         u8 __agg_val5;
1657         u8 __agg_val5_th;
1658         u8 __agg_val6;
1659         u8 __agg_val3;
1660 #endif
1661 #if defined(__BIG_ENDIAN)
1662         u16 __agg_misc1;
1663         u16 __bd_ind_max_val;
1664 #elif defined(__LITTLE_ENDIAN)
1665         u16 __bd_ind_max_val;
1666         u16 __agg_misc1;
1667 #endif
1668         u32 __reserved57;
1669         u32 __agg_misc4;
1670         u32 __agg_misc5;
1671 };
1672
1673 /*
1674  * The eth extra aggregative context section of Tstorm
1675  */
1676 struct tstorm_eth_extra_ag_context_section {
1677         u32 __agg_val1;
1678 #if defined(__BIG_ENDIAN)
1679         u8 __tcp_agg_vars2;
1680         u8 __agg_val3;
1681         u16 __agg_val2;
1682 #elif defined(__LITTLE_ENDIAN)
1683         u16 __agg_val2;
1684         u8 __agg_val3;
1685         u8 __tcp_agg_vars2;
1686 #endif
1687 #if defined(__BIG_ENDIAN)
1688         u16 __agg_val5;
1689         u8 __agg_val6;
1690         u8 __tcp_agg_vars3;
1691 #elif defined(__LITTLE_ENDIAN)
1692         u8 __tcp_agg_vars3;
1693         u8 __agg_val6;
1694         u16 __agg_val5;
1695 #endif
1696         u32 __reserved63;
1697         u32 __reserved64;
1698         u32 __reserved65;
1699         u32 __reserved66;
1700         u32 __reserved67;
1701         u32 __tcp_agg_vars1;
1702         u32 __reserved61;
1703         u32 __reserved62;
1704         u32 __reserved2;
1705 };
1706
1707 /*
1708  * The eth aggregative context of Tstorm
1709  */
1710 struct tstorm_eth_ag_context {
1711 #if defined(__BIG_ENDIAN)
1712         u16 __reserved54;
1713         u8 __agg_vars1;
1714         u8 __state;
1715 #elif defined(__LITTLE_ENDIAN)
1716         u8 __state;
1717         u8 __agg_vars1;
1718         u16 __reserved54;
1719 #endif
1720 #if defined(__BIG_ENDIAN)
1721         u16 __agg_val4;
1722         u16 __agg_vars2;
1723 #elif defined(__LITTLE_ENDIAN)
1724         u16 __agg_vars2;
1725         u16 __agg_val4;
1726 #endif
1727         struct tstorm_eth_extra_ag_context_section __extra_section;
1728 };
1729
1730 /*
1731  * The eth aggregative context of Cstorm
1732  */
1733 struct cstorm_eth_ag_context {
1734         u32 __agg_vars1;
1735 #if defined(__BIG_ENDIAN)
1736         u8 __aux1_th;
1737         u8 __aux1_val;
1738         u16 __agg_vars2;
1739 #elif defined(__LITTLE_ENDIAN)
1740         u16 __agg_vars2;
1741         u8 __aux1_val;
1742         u8 __aux1_th;
1743 #endif
1744         u32 __num_of_treated_packet;
1745         u32 __last_packet_treated;
1746 #if defined(__BIG_ENDIAN)
1747         u16 __reserved58;
1748         u16 __reserved57;
1749 #elif defined(__LITTLE_ENDIAN)
1750         u16 __reserved57;
1751         u16 __reserved58;
1752 #endif
1753 #if defined(__BIG_ENDIAN)
1754         u8 __reserved62;
1755         u8 __reserved61;
1756         u8 __reserved60;
1757         u8 __reserved59;
1758 #elif defined(__LITTLE_ENDIAN)
1759         u8 __reserved59;
1760         u8 __reserved60;
1761         u8 __reserved61;
1762         u8 __reserved62;
1763 #endif
1764 #if defined(__BIG_ENDIAN)
1765         u16 __reserved64;
1766         u16 __reserved63;
1767 #elif defined(__LITTLE_ENDIAN)
1768         u16 __reserved63;
1769         u16 __reserved64;
1770 #endif
1771         u32 __reserved65;
1772 #if defined(__BIG_ENDIAN)
1773         u16 __agg_vars3;
1774         u16 __rq_inv_cnt;
1775 #elif defined(__LITTLE_ENDIAN)
1776         u16 __rq_inv_cnt;
1777         u16 __agg_vars3;
1778 #endif
1779 #if defined(__BIG_ENDIAN)
1780         u16 __packet_index_th;
1781         u16 __packet_index;
1782 #elif defined(__LITTLE_ENDIAN)
1783         u16 __packet_index;
1784         u16 __packet_index_th;
1785 #endif
1786 };
1787
1788 /*
1789  * The eth aggregative context of Ustorm
1790  */
1791 struct ustorm_eth_ag_context {
1792 #if defined(__BIG_ENDIAN)
1793         u8 __aux_counter_flags;
1794         u8 __agg_vars2;
1795         u8 __agg_vars1;
1796         u8 __state;
1797 #elif defined(__LITTLE_ENDIAN)
1798         u8 __state;
1799         u8 __agg_vars1;
1800         u8 __agg_vars2;
1801         u8 __aux_counter_flags;
1802 #endif
1803 #if defined(__BIG_ENDIAN)
1804         u8 cdu_usage;
1805         u8 __agg_misc2;
1806         u16 __agg_misc1;
1807 #elif defined(__LITTLE_ENDIAN)
1808         u16 __agg_misc1;
1809         u8 __agg_misc2;
1810         u8 cdu_usage;
1811 #endif
1812         u32 __agg_misc4;
1813 #if defined(__BIG_ENDIAN)
1814         u8 __agg_val3_th;
1815         u8 __agg_val3;
1816         u16 __agg_misc3;
1817 #elif defined(__LITTLE_ENDIAN)
1818         u16 __agg_misc3;
1819         u8 __agg_val3;
1820         u8 __agg_val3_th;
1821 #endif
1822         u32 __agg_val1;
1823         u32 __agg_misc4_th;
1824 #if defined(__BIG_ENDIAN)
1825         u16 __agg_val2_th;
1826         u16 __agg_val2;
1827 #elif defined(__LITTLE_ENDIAN)
1828         u16 __agg_val2;
1829         u16 __agg_val2_th;
1830 #endif
1831 #if defined(__BIG_ENDIAN)
1832         u16 __reserved2;
1833         u8 __decision_rules;
1834         u8 __decision_rule_enable_bits;
1835 #elif defined(__LITTLE_ENDIAN)
1836         u8 __decision_rule_enable_bits;
1837         u8 __decision_rules;
1838         u16 __reserved2;
1839 #endif
1840 };
1841
1842 /*
1843  * Timers connection context
1844  */
1845 struct timers_block_context {
1846         u32 __reserved_0;
1847         u32 __reserved_1;
1848         u32 __reserved_2;
1849         u32 flags;
1850 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1851 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1852 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1853 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1854 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1855 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1856 };
1857
1858 /*
1859  * structure for easy accessibility to assembler
1860  */
1861 struct eth_tx_bd_flags {
1862         u8 as_bitfield;
1863 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1864 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1865 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1866 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1867 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1868 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1869 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1870 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1871 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1872 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1873 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1874 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1875 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1876 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1877 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1878 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1879 };
1880
1881 /*
1882  * The eth Tx Buffer Descriptor
1883  */
1884 struct eth_tx_bd {
1885         __le32 addr_lo;
1886         __le32 addr_hi;
1887         __le16 nbd;
1888         __le16 nbytes;
1889         __le16 vlan;
1890         struct eth_tx_bd_flags bd_flags;
1891         u8 general_data;
1892 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1893 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1894 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1895 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1896 };
1897
1898 /*
1899  * Tx parsing BD structure for ETH,Relevant in START
1900  */
1901 struct eth_tx_parse_bd {
1902         u8 global_data;
1903 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1904 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1905 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1906 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1907 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1908 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1909 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1910 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1911 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1912 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1913         u8 tcp_flags;
1914 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1915 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1916 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1917 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1918 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1919 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1920 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1921 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1922 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1923 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1924 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1925 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1926 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1927 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1928 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1929 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1930         u8 ip_hlen;
1931         s8 cs_offset;
1932         __le16 total_hlen;
1933         __le16 lso_mss;
1934         __le16 tcp_pseudo_csum;
1935         __le16 ip_id;
1936         __le32 tcp_send_seq;
1937 };
1938
1939 /*
1940  * The last BD in the BD memory will hold a pointer to the next BD memory
1941  */
1942 struct eth_tx_next_bd {
1943         u32 addr_lo;
1944         u32 addr_hi;
1945         u8 reserved[8];
1946 };
1947
1948 /*
1949  * union for 3 Bd types
1950  */
1951 union eth_tx_bd_types {
1952         struct eth_tx_bd reg_bd;
1953         struct eth_tx_parse_bd parse_bd;
1954         struct eth_tx_next_bd next_bd;
1955 };
1956
1957 /*
1958  * The eth storm context of Xstorm
1959  */
1960 struct xstorm_eth_st_context {
1961         u32 tx_bd_page_base_lo;
1962         u32 tx_bd_page_base_hi;
1963 #if defined(__BIG_ENDIAN)
1964         u16 tx_bd_cons;
1965         u8 statistics_data;
1966 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1967 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1968 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1969 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1970         u8 __local_tx_bd_prod;
1971 #elif defined(__LITTLE_ENDIAN)
1972         u8 __local_tx_bd_prod;
1973         u8 statistics_data;
1974 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1975 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1976 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1977 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1978         u16 tx_bd_cons;
1979 #endif
1980         u32 db_data_addr_lo;
1981         u32 db_data_addr_hi;
1982         u32 __pkt_cons;
1983         u32 __gso_next;
1984         u32 is_eth_conn_1b;
1985         union eth_tx_bd_types __bds[13];
1986 };
1987
1988 /*
1989  * The eth storm context of Cstorm
1990  */
1991 struct cstorm_eth_st_context {
1992 #if defined(__BIG_ENDIAN)
1993         u16 __reserved0;
1994         u8 sb_index_number;
1995         u8 status_block_id;
1996 #elif defined(__LITTLE_ENDIAN)
1997         u8 status_block_id;
1998         u8 sb_index_number;
1999         u16 __reserved0;
2000 #endif
2001         u32 __reserved1[3];
2002 };
2003
2004 /*
2005  * Ethernet connection context
2006  */
2007 struct eth_context {
2008         struct ustorm_eth_st_context ustorm_st_context;
2009         struct tstorm_eth_st_context tstorm_st_context;
2010         struct xstorm_eth_ag_context xstorm_ag_context;
2011         struct tstorm_eth_ag_context tstorm_ag_context;
2012         struct cstorm_eth_ag_context cstorm_ag_context;
2013         struct ustorm_eth_ag_context ustorm_ag_context;
2014         struct timers_block_context timers_context;
2015         struct xstorm_eth_st_context xstorm_st_context;
2016         struct cstorm_eth_st_context cstorm_st_context;
2017 };
2018
2019
2020 /*
2021  * Ethernet doorbell
2022  */
2023 struct eth_tx_doorbell {
2024 #if defined(__BIG_ENDIAN)
2025         u16 npackets;
2026         u8 params;
2027 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2028 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2029 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2030 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2031 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2032 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2033         struct doorbell_hdr hdr;
2034 #elif defined(__LITTLE_ENDIAN)
2035         struct doorbell_hdr hdr;
2036         u8 params;
2037 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2038 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2039 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2040 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2041 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2042 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2043         u16 npackets;
2044 #endif
2045 };
2046
2047
2048 /*
2049  * ustorm status block
2050  */
2051 struct ustorm_def_status_block {
2052         __le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2053         __le16 status_block_index;
2054         u8 func;
2055         u8 status_block_id;
2056         __le32 __flags;
2057 };
2058
2059 /*
2060  * cstorm status block
2061  */
2062 struct cstorm_def_status_block {
2063         __le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2064         __le16 status_block_index;
2065         u8 func;
2066         u8 status_block_id;
2067         __le32 __flags;
2068 };
2069
2070 /*
2071  * xstorm status block
2072  */
2073 struct xstorm_def_status_block {
2074         __le16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2075         __le16 status_block_index;
2076         u8 func;
2077         u8 status_block_id;
2078         __le32 __flags;
2079 };
2080
2081 /*
2082  * tstorm status block
2083  */
2084 struct tstorm_def_status_block {
2085         __le16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2086         __le16 status_block_index;
2087         u8 func;
2088         u8 status_block_id;
2089         __le32 __flags;
2090 };
2091
2092 /*
2093  * host status block
2094  */
2095 struct host_def_status_block {
2096         struct atten_def_status_block atten_status_block;
2097         struct ustorm_def_status_block u_def_status_block;
2098         struct cstorm_def_status_block c_def_status_block;
2099         struct xstorm_def_status_block x_def_status_block;
2100         struct tstorm_def_status_block t_def_status_block;
2101 };
2102
2103
2104 /*
2105  * ustorm status block
2106  */
2107 struct ustorm_status_block {
2108         __le16 index_values[HC_USTORM_SB_NUM_INDICES];
2109         __le16 status_block_index;
2110         u8 func;
2111         u8 status_block_id;
2112         __le32 __flags;
2113 };
2114
2115 /*
2116  * cstorm status block
2117  */
2118 struct cstorm_status_block {
2119         __le16 index_values[HC_CSTORM_SB_NUM_INDICES];
2120         __le16 status_block_index;
2121         u8 func;
2122         u8 status_block_id;
2123         __le32 __flags;
2124 };
2125
2126 /*
2127  * host status block
2128  */
2129 struct host_status_block {
2130         struct ustorm_status_block u_status_block;
2131         struct cstorm_status_block c_status_block;
2132 };
2133
2134
2135 /*
2136  * The data for RSS setup ramrod
2137  */
2138 struct eth_client_setup_ramrod_data {
2139         u32 client_id;
2140         u8 is_rdma;
2141         u8 is_fcoe;
2142         u16 reserved1;
2143 };
2144
2145
2146 /*
2147  * L2 dynamic host coalescing init parameters
2148  */
2149 struct eth_dynamic_hc_config {
2150         u32 threshold[3];
2151         u8 hc_timeout[4];
2152 };
2153
2154
2155 /*
2156  * regular eth FP CQE parameters struct
2157  */
2158 struct eth_fast_path_rx_cqe {
2159         u8 type_error_flags;
2160 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2161 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2162 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2163 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2164 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2165 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2166 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2167 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2168 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2169 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2170 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2171 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2172 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2173 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2174         u8 status_flags;
2175 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2176 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2177 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2178 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2179 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2180 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2181 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2182 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2183 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2184 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2185 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2186 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2187         u8 placement_offset;
2188         u8 queue_index;
2189         __le32 rss_hash_result;
2190         __le16 vlan_tag;
2191         __le16 pkt_len;
2192         __le16 len_on_bd;
2193         struct parsing_flags pars_flags;
2194         __le16 sgl[8];
2195 };
2196
2197
2198 /*
2199  * The data for RSS setup ramrod
2200  */
2201 struct eth_halt_ramrod_data {
2202         u32 client_id;
2203         u32 reserved0;
2204 };
2205
2206
2207 /*
2208  * The data for statistics query ramrod
2209  */
2210 struct eth_query_ramrod_data {
2211 #if defined(__BIG_ENDIAN)
2212         u8 reserved0;
2213         u8 collect_port;
2214         u16 drv_counter;
2215 #elif defined(__LITTLE_ENDIAN)
2216         u16 drv_counter;
2217         u8 collect_port;
2218         u8 reserved0;
2219 #endif
2220         u32 ctr_id_vector;
2221 };
2222
2223
2224 /*
2225  * Place holder for ramrods protocol specific data
2226  */
2227 struct ramrod_data {
2228         __le32 data_lo;
2229         __le32 data_hi;
2230 };
2231
2232 /*
2233  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2234  */
2235 union eth_ramrod_data {
2236         struct ramrod_data general;
2237 };
2238
2239
2240 /*
2241  * Eth Rx Cqe structure- general structure for ramrods
2242  */
2243 struct common_ramrod_eth_rx_cqe {
2244         u8 ramrod_type;
2245 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2246 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2247 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2248 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
2249         u8 conn_type;
2250         __le16 reserved1;
2251         __le32 conn_and_cmd_data;
2252 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2253 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2254 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2255 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2256         struct ramrod_data protocol_data;
2257         __le32 reserved2[4];
2258 };
2259
2260 /*
2261  * Rx Last CQE in page (in ETH)
2262  */
2263 struct eth_rx_cqe_next_page {
2264         __le32 addr_lo;
2265         __le32 addr_hi;
2266         __le32 reserved[6];
2267 };
2268
2269 /*
2270  * union for all eth rx cqe types (fix their sizes)
2271  */
2272 union eth_rx_cqe {
2273         struct eth_fast_path_rx_cqe fast_path_cqe;
2274         struct common_ramrod_eth_rx_cqe ramrod_cqe;
2275         struct eth_rx_cqe_next_page next_page_cqe;
2276 };
2277
2278
2279 /*
2280  * common data for all protocols
2281  */
2282 struct spe_hdr {
2283         __le32 conn_and_cmd_data;
2284 #define SPE_HDR_CID (0xFFFFFF<<0)
2285 #define SPE_HDR_CID_SHIFT 0
2286 #define SPE_HDR_CMD_ID (0xFF<<24)
2287 #define SPE_HDR_CMD_ID_SHIFT 24
2288         __le16 type;
2289 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2290 #define SPE_HDR_CONN_TYPE_SHIFT 0
2291 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2292 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2293         __le16 reserved;
2294 };
2295
2296 /*
2297  * Ethernet slow path element
2298  */
2299 union eth_specific_data {
2300         u8 protocol_data[8];
2301         struct regpair mac_config_addr;
2302         struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2303         struct eth_halt_ramrod_data halt_ramrod_data;
2304         struct regpair leading_cqe_addr;
2305         struct regpair update_data_addr;
2306         struct eth_query_ramrod_data query_ramrod_data;
2307 };
2308
2309 /*
2310  * Ethernet slow path element
2311  */
2312 struct eth_spe {
2313         struct spe_hdr hdr;
2314         union eth_specific_data data;
2315 };
2316
2317
2318 /*
2319  * doorbell data in host memory
2320  */
2321 struct eth_tx_db_data {
2322         __le32 packets_prod;
2323         __le16 bds_prod;
2324         __le16 reserved;
2325 };
2326
2327
2328 /*
2329  * Common configuration parameters per function in Tstorm
2330  */
2331 struct tstorm_eth_function_common_config {
2332 #if defined(__BIG_ENDIAN)
2333         u8 leading_client_id;
2334         u8 rss_result_mask;
2335         u16 config_flags;
2336 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2337 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2338 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2339 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2340 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2341 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2342 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2343 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2344 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2345 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2346 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2347 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2348 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2349 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2350 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2351 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2352 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2353 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2354 #elif defined(__LITTLE_ENDIAN)
2355         u16 config_flags;
2356 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2357 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2358 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2359 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2360 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2361 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2362 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2363 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2364 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2365 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2366 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2367 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2368 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2369 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2370 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2371 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2372 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2373 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2374         u8 rss_result_mask;
2375         u8 leading_client_id;
2376 #endif
2377         u16 vlan_id[2];
2378 };
2379
2380 /*
2381  * parameters for eth update ramrod
2382  */
2383 struct eth_update_ramrod_data {
2384         struct tstorm_eth_function_common_config func_config;
2385         u8 indirectionTable[128];
2386 };
2387
2388
2389 /*
2390  * MAC filtering configuration command header
2391  */
2392 struct mac_configuration_hdr {
2393         u8 length;
2394         u8 offset;
2395         u16 client_id;
2396         u32 reserved1;
2397 };
2398
2399 /*
2400  * MAC address in list for ramrod
2401  */
2402 struct tstorm_cam_entry {
2403         __le16 lsb_mac_addr;
2404         __le16 middle_mac_addr;
2405         __le16 msb_mac_addr;
2406         __le16 flags;
2407 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2408 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2409 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2410 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2411 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2412 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2413 };
2414
2415 /*
2416  * MAC filtering: CAM target table entry
2417  */
2418 struct tstorm_cam_target_table_entry {
2419         u8 flags;
2420 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2421 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2422 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2423 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2424 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2425 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2426 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2427 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2428 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2429 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2430         u8 client_id;
2431         u16 vlan_id;
2432 };
2433
2434 /*
2435  * MAC address in list for ramrod
2436  */
2437 struct mac_configuration_entry {
2438         struct tstorm_cam_entry cam_entry;
2439         struct tstorm_cam_target_table_entry target_table_entry;
2440 };
2441
2442 /*
2443  * MAC filtering configuration command
2444  */
2445 struct mac_configuration_cmd {
2446         struct mac_configuration_hdr hdr;
2447         struct mac_configuration_entry config_table[64];
2448 };
2449
2450
2451 /*
2452  * MAC address in list for ramrod
2453  */
2454 struct mac_configuration_entry_e1h {
2455         __le16 lsb_mac_addr;
2456         __le16 middle_mac_addr;
2457         __le16 msb_mac_addr;
2458         __le16 vlan_id;
2459         __le16 e1hov_id;
2460         u8 client_id;
2461         u8 flags;
2462 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2463 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2464 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2465 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2466 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2467 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2468 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2469 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2470 };
2471
2472 /*
2473  * MAC filtering configuration command
2474  */
2475 struct mac_configuration_cmd_e1h {
2476         struct mac_configuration_hdr hdr;
2477         struct mac_configuration_entry_e1h config_table[32];
2478 };
2479
2480
2481 /*
2482  * approximate-match multicast filtering for E1H per function in Tstorm
2483  */
2484 struct tstorm_eth_approximate_match_multicast_filtering {
2485         u32 mcast_add_hash_bit_array[8];
2486 };
2487
2488
2489 /*
2490  * Configuration parameters per client in Tstorm
2491  */
2492 struct tstorm_eth_client_config {
2493 #if defined(__BIG_ENDIAN)
2494         u8 max_sges_for_packet;
2495         u8 statistics_counter_id;
2496         u16 mtu;
2497 #elif defined(__LITTLE_ENDIAN)
2498         u16 mtu;
2499         u8 statistics_counter_id;
2500         u8 max_sges_for_packet;
2501 #endif
2502 #if defined(__BIG_ENDIAN)
2503         u16 drop_flags;
2504 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2505 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2506 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2507 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2508 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2509 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2510 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2511 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2512 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2513 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2514         u16 config_flags;
2515 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2516 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2517 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2518 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2519 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2520 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2521 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2522 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2523 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2524 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2525 #elif defined(__LITTLE_ENDIAN)
2526         u16 config_flags;
2527 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2528 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2529 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2530 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2531 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2532 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2533 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2534 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2535 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2536 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2537         u16 drop_flags;
2538 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2539 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2540 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2541 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2542 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2543 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2544 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2545 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2546 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2547 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2548 #endif
2549 };
2550
2551
2552 /*
2553  * MAC filtering configuration parameters per port in Tstorm
2554  */
2555 struct tstorm_eth_mac_filter_config {
2556         u32 ucast_drop_all;
2557         u32 ucast_accept_all;
2558         u32 mcast_drop_all;
2559         u32 mcast_accept_all;
2560         u32 bcast_drop_all;
2561         u32 bcast_accept_all;
2562         u32 strict_vlan;
2563         u32 vlan_filter[2];
2564         u32 reserved;
2565 };
2566
2567
2568 /*
2569  * common flag to indicate existance of TPA.
2570  */
2571 struct tstorm_eth_tpa_exist {
2572 #if defined(__BIG_ENDIAN)
2573         u16 reserved1;
2574         u8 reserved0;
2575         u8 tpa_exist;
2576 #elif defined(__LITTLE_ENDIAN)
2577         u8 tpa_exist;
2578         u8 reserved0;
2579         u16 reserved1;
2580 #endif
2581         u32 reserved2;
2582 };
2583
2584
2585 /*
2586  * rx rings pause data for E1h only
2587  */
2588 struct ustorm_eth_rx_pause_data_e1h {
2589 #if defined(__BIG_ENDIAN)
2590         u16 bd_thr_low;
2591         u16 cqe_thr_low;
2592 #elif defined(__LITTLE_ENDIAN)
2593         u16 cqe_thr_low;
2594         u16 bd_thr_low;
2595 #endif
2596 #if defined(__BIG_ENDIAN)
2597         u16 cos;
2598         u16 sge_thr_low;
2599 #elif defined(__LITTLE_ENDIAN)
2600         u16 sge_thr_low;
2601         u16 cos;
2602 #endif
2603 #if defined(__BIG_ENDIAN)
2604         u16 bd_thr_high;
2605         u16 cqe_thr_high;
2606 #elif defined(__LITTLE_ENDIAN)
2607         u16 cqe_thr_high;
2608         u16 bd_thr_high;
2609 #endif
2610 #if defined(__BIG_ENDIAN)
2611         u16 reserved0;
2612         u16 sge_thr_high;
2613 #elif defined(__LITTLE_ENDIAN)
2614         u16 sge_thr_high;
2615         u16 reserved0;
2616 #endif
2617 };
2618
2619
2620 /*
2621  * Three RX producers for ETH
2622  */
2623 struct ustorm_eth_rx_producers {
2624 #if defined(__BIG_ENDIAN)
2625         u16 bd_prod;
2626         u16 cqe_prod;
2627 #elif defined(__LITTLE_ENDIAN)
2628         u16 cqe_prod;
2629         u16 bd_prod;
2630 #endif
2631 #if defined(__BIG_ENDIAN)
2632         u16 reserved;
2633         u16 sge_prod;
2634 #elif defined(__LITTLE_ENDIAN)
2635         u16 sge_prod;
2636         u16 reserved;
2637 #endif
2638 };
2639
2640
2641 /*
2642  * per-port SAFC demo variables
2643  */
2644 struct cmng_flags_per_port {
2645         u8 con_number[NUM_OF_PROTOCOLS];
2646         u32 cmng_enables;
2647 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2648 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2649 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2650 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2651 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2652 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2653 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2654 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2655 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2656 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2657 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
2658 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
2659 };
2660
2661
2662 /*
2663  * per-port rate shaping variables
2664  */
2665 struct rate_shaping_vars_per_port {
2666         u32 rs_periodic_timeout;
2667         u32 rs_threshold;
2668 };
2669
2670
2671 /*
2672  * per-port fairness variables
2673  */
2674 struct fairness_vars_per_port {
2675         u32 upper_bound;
2676         u32 fair_threshold;
2677         u32 fairness_timeout;
2678 };
2679
2680
2681 /*
2682  * per-port SAFC variables
2683  */
2684 struct safc_struct_per_port {
2685 #if defined(__BIG_ENDIAN)
2686         u16 __reserved1;
2687         u8 __reserved0;
2688         u8 safc_timeout_usec;
2689 #elif defined(__LITTLE_ENDIAN)
2690         u8 safc_timeout_usec;
2691         u8 __reserved0;
2692         u16 __reserved1;
2693 #endif
2694         u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2695 };
2696
2697
2698 /*
2699  * Per-port congestion management variables
2700  */
2701 struct cmng_struct_per_port {
2702         struct rate_shaping_vars_per_port rs_vars;
2703         struct fairness_vars_per_port fair_vars;
2704         struct safc_struct_per_port safc_vars;
2705         struct cmng_flags_per_port flags;
2706 };
2707
2708
2709 /*
2710  * Protocol-common statistics collected by the Xstorm (per client)
2711  */
2712 struct xstorm_per_client_stats {
2713         struct regpair total_sent_bytes;
2714         __le32 total_sent_pkts;
2715         __le32 unicast_pkts_sent;
2716         struct regpair unicast_bytes_sent;
2717         struct regpair multicast_bytes_sent;
2718         __le32 multicast_pkts_sent;
2719         __le32 broadcast_pkts_sent;
2720         struct regpair broadcast_bytes_sent;
2721         __le16 stats_counter;
2722         __le16 reserved0;
2723         __le32 reserved1;
2724 };
2725
2726
2727 /*
2728  * Common statistics collected by the Xstorm (per port)
2729  */
2730 struct xstorm_common_stats {
2731  struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2732 };
2733
2734
2735 /*
2736  * Protocol-common statistics collected by the Tstorm (per port)
2737  */
2738 struct tstorm_per_port_stats {
2739         __le32 mac_filter_discard;
2740         __le32 xxoverflow_discard;
2741         __le32 brb_truncate_discard;
2742         __le32 mac_discard;
2743 };
2744
2745
2746 /*
2747  * Protocol-common statistics collected by the Tstorm (per client)
2748  */
2749 struct tstorm_per_client_stats {
2750         struct regpair total_rcv_bytes;
2751         struct regpair rcv_unicast_bytes;
2752         struct regpair rcv_broadcast_bytes;
2753         struct regpair rcv_multicast_bytes;
2754         struct regpair rcv_error_bytes;
2755         __le32 checksum_discard;
2756         __le32 packets_too_big_discard;
2757         __le32 total_rcv_pkts;
2758         __le32 rcv_unicast_pkts;
2759         __le32 rcv_broadcast_pkts;
2760         __le32 rcv_multicast_pkts;
2761         __le32 no_buff_discard;
2762         __le32 ttl0_discard;
2763         __le16 stats_counter;
2764         __le16 reserved0;
2765         __le32 reserved1;
2766 };
2767
2768 /*
2769  * Protocol-common statistics collected by the Tstorm
2770  */
2771 struct tstorm_common_stats {
2772         struct tstorm_per_port_stats port_statistics;
2773  struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2774 };
2775
2776 /*
2777  * Protocol-common statistics collected by the Ustorm (per client)
2778  */
2779 struct ustorm_per_client_stats {
2780         struct regpair ucast_no_buff_bytes;
2781         struct regpair mcast_no_buff_bytes;
2782         struct regpair bcast_no_buff_bytes;
2783         __le32 ucast_no_buff_pkts;
2784         __le32 mcast_no_buff_pkts;
2785         __le32 bcast_no_buff_pkts;
2786         __le16 stats_counter;
2787         __le16 reserved0;
2788 };
2789
2790 /*
2791  * Protocol-common statistics collected by the Ustorm
2792  */
2793 struct ustorm_common_stats {
2794  struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
2795 };
2796
2797 /*
2798  * Eth statistics query structure for the eth_stats_query ramrod
2799  */
2800 struct eth_stats_query {
2801         struct xstorm_common_stats xstorm_common;
2802         struct tstorm_common_stats tstorm_common;
2803         struct ustorm_common_stats ustorm_common;
2804 };
2805
2806
2807 /*
2808  * per-vnic fairness variables
2809  */
2810 struct fairness_vars_per_vn {
2811         u32 cos_credit_delta[MAX_COS_NUMBER];
2812         u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2813         u32 vn_credit_delta;
2814         u32 __reserved0;
2815 };
2816
2817
2818 /*
2819  * FW version stored in the Xstorm RAM
2820  */
2821 struct fw_version {
2822 #if defined(__BIG_ENDIAN)
2823         u8 engineering;
2824         u8 revision;
2825         u8 minor;
2826         u8 major;
2827 #elif defined(__LITTLE_ENDIAN)
2828         u8 major;
2829         u8 minor;
2830         u8 revision;
2831         u8 engineering;
2832 #endif
2833         u32 flags;
2834 #define FW_VERSION_OPTIMIZED (0x1<<0)
2835 #define FW_VERSION_OPTIMIZED_SHIFT 0
2836 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2837 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2838 #define FW_VERSION_CHIP_VERSION (0x3<<2)
2839 #define FW_VERSION_CHIP_VERSION_SHIFT 2
2840 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2841 #define __FW_VERSION_RESERVED_SHIFT 4
2842 };
2843
2844
2845 /*
2846  * FW version stored in first line of pram
2847  */
2848 struct pram_fw_version {
2849         u8 major;
2850         u8 minor;
2851         u8 revision;
2852         u8 engineering;
2853         u8 flags;
2854 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2855 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2856 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2857 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2858 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2859 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2860 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2861 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2862 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2863 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2864 };
2865
2866
2867 /*
2868  * a single rate shaping counter. can be used as protocol or vnic counter
2869  */
2870 struct rate_shaping_counter {
2871         u32 quota;
2872 #if defined(__BIG_ENDIAN)
2873         u16 __reserved0;
2874         u16 rate;
2875 #elif defined(__LITTLE_ENDIAN)
2876         u16 rate;
2877         u16 __reserved0;
2878 #endif
2879 };
2880
2881
2882 /*
2883  * per-vnic rate shaping variables
2884  */
2885 struct rate_shaping_vars_per_vn {
2886         struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2887         struct rate_shaping_counter vn_counter;
2888 };
2889
2890
2891 /*
2892  * The send queue element
2893  */
2894 struct slow_path_element {
2895         struct spe_hdr hdr;
2896         u8 protocol_data[8];
2897 };
2898
2899
2900 /*
2901  * eth/toe flags that indicate if to query
2902  */
2903 struct stats_indication_flags {
2904         u32 collect_eth;
2905         u32 collect_toe;
2906 };
2907
2908