6fd959c34d1f34cff73a6f7a9c0daa8fe5d43577
[linux-2.6.git] / drivers / net / bnx2x_hsi.h
1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9
10
11 #define FUNC_0                          0
12 #define FUNC_1                          1
13 #define FUNC_MAX                        2
14
15
16 /* This value (in milliseconds) determines the frequency of the driver
17  * issuing the PULSE message code.  The firmware monitors this periodic
18  * pulse to determine when to switch to an OS-absent mode. */
19 #define DRV_PULSE_PERIOD_MS             250
20
21 /* This value (in milliseconds) determines how long the driver should
22  * wait for an acknowledgement from the firmware before timing out.  Once
23  * the firmware has timed out, the driver will assume there is no firmware
24  * running and there won't be any firmware-driver synchronization during a
25  * driver reset. */
26 #define FW_ACK_TIME_OUT_MS              5000
27
28 #define FW_ACK_POLL_TIME_MS             1
29
30 #define FW_ACK_NUM_OF_POLL      (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
31
32 /* LED Blink rate that will achieve ~15.9Hz */
33 #define LED_BLINK_RATE_VAL              480
34
35 /****************************************************************************
36  * Driver <-> FW Mailbox                                                    *
37  ****************************************************************************/
38 struct drv_fw_mb {
39         u32 drv_mb_header;
40 #define DRV_MSG_CODE_MASK                       0xffff0000
41 #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
42 #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
43 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
44 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
45 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
46 #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
47 #define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
48 #define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
49 #define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
50 #define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
51 #define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
52 #define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
53 #define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
54
55 #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
56
57         u32 drv_mb_param;
58
59         u32 fw_mb_header;
60 #define FW_MSG_CODE_MASK                        0xffff0000
61 #define FW_MSG_CODE_DRV_LOAD_COMMON             0x11000000
62 #define FW_MSG_CODE_DRV_LOAD_PORT               0x12000000
63 #define FW_MSG_CODE_DRV_LOAD_REFUSED            0x13000000
64 #define FW_MSG_CODE_DRV_LOAD_DONE               0x14000000
65 #define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x21000000
66 #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x22000000
67 #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x23000000
68 #define FW_MSG_CODE_DIAG_ENTER_DONE             0x50000000
69 #define FW_MSG_CODE_DIAG_REFUSE                 0x51000000
70 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70000000
71 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x71000000
72 #define FW_MSG_CODE_GET_KEY_DONE                0x80000000
73 #define FW_MSG_CODE_NO_KEY                      0x8f000000
74 #define FW_MSG_CODE_LIC_INFO_NOT_READY          0x8f800000
75 #define FW_MSG_CODE_L2B_PRAM_LOADED             0x90000000
76 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x91000000
77 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x92000000
78 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x93000000
79 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x94000000
80
81 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
82
83         u32 fw_mb_param;
84
85         u32 link_status;
86         /* Driver should update this field on any link change event */
87
88 #define LINK_STATUS_LINK_FLAG_MASK              0x00000001
89 #define LINK_STATUS_LINK_UP                     0x00000001
90 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK       0x0000001E
91 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
92 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
93 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
94 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
95 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
96 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
97 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
98 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
99 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
100 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
101 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
102 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
103 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
104 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
105 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD             (11<<1)
106 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD             (11<<1)
107 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD           (12<<1)
108 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD           (12<<1)
109 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD             (13<<1)
110 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD             (13<<1)
111 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD             (14<<1)
112 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD             (14<<1)
113 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD             (15<<1)
114 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD             (15<<1)
115
116 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
117 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
118
119 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
120 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
121 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
122
123 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
124 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
125 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
126 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
127 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
128 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
129 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
130
131 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
132 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
133
134 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
135 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
136
137 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
138 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
139 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
140 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
141 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
142
143 #define LINK_STATUS_SERDES_LINK                         0x00100000
144
145 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
146 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
147 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
148 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE         0x01000000
149 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE       0x02000000
150 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE         0x04000000
151 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE         0x08000000
152 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE         0x10000000
153
154         u32 drv_pulse_mb;
155 #define DRV_PULSE_SEQ_MASK                              0x00007fff
156 #define DRV_PULSE_SYSTEM_TIME_MASK                      0xffff0000
157         /* The system time is in the format of
158          * (year-2001)*12*32 + month*32 + day. */
159 #define DRV_PULSE_ALWAYS_ALIVE                          0x00008000
160         /* Indicate to the firmware not to go into the
161          * OS-absent when it is not getting driver pulse.
162          * This is used for debugging as well for PXE(MBA). */
163
164         u32 mcp_pulse_mb;
165 #define MCP_PULSE_SEQ_MASK                              0x00007fff
166 #define MCP_PULSE_ALWAYS_ALIVE                          0x00008000
167         /* Indicates to the driver not to assert due to lack
168          * of MCP response */
169 #define MCP_EVENT_MASK                                  0xffff0000
170 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ                0x00010000
171
172 };
173
174
175 /****************************************************************************
176  * Shared HW configuration                                                  *
177  ****************************************************************************/
178 struct shared_hw_cfg {                                   /* NVRAM Offset */
179         /* Up to 16 bytes of NULL-terminated string */
180         u8  part_num[16];                                       /* 0x104 */
181
182         u32 config;                                             /* 0x114 */
183 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
184 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT            0
185 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V             0x00000000
186 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V             0x00000001
187 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
188
189 #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
190
191 #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
192
193 #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
194 #define SHARED_HW_CFG_MFW_SELECT_SHIFT              8
195         /* Whatever MFW found in NVM
196            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
197 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT            0x00000000
198 #define SHARED_HW_CFG_MFW_SELECT_NC_SI              0x00000100
199 #define SHARED_HW_CFG_MFW_SELECT_UMP                0x00000200
200 #define SHARED_HW_CFG_MFW_SELECT_IPMI               0x00000300
201         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
202           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
203 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
204         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
205           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
206 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
207         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
208           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
209 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
210
211 #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
212 #define SHARED_HW_CFG_LED_MODE_SHIFT                16
213 #define SHARED_HW_CFG_LED_MAC1                      0x00000000
214 #define SHARED_HW_CFG_LED_PHY1                      0x00010000
215 #define SHARED_HW_CFG_LED_PHY2                      0x00020000
216 #define SHARED_HW_CFG_LED_PHY3                      0x00030000
217 #define SHARED_HW_CFG_LED_MAC2                      0x00040000
218 #define SHARED_HW_CFG_LED_PHY4                      0x00050000
219 #define SHARED_HW_CFG_LED_PHY5                      0x00060000
220 #define SHARED_HW_CFG_LED_PHY6                      0x00070000
221 #define SHARED_HW_CFG_LED_MAC3                      0x00080000
222 #define SHARED_HW_CFG_LED_PHY7                      0x00090000
223 #define SHARED_HW_CFG_LED_PHY9                      0x000a0000
224 #define SHARED_HW_CFG_LED_PHY11                     0x000b0000
225 #define SHARED_HW_CFG_LED_MAC4                      0x000c0000
226 #define SHARED_HW_CFG_LED_PHY8                      0x000d0000
227
228 #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
229 #define SHARED_HW_CFG_AN_ENABLE_SHIFT               24
230 #define SHARED_HW_CFG_AN_ENABLE_CL37                0x01000000
231 #define SHARED_HW_CFG_AN_ENABLE_CL73                0x02000000
232 #define SHARED_HW_CFG_AN_ENABLE_BAM                 0x04000000
233 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
234 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
235 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY          0x20000000
236
237         u32 config2;                                            /* 0x118 */
238         /* one time auto detect grace period (in sec) */
239 #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
240 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT            0
241
242 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
243
244         /* The default value for the core clock is 250MHz and it is
245            achieved by setting the clock change to 4 */
246 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
247 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT            9
248
249 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ           0x00000000
250 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ           0x00001000
251
252 #define SHARED_HW_CFG_HIDE_FUNC1                    0x00002000
253
254         u32 power_dissipated;                                   /* 0x11c */
255 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
256 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT           24
257
258 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
259 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT        16
260 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE      0x00000000
261 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT         0x00010000
262 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT        0x00020000
263 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT       0x00030000
264
265         u32 ump_nc_si_config;                                   /* 0x120 */
266 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
267 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT      0
268 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC        0x00000000
269 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY        0x00000001
270 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII        0x00000000
271 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII       0x00000002
272
273 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
274 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT      8
275
276 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
277 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
278 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
279 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
280
281         u32 board;                                              /* 0x124 */
282 #define SHARED_HW_CFG_BOARD_TYPE_MASK               0x0000ffff
283 #define SHARED_HW_CFG_BOARD_TYPE_SHIFT              0
284 #define SHARED_HW_CFG_BOARD_TYPE_NONE               0x00000000
285 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000     0x00000001
286 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001     0x00000002
287 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G    0x00000003
288 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G    0x00000004
289 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G    0x00000005
290 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G    0x00000006
291 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G    0x00000007
292 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G    0x00000008
293
294 #define SHARED_HW_CFG_BOARD_VER_MASK                0xffff0000
295 #define SHARED_HW_CFG_BOARD_VER_SHIFT               16
296 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0xf0000000
297 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT         28
298 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0x0f000000
299 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT         24
300 #define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000
301 #define SHARED_HW_CFG_BOARD_REV_SHIFT               16
302
303         u32 reserved;                                           /* 0x128 */
304
305 };
306
307 /****************************************************************************
308  * Port HW configuration                                                    *
309  ****************************************************************************/
310 struct port_hw_cfg {    /* function 0: 0x12c-0x2bb, function 1: 0x2bc-0x44b */
311
312         /* Fields below are port specific (in anticipation of dual port
313            devices */
314         u32 pci_id;
315 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
316 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
317
318         u32 pci_sub_id;
319 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
320 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
321
322         u32 power_dissipated;
323 #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
324 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT              24
325 #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
326 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT              16
327 #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
328 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT              8
329 #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
330 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT              0
331
332         u32 power_consumed;
333 #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
334 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT             24
335 #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
336 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT             16
337 #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
338 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT             8
339 #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
340 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT             0
341
342         u32 mac_upper;
343 #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
344 #define PORT_HW_CFG_UPPERMAC_SHIFT                  0
345         u32 mac_lower;
346
347         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
348         u32 iscsi_mac_lower;
349
350         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
351         u32 rdma_mac_lower;
352
353         u32 serdes_config;
354         /* for external PHY, or forced mode or during AN */
355 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
356 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT  16
357
358 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0x0000ffff
359 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT   0
360
361         u16 serdes_tx_driver_pre_emphasis[16];
362         u16 serdes_rx_driver_equalizer[16];
363
364         u32 xgxs_config_lane0;
365         u32 xgxs_config_lane1;
366         u32 xgxs_config_lane2;
367         u32 xgxs_config_lane3;
368         /* for external PHY, or forced mode or during AN */
369 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK   0xffff0000
370 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT  16
371
372 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK      0x0000ffff
373 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT     0
374
375         u16 xgxs_tx_driver_pre_emphasis_lane0[16];
376         u16 xgxs_tx_driver_pre_emphasis_lane1[16];
377         u16 xgxs_tx_driver_pre_emphasis_lane2[16];
378         u16 xgxs_tx_driver_pre_emphasis_lane3[16];
379
380         u16 xgxs_rx_driver_equalizer_lane0[16];
381         u16 xgxs_rx_driver_equalizer_lane1[16];
382         u16 xgxs_rx_driver_equalizer_lane2[16];
383         u16 xgxs_rx_driver_equalizer_lane3[16];
384
385         u32 lane_config;
386 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
387 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT             0
388 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
389 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT          0
390 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
391 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT          8
392 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
393 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT      14
394         /* AN and forced */
395 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123          0x00001b1b
396         /* forced only */
397 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210          0x00001be4
398         /* forced only */
399 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120          0x0000d8d8
400         /* forced only */
401 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210          0x0000e4e4
402
403         u32 external_phy_config;
404 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
405 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT       24
406 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT      0x00000000
407 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
408 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
409
410 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
411 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT       16
412
413 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
414 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT         8
415 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT        0x00000000
416 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071       0x00000100
417 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072       0x00000200
418 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073       0x00000300
419 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705       0x00000400
420 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706       0x00000500
421 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276       0x00000600
422 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481       0x00000700
423 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN      0x0000ff00
424
425 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
426 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT         0
427
428         u32 speed_capability_mask;
429 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
430 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT       16
431 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
432 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
433 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
434 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
435 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G          0x00100000
436 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G        0x00200000
437 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G         0x00400000
438 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G         0x00800000
439 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G       0x01000000
440 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G         0x02000000
441 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G         0x04000000
442 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G         0x08000000
443 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
444
445 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
446 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT       0
447 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
448 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
449 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
450 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
451 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G          0x00000010
452 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G        0x00000020
453 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G         0x00000040
454 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G         0x00000080
455 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G       0x00000100
456 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G         0x00000200
457 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G         0x00000400
458 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G         0x00000800
459 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
460
461         u32 reserved[2];
462
463 };
464
465 /****************************************************************************
466  * Shared Feature configuration                                             *
467  ****************************************************************************/
468 struct shared_feat_cfg {                                 /* NVRAM Offset */
469         u32 bmc_common;                                         /* 0x450 */
470 #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
471
472 };
473
474
475 /****************************************************************************
476  * Port Feature configuration                                               *
477  ****************************************************************************/
478 struct port_feat_cfg {  /* function 0: 0x454-0x4c7, function 1: 0x4c8-0x53b */
479         u32 config;
480 #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
481 #define PORT_FEATURE_BAR1_SIZE_SHIFT                0
482 #define PORT_FEATURE_BAR1_SIZE_DISABLED             0x00000000
483 #define PORT_FEATURE_BAR1_SIZE_64K                  0x00000001
484 #define PORT_FEATURE_BAR1_SIZE_128K                 0x00000002
485 #define PORT_FEATURE_BAR1_SIZE_256K                 0x00000003
486 #define PORT_FEATURE_BAR1_SIZE_512K                 0x00000004
487 #define PORT_FEATURE_BAR1_SIZE_1M                   0x00000005
488 #define PORT_FEATURE_BAR1_SIZE_2M                   0x00000006
489 #define PORT_FEATURE_BAR1_SIZE_4M                   0x00000007
490 #define PORT_FEATURE_BAR1_SIZE_8M                   0x00000008
491 #define PORT_FEATURE_BAR1_SIZE_16M                  0x00000009
492 #define PORT_FEATURE_BAR1_SIZE_32M                  0x0000000a
493 #define PORT_FEATURE_BAR1_SIZE_64M                  0x0000000b
494 #define PORT_FEATURE_BAR1_SIZE_128M                 0x0000000c
495 #define PORT_FEATURE_BAR1_SIZE_256M                 0x0000000d
496 #define PORT_FEATURE_BAR1_SIZE_512M                 0x0000000e
497 #define PORT_FEATURE_BAR1_SIZE_1G                   0x0000000f
498 #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
499 #define PORT_FEATURE_BAR2_SIZE_SHIFT                4
500 #define PORT_FEATURE_BAR2_SIZE_DISABLED             0x00000000
501 #define PORT_FEATURE_BAR2_SIZE_64K                  0x00000010
502 #define PORT_FEATURE_BAR2_SIZE_128K                 0x00000020
503 #define PORT_FEATURE_BAR2_SIZE_256K                 0x00000030
504 #define PORT_FEATURE_BAR2_SIZE_512K                 0x00000040
505 #define PORT_FEATURE_BAR2_SIZE_1M                   0x00000050
506 #define PORT_FEATURE_BAR2_SIZE_2M                   0x00000060
507 #define PORT_FEATURE_BAR2_SIZE_4M                   0x00000070
508 #define PORT_FEATURE_BAR2_SIZE_8M                   0x00000080
509 #define PORT_FEATURE_BAR2_SIZE_16M                  0x00000090
510 #define PORT_FEATURE_BAR2_SIZE_32M                  0x000000a0
511 #define PORT_FEATURE_BAR2_SIZE_64M                  0x000000b0
512 #define PORT_FEATURE_BAR2_SIZE_128M                 0x000000c0
513 #define PORT_FEATURE_BAR2_SIZE_256M                 0x000000d0
514 #define PORT_FEATURE_BAR2_SIZE_512M                 0x000000e0
515 #define PORT_FEATURE_BAR2_SIZE_1G                   0x000000f0
516 #define PORT_FEATURE_EN_SIZE_MASK                   0x07000000
517 #define PORT_FEATURE_EN_SIZE_SHIFT                  24
518 #define PORT_FEATURE_WOL_ENABLED                    0x01000000
519 #define PORT_FEATURE_MBA_ENABLED                    0x02000000
520 #define PORT_FEATURE_MFW_ENABLED                    0x04000000
521
522         u32 wol_config;
523         /* Default is used when driver sets to "auto" mode */
524 #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
525 #define PORT_FEATURE_WOL_DEFAULT_SHIFT              0
526 #define PORT_FEATURE_WOL_DEFAULT_DISABLE            0x00000000
527 #define PORT_FEATURE_WOL_DEFAULT_MAGIC              0x00000001
528 #define PORT_FEATURE_WOL_DEFAULT_ACPI               0x00000002
529 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
530 #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
531 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
532 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
533
534         u32 mba_config;
535 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000003
536 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT      0
537 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0x00000000
538 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        0x00000001
539 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      0x00000002
540 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
541 #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
542 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
543 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
544 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S              0x00000000
545 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B              0x00000800
546 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
547 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT         12
548 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0x00000000
549 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K            0x00001000
550 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K            0x00002000
551 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K            0x00003000
552 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K           0x00004000
553 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K           0x00005000
554 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K           0x00006000
555 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K          0x00007000
556 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K          0x00008000
557 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K          0x00009000
558 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M            0x0000a000
559 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M            0x0000b000
560 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M            0x0000c000
561 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M            0x0000d000
562 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M           0x0000e000
563 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M           0x0000f000
564 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
565 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT          20
566 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
567 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT       24
568 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0x00000000
569 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x01000000
570 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x02000000
571 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x03000000
572 #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
573 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT           26
574 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO            0x00000000
575 #define PORT_FEATURE_MBA_LINK_SPEED_10HD            0x04000000
576 #define PORT_FEATURE_MBA_LINK_SPEED_10FD            0x08000000
577 #define PORT_FEATURE_MBA_LINK_SPEED_100HD           0x0c000000
578 #define PORT_FEATURE_MBA_LINK_SPEED_100FD           0x10000000
579 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS           0x14000000
580 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS         0x18000000
581 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4      0x1c000000
582 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4      0x20000000
583 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR       0x24000000
584 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS          0x28000000
585 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS        0x2c000000
586 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS          0x30000000
587 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS          0x34000000
588 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS          0x38000000
589
590         u32 bmc_config;
591 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT      0x00000000
592 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN           0x00000001
593
594         u32 mba_vlan_cfg;
595 #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
596 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT             0
597 #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
598
599         u32 resource_cfg;
600 #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
601 #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
602 #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
603 #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
604 #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
605
606         u32 smbus_config;
607         /* Obsolete */
608 #define PORT_FEATURE_SMBUS_EN                       0x00000001
609 #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
610 #define PORT_FEATURE_SMBUS_ADDR_SHIFT               1
611
612         u32 iscsib_boot_cfg;
613 #define PORT_FEATURE_ISCSIB_SKIP_TARGET_BOOT        0x00000001
614
615         u32 link_config;    /* Used as HW defaults for the driver */
616 #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
617 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT         24
618         /* (forced) low speed switch (< 10G) */
619 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH           0x00000000
620         /* (forced) high speed switch (>= 10G) */
621 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH          0x01000000
622 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT         0x02000000
623 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
624
625 #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
626 #define PORT_FEATURE_LINK_SPEED_SHIFT               16
627 #define PORT_FEATURE_LINK_SPEED_AUTO                0x00000000
628 #define PORT_FEATURE_LINK_SPEED_10M_FULL            0x00010000
629 #define PORT_FEATURE_LINK_SPEED_10M_HALF            0x00020000
630 #define PORT_FEATURE_LINK_SPEED_100M_HALF           0x00030000
631 #define PORT_FEATURE_LINK_SPEED_100M_FULL           0x00040000
632 #define PORT_FEATURE_LINK_SPEED_1G                  0x00050000
633 #define PORT_FEATURE_LINK_SPEED_2_5G                0x00060000
634 #define PORT_FEATURE_LINK_SPEED_10G_CX4             0x00070000
635 #define PORT_FEATURE_LINK_SPEED_10G_KX4             0x00080000
636 #define PORT_FEATURE_LINK_SPEED_10G_KR              0x00090000
637 #define PORT_FEATURE_LINK_SPEED_12G                 0x000a0000
638 #define PORT_FEATURE_LINK_SPEED_12_5G               0x000b0000
639 #define PORT_FEATURE_LINK_SPEED_13G                 0x000c0000
640 #define PORT_FEATURE_LINK_SPEED_15G                 0x000d0000
641 #define PORT_FEATURE_LINK_SPEED_16G                 0x000e0000
642
643 #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
644 #define PORT_FEATURE_FLOW_CONTROL_SHIFT             8
645 #define PORT_FEATURE_FLOW_CONTROL_AUTO              0x00000000
646 #define PORT_FEATURE_FLOW_CONTROL_TX                0x00000100
647 #define PORT_FEATURE_FLOW_CONTROL_RX                0x00000200
648 #define PORT_FEATURE_FLOW_CONTROL_BOTH              0x00000300
649 #define PORT_FEATURE_FLOW_CONTROL_NONE              0x00000400
650
651         /* The default for MCP link configuration,
652            uses the same defines as link_config */
653         u32 mfw_wol_link_cfg;
654
655         u32 reserved[19];
656
657 };
658
659
660 /****************************************************************************
661  * Device Information                                                       *
662  ****************************************************************************/
663 struct dev_info {                                                   /* size */
664
665         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
666
667         struct shared_hw_cfg     shared_hw_config;                    /* 40 */
668
669         struct port_hw_cfg       port_hw_config[FUNC_MAX];     /* 400*2=800 */
670
671         struct shared_feat_cfg   shared_feature_config;                /* 4 */
672
673         struct port_feat_cfg     port_feature_config[FUNC_MAX];/* 116*2=232 */
674
675 };
676
677
678 /****************************************************************************
679  * Management firmware state                                                *
680  ****************************************************************************/
681 /* Allocate 320 bytes for management firmware: still not known exactly
682  * how much IMD needs. */
683 #define MGMTFW_STATE_WORD_SIZE                              80
684
685 struct mgmtfw_state {
686         u32 opaque[MGMTFW_STATE_WORD_SIZE];
687 };
688
689
690 /****************************************************************************
691  * Shared Memory Region                                                     *
692  ****************************************************************************/
693 struct shmem_region {                          /*   SharedMem Offset (size) */
694         u32                 validity_map[FUNC_MAX];    /* 0x0 (4 * 2 = 0x8) */
695 #define SHR_MEM_VALIDITY_PCI_CFG                    0x00000001
696 #define SHR_MEM_VALIDITY_MB                         0x00000002
697 #define SHR_MEM_VALIDITY_DEV_INFO                   0x00000004
698         /* One licensing bit should be set */
699 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
700 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
701 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
702 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
703
704         struct drv_fw_mb    drv_fw_mb[FUNC_MAX];     /* 0x8 (28 * 2 = 0x38) */
705
706         struct dev_info     dev_info;                       /* 0x40 (0x438) */
707
708 #ifdef _LICENSE_H
709         license_key_t       drv_lic_key[FUNC_MAX]; /* 0x478 (52 * 2 = 0x68) */
710 #else /* Linux! */
711         u8                  reserved[52*FUNC_MAX];
712 #endif
713
714         /* FW information (for internal FW use) */
715         u32                 fw_info_fio_offset;            /* 0x4e0 (0x4)   */
716         struct mgmtfw_state mgmtfw_state;                  /* 0x4e4 (0x140) */
717
718 };                                                         /* 0x624 */
719
720
721 #define BCM_5710_FW_MAJOR_VERSION                       4
722 #define BCM_5710_FW_MINOR_VERSION                       0
723 #define BCM_5710_FW_REVISION_VERSION                    14
724 #define BCM_5710_FW_COMPILE_FLAGS                       1
725
726
727 /*
728  * attention bits
729  */
730 struct atten_def_status_block {
731         u32 attn_bits;
732         u32 attn_bits_ack;
733 #if defined(__BIG_ENDIAN)
734         u16 attn_bits_index;
735         u8 reserved0;
736         u8 status_block_id;
737 #elif defined(__LITTLE_ENDIAN)
738         u8 status_block_id;
739         u8 reserved0;
740         u16 attn_bits_index;
741 #endif
742         u32 reserved1;
743 };
744
745
746 /*
747  * common data for all protocols
748  */
749 struct doorbell_hdr {
750         u8 header;
751 #define DOORBELL_HDR_RX (0x1<<0)
752 #define DOORBELL_HDR_RX_SHIFT 0
753 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
754 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
755 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
756 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
757 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
758 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
759 };
760
761 /*
762  * doorbell message send to the chip
763  */
764 struct doorbell {
765 #if defined(__BIG_ENDIAN)
766         u16 zero_fill2;
767         u8 zero_fill1;
768         struct doorbell_hdr header;
769 #elif defined(__LITTLE_ENDIAN)
770         struct doorbell_hdr header;
771         u8 zero_fill1;
772         u16 zero_fill2;
773 #endif
774 };
775
776
777 /*
778  * IGU driver acknowlegement register
779  */
780 struct igu_ack_register {
781 #if defined(__BIG_ENDIAN)
782         u16 sb_id_and_flags;
783 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
784 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
785 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
786 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
787 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
788 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
789 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
790 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
791 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
792 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
793         u16 status_block_index;
794 #elif defined(__LITTLE_ENDIAN)
795         u16 status_block_index;
796         u16 sb_id_and_flags;
797 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
798 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
799 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
800 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
801 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
802 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
803 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
804 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
805 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
806 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
807 #endif
808 };
809
810
811 /*
812  * Parser parsing flags field
813  */
814 struct parsing_flags {
815         u16 flags;
816 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
817 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
818 #define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1)
819 #define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS_SHIFT 1
820 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
821 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
822 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
823 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
824 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
825 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
826 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
827 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
828 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
829 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
830 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
831 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
832 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
833 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
834 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
835 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
836 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
837 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
838 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
839 #define PARSING_FLAGS_RESERVED0_SHIFT 14
840 };
841
842
843 /*
844  * dmae command structure
845  */
846 struct dmae_command {
847         u32 opcode;
848 #define DMAE_COMMAND_SRC (0x1<<0)
849 #define DMAE_COMMAND_SRC_SHIFT 0
850 #define DMAE_COMMAND_DST (0x3<<1)
851 #define DMAE_COMMAND_DST_SHIFT 1
852 #define DMAE_COMMAND_C_DST (0x1<<3)
853 #define DMAE_COMMAND_C_DST_SHIFT 3
854 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
855 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
856 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
857 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
858 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
859 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
860 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
861 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
862 #define DMAE_COMMAND_PORT (0x1<<11)
863 #define DMAE_COMMAND_PORT_SHIFT 11
864 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
865 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
866 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
867 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
868 #define DMAE_COMMAND_DST_RESET (0x1<<14)
869 #define DMAE_COMMAND_DST_RESET_SHIFT 14
870 #define DMAE_COMMAND_RESERVED0 (0x1FFFF<<15)
871 #define DMAE_COMMAND_RESERVED0_SHIFT 15
872         u32 src_addr_lo;
873         u32 src_addr_hi;
874         u32 dst_addr_lo;
875         u32 dst_addr_hi;
876 #if defined(__BIG_ENDIAN)
877         u16 reserved1;
878         u16 len;
879 #elif defined(__LITTLE_ENDIAN)
880         u16 len;
881         u16 reserved1;
882 #endif
883         u32 comp_addr_lo;
884         u32 comp_addr_hi;
885         u32 comp_val;
886         u32 crc32;
887         u32 crc32_c;
888 #if defined(__BIG_ENDIAN)
889         u16 crc16_c;
890         u16 crc16;
891 #elif defined(__LITTLE_ENDIAN)
892         u16 crc16;
893         u16 crc16_c;
894 #endif
895 #if defined(__BIG_ENDIAN)
896         u16 reserved2;
897         u16 crc_t10;
898 #elif defined(__LITTLE_ENDIAN)
899         u16 crc_t10;
900         u16 reserved2;
901 #endif
902 #if defined(__BIG_ENDIAN)
903         u16 xsum8;
904         u16 xsum16;
905 #elif defined(__LITTLE_ENDIAN)
906         u16 xsum16;
907         u16 xsum8;
908 #endif
909 };
910
911
912 struct double_regpair {
913         u32 regpair0_lo;
914         u32 regpair0_hi;
915         u32 regpair1_lo;
916         u32 regpair1_hi;
917 };
918
919
920 /*
921  * The eth Rx Buffer Descriptor
922  */
923 struct eth_rx_bd {
924         u32 addr_lo;
925         u32 addr_hi;
926 };
927
928 /*
929  * The eth storm context of Ustorm
930  */
931 struct ustorm_eth_st_context {
932 #if defined(__BIG_ENDIAN)
933         u8 sb_index_number;
934         u8 status_block_id;
935         u8 __local_rx_bd_cons;
936         u8 __local_rx_bd_prod;
937 #elif defined(__LITTLE_ENDIAN)
938         u8 __local_rx_bd_prod;
939         u8 __local_rx_bd_cons;
940         u8 status_block_id;
941         u8 sb_index_number;
942 #endif
943 #if defined(__BIG_ENDIAN)
944         u16 rcq_cons;
945         u16 rx_bd_cons;
946 #elif defined(__LITTLE_ENDIAN)
947         u16 rx_bd_cons;
948         u16 rcq_cons;
949 #endif
950         u32 rx_bd_page_base_lo;
951         u32 rx_bd_page_base_hi;
952         u32 rcq_base_address_lo;
953         u32 rcq_base_address_hi;
954 #if defined(__BIG_ENDIAN)
955         u16 __num_of_returned_cqes;
956         u8 num_rss;
957         u8 flags;
958 #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
959 #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
960 #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
961 #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
962 #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
963 #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
964 #define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
965 #define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
966 #elif defined(__LITTLE_ENDIAN)
967         u8 flags;
968 #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
969 #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
970 #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
971 #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
972 #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
973 #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
974 #define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
975 #define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
976         u8 num_rss;
977         u16 __num_of_returned_cqes;
978 #endif
979 #if defined(__BIG_ENDIAN)
980         u16 mc_alignment_size;
981         u16 agg_threshold;
982 #elif defined(__LITTLE_ENDIAN)
983         u16 agg_threshold;
984         u16 mc_alignment_size;
985 #endif
986         struct eth_rx_bd __local_bd_ring[16];
987 };
988
989 /*
990  * The eth storm context of Tstorm
991  */
992 struct tstorm_eth_st_context {
993         u32 __reserved0[28];
994 };
995
996 /*
997  * The eth aggregative context section of Xstorm
998  */
999 struct xstorm_eth_extra_ag_context_section {
1000 #if defined(__BIG_ENDIAN)
1001         u8 __tcp_agg_vars1;
1002         u8 __reserved50;
1003         u16 __mss;
1004 #elif defined(__LITTLE_ENDIAN)
1005         u16 __mss;
1006         u8 __reserved50;
1007         u8 __tcp_agg_vars1;
1008 #endif
1009         u32 __snd_nxt;
1010         u32 __tx_wnd;
1011         u32 __snd_una;
1012         u32 __reserved53;
1013 #if defined(__BIG_ENDIAN)
1014         u8 __agg_val8_th;
1015         u8 __agg_val8;
1016         u16 __tcp_agg_vars2;
1017 #elif defined(__LITTLE_ENDIAN)
1018         u16 __tcp_agg_vars2;
1019         u8 __agg_val8;
1020         u8 __agg_val8_th;
1021 #endif
1022         u32 __reserved58;
1023         u32 __reserved59;
1024         u32 __reserved60;
1025         u32 __reserved61;
1026 #if defined(__BIG_ENDIAN)
1027         u16 __agg_val7_th;
1028         u16 __agg_val7;
1029 #elif defined(__LITTLE_ENDIAN)
1030         u16 __agg_val7;
1031         u16 __agg_val7_th;
1032 #endif
1033 #if defined(__BIG_ENDIAN)
1034         u8 __tcp_agg_vars5;
1035         u8 __tcp_agg_vars4;
1036         u8 __tcp_agg_vars3;
1037         u8 __reserved62;
1038 #elif defined(__LITTLE_ENDIAN)
1039         u8 __reserved62;
1040         u8 __tcp_agg_vars3;
1041         u8 __tcp_agg_vars4;
1042         u8 __tcp_agg_vars5;
1043 #endif
1044         u32 __tcp_agg_vars6;
1045 #if defined(__BIG_ENDIAN)
1046         u16 __agg_misc6;
1047         u16 __tcp_agg_vars7;
1048 #elif defined(__LITTLE_ENDIAN)
1049         u16 __tcp_agg_vars7;
1050         u16 __agg_misc6;
1051 #endif
1052         u32 __agg_val10;
1053         u32 __agg_val10_th;
1054 #if defined(__BIG_ENDIAN)
1055         u16 __reserved3;
1056         u8 __reserved2;
1057         u8 __agg_misc7;
1058 #elif defined(__LITTLE_ENDIAN)
1059         u8 __agg_misc7;
1060         u8 __reserved2;
1061         u16 __reserved3;
1062 #endif
1063 };
1064
1065 /*
1066  * The eth aggregative context of Xstorm
1067  */
1068 struct xstorm_eth_ag_context {
1069 #if defined(__BIG_ENDIAN)
1070         u16 __bd_prod;
1071         u8 __agg_vars1;
1072         u8 __state;
1073 #elif defined(__LITTLE_ENDIAN)
1074         u8 __state;
1075         u8 __agg_vars1;
1076         u16 __bd_prod;
1077 #endif
1078 #if defined(__BIG_ENDIAN)
1079         u8 cdu_reserved;
1080         u8 __agg_vars4;
1081         u8 __agg_vars3;
1082         u8 __agg_vars2;
1083 #elif defined(__LITTLE_ENDIAN)
1084         u8 __agg_vars2;
1085         u8 __agg_vars3;
1086         u8 __agg_vars4;
1087         u8 cdu_reserved;
1088 #endif
1089         u32 __more_packets_to_send;
1090 #if defined(__BIG_ENDIAN)
1091         u16 __agg_vars5;
1092         u16 __agg_val4_th;
1093 #elif defined(__LITTLE_ENDIAN)
1094         u16 __agg_val4_th;
1095         u16 __agg_vars5;
1096 #endif
1097         struct xstorm_eth_extra_ag_context_section __extra_section;
1098 #if defined(__BIG_ENDIAN)
1099         u16 __agg_vars7;
1100         u8 __agg_val3_th;
1101         u8 __agg_vars6;
1102 #elif defined(__LITTLE_ENDIAN)
1103         u8 __agg_vars6;
1104         u8 __agg_val3_th;
1105         u16 __agg_vars7;
1106 #endif
1107 #if defined(__BIG_ENDIAN)
1108         u16 __agg_val11_th;
1109         u16 __agg_val11;
1110 #elif defined(__LITTLE_ENDIAN)
1111         u16 __agg_val11;
1112         u16 __agg_val11_th;
1113 #endif
1114 #if defined(__BIG_ENDIAN)
1115         u8 __reserved1;
1116         u8 __agg_val6_th;
1117         u16 __agg_val9;
1118 #elif defined(__LITTLE_ENDIAN)
1119         u16 __agg_val9;
1120         u8 __agg_val6_th;
1121         u8 __reserved1;
1122 #endif
1123 #if defined(__BIG_ENDIAN)
1124         u16 __agg_val2_th;
1125         u16 __agg_val2;
1126 #elif defined(__LITTLE_ENDIAN)
1127         u16 __agg_val2;
1128         u16 __agg_val2_th;
1129 #endif
1130         u32 __agg_vars8;
1131 #if defined(__BIG_ENDIAN)
1132         u16 __agg_misc0;
1133         u16 __agg_val4;
1134 #elif defined(__LITTLE_ENDIAN)
1135         u16 __agg_val4;
1136         u16 __agg_misc0;
1137 #endif
1138 #if defined(__BIG_ENDIAN)
1139         u8 __agg_val3;
1140         u8 __agg_val6;
1141         u8 __agg_val5_th;
1142         u8 __agg_val5;
1143 #elif defined(__LITTLE_ENDIAN)
1144         u8 __agg_val5;
1145         u8 __agg_val5_th;
1146         u8 __agg_val6;
1147         u8 __agg_val3;
1148 #endif
1149 #if defined(__BIG_ENDIAN)
1150         u16 __agg_misc1;
1151         u16 __bd_ind_max_val;
1152 #elif defined(__LITTLE_ENDIAN)
1153         u16 __bd_ind_max_val;
1154         u16 __agg_misc1;
1155 #endif
1156         u32 __reserved57;
1157         u32 __agg_misc4;
1158         u32 __agg_misc5;
1159 };
1160
1161 /*
1162  * The eth aggregative context section of Tstorm
1163  */
1164 struct tstorm_eth_extra_ag_context_section {
1165         u32 __agg_val1;
1166 #if defined(__BIG_ENDIAN)
1167         u8 __tcp_agg_vars2;
1168         u8 __agg_val3;
1169         u16 __agg_val2;
1170 #elif defined(__LITTLE_ENDIAN)
1171         u16 __agg_val2;
1172         u8 __agg_val3;
1173         u8 __tcp_agg_vars2;
1174 #endif
1175 #if defined(__BIG_ENDIAN)
1176         u16 __agg_val5;
1177         u8 __agg_val6;
1178         u8 __tcp_agg_vars3;
1179 #elif defined(__LITTLE_ENDIAN)
1180         u8 __tcp_agg_vars3;
1181         u8 __agg_val6;
1182         u16 __agg_val5;
1183 #endif
1184         u32 __reserved63;
1185         u32 __reserved64;
1186         u32 __reserved65;
1187         u32 __reserved66;
1188         u32 __reserved67;
1189         u32 __tcp_agg_vars1;
1190         u32 __reserved61;
1191         u32 __reserved62;
1192         u32 __reserved2;
1193 };
1194
1195 /*
1196  * The eth aggregative context of Tstorm
1197  */
1198 struct tstorm_eth_ag_context {
1199 #if defined(__BIG_ENDIAN)
1200         u16 __reserved54;
1201         u8 __agg_vars1;
1202         u8 __state;
1203 #elif defined(__LITTLE_ENDIAN)
1204         u8 __state;
1205         u8 __agg_vars1;
1206         u16 __reserved54;
1207 #endif
1208 #if defined(__BIG_ENDIAN)
1209         u16 __agg_val4;
1210         u16 __agg_vars2;
1211 #elif defined(__LITTLE_ENDIAN)
1212         u16 __agg_vars2;
1213         u16 __agg_val4;
1214 #endif
1215         struct tstorm_eth_extra_ag_context_section __extra_section;
1216 };
1217
1218 /*
1219  * The eth aggregative context of Cstorm
1220  */
1221 struct cstorm_eth_ag_context {
1222         u32 __agg_vars1;
1223 #if defined(__BIG_ENDIAN)
1224         u8 __aux1_th;
1225         u8 __aux1_val;
1226         u16 __agg_vars2;
1227 #elif defined(__LITTLE_ENDIAN)
1228         u16 __agg_vars2;
1229         u8 __aux1_val;
1230         u8 __aux1_th;
1231 #endif
1232         u32 __num_of_treated_packet;
1233         u32 __last_packet_treated;
1234 #if defined(__BIG_ENDIAN)
1235         u16 __reserved58;
1236         u16 __reserved57;
1237 #elif defined(__LITTLE_ENDIAN)
1238         u16 __reserved57;
1239         u16 __reserved58;
1240 #endif
1241 #if defined(__BIG_ENDIAN)
1242         u8 __reserved62;
1243         u8 __reserved61;
1244         u8 __reserved60;
1245         u8 __reserved59;
1246 #elif defined(__LITTLE_ENDIAN)
1247         u8 __reserved59;
1248         u8 __reserved60;
1249         u8 __reserved61;
1250         u8 __reserved62;
1251 #endif
1252 #if defined(__BIG_ENDIAN)
1253         u16 __reserved64;
1254         u16 __reserved63;
1255 #elif defined(__LITTLE_ENDIAN)
1256         u16 __reserved63;
1257         u16 __reserved64;
1258 #endif
1259         u32 __reserved65;
1260 #if defined(__BIG_ENDIAN)
1261         u16 __agg_vars3;
1262         u16 __rq_inv_cnt;
1263 #elif defined(__LITTLE_ENDIAN)
1264         u16 __rq_inv_cnt;
1265         u16 __agg_vars3;
1266 #endif
1267 #if defined(__BIG_ENDIAN)
1268         u16 __packet_index_th;
1269         u16 __packet_index;
1270 #elif defined(__LITTLE_ENDIAN)
1271         u16 __packet_index;
1272         u16 __packet_index_th;
1273 #endif
1274 };
1275
1276 /*
1277  * The eth aggregative context of Ustorm
1278  */
1279 struct ustorm_eth_ag_context {
1280 #if defined(__BIG_ENDIAN)
1281         u8 __aux_counter_flags;
1282         u8 __agg_vars2;
1283         u8 __agg_vars1;
1284         u8 __state;
1285 #elif defined(__LITTLE_ENDIAN)
1286         u8 __state;
1287         u8 __agg_vars1;
1288         u8 __agg_vars2;
1289         u8 __aux_counter_flags;
1290 #endif
1291 #if defined(__BIG_ENDIAN)
1292         u8 cdu_usage;
1293         u8 __agg_misc2;
1294         u16 __agg_misc1;
1295 #elif defined(__LITTLE_ENDIAN)
1296         u16 __agg_misc1;
1297         u8 __agg_misc2;
1298         u8 cdu_usage;
1299 #endif
1300         u32 __agg_misc4;
1301 #if defined(__BIG_ENDIAN)
1302         u8 __agg_val3_th;
1303         u8 __agg_val3;
1304         u16 __agg_misc3;
1305 #elif defined(__LITTLE_ENDIAN)
1306         u16 __agg_misc3;
1307         u8 __agg_val3;
1308         u8 __agg_val3_th;
1309 #endif
1310         u32 __agg_val1;
1311         u32 __agg_misc4_th;
1312 #if defined(__BIG_ENDIAN)
1313         u16 __agg_val2_th;
1314         u16 __agg_val2;
1315 #elif defined(__LITTLE_ENDIAN)
1316         u16 __agg_val2;
1317         u16 __agg_val2_th;
1318 #endif
1319 #if defined(__BIG_ENDIAN)
1320         u16 __reserved2;
1321         u8 __decision_rules;
1322         u8 __decision_rule_enable_bits;
1323 #elif defined(__LITTLE_ENDIAN)
1324         u8 __decision_rule_enable_bits;
1325         u8 __decision_rules;
1326         u16 __reserved2;
1327 #endif
1328 };
1329
1330 /*
1331  * Timers connection context
1332  */
1333 struct timers_block_context {
1334         u32 __reserved_0;
1335         u32 __reserved_1;
1336         u32 __reserved_2;
1337         u32 __reserved_flags;
1338 };
1339
1340 /*
1341  * structure for easy accessability to assembler
1342  */
1343 struct eth_tx_bd_flags {
1344         u8 as_bitfield;
1345 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1346 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1347 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1348 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1349 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1350 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1351 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1352 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1353 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1354 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1355 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1356 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1357 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1358 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1359 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1360 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1361 };
1362
1363 /*
1364  * The eth Tx Buffer Descriptor
1365  */
1366 struct eth_tx_bd {
1367         u32 addr_lo;
1368         u32 addr_hi;
1369         u16 nbd;
1370         u16 nbytes;
1371         u16 vlan;
1372         struct eth_tx_bd_flags bd_flags;
1373         u8 general_data;
1374 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1375 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1376 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1377 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1378 };
1379
1380 /*
1381  * Tx parsing BD structure for ETH,Relevant in START
1382  */
1383 struct eth_tx_parse_bd {
1384         u8 global_data;
1385 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1386 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1387 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1388 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1389 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1390 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1391 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1392 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1393 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1394 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1395         u8 tcp_flags;
1396 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1397 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1398 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1399 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1400 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1401 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1402 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1403 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1404 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1405 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1406 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1407 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1408 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1409 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1410 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1411 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1412         u8 ip_hlen;
1413         s8 cs_offset;
1414         u16 total_hlen;
1415         u16 lso_mss;
1416         u16 tcp_pseudo_csum;
1417         u16 ip_id;
1418         u32 tcp_send_seq;
1419 };
1420
1421 /*
1422  * The last BD in the BD memory will hold a pointer to the next BD memory
1423  */
1424 struct eth_tx_next_bd {
1425         u32 addr_lo;
1426         u32 addr_hi;
1427         u8 reserved[8];
1428 };
1429
1430 /*
1431  * union for 3 Bd types
1432  */
1433 union eth_tx_bd_types {
1434         struct eth_tx_bd reg_bd;
1435         struct eth_tx_parse_bd parse_bd;
1436         struct eth_tx_next_bd next_bd;
1437 };
1438
1439 /*
1440  * The eth storm context of Xstorm
1441  */
1442 struct xstorm_eth_st_context {
1443         u32 tx_bd_page_base_lo;
1444         u32 tx_bd_page_base_hi;
1445 #if defined(__BIG_ENDIAN)
1446         u16 tx_bd_cons;
1447         u8 __reserved0;
1448         u8 __local_tx_bd_prod;
1449 #elif defined(__LITTLE_ENDIAN)
1450         u8 __local_tx_bd_prod;
1451         u8 __reserved0;
1452         u16 tx_bd_cons;
1453 #endif
1454         u32 db_data_addr_lo;
1455         u32 db_data_addr_hi;
1456         u32 __pkt_cons;
1457         u32 __gso_next;
1458         u32 is_eth_conn_1b;
1459         union eth_tx_bd_types __bds[13];
1460 };
1461
1462 /*
1463  * The eth storm context of Cstorm
1464  */
1465 struct cstorm_eth_st_context {
1466 #if defined(__BIG_ENDIAN)
1467         u16 __reserved0;
1468         u8 sb_index_number;
1469         u8 status_block_id;
1470 #elif defined(__LITTLE_ENDIAN)
1471         u8 status_block_id;
1472         u8 sb_index_number;
1473         u16 __reserved0;
1474 #endif
1475         u32 __reserved1[3];
1476 };
1477
1478 /*
1479  * Ethernet connection context
1480  */
1481 struct eth_context {
1482         struct ustorm_eth_st_context ustorm_st_context;
1483         struct tstorm_eth_st_context tstorm_st_context;
1484         struct xstorm_eth_ag_context xstorm_ag_context;
1485         struct tstorm_eth_ag_context tstorm_ag_context;
1486         struct cstorm_eth_ag_context cstorm_ag_context;
1487         struct ustorm_eth_ag_context ustorm_ag_context;
1488         struct timers_block_context timers_context;
1489         struct xstorm_eth_st_context xstorm_st_context;
1490         struct cstorm_eth_st_context cstorm_st_context;
1491 };
1492
1493
1494 /*
1495  * ethernet doorbell
1496  */
1497 struct eth_tx_doorbell {
1498 #if defined(__BIG_ENDIAN)
1499         u16 npackets;
1500         u8 params;
1501 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
1502 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
1503 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
1504 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
1505 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
1506 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
1507         struct doorbell_hdr hdr;
1508 #elif defined(__LITTLE_ENDIAN)
1509         struct doorbell_hdr hdr;
1510         u8 params;
1511 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
1512 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
1513 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
1514 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
1515 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
1516 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
1517         u16 npackets;
1518 #endif
1519 };
1520
1521
1522 /*
1523  * ustorm status block
1524  */
1525 struct ustorm_def_status_block {
1526         u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
1527         u16 status_block_index;
1528         u8 reserved0;
1529         u8 status_block_id;
1530         u32 __flags;
1531 };
1532
1533 /*
1534  * cstorm status block
1535  */
1536 struct cstorm_def_status_block {
1537         u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
1538         u16 status_block_index;
1539         u8 reserved0;
1540         u8 status_block_id;
1541         u32 __flags;
1542 };
1543
1544 /*
1545  * xstorm status block
1546  */
1547 struct xstorm_def_status_block {
1548         u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
1549         u16 status_block_index;
1550         u8 reserved0;
1551         u8 status_block_id;
1552         u32 __flags;
1553 };
1554
1555 /*
1556  * tstorm status block
1557  */
1558 struct tstorm_def_status_block {
1559         u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
1560         u16 status_block_index;
1561         u8 reserved0;
1562         u8 status_block_id;
1563         u32 __flags;
1564 };
1565
1566 /*
1567  * host status block
1568  */
1569 struct host_def_status_block {
1570         struct atten_def_status_block atten_status_block;
1571         struct ustorm_def_status_block u_def_status_block;
1572         struct cstorm_def_status_block c_def_status_block;
1573         struct xstorm_def_status_block x_def_status_block;
1574         struct tstorm_def_status_block t_def_status_block;
1575 };
1576
1577
1578 /*
1579  * ustorm status block
1580  */
1581 struct ustorm_status_block {
1582         u16 index_values[HC_USTORM_SB_NUM_INDICES];
1583         u16 status_block_index;
1584         u8 reserved0;
1585         u8 status_block_id;
1586         u32 __flags;
1587 };
1588
1589 /*
1590  * cstorm status block
1591  */
1592 struct cstorm_status_block {
1593         u16 index_values[HC_CSTORM_SB_NUM_INDICES];
1594         u16 status_block_index;
1595         u8 reserved0;
1596         u8 status_block_id;
1597         u32 __flags;
1598 };
1599
1600 /*
1601  * host status block
1602  */
1603 struct host_status_block {
1604         struct ustorm_status_block u_status_block;
1605         struct cstorm_status_block c_status_block;
1606 };
1607
1608
1609 /*
1610  * The data for RSS setup ramrod
1611  */
1612 struct eth_client_setup_ramrod_data {
1613         u32 client_id_5b;
1614         u8 is_rdma_1b;
1615         u8 reserved0;
1616         u16 reserved1;
1617 };
1618
1619
1620 /*
1621  * L2 dynamic host coalescing init parameters
1622  */
1623 struct eth_dynamic_hc_config {
1624         u32 threshold[3];
1625         u8 hc_timeout[4];
1626 };
1627
1628
1629 /*
1630  * regular eth FP CQE parameters struct
1631  */
1632 struct eth_fast_path_rx_cqe {
1633         u8 type;
1634         u8 error_type_flags;
1635 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0)
1636 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0
1637 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1)
1638 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1
1639 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2)
1640 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2
1641 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<3)
1642 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 3
1643 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<4)
1644 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 4
1645 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x7<<5)
1646 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 5
1647         u8 status_flags;
1648 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
1649 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
1650 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
1651 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
1652 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
1653 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
1654 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
1655 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
1656 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
1657 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
1658 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
1659 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
1660         u8 placement_offset;
1661         u32 rss_hash_result;
1662         u16 vlan_tag;
1663         u16 pkt_len;
1664         u16 queue_index;
1665         struct parsing_flags pars_flags;
1666 };
1667
1668
1669 /*
1670  * The data for RSS setup ramrod
1671  */
1672 struct eth_halt_ramrod_data {
1673         u32 client_id_5b;
1674         u32 reserved0;
1675 };
1676
1677
1678 /*
1679  * Place holder for ramrods protocol specific data
1680  */
1681 struct ramrod_data {
1682         u32 data_lo;
1683         u32 data_hi;
1684 };
1685
1686 /*
1687  * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
1688  */
1689 union eth_ramrod_data {
1690         struct ramrod_data general;
1691 };
1692
1693
1694 /*
1695  * Rx Last BD in page (in ETH)
1696  */
1697 struct eth_rx_bd_next_page {
1698         u32 addr_lo;
1699         u32 addr_hi;
1700         u8 reserved[8];
1701 };
1702
1703
1704 /*
1705  * Eth Rx Cqe structure- general structure for ramrods
1706  */
1707 struct common_ramrod_eth_rx_cqe {
1708         u8 type;
1709         u8 conn_type_3b;
1710         u16 reserved;
1711         u32 conn_and_cmd_data;
1712 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
1713 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
1714 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
1715 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
1716         struct ramrod_data protocol_data;
1717 };
1718
1719 /*
1720  * Rx Last CQE in page (in ETH)
1721  */
1722 struct eth_rx_cqe_next_page {
1723         u32 addr_lo;
1724         u32 addr_hi;
1725         u32 reserved0;
1726         u32 reserved1;
1727 };
1728
1729 /*
1730  * union for all eth rx cqe types (fix their sizes)
1731  */
1732 union eth_rx_cqe {
1733         struct eth_fast_path_rx_cqe fast_path_cqe;
1734         struct common_ramrod_eth_rx_cqe ramrod_cqe;
1735         struct eth_rx_cqe_next_page next_page_cqe;
1736 };
1737
1738
1739 /*
1740  * common data for all protocols
1741  */
1742 struct spe_hdr {
1743         u32 conn_and_cmd_data;
1744 #define SPE_HDR_CID (0xFFFFFF<<0)
1745 #define SPE_HDR_CID_SHIFT 0
1746 #define SPE_HDR_CMD_ID (0xFF<<24)
1747 #define SPE_HDR_CMD_ID_SHIFT 24
1748         u16 type;
1749 #define SPE_HDR_CONN_TYPE (0xFF<<0)
1750 #define SPE_HDR_CONN_TYPE_SHIFT 0
1751 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
1752 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
1753         u16 reserved;
1754 };
1755
1756 struct regpair {
1757         u32 lo;
1758         u32 hi;
1759 };
1760
1761 /*
1762  * ethernet slow path element
1763  */
1764 union eth_specific_data {
1765         u8 protocol_data[8];
1766         struct regpair mac_config_addr;
1767         struct eth_client_setup_ramrod_data client_setup_ramrod_data;
1768         struct eth_halt_ramrod_data halt_ramrod_data;
1769         struct regpair leading_cqe_addr;
1770         struct regpair update_data_addr;
1771 };
1772
1773 /*
1774  * ethernet slow path element
1775  */
1776 struct eth_spe {
1777         struct spe_hdr hdr;
1778         union eth_specific_data data;
1779 };
1780
1781
1782 /*
1783  * doorbell data in host memory
1784  */
1785 struct eth_tx_db_data {
1786         u32 packets_prod;
1787         u16 bds_prod;
1788         u16 reserved;
1789 };
1790
1791
1792 /*
1793  * Common configuration parameters per port in Tstorm
1794  */
1795 struct tstorm_eth_function_common_config {
1796         u32 config_flags;
1797 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
1798 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
1799 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
1800 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
1801 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
1802 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
1803 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
1804 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
1805 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
1806 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
1807 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
1808 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
1809 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3FFFFFF<<6)
1810 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 6
1811 #if defined(__BIG_ENDIAN)
1812         u16 __secondary_vlan_id;
1813         u8 leading_client_id;
1814         u8 rss_result_mask;
1815 #elif defined(__LITTLE_ENDIAN)
1816         u8 rss_result_mask;
1817         u8 leading_client_id;
1818         u16 __secondary_vlan_id;
1819 #endif
1820 };
1821
1822 /*
1823  * parameters for eth update ramrod
1824  */
1825 struct eth_update_ramrod_data {
1826         struct tstorm_eth_function_common_config func_config;
1827         u8 indirectionTable[128];
1828 };
1829
1830
1831 /*
1832  * MAC filtering configuration command header
1833  */
1834 struct mac_configuration_hdr {
1835         u8 length_6b;
1836         u8 offset;
1837         u16 reserved0;
1838         u32 reserved1;
1839 };
1840
1841 /*
1842  * MAC address in list for ramrod
1843  */
1844 struct tstorm_cam_entry {
1845         u16 lsb_mac_addr;
1846         u16 middle_mac_addr;
1847         u16 msb_mac_addr;
1848         u16 flags;
1849 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
1850 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
1851 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
1852 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
1853 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
1854 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
1855 };
1856
1857 /*
1858  * MAC filtering: CAM target table entry
1859  */
1860 struct tstorm_cam_target_table_entry {
1861         u8 flags;
1862 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
1863 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
1864 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
1865 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
1866 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
1867 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
1868 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
1869 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
1870 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
1871 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
1872         u8 client_id;
1873         u16 vlan_id;
1874 };
1875
1876 /*
1877  * MAC address in list for ramrod
1878  */
1879 struct mac_configuration_entry {
1880         struct tstorm_cam_entry cam_entry;
1881         struct tstorm_cam_target_table_entry target_table_entry;
1882 };
1883
1884 /*
1885  * MAC filtering configuration command
1886  */
1887 struct mac_configuration_cmd {
1888         struct mac_configuration_hdr hdr;
1889         struct mac_configuration_entry config_table[64];
1890 };
1891
1892
1893 /*
1894  * Configuration parameters per client in Tstorm
1895  */
1896 struct tstorm_eth_client_config {
1897 #if defined(__BIG_ENDIAN)
1898         u16 statistics_counter_id;
1899         u16 mtu;
1900 #elif defined(__LITTLE_ENDIAN)
1901         u16 mtu;
1902         u16 statistics_counter_id;
1903 #endif
1904 #if defined(__BIG_ENDIAN)
1905         u16 drop_flags;
1906 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
1907 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1908 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1909 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1910 #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
1911 #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
1912 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
1913 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
1914 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
1915 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
1916 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1917 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1918         u16 config_flags;
1919 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1920 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1921 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1922 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1923 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
1924 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
1925 #elif defined(__LITTLE_ENDIAN)
1926         u16 config_flags;
1927 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1928 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1929 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1930 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1931 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
1932 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
1933         u16 drop_flags;
1934 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
1935 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1936 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1937 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1938 #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
1939 #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
1940 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
1941 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
1942 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
1943 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
1944 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1945 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1946 #endif
1947 };
1948
1949
1950 /*
1951  * MAC filtering configuration parameters per port in Tstorm
1952  */
1953 struct tstorm_eth_mac_filter_config {
1954         u32 ucast_drop_all;
1955         u32 ucast_accept_all;
1956         u32 mcast_drop_all;
1957         u32 mcast_accept_all;
1958         u32 bcast_drop_all;
1959         u32 bcast_accept_all;
1960         u32 strict_vlan;
1961         u32 __secondary_vlan_clients;
1962 };
1963
1964
1965 struct rate_shaping_per_protocol {
1966 #if defined(__BIG_ENDIAN)
1967         u16 reserved0;
1968         u16 protocol_rate;
1969 #elif defined(__LITTLE_ENDIAN)
1970         u16 protocol_rate;
1971         u16 reserved0;
1972 #endif
1973         u32 protocol_quota;
1974         s32 current_credit;
1975         u32 reserved;
1976 };
1977
1978 struct rate_shaping_vars {
1979         struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
1980         u32 pause_mask;
1981         u32 periodic_stop;
1982         u32 rs_periodic_timeout;
1983         u32 rs_threshold;
1984         u32 last_periodic_time;
1985         u32 reserved;
1986 };
1987
1988 struct fairness_per_protocol {
1989         u32 credit_delta;
1990         s32 fair_credit;
1991 #if defined(__BIG_ENDIAN)
1992         u16 reserved0;
1993         u8 state;
1994         u8 weight;
1995 #elif defined(__LITTLE_ENDIAN)
1996         u8 weight;
1997         u8 state;
1998         u16 reserved0;
1999 #endif
2000         u32 reserved1;
2001 };
2002
2003 struct fairness_vars {
2004         struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
2005         u32 upper_bound;
2006         u32 port_rate;
2007         u32 pause_mask;
2008         u32 fair_threshold;
2009 };
2010
2011 struct safc_struct {
2012         u32 cur_pause_mask;
2013         u32 expire_time;
2014 #if defined(__BIG_ENDIAN)
2015         u16 reserved0;
2016         u8 cur_cos_types;
2017         u8 safc_timeout_usec;
2018 #elif defined(__LITTLE_ENDIAN)
2019         u8 safc_timeout_usec;
2020         u8 cur_cos_types;
2021         u16 reserved0;
2022 #endif
2023         u32 reserved1;
2024 };
2025
2026 struct demo_struct {
2027         u8 con_number[NUM_OF_PROTOCOLS];
2028 #if defined(__BIG_ENDIAN)
2029         u8 reserved1;
2030         u8 fairness_enable;
2031         u8 rate_shaping_enable;
2032         u8 cmng_enable;
2033 #elif defined(__LITTLE_ENDIAN)
2034         u8 cmng_enable;
2035         u8 rate_shaping_enable;
2036         u8 fairness_enable;
2037         u8 reserved1;
2038 #endif
2039 };
2040
2041 struct cmng_struct {
2042         struct rate_shaping_vars rs_vars;
2043         struct fairness_vars fair_vars;
2044         struct safc_struct safc_vars;
2045         struct demo_struct demo_vars;
2046 };
2047
2048
2049 struct cos_to_protocol {
2050         u8 mask[MAX_COS_NUMBER];
2051 };
2052
2053
2054 /*
2055  * Common statistics collected by the Xstorm (per port)
2056  */
2057 struct xstorm_common_stats {
2058         struct regpair total_sent_bytes;
2059         u32 total_sent_pkts;
2060         u32 unicast_pkts_sent;
2061         struct regpair unicast_bytes_sent;
2062         struct regpair multicast_bytes_sent;
2063         u32 multicast_pkts_sent;
2064         u32 broadcast_pkts_sent;
2065         struct regpair broadcast_bytes_sent;
2066         struct regpair done;
2067 };
2068
2069 /*
2070  * Protocol-common statistics collected by the Tstorm (per client)
2071  */
2072 struct tstorm_per_client_stats {
2073         struct regpair total_rcv_bytes;
2074         struct regpair rcv_unicast_bytes;
2075         struct regpair rcv_broadcast_bytes;
2076         struct regpair rcv_multicast_bytes;
2077         struct regpair rcv_error_bytes;
2078         u32 checksum_discard;
2079         u32 packets_too_big_discard;
2080         u32 total_rcv_pkts;
2081         u32 rcv_unicast_pkts;
2082         u32 rcv_broadcast_pkts;
2083         u32 rcv_multicast_pkts;
2084         u32 no_buff_discard;
2085         u32 ttl0_discard;
2086         u32 mac_discard;
2087         u32 reserved;
2088 };
2089
2090 /*
2091  * Protocol-common statistics collected by the Tstorm (per port)
2092  */
2093 struct tstorm_common_stats {
2094         struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2095         u32 mac_filter_discard;
2096         u32 xxoverflow_discard;
2097         u32 brb_truncate_discard;
2098         u32 reserved;
2099         struct regpair done;
2100 };
2101
2102 /*
2103  * Eth statistics query sturcture for the eth_stats_quesry ramrod
2104  */
2105 struct eth_stats_query {
2106         struct xstorm_common_stats xstorm_common;
2107         struct tstorm_common_stats tstorm_common;
2108 };
2109
2110
2111 /*
2112  * FW version stored in the Xstorm RAM
2113  */
2114 struct fw_version {
2115 #if defined(__BIG_ENDIAN)
2116         u16 patch;
2117         u8 primary;
2118         u8 client;
2119 #elif defined(__LITTLE_ENDIAN)
2120         u8 client;
2121         u8 primary;
2122         u16 patch;
2123 #endif
2124         u32 flags;
2125 #define FW_VERSION_OPTIMIZED (0x1<<0)
2126 #define FW_VERSION_OPTIMIZED_SHIFT 0
2127 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2128 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2129 #define __FW_VERSION_RESERVED (0x3FFFFFFF<<2)
2130 #define __FW_VERSION_RESERVED_SHIFT 2
2131 };
2132
2133
2134 /*
2135  * FW version stored in first line of pram
2136  */
2137 struct pram_fw_version {
2138 #if defined(__BIG_ENDIAN)
2139         u16 patch;
2140         u8 primary;
2141         u8 client;
2142 #elif defined(__LITTLE_ENDIAN)
2143         u8 client;
2144         u8 primary;
2145         u16 patch;
2146 #endif
2147         u8 flags;
2148 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2149 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2150 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2151 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2152 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2153 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2154 #define __PRAM_FW_VERSION_RESERVED0 (0xF<<4)
2155 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 4
2156 };
2157
2158
2159 /*
2160  * The send queue element
2161  */
2162 struct slow_path_element {
2163         struct spe_hdr hdr;
2164         u8 protocol_data[8];
2165 };
2166
2167
2168 /*
2169  * eth/toe flags that indicate if to query
2170  */
2171 struct stats_indication_flags {
2172         u32 collect_eth;
2173         u32 collect_toe;
2174 };
2175
2176