bnx2x: Per queue statistics
[linux-2.6.git] / drivers / net / bnx2x_hsi.h
1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2008 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9
10
11 #define PORT_0                          0
12 #define PORT_1                          1
13 #define PORT_MAX                        2
14
15 /****************************************************************************
16  * Shared HW configuration                                                  *
17  ****************************************************************************/
18 struct shared_hw_cfg {                                   /* NVRAM Offset */
19         /* Up to 16 bytes of NULL-terminated string */
20         u8  part_num[16];                                       /* 0x104 */
21
22         u32 config;                                             /* 0x114 */
23 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
24 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT            0
25 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V             0x00000000
26 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V             0x00000001
27 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
28
29 #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
30
31 #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
32
33 #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
34 #define SHARED_HW_CFG_MFW_SELECT_SHIFT              8
35         /* Whatever MFW found in NVM
36            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT            0x00000000
38 #define SHARED_HW_CFG_MFW_SELECT_NC_SI              0x00000100
39 #define SHARED_HW_CFG_MFW_SELECT_UMP                0x00000200
40 #define SHARED_HW_CFG_MFW_SELECT_IPMI               0x00000300
41         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
44         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
47         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
50
51 #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
52 #define SHARED_HW_CFG_LED_MODE_SHIFT                16
53 #define SHARED_HW_CFG_LED_MAC1                      0x00000000
54 #define SHARED_HW_CFG_LED_PHY1                      0x00010000
55 #define SHARED_HW_CFG_LED_PHY2                      0x00020000
56 #define SHARED_HW_CFG_LED_PHY3                      0x00030000
57 #define SHARED_HW_CFG_LED_MAC2                      0x00040000
58 #define SHARED_HW_CFG_LED_PHY4                      0x00050000
59 #define SHARED_HW_CFG_LED_PHY5                      0x00060000
60 #define SHARED_HW_CFG_LED_PHY6                      0x00070000
61 #define SHARED_HW_CFG_LED_MAC3                      0x00080000
62 #define SHARED_HW_CFG_LED_PHY7                      0x00090000
63 #define SHARED_HW_CFG_LED_PHY9                      0x000a0000
64 #define SHARED_HW_CFG_LED_PHY11                     0x000b0000
65 #define SHARED_HW_CFG_LED_MAC4                      0x000c0000
66 #define SHARED_HW_CFG_LED_PHY8                      0x000d0000
67
68 #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
69 #define SHARED_HW_CFG_AN_ENABLE_SHIFT               24
70 #define SHARED_HW_CFG_AN_ENABLE_CL37                0x01000000
71 #define SHARED_HW_CFG_AN_ENABLE_CL73                0x02000000
72 #define SHARED_HW_CFG_AN_ENABLE_BAM                 0x04000000
73 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
74 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY          0x20000000
76
77         u32 config2;                                            /* 0x118 */
78         /* one time auto detect grace period (in sec) */
79 #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
80 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT            0
81
82 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
83
84         /* The default value for the core clock is 250MHz and it is
85            achieved by setting the clock change to 4 */
86 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
87 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT            9
88
89 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ           0x00000000
90 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ           0x00001000
91
92 #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
93
94         u32 power_dissipated;                                   /* 0x11c */
95 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
96 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT           24
97
98 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
99 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT        16
100 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE      0x00000000
101 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT         0x00010000
102 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT        0x00020000
103 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT       0x00030000
104
105         u32 ump_nc_si_config;                                   /* 0x120 */
106 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
107 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT      0
108 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC        0x00000000
109 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY        0x00000001
110 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII        0x00000000
111 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII       0x00000002
112
113 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
114 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT      8
115
116 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
117 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
118 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
119 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
120
121         u32 board;                                              /* 0x124 */
122 #define SHARED_HW_CFG_BOARD_TYPE_MASK               0x0000ffff
123 #define SHARED_HW_CFG_BOARD_TYPE_SHIFT              0
124 #define SHARED_HW_CFG_BOARD_TYPE_NONE               0x00000000
125 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000     0x00000001
126 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001     0x00000002
127 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G    0x00000003
128 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G    0x00000004
129 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G    0x00000005
130 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G    0x00000006
131 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G    0x00000007
132 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G    0x00000008
133 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G    0x00000009
134 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G    0x0000000a
135 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G    0x0000000b
136 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G    0x0000000c
137 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101     0x0000000d
138 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201    0x0000000e
139 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G    0x0000000f
140 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G   0x00000010
141
142 #define SHARED_HW_CFG_BOARD_VER_MASK                0xffff0000
143 #define SHARED_HW_CFG_BOARD_VER_SHIFT               16
144 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0xf0000000
145 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT         28
146 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0x0f000000
147 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT         24
148 #define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000
149 #define SHARED_HW_CFG_BOARD_REV_SHIFT               16
150
151         u32 reserved;                                           /* 0x128 */
152
153 };
154
155
156 /****************************************************************************
157  * Port HW configuration                                                    *
158  ****************************************************************************/
159 struct port_hw_cfg {                        /* port 0: 0x12c  port 1: 0x2bc */
160
161         u32 pci_id;
162 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
163 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
164
165         u32 pci_sub_id;
166 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
167 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
168
169         u32 power_dissipated;
170 #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
171 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT              24
172 #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
173 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT              16
174 #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
175 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT              8
176 #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
177 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT              0
178
179         u32 power_consumed;
180 #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
181 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT             24
182 #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
183 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT             16
184 #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
185 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT             8
186 #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
187 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT             0
188
189         u32 mac_upper;
190 #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
191 #define PORT_HW_CFG_UPPERMAC_SHIFT                  0
192         u32 mac_lower;
193
194         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
195         u32 iscsi_mac_lower;
196
197         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
198         u32 rdma_mac_lower;
199
200         u32 serdes_config;
201         /* for external PHY, or forced mode or during AN */
202 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
203 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT  16
204
205 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0x0000ffff
206 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT   0
207
208         u16 serdes_tx_driver_pre_emphasis[16];
209         u16 serdes_rx_driver_equalizer[16];
210
211         u32 xgxs_config_lane0;
212         u32 xgxs_config_lane1;
213         u32 xgxs_config_lane2;
214         u32 xgxs_config_lane3;
215         /* for external PHY, or forced mode or during AN */
216 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK   0xffff0000
217 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT  16
218
219 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK      0x0000ffff
220 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT     0
221
222         u16 xgxs_tx_driver_pre_emphasis_lane0[16];
223         u16 xgxs_tx_driver_pre_emphasis_lane1[16];
224         u16 xgxs_tx_driver_pre_emphasis_lane2[16];
225         u16 xgxs_tx_driver_pre_emphasis_lane3[16];
226
227         u16 xgxs_rx_driver_equalizer_lane0[16];
228         u16 xgxs_rx_driver_equalizer_lane1[16];
229         u16 xgxs_rx_driver_equalizer_lane2[16];
230         u16 xgxs_rx_driver_equalizer_lane3[16];
231
232         u32 lane_config;
233 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
234 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT             0
235 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
236 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT          0
237 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
238 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT          8
239 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
240 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT      14
241         /* AN and forced */
242 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123          0x00001b1b
243         /* forced only */
244 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210          0x00001be4
245         /* forced only */
246 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120          0x0000d8d8
247         /* forced only */
248 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210          0x0000e4e4
249
250         u32 external_phy_config;
251 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
252 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT       24
253 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT      0x00000000
254 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
255 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
256
257 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
258 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT       16
259
260 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
261 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT         8
262 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT        0x00000000
263 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071       0x00000100
264 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072       0x00000200
265 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073       0x00000300
266 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705       0x00000400
267 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706       0x00000500
268 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276       0x00000600
269 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481       0x00000700
270 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101       0x00000800
271 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE       0x0000fd00
272 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN      0x0000ff00
273
274 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
275 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT         0
276
277         u32 speed_capability_mask;
278 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
279 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT       16
280 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
281 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
282 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
283 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
284 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G          0x00100000
285 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G        0x00200000
286 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G         0x00400000
287 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G         0x00800000
288 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G       0x01000000
289 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G         0x02000000
290 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G         0x04000000
291 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G         0x08000000
292 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
293
294 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
295 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT       0
296 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
297 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
298 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
299 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
300 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G          0x00000010
301 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G        0x00000020
302 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G         0x00000040
303 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G         0x00000080
304 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G       0x00000100
305 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G         0x00000200
306 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G         0x00000400
307 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G         0x00000800
308 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
309
310         u32 reserved[2];
311
312 };
313
314
315 /****************************************************************************
316  * Shared Feature configuration                                             *
317  ****************************************************************************/
318 struct shared_feat_cfg {                                 /* NVRAM Offset */
319
320         u32 config;                                             /* 0x450 */
321 #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
322 #define SHARED_FEATURE_MF_MODE_DISABLED             0x00000100
323
324 };
325
326
327 /****************************************************************************
328  * Port Feature configuration                                               *
329  ****************************************************************************/
330 struct port_feat_cfg {                      /* port 0: 0x454  port 1: 0x4c8 */
331
332         u32 config;
333 #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
334 #define PORT_FEATURE_BAR1_SIZE_SHIFT                0
335 #define PORT_FEATURE_BAR1_SIZE_DISABLED             0x00000000
336 #define PORT_FEATURE_BAR1_SIZE_64K                  0x00000001
337 #define PORT_FEATURE_BAR1_SIZE_128K                 0x00000002
338 #define PORT_FEATURE_BAR1_SIZE_256K                 0x00000003
339 #define PORT_FEATURE_BAR1_SIZE_512K                 0x00000004
340 #define PORT_FEATURE_BAR1_SIZE_1M                   0x00000005
341 #define PORT_FEATURE_BAR1_SIZE_2M                   0x00000006
342 #define PORT_FEATURE_BAR1_SIZE_4M                   0x00000007
343 #define PORT_FEATURE_BAR1_SIZE_8M                   0x00000008
344 #define PORT_FEATURE_BAR1_SIZE_16M                  0x00000009
345 #define PORT_FEATURE_BAR1_SIZE_32M                  0x0000000a
346 #define PORT_FEATURE_BAR1_SIZE_64M                  0x0000000b
347 #define PORT_FEATURE_BAR1_SIZE_128M                 0x0000000c
348 #define PORT_FEATURE_BAR1_SIZE_256M                 0x0000000d
349 #define PORT_FEATURE_BAR1_SIZE_512M                 0x0000000e
350 #define PORT_FEATURE_BAR1_SIZE_1G                   0x0000000f
351 #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
352 #define PORT_FEATURE_BAR2_SIZE_SHIFT                4
353 #define PORT_FEATURE_BAR2_SIZE_DISABLED             0x00000000
354 #define PORT_FEATURE_BAR2_SIZE_64K                  0x00000010
355 #define PORT_FEATURE_BAR2_SIZE_128K                 0x00000020
356 #define PORT_FEATURE_BAR2_SIZE_256K                 0x00000030
357 #define PORT_FEATURE_BAR2_SIZE_512K                 0x00000040
358 #define PORT_FEATURE_BAR2_SIZE_1M                   0x00000050
359 #define PORT_FEATURE_BAR2_SIZE_2M                   0x00000060
360 #define PORT_FEATURE_BAR2_SIZE_4M                   0x00000070
361 #define PORT_FEATURE_BAR2_SIZE_8M                   0x00000080
362 #define PORT_FEATURE_BAR2_SIZE_16M                  0x00000090
363 #define PORT_FEATURE_BAR2_SIZE_32M                  0x000000a0
364 #define PORT_FEATURE_BAR2_SIZE_64M                  0x000000b0
365 #define PORT_FEATURE_BAR2_SIZE_128M                 0x000000c0
366 #define PORT_FEATURE_BAR2_SIZE_256M                 0x000000d0
367 #define PORT_FEATURE_BAR2_SIZE_512M                 0x000000e0
368 #define PORT_FEATURE_BAR2_SIZE_1G                   0x000000f0
369 #define PORT_FEATURE_EN_SIZE_MASK                   0x07000000
370 #define PORT_FEATURE_EN_SIZE_SHIFT                  24
371 #define PORT_FEATURE_WOL_ENABLED                    0x01000000
372 #define PORT_FEATURE_MBA_ENABLED                    0x02000000
373 #define PORT_FEATURE_MFW_ENABLED                    0x04000000
374
375         u32 wol_config;
376         /* Default is used when driver sets to "auto" mode */
377 #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
378 #define PORT_FEATURE_WOL_DEFAULT_SHIFT              0
379 #define PORT_FEATURE_WOL_DEFAULT_DISABLE            0x00000000
380 #define PORT_FEATURE_WOL_DEFAULT_MAGIC              0x00000001
381 #define PORT_FEATURE_WOL_DEFAULT_ACPI               0x00000002
382 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
383 #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
384 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
385 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
386
387         u32 mba_config;
388 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000003
389 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT      0
390 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0x00000000
391 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        0x00000001
392 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      0x00000002
393 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
394 #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
395 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
396 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
397 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S              0x00000000
398 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B              0x00000800
399 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
400 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT         12
401 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0x00000000
402 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K            0x00001000
403 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K            0x00002000
404 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K            0x00003000
405 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K           0x00004000
406 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K           0x00005000
407 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K           0x00006000
408 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K          0x00007000
409 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K          0x00008000
410 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K          0x00009000
411 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M            0x0000a000
412 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M            0x0000b000
413 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M            0x0000c000
414 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M            0x0000d000
415 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M           0x0000e000
416 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M           0x0000f000
417 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
418 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT          20
419 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
420 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT       24
421 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0x00000000
422 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x01000000
423 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x02000000
424 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x03000000
425 #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
426 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT           26
427 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO            0x00000000
428 #define PORT_FEATURE_MBA_LINK_SPEED_10HD            0x04000000
429 #define PORT_FEATURE_MBA_LINK_SPEED_10FD            0x08000000
430 #define PORT_FEATURE_MBA_LINK_SPEED_100HD           0x0c000000
431 #define PORT_FEATURE_MBA_LINK_SPEED_100FD           0x10000000
432 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS           0x14000000
433 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS         0x18000000
434 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4      0x1c000000
435 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4      0x20000000
436 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR       0x24000000
437 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS          0x28000000
438 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS        0x2c000000
439 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS          0x30000000
440 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS          0x34000000
441 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS          0x38000000
442
443         u32 bmc_config;
444 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT      0x00000000
445 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN           0x00000001
446
447         u32 mba_vlan_cfg;
448 #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
449 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT             0
450 #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
451
452         u32 resource_cfg;
453 #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
454 #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
455 #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
456 #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
457 #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
458
459         u32 smbus_config;
460         /* Obsolete */
461 #define PORT_FEATURE_SMBUS_EN                       0x00000001
462 #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
463 #define PORT_FEATURE_SMBUS_ADDR_SHIFT               1
464
465         u32 reserved1;
466
467         u32 link_config;    /* Used as HW defaults for the driver */
468 #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
469 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT         24
470         /* (forced) low speed switch (< 10G) */
471 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH           0x00000000
472         /* (forced) high speed switch (>= 10G) */
473 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH          0x01000000
474 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT         0x02000000
475 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
476
477 #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
478 #define PORT_FEATURE_LINK_SPEED_SHIFT               16
479 #define PORT_FEATURE_LINK_SPEED_AUTO                0x00000000
480 #define PORT_FEATURE_LINK_SPEED_10M_FULL            0x00010000
481 #define PORT_FEATURE_LINK_SPEED_10M_HALF            0x00020000
482 #define PORT_FEATURE_LINK_SPEED_100M_HALF           0x00030000
483 #define PORT_FEATURE_LINK_SPEED_100M_FULL           0x00040000
484 #define PORT_FEATURE_LINK_SPEED_1G                  0x00050000
485 #define PORT_FEATURE_LINK_SPEED_2_5G                0x00060000
486 #define PORT_FEATURE_LINK_SPEED_10G_CX4             0x00070000
487 #define PORT_FEATURE_LINK_SPEED_10G_KX4             0x00080000
488 #define PORT_FEATURE_LINK_SPEED_10G_KR              0x00090000
489 #define PORT_FEATURE_LINK_SPEED_12G                 0x000a0000
490 #define PORT_FEATURE_LINK_SPEED_12_5G               0x000b0000
491 #define PORT_FEATURE_LINK_SPEED_13G                 0x000c0000
492 #define PORT_FEATURE_LINK_SPEED_15G                 0x000d0000
493 #define PORT_FEATURE_LINK_SPEED_16G                 0x000e0000
494
495 #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
496 #define PORT_FEATURE_FLOW_CONTROL_SHIFT             8
497 #define PORT_FEATURE_FLOW_CONTROL_AUTO              0x00000000
498 #define PORT_FEATURE_FLOW_CONTROL_TX                0x00000100
499 #define PORT_FEATURE_FLOW_CONTROL_RX                0x00000200
500 #define PORT_FEATURE_FLOW_CONTROL_BOTH              0x00000300
501 #define PORT_FEATURE_FLOW_CONTROL_NONE              0x00000400
502
503         /* The default for MCP link configuration,
504            uses the same defines as link_config */
505         u32 mfw_wol_link_cfg;
506
507         u32 reserved[19];
508
509 };
510
511
512 /****************************************************************************
513  * Device Information                                                       *
514  ****************************************************************************/
515 struct dev_info {                                                   /* size */
516
517         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
518
519         struct shared_hw_cfg     shared_hw_config;                    /* 40 */
520
521         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
522
523         struct shared_feat_cfg   shared_feature_config;                /* 4 */
524
525         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
526
527 };
528
529
530 #define FUNC_0                          0
531 #define FUNC_1                          1
532 #define FUNC_2                          2
533 #define FUNC_3                          3
534 #define FUNC_4                          4
535 #define FUNC_5                          5
536 #define FUNC_6                          6
537 #define FUNC_7                          7
538 #define E1_FUNC_MAX                     2
539 #define E1H_FUNC_MAX                    8
540
541 #define VN_0                            0
542 #define VN_1                            1
543 #define VN_2                            2
544 #define VN_3                            3
545 #define E1VN_MAX                        1
546 #define E1HVN_MAX                       4
547
548
549 /* This value (in milliseconds) determines the frequency of the driver
550  * issuing the PULSE message code.  The firmware monitors this periodic
551  * pulse to determine when to switch to an OS-absent mode. */
552 #define DRV_PULSE_PERIOD_MS             250
553
554 /* This value (in milliseconds) determines how long the driver should
555  * wait for an acknowledgement from the firmware before timing out.  Once
556  * the firmware has timed out, the driver will assume there is no firmware
557  * running and there won't be any firmware-driver synchronization during a
558  * driver reset. */
559 #define FW_ACK_TIME_OUT_MS              5000
560
561 #define FW_ACK_POLL_TIME_MS             1
562
563 #define FW_ACK_NUM_OF_POLL      (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
564
565 /* LED Blink rate that will achieve ~15.9Hz */
566 #define LED_BLINK_RATE_VAL              480
567
568 /****************************************************************************
569  * Driver <-> FW Mailbox                                                    *
570  ****************************************************************************/
571 struct drv_port_mb {
572
573         u32 link_status;
574         /* Driver should update this field on any link change event */
575
576 #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
577 #define LINK_STATUS_LINK_UP                             0x00000001
578 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
579 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
580 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
581 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
582 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
583 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
584 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
585 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
586 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
587 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
588 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
589 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
590 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
591 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
592 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
593 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD             (11<<1)
594 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD             (11<<1)
595 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD           (12<<1)
596 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD           (12<<1)
597 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD             (13<<1)
598 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD             (13<<1)
599 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD             (14<<1)
600 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD             (14<<1)
601 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD             (15<<1)
602 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD             (15<<1)
603
604 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
605 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
606
607 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
608 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
609 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
610
611 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
612 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
613 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
614 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
615 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
616 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
617 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
618
619 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
620 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
621
622 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
623 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
624
625 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
626 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
627 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
628 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
629 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
630
631 #define LINK_STATUS_SERDES_LINK                         0x00100000
632
633 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
634 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
635 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
636 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE         0x01000000
637 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE       0x02000000
638 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE         0x04000000
639 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE         0x08000000
640 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE         0x10000000
641
642         u32 port_stx;
643
644         u32 stat_nig_timer;
645
646
647 };
648
649
650 struct drv_func_mb {
651
652         u32 drv_mb_header;
653 #define DRV_MSG_CODE_MASK                               0xffff0000
654 #define DRV_MSG_CODE_LOAD_REQ                           0x10000000
655 #define DRV_MSG_CODE_LOAD_DONE                          0x11000000
656 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN                  0x20000000
657 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS                 0x20010000
658 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP                 0x20020000
659 #define DRV_MSG_CODE_UNLOAD_DONE                        0x21000000
660 #define DRV_MSG_CODE_DIAG_ENTER_REQ                     0x50000000
661 #define DRV_MSG_CODE_DIAG_EXIT_REQ                      0x60000000
662 #define DRV_MSG_CODE_VALIDATE_KEY                       0x70000000
663 #define DRV_MSG_CODE_GET_CURR_KEY                       0x80000000
664 #define DRV_MSG_CODE_GET_UPGRADE_KEY                    0x81000000
665 #define DRV_MSG_CODE_GET_MANUF_KEY                      0x82000000
666 #define DRV_MSG_CODE_LOAD_L2B_PRAM                      0x90000000
667
668 #define BIOS_MSG_CODE_LIC_CHALLENGE                     0xff010000
669 #define BIOS_MSG_CODE_LIC_RESPONSE                      0xff020000
670 #define BIOS_MSG_CODE_VIRT_MAC_PRIM                     0xff030000
671 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI                    0xff040000
672
673 #define DRV_MSG_SEQ_NUMBER_MASK                         0x0000ffff
674
675         u32 drv_mb_param;
676
677         u32 fw_mb_header;
678 #define FW_MSG_CODE_MASK                                0xffff0000
679 #define FW_MSG_CODE_DRV_LOAD_COMMON                     0x10100000
680 #define FW_MSG_CODE_DRV_LOAD_PORT                       0x10110000
681 #define FW_MSG_CODE_DRV_LOAD_FUNCTION                   0x10120000
682 #define FW_MSG_CODE_DRV_LOAD_REFUSED                    0x10200000
683 #define FW_MSG_CODE_DRV_LOAD_DONE                       0x11100000
684 #define FW_MSG_CODE_DRV_UNLOAD_COMMON                   0x20100000
685 #define FW_MSG_CODE_DRV_UNLOAD_PORT                     0x20110000
686 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION                 0x20120000
687 #define FW_MSG_CODE_DRV_UNLOAD_DONE                     0x21100000
688 #define FW_MSG_CODE_DIAG_ENTER_DONE                     0x50100000
689 #define FW_MSG_CODE_DIAG_REFUSE                         0x50200000
690 #define FW_MSG_CODE_DIAG_EXIT_DONE                      0x60100000
691 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS                0x70100000
692 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE                0x70200000
693 #define FW_MSG_CODE_GET_KEY_DONE                        0x80100000
694 #define FW_MSG_CODE_NO_KEY                              0x80f00000
695 #define FW_MSG_CODE_LIC_INFO_NOT_READY                  0x80f80000
696 #define FW_MSG_CODE_L2B_PRAM_LOADED                     0x90100000
697 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE             0x90210000
698 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE             0x90220000
699 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE             0x90230000
700 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE             0x90240000
701
702 #define FW_MSG_CODE_LIC_CHALLENGE                       0xff010000
703 #define FW_MSG_CODE_LIC_RESPONSE                        0xff020000
704 #define FW_MSG_CODE_VIRT_MAC_PRIM                       0xff030000
705 #define FW_MSG_CODE_VIRT_MAC_ISCSI                      0xff040000
706
707 #define FW_MSG_SEQ_NUMBER_MASK                          0x0000ffff
708
709         u32 fw_mb_param;
710
711         u32 drv_pulse_mb;
712 #define DRV_PULSE_SEQ_MASK                              0x00007fff
713 #define DRV_PULSE_SYSTEM_TIME_MASK                      0xffff0000
714         /* The system time is in the format of
715          * (year-2001)*12*32 + month*32 + day. */
716 #define DRV_PULSE_ALWAYS_ALIVE                          0x00008000
717         /* Indicate to the firmware not to go into the
718          * OS-absent when it is not getting driver pulse.
719          * This is used for debugging as well for PXE(MBA). */
720
721         u32 mcp_pulse_mb;
722 #define MCP_PULSE_SEQ_MASK                              0x00007fff
723 #define MCP_PULSE_ALWAYS_ALIVE                          0x00008000
724         /* Indicates to the driver not to assert due to lack
725          * of MCP response */
726 #define MCP_EVENT_MASK                                  0xffff0000
727 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ                0x00010000
728
729         u32 iscsi_boot_signature;
730         u32 iscsi_boot_block_offset;
731
732         u32 drv_status;
733 #define DRV_STATUS_PMF                                  0x00000001
734
735         u32 virt_mac_upper;
736 #define VIRT_MAC_SIGN_MASK                              0xffff0000
737 #define VIRT_MAC_SIGNATURE                              0x564d0000
738         u32 virt_mac_lower;
739
740 };
741
742
743 /****************************************************************************
744  * Management firmware state                                                *
745  ****************************************************************************/
746 /* Allocate 440 bytes for management firmware */
747 #define MGMTFW_STATE_WORD_SIZE                              110
748
749 struct mgmtfw_state {
750         u32 opaque[MGMTFW_STATE_WORD_SIZE];
751 };
752
753
754 /****************************************************************************
755  * Multi-Function configuration                                             *
756  ****************************************************************************/
757 struct shared_mf_cfg {
758
759         u32 clp_mb;
760 #define SHARED_MF_CLP_SET_DEFAULT                   0x00000000
761         /* set by CLP */
762 #define SHARED_MF_CLP_EXIT                          0x00000001
763         /* set by MCP */
764 #define SHARED_MF_CLP_EXIT_DONE                     0x00010000
765
766 };
767
768 struct port_mf_cfg {
769
770         u32 dynamic_cfg;        /* device control channel */
771 #define PORT_MF_CFG_OUTER_VLAN_TAG_MASK             0x0000ffff
772 #define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT            0
773 #define PORT_MF_CFG_DYNAMIC_CFG_ENABLED             0x00010000
774 #define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT             0x00000000
775
776         u32 reserved[3];
777
778 };
779
780 struct func_mf_cfg {
781
782         u32 config;
783         /* E/R/I/D */
784         /* function 0 of each port cannot be hidden */
785 #define FUNC_MF_CFG_FUNC_HIDE                       0x00000001
786
787 #define FUNC_MF_CFG_PROTOCOL_MASK                   0x00000007
788 #define FUNC_MF_CFG_PROTOCOL_ETHERNET               0x00000002
789 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA     0x00000004
790 #define FUNC_MF_CFG_PROTOCOL_ISCSI                  0x00000006
791 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
792         FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
793
794 #define FUNC_MF_CFG_FUNC_DISABLED                   0x00000008
795
796         /* PRI */
797         /* 0 - low priority, 3 - high priority */
798 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK          0x00000300
799 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT         8
800 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT       0x00000000
801
802         /* MINBW, MAXBW */
803         /* value range - 0..100, increments in 100Mbps */
804 #define FUNC_MF_CFG_MIN_BW_MASK                     0x00ff0000
805 #define FUNC_MF_CFG_MIN_BW_SHIFT                    16
806 #define FUNC_MF_CFG_MIN_BW_DEFAULT                  0x00000000
807 #define FUNC_MF_CFG_MAX_BW_MASK                     0xff000000
808 #define FUNC_MF_CFG_MAX_BW_SHIFT                    24
809 #define FUNC_MF_CFG_MAX_BW_DEFAULT                  0x64000000
810
811         u32 mac_upper;          /* MAC */
812 #define FUNC_MF_CFG_UPPERMAC_MASK                   0x0000ffff
813 #define FUNC_MF_CFG_UPPERMAC_SHIFT                  0
814 #define FUNC_MF_CFG_UPPERMAC_DEFAULT                FUNC_MF_CFG_UPPERMAC_MASK
815         u32 mac_lower;
816 #define FUNC_MF_CFG_LOWERMAC_DEFAULT                0xffffffff
817
818         u32 e1hov_tag;  /* VNI */
819 #define FUNC_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
820 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT                 0
821 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT               FUNC_MF_CFG_E1HOV_TAG_MASK
822
823         u32 reserved[2];
824
825 };
826
827 struct mf_cfg {
828
829         struct shared_mf_cfg    shared_mf_config;
830         struct port_mf_cfg      port_mf_config[PORT_MAX];
831 #if defined(b710)
832         struct func_mf_cfg      func_mf_config[E1_FUNC_MAX];
833 #else
834         struct func_mf_cfg      func_mf_config[E1H_FUNC_MAX];
835 #endif
836
837 };
838
839
840 /****************************************************************************
841  * Shared Memory Region                                                     *
842  ****************************************************************************/
843 struct shmem_region {                          /*   SharedMem Offset (size) */
844
845         u32                     validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
846 #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
847 #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
848         /* validity bits */
849 #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
850 #define SHR_MEM_VALIDITY_MB                         0x00200000
851 #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
852 #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
853         /* One licensing bit should be set */
854 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
855 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
856 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
857 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
858         /* Active MFW */
859 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
860 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
861 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
862 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
863 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
864 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
865
866         struct dev_info         dev_info;                /* 0x8     (0x438) */
867
868         u8                      reserved[52*PORT_MAX];
869
870         /* FW information (for internal FW use) */
871         u32                     fw_info_fio_offset;    /* 0x4a8       (0x4) */
872         struct mgmtfw_state     mgmtfw_state;          /* 0x4ac     (0x1b8) */
873
874         struct drv_port_mb      port_mb[PORT_MAX];     /* 0x664 (16*2=0x20) */
875         struct drv_func_mb      func_mb[E1H_FUNC_MAX];
876
877         struct mf_cfg           mf_cfg;
878
879 };                                                     /* 0x6dc */
880
881
882 struct emac_stats {
883     u32     rx_stat_ifhcinoctets;
884     u32     rx_stat_ifhcinbadoctets;
885     u32     rx_stat_etherstatsfragments;
886     u32     rx_stat_ifhcinucastpkts;
887     u32     rx_stat_ifhcinmulticastpkts;
888     u32     rx_stat_ifhcinbroadcastpkts;
889     u32     rx_stat_dot3statsfcserrors;
890     u32     rx_stat_dot3statsalignmenterrors;
891     u32     rx_stat_dot3statscarriersenseerrors;
892     u32     rx_stat_xonpauseframesreceived;
893     u32     rx_stat_xoffpauseframesreceived;
894     u32     rx_stat_maccontrolframesreceived;
895     u32     rx_stat_xoffstateentered;
896     u32     rx_stat_dot3statsframestoolong;
897     u32     rx_stat_etherstatsjabbers;
898     u32     rx_stat_etherstatsundersizepkts;
899     u32     rx_stat_etherstatspkts64octets;
900     u32     rx_stat_etherstatspkts65octetsto127octets;
901     u32     rx_stat_etherstatspkts128octetsto255octets;
902     u32     rx_stat_etherstatspkts256octetsto511octets;
903     u32     rx_stat_etherstatspkts512octetsto1023octets;
904     u32     rx_stat_etherstatspkts1024octetsto1522octets;
905     u32     rx_stat_etherstatspktsover1522octets;
906
907     u32     rx_stat_falsecarriererrors;
908
909     u32     tx_stat_ifhcoutoctets;
910     u32     tx_stat_ifhcoutbadoctets;
911     u32     tx_stat_etherstatscollisions;
912     u32     tx_stat_outxonsent;
913     u32     tx_stat_outxoffsent;
914     u32     tx_stat_flowcontroldone;
915     u32     tx_stat_dot3statssinglecollisionframes;
916     u32     tx_stat_dot3statsmultiplecollisionframes;
917     u32     tx_stat_dot3statsdeferredtransmissions;
918     u32     tx_stat_dot3statsexcessivecollisions;
919     u32     tx_stat_dot3statslatecollisions;
920     u32     tx_stat_ifhcoutucastpkts;
921     u32     tx_stat_ifhcoutmulticastpkts;
922     u32     tx_stat_ifhcoutbroadcastpkts;
923     u32     tx_stat_etherstatspkts64octets;
924     u32     tx_stat_etherstatspkts65octetsto127octets;
925     u32     tx_stat_etherstatspkts128octetsto255octets;
926     u32     tx_stat_etherstatspkts256octetsto511octets;
927     u32     tx_stat_etherstatspkts512octetsto1023octets;
928     u32     tx_stat_etherstatspkts1024octetsto1522octets;
929     u32     tx_stat_etherstatspktsover1522octets;
930     u32     tx_stat_dot3statsinternalmactransmiterrors;
931 };
932
933
934 struct bmac_stats {
935     u32     tx_stat_gtpkt_lo;
936     u32     tx_stat_gtpkt_hi;
937     u32     tx_stat_gtxpf_lo;
938     u32     tx_stat_gtxpf_hi;
939     u32     tx_stat_gtfcs_lo;
940     u32     tx_stat_gtfcs_hi;
941     u32     tx_stat_gtmca_lo;
942     u32     tx_stat_gtmca_hi;
943     u32     tx_stat_gtbca_lo;
944     u32     tx_stat_gtbca_hi;
945     u32     tx_stat_gtfrg_lo;
946     u32     tx_stat_gtfrg_hi;
947     u32     tx_stat_gtovr_lo;
948     u32     tx_stat_gtovr_hi;
949     u32     tx_stat_gt64_lo;
950     u32     tx_stat_gt64_hi;
951     u32     tx_stat_gt127_lo;
952     u32     tx_stat_gt127_hi;
953     u32     tx_stat_gt255_lo;
954     u32     tx_stat_gt255_hi;
955     u32     tx_stat_gt511_lo;
956     u32     tx_stat_gt511_hi;
957     u32     tx_stat_gt1023_lo;
958     u32     tx_stat_gt1023_hi;
959     u32     tx_stat_gt1518_lo;
960     u32     tx_stat_gt1518_hi;
961     u32     tx_stat_gt2047_lo;
962     u32     tx_stat_gt2047_hi;
963     u32     tx_stat_gt4095_lo;
964     u32     tx_stat_gt4095_hi;
965     u32     tx_stat_gt9216_lo;
966     u32     tx_stat_gt9216_hi;
967     u32     tx_stat_gt16383_lo;
968     u32     tx_stat_gt16383_hi;
969     u32     tx_stat_gtmax_lo;
970     u32     tx_stat_gtmax_hi;
971     u32     tx_stat_gtufl_lo;
972     u32     tx_stat_gtufl_hi;
973     u32     tx_stat_gterr_lo;
974     u32     tx_stat_gterr_hi;
975     u32     tx_stat_gtbyt_lo;
976     u32     tx_stat_gtbyt_hi;
977
978     u32     rx_stat_gr64_lo;
979     u32     rx_stat_gr64_hi;
980     u32     rx_stat_gr127_lo;
981     u32     rx_stat_gr127_hi;
982     u32     rx_stat_gr255_lo;
983     u32     rx_stat_gr255_hi;
984     u32     rx_stat_gr511_lo;
985     u32     rx_stat_gr511_hi;
986     u32     rx_stat_gr1023_lo;
987     u32     rx_stat_gr1023_hi;
988     u32     rx_stat_gr1518_lo;
989     u32     rx_stat_gr1518_hi;
990     u32     rx_stat_gr2047_lo;
991     u32     rx_stat_gr2047_hi;
992     u32     rx_stat_gr4095_lo;
993     u32     rx_stat_gr4095_hi;
994     u32     rx_stat_gr9216_lo;
995     u32     rx_stat_gr9216_hi;
996     u32     rx_stat_gr16383_lo;
997     u32     rx_stat_gr16383_hi;
998     u32     rx_stat_grmax_lo;
999     u32     rx_stat_grmax_hi;
1000     u32     rx_stat_grpkt_lo;
1001     u32     rx_stat_grpkt_hi;
1002     u32     rx_stat_grfcs_lo;
1003     u32     rx_stat_grfcs_hi;
1004     u32     rx_stat_grmca_lo;
1005     u32     rx_stat_grmca_hi;
1006     u32     rx_stat_grbca_lo;
1007     u32     rx_stat_grbca_hi;
1008     u32     rx_stat_grxcf_lo;
1009     u32     rx_stat_grxcf_hi;
1010     u32     rx_stat_grxpf_lo;
1011     u32     rx_stat_grxpf_hi;
1012     u32     rx_stat_grxuo_lo;
1013     u32     rx_stat_grxuo_hi;
1014     u32     rx_stat_grjbr_lo;
1015     u32     rx_stat_grjbr_hi;
1016     u32     rx_stat_grovr_lo;
1017     u32     rx_stat_grovr_hi;
1018     u32     rx_stat_grflr_lo;
1019     u32     rx_stat_grflr_hi;
1020     u32     rx_stat_grmeg_lo;
1021     u32     rx_stat_grmeg_hi;
1022     u32     rx_stat_grmeb_lo;
1023     u32     rx_stat_grmeb_hi;
1024     u32     rx_stat_grbyt_lo;
1025     u32     rx_stat_grbyt_hi;
1026     u32     rx_stat_grund_lo;
1027     u32     rx_stat_grund_hi;
1028     u32     rx_stat_grfrg_lo;
1029     u32     rx_stat_grfrg_hi;
1030     u32     rx_stat_grerb_lo;
1031     u32     rx_stat_grerb_hi;
1032     u32     rx_stat_grfre_lo;
1033     u32     rx_stat_grfre_hi;
1034     u32     rx_stat_gripj_lo;
1035     u32     rx_stat_gripj_hi;
1036 };
1037
1038
1039 union mac_stats {
1040     struct emac_stats   emac_stats;
1041     struct bmac_stats   bmac_stats;
1042 };
1043
1044
1045 struct mac_stx {
1046     /* in_bad_octets */
1047     u32     rx_stat_ifhcinbadoctets_hi;
1048     u32     rx_stat_ifhcinbadoctets_lo;
1049
1050     /* out_bad_octets */
1051     u32     tx_stat_ifhcoutbadoctets_hi;
1052     u32     tx_stat_ifhcoutbadoctets_lo;
1053
1054     /* crc_receive_errors */
1055     u32     rx_stat_dot3statsfcserrors_hi;
1056     u32     rx_stat_dot3statsfcserrors_lo;
1057     /* alignment_errors */
1058     u32     rx_stat_dot3statsalignmenterrors_hi;
1059     u32     rx_stat_dot3statsalignmenterrors_lo;
1060     /* carrier_sense_errors */
1061     u32     rx_stat_dot3statscarriersenseerrors_hi;
1062     u32     rx_stat_dot3statscarriersenseerrors_lo;
1063     /* false_carrier_detections */
1064     u32     rx_stat_falsecarriererrors_hi;
1065     u32     rx_stat_falsecarriererrors_lo;
1066
1067     /* runt_packets_received */
1068     u32     rx_stat_etherstatsundersizepkts_hi;
1069     u32     rx_stat_etherstatsundersizepkts_lo;
1070     /* jabber_packets_received */
1071     u32     rx_stat_dot3statsframestoolong_hi;
1072     u32     rx_stat_dot3statsframestoolong_lo;
1073
1074     /* error_runt_packets_received */
1075     u32     rx_stat_etherstatsfragments_hi;
1076     u32     rx_stat_etherstatsfragments_lo;
1077     /* error_jabber_packets_received */
1078     u32     rx_stat_etherstatsjabbers_hi;
1079     u32     rx_stat_etherstatsjabbers_lo;
1080
1081     /* control_frames_received */
1082     u32     rx_stat_maccontrolframesreceived_hi;
1083     u32     rx_stat_maccontrolframesreceived_lo;
1084     u32     rx_stat_bmac_xpf_hi;
1085     u32     rx_stat_bmac_xpf_lo;
1086     u32     rx_stat_bmac_xcf_hi;
1087     u32     rx_stat_bmac_xcf_lo;
1088
1089     /* xoff_state_entered */
1090     u32     rx_stat_xoffstateentered_hi;
1091     u32     rx_stat_xoffstateentered_lo;
1092     /* pause_xon_frames_received */
1093     u32     rx_stat_xonpauseframesreceived_hi;
1094     u32     rx_stat_xonpauseframesreceived_lo;
1095     /* pause_xoff_frames_received */
1096     u32     rx_stat_xoffpauseframesreceived_hi;
1097     u32     rx_stat_xoffpauseframesreceived_lo;
1098     /* pause_xon_frames_transmitted */
1099     u32     tx_stat_outxonsent_hi;
1100     u32     tx_stat_outxonsent_lo;
1101     /* pause_xoff_frames_transmitted */
1102     u32     tx_stat_outxoffsent_hi;
1103     u32     tx_stat_outxoffsent_lo;
1104     /* flow_control_done */
1105     u32     tx_stat_flowcontroldone_hi;
1106     u32     tx_stat_flowcontroldone_lo;
1107
1108     /* ether_stats_collisions */
1109     u32     tx_stat_etherstatscollisions_hi;
1110     u32     tx_stat_etherstatscollisions_lo;
1111     /* single_collision_transmit_frames */
1112     u32     tx_stat_dot3statssinglecollisionframes_hi;
1113     u32     tx_stat_dot3statssinglecollisionframes_lo;
1114     /* multiple_collision_transmit_frames */
1115     u32     tx_stat_dot3statsmultiplecollisionframes_hi;
1116     u32     tx_stat_dot3statsmultiplecollisionframes_lo;
1117     /* deferred_transmissions */
1118     u32     tx_stat_dot3statsdeferredtransmissions_hi;
1119     u32     tx_stat_dot3statsdeferredtransmissions_lo;
1120     /* excessive_collision_frames */
1121     u32     tx_stat_dot3statsexcessivecollisions_hi;
1122     u32     tx_stat_dot3statsexcessivecollisions_lo;
1123     /* late_collision_frames */
1124     u32     tx_stat_dot3statslatecollisions_hi;
1125     u32     tx_stat_dot3statslatecollisions_lo;
1126
1127     /* frames_transmitted_64_bytes */
1128     u32     tx_stat_etherstatspkts64octets_hi;
1129     u32     tx_stat_etherstatspkts64octets_lo;
1130     /* frames_transmitted_65_127_bytes */
1131     u32     tx_stat_etherstatspkts65octetsto127octets_hi;
1132     u32     tx_stat_etherstatspkts65octetsto127octets_lo;
1133     /* frames_transmitted_128_255_bytes */
1134     u32     tx_stat_etherstatspkts128octetsto255octets_hi;
1135     u32     tx_stat_etherstatspkts128octetsto255octets_lo;
1136     /* frames_transmitted_256_511_bytes */
1137     u32     tx_stat_etherstatspkts256octetsto511octets_hi;
1138     u32     tx_stat_etherstatspkts256octetsto511octets_lo;
1139     /* frames_transmitted_512_1023_bytes */
1140     u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
1141     u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
1142     /* frames_transmitted_1024_1522_bytes */
1143     u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
1144     u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
1145     /* frames_transmitted_1523_9022_bytes */
1146     u32     tx_stat_etherstatspktsover1522octets_hi;
1147     u32     tx_stat_etherstatspktsover1522octets_lo;
1148     u32     tx_stat_bmac_2047_hi;
1149     u32     tx_stat_bmac_2047_lo;
1150     u32     tx_stat_bmac_4095_hi;
1151     u32     tx_stat_bmac_4095_lo;
1152     u32     tx_stat_bmac_9216_hi;
1153     u32     tx_stat_bmac_9216_lo;
1154     u32     tx_stat_bmac_16383_hi;
1155     u32     tx_stat_bmac_16383_lo;
1156
1157     /* internal_mac_transmit_errors */
1158     u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
1159     u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
1160
1161     /* if_out_discards */
1162     u32     tx_stat_bmac_ufl_hi;
1163     u32     tx_stat_bmac_ufl_lo;
1164 };
1165
1166
1167 #define MAC_STX_IDX_MAX                     2
1168
1169 struct host_port_stats {
1170     u32            host_port_stats_start;
1171
1172     struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1173
1174     u32            brb_drop_hi;
1175     u32            brb_drop_lo;
1176
1177     u32            host_port_stats_end;
1178 };
1179
1180
1181 struct host_func_stats {
1182     u32     host_func_stats_start;
1183
1184     u32     total_bytes_received_hi;
1185     u32     total_bytes_received_lo;
1186
1187     u32     total_bytes_transmitted_hi;
1188     u32     total_bytes_transmitted_lo;
1189
1190     u32     total_unicast_packets_received_hi;
1191     u32     total_unicast_packets_received_lo;
1192
1193     u32     total_multicast_packets_received_hi;
1194     u32     total_multicast_packets_received_lo;
1195
1196     u32     total_broadcast_packets_received_hi;
1197     u32     total_broadcast_packets_received_lo;
1198
1199     u32     total_unicast_packets_transmitted_hi;
1200     u32     total_unicast_packets_transmitted_lo;
1201
1202     u32     total_multicast_packets_transmitted_hi;
1203     u32     total_multicast_packets_transmitted_lo;
1204
1205     u32     total_broadcast_packets_transmitted_hi;
1206     u32     total_broadcast_packets_transmitted_lo;
1207
1208     u32     valid_bytes_received_hi;
1209     u32     valid_bytes_received_lo;
1210
1211     u32     host_func_stats_end;
1212 };
1213
1214
1215 #define BCM_5710_FW_MAJOR_VERSION                       4
1216 #define BCM_5710_FW_MINOR_VERSION                       8
1217 #define BCM_5710_FW_REVISION_VERSION                    53
1218 #define BCM_5710_FW_ENGINEERING_VERSION                 0
1219 #define BCM_5710_FW_COMPILE_FLAGS                       1
1220
1221
1222 /*
1223  * attention bits
1224  */
1225 struct atten_def_status_block {
1226         u32 attn_bits;
1227         u32 attn_bits_ack;
1228         u8 status_block_id;
1229         u8 reserved0;
1230         u16 attn_bits_index;
1231         u32 reserved1;
1232 };
1233
1234
1235 /*
1236  * common data for all protocols
1237  */
1238 struct doorbell_hdr {
1239         u8 header;
1240 #define DOORBELL_HDR_RX (0x1<<0)
1241 #define DOORBELL_HDR_RX_SHIFT 0
1242 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1243 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1244 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1245 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1246 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1247 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1248 };
1249
1250 /*
1251  * doorbell message sent to the chip
1252  */
1253 struct doorbell {
1254 #if defined(__BIG_ENDIAN)
1255         u16 zero_fill2;
1256         u8 zero_fill1;
1257         struct doorbell_hdr header;
1258 #elif defined(__LITTLE_ENDIAN)
1259         struct doorbell_hdr header;
1260         u8 zero_fill1;
1261         u16 zero_fill2;
1262 #endif
1263 };
1264
1265
1266 /*
1267  * IGU driver acknowledgement register
1268  */
1269 struct igu_ack_register {
1270 #if defined(__BIG_ENDIAN)
1271         u16 sb_id_and_flags;
1272 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1273 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1274 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1275 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1276 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1277 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1278 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1279 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1280 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1281 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1282         u16 status_block_index;
1283 #elif defined(__LITTLE_ENDIAN)
1284         u16 status_block_index;
1285         u16 sb_id_and_flags;
1286 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1287 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1288 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1289 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1290 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1291 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1292 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1293 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1294 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1295 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1296 #endif
1297 };
1298
1299
1300 /*
1301  * Parser parsing flags field
1302  */
1303 struct parsing_flags {
1304         u16 flags;
1305 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1306 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1307 #define PARSING_FLAGS_VLAN (0x1<<1)
1308 #define PARSING_FLAGS_VLAN_SHIFT 1
1309 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1310 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1311 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1312 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1313 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1314 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1315 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1316 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1317 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1318 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1319 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1320 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1321 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1322 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1323 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1324 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1325 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1326 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1327 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1328 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1329 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1330 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1331 };
1332
1333
1334 struct regpair {
1335         u32 lo;
1336         u32 hi;
1337 };
1338
1339
1340 /*
1341  * dmae command structure
1342  */
1343 struct dmae_command {
1344         u32 opcode;
1345 #define DMAE_COMMAND_SRC (0x1<<0)
1346 #define DMAE_COMMAND_SRC_SHIFT 0
1347 #define DMAE_COMMAND_DST (0x3<<1)
1348 #define DMAE_COMMAND_DST_SHIFT 1
1349 #define DMAE_COMMAND_C_DST (0x1<<3)
1350 #define DMAE_COMMAND_C_DST_SHIFT 3
1351 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1352 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1353 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1354 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1355 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1356 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1357 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1358 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1359 #define DMAE_COMMAND_PORT (0x1<<11)
1360 #define DMAE_COMMAND_PORT_SHIFT 11
1361 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1362 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1363 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1364 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1365 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1366 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1367 #define DMAE_COMMAND_E1HVN (0x3<<15)
1368 #define DMAE_COMMAND_E1HVN_SHIFT 15
1369 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1370 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1371         u32 src_addr_lo;
1372         u32 src_addr_hi;
1373         u32 dst_addr_lo;
1374         u32 dst_addr_hi;
1375 #if defined(__BIG_ENDIAN)
1376         u16 reserved1;
1377         u16 len;
1378 #elif defined(__LITTLE_ENDIAN)
1379         u16 len;
1380         u16 reserved1;
1381 #endif
1382         u32 comp_addr_lo;
1383         u32 comp_addr_hi;
1384         u32 comp_val;
1385         u32 crc32;
1386         u32 crc32_c;
1387 #if defined(__BIG_ENDIAN)
1388         u16 crc16_c;
1389         u16 crc16;
1390 #elif defined(__LITTLE_ENDIAN)
1391         u16 crc16;
1392         u16 crc16_c;
1393 #endif
1394 #if defined(__BIG_ENDIAN)
1395         u16 reserved2;
1396         u16 crc_t10;
1397 #elif defined(__LITTLE_ENDIAN)
1398         u16 crc_t10;
1399         u16 reserved2;
1400 #endif
1401 #if defined(__BIG_ENDIAN)
1402         u16 xsum8;
1403         u16 xsum16;
1404 #elif defined(__LITTLE_ENDIAN)
1405         u16 xsum16;
1406         u16 xsum8;
1407 #endif
1408 };
1409
1410
1411 struct double_regpair {
1412         u32 regpair0_lo;
1413         u32 regpair0_hi;
1414         u32 regpair1_lo;
1415         u32 regpair1_hi;
1416 };
1417
1418
1419 /*
1420  * The eth storm context of Ustorm (configuration part)
1421  */
1422 struct ustorm_eth_st_context_config {
1423 #if defined(__BIG_ENDIAN)
1424         u8 flags;
1425 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1426 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1427 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1428 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1429 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1430 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1431 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1432 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1433 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1434 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1435 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1436 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1437         u8 status_block_id;
1438         u8 clientId;
1439         u8 sb_index_numbers;
1440 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1441 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1442 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1443 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1444 #elif defined(__LITTLE_ENDIAN)
1445         u8 sb_index_numbers;
1446 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1447 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1448 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1449 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1450         u8 clientId;
1451         u8 status_block_id;
1452         u8 flags;
1453 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1454 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1455 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1456 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1457 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1458 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1459 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1460 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1461 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1462 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1463 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1464 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1465 #endif
1466 #if defined(__BIG_ENDIAN)
1467         u16 bd_buff_size;
1468         u8 statistics_counter_id;
1469         u8 mc_alignment_log_size;
1470 #elif defined(__LITTLE_ENDIAN)
1471         u8 mc_alignment_log_size;
1472         u8 statistics_counter_id;
1473         u16 bd_buff_size;
1474 #endif
1475 #if defined(__BIG_ENDIAN)
1476         u8 __local_sge_prod;
1477         u8 __local_bd_prod;
1478         u16 sge_buff_size;
1479 #elif defined(__LITTLE_ENDIAN)
1480         u16 sge_buff_size;
1481         u8 __local_bd_prod;
1482         u8 __local_sge_prod;
1483 #endif
1484         u32 reserved;
1485         u32 bd_page_base_lo;
1486         u32 bd_page_base_hi;
1487         u32 sge_page_base_lo;
1488         u32 sge_page_base_hi;
1489 };
1490
1491 /*
1492  * The eth Rx Buffer Descriptor
1493  */
1494 struct eth_rx_bd {
1495         u32 addr_lo;
1496         u32 addr_hi;
1497 };
1498
1499 /*
1500  * The eth Rx SGE Descriptor
1501  */
1502 struct eth_rx_sge {
1503         u32 addr_lo;
1504         u32 addr_hi;
1505 };
1506
1507 /*
1508  * Local BDs and SGEs rings (in ETH)
1509  */
1510 struct eth_local_rx_rings {
1511         struct eth_rx_bd __local_bd_ring[16];
1512         struct eth_rx_sge __local_sge_ring[12];
1513 };
1514
1515 /*
1516  * The eth storm context of Ustorm
1517  */
1518 struct ustorm_eth_st_context {
1519         struct ustorm_eth_st_context_config common;
1520         struct eth_local_rx_rings __rings;
1521 };
1522
1523 /*
1524  * The eth storm context of Tstorm
1525  */
1526 struct tstorm_eth_st_context {
1527         u32 __reserved0[28];
1528 };
1529
1530 /*
1531  * The eth aggregative context section of Xstorm
1532  */
1533 struct xstorm_eth_extra_ag_context_section {
1534 #if defined(__BIG_ENDIAN)
1535         u8 __tcp_agg_vars1;
1536         u8 __reserved50;
1537         u16 __mss;
1538 #elif defined(__LITTLE_ENDIAN)
1539         u16 __mss;
1540         u8 __reserved50;
1541         u8 __tcp_agg_vars1;
1542 #endif
1543         u32 __snd_nxt;
1544         u32 __tx_wnd;
1545         u32 __snd_una;
1546         u32 __reserved53;
1547 #if defined(__BIG_ENDIAN)
1548         u8 __agg_val8_th;
1549         u8 __agg_val8;
1550         u16 __tcp_agg_vars2;
1551 #elif defined(__LITTLE_ENDIAN)
1552         u16 __tcp_agg_vars2;
1553         u8 __agg_val8;
1554         u8 __agg_val8_th;
1555 #endif
1556         u32 __reserved58;
1557         u32 __reserved59;
1558         u32 __reserved60;
1559         u32 __reserved61;
1560 #if defined(__BIG_ENDIAN)
1561         u16 __agg_val7_th;
1562         u16 __agg_val7;
1563 #elif defined(__LITTLE_ENDIAN)
1564         u16 __agg_val7;
1565         u16 __agg_val7_th;
1566 #endif
1567 #if defined(__BIG_ENDIAN)
1568         u8 __tcp_agg_vars5;
1569         u8 __tcp_agg_vars4;
1570         u8 __tcp_agg_vars3;
1571         u8 __reserved62;
1572 #elif defined(__LITTLE_ENDIAN)
1573         u8 __reserved62;
1574         u8 __tcp_agg_vars3;
1575         u8 __tcp_agg_vars4;
1576         u8 __tcp_agg_vars5;
1577 #endif
1578         u32 __tcp_agg_vars6;
1579 #if defined(__BIG_ENDIAN)
1580         u16 __agg_misc6;
1581         u16 __tcp_agg_vars7;
1582 #elif defined(__LITTLE_ENDIAN)
1583         u16 __tcp_agg_vars7;
1584         u16 __agg_misc6;
1585 #endif
1586         u32 __agg_val10;
1587         u32 __agg_val10_th;
1588 #if defined(__BIG_ENDIAN)
1589         u16 __reserved3;
1590         u8 __reserved2;
1591         u8 __da_only_cnt;
1592 #elif defined(__LITTLE_ENDIAN)
1593         u8 __da_only_cnt;
1594         u8 __reserved2;
1595         u16 __reserved3;
1596 #endif
1597 };
1598
1599 /*
1600  * The eth aggregative context of Xstorm
1601  */
1602 struct xstorm_eth_ag_context {
1603 #if defined(__BIG_ENDIAN)
1604         u16 __bd_prod;
1605         u8 __agg_vars1;
1606         u8 __state;
1607 #elif defined(__LITTLE_ENDIAN)
1608         u8 __state;
1609         u8 __agg_vars1;
1610         u16 __bd_prod;
1611 #endif
1612 #if defined(__BIG_ENDIAN)
1613         u8 cdu_reserved;
1614         u8 __agg_vars4;
1615         u8 __agg_vars3;
1616         u8 __agg_vars2;
1617 #elif defined(__LITTLE_ENDIAN)
1618         u8 __agg_vars2;
1619         u8 __agg_vars3;
1620         u8 __agg_vars4;
1621         u8 cdu_reserved;
1622 #endif
1623         u32 __more_packets_to_send;
1624 #if defined(__BIG_ENDIAN)
1625         u16 __agg_vars5;
1626         u16 __agg_val4_th;
1627 #elif defined(__LITTLE_ENDIAN)
1628         u16 __agg_val4_th;
1629         u16 __agg_vars5;
1630 #endif
1631         struct xstorm_eth_extra_ag_context_section __extra_section;
1632 #if defined(__BIG_ENDIAN)
1633         u16 __agg_vars7;
1634         u8 __agg_val3_th;
1635         u8 __agg_vars6;
1636 #elif defined(__LITTLE_ENDIAN)
1637         u8 __agg_vars6;
1638         u8 __agg_val3_th;
1639         u16 __agg_vars7;
1640 #endif
1641 #if defined(__BIG_ENDIAN)
1642         u16 __agg_val11_th;
1643         u16 __agg_val11;
1644 #elif defined(__LITTLE_ENDIAN)
1645         u16 __agg_val11;
1646         u16 __agg_val11_th;
1647 #endif
1648 #if defined(__BIG_ENDIAN)
1649         u8 __reserved1;
1650         u8 __agg_val6_th;
1651         u16 __agg_val9;
1652 #elif defined(__LITTLE_ENDIAN)
1653         u16 __agg_val9;
1654         u8 __agg_val6_th;
1655         u8 __reserved1;
1656 #endif
1657 #if defined(__BIG_ENDIAN)
1658         u16 __agg_val2_th;
1659         u16 __agg_val2;
1660 #elif defined(__LITTLE_ENDIAN)
1661         u16 __agg_val2;
1662         u16 __agg_val2_th;
1663 #endif
1664         u32 __agg_vars8;
1665 #if defined(__BIG_ENDIAN)
1666         u16 __agg_misc0;
1667         u16 __agg_val4;
1668 #elif defined(__LITTLE_ENDIAN)
1669         u16 __agg_val4;
1670         u16 __agg_misc0;
1671 #endif
1672 #if defined(__BIG_ENDIAN)
1673         u8 __agg_val3;
1674         u8 __agg_val6;
1675         u8 __agg_val5_th;
1676         u8 __agg_val5;
1677 #elif defined(__LITTLE_ENDIAN)
1678         u8 __agg_val5;
1679         u8 __agg_val5_th;
1680         u8 __agg_val6;
1681         u8 __agg_val3;
1682 #endif
1683 #if defined(__BIG_ENDIAN)
1684         u16 __agg_misc1;
1685         u16 __bd_ind_max_val;
1686 #elif defined(__LITTLE_ENDIAN)
1687         u16 __bd_ind_max_val;
1688         u16 __agg_misc1;
1689 #endif
1690         u32 __reserved57;
1691         u32 __agg_misc4;
1692         u32 __agg_misc5;
1693 };
1694
1695 /*
1696  * The eth aggregative context section of Tstorm
1697  */
1698 struct tstorm_eth_extra_ag_context_section {
1699         u32 __agg_val1;
1700 #if defined(__BIG_ENDIAN)
1701         u8 __tcp_agg_vars2;
1702         u8 __agg_val3;
1703         u16 __agg_val2;
1704 #elif defined(__LITTLE_ENDIAN)
1705         u16 __agg_val2;
1706         u8 __agg_val3;
1707         u8 __tcp_agg_vars2;
1708 #endif
1709 #if defined(__BIG_ENDIAN)
1710         u16 __agg_val5;
1711         u8 __agg_val6;
1712         u8 __tcp_agg_vars3;
1713 #elif defined(__LITTLE_ENDIAN)
1714         u8 __tcp_agg_vars3;
1715         u8 __agg_val6;
1716         u16 __agg_val5;
1717 #endif
1718         u32 __reserved63;
1719         u32 __reserved64;
1720         u32 __reserved65;
1721         u32 __reserved66;
1722         u32 __reserved67;
1723         u32 __tcp_agg_vars1;
1724         u32 __reserved61;
1725         u32 __reserved62;
1726         u32 __reserved2;
1727 };
1728
1729 /*
1730  * The eth aggregative context of Tstorm
1731  */
1732 struct tstorm_eth_ag_context {
1733 #if defined(__BIG_ENDIAN)
1734         u16 __reserved54;
1735         u8 __agg_vars1;
1736         u8 __state;
1737 #elif defined(__LITTLE_ENDIAN)
1738         u8 __state;
1739         u8 __agg_vars1;
1740         u16 __reserved54;
1741 #endif
1742 #if defined(__BIG_ENDIAN)
1743         u16 __agg_val4;
1744         u16 __agg_vars2;
1745 #elif defined(__LITTLE_ENDIAN)
1746         u16 __agg_vars2;
1747         u16 __agg_val4;
1748 #endif
1749         struct tstorm_eth_extra_ag_context_section __extra_section;
1750 };
1751
1752 /*
1753  * The eth aggregative context of Cstorm
1754  */
1755 struct cstorm_eth_ag_context {
1756         u32 __agg_vars1;
1757 #if defined(__BIG_ENDIAN)
1758         u8 __aux1_th;
1759         u8 __aux1_val;
1760         u16 __agg_vars2;
1761 #elif defined(__LITTLE_ENDIAN)
1762         u16 __agg_vars2;
1763         u8 __aux1_val;
1764         u8 __aux1_th;
1765 #endif
1766         u32 __num_of_treated_packet;
1767         u32 __last_packet_treated;
1768 #if defined(__BIG_ENDIAN)
1769         u16 __reserved58;
1770         u16 __reserved57;
1771 #elif defined(__LITTLE_ENDIAN)
1772         u16 __reserved57;
1773         u16 __reserved58;
1774 #endif
1775 #if defined(__BIG_ENDIAN)
1776         u8 __reserved62;
1777         u8 __reserved61;
1778         u8 __reserved60;
1779         u8 __reserved59;
1780 #elif defined(__LITTLE_ENDIAN)
1781         u8 __reserved59;
1782         u8 __reserved60;
1783         u8 __reserved61;
1784         u8 __reserved62;
1785 #endif
1786 #if defined(__BIG_ENDIAN)
1787         u16 __reserved64;
1788         u16 __reserved63;
1789 #elif defined(__LITTLE_ENDIAN)
1790         u16 __reserved63;
1791         u16 __reserved64;
1792 #endif
1793         u32 __reserved65;
1794 #if defined(__BIG_ENDIAN)
1795         u16 __agg_vars3;
1796         u16 __rq_inv_cnt;
1797 #elif defined(__LITTLE_ENDIAN)
1798         u16 __rq_inv_cnt;
1799         u16 __agg_vars3;
1800 #endif
1801 #if defined(__BIG_ENDIAN)
1802         u16 __packet_index_th;
1803         u16 __packet_index;
1804 #elif defined(__LITTLE_ENDIAN)
1805         u16 __packet_index;
1806         u16 __packet_index_th;
1807 #endif
1808 };
1809
1810 /*
1811  * The eth aggregative context of Ustorm
1812  */
1813 struct ustorm_eth_ag_context {
1814 #if defined(__BIG_ENDIAN)
1815         u8 __aux_counter_flags;
1816         u8 __agg_vars2;
1817         u8 __agg_vars1;
1818         u8 __state;
1819 #elif defined(__LITTLE_ENDIAN)
1820         u8 __state;
1821         u8 __agg_vars1;
1822         u8 __agg_vars2;
1823         u8 __aux_counter_flags;
1824 #endif
1825 #if defined(__BIG_ENDIAN)
1826         u8 cdu_usage;
1827         u8 __agg_misc2;
1828         u16 __agg_misc1;
1829 #elif defined(__LITTLE_ENDIAN)
1830         u16 __agg_misc1;
1831         u8 __agg_misc2;
1832         u8 cdu_usage;
1833 #endif
1834         u32 __agg_misc4;
1835 #if defined(__BIG_ENDIAN)
1836         u8 __agg_val3_th;
1837         u8 __agg_val3;
1838         u16 __agg_misc3;
1839 #elif defined(__LITTLE_ENDIAN)
1840         u16 __agg_misc3;
1841         u8 __agg_val3;
1842         u8 __agg_val3_th;
1843 #endif
1844         u32 __agg_val1;
1845         u32 __agg_misc4_th;
1846 #if defined(__BIG_ENDIAN)
1847         u16 __agg_val2_th;
1848         u16 __agg_val2;
1849 #elif defined(__LITTLE_ENDIAN)
1850         u16 __agg_val2;
1851         u16 __agg_val2_th;
1852 #endif
1853 #if defined(__BIG_ENDIAN)
1854         u16 __reserved2;
1855         u8 __decision_rules;
1856         u8 __decision_rule_enable_bits;
1857 #elif defined(__LITTLE_ENDIAN)
1858         u8 __decision_rule_enable_bits;
1859         u8 __decision_rules;
1860         u16 __reserved2;
1861 #endif
1862 };
1863
1864 /*
1865  * Timers connection context
1866  */
1867 struct timers_block_context {
1868         u32 __reserved_0;
1869         u32 __reserved_1;
1870         u32 __reserved_2;
1871         u32 flags;
1872 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1873 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1874 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1875 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1876 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1877 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1878 };
1879
1880 /*
1881  * structure for easy accessibility to assembler
1882  */
1883 struct eth_tx_bd_flags {
1884         u8 as_bitfield;
1885 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1886 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1887 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1888 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1889 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1890 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1891 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1892 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1893 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1894 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1895 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1896 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1897 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1898 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1899 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1900 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1901 };
1902
1903 /*
1904  * The eth Tx Buffer Descriptor
1905  */
1906 struct eth_tx_bd {
1907         u32 addr_lo;
1908         u32 addr_hi;
1909         u16 nbd;
1910         u16 nbytes;
1911         u16 vlan;
1912         struct eth_tx_bd_flags bd_flags;
1913         u8 general_data;
1914 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1915 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1916 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1917 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1918 };
1919
1920 /*
1921  * Tx parsing BD structure for ETH,Relevant in START
1922  */
1923 struct eth_tx_parse_bd {
1924         u8 global_data;
1925 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1926 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1927 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1928 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1929 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1930 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1931 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1932 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1933 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1934 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1935         u8 tcp_flags;
1936 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1937 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1938 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1939 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1940 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1941 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1942 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1943 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1944 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1945 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1946 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1947 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1948 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1949 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1950 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1951 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1952         u8 ip_hlen;
1953         s8 cs_offset;
1954         u16 total_hlen;
1955         u16 lso_mss;
1956         u16 tcp_pseudo_csum;
1957         u16 ip_id;
1958         u32 tcp_send_seq;
1959 };
1960
1961 /*
1962  * The last BD in the BD memory will hold a pointer to the next BD memory
1963  */
1964 struct eth_tx_next_bd {
1965         u32 addr_lo;
1966         u32 addr_hi;
1967         u8 reserved[8];
1968 };
1969
1970 /*
1971  * union for 3 Bd types
1972  */
1973 union eth_tx_bd_types {
1974         struct eth_tx_bd reg_bd;
1975         struct eth_tx_parse_bd parse_bd;
1976         struct eth_tx_next_bd next_bd;
1977 };
1978
1979 /*
1980  * The eth storm context of Xstorm
1981  */
1982 struct xstorm_eth_st_context {
1983         u32 tx_bd_page_base_lo;
1984         u32 tx_bd_page_base_hi;
1985 #if defined(__BIG_ENDIAN)
1986         u16 tx_bd_cons;
1987         u8 statistics_data;
1988 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1989 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1990 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1991 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1992         u8 __local_tx_bd_prod;
1993 #elif defined(__LITTLE_ENDIAN)
1994         u8 __local_tx_bd_prod;
1995         u8 statistics_data;
1996 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1997 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1998 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1999 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
2000         u16 tx_bd_cons;
2001 #endif
2002         u32 db_data_addr_lo;
2003         u32 db_data_addr_hi;
2004         u32 __pkt_cons;
2005         u32 __gso_next;
2006         u32 is_eth_conn_1b;
2007         union eth_tx_bd_types __bds[13];
2008 };
2009
2010 /*
2011  * The eth storm context of Cstorm
2012  */
2013 struct cstorm_eth_st_context {
2014 #if defined(__BIG_ENDIAN)
2015         u16 __reserved0;
2016         u8 sb_index_number;
2017         u8 status_block_id;
2018 #elif defined(__LITTLE_ENDIAN)
2019         u8 status_block_id;
2020         u8 sb_index_number;
2021         u16 __reserved0;
2022 #endif
2023         u32 __reserved1[3];
2024 };
2025
2026 /*
2027  * Ethernet connection context
2028  */
2029 struct eth_context {
2030         struct ustorm_eth_st_context ustorm_st_context;
2031         struct tstorm_eth_st_context tstorm_st_context;
2032         struct xstorm_eth_ag_context xstorm_ag_context;
2033         struct tstorm_eth_ag_context tstorm_ag_context;
2034         struct cstorm_eth_ag_context cstorm_ag_context;
2035         struct ustorm_eth_ag_context ustorm_ag_context;
2036         struct timers_block_context timers_context;
2037         struct xstorm_eth_st_context xstorm_st_context;
2038         struct cstorm_eth_st_context cstorm_st_context;
2039 };
2040
2041
2042 /*
2043  * Ethernet doorbell
2044  */
2045 struct eth_tx_doorbell {
2046 #if defined(__BIG_ENDIAN)
2047         u16 npackets;
2048         u8 params;
2049 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2050 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2051 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2052 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2053 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2054 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2055         struct doorbell_hdr hdr;
2056 #elif defined(__LITTLE_ENDIAN)
2057         struct doorbell_hdr hdr;
2058         u8 params;
2059 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2060 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2061 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2062 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2063 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2064 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2065         u16 npackets;
2066 #endif
2067 };
2068
2069
2070 /*
2071  * ustorm status block
2072  */
2073 struct ustorm_def_status_block {
2074         u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2075         u16 status_block_index;
2076         u8 func;
2077         u8 status_block_id;
2078         u32 __flags;
2079 };
2080
2081 /*
2082  * cstorm status block
2083  */
2084 struct cstorm_def_status_block {
2085         u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2086         u16 status_block_index;
2087         u8 func;
2088         u8 status_block_id;
2089         u32 __flags;
2090 };
2091
2092 /*
2093  * xstorm status block
2094  */
2095 struct xstorm_def_status_block {
2096         u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2097         u16 status_block_index;
2098         u8 func;
2099         u8 status_block_id;
2100         u32 __flags;
2101 };
2102
2103 /*
2104  * tstorm status block
2105  */
2106 struct tstorm_def_status_block {
2107         u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2108         u16 status_block_index;
2109         u8 func;
2110         u8 status_block_id;
2111         u32 __flags;
2112 };
2113
2114 /*
2115  * host status block
2116  */
2117 struct host_def_status_block {
2118         struct atten_def_status_block atten_status_block;
2119         struct ustorm_def_status_block u_def_status_block;
2120         struct cstorm_def_status_block c_def_status_block;
2121         struct xstorm_def_status_block x_def_status_block;
2122         struct tstorm_def_status_block t_def_status_block;
2123 };
2124
2125
2126 /*
2127  * ustorm status block
2128  */
2129 struct ustorm_status_block {
2130         u16 index_values[HC_USTORM_SB_NUM_INDICES];
2131         u16 status_block_index;
2132         u8 func;
2133         u8 status_block_id;
2134         u32 __flags;
2135 };
2136
2137 /*
2138  * cstorm status block
2139  */
2140 struct cstorm_status_block {
2141         u16 index_values[HC_CSTORM_SB_NUM_INDICES];
2142         u16 status_block_index;
2143         u8 func;
2144         u8 status_block_id;
2145         u32 __flags;
2146 };
2147
2148 /*
2149  * host status block
2150  */
2151 struct host_status_block {
2152         struct ustorm_status_block u_status_block;
2153         struct cstorm_status_block c_status_block;
2154 };
2155
2156
2157 /*
2158  * The data for RSS setup ramrod
2159  */
2160 struct eth_client_setup_ramrod_data {
2161         u32 client_id;
2162         u8 is_rdma;
2163         u8 is_fcoe;
2164         u16 reserved1;
2165 };
2166
2167
2168 /*
2169  * L2 dynamic host coalescing init parameters
2170  */
2171 struct eth_dynamic_hc_config {
2172         u32 threshold[3];
2173         u8 hc_timeout[4];
2174 };
2175
2176
2177 /*
2178  * regular eth FP CQE parameters struct
2179  */
2180 struct eth_fast_path_rx_cqe {
2181         u8 type_error_flags;
2182 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2183 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2184 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2185 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2186 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2187 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2188 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2189 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2190 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2191 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2192 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2193 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2194 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2195 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2196         u8 status_flags;
2197 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2198 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2199 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2200 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2201 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2202 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2203 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2204 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2205 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2206 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2207 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2208 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2209         u8 placement_offset;
2210         u8 queue_index;
2211         u32 rss_hash_result;
2212         u16 vlan_tag;
2213         u16 pkt_len;
2214         u16 len_on_bd;
2215         struct parsing_flags pars_flags;
2216         u16 sgl[8];
2217 };
2218
2219
2220 /*
2221  * The data for RSS setup ramrod
2222  */
2223 struct eth_halt_ramrod_data {
2224         u32 client_id;
2225         u32 reserved0;
2226 };
2227
2228
2229 /*
2230  * The data for statistics query ramrod
2231  */
2232 struct eth_query_ramrod_data {
2233 #if defined(__BIG_ENDIAN)
2234         u8 reserved0;
2235         u8 collect_port;
2236         u16 drv_counter;
2237 #elif defined(__LITTLE_ENDIAN)
2238         u16 drv_counter;
2239         u8 collect_port;
2240         u8 reserved0;
2241 #endif
2242         u32 ctr_id_vector;
2243 };
2244
2245
2246 /*
2247  * Place holder for ramrods protocol specific data
2248  */
2249 struct ramrod_data {
2250         u32 data_lo;
2251         u32 data_hi;
2252 };
2253
2254 /*
2255  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2256  */
2257 union eth_ramrod_data {
2258         struct ramrod_data general;
2259 };
2260
2261
2262 /*
2263  * Rx Last BD in page (in ETH)
2264  */
2265 struct eth_rx_bd_next_page {
2266         u32 addr_lo;
2267         u32 addr_hi;
2268         u8 reserved[8];
2269 };
2270
2271
2272 /*
2273  * Eth Rx Cqe structure- general structure for ramrods
2274  */
2275 struct common_ramrod_eth_rx_cqe {
2276         u8 ramrod_type;
2277 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2278 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2279 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2280 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
2281         u8 conn_type;
2282         u16 reserved1;
2283         u32 conn_and_cmd_data;
2284 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2285 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2286 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2287 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2288         struct ramrod_data protocol_data;
2289         u32 reserved2[4];
2290 };
2291
2292 /*
2293  * Rx Last CQE in page (in ETH)
2294  */
2295 struct eth_rx_cqe_next_page {
2296         u32 addr_lo;
2297         u32 addr_hi;
2298         u32 reserved[6];
2299 };
2300
2301 /*
2302  * union for all eth rx cqe types (fix their sizes)
2303  */
2304 union eth_rx_cqe {
2305         struct eth_fast_path_rx_cqe fast_path_cqe;
2306         struct common_ramrod_eth_rx_cqe ramrod_cqe;
2307         struct eth_rx_cqe_next_page next_page_cqe;
2308 };
2309
2310
2311 /*
2312  * common data for all protocols
2313  */
2314 struct spe_hdr {
2315         u32 conn_and_cmd_data;
2316 #define SPE_HDR_CID (0xFFFFFF<<0)
2317 #define SPE_HDR_CID_SHIFT 0
2318 #define SPE_HDR_CMD_ID (0xFF<<24)
2319 #define SPE_HDR_CMD_ID_SHIFT 24
2320         u16 type;
2321 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2322 #define SPE_HDR_CONN_TYPE_SHIFT 0
2323 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2324 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2325         u16 reserved;
2326 };
2327
2328 /*
2329  * Ethernet slow path element
2330  */
2331 union eth_specific_data {
2332         u8 protocol_data[8];
2333         struct regpair mac_config_addr;
2334         struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2335         struct eth_halt_ramrod_data halt_ramrod_data;
2336         struct regpair leading_cqe_addr;
2337         struct regpair update_data_addr;
2338         struct eth_query_ramrod_data query_ramrod_data;
2339 };
2340
2341 /*
2342  * Ethernet slow path element
2343  */
2344 struct eth_spe {
2345         struct spe_hdr hdr;
2346         union eth_specific_data data;
2347 };
2348
2349
2350 /*
2351  * doorbell data in host memory
2352  */
2353 struct eth_tx_db_data {
2354         u32 packets_prod;
2355         u16 bds_prod;
2356         u16 reserved;
2357 };
2358
2359
2360 /*
2361  * Common configuration parameters per function in Tstorm
2362  */
2363 struct tstorm_eth_function_common_config {
2364 #if defined(__BIG_ENDIAN)
2365         u8 leading_client_id;
2366         u8 rss_result_mask;
2367         u16 config_flags;
2368 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2369 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2370 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2371 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2372 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2373 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2374 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2375 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2376 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2377 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2378 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2379 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2380 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2381 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2382 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2383 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2384 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2385 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2386 #elif defined(__LITTLE_ENDIAN)
2387         u16 config_flags;
2388 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2389 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2390 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2391 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2392 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2393 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2394 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2395 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2396 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2397 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2398 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2399 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2400 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2401 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2402 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2403 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2404 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2405 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2406         u8 rss_result_mask;
2407         u8 leading_client_id;
2408 #endif
2409         u16 vlan_id[2];
2410 };
2411
2412 /*
2413  * parameters for eth update ramrod
2414  */
2415 struct eth_update_ramrod_data {
2416         struct tstorm_eth_function_common_config func_config;
2417         u8 indirectionTable[128];
2418 };
2419
2420
2421 /*
2422  * MAC filtering configuration command header
2423  */
2424 struct mac_configuration_hdr {
2425         u8 length;
2426         u8 offset;
2427         u16 client_id;
2428         u32 reserved1;
2429 };
2430
2431 /*
2432  * MAC address in list for ramrod
2433  */
2434 struct tstorm_cam_entry {
2435         u16 lsb_mac_addr;
2436         u16 middle_mac_addr;
2437         u16 msb_mac_addr;
2438         u16 flags;
2439 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2440 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2441 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2442 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2443 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2444 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2445 };
2446
2447 /*
2448  * MAC filtering: CAM target table entry
2449  */
2450 struct tstorm_cam_target_table_entry {
2451         u8 flags;
2452 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2453 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2454 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2455 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2456 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2457 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2458 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2459 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2460 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2461 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2462         u8 client_id;
2463         u16 vlan_id;
2464 };
2465
2466 /*
2467  * MAC address in list for ramrod
2468  */
2469 struct mac_configuration_entry {
2470         struct tstorm_cam_entry cam_entry;
2471         struct tstorm_cam_target_table_entry target_table_entry;
2472 };
2473
2474 /*
2475  * MAC filtering configuration command
2476  */
2477 struct mac_configuration_cmd {
2478         struct mac_configuration_hdr hdr;
2479         struct mac_configuration_entry config_table[64];
2480 };
2481
2482
2483 /*
2484  * MAC address in list for ramrod
2485  */
2486 struct mac_configuration_entry_e1h {
2487         u16 lsb_mac_addr;
2488         u16 middle_mac_addr;
2489         u16 msb_mac_addr;
2490         u16 vlan_id;
2491         u16 e1hov_id;
2492         u8 client_id;
2493         u8 flags;
2494 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2495 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2496 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2497 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2498 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2499 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2500 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2501 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2502 };
2503
2504 /*
2505  * MAC filtering configuration command
2506  */
2507 struct mac_configuration_cmd_e1h {
2508         struct mac_configuration_hdr hdr;
2509         struct mac_configuration_entry_e1h config_table[32];
2510 };
2511
2512
2513 /*
2514  * approximate-match multicast filtering for E1H per function in Tstorm
2515  */
2516 struct tstorm_eth_approximate_match_multicast_filtering {
2517         u32 mcast_add_hash_bit_array[8];
2518 };
2519
2520
2521 /*
2522  * Configuration parameters per client in Tstorm
2523  */
2524 struct tstorm_eth_client_config {
2525 #if defined(__BIG_ENDIAN)
2526         u8 max_sges_for_packet;
2527         u8 statistics_counter_id;
2528         u16 mtu;
2529 #elif defined(__LITTLE_ENDIAN)
2530         u16 mtu;
2531         u8 statistics_counter_id;
2532         u8 max_sges_for_packet;
2533 #endif
2534 #if defined(__BIG_ENDIAN)
2535         u16 drop_flags;
2536 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2537 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2538 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2539 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2540 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2541 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2542 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2543 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2544 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2545 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2546         u16 config_flags;
2547 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2548 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2549 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2550 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2551 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2552 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2553 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2554 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2555 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2556 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2557 #elif defined(__LITTLE_ENDIAN)
2558         u16 config_flags;
2559 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2560 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2561 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2562 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2563 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2564 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2565 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2566 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2567 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2568 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2569         u16 drop_flags;
2570 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2571 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2572 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2573 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2574 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2575 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2576 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2577 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2578 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2579 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2580 #endif
2581 };
2582
2583
2584 /*
2585  * MAC filtering configuration parameters per port in Tstorm
2586  */
2587 struct tstorm_eth_mac_filter_config {
2588         u32 ucast_drop_all;
2589         u32 ucast_accept_all;
2590         u32 mcast_drop_all;
2591         u32 mcast_accept_all;
2592         u32 bcast_drop_all;
2593         u32 bcast_accept_all;
2594         u32 strict_vlan;
2595         u32 vlan_filter[2];
2596         u32 reserved;
2597 };
2598
2599
2600 /*
2601  * common flag to indicate existance of TPA.
2602  */
2603 struct tstorm_eth_tpa_exist {
2604 #if defined(__BIG_ENDIAN)
2605         u16 reserved1;
2606         u8 reserved0;
2607         u8 tpa_exist;
2608 #elif defined(__LITTLE_ENDIAN)
2609         u8 tpa_exist;
2610         u8 reserved0;
2611         u16 reserved1;
2612 #endif
2613         u32 reserved2;
2614 };
2615
2616
2617 /*
2618  * Three RX producers for ETH
2619  */
2620 struct ustorm_eth_rx_producers {
2621 #if defined(__BIG_ENDIAN)
2622         u16 bd_prod;
2623         u16 cqe_prod;
2624 #elif defined(__LITTLE_ENDIAN)
2625         u16 cqe_prod;
2626         u16 bd_prod;
2627 #endif
2628 #if defined(__BIG_ENDIAN)
2629         u16 reserved;
2630         u16 sge_prod;
2631 #elif defined(__LITTLE_ENDIAN)
2632         u16 sge_prod;
2633         u16 reserved;
2634 #endif
2635 };
2636
2637
2638 /*
2639  * per-port SAFC demo variables
2640  */
2641 struct cmng_flags_per_port {
2642         u8 con_number[NUM_OF_PROTOCOLS];
2643 #if defined(__BIG_ENDIAN)
2644         u8 fairness_enable;
2645         u8 rate_shaping_enable;
2646         u8 cmng_protocol_enable;
2647         u8 cmng_vn_enable;
2648 #elif defined(__LITTLE_ENDIAN)
2649         u8 cmng_vn_enable;
2650         u8 cmng_protocol_enable;
2651         u8 rate_shaping_enable;
2652         u8 fairness_enable;
2653 #endif
2654 };
2655
2656
2657 /*
2658  * per-port rate shaping variables
2659  */
2660 struct rate_shaping_vars_per_port {
2661         u32 rs_periodic_timeout;
2662         u32 rs_threshold;
2663 };
2664
2665
2666 /*
2667  * per-port fairness variables
2668  */
2669 struct fairness_vars_per_port {
2670         u32 upper_bound;
2671         u32 fair_threshold;
2672         u32 fairness_timeout;
2673 };
2674
2675
2676 /*
2677  * per-port SAFC variables
2678  */
2679 struct safc_struct_per_port {
2680 #if defined(__BIG_ENDIAN)
2681         u16 __reserved1;
2682         u8 __reserved0;
2683         u8 safc_timeout_usec;
2684 #elif defined(__LITTLE_ENDIAN)
2685         u8 safc_timeout_usec;
2686         u8 __reserved0;
2687         u16 __reserved1;
2688 #endif
2689         u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2690 };
2691
2692
2693 /*
2694  * Per-port congestion management variables
2695  */
2696 struct cmng_struct_per_port {
2697         struct rate_shaping_vars_per_port rs_vars;
2698         struct fairness_vars_per_port fair_vars;
2699         struct safc_struct_per_port safc_vars;
2700         struct cmng_flags_per_port flags;
2701 };
2702
2703
2704 /*
2705  * Protocol-common statistics collected by the Xstorm (per client)
2706  */
2707 struct xstorm_per_client_stats {
2708         struct regpair total_sent_bytes;
2709         u32 total_sent_pkts;
2710         u32 unicast_pkts_sent;
2711         struct regpair unicast_bytes_sent;
2712         struct regpair multicast_bytes_sent;
2713         u32 multicast_pkts_sent;
2714         u32 broadcast_pkts_sent;
2715         struct regpair broadcast_bytes_sent;
2716         u16 stats_counter;
2717         u16 reserved0;
2718         u32 reserved1;
2719 };
2720
2721
2722 /*
2723  * Common statistics collected by the Xstorm (per port)
2724  */
2725 struct xstorm_common_stats {
2726  struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2727 };
2728
2729
2730 /*
2731  * Protocol-common statistics collected by the Tstorm (per port)
2732  */
2733 struct tstorm_per_port_stats {
2734         u32 mac_filter_discard;
2735         u32 xxoverflow_discard;
2736         u32 brb_truncate_discard;
2737         u32 mac_discard;
2738 };
2739
2740
2741 /*
2742  * Protocol-common statistics collected by the Tstorm (per client)
2743  */
2744 struct tstorm_per_client_stats {
2745         struct regpair total_rcv_bytes;
2746         struct regpair rcv_unicast_bytes;
2747         struct regpair rcv_broadcast_bytes;
2748         struct regpair rcv_multicast_bytes;
2749         struct regpair rcv_error_bytes;
2750         u32 checksum_discard;
2751         u32 packets_too_big_discard;
2752         u32 total_rcv_pkts;
2753         u32 rcv_unicast_pkts;
2754         u32 rcv_broadcast_pkts;
2755         u32 rcv_multicast_pkts;
2756         u32 no_buff_discard;
2757         u32 ttl0_discard;
2758         u16 stats_counter;
2759         u16 reserved0;
2760         u32 reserved1;
2761 };
2762
2763 /*
2764  * Protocol-common statistics collected by the Tstorm
2765  */
2766 struct tstorm_common_stats {
2767         struct tstorm_per_port_stats port_statistics;
2768  struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2769 };
2770
2771 /*
2772  * Protocol-common statistics collected by the Ustorm (per client)
2773  */
2774 struct ustorm_per_client_stats {
2775         struct regpair ucast_no_buff_bytes;
2776         struct regpair mcast_no_buff_bytes;
2777         struct regpair bcast_no_buff_bytes;
2778         __le32 ucast_no_buff_pkts;
2779         __le32 mcast_no_buff_pkts;
2780         __le32 bcast_no_buff_pkts;
2781         __le16 stats_counter;
2782         __le16 reserved0;
2783 };
2784
2785 /*
2786  * Protocol-common statistics collected by the Ustorm
2787  */
2788 struct ustorm_common_stats {
2789  struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
2790 };
2791
2792 /*
2793  * Eth statistics query structure for the eth_stats_query ramrod
2794  */
2795 struct eth_stats_query {
2796         struct xstorm_common_stats xstorm_common;
2797         struct tstorm_common_stats tstorm_common;
2798         struct ustorm_common_stats ustorm_common;
2799 };
2800
2801
2802 /*
2803  * per-vnic fairness variables
2804  */
2805 struct fairness_vars_per_vn {
2806         u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2807         u32 vn_credit_delta;
2808         u32 __reserved0;
2809 };
2810
2811
2812 /*
2813  * FW version stored in the Xstorm RAM
2814  */
2815 struct fw_version {
2816 #if defined(__BIG_ENDIAN)
2817         u8 engineering;
2818         u8 revision;
2819         u8 minor;
2820         u8 major;
2821 #elif defined(__LITTLE_ENDIAN)
2822         u8 major;
2823         u8 minor;
2824         u8 revision;
2825         u8 engineering;
2826 #endif
2827         u32 flags;
2828 #define FW_VERSION_OPTIMIZED (0x1<<0)
2829 #define FW_VERSION_OPTIMIZED_SHIFT 0
2830 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2831 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2832 #define FW_VERSION_CHIP_VERSION (0x3<<2)
2833 #define FW_VERSION_CHIP_VERSION_SHIFT 2
2834 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2835 #define __FW_VERSION_RESERVED_SHIFT 4
2836 };
2837
2838
2839 /*
2840  * FW version stored in first line of pram
2841  */
2842 struct pram_fw_version {
2843         u8 major;
2844         u8 minor;
2845         u8 revision;
2846         u8 engineering;
2847         u8 flags;
2848 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2849 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2850 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2851 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2852 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2853 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2854 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2855 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2856 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2857 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2858 };
2859
2860
2861 /*
2862  * a single rate shaping counter. can be used as protocol or vnic counter
2863  */
2864 struct rate_shaping_counter {
2865         u32 quota;
2866 #if defined(__BIG_ENDIAN)
2867         u16 __reserved0;
2868         u16 rate;
2869 #elif defined(__LITTLE_ENDIAN)
2870         u16 rate;
2871         u16 __reserved0;
2872 #endif
2873 };
2874
2875
2876 /*
2877  * per-vnic rate shaping variables
2878  */
2879 struct rate_shaping_vars_per_vn {
2880         struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2881         struct rate_shaping_counter vn_counter;
2882 };
2883
2884
2885 /*
2886  * The send queue element
2887  */
2888 struct slow_path_element {
2889         struct spe_hdr hdr;
2890         u8 protocol_data[8];
2891 };
2892
2893
2894 /*
2895  * eth/toe flags that indicate if to query
2896  */
2897 struct stats_indication_flags {
2898         u32 collect_eth;
2899         u32 collect_toe;
2900 };
2901
2902