clocksource: improve sh_cmt clocksource overflow handling
[linux-2.6.git] / drivers / net / bnx2x_hsi.h
1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2009 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9
10
11 #define PORT_0                          0
12 #define PORT_1                          1
13 #define PORT_MAX                        2
14
15 /****************************************************************************
16  * Shared HW configuration                                                  *
17  ****************************************************************************/
18 struct shared_hw_cfg {                                   /* NVRAM Offset */
19         /* Up to 16 bytes of NULL-terminated string */
20         u8  part_num[16];                                       /* 0x104 */
21
22         u32 config;                                             /* 0x114 */
23 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
24 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT            0
25 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V             0x00000000
26 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V             0x00000001
27 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
28
29 #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
30
31 #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
32
33 #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
34 #define SHARED_HW_CFG_MFW_SELECT_SHIFT              8
35         /* Whatever MFW found in NVM
36            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT            0x00000000
38 #define SHARED_HW_CFG_MFW_SELECT_NC_SI              0x00000100
39 #define SHARED_HW_CFG_MFW_SELECT_UMP                0x00000200
40 #define SHARED_HW_CFG_MFW_SELECT_IPMI               0x00000300
41         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
44         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
47         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
50
51 #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
52 #define SHARED_HW_CFG_LED_MODE_SHIFT                16
53 #define SHARED_HW_CFG_LED_MAC1                      0x00000000
54 #define SHARED_HW_CFG_LED_PHY1                      0x00010000
55 #define SHARED_HW_CFG_LED_PHY2                      0x00020000
56 #define SHARED_HW_CFG_LED_PHY3                      0x00030000
57 #define SHARED_HW_CFG_LED_MAC2                      0x00040000
58 #define SHARED_HW_CFG_LED_PHY4                      0x00050000
59 #define SHARED_HW_CFG_LED_PHY5                      0x00060000
60 #define SHARED_HW_CFG_LED_PHY6                      0x00070000
61 #define SHARED_HW_CFG_LED_MAC3                      0x00080000
62 #define SHARED_HW_CFG_LED_PHY7                      0x00090000
63 #define SHARED_HW_CFG_LED_PHY9                      0x000a0000
64 #define SHARED_HW_CFG_LED_PHY11                     0x000b0000
65 #define SHARED_HW_CFG_LED_MAC4                      0x000c0000
66 #define SHARED_HW_CFG_LED_PHY8                      0x000d0000
67
68 #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
69 #define SHARED_HW_CFG_AN_ENABLE_SHIFT               24
70 #define SHARED_HW_CFG_AN_ENABLE_CL37                0x01000000
71 #define SHARED_HW_CFG_AN_ENABLE_CL73                0x02000000
72 #define SHARED_HW_CFG_AN_ENABLE_BAM                 0x04000000
73 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
74 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY          0x20000000
76
77         u32 config2;                                            /* 0x118 */
78         /* one time auto detect grace period (in sec) */
79 #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
80 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT            0
81
82 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
83
84         /* The default value for the core clock is 250MHz and it is
85            achieved by setting the clock change to 4 */
86 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
87 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT            9
88
89 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ           0x00000000
90 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ           0x00001000
91
92 #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
93
94         u32 power_dissipated;                                   /* 0x11c */
95 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
96 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT           24
97
98 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
99 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT        16
100 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE      0x00000000
101 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT         0x00010000
102 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT        0x00020000
103 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT       0x00030000
104
105         u32 ump_nc_si_config;                                   /* 0x120 */
106 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
107 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT      0
108 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC        0x00000000
109 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY        0x00000001
110 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII        0x00000000
111 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII       0x00000002
112
113 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
114 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT      8
115
116 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
117 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
118 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
119 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
120
121         u32 board;                                              /* 0x124 */
122 #define SHARED_HW_CFG_BOARD_REV_MASK                0x00FF0000
123 #define SHARED_HW_CFG_BOARD_REV_SHIFT               16
124
125 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0F000000
126 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT         24
127
128 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xF0000000
129 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT         28
130
131         u32 reserved;                                           /* 0x128 */
132
133 };
134
135
136 /****************************************************************************
137  * Port HW configuration                                                    *
138  ****************************************************************************/
139 struct port_hw_cfg {                        /* port 0: 0x12c  port 1: 0x2bc */
140
141         u32 pci_id;
142 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
143 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
144
145         u32 pci_sub_id;
146 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
147 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
148
149         u32 power_dissipated;
150 #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
151 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT              24
152 #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
153 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT              16
154 #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
155 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT              8
156 #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
157 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT              0
158
159         u32 power_consumed;
160 #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
161 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT             24
162 #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
163 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT             16
164 #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
165 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT             8
166 #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
167 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT             0
168
169         u32 mac_upper;
170 #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
171 #define PORT_HW_CFG_UPPERMAC_SHIFT                  0
172         u32 mac_lower;
173
174         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
175         u32 iscsi_mac_lower;
176
177         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
178         u32 rdma_mac_lower;
179
180         u32 serdes_config;
181 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK           0x0000FFFF
182 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT          0
183
184 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK              0xFFFF0000
185 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT             16
186
187
188         u32 Reserved0[16];                                  /* 0x158 */
189
190         /*  for external PHY, or forced mode or during AN */
191         u16 xgxs_config_rx[4];                              /* 0x198 */
192
193         u16 xgxs_config_tx[4];                              /* 0x1A0 */
194
195         u32 Reserved1[64];                                  /* 0x1A8 */
196
197         u32 lane_config;
198 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
199 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT             0
200 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
201 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT          0
202 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
203 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT          8
204 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
205 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT      14
206         /* AN and forced */
207 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123          0x00001b1b
208         /* forced only */
209 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210          0x00001be4
210         /* forced only */
211 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120          0x0000d8d8
212         /* forced only */
213 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210          0x0000e4e4
214
215         u32 external_phy_config;
216 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
217 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT       24
218 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT      0x00000000
219 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
220 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
221
222 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
223 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT       16
224
225 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
226 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT         8
227 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT        0x00000000
228 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071       0x00000100
229 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072       0x00000200
230 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073       0x00000300
231 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705       0x00000400
232 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706       0x00000500
233 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726       0x00000600
234 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481       0x00000700
235 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101       0x00000800
236 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE       0x0000fd00
237 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN      0x0000ff00
238
239 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
240 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT         0
241
242         u32 speed_capability_mask;
243 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
244 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT       16
245 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
246 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
247 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
248 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
249 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G          0x00100000
250 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G        0x00200000
251 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G         0x00400000
252 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G         0x00800000
253 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G       0x01000000
254 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G         0x02000000
255 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G         0x04000000
256 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G         0x08000000
257 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
258
259 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
260 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT       0
261 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
262 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
263 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
264 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
265 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G          0x00000010
266 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G        0x00000020
267 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G         0x00000040
268 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G         0x00000080
269 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G       0x00000100
270 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G         0x00000200
271 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G         0x00000400
272 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G         0x00000800
273 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
274
275         u32 reserved[2];
276
277 };
278
279
280 /****************************************************************************
281  * Shared Feature configuration                                             *
282  ****************************************************************************/
283 struct shared_feat_cfg {                                 /* NVRAM Offset */
284
285         u32 config;                                             /* 0x450 */
286 #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
287
288         /*  Use the values from options 47 and 48 instead of the HW default
289           values */
290 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED     0x00000000
291 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED      0x00000002
292
293 #define SHARED_FEATURE_MF_MODE_DISABLED             0x00000100
294
295 };
296
297
298 /****************************************************************************
299  * Port Feature configuration                                               *
300  ****************************************************************************/
301 struct port_feat_cfg {                      /* port 0: 0x454  port 1: 0x4c8 */
302
303         u32 config;
304 #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
305 #define PORT_FEATURE_BAR1_SIZE_SHIFT                0
306 #define PORT_FEATURE_BAR1_SIZE_DISABLED             0x00000000
307 #define PORT_FEATURE_BAR1_SIZE_64K                  0x00000001
308 #define PORT_FEATURE_BAR1_SIZE_128K                 0x00000002
309 #define PORT_FEATURE_BAR1_SIZE_256K                 0x00000003
310 #define PORT_FEATURE_BAR1_SIZE_512K                 0x00000004
311 #define PORT_FEATURE_BAR1_SIZE_1M                   0x00000005
312 #define PORT_FEATURE_BAR1_SIZE_2M                   0x00000006
313 #define PORT_FEATURE_BAR1_SIZE_4M                   0x00000007
314 #define PORT_FEATURE_BAR1_SIZE_8M                   0x00000008
315 #define PORT_FEATURE_BAR1_SIZE_16M                  0x00000009
316 #define PORT_FEATURE_BAR1_SIZE_32M                  0x0000000a
317 #define PORT_FEATURE_BAR1_SIZE_64M                  0x0000000b
318 #define PORT_FEATURE_BAR1_SIZE_128M                 0x0000000c
319 #define PORT_FEATURE_BAR1_SIZE_256M                 0x0000000d
320 #define PORT_FEATURE_BAR1_SIZE_512M                 0x0000000e
321 #define PORT_FEATURE_BAR1_SIZE_1G                   0x0000000f
322 #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
323 #define PORT_FEATURE_BAR2_SIZE_SHIFT                4
324 #define PORT_FEATURE_BAR2_SIZE_DISABLED             0x00000000
325 #define PORT_FEATURE_BAR2_SIZE_64K                  0x00000010
326 #define PORT_FEATURE_BAR2_SIZE_128K                 0x00000020
327 #define PORT_FEATURE_BAR2_SIZE_256K                 0x00000030
328 #define PORT_FEATURE_BAR2_SIZE_512K                 0x00000040
329 #define PORT_FEATURE_BAR2_SIZE_1M                   0x00000050
330 #define PORT_FEATURE_BAR2_SIZE_2M                   0x00000060
331 #define PORT_FEATURE_BAR2_SIZE_4M                   0x00000070
332 #define PORT_FEATURE_BAR2_SIZE_8M                   0x00000080
333 #define PORT_FEATURE_BAR2_SIZE_16M                  0x00000090
334 #define PORT_FEATURE_BAR2_SIZE_32M                  0x000000a0
335 #define PORT_FEATURE_BAR2_SIZE_64M                  0x000000b0
336 #define PORT_FEATURE_BAR2_SIZE_128M                 0x000000c0
337 #define PORT_FEATURE_BAR2_SIZE_256M                 0x000000d0
338 #define PORT_FEATURE_BAR2_SIZE_512M                 0x000000e0
339 #define PORT_FEATURE_BAR2_SIZE_1G                   0x000000f0
340 #define PORT_FEATURE_EN_SIZE_MASK                   0x07000000
341 #define PORT_FEATURE_EN_SIZE_SHIFT                  24
342 #define PORT_FEATURE_WOL_ENABLED                    0x01000000
343 #define PORT_FEATURE_MBA_ENABLED                    0x02000000
344 #define PORT_FEATURE_MFW_ENABLED                    0x04000000
345
346         /*  Check the optic vendor via i2c before allowing it to be used by
347           SW */
348 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLED               0x00000000
349 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED                0x08000000
350
351         u32 wol_config;
352         /* Default is used when driver sets to "auto" mode */
353 #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
354 #define PORT_FEATURE_WOL_DEFAULT_SHIFT              0
355 #define PORT_FEATURE_WOL_DEFAULT_DISABLE            0x00000000
356 #define PORT_FEATURE_WOL_DEFAULT_MAGIC              0x00000001
357 #define PORT_FEATURE_WOL_DEFAULT_ACPI               0x00000002
358 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
359 #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
360 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
361 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
362
363         u32 mba_config;
364 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000003
365 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT      0
366 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0x00000000
367 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        0x00000001
368 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      0x00000002
369 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
370 #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
371 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
372 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
373 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S              0x00000000
374 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B              0x00000800
375 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
376 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT         12
377 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0x00000000
378 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K            0x00001000
379 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K            0x00002000
380 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K            0x00003000
381 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K           0x00004000
382 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K           0x00005000
383 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K           0x00006000
384 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K          0x00007000
385 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K          0x00008000
386 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K          0x00009000
387 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M            0x0000a000
388 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M            0x0000b000
389 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M            0x0000c000
390 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M            0x0000d000
391 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M           0x0000e000
392 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M           0x0000f000
393 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
394 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT          20
395 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
396 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT       24
397 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0x00000000
398 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x01000000
399 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x02000000
400 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x03000000
401 #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
402 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT           26
403 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO            0x00000000
404 #define PORT_FEATURE_MBA_LINK_SPEED_10HD            0x04000000
405 #define PORT_FEATURE_MBA_LINK_SPEED_10FD            0x08000000
406 #define PORT_FEATURE_MBA_LINK_SPEED_100HD           0x0c000000
407 #define PORT_FEATURE_MBA_LINK_SPEED_100FD           0x10000000
408 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS           0x14000000
409 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS         0x18000000
410 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4      0x1c000000
411 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4      0x20000000
412 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR       0x24000000
413 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS          0x28000000
414 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS        0x2c000000
415 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS          0x30000000
416 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS          0x34000000
417 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS          0x38000000
418
419         u32 bmc_config;
420 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT      0x00000000
421 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN           0x00000001
422
423         u32 mba_vlan_cfg;
424 #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
425 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT             0
426 #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
427
428         u32 resource_cfg;
429 #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
430 #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
431 #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
432 #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
433 #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
434
435         u32 smbus_config;
436         /* Obsolete */
437 #define PORT_FEATURE_SMBUS_EN                       0x00000001
438 #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
439 #define PORT_FEATURE_SMBUS_ADDR_SHIFT               1
440
441         u32 reserved1;
442
443         u32 link_config;    /* Used as HW defaults for the driver */
444 #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
445 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT         24
446         /* (forced) low speed switch (< 10G) */
447 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH           0x00000000
448         /* (forced) high speed switch (>= 10G) */
449 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH          0x01000000
450 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT         0x02000000
451 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
452
453 #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
454 #define PORT_FEATURE_LINK_SPEED_SHIFT               16
455 #define PORT_FEATURE_LINK_SPEED_AUTO                0x00000000
456 #define PORT_FEATURE_LINK_SPEED_10M_FULL            0x00010000
457 #define PORT_FEATURE_LINK_SPEED_10M_HALF            0x00020000
458 #define PORT_FEATURE_LINK_SPEED_100M_HALF           0x00030000
459 #define PORT_FEATURE_LINK_SPEED_100M_FULL           0x00040000
460 #define PORT_FEATURE_LINK_SPEED_1G                  0x00050000
461 #define PORT_FEATURE_LINK_SPEED_2_5G                0x00060000
462 #define PORT_FEATURE_LINK_SPEED_10G_CX4             0x00070000
463 #define PORT_FEATURE_LINK_SPEED_10G_KX4             0x00080000
464 #define PORT_FEATURE_LINK_SPEED_10G_KR              0x00090000
465 #define PORT_FEATURE_LINK_SPEED_12G                 0x000a0000
466 #define PORT_FEATURE_LINK_SPEED_12_5G               0x000b0000
467 #define PORT_FEATURE_LINK_SPEED_13G                 0x000c0000
468 #define PORT_FEATURE_LINK_SPEED_15G                 0x000d0000
469 #define PORT_FEATURE_LINK_SPEED_16G                 0x000e0000
470
471 #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
472 #define PORT_FEATURE_FLOW_CONTROL_SHIFT             8
473 #define PORT_FEATURE_FLOW_CONTROL_AUTO              0x00000000
474 #define PORT_FEATURE_FLOW_CONTROL_TX                0x00000100
475 #define PORT_FEATURE_FLOW_CONTROL_RX                0x00000200
476 #define PORT_FEATURE_FLOW_CONTROL_BOTH              0x00000300
477 #define PORT_FEATURE_FLOW_CONTROL_NONE              0x00000400
478
479         /* The default for MCP link configuration,
480            uses the same defines as link_config */
481         u32 mfw_wol_link_cfg;
482
483         u32 reserved[19];
484
485 };
486
487
488 /****************************************************************************
489  * Device Information                                                       *
490  ****************************************************************************/
491 struct shm_dev_info {                                               /* size */
492
493         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
494
495         struct shared_hw_cfg     shared_hw_config;                    /* 40 */
496
497         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
498
499         struct shared_feat_cfg   shared_feature_config;                /* 4 */
500
501         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
502
503 };
504
505
506 #define FUNC_0                          0
507 #define FUNC_1                          1
508 #define FUNC_2                          2
509 #define FUNC_3                          3
510 #define FUNC_4                          4
511 #define FUNC_5                          5
512 #define FUNC_6                          6
513 #define FUNC_7                          7
514 #define E1_FUNC_MAX                     2
515 #define E1H_FUNC_MAX                    8
516
517 #define VN_0                            0
518 #define VN_1                            1
519 #define VN_2                            2
520 #define VN_3                            3
521 #define E1VN_MAX                        1
522 #define E1HVN_MAX                       4
523
524
525 /* This value (in milliseconds) determines the frequency of the driver
526  * issuing the PULSE message code.  The firmware monitors this periodic
527  * pulse to determine when to switch to an OS-absent mode. */
528 #define DRV_PULSE_PERIOD_MS             250
529
530 /* This value (in milliseconds) determines how long the driver should
531  * wait for an acknowledgement from the firmware before timing out.  Once
532  * the firmware has timed out, the driver will assume there is no firmware
533  * running and there won't be any firmware-driver synchronization during a
534  * driver reset. */
535 #define FW_ACK_TIME_OUT_MS              5000
536
537 #define FW_ACK_POLL_TIME_MS             1
538
539 #define FW_ACK_NUM_OF_POLL      (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
540
541 /* LED Blink rate that will achieve ~15.9Hz */
542 #define LED_BLINK_RATE_VAL              480
543
544 /****************************************************************************
545  * Driver <-> FW Mailbox                                                    *
546  ****************************************************************************/
547 struct drv_port_mb {
548
549         u32 link_status;
550         /* Driver should update this field on any link change event */
551
552 #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
553 #define LINK_STATUS_LINK_UP                             0x00000001
554 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
555 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
556 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
557 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
558 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
559 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
560 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
561 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
562 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
563 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
564 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
565 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
566 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
567 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
568 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
569 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD             (11<<1)
570 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD             (11<<1)
571 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD           (12<<1)
572 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD           (12<<1)
573 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD             (13<<1)
574 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD             (13<<1)
575 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD             (14<<1)
576 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD             (14<<1)
577 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD             (15<<1)
578 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD             (15<<1)
579
580 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
581 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
582
583 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
584 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
585 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
586
587 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
588 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
589 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
590 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
591 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
592 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
593 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
594
595 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
596 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
597
598 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
599 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
600
601 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
602 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
603 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
604 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
605 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
606
607 #define LINK_STATUS_SERDES_LINK                         0x00100000
608
609 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
610 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
611 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
612 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE         0x01000000
613 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE       0x02000000
614 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE         0x04000000
615 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE         0x08000000
616 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE         0x10000000
617
618         u32 port_stx;
619
620         u32 stat_nig_timer;
621
622         /* MCP firmware does not use this field */
623         u32 ext_phy_fw_version;
624
625 };
626
627
628 struct drv_func_mb {
629
630         u32 drv_mb_header;
631 #define DRV_MSG_CODE_MASK                               0xffff0000
632 #define DRV_MSG_CODE_LOAD_REQ                           0x10000000
633 #define DRV_MSG_CODE_LOAD_DONE                          0x11000000
634 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN                  0x20000000
635 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS                 0x20010000
636 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP                 0x20020000
637 #define DRV_MSG_CODE_UNLOAD_DONE                        0x21000000
638 #define DRV_MSG_CODE_DIAG_ENTER_REQ                     0x50000000
639 #define DRV_MSG_CODE_DIAG_EXIT_REQ                      0x60000000
640 #define DRV_MSG_CODE_VALIDATE_KEY                       0x70000000
641 #define DRV_MSG_CODE_GET_CURR_KEY                       0x80000000
642 #define DRV_MSG_CODE_GET_UPGRADE_KEY                    0x81000000
643 #define DRV_MSG_CODE_GET_MANUF_KEY                      0x82000000
644 #define DRV_MSG_CODE_LOAD_L2B_PRAM                      0x90000000
645
646 #define BIOS_MSG_CODE_LIC_CHALLENGE                     0xff010000
647 #define BIOS_MSG_CODE_LIC_RESPONSE                      0xff020000
648 #define BIOS_MSG_CODE_VIRT_MAC_PRIM                     0xff030000
649 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI                    0xff040000
650
651 #define DRV_MSG_SEQ_NUMBER_MASK                         0x0000ffff
652
653         u32 drv_mb_param;
654
655         u32 fw_mb_header;
656 #define FW_MSG_CODE_MASK                                0xffff0000
657 #define FW_MSG_CODE_DRV_LOAD_COMMON                     0x10100000
658 #define FW_MSG_CODE_DRV_LOAD_PORT                       0x10110000
659 #define FW_MSG_CODE_DRV_LOAD_FUNCTION                   0x10120000
660 #define FW_MSG_CODE_DRV_LOAD_REFUSED                    0x10200000
661 #define FW_MSG_CODE_DRV_LOAD_DONE                       0x11100000
662 #define FW_MSG_CODE_DRV_UNLOAD_COMMON                   0x20100000
663 #define FW_MSG_CODE_DRV_UNLOAD_PORT                     0x20110000
664 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION                 0x20120000
665 #define FW_MSG_CODE_DRV_UNLOAD_DONE                     0x21100000
666 #define FW_MSG_CODE_DIAG_ENTER_DONE                     0x50100000
667 #define FW_MSG_CODE_DIAG_REFUSE                         0x50200000
668 #define FW_MSG_CODE_DIAG_EXIT_DONE                      0x60100000
669 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS                0x70100000
670 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE                0x70200000
671 #define FW_MSG_CODE_GET_KEY_DONE                        0x80100000
672 #define FW_MSG_CODE_NO_KEY                              0x80f00000
673 #define FW_MSG_CODE_LIC_INFO_NOT_READY                  0x80f80000
674 #define FW_MSG_CODE_L2B_PRAM_LOADED                     0x90100000
675 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE             0x90210000
676 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE             0x90220000
677 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE             0x90230000
678 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE             0x90240000
679
680 #define FW_MSG_CODE_LIC_CHALLENGE                       0xff010000
681 #define FW_MSG_CODE_LIC_RESPONSE                        0xff020000
682 #define FW_MSG_CODE_VIRT_MAC_PRIM                       0xff030000
683 #define FW_MSG_CODE_VIRT_MAC_ISCSI                      0xff040000
684
685 #define FW_MSG_SEQ_NUMBER_MASK                          0x0000ffff
686
687         u32 fw_mb_param;
688
689         u32 drv_pulse_mb;
690 #define DRV_PULSE_SEQ_MASK                              0x00007fff
691 #define DRV_PULSE_SYSTEM_TIME_MASK                      0xffff0000
692         /* The system time is in the format of
693          * (year-2001)*12*32 + month*32 + day. */
694 #define DRV_PULSE_ALWAYS_ALIVE                          0x00008000
695         /* Indicate to the firmware not to go into the
696          * OS-absent when it is not getting driver pulse.
697          * This is used for debugging as well for PXE(MBA). */
698
699         u32 mcp_pulse_mb;
700 #define MCP_PULSE_SEQ_MASK                              0x00007fff
701 #define MCP_PULSE_ALWAYS_ALIVE                          0x00008000
702         /* Indicates to the driver not to assert due to lack
703          * of MCP response */
704 #define MCP_EVENT_MASK                                  0xffff0000
705 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ                0x00010000
706
707         u32 iscsi_boot_signature;
708         u32 iscsi_boot_block_offset;
709
710         u32 drv_status;
711 #define DRV_STATUS_PMF                                  0x00000001
712
713         u32 virt_mac_upper;
714 #define VIRT_MAC_SIGN_MASK                              0xffff0000
715 #define VIRT_MAC_SIGNATURE                              0x564d0000
716         u32 virt_mac_lower;
717
718 };
719
720
721 /****************************************************************************
722  * Management firmware state                                                *
723  ****************************************************************************/
724 /* Allocate 440 bytes for management firmware */
725 #define MGMTFW_STATE_WORD_SIZE                              110
726
727 struct mgmtfw_state {
728         u32 opaque[MGMTFW_STATE_WORD_SIZE];
729 };
730
731
732 /****************************************************************************
733  * Multi-Function configuration                                             *
734  ****************************************************************************/
735 struct shared_mf_cfg {
736
737         u32 clp_mb;
738 #define SHARED_MF_CLP_SET_DEFAULT                   0x00000000
739         /* set by CLP */
740 #define SHARED_MF_CLP_EXIT                          0x00000001
741         /* set by MCP */
742 #define SHARED_MF_CLP_EXIT_DONE                     0x00010000
743
744 };
745
746 struct port_mf_cfg {
747
748         u32 dynamic_cfg;        /* device control channel */
749 #define PORT_MF_CFG_OUTER_VLAN_TAG_MASK             0x0000ffff
750 #define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT            0
751 #define PORT_MF_CFG_DYNAMIC_CFG_ENABLED             0x00010000
752 #define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT             0x00000000
753
754         u32 reserved[3];
755
756 };
757
758 struct func_mf_cfg {
759
760         u32 config;
761         /* E/R/I/D */
762         /* function 0 of each port cannot be hidden */
763 #define FUNC_MF_CFG_FUNC_HIDE                       0x00000001
764
765 #define FUNC_MF_CFG_PROTOCOL_MASK                   0x00000007
766 #define FUNC_MF_CFG_PROTOCOL_ETHERNET               0x00000002
767 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA     0x00000004
768 #define FUNC_MF_CFG_PROTOCOL_ISCSI                  0x00000006
769 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
770         FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
771
772 #define FUNC_MF_CFG_FUNC_DISABLED                   0x00000008
773
774         /* PRI */
775         /* 0 - low priority, 3 - high priority */
776 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK          0x00000300
777 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT         8
778 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT       0x00000000
779
780         /* MINBW, MAXBW */
781         /* value range - 0..100, increments in 100Mbps */
782 #define FUNC_MF_CFG_MIN_BW_MASK                     0x00ff0000
783 #define FUNC_MF_CFG_MIN_BW_SHIFT                    16
784 #define FUNC_MF_CFG_MIN_BW_DEFAULT                  0x00000000
785 #define FUNC_MF_CFG_MAX_BW_MASK                     0xff000000
786 #define FUNC_MF_CFG_MAX_BW_SHIFT                    24
787 #define FUNC_MF_CFG_MAX_BW_DEFAULT                  0x64000000
788
789         u32 mac_upper;          /* MAC */
790 #define FUNC_MF_CFG_UPPERMAC_MASK                   0x0000ffff
791 #define FUNC_MF_CFG_UPPERMAC_SHIFT                  0
792 #define FUNC_MF_CFG_UPPERMAC_DEFAULT                FUNC_MF_CFG_UPPERMAC_MASK
793         u32 mac_lower;
794 #define FUNC_MF_CFG_LOWERMAC_DEFAULT                0xffffffff
795
796         u32 e1hov_tag;  /* VNI */
797 #define FUNC_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
798 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT                 0
799 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT               FUNC_MF_CFG_E1HOV_TAG_MASK
800
801         u32 reserved[2];
802
803 };
804
805 struct mf_cfg {
806
807         struct shared_mf_cfg    shared_mf_config;
808         struct port_mf_cfg      port_mf_config[PORT_MAX];
809         struct func_mf_cfg      func_mf_config[E1H_FUNC_MAX];
810
811 };
812
813
814 /****************************************************************************
815  * Shared Memory Region                                                     *
816  ****************************************************************************/
817 struct shmem_region {                          /*   SharedMem Offset (size) */
818
819         u32                     validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
820 #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
821 #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
822         /* validity bits */
823 #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
824 #define SHR_MEM_VALIDITY_MB                         0x00200000
825 #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
826 #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
827         /* One licensing bit should be set */
828 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
829 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
830 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
831 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
832         /* Active MFW */
833 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
834 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
835 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
836 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
837 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
838 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
839
840         struct shm_dev_info     dev_info;                /* 0x8     (0x438) */
841
842         u8                      reserved[52*PORT_MAX];
843
844         /* FW information (for internal FW use) */
845         u32                     fw_info_fio_offset;    /* 0x4a8       (0x4) */
846         struct mgmtfw_state     mgmtfw_state;          /* 0x4ac     (0x1b8) */
847
848         struct drv_port_mb      port_mb[PORT_MAX];     /* 0x664 (16*2=0x20) */
849         struct drv_func_mb      func_mb[E1H_FUNC_MAX];
850
851         struct mf_cfg           mf_cfg;
852
853 };                                                     /* 0x6dc */
854
855
856 struct emac_stats {
857     u32     rx_stat_ifhcinoctets;
858     u32     rx_stat_ifhcinbadoctets;
859     u32     rx_stat_etherstatsfragments;
860     u32     rx_stat_ifhcinucastpkts;
861     u32     rx_stat_ifhcinmulticastpkts;
862     u32     rx_stat_ifhcinbroadcastpkts;
863     u32     rx_stat_dot3statsfcserrors;
864     u32     rx_stat_dot3statsalignmenterrors;
865     u32     rx_stat_dot3statscarriersenseerrors;
866     u32     rx_stat_xonpauseframesreceived;
867     u32     rx_stat_xoffpauseframesreceived;
868     u32     rx_stat_maccontrolframesreceived;
869     u32     rx_stat_xoffstateentered;
870     u32     rx_stat_dot3statsframestoolong;
871     u32     rx_stat_etherstatsjabbers;
872     u32     rx_stat_etherstatsundersizepkts;
873     u32     rx_stat_etherstatspkts64octets;
874     u32     rx_stat_etherstatspkts65octetsto127octets;
875     u32     rx_stat_etherstatspkts128octetsto255octets;
876     u32     rx_stat_etherstatspkts256octetsto511octets;
877     u32     rx_stat_etherstatspkts512octetsto1023octets;
878     u32     rx_stat_etherstatspkts1024octetsto1522octets;
879     u32     rx_stat_etherstatspktsover1522octets;
880
881     u32     rx_stat_falsecarriererrors;
882
883     u32     tx_stat_ifhcoutoctets;
884     u32     tx_stat_ifhcoutbadoctets;
885     u32     tx_stat_etherstatscollisions;
886     u32     tx_stat_outxonsent;
887     u32     tx_stat_outxoffsent;
888     u32     tx_stat_flowcontroldone;
889     u32     tx_stat_dot3statssinglecollisionframes;
890     u32     tx_stat_dot3statsmultiplecollisionframes;
891     u32     tx_stat_dot3statsdeferredtransmissions;
892     u32     tx_stat_dot3statsexcessivecollisions;
893     u32     tx_stat_dot3statslatecollisions;
894     u32     tx_stat_ifhcoutucastpkts;
895     u32     tx_stat_ifhcoutmulticastpkts;
896     u32     tx_stat_ifhcoutbroadcastpkts;
897     u32     tx_stat_etherstatspkts64octets;
898     u32     tx_stat_etherstatspkts65octetsto127octets;
899     u32     tx_stat_etherstatspkts128octetsto255octets;
900     u32     tx_stat_etherstatspkts256octetsto511octets;
901     u32     tx_stat_etherstatspkts512octetsto1023octets;
902     u32     tx_stat_etherstatspkts1024octetsto1522octets;
903     u32     tx_stat_etherstatspktsover1522octets;
904     u32     tx_stat_dot3statsinternalmactransmiterrors;
905 };
906
907
908 struct bmac_stats {
909     u32     tx_stat_gtpkt_lo;
910     u32     tx_stat_gtpkt_hi;
911     u32     tx_stat_gtxpf_lo;
912     u32     tx_stat_gtxpf_hi;
913     u32     tx_stat_gtfcs_lo;
914     u32     tx_stat_gtfcs_hi;
915     u32     tx_stat_gtmca_lo;
916     u32     tx_stat_gtmca_hi;
917     u32     tx_stat_gtbca_lo;
918     u32     tx_stat_gtbca_hi;
919     u32     tx_stat_gtfrg_lo;
920     u32     tx_stat_gtfrg_hi;
921     u32     tx_stat_gtovr_lo;
922     u32     tx_stat_gtovr_hi;
923     u32     tx_stat_gt64_lo;
924     u32     tx_stat_gt64_hi;
925     u32     tx_stat_gt127_lo;
926     u32     tx_stat_gt127_hi;
927     u32     tx_stat_gt255_lo;
928     u32     tx_stat_gt255_hi;
929     u32     tx_stat_gt511_lo;
930     u32     tx_stat_gt511_hi;
931     u32     tx_stat_gt1023_lo;
932     u32     tx_stat_gt1023_hi;
933     u32     tx_stat_gt1518_lo;
934     u32     tx_stat_gt1518_hi;
935     u32     tx_stat_gt2047_lo;
936     u32     tx_stat_gt2047_hi;
937     u32     tx_stat_gt4095_lo;
938     u32     tx_stat_gt4095_hi;
939     u32     tx_stat_gt9216_lo;
940     u32     tx_stat_gt9216_hi;
941     u32     tx_stat_gt16383_lo;
942     u32     tx_stat_gt16383_hi;
943     u32     tx_stat_gtmax_lo;
944     u32     tx_stat_gtmax_hi;
945     u32     tx_stat_gtufl_lo;
946     u32     tx_stat_gtufl_hi;
947     u32     tx_stat_gterr_lo;
948     u32     tx_stat_gterr_hi;
949     u32     tx_stat_gtbyt_lo;
950     u32     tx_stat_gtbyt_hi;
951
952     u32     rx_stat_gr64_lo;
953     u32     rx_stat_gr64_hi;
954     u32     rx_stat_gr127_lo;
955     u32     rx_stat_gr127_hi;
956     u32     rx_stat_gr255_lo;
957     u32     rx_stat_gr255_hi;
958     u32     rx_stat_gr511_lo;
959     u32     rx_stat_gr511_hi;
960     u32     rx_stat_gr1023_lo;
961     u32     rx_stat_gr1023_hi;
962     u32     rx_stat_gr1518_lo;
963     u32     rx_stat_gr1518_hi;
964     u32     rx_stat_gr2047_lo;
965     u32     rx_stat_gr2047_hi;
966     u32     rx_stat_gr4095_lo;
967     u32     rx_stat_gr4095_hi;
968     u32     rx_stat_gr9216_lo;
969     u32     rx_stat_gr9216_hi;
970     u32     rx_stat_gr16383_lo;
971     u32     rx_stat_gr16383_hi;
972     u32     rx_stat_grmax_lo;
973     u32     rx_stat_grmax_hi;
974     u32     rx_stat_grpkt_lo;
975     u32     rx_stat_grpkt_hi;
976     u32     rx_stat_grfcs_lo;
977     u32     rx_stat_grfcs_hi;
978     u32     rx_stat_grmca_lo;
979     u32     rx_stat_grmca_hi;
980     u32     rx_stat_grbca_lo;
981     u32     rx_stat_grbca_hi;
982     u32     rx_stat_grxcf_lo;
983     u32     rx_stat_grxcf_hi;
984     u32     rx_stat_grxpf_lo;
985     u32     rx_stat_grxpf_hi;
986     u32     rx_stat_grxuo_lo;
987     u32     rx_stat_grxuo_hi;
988     u32     rx_stat_grjbr_lo;
989     u32     rx_stat_grjbr_hi;
990     u32     rx_stat_grovr_lo;
991     u32     rx_stat_grovr_hi;
992     u32     rx_stat_grflr_lo;
993     u32     rx_stat_grflr_hi;
994     u32     rx_stat_grmeg_lo;
995     u32     rx_stat_grmeg_hi;
996     u32     rx_stat_grmeb_lo;
997     u32     rx_stat_grmeb_hi;
998     u32     rx_stat_grbyt_lo;
999     u32     rx_stat_grbyt_hi;
1000     u32     rx_stat_grund_lo;
1001     u32     rx_stat_grund_hi;
1002     u32     rx_stat_grfrg_lo;
1003     u32     rx_stat_grfrg_hi;
1004     u32     rx_stat_grerb_lo;
1005     u32     rx_stat_grerb_hi;
1006     u32     rx_stat_grfre_lo;
1007     u32     rx_stat_grfre_hi;
1008     u32     rx_stat_gripj_lo;
1009     u32     rx_stat_gripj_hi;
1010 };
1011
1012
1013 union mac_stats {
1014     struct emac_stats   emac_stats;
1015     struct bmac_stats   bmac_stats;
1016 };
1017
1018
1019 struct mac_stx {
1020     /* in_bad_octets */
1021     u32     rx_stat_ifhcinbadoctets_hi;
1022     u32     rx_stat_ifhcinbadoctets_lo;
1023
1024     /* out_bad_octets */
1025     u32     tx_stat_ifhcoutbadoctets_hi;
1026     u32     tx_stat_ifhcoutbadoctets_lo;
1027
1028     /* crc_receive_errors */
1029     u32     rx_stat_dot3statsfcserrors_hi;
1030     u32     rx_stat_dot3statsfcserrors_lo;
1031     /* alignment_errors */
1032     u32     rx_stat_dot3statsalignmenterrors_hi;
1033     u32     rx_stat_dot3statsalignmenterrors_lo;
1034     /* carrier_sense_errors */
1035     u32     rx_stat_dot3statscarriersenseerrors_hi;
1036     u32     rx_stat_dot3statscarriersenseerrors_lo;
1037     /* false_carrier_detections */
1038     u32     rx_stat_falsecarriererrors_hi;
1039     u32     rx_stat_falsecarriererrors_lo;
1040
1041     /* runt_packets_received */
1042     u32     rx_stat_etherstatsundersizepkts_hi;
1043     u32     rx_stat_etherstatsundersizepkts_lo;
1044     /* jabber_packets_received */
1045     u32     rx_stat_dot3statsframestoolong_hi;
1046     u32     rx_stat_dot3statsframestoolong_lo;
1047
1048     /* error_runt_packets_received */
1049     u32     rx_stat_etherstatsfragments_hi;
1050     u32     rx_stat_etherstatsfragments_lo;
1051     /* error_jabber_packets_received */
1052     u32     rx_stat_etherstatsjabbers_hi;
1053     u32     rx_stat_etherstatsjabbers_lo;
1054
1055     /* control_frames_received */
1056     u32     rx_stat_maccontrolframesreceived_hi;
1057     u32     rx_stat_maccontrolframesreceived_lo;
1058     u32     rx_stat_bmac_xpf_hi;
1059     u32     rx_stat_bmac_xpf_lo;
1060     u32     rx_stat_bmac_xcf_hi;
1061     u32     rx_stat_bmac_xcf_lo;
1062
1063     /* xoff_state_entered */
1064     u32     rx_stat_xoffstateentered_hi;
1065     u32     rx_stat_xoffstateentered_lo;
1066     /* pause_xon_frames_received */
1067     u32     rx_stat_xonpauseframesreceived_hi;
1068     u32     rx_stat_xonpauseframesreceived_lo;
1069     /* pause_xoff_frames_received */
1070     u32     rx_stat_xoffpauseframesreceived_hi;
1071     u32     rx_stat_xoffpauseframesreceived_lo;
1072     /* pause_xon_frames_transmitted */
1073     u32     tx_stat_outxonsent_hi;
1074     u32     tx_stat_outxonsent_lo;
1075     /* pause_xoff_frames_transmitted */
1076     u32     tx_stat_outxoffsent_hi;
1077     u32     tx_stat_outxoffsent_lo;
1078     /* flow_control_done */
1079     u32     tx_stat_flowcontroldone_hi;
1080     u32     tx_stat_flowcontroldone_lo;
1081
1082     /* ether_stats_collisions */
1083     u32     tx_stat_etherstatscollisions_hi;
1084     u32     tx_stat_etherstatscollisions_lo;
1085     /* single_collision_transmit_frames */
1086     u32     tx_stat_dot3statssinglecollisionframes_hi;
1087     u32     tx_stat_dot3statssinglecollisionframes_lo;
1088     /* multiple_collision_transmit_frames */
1089     u32     tx_stat_dot3statsmultiplecollisionframes_hi;
1090     u32     tx_stat_dot3statsmultiplecollisionframes_lo;
1091     /* deferred_transmissions */
1092     u32     tx_stat_dot3statsdeferredtransmissions_hi;
1093     u32     tx_stat_dot3statsdeferredtransmissions_lo;
1094     /* excessive_collision_frames */
1095     u32     tx_stat_dot3statsexcessivecollisions_hi;
1096     u32     tx_stat_dot3statsexcessivecollisions_lo;
1097     /* late_collision_frames */
1098     u32     tx_stat_dot3statslatecollisions_hi;
1099     u32     tx_stat_dot3statslatecollisions_lo;
1100
1101     /* frames_transmitted_64_bytes */
1102     u32     tx_stat_etherstatspkts64octets_hi;
1103     u32     tx_stat_etherstatspkts64octets_lo;
1104     /* frames_transmitted_65_127_bytes */
1105     u32     tx_stat_etherstatspkts65octetsto127octets_hi;
1106     u32     tx_stat_etherstatspkts65octetsto127octets_lo;
1107     /* frames_transmitted_128_255_bytes */
1108     u32     tx_stat_etherstatspkts128octetsto255octets_hi;
1109     u32     tx_stat_etherstatspkts128octetsto255octets_lo;
1110     /* frames_transmitted_256_511_bytes */
1111     u32     tx_stat_etherstatspkts256octetsto511octets_hi;
1112     u32     tx_stat_etherstatspkts256octetsto511octets_lo;
1113     /* frames_transmitted_512_1023_bytes */
1114     u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
1115     u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
1116     /* frames_transmitted_1024_1522_bytes */
1117     u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
1118     u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
1119     /* frames_transmitted_1523_9022_bytes */
1120     u32     tx_stat_etherstatspktsover1522octets_hi;
1121     u32     tx_stat_etherstatspktsover1522octets_lo;
1122     u32     tx_stat_bmac_2047_hi;
1123     u32     tx_stat_bmac_2047_lo;
1124     u32     tx_stat_bmac_4095_hi;
1125     u32     tx_stat_bmac_4095_lo;
1126     u32     tx_stat_bmac_9216_hi;
1127     u32     tx_stat_bmac_9216_lo;
1128     u32     tx_stat_bmac_16383_hi;
1129     u32     tx_stat_bmac_16383_lo;
1130
1131     /* internal_mac_transmit_errors */
1132     u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
1133     u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
1134
1135     /* if_out_discards */
1136     u32     tx_stat_bmac_ufl_hi;
1137     u32     tx_stat_bmac_ufl_lo;
1138 };
1139
1140
1141 #define MAC_STX_IDX_MAX                     2
1142
1143 struct host_port_stats {
1144     u32            host_port_stats_start;
1145
1146     struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1147
1148     u32            brb_drop_hi;
1149     u32            brb_drop_lo;
1150
1151     u32            host_port_stats_end;
1152 };
1153
1154
1155 struct host_func_stats {
1156     u32     host_func_stats_start;
1157
1158     u32     total_bytes_received_hi;
1159     u32     total_bytes_received_lo;
1160
1161     u32     total_bytes_transmitted_hi;
1162     u32     total_bytes_transmitted_lo;
1163
1164     u32     total_unicast_packets_received_hi;
1165     u32     total_unicast_packets_received_lo;
1166
1167     u32     total_multicast_packets_received_hi;
1168     u32     total_multicast_packets_received_lo;
1169
1170     u32     total_broadcast_packets_received_hi;
1171     u32     total_broadcast_packets_received_lo;
1172
1173     u32     total_unicast_packets_transmitted_hi;
1174     u32     total_unicast_packets_transmitted_lo;
1175
1176     u32     total_multicast_packets_transmitted_hi;
1177     u32     total_multicast_packets_transmitted_lo;
1178
1179     u32     total_broadcast_packets_transmitted_hi;
1180     u32     total_broadcast_packets_transmitted_lo;
1181
1182     u32     valid_bytes_received_hi;
1183     u32     valid_bytes_received_lo;
1184
1185     u32     host_func_stats_end;
1186 };
1187
1188
1189 #define BCM_5710_FW_MAJOR_VERSION                       4
1190 #define BCM_5710_FW_MINOR_VERSION                       8
1191 #define BCM_5710_FW_REVISION_VERSION                    53
1192 #define BCM_5710_FW_ENGINEERING_VERSION                 0
1193 #define BCM_5710_FW_COMPILE_FLAGS                       1
1194
1195
1196 /*
1197  * attention bits
1198  */
1199 struct atten_def_status_block {
1200         __le32 attn_bits;
1201         __le32 attn_bits_ack;
1202         u8 status_block_id;
1203         u8 reserved0;
1204         __le16 attn_bits_index;
1205         __le32 reserved1;
1206 };
1207
1208
1209 /*
1210  * common data for all protocols
1211  */
1212 struct doorbell_hdr {
1213         u8 header;
1214 #define DOORBELL_HDR_RX (0x1<<0)
1215 #define DOORBELL_HDR_RX_SHIFT 0
1216 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1217 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1218 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1219 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1220 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1221 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1222 };
1223
1224 /*
1225  * doorbell message sent to the chip
1226  */
1227 struct doorbell {
1228 #if defined(__BIG_ENDIAN)
1229         u16 zero_fill2;
1230         u8 zero_fill1;
1231         struct doorbell_hdr header;
1232 #elif defined(__LITTLE_ENDIAN)
1233         struct doorbell_hdr header;
1234         u8 zero_fill1;
1235         u16 zero_fill2;
1236 #endif
1237 };
1238
1239
1240 /*
1241  * IGU driver acknowledgement register
1242  */
1243 struct igu_ack_register {
1244 #if defined(__BIG_ENDIAN)
1245         u16 sb_id_and_flags;
1246 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1247 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1248 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1249 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1250 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1251 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1252 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1253 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1254 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1255 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1256         u16 status_block_index;
1257 #elif defined(__LITTLE_ENDIAN)
1258         u16 status_block_index;
1259         u16 sb_id_and_flags;
1260 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1261 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1262 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1263 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1264 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1265 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1266 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1267 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1268 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1269 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1270 #endif
1271 };
1272
1273
1274 /*
1275  * Parser parsing flags field
1276  */
1277 struct parsing_flags {
1278         __le16 flags;
1279 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1280 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1281 #define PARSING_FLAGS_VLAN (0x1<<1)
1282 #define PARSING_FLAGS_VLAN_SHIFT 1
1283 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1284 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1285 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1286 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1287 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1288 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1289 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1290 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1291 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1292 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1293 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1294 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1295 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1296 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1297 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1298 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1299 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1300 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1301 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1302 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1303 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1304 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1305 };
1306
1307
1308 struct regpair {
1309         __le32 lo;
1310         __le32 hi;
1311 };
1312
1313
1314 /*
1315  * dmae command structure
1316  */
1317 struct dmae_command {
1318         u32 opcode;
1319 #define DMAE_COMMAND_SRC (0x1<<0)
1320 #define DMAE_COMMAND_SRC_SHIFT 0
1321 #define DMAE_COMMAND_DST (0x3<<1)
1322 #define DMAE_COMMAND_DST_SHIFT 1
1323 #define DMAE_COMMAND_C_DST (0x1<<3)
1324 #define DMAE_COMMAND_C_DST_SHIFT 3
1325 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1326 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1327 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1328 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1329 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1330 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1331 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1332 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1333 #define DMAE_COMMAND_PORT (0x1<<11)
1334 #define DMAE_COMMAND_PORT_SHIFT 11
1335 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1336 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1337 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1338 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1339 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1340 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1341 #define DMAE_COMMAND_E1HVN (0x3<<15)
1342 #define DMAE_COMMAND_E1HVN_SHIFT 15
1343 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1344 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1345         u32 src_addr_lo;
1346         u32 src_addr_hi;
1347         u32 dst_addr_lo;
1348         u32 dst_addr_hi;
1349 #if defined(__BIG_ENDIAN)
1350         u16 reserved1;
1351         u16 len;
1352 #elif defined(__LITTLE_ENDIAN)
1353         u16 len;
1354         u16 reserved1;
1355 #endif
1356         u32 comp_addr_lo;
1357         u32 comp_addr_hi;
1358         u32 comp_val;
1359         u32 crc32;
1360         u32 crc32_c;
1361 #if defined(__BIG_ENDIAN)
1362         u16 crc16_c;
1363         u16 crc16;
1364 #elif defined(__LITTLE_ENDIAN)
1365         u16 crc16;
1366         u16 crc16_c;
1367 #endif
1368 #if defined(__BIG_ENDIAN)
1369         u16 reserved2;
1370         u16 crc_t10;
1371 #elif defined(__LITTLE_ENDIAN)
1372         u16 crc_t10;
1373         u16 reserved2;
1374 #endif
1375 #if defined(__BIG_ENDIAN)
1376         u16 xsum8;
1377         u16 xsum16;
1378 #elif defined(__LITTLE_ENDIAN)
1379         u16 xsum16;
1380         u16 xsum8;
1381 #endif
1382 };
1383
1384
1385 struct double_regpair {
1386         u32 regpair0_lo;
1387         u32 regpair0_hi;
1388         u32 regpair1_lo;
1389         u32 regpair1_hi;
1390 };
1391
1392
1393 /*
1394  * The eth storm context of Ustorm (configuration part)
1395  */
1396 struct ustorm_eth_st_context_config {
1397 #if defined(__BIG_ENDIAN)
1398         u8 flags;
1399 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1400 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1401 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1402 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1403 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1404 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1405 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1406 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1407 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1408 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1409 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1410 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1411         u8 status_block_id;
1412         u8 clientId;
1413         u8 sb_index_numbers;
1414 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1415 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1416 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1417 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1418 #elif defined(__LITTLE_ENDIAN)
1419         u8 sb_index_numbers;
1420 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1421 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1422 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1423 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1424         u8 clientId;
1425         u8 status_block_id;
1426         u8 flags;
1427 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1428 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1429 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1430 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1431 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1432 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1433 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1434 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1435 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1436 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1437 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1438 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1439 #endif
1440 #if defined(__BIG_ENDIAN)
1441         u16 bd_buff_size;
1442         u8 statistics_counter_id;
1443         u8 mc_alignment_log_size;
1444 #elif defined(__LITTLE_ENDIAN)
1445         u8 mc_alignment_log_size;
1446         u8 statistics_counter_id;
1447         u16 bd_buff_size;
1448 #endif
1449 #if defined(__BIG_ENDIAN)
1450         u8 __local_sge_prod;
1451         u8 __local_bd_prod;
1452         u16 sge_buff_size;
1453 #elif defined(__LITTLE_ENDIAN)
1454         u16 sge_buff_size;
1455         u8 __local_bd_prod;
1456         u8 __local_sge_prod;
1457 #endif
1458         u32 reserved;
1459         u32 bd_page_base_lo;
1460         u32 bd_page_base_hi;
1461         u32 sge_page_base_lo;
1462         u32 sge_page_base_hi;
1463 };
1464
1465 /*
1466  * The eth Rx Buffer Descriptor
1467  */
1468 struct eth_rx_bd {
1469         __le32 addr_lo;
1470         __le32 addr_hi;
1471 };
1472
1473 /*
1474  * The eth Rx SGE Descriptor
1475  */
1476 struct eth_rx_sge {
1477         __le32 addr_lo;
1478         __le32 addr_hi;
1479 };
1480
1481 /*
1482  * Local BDs and SGEs rings (in ETH)
1483  */
1484 struct eth_local_rx_rings {
1485         struct eth_rx_bd __local_bd_ring[16];
1486         struct eth_rx_sge __local_sge_ring[12];
1487 };
1488
1489 /*
1490  * The eth storm context of Ustorm
1491  */
1492 struct ustorm_eth_st_context {
1493         struct ustorm_eth_st_context_config common;
1494         struct eth_local_rx_rings __rings;
1495 };
1496
1497 /*
1498  * The eth storm context of Tstorm
1499  */
1500 struct tstorm_eth_st_context {
1501         u32 __reserved0[28];
1502 };
1503
1504 /*
1505  * The eth aggregative context section of Xstorm
1506  */
1507 struct xstorm_eth_extra_ag_context_section {
1508 #if defined(__BIG_ENDIAN)
1509         u8 __tcp_agg_vars1;
1510         u8 __reserved50;
1511         u16 __mss;
1512 #elif defined(__LITTLE_ENDIAN)
1513         u16 __mss;
1514         u8 __reserved50;
1515         u8 __tcp_agg_vars1;
1516 #endif
1517         u32 __snd_nxt;
1518         u32 __tx_wnd;
1519         u32 __snd_una;
1520         u32 __reserved53;
1521 #if defined(__BIG_ENDIAN)
1522         u8 __agg_val8_th;
1523         u8 __agg_val8;
1524         u16 __tcp_agg_vars2;
1525 #elif defined(__LITTLE_ENDIAN)
1526         u16 __tcp_agg_vars2;
1527         u8 __agg_val8;
1528         u8 __agg_val8_th;
1529 #endif
1530         u32 __reserved58;
1531         u32 __reserved59;
1532         u32 __reserved60;
1533         u32 __reserved61;
1534 #if defined(__BIG_ENDIAN)
1535         u16 __agg_val7_th;
1536         u16 __agg_val7;
1537 #elif defined(__LITTLE_ENDIAN)
1538         u16 __agg_val7;
1539         u16 __agg_val7_th;
1540 #endif
1541 #if defined(__BIG_ENDIAN)
1542         u8 __tcp_agg_vars5;
1543         u8 __tcp_agg_vars4;
1544         u8 __tcp_agg_vars3;
1545         u8 __reserved62;
1546 #elif defined(__LITTLE_ENDIAN)
1547         u8 __reserved62;
1548         u8 __tcp_agg_vars3;
1549         u8 __tcp_agg_vars4;
1550         u8 __tcp_agg_vars5;
1551 #endif
1552         u32 __tcp_agg_vars6;
1553 #if defined(__BIG_ENDIAN)
1554         u16 __agg_misc6;
1555         u16 __tcp_agg_vars7;
1556 #elif defined(__LITTLE_ENDIAN)
1557         u16 __tcp_agg_vars7;
1558         u16 __agg_misc6;
1559 #endif
1560         u32 __agg_val10;
1561         u32 __agg_val10_th;
1562 #if defined(__BIG_ENDIAN)
1563         u16 __reserved3;
1564         u8 __reserved2;
1565         u8 __da_only_cnt;
1566 #elif defined(__LITTLE_ENDIAN)
1567         u8 __da_only_cnt;
1568         u8 __reserved2;
1569         u16 __reserved3;
1570 #endif
1571 };
1572
1573 /*
1574  * The eth aggregative context of Xstorm
1575  */
1576 struct xstorm_eth_ag_context {
1577 #if defined(__BIG_ENDIAN)
1578         u16 __bd_prod;
1579         u8 __agg_vars1;
1580         u8 __state;
1581 #elif defined(__LITTLE_ENDIAN)
1582         u8 __state;
1583         u8 __agg_vars1;
1584         u16 __bd_prod;
1585 #endif
1586 #if defined(__BIG_ENDIAN)
1587         u8 cdu_reserved;
1588         u8 __agg_vars4;
1589         u8 __agg_vars3;
1590         u8 __agg_vars2;
1591 #elif defined(__LITTLE_ENDIAN)
1592         u8 __agg_vars2;
1593         u8 __agg_vars3;
1594         u8 __agg_vars4;
1595         u8 cdu_reserved;
1596 #endif
1597         u32 __more_packets_to_send;
1598 #if defined(__BIG_ENDIAN)
1599         u16 __agg_vars5;
1600         u16 __agg_val4_th;
1601 #elif defined(__LITTLE_ENDIAN)
1602         u16 __agg_val4_th;
1603         u16 __agg_vars5;
1604 #endif
1605         struct xstorm_eth_extra_ag_context_section __extra_section;
1606 #if defined(__BIG_ENDIAN)
1607         u16 __agg_vars7;
1608         u8 __agg_val3_th;
1609         u8 __agg_vars6;
1610 #elif defined(__LITTLE_ENDIAN)
1611         u8 __agg_vars6;
1612         u8 __agg_val3_th;
1613         u16 __agg_vars7;
1614 #endif
1615 #if defined(__BIG_ENDIAN)
1616         u16 __agg_val11_th;
1617         u16 __agg_val11;
1618 #elif defined(__LITTLE_ENDIAN)
1619         u16 __agg_val11;
1620         u16 __agg_val11_th;
1621 #endif
1622 #if defined(__BIG_ENDIAN)
1623         u8 __reserved1;
1624         u8 __agg_val6_th;
1625         u16 __agg_val9;
1626 #elif defined(__LITTLE_ENDIAN)
1627         u16 __agg_val9;
1628         u8 __agg_val6_th;
1629         u8 __reserved1;
1630 #endif
1631 #if defined(__BIG_ENDIAN)
1632         u16 __agg_val2_th;
1633         u16 __agg_val2;
1634 #elif defined(__LITTLE_ENDIAN)
1635         u16 __agg_val2;
1636         u16 __agg_val2_th;
1637 #endif
1638         u32 __agg_vars8;
1639 #if defined(__BIG_ENDIAN)
1640         u16 __agg_misc0;
1641         u16 __agg_val4;
1642 #elif defined(__LITTLE_ENDIAN)
1643         u16 __agg_val4;
1644         u16 __agg_misc0;
1645 #endif
1646 #if defined(__BIG_ENDIAN)
1647         u8 __agg_val3;
1648         u8 __agg_val6;
1649         u8 __agg_val5_th;
1650         u8 __agg_val5;
1651 #elif defined(__LITTLE_ENDIAN)
1652         u8 __agg_val5;
1653         u8 __agg_val5_th;
1654         u8 __agg_val6;
1655         u8 __agg_val3;
1656 #endif
1657 #if defined(__BIG_ENDIAN)
1658         u16 __agg_misc1;
1659         u16 __bd_ind_max_val;
1660 #elif defined(__LITTLE_ENDIAN)
1661         u16 __bd_ind_max_val;
1662         u16 __agg_misc1;
1663 #endif
1664         u32 __reserved57;
1665         u32 __agg_misc4;
1666         u32 __agg_misc5;
1667 };
1668
1669 /*
1670  * The eth extra aggregative context section of Tstorm
1671  */
1672 struct tstorm_eth_extra_ag_context_section {
1673         u32 __agg_val1;
1674 #if defined(__BIG_ENDIAN)
1675         u8 __tcp_agg_vars2;
1676         u8 __agg_val3;
1677         u16 __agg_val2;
1678 #elif defined(__LITTLE_ENDIAN)
1679         u16 __agg_val2;
1680         u8 __agg_val3;
1681         u8 __tcp_agg_vars2;
1682 #endif
1683 #if defined(__BIG_ENDIAN)
1684         u16 __agg_val5;
1685         u8 __agg_val6;
1686         u8 __tcp_agg_vars3;
1687 #elif defined(__LITTLE_ENDIAN)
1688         u8 __tcp_agg_vars3;
1689         u8 __agg_val6;
1690         u16 __agg_val5;
1691 #endif
1692         u32 __reserved63;
1693         u32 __reserved64;
1694         u32 __reserved65;
1695         u32 __reserved66;
1696         u32 __reserved67;
1697         u32 __tcp_agg_vars1;
1698         u32 __reserved61;
1699         u32 __reserved62;
1700         u32 __reserved2;
1701 };
1702
1703 /*
1704  * The eth aggregative context of Tstorm
1705  */
1706 struct tstorm_eth_ag_context {
1707 #if defined(__BIG_ENDIAN)
1708         u16 __reserved54;
1709         u8 __agg_vars1;
1710         u8 __state;
1711 #elif defined(__LITTLE_ENDIAN)
1712         u8 __state;
1713         u8 __agg_vars1;
1714         u16 __reserved54;
1715 #endif
1716 #if defined(__BIG_ENDIAN)
1717         u16 __agg_val4;
1718         u16 __agg_vars2;
1719 #elif defined(__LITTLE_ENDIAN)
1720         u16 __agg_vars2;
1721         u16 __agg_val4;
1722 #endif
1723         struct tstorm_eth_extra_ag_context_section __extra_section;
1724 };
1725
1726 /*
1727  * The eth aggregative context of Cstorm
1728  */
1729 struct cstorm_eth_ag_context {
1730         u32 __agg_vars1;
1731 #if defined(__BIG_ENDIAN)
1732         u8 __aux1_th;
1733         u8 __aux1_val;
1734         u16 __agg_vars2;
1735 #elif defined(__LITTLE_ENDIAN)
1736         u16 __agg_vars2;
1737         u8 __aux1_val;
1738         u8 __aux1_th;
1739 #endif
1740         u32 __num_of_treated_packet;
1741         u32 __last_packet_treated;
1742 #if defined(__BIG_ENDIAN)
1743         u16 __reserved58;
1744         u16 __reserved57;
1745 #elif defined(__LITTLE_ENDIAN)
1746         u16 __reserved57;
1747         u16 __reserved58;
1748 #endif
1749 #if defined(__BIG_ENDIAN)
1750         u8 __reserved62;
1751         u8 __reserved61;
1752         u8 __reserved60;
1753         u8 __reserved59;
1754 #elif defined(__LITTLE_ENDIAN)
1755         u8 __reserved59;
1756         u8 __reserved60;
1757         u8 __reserved61;
1758         u8 __reserved62;
1759 #endif
1760 #if defined(__BIG_ENDIAN)
1761         u16 __reserved64;
1762         u16 __reserved63;
1763 #elif defined(__LITTLE_ENDIAN)
1764         u16 __reserved63;
1765         u16 __reserved64;
1766 #endif
1767         u32 __reserved65;
1768 #if defined(__BIG_ENDIAN)
1769         u16 __agg_vars3;
1770         u16 __rq_inv_cnt;
1771 #elif defined(__LITTLE_ENDIAN)
1772         u16 __rq_inv_cnt;
1773         u16 __agg_vars3;
1774 #endif
1775 #if defined(__BIG_ENDIAN)
1776         u16 __packet_index_th;
1777         u16 __packet_index;
1778 #elif defined(__LITTLE_ENDIAN)
1779         u16 __packet_index;
1780         u16 __packet_index_th;
1781 #endif
1782 };
1783
1784 /*
1785  * The eth aggregative context of Ustorm
1786  */
1787 struct ustorm_eth_ag_context {
1788 #if defined(__BIG_ENDIAN)
1789         u8 __aux_counter_flags;
1790         u8 __agg_vars2;
1791         u8 __agg_vars1;
1792         u8 __state;
1793 #elif defined(__LITTLE_ENDIAN)
1794         u8 __state;
1795         u8 __agg_vars1;
1796         u8 __agg_vars2;
1797         u8 __aux_counter_flags;
1798 #endif
1799 #if defined(__BIG_ENDIAN)
1800         u8 cdu_usage;
1801         u8 __agg_misc2;
1802         u16 __agg_misc1;
1803 #elif defined(__LITTLE_ENDIAN)
1804         u16 __agg_misc1;
1805         u8 __agg_misc2;
1806         u8 cdu_usage;
1807 #endif
1808         u32 __agg_misc4;
1809 #if defined(__BIG_ENDIAN)
1810         u8 __agg_val3_th;
1811         u8 __agg_val3;
1812         u16 __agg_misc3;
1813 #elif defined(__LITTLE_ENDIAN)
1814         u16 __agg_misc3;
1815         u8 __agg_val3;
1816         u8 __agg_val3_th;
1817 #endif
1818         u32 __agg_val1;
1819         u32 __agg_misc4_th;
1820 #if defined(__BIG_ENDIAN)
1821         u16 __agg_val2_th;
1822         u16 __agg_val2;
1823 #elif defined(__LITTLE_ENDIAN)
1824         u16 __agg_val2;
1825         u16 __agg_val2_th;
1826 #endif
1827 #if defined(__BIG_ENDIAN)
1828         u16 __reserved2;
1829         u8 __decision_rules;
1830         u8 __decision_rule_enable_bits;
1831 #elif defined(__LITTLE_ENDIAN)
1832         u8 __decision_rule_enable_bits;
1833         u8 __decision_rules;
1834         u16 __reserved2;
1835 #endif
1836 };
1837
1838 /*
1839  * Timers connection context
1840  */
1841 struct timers_block_context {
1842         u32 __reserved_0;
1843         u32 __reserved_1;
1844         u32 __reserved_2;
1845         u32 flags;
1846 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1847 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1848 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1849 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1850 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1851 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1852 };
1853
1854 /*
1855  * structure for easy accessibility to assembler
1856  */
1857 struct eth_tx_bd_flags {
1858         u8 as_bitfield;
1859 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1860 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1861 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1862 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1863 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1864 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1865 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1866 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1867 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1868 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1869 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1870 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1871 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1872 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1873 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1874 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1875 };
1876
1877 /*
1878  * The eth Tx Buffer Descriptor
1879  */
1880 struct eth_tx_bd {
1881         __le32 addr_lo;
1882         __le32 addr_hi;
1883         __le16 nbd;
1884         __le16 nbytes;
1885         __le16 vlan;
1886         struct eth_tx_bd_flags bd_flags;
1887         u8 general_data;
1888 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1889 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1890 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1891 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1892 };
1893
1894 /*
1895  * Tx parsing BD structure for ETH,Relevant in START
1896  */
1897 struct eth_tx_parse_bd {
1898         u8 global_data;
1899 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1900 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1901 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1902 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1903 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1904 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1905 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1906 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1907 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1908 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1909         u8 tcp_flags;
1910 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1911 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1912 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1913 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1914 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1915 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1916 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1917 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1918 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1919 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1920 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1921 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1922 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1923 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1924 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1925 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1926         u8 ip_hlen;
1927         s8 cs_offset;
1928         __le16 total_hlen;
1929         __le16 lso_mss;
1930         __le16 tcp_pseudo_csum;
1931         __le16 ip_id;
1932         __le32 tcp_send_seq;
1933 };
1934
1935 /*
1936  * The last BD in the BD memory will hold a pointer to the next BD memory
1937  */
1938 struct eth_tx_next_bd {
1939         u32 addr_lo;
1940         u32 addr_hi;
1941         u8 reserved[8];
1942 };
1943
1944 /*
1945  * union for 3 Bd types
1946  */
1947 union eth_tx_bd_types {
1948         struct eth_tx_bd reg_bd;
1949         struct eth_tx_parse_bd parse_bd;
1950         struct eth_tx_next_bd next_bd;
1951 };
1952
1953 /*
1954  * The eth storm context of Xstorm
1955  */
1956 struct xstorm_eth_st_context {
1957         u32 tx_bd_page_base_lo;
1958         u32 tx_bd_page_base_hi;
1959 #if defined(__BIG_ENDIAN)
1960         u16 tx_bd_cons;
1961         u8 statistics_data;
1962 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1963 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1964 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1965 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1966         u8 __local_tx_bd_prod;
1967 #elif defined(__LITTLE_ENDIAN)
1968         u8 __local_tx_bd_prod;
1969         u8 statistics_data;
1970 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1971 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1972 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1973 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1974         u16 tx_bd_cons;
1975 #endif
1976         u32 db_data_addr_lo;
1977         u32 db_data_addr_hi;
1978         u32 __pkt_cons;
1979         u32 __gso_next;
1980         u32 is_eth_conn_1b;
1981         union eth_tx_bd_types __bds[13];
1982 };
1983
1984 /*
1985  * The eth storm context of Cstorm
1986  */
1987 struct cstorm_eth_st_context {
1988 #if defined(__BIG_ENDIAN)
1989         u16 __reserved0;
1990         u8 sb_index_number;
1991         u8 status_block_id;
1992 #elif defined(__LITTLE_ENDIAN)
1993         u8 status_block_id;
1994         u8 sb_index_number;
1995         u16 __reserved0;
1996 #endif
1997         u32 __reserved1[3];
1998 };
1999
2000 /*
2001  * Ethernet connection context
2002  */
2003 struct eth_context {
2004         struct ustorm_eth_st_context ustorm_st_context;
2005         struct tstorm_eth_st_context tstorm_st_context;
2006         struct xstorm_eth_ag_context xstorm_ag_context;
2007         struct tstorm_eth_ag_context tstorm_ag_context;
2008         struct cstorm_eth_ag_context cstorm_ag_context;
2009         struct ustorm_eth_ag_context ustorm_ag_context;
2010         struct timers_block_context timers_context;
2011         struct xstorm_eth_st_context xstorm_st_context;
2012         struct cstorm_eth_st_context cstorm_st_context;
2013 };
2014
2015
2016 /*
2017  * Ethernet doorbell
2018  */
2019 struct eth_tx_doorbell {
2020 #if defined(__BIG_ENDIAN)
2021         u16 npackets;
2022         u8 params;
2023 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2024 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2025 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2026 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2027 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2028 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2029         struct doorbell_hdr hdr;
2030 #elif defined(__LITTLE_ENDIAN)
2031         struct doorbell_hdr hdr;
2032         u8 params;
2033 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2034 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2035 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2036 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2037 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2038 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2039         u16 npackets;
2040 #endif
2041 };
2042
2043
2044 /*
2045  * ustorm status block
2046  */
2047 struct ustorm_def_status_block {
2048         __le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2049         __le16 status_block_index;
2050         u8 func;
2051         u8 status_block_id;
2052         __le32 __flags;
2053 };
2054
2055 /*
2056  * cstorm status block
2057  */
2058 struct cstorm_def_status_block {
2059         __le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2060         __le16 status_block_index;
2061         u8 func;
2062         u8 status_block_id;
2063         __le32 __flags;
2064 };
2065
2066 /*
2067  * xstorm status block
2068  */
2069 struct xstorm_def_status_block {
2070         __le16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2071         __le16 status_block_index;
2072         u8 func;
2073         u8 status_block_id;
2074         __le32 __flags;
2075 };
2076
2077 /*
2078  * tstorm status block
2079  */
2080 struct tstorm_def_status_block {
2081         __le16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2082         __le16 status_block_index;
2083         u8 func;
2084         u8 status_block_id;
2085         __le32 __flags;
2086 };
2087
2088 /*
2089  * host status block
2090  */
2091 struct host_def_status_block {
2092         struct atten_def_status_block atten_status_block;
2093         struct ustorm_def_status_block u_def_status_block;
2094         struct cstorm_def_status_block c_def_status_block;
2095         struct xstorm_def_status_block x_def_status_block;
2096         struct tstorm_def_status_block t_def_status_block;
2097 };
2098
2099
2100 /*
2101  * ustorm status block
2102  */
2103 struct ustorm_status_block {
2104         __le16 index_values[HC_USTORM_SB_NUM_INDICES];
2105         __le16 status_block_index;
2106         u8 func;
2107         u8 status_block_id;
2108         __le32 __flags;
2109 };
2110
2111 /*
2112  * cstorm status block
2113  */
2114 struct cstorm_status_block {
2115         __le16 index_values[HC_CSTORM_SB_NUM_INDICES];
2116         __le16 status_block_index;
2117         u8 func;
2118         u8 status_block_id;
2119         __le32 __flags;
2120 };
2121
2122 /*
2123  * host status block
2124  */
2125 struct host_status_block {
2126         struct ustorm_status_block u_status_block;
2127         struct cstorm_status_block c_status_block;
2128 };
2129
2130
2131 /*
2132  * The data for RSS setup ramrod
2133  */
2134 struct eth_client_setup_ramrod_data {
2135         u32 client_id;
2136         u8 is_rdma;
2137         u8 is_fcoe;
2138         u16 reserved1;
2139 };
2140
2141
2142 /*
2143  * L2 dynamic host coalescing init parameters
2144  */
2145 struct eth_dynamic_hc_config {
2146         u32 threshold[3];
2147         u8 hc_timeout[4];
2148 };
2149
2150
2151 /*
2152  * regular eth FP CQE parameters struct
2153  */
2154 struct eth_fast_path_rx_cqe {
2155         u8 type_error_flags;
2156 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2157 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2158 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2159 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2160 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2161 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2162 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2163 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2164 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2165 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2166 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2167 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2168 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2169 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2170         u8 status_flags;
2171 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2172 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2173 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2174 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2175 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2176 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2177 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2178 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2179 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2180 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2181 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2182 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2183         u8 placement_offset;
2184         u8 queue_index;
2185         __le32 rss_hash_result;
2186         __le16 vlan_tag;
2187         __le16 pkt_len;
2188         __le16 len_on_bd;
2189         struct parsing_flags pars_flags;
2190         __le16 sgl[8];
2191 };
2192
2193
2194 /*
2195  * The data for RSS setup ramrod
2196  */
2197 struct eth_halt_ramrod_data {
2198         u32 client_id;
2199         u32 reserved0;
2200 };
2201
2202
2203 /*
2204  * The data for statistics query ramrod
2205  */
2206 struct eth_query_ramrod_data {
2207 #if defined(__BIG_ENDIAN)
2208         u8 reserved0;
2209         u8 collect_port;
2210         u16 drv_counter;
2211 #elif defined(__LITTLE_ENDIAN)
2212         u16 drv_counter;
2213         u8 collect_port;
2214         u8 reserved0;
2215 #endif
2216         u32 ctr_id_vector;
2217 };
2218
2219
2220 /*
2221  * Place holder for ramrods protocol specific data
2222  */
2223 struct ramrod_data {
2224         __le32 data_lo;
2225         __le32 data_hi;
2226 };
2227
2228 /*
2229  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2230  */
2231 union eth_ramrod_data {
2232         struct ramrod_data general;
2233 };
2234
2235
2236 /*
2237  * Eth Rx Cqe structure- general structure for ramrods
2238  */
2239 struct common_ramrod_eth_rx_cqe {
2240         u8 ramrod_type;
2241 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2242 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2243 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2244 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
2245         u8 conn_type;
2246         __le16 reserved1;
2247         __le32 conn_and_cmd_data;
2248 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2249 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2250 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2251 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2252         struct ramrod_data protocol_data;
2253         __le32 reserved2[4];
2254 };
2255
2256 /*
2257  * Rx Last CQE in page (in ETH)
2258  */
2259 struct eth_rx_cqe_next_page {
2260         __le32 addr_lo;
2261         __le32 addr_hi;
2262         __le32 reserved[6];
2263 };
2264
2265 /*
2266  * union for all eth rx cqe types (fix their sizes)
2267  */
2268 union eth_rx_cqe {
2269         struct eth_fast_path_rx_cqe fast_path_cqe;
2270         struct common_ramrod_eth_rx_cqe ramrod_cqe;
2271         struct eth_rx_cqe_next_page next_page_cqe;
2272 };
2273
2274
2275 /*
2276  * common data for all protocols
2277  */
2278 struct spe_hdr {
2279         __le32 conn_and_cmd_data;
2280 #define SPE_HDR_CID (0xFFFFFF<<0)
2281 #define SPE_HDR_CID_SHIFT 0
2282 #define SPE_HDR_CMD_ID (0xFF<<24)
2283 #define SPE_HDR_CMD_ID_SHIFT 24
2284         __le16 type;
2285 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2286 #define SPE_HDR_CONN_TYPE_SHIFT 0
2287 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2288 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2289         __le16 reserved;
2290 };
2291
2292 /*
2293  * Ethernet slow path element
2294  */
2295 union eth_specific_data {
2296         u8 protocol_data[8];
2297         struct regpair mac_config_addr;
2298         struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2299         struct eth_halt_ramrod_data halt_ramrod_data;
2300         struct regpair leading_cqe_addr;
2301         struct regpair update_data_addr;
2302         struct eth_query_ramrod_data query_ramrod_data;
2303 };
2304
2305 /*
2306  * Ethernet slow path element
2307  */
2308 struct eth_spe {
2309         struct spe_hdr hdr;
2310         union eth_specific_data data;
2311 };
2312
2313
2314 /*
2315  * doorbell data in host memory
2316  */
2317 struct eth_tx_db_data {
2318         __le32 packets_prod;
2319         __le16 bds_prod;
2320         __le16 reserved;
2321 };
2322
2323
2324 /*
2325  * Common configuration parameters per function in Tstorm
2326  */
2327 struct tstorm_eth_function_common_config {
2328 #if defined(__BIG_ENDIAN)
2329         u8 leading_client_id;
2330         u8 rss_result_mask;
2331         u16 config_flags;
2332 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2333 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2334 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2335 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2336 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2337 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2338 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2339 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2340 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2341 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2342 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2343 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2344 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2345 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2346 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2347 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2348 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2349 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2350 #elif defined(__LITTLE_ENDIAN)
2351         u16 config_flags;
2352 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2353 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2354 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2355 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2356 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2357 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2358 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2359 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2360 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2361 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2362 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2363 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2364 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2365 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2366 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2367 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2368 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2369 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2370         u8 rss_result_mask;
2371         u8 leading_client_id;
2372 #endif
2373         u16 vlan_id[2];
2374 };
2375
2376 /*
2377  * parameters for eth update ramrod
2378  */
2379 struct eth_update_ramrod_data {
2380         struct tstorm_eth_function_common_config func_config;
2381         u8 indirectionTable[128];
2382 };
2383
2384
2385 /*
2386  * MAC filtering configuration command header
2387  */
2388 struct mac_configuration_hdr {
2389         u8 length;
2390         u8 offset;
2391         u16 client_id;
2392         u32 reserved1;
2393 };
2394
2395 /*
2396  * MAC address in list for ramrod
2397  */
2398 struct tstorm_cam_entry {
2399         __le16 lsb_mac_addr;
2400         __le16 middle_mac_addr;
2401         __le16 msb_mac_addr;
2402         __le16 flags;
2403 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2404 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2405 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2406 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2407 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2408 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2409 };
2410
2411 /*
2412  * MAC filtering: CAM target table entry
2413  */
2414 struct tstorm_cam_target_table_entry {
2415         u8 flags;
2416 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2417 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2418 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2419 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2420 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2421 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2422 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2423 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2424 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2425 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2426         u8 client_id;
2427         u16 vlan_id;
2428 };
2429
2430 /*
2431  * MAC address in list for ramrod
2432  */
2433 struct mac_configuration_entry {
2434         struct tstorm_cam_entry cam_entry;
2435         struct tstorm_cam_target_table_entry target_table_entry;
2436 };
2437
2438 /*
2439  * MAC filtering configuration command
2440  */
2441 struct mac_configuration_cmd {
2442         struct mac_configuration_hdr hdr;
2443         struct mac_configuration_entry config_table[64];
2444 };
2445
2446
2447 /*
2448  * MAC address in list for ramrod
2449  */
2450 struct mac_configuration_entry_e1h {
2451         __le16 lsb_mac_addr;
2452         __le16 middle_mac_addr;
2453         __le16 msb_mac_addr;
2454         __le16 vlan_id;
2455         __le16 e1hov_id;
2456         u8 client_id;
2457         u8 flags;
2458 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2459 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2460 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2461 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2462 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2463 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2464 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2465 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2466 };
2467
2468 /*
2469  * MAC filtering configuration command
2470  */
2471 struct mac_configuration_cmd_e1h {
2472         struct mac_configuration_hdr hdr;
2473         struct mac_configuration_entry_e1h config_table[32];
2474 };
2475
2476
2477 /*
2478  * approximate-match multicast filtering for E1H per function in Tstorm
2479  */
2480 struct tstorm_eth_approximate_match_multicast_filtering {
2481         u32 mcast_add_hash_bit_array[8];
2482 };
2483
2484
2485 /*
2486  * Configuration parameters per client in Tstorm
2487  */
2488 struct tstorm_eth_client_config {
2489 #if defined(__BIG_ENDIAN)
2490         u8 max_sges_for_packet;
2491         u8 statistics_counter_id;
2492         u16 mtu;
2493 #elif defined(__LITTLE_ENDIAN)
2494         u16 mtu;
2495         u8 statistics_counter_id;
2496         u8 max_sges_for_packet;
2497 #endif
2498 #if defined(__BIG_ENDIAN)
2499         u16 drop_flags;
2500 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2501 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2502 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2503 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2504 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2505 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2506 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2507 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2508 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2509 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2510         u16 config_flags;
2511 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2512 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2513 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2514 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2515 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2516 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2517 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2518 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2519 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2520 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2521 #elif defined(__LITTLE_ENDIAN)
2522         u16 config_flags;
2523 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2524 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2525 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2526 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2527 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2528 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2529 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2530 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2531 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2532 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2533         u16 drop_flags;
2534 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2535 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2536 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2537 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2538 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2539 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2540 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2541 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2542 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2543 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2544 #endif
2545 };
2546
2547
2548 /*
2549  * MAC filtering configuration parameters per port in Tstorm
2550  */
2551 struct tstorm_eth_mac_filter_config {
2552         u32 ucast_drop_all;
2553         u32 ucast_accept_all;
2554         u32 mcast_drop_all;
2555         u32 mcast_accept_all;
2556         u32 bcast_drop_all;
2557         u32 bcast_accept_all;
2558         u32 strict_vlan;
2559         u32 vlan_filter[2];
2560         u32 reserved;
2561 };
2562
2563
2564 /*
2565  * common flag to indicate existance of TPA.
2566  */
2567 struct tstorm_eth_tpa_exist {
2568 #if defined(__BIG_ENDIAN)
2569         u16 reserved1;
2570         u8 reserved0;
2571         u8 tpa_exist;
2572 #elif defined(__LITTLE_ENDIAN)
2573         u8 tpa_exist;
2574         u8 reserved0;
2575         u16 reserved1;
2576 #endif
2577         u32 reserved2;
2578 };
2579
2580
2581 /*
2582  * rx rings pause data for E1h only
2583  */
2584 struct ustorm_eth_rx_pause_data_e1h {
2585 #if defined(__BIG_ENDIAN)
2586         u16 bd_thr_low;
2587         u16 cqe_thr_low;
2588 #elif defined(__LITTLE_ENDIAN)
2589         u16 cqe_thr_low;
2590         u16 bd_thr_low;
2591 #endif
2592 #if defined(__BIG_ENDIAN)
2593         u16 cos;
2594         u16 sge_thr_low;
2595 #elif defined(__LITTLE_ENDIAN)
2596         u16 sge_thr_low;
2597         u16 cos;
2598 #endif
2599 #if defined(__BIG_ENDIAN)
2600         u16 bd_thr_high;
2601         u16 cqe_thr_high;
2602 #elif defined(__LITTLE_ENDIAN)
2603         u16 cqe_thr_high;
2604         u16 bd_thr_high;
2605 #endif
2606 #if defined(__BIG_ENDIAN)
2607         u16 reserved0;
2608         u16 sge_thr_high;
2609 #elif defined(__LITTLE_ENDIAN)
2610         u16 sge_thr_high;
2611         u16 reserved0;
2612 #endif
2613 };
2614
2615
2616 /*
2617  * Three RX producers for ETH
2618  */
2619 struct ustorm_eth_rx_producers {
2620 #if defined(__BIG_ENDIAN)
2621         u16 bd_prod;
2622         u16 cqe_prod;
2623 #elif defined(__LITTLE_ENDIAN)
2624         u16 cqe_prod;
2625         u16 bd_prod;
2626 #endif
2627 #if defined(__BIG_ENDIAN)
2628         u16 reserved;
2629         u16 sge_prod;
2630 #elif defined(__LITTLE_ENDIAN)
2631         u16 sge_prod;
2632         u16 reserved;
2633 #endif
2634 };
2635
2636
2637 /*
2638  * per-port SAFC demo variables
2639  */
2640 struct cmng_flags_per_port {
2641         u8 con_number[NUM_OF_PROTOCOLS];
2642         u32 cmng_enables;
2643 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2644 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2645 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2646 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2647 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2648 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2649 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2650 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2651 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2652 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2653 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
2654 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
2655 };
2656
2657
2658 /*
2659  * per-port rate shaping variables
2660  */
2661 struct rate_shaping_vars_per_port {
2662         u32 rs_periodic_timeout;
2663         u32 rs_threshold;
2664 };
2665
2666
2667 /*
2668  * per-port fairness variables
2669  */
2670 struct fairness_vars_per_port {
2671         u32 upper_bound;
2672         u32 fair_threshold;
2673         u32 fairness_timeout;
2674 };
2675
2676
2677 /*
2678  * per-port SAFC variables
2679  */
2680 struct safc_struct_per_port {
2681 #if defined(__BIG_ENDIAN)
2682         u16 __reserved1;
2683         u8 __reserved0;
2684         u8 safc_timeout_usec;
2685 #elif defined(__LITTLE_ENDIAN)
2686         u8 safc_timeout_usec;
2687         u8 __reserved0;
2688         u16 __reserved1;
2689 #endif
2690         u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2691 };
2692
2693
2694 /*
2695  * Per-port congestion management variables
2696  */
2697 struct cmng_struct_per_port {
2698         struct rate_shaping_vars_per_port rs_vars;
2699         struct fairness_vars_per_port fair_vars;
2700         struct safc_struct_per_port safc_vars;
2701         struct cmng_flags_per_port flags;
2702 };
2703
2704
2705 /*
2706  * Protocol-common statistics collected by the Xstorm (per client)
2707  */
2708 struct xstorm_per_client_stats {
2709         struct regpair total_sent_bytes;
2710         __le32 total_sent_pkts;
2711         __le32 unicast_pkts_sent;
2712         struct regpair unicast_bytes_sent;
2713         struct regpair multicast_bytes_sent;
2714         __le32 multicast_pkts_sent;
2715         __le32 broadcast_pkts_sent;
2716         struct regpair broadcast_bytes_sent;
2717         __le16 stats_counter;
2718         __le16 reserved0;
2719         __le32 reserved1;
2720 };
2721
2722
2723 /*
2724  * Common statistics collected by the Xstorm (per port)
2725  */
2726 struct xstorm_common_stats {
2727  struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2728 };
2729
2730
2731 /*
2732  * Protocol-common statistics collected by the Tstorm (per port)
2733  */
2734 struct tstorm_per_port_stats {
2735         __le32 mac_filter_discard;
2736         __le32 xxoverflow_discard;
2737         __le32 brb_truncate_discard;
2738         __le32 mac_discard;
2739 };
2740
2741
2742 /*
2743  * Protocol-common statistics collected by the Tstorm (per client)
2744  */
2745 struct tstorm_per_client_stats {
2746         struct regpair total_rcv_bytes;
2747         struct regpair rcv_unicast_bytes;
2748         struct regpair rcv_broadcast_bytes;
2749         struct regpair rcv_multicast_bytes;
2750         struct regpair rcv_error_bytes;
2751         __le32 checksum_discard;
2752         __le32 packets_too_big_discard;
2753         __le32 total_rcv_pkts;
2754         __le32 rcv_unicast_pkts;
2755         __le32 rcv_broadcast_pkts;
2756         __le32 rcv_multicast_pkts;
2757         __le32 no_buff_discard;
2758         __le32 ttl0_discard;
2759         __le16 stats_counter;
2760         __le16 reserved0;
2761         __le32 reserved1;
2762 };
2763
2764 /*
2765  * Protocol-common statistics collected by the Tstorm
2766  */
2767 struct tstorm_common_stats {
2768         struct tstorm_per_port_stats port_statistics;
2769  struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2770 };
2771
2772 /*
2773  * Protocol-common statistics collected by the Ustorm (per client)
2774  */
2775 struct ustorm_per_client_stats {
2776         struct regpair ucast_no_buff_bytes;
2777         struct regpair mcast_no_buff_bytes;
2778         struct regpair bcast_no_buff_bytes;
2779         __le32 ucast_no_buff_pkts;
2780         __le32 mcast_no_buff_pkts;
2781         __le32 bcast_no_buff_pkts;
2782         __le16 stats_counter;
2783         __le16 reserved0;
2784 };
2785
2786 /*
2787  * Protocol-common statistics collected by the Ustorm
2788  */
2789 struct ustorm_common_stats {
2790  struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
2791 };
2792
2793 /*
2794  * Eth statistics query structure for the eth_stats_query ramrod
2795  */
2796 struct eth_stats_query {
2797         struct xstorm_common_stats xstorm_common;
2798         struct tstorm_common_stats tstorm_common;
2799         struct ustorm_common_stats ustorm_common;
2800 };
2801
2802
2803 /*
2804  * per-vnic fairness variables
2805  */
2806 struct fairness_vars_per_vn {
2807         u32 cos_credit_delta[MAX_COS_NUMBER];
2808         u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2809         u32 vn_credit_delta;
2810         u32 __reserved0;
2811 };
2812
2813
2814 /*
2815  * FW version stored in the Xstorm RAM
2816  */
2817 struct fw_version {
2818 #if defined(__BIG_ENDIAN)
2819         u8 engineering;
2820         u8 revision;
2821         u8 minor;
2822         u8 major;
2823 #elif defined(__LITTLE_ENDIAN)
2824         u8 major;
2825         u8 minor;
2826         u8 revision;
2827         u8 engineering;
2828 #endif
2829         u32 flags;
2830 #define FW_VERSION_OPTIMIZED (0x1<<0)
2831 #define FW_VERSION_OPTIMIZED_SHIFT 0
2832 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2833 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2834 #define FW_VERSION_CHIP_VERSION (0x3<<2)
2835 #define FW_VERSION_CHIP_VERSION_SHIFT 2
2836 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2837 #define __FW_VERSION_RESERVED_SHIFT 4
2838 };
2839
2840
2841 /*
2842  * FW version stored in first line of pram
2843  */
2844 struct pram_fw_version {
2845         u8 major;
2846         u8 minor;
2847         u8 revision;
2848         u8 engineering;
2849         u8 flags;
2850 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2851 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2852 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2853 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2854 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2855 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2856 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2857 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2858 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2859 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2860 };
2861
2862
2863 /*
2864  * a single rate shaping counter. can be used as protocol or vnic counter
2865  */
2866 struct rate_shaping_counter {
2867         u32 quota;
2868 #if defined(__BIG_ENDIAN)
2869         u16 __reserved0;
2870         u16 rate;
2871 #elif defined(__LITTLE_ENDIAN)
2872         u16 rate;
2873         u16 __reserved0;
2874 #endif
2875 };
2876
2877
2878 /*
2879  * per-vnic rate shaping variables
2880  */
2881 struct rate_shaping_vars_per_vn {
2882         struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2883         struct rate_shaping_counter vn_counter;
2884 };
2885
2886
2887 /*
2888  * The send queue element
2889  */
2890 struct slow_path_element {
2891         struct spe_hdr hdr;
2892         u8 protocol_data[8];
2893 };
2894
2895
2896 /*
2897  * eth/toe flags that indicate if to query
2898  */
2899 struct stats_indication_flags {
2900         u32 collect_eth;
2901         u32 collect_toe;
2902 };
2903
2904