Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / net / bnx2x / bnx2x_link.c
1 /* Copyright 2008-2011 Broadcom Corporation
2  *
3  * Unless you and Broadcom execute a separate written software license
4  * agreement governing use of this software, this software is licensed to you
5  * under the terms of the GNU General Public License version 2, available
6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7  *
8  * Notwithstanding the above, under no circumstances may you combine this
9  * software in any way with any other Broadcom software provided under a
10  * license other than the GPL, without Broadcom's express prior written
11  * consent.
12  *
13  * Written by Yaniv Rosner
14  *
15  */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
26
27 #include "bnx2x.h"
28
29 /********************************************************/
30 #define ETH_HLEN                        14
31 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
32 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
33 #define ETH_MIN_PACKET_SIZE             60
34 #define ETH_MAX_PACKET_SIZE             1500
35 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
36 #define MDIO_ACCESS_TIMEOUT             1000
37 #define BMAC_CONTROL_RX_ENABLE          2
38
39 /***********************************************************/
40 /*                      Shortcut definitions               */
41 /***********************************************************/
42
43 #define NIG_LATCH_BC_ENABLE_MI_INT 0
44
45 #define NIG_STATUS_EMAC0_MI_INT \
46                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
47 #define NIG_STATUS_XGXS0_LINK10G \
48                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
49 #define NIG_STATUS_XGXS0_LINK_STATUS \
50                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
51 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
52                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
53 #define NIG_STATUS_SERDES0_LINK_STATUS \
54                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
55 #define NIG_MASK_MI_INT \
56                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
57 #define NIG_MASK_XGXS0_LINK10G \
58                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
59 #define NIG_MASK_XGXS0_LINK_STATUS \
60                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
61 #define NIG_MASK_SERDES0_LINK_STATUS \
62                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
63
64 #define MDIO_AN_CL73_OR_37_COMPLETE \
65                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
66                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
67
68 #define XGXS_RESET_BITS \
69         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
70          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
71          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
72          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
73          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
74
75 #define SERDES_RESET_BITS \
76         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
77          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
78          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
80
81 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
82 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
83 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
84 #define AUTONEG_PARALLEL \
85                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
86 #define AUTONEG_SGMII_FIBER_AUTODET \
87                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
88 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
89
90 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
91                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
92 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
93                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
94 #define GP_STATUS_SPEED_MASK \
95                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
96 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
97 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
98 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
99 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
100 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
101 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
102 #define GP_STATUS_10G_HIG \
103                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
104 #define GP_STATUS_10G_CX4 \
105                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
106 #define GP_STATUS_12G_HIG \
107                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
108 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
109 #define GP_STATUS_13G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
110 #define GP_STATUS_15G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
111 #define GP_STATUS_16G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
112 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
113 #define GP_STATUS_10G_KX4 \
114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
115
116 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
117 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
118 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
119 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
120 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
121 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
122 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
123 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
124 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
125 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
126 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
127 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
128 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
129 #define LINK_12GTFD             LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
130 #define LINK_12GXFD             LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
131 #define LINK_12_5GTFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
132 #define LINK_12_5GXFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
133 #define LINK_13GTFD             LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
134 #define LINK_13GXFD             LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
135 #define LINK_15GTFD             LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
136 #define LINK_15GXFD             LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
137 #define LINK_16GTFD             LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
138 #define LINK_16GXFD             LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
139
140 #define PHY_XGXS_FLAG                   0x1
141 #define PHY_SGMII_FLAG                  0x2
142 #define PHY_SERDES_FLAG                 0x4
143
144 /* */
145 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
146         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
147         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
148
149
150 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
151         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
152         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
153         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
154
155 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
156         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
157         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
158
159 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
160         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
161 #define SFP_EEPROM_OPTIONS_SIZE                 2
162
163 #define EDC_MODE_LINEAR                         0x0022
164 #define EDC_MODE_LIMITING                               0x0044
165 #define EDC_MODE_PASSIVE_DAC                    0x0055
166
167
168 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
169 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
170 /**********************************************************/
171 /*                     INTERFACE                          */
172 /**********************************************************/
173
174 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
175         bnx2x_cl45_write(_bp, _phy, \
176                 (_phy)->def_md_devad, \
177                 (_bank + (_addr & 0xf)), \
178                 _val)
179
180 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
181         bnx2x_cl45_read(_bp, _phy, \
182                 (_phy)->def_md_devad, \
183                 (_bank + (_addr & 0xf)), \
184                 _val)
185
186 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
187 {
188         u32 val = REG_RD(bp, reg);
189
190         val |= bits;
191         REG_WR(bp, reg, val);
192         return val;
193 }
194
195 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
196 {
197         u32 val = REG_RD(bp, reg);
198
199         val &= ~bits;
200         REG_WR(bp, reg, val);
201         return val;
202 }
203
204 /******************************************************************/
205 /*                              ETS section                       */
206 /******************************************************************/
207 void bnx2x_ets_disabled(struct link_params *params)
208 {
209         /* ETS disabled configuration*/
210         struct bnx2x *bp = params->bp;
211
212         DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
213
214         /*
215          * mapping between entry  priority to client number (0,1,2 -debug and
216          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
217          * 3bits client num.
218          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
219          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
220          */
221
222         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
223         /*
224          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
225          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
226          * COS0 entry, 4 - COS1 entry.
227          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
228          * bit4   bit3    bit2   bit1     bit0
229          * MCP and debug are strict
230          */
231
232         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
233         /* defines which entries (clients) are subjected to WFQ arbitration */
234         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
235         /*
236          * For strict priority entries defines the number of consecutive
237          * slots for the highest priority.
238          */
239         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
240         /*
241          * mapping between the CREDIT_WEIGHT registers and actual client
242          * numbers
243          */
244         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
245         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
246         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
247
248         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
249         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
250         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
251         /* ETS mode disable */
252         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
253         /*
254          * If ETS mode is enabled (there is no strict priority) defines a WFQ
255          * weight for COS0/COS1.
256          */
257         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
258         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
259         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
260         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
261         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
262         /* Defines the number of consecutive slots for the strict priority */
263         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
264 }
265
266 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
267 {
268         /* ETS disabled configuration */
269         struct bnx2x *bp = params->bp;
270         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
271         /*
272          * defines which entries (clients) are subjected to WFQ arbitration
273          * COS0 0x8
274          * COS1 0x10
275          */
276         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
277         /*
278          * mapping between the ARB_CREDIT_WEIGHT registers and actual
279          * client numbers (WEIGHT_0 does not actually have to represent
280          * client 0)
281          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
282          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
283          */
284         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
285
286         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
287                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
288         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
289                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
290
291         /* ETS mode enabled*/
292         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
293
294         /* Defines the number of consecutive slots for the strict priority */
295         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
296         /*
297          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
298          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
299          * entry, 4 - COS1 entry.
300          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
301          * bit4   bit3    bit2     bit1    bit0
302          * MCP and debug are strict
303          */
304         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
305
306         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
307         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
308                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
309         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
310                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
311 }
312
313 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
314                         const u32 cos1_bw)
315 {
316         /* ETS disabled configuration*/
317         struct bnx2x *bp = params->bp;
318         const u32 total_bw = cos0_bw + cos1_bw;
319         u32 cos0_credit_weight = 0;
320         u32 cos1_credit_weight = 0;
321
322         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
323
324         if ((0 == total_bw) ||
325             (0 == cos0_bw) ||
326             (0 == cos1_bw)) {
327                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
328                 return;
329         }
330
331         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
332                 total_bw;
333         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
334                 total_bw;
335
336         bnx2x_ets_bw_limit_common(params);
337
338         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
339         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
340
341         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
342         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
343 }
344
345 u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
346 {
347         /* ETS disabled configuration*/
348         struct bnx2x *bp = params->bp;
349         u32 val = 0;
350
351         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
352         /*
353          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
354          * as strict.  Bits 0,1,2 - debug and management entries,
355          * 3 - COS0 entry, 4 - COS1 entry.
356          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
357          *  bit4   bit3   bit2      bit1     bit0
358          * MCP and debug are strict
359          */
360         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
361         /*
362          * For strict priority entries defines the number of consecutive slots
363          * for the highest priority.
364          */
365         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
366         /* ETS mode disable */
367         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
368         /* Defines the number of consecutive slots for the strict priority */
369         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
370
371         /* Defines the number of consecutive slots for the strict priority */
372         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
373
374         /*
375          * mapping between entry  priority to client number (0,1,2 -debug and
376          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
377          * 3bits client num.
378          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
379          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
380          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
381          */
382         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
383         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
384
385         return 0;
386 }
387 /******************************************************************/
388 /*                      ETS section                               */
389 /******************************************************************/
390
391 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
392                                      u32 pfc_frames_sent[2],
393                                      u32 pfc_frames_received[2])
394 {
395         /* Read pfc statistic */
396         struct bnx2x *bp = params->bp;
397         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
398                 NIG_REG_INGRESS_BMAC0_MEM;
399
400         DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
401
402         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
403                                         pfc_frames_sent, 2);
404
405         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
406                                         pfc_frames_received, 2);
407
408 }
409 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
410                                     u32 pfc_frames_sent[2],
411                                     u32 pfc_frames_received[2])
412 {
413         /* Read pfc statistic */
414         struct bnx2x *bp = params->bp;
415         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
416         u32 val_xon = 0;
417         u32 val_xoff = 0;
418
419         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
420
421         /* PFC received frames */
422         val_xoff = REG_RD(bp, emac_base +
423                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
424         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
425         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
426         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
427
428         pfc_frames_received[0] = val_xon + val_xoff;
429
430         /* PFC received sent */
431         val_xoff = REG_RD(bp, emac_base +
432                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
433         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
434         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
435         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
436
437         pfc_frames_sent[0] = val_xon + val_xoff;
438 }
439
440 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
441                          u32 pfc_frames_sent[2],
442                          u32 pfc_frames_received[2])
443 {
444         /* Read pfc statistic */
445         struct bnx2x *bp = params->bp;
446         u32 val = 0;
447         DP(NETIF_MSG_LINK, "pfc statistic\n");
448
449         if (!vars->link_up)
450                 return;
451
452         val = REG_RD(bp, MISC_REG_RESET_REG_2);
453         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
454             == 0) {
455                 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
456                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
457                                         pfc_frames_received);
458         } else {
459                 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
460                 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
461                                          pfc_frames_received);
462         }
463 }
464 /******************************************************************/
465 /*                      MAC/PBF section                           */
466 /******************************************************************/
467 static void bnx2x_emac_init(struct link_params *params,
468                             struct link_vars *vars)
469 {
470         /* reset and unreset the emac core */
471         struct bnx2x *bp = params->bp;
472         u8 port = params->port;
473         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
474         u32 val;
475         u16 timeout;
476
477         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
478                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
479         udelay(5);
480         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
481                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
482
483         /* init emac - use read-modify-write */
484         /* self clear reset */
485         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
486         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
487
488         timeout = 200;
489         do {
490                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
491                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
492                 if (!timeout) {
493                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
494                         return;
495                 }
496                 timeout--;
497         } while (val & EMAC_MODE_RESET);
498
499         /* Set mac address */
500         val = ((params->mac_addr[0] << 8) |
501                 params->mac_addr[1]);
502         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
503
504         val = ((params->mac_addr[2] << 24) |
505                (params->mac_addr[3] << 16) |
506                (params->mac_addr[4] << 8) |
507                 params->mac_addr[5]);
508         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
509 }
510
511 static u8 bnx2x_emac_enable(struct link_params *params,
512                             struct link_vars *vars, u8 lb)
513 {
514         struct bnx2x *bp = params->bp;
515         u8 port = params->port;
516         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
517         u32 val;
518
519         DP(NETIF_MSG_LINK, "enabling EMAC\n");
520
521         /* enable emac and not bmac */
522         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
523
524         /* ASIC */
525         if (vars->phy_flags & PHY_XGXS_FLAG) {
526                 u32 ser_lane = ((params->lane_config &
527                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
528                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
529
530                 DP(NETIF_MSG_LINK, "XGXS\n");
531                 /* select the master lanes (out of 0-3) */
532                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
533                 /* select XGXS */
534                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
535
536         } else { /* SerDes */
537                 DP(NETIF_MSG_LINK, "SerDes\n");
538                 /* select SerDes */
539                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
540         }
541
542         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
543                       EMAC_RX_MODE_RESET);
544         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
545                       EMAC_TX_MODE_RESET);
546
547         if (CHIP_REV_IS_SLOW(bp)) {
548                 /* config GMII mode */
549                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
550                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
551         } else { /* ASIC */
552                 /* pause enable/disable */
553                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
554                                EMAC_RX_MODE_FLOW_EN);
555
556                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
557                                (EMAC_TX_MODE_EXT_PAUSE_EN |
558                                 EMAC_TX_MODE_FLOW_EN));
559                 if (!(params->feature_config_flags &
560                       FEATURE_CONFIG_PFC_ENABLED)) {
561                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
562                                 bnx2x_bits_en(bp, emac_base +
563                                               EMAC_REG_EMAC_RX_MODE,
564                                               EMAC_RX_MODE_FLOW_EN);
565
566                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
567                                 bnx2x_bits_en(bp, emac_base +
568                                               EMAC_REG_EMAC_TX_MODE,
569                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
570                                                EMAC_TX_MODE_FLOW_EN));
571                 } else
572                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
573                                       EMAC_TX_MODE_FLOW_EN);
574         }
575
576         /* KEEP_VLAN_TAG, promiscuous */
577         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
578         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
579
580         /*
581          * Setting this bit causes MAC control frames (except for pause
582          * frames) to be passed on for processing. This setting has no
583          * affect on the operation of the pause frames. This bit effects
584          * all packets regardless of RX Parser packet sorting logic.
585          * Turn the PFC off to make sure we are in Xon state before
586          * enabling it.
587          */
588         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
589         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
590                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
591                 /* Enable PFC again */
592                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
593                         EMAC_REG_RX_PFC_MODE_RX_EN |
594                         EMAC_REG_RX_PFC_MODE_TX_EN |
595                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
596
597                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
598                         ((0x0101 <<
599                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
600                          (0x00ff <<
601                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
602                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
603         }
604         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
605
606         /* Set Loopback */
607         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
608         if (lb)
609                 val |= 0x810;
610         else
611                 val &= ~0x810;
612         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
613
614         /* enable emac */
615         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
616
617         /* enable emac for jumbo packets */
618         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
619                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
620                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
621
622         /* strip CRC */
623         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
624
625         /* disable the NIG in/out to the bmac */
626         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
627         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
628         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
629
630         /* enable the NIG in/out to the emac */
631         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
632         val = 0;
633         if ((params->feature_config_flags &
634               FEATURE_CONFIG_PFC_ENABLED) ||
635             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
636                 val = 1;
637
638         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
639         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
640
641         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
642
643         vars->mac_type = MAC_TYPE_EMAC;
644         return 0;
645 }
646
647 static void bnx2x_update_pfc_bmac1(struct link_params *params,
648                                    struct link_vars *vars)
649 {
650         u32 wb_data[2];
651         struct bnx2x *bp = params->bp;
652         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
653                 NIG_REG_INGRESS_BMAC0_MEM;
654
655         u32 val = 0x14;
656         if ((!(params->feature_config_flags &
657               FEATURE_CONFIG_PFC_ENABLED)) &&
658                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
659                 /* Enable BigMAC to react on received Pause packets */
660                 val |= (1<<5);
661         wb_data[0] = val;
662         wb_data[1] = 0;
663         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
664
665         /* tx control */
666         val = 0xc0;
667         if (!(params->feature_config_flags &
668               FEATURE_CONFIG_PFC_ENABLED) &&
669                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
670                 val |= 0x800000;
671         wb_data[0] = val;
672         wb_data[1] = 0;
673         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
674 }
675
676 static void bnx2x_update_pfc_bmac2(struct link_params *params,
677                                    struct link_vars *vars,
678                                    u8 is_lb)
679 {
680         /*
681          * Set rx control: Strip CRC and enable BigMAC to relay
682          * control packets to the system as well
683          */
684         u32 wb_data[2];
685         struct bnx2x *bp = params->bp;
686         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
687                 NIG_REG_INGRESS_BMAC0_MEM;
688         u32 val = 0x14;
689
690         if ((!(params->feature_config_flags &
691               FEATURE_CONFIG_PFC_ENABLED)) &&
692                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
693                 /* Enable BigMAC to react on received Pause packets */
694                 val |= (1<<5);
695         wb_data[0] = val;
696         wb_data[1] = 0;
697         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
698         udelay(30);
699
700         /* Tx control */
701         val = 0xc0;
702         if (!(params->feature_config_flags &
703                                 FEATURE_CONFIG_PFC_ENABLED) &&
704             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
705                 val |= 0x800000;
706         wb_data[0] = val;
707         wb_data[1] = 0;
708         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
709
710         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
711                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
712                 /* Enable PFC RX & TX & STATS and set 8 COS  */
713                 wb_data[0] = 0x0;
714                 wb_data[0] |= (1<<0);  /* RX */
715                 wb_data[0] |= (1<<1);  /* TX */
716                 wb_data[0] |= (1<<2);  /* Force initial Xon */
717                 wb_data[0] |= (1<<3);  /* 8 cos */
718                 wb_data[0] |= (1<<5);  /* STATS */
719                 wb_data[1] = 0;
720                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
721                             wb_data, 2);
722                 /* Clear the force Xon */
723                 wb_data[0] &= ~(1<<2);
724         } else {
725                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
726                 /* disable PFC RX & TX & STATS and set 8 COS */
727                 wb_data[0] = 0x8;
728                 wb_data[1] = 0;
729         }
730
731         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
732
733         /*
734          * Set Time (based unit is 512 bit time) between automatic
735          * re-sending of PP packets amd enable automatic re-send of
736          * Per-Priroity Packet as long as pp_gen is asserted and
737          * pp_disable is low.
738          */
739         val = 0x8000;
740         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
741                 val |= (1<<16); /* enable automatic re-send */
742
743         wb_data[0] = val;
744         wb_data[1] = 0;
745         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
746                     wb_data, 2);
747
748         /* mac control */
749         val = 0x3; /* Enable RX and TX */
750         if (is_lb) {
751                 val |= 0x4; /* Local loopback */
752                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
753         }
754         /* When PFC enabled, Pass pause frames towards the NIG. */
755         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
756                 val |= ((1<<6)|(1<<5));
757
758         wb_data[0] = val;
759         wb_data[1] = 0;
760         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
761 }
762
763 static void bnx2x_update_pfc_brb(struct link_params *params,
764                 struct link_vars *vars,
765                 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
766 {
767         struct bnx2x *bp = params->bp;
768         int set_pfc = params->feature_config_flags &
769                 FEATURE_CONFIG_PFC_ENABLED;
770
771         /* default - pause configuration */
772         u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
773         u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
774         u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
775         u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
776
777         if (set_pfc && pfc_params)
778                 /* First COS */
779                 if (!pfc_params->cos0_pauseable) {
780                         pause_xoff_th =
781                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
782                         pause_xon_th =
783                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
784                         full_xoff_th =
785                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
786                         full_xon_th =
787                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
788                 }
789         /*
790          * The number of free blocks below which the pause signal to class 0
791          * of MAC #n is asserted. n=0,1
792          */
793         REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
794         /*
795          * The number of free blocks above which the pause signal to class 0
796          * of MAC #n is de-asserted. n=0,1
797          */
798         REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
799         /*
800          * The number of free blocks below which the full signal to class 0
801          * of MAC #n is asserted. n=0,1
802          */
803         REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
804         /*
805          * The number of free blocks above which the full signal to class 0
806          * of MAC #n is de-asserted. n=0,1
807          */
808         REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
809
810         if (set_pfc && pfc_params) {
811                 /* Second COS */
812                 if (pfc_params->cos1_pauseable) {
813                         pause_xoff_th =
814                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
815                         pause_xon_th =
816                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
817                         full_xoff_th =
818                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
819                         full_xon_th =
820                           PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
821                 } else {
822                         pause_xoff_th =
823                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
824                         pause_xon_th =
825                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
826                         full_xoff_th =
827                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
828                         full_xon_th =
829                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
830                 }
831                 /*
832                  * The number of free blocks below which the pause signal to
833                  * class 1 of MAC #n is asserted. n=0,1
834                  */
835                 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
836                 /*
837                  * The number of free blocks above which the pause signal to
838                  * class 1 of MAC #n is de-asserted. n=0,1
839                  */
840                 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
841                 /*
842                  * The number of free blocks below which the full signal to
843                  * class 1 of MAC #n is asserted. n=0,1
844                  */
845                 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
846                 /*
847                  * The number of free blocks above which the full signal to
848                  * class 1 of MAC #n is de-asserted. n=0,1
849                  */
850                 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
851         }
852 }
853
854 static void bnx2x_update_pfc_nig(struct link_params *params,
855                 struct link_vars *vars,
856                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
857 {
858         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
859         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
860         u32 pkt_priority_to_cos = 0;
861         u32 val;
862         struct bnx2x *bp = params->bp;
863         int port = params->port;
864         int set_pfc = params->feature_config_flags &
865                 FEATURE_CONFIG_PFC_ENABLED;
866         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
867
868         /*
869          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
870          * MAC control frames (that are not pause packets)
871          * will be forwarded to the XCM.
872          */
873         xcm_mask = REG_RD(bp,
874                                 port ? NIG_REG_LLH1_XCM_MASK :
875                                 NIG_REG_LLH0_XCM_MASK);
876         /*
877          * nig params will override non PFC params, since it's possible to
878          * do transition from PFC to SAFC
879          */
880         if (set_pfc) {
881                 pause_enable = 0;
882                 llfc_out_en = 0;
883                 llfc_enable = 0;
884                 ppp_enable = 1;
885                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
886                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
887                 xcm0_out_en = 0;
888                 p0_hwpfc_enable = 1;
889         } else  {
890                 if (nig_params) {
891                         llfc_out_en = nig_params->llfc_out_en;
892                         llfc_enable = nig_params->llfc_enable;
893                         pause_enable = nig_params->pause_enable;
894                 } else  /*defaul non PFC mode - PAUSE */
895                         pause_enable = 1;
896
897                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
898                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
899                 xcm0_out_en = 1;
900         }
901
902         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
903                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
904         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
905                NIG_REG_LLFC_ENABLE_0, llfc_enable);
906         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
907                NIG_REG_PAUSE_ENABLE_0, pause_enable);
908
909         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
910                NIG_REG_PPP_ENABLE_0, ppp_enable);
911
912         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
913                NIG_REG_LLH0_XCM_MASK, xcm_mask);
914
915         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
916
917         /* output enable for RX_XCM # IF */
918         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
919
920         /* HW PFC TX enable */
921         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
922
923         /* 0x2 = BMAC, 0x1= EMAC */
924         switch (vars->mac_type) {
925         case MAC_TYPE_EMAC:
926                 val = 1;
927                 break;
928         case MAC_TYPE_BMAC:
929                 val = 0;
930                 break;
931         default:
932                 val = 0;
933                 break;
934         }
935         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
936
937         if (nig_params) {
938                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
939
940                 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
941                        NIG_REG_P0_RX_COS0_PRIORITY_MASK,
942                        nig_params->rx_cos0_priority_mask);
943
944                 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
945                        NIG_REG_P0_RX_COS1_PRIORITY_MASK,
946                        nig_params->rx_cos1_priority_mask);
947
948                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
949                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
950                        nig_params->llfc_high_priority_classes);
951
952                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
953                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
954                        nig_params->llfc_low_priority_classes);
955         }
956         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
957                NIG_REG_P0_PKT_PRIORITY_TO_COS,
958                pkt_priority_to_cos);
959 }
960
961
962 void bnx2x_update_pfc(struct link_params *params,
963                       struct link_vars *vars,
964                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
965 {
966         /*
967          * The PFC and pause are orthogonal to one another, meaning when
968          * PFC is enabled, the pause are disabled, and when PFC is
969          * disabled, pause are set according to the pause result.
970          */
971         u32 val;
972         struct bnx2x *bp = params->bp;
973
974         /* update NIG params */
975         bnx2x_update_pfc_nig(params, vars, pfc_params);
976
977         /* update BRB params */
978         bnx2x_update_pfc_brb(params, vars, pfc_params);
979
980         if (!vars->link_up)
981                 return;
982
983         val = REG_RD(bp, MISC_REG_RESET_REG_2);
984         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
985             == 0) {
986                 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
987                 bnx2x_emac_enable(params, vars, 0);
988                 return;
989         }
990
991         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
992         if (CHIP_IS_E2(bp))
993                 bnx2x_update_pfc_bmac2(params, vars, 0);
994         else
995                 bnx2x_update_pfc_bmac1(params, vars);
996
997         val = 0;
998         if ((params->feature_config_flags &
999               FEATURE_CONFIG_PFC_ENABLED) ||
1000             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1001                 val = 1;
1002         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1003 }
1004
1005 static u8 bnx2x_bmac1_enable(struct link_params *params,
1006                              struct link_vars *vars,
1007                              u8 is_lb)
1008 {
1009         struct bnx2x *bp = params->bp;
1010         u8 port = params->port;
1011         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1012                                NIG_REG_INGRESS_BMAC0_MEM;
1013         u32 wb_data[2];
1014         u32 val;
1015
1016         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
1017
1018         /* XGXS control */
1019         wb_data[0] = 0x3c;
1020         wb_data[1] = 0;
1021         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1022                     wb_data, 2);
1023
1024         /* tx MAC SA */
1025         wb_data[0] = ((params->mac_addr[2] << 24) |
1026                        (params->mac_addr[3] << 16) |
1027                        (params->mac_addr[4] << 8) |
1028                         params->mac_addr[5]);
1029         wb_data[1] = ((params->mac_addr[0] << 8) |
1030                         params->mac_addr[1]);
1031         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
1032
1033         /* mac control */
1034         val = 0x3;
1035         if (is_lb) {
1036                 val |= 0x4;
1037                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1038         }
1039         wb_data[0] = val;
1040         wb_data[1] = 0;
1041         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
1042
1043         /* set rx mtu */
1044         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1045         wb_data[1] = 0;
1046         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
1047
1048         bnx2x_update_pfc_bmac1(params, vars);
1049
1050         /* set tx mtu */
1051         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1052         wb_data[1] = 0;
1053         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
1054
1055         /* set cnt max size */
1056         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1057         wb_data[1] = 0;
1058         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1059
1060         /* configure safc */
1061         wb_data[0] = 0x1000200;
1062         wb_data[1] = 0;
1063         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1064                     wb_data, 2);
1065
1066         return 0;
1067 }
1068
1069 static u8 bnx2x_bmac2_enable(struct link_params *params,
1070                              struct link_vars *vars,
1071                              u8 is_lb)
1072 {
1073         struct bnx2x *bp = params->bp;
1074         u8 port = params->port;
1075         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1076                                NIG_REG_INGRESS_BMAC0_MEM;
1077         u32 wb_data[2];
1078
1079         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1080
1081         wb_data[0] = 0;
1082         wb_data[1] = 0;
1083         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1084         udelay(30);
1085
1086         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1087         wb_data[0] = 0x3c;
1088         wb_data[1] = 0;
1089         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1090                     wb_data, 2);
1091
1092         udelay(30);
1093
1094         /* tx MAC SA */
1095         wb_data[0] = ((params->mac_addr[2] << 24) |
1096                        (params->mac_addr[3] << 16) |
1097                        (params->mac_addr[4] << 8) |
1098                         params->mac_addr[5]);
1099         wb_data[1] = ((params->mac_addr[0] << 8) |
1100                         params->mac_addr[1]);
1101         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1102                     wb_data, 2);
1103
1104         udelay(30);
1105
1106         /* Configure SAFC */
1107         wb_data[0] = 0x1000200;
1108         wb_data[1] = 0;
1109         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1110                     wb_data, 2);
1111         udelay(30);
1112
1113         /* set rx mtu */
1114         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1115         wb_data[1] = 0;
1116         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
1117         udelay(30);
1118
1119         /* set tx mtu */
1120         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1121         wb_data[1] = 0;
1122         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
1123         udelay(30);
1124         /* set cnt max size */
1125         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1126         wb_data[1] = 0;
1127         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1128         udelay(30);
1129         bnx2x_update_pfc_bmac2(params, vars, is_lb);
1130
1131         return 0;
1132 }
1133
1134 static u8 bnx2x_bmac_enable(struct link_params *params,
1135                             struct link_vars *vars,
1136                             u8 is_lb)
1137 {
1138         u8 rc, port = params->port;
1139         struct bnx2x *bp = params->bp;
1140         u32 val;
1141         /* reset and unreset the BigMac */
1142         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1143                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1144         msleep(1);
1145
1146         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1147                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1148
1149         /* enable access for bmac registers */
1150         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1151
1152         /* Enable BMAC according to BMAC type*/
1153         if (CHIP_IS_E2(bp))
1154                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1155         else
1156                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
1157         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1158         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1159         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1160         val = 0;
1161         if ((params->feature_config_flags &
1162               FEATURE_CONFIG_PFC_ENABLED) ||
1163             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1164                 val = 1;
1165         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1166         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1167         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1168         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1169         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1170         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1171
1172         vars->mac_type = MAC_TYPE_BMAC;
1173         return rc;
1174 }
1175
1176
1177 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1178 {
1179         struct bnx2x *bp = params->bp;
1180
1181         REG_WR(bp, params->shmem_base +
1182                offsetof(struct shmem_region,
1183                         port_mb[params->port].link_status), link_status);
1184 }
1185
1186 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1187 {
1188         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1189                         NIG_REG_INGRESS_BMAC0_MEM;
1190         u32 wb_data[2];
1191         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
1192
1193         /* Only if the bmac is out of reset */
1194         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1195                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1196             nig_bmac_enable) {
1197
1198                 if (CHIP_IS_E2(bp)) {
1199                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1200                         REG_RD_DMAE(bp, bmac_addr +
1201                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1202                                     wb_data, 2);
1203                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1204                         REG_WR_DMAE(bp, bmac_addr +
1205                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1206                                     wb_data, 2);
1207                 } else {
1208                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1209                         REG_RD_DMAE(bp, bmac_addr +
1210                                         BIGMAC_REGISTER_BMAC_CONTROL,
1211                                         wb_data, 2);
1212                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1213                         REG_WR_DMAE(bp, bmac_addr +
1214                                         BIGMAC_REGISTER_BMAC_CONTROL,
1215                                         wb_data, 2);
1216                 }
1217                 msleep(1);
1218         }
1219 }
1220
1221 static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1222                            u32 line_speed)
1223 {
1224         struct bnx2x *bp = params->bp;
1225         u8 port = params->port;
1226         u32 init_crd, crd;
1227         u32 count = 1000;
1228
1229         /* disable port */
1230         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1231
1232         /* wait for init credit */
1233         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1234         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1235         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
1236
1237         while ((init_crd != crd) && count) {
1238                 msleep(5);
1239
1240                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1241                 count--;
1242         }
1243         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1244         if (init_crd != crd) {
1245                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1246                           init_crd, crd);
1247                 return -EINVAL;
1248         }
1249
1250         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
1251             line_speed == SPEED_10 ||
1252             line_speed == SPEED_100 ||
1253             line_speed == SPEED_1000 ||
1254             line_speed == SPEED_2500) {
1255                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
1256                 /* update threshold */
1257                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1258                 /* update init credit */
1259                 init_crd = 778;         /* (800-18-4) */
1260
1261         } else {
1262                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1263                               ETH_OVREHEAD)/16;
1264                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
1265                 /* update threshold */
1266                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1267                 /* update init credit */
1268                 switch (line_speed) {
1269                 case SPEED_10000:
1270                         init_crd = thresh + 553 - 22;
1271                         break;
1272
1273                 case SPEED_12000:
1274                         init_crd = thresh + 664 - 22;
1275                         break;
1276
1277                 case SPEED_13000:
1278                         init_crd = thresh + 742 - 22;
1279                         break;
1280
1281                 case SPEED_16000:
1282                         init_crd = thresh + 778 - 22;
1283                         break;
1284                 default:
1285                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1286                                   line_speed);
1287                         return -EINVAL;
1288                 }
1289         }
1290         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1291         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1292                  line_speed, init_crd);
1293
1294         /* probe the credit changes */
1295         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1296         msleep(5);
1297         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1298
1299         /* enable port */
1300         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1301         return 0;
1302 }
1303
1304 /*
1305  * get_emac_base
1306  *
1307  * @param cb
1308  * @param mdc_mdio_access
1309  * @param port
1310  *
1311  * @return u32
1312  *
1313  * This function selects the MDC/MDIO access (through emac0 or
1314  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
1315  * phy has a default access mode, which could also be overridden
1316  * by nvram configuration. This parameter, whether this is the
1317  * default phy configuration, or the nvram overrun
1318  * configuration, is passed here as mdc_mdio_access and selects
1319  * the emac_base for the CL45 read/writes operations
1320  */
1321 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1322                                u32 mdc_mdio_access, u8 port)
1323 {
1324         u32 emac_base = 0;
1325         switch (mdc_mdio_access) {
1326         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1327                 break;
1328         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1329                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1330                         emac_base = GRCBASE_EMAC1;
1331                 else
1332                         emac_base = GRCBASE_EMAC0;
1333                 break;
1334         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
1335                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1336                         emac_base = GRCBASE_EMAC0;
1337                 else
1338                         emac_base = GRCBASE_EMAC1;
1339                 break;
1340         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1341                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1342                 break;
1343         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
1344                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
1345                 break;
1346         default:
1347                 break;
1348         }
1349         return emac_base;
1350
1351 }
1352
1353 /******************************************************************/
1354 /*                      CL45 access functions                     */
1355 /******************************************************************/
1356 static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1357                            u8 devad, u16 reg, u16 val)
1358 {
1359         u32 tmp, saved_mode;
1360         u8 i, rc = 0;
1361         /*
1362          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1363          * (a value of 49==0x31) and make sure that the AUTO poll is off
1364          */
1365
1366         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1367         tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1368                              EMAC_MDIO_MODE_CLOCK_CNT);
1369         tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1370                 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1371         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1372         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1373         udelay(40);
1374
1375         /* address */
1376
1377         tmp = ((phy->addr << 21) | (devad << 16) | reg |
1378                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1379                EMAC_MDIO_COMM_START_BUSY);
1380         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1381
1382         for (i = 0; i < 50; i++) {
1383                 udelay(10);
1384
1385                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1386                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1387                         udelay(5);
1388                         break;
1389                 }
1390         }
1391         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1392                 DP(NETIF_MSG_LINK, "write phy register failed\n");
1393                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1394                 rc = -EFAULT;
1395         } else {
1396                 /* data */
1397                 tmp = ((phy->addr << 21) | (devad << 16) | val |
1398                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1399                        EMAC_MDIO_COMM_START_BUSY);
1400                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1401
1402                 for (i = 0; i < 50; i++) {
1403                         udelay(10);
1404
1405                         tmp = REG_RD(bp, phy->mdio_ctrl +
1406                                      EMAC_REG_EMAC_MDIO_COMM);
1407                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1408                                 udelay(5);
1409                                 break;
1410                         }
1411                 }
1412                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1413                         DP(NETIF_MSG_LINK, "write phy register failed\n");
1414                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1415                         rc = -EFAULT;
1416                 }
1417         }
1418
1419         /* Restore the saved mode */
1420         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1421
1422         return rc;
1423 }
1424
1425 static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1426                           u8 devad, u16 reg, u16 *ret_val)
1427 {
1428         u32 val, saved_mode;
1429         u16 i;
1430         u8 rc = 0;
1431         /*
1432          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1433          * (a value of 49==0x31) and make sure that the AUTO poll is off
1434          */
1435
1436         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1437         val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
1438                               EMAC_MDIO_MODE_CLOCK_CNT));
1439         val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1440                 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1441         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1442         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1443         udelay(40);
1444
1445         /* address */
1446         val = ((phy->addr << 21) | (devad << 16) | reg |
1447                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1448                EMAC_MDIO_COMM_START_BUSY);
1449         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1450
1451         for (i = 0; i < 50; i++) {
1452                 udelay(10);
1453
1454                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1455                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1456                         udelay(5);
1457                         break;
1458                 }
1459         }
1460         if (val & EMAC_MDIO_COMM_START_BUSY) {
1461                 DP(NETIF_MSG_LINK, "read phy register failed\n");
1462                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1463                 *ret_val = 0;
1464                 rc = -EFAULT;
1465
1466         } else {
1467                 /* data */
1468                 val = ((phy->addr << 21) | (devad << 16) |
1469                        EMAC_MDIO_COMM_COMMAND_READ_45 |
1470                        EMAC_MDIO_COMM_START_BUSY);
1471                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1472
1473                 for (i = 0; i < 50; i++) {
1474                         udelay(10);
1475
1476                         val = REG_RD(bp, phy->mdio_ctrl +
1477                                      EMAC_REG_EMAC_MDIO_COMM);
1478                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1479                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1480                                 break;
1481                         }
1482                 }
1483                 if (val & EMAC_MDIO_COMM_START_BUSY) {
1484                         DP(NETIF_MSG_LINK, "read phy register failed\n");
1485                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1486                         *ret_val = 0;
1487                         rc = -EFAULT;
1488                 }
1489         }
1490
1491         /* Restore the saved mode */
1492         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1493
1494         return rc;
1495 }
1496
1497 u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1498                   u8 devad, u16 reg, u16 *ret_val)
1499 {
1500         u8 phy_index;
1501         /*
1502          * Probe for the phy according to the given phy_addr, and execute
1503          * the read request on it
1504          */
1505         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1506                 if (params->phy[phy_index].addr == phy_addr) {
1507                         return bnx2x_cl45_read(params->bp,
1508                                                &params->phy[phy_index], devad,
1509                                                reg, ret_val);
1510                 }
1511         }
1512         return -EINVAL;
1513 }
1514
1515 u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1516                    u8 devad, u16 reg, u16 val)
1517 {
1518         u8 phy_index;
1519         /*
1520          * Probe for the phy according to the given phy_addr, and execute
1521          * the write request on it
1522          */
1523         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1524                 if (params->phy[phy_index].addr == phy_addr) {
1525                         return bnx2x_cl45_write(params->bp,
1526                                                 &params->phy[phy_index], devad,
1527                                                 reg, val);
1528                 }
1529         }
1530         return -EINVAL;
1531 }
1532
1533 static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1534                                    struct bnx2x_phy *phy)
1535 {
1536         u32 ser_lane;
1537         u16 offset, aer_val;
1538         struct bnx2x *bp = params->bp;
1539         ser_lane = ((params->lane_config &
1540                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1541                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1542
1543         offset = phy->addr + ser_lane;
1544         if (CHIP_IS_E2(bp))
1545                 aer_val = 0x3800 + offset - 1;
1546         else
1547                 aer_val = 0x3800 + offset;
1548         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
1549                           MDIO_AER_BLOCK_AER_REG, aer_val);
1550 }
1551 static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1552                                      struct bnx2x_phy *phy)
1553 {
1554         CL22_WR_OVER_CL45(bp, phy,
1555                           MDIO_REG_BANK_AER_BLOCK,
1556                           MDIO_AER_BLOCK_AER_REG, 0x3800);
1557 }
1558
1559 /******************************************************************/
1560 /*                      Internal phy section                      */
1561 /******************************************************************/
1562
1563 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1564 {
1565         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1566
1567         /* Set Clause 22 */
1568         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1569         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1570         udelay(500);
1571         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1572         udelay(500);
1573          /* Set Clause 45 */
1574         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
1575 }
1576
1577 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1578 {
1579         u32 val;
1580
1581         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
1582
1583         val = SERDES_RESET_BITS << (port*16);
1584
1585         /* reset and unreset the SerDes/XGXS */
1586         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1587         udelay(500);
1588         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1589
1590         bnx2x_set_serdes_access(bp, port);
1591
1592         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
1593                DEFAULT_PHY_DEV_ADDR);
1594 }
1595
1596 static void bnx2x_xgxs_deassert(struct link_params *params)
1597 {
1598         struct bnx2x *bp = params->bp;
1599         u8 port;
1600         u32 val;
1601         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1602         port = params->port;
1603
1604         val = XGXS_RESET_BITS << (port*16);
1605
1606         /* reset and unreset the SerDes/XGXS */
1607         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1608         udelay(500);
1609         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1610
1611         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
1612         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1613                params->phy[INT_PHY].def_md_devad);
1614 }
1615
1616
1617 void bnx2x_link_status_update(struct link_params *params,
1618                               struct link_vars *vars)
1619 {
1620         struct bnx2x *bp = params->bp;
1621         u8 link_10g;
1622         u8 port = params->port;
1623
1624         vars->link_status = REG_RD(bp, params->shmem_base +
1625                                    offsetof(struct shmem_region,
1626                                             port_mb[port].link_status));
1627
1628         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1629
1630         if (vars->link_up) {
1631                 DP(NETIF_MSG_LINK, "phy link up\n");
1632
1633                 vars->phy_link_up = 1;
1634                 vars->duplex = DUPLEX_FULL;
1635                 switch (vars->link_status &
1636                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1637                         case LINK_10THD:
1638                                 vars->duplex = DUPLEX_HALF;
1639                                 /* fall thru */
1640                         case LINK_10TFD:
1641                                 vars->line_speed = SPEED_10;
1642                                 break;
1643
1644                         case LINK_100TXHD:
1645                                 vars->duplex = DUPLEX_HALF;
1646                                 /* fall thru */
1647                         case LINK_100T4:
1648                         case LINK_100TXFD:
1649                                 vars->line_speed = SPEED_100;
1650                                 break;
1651
1652                         case LINK_1000THD:
1653                                 vars->duplex = DUPLEX_HALF;
1654                                 /* fall thru */
1655                         case LINK_1000TFD:
1656                                 vars->line_speed = SPEED_1000;
1657                                 break;
1658
1659                         case LINK_2500THD:
1660                                 vars->duplex = DUPLEX_HALF;
1661                                 /* fall thru */
1662                         case LINK_2500TFD:
1663                                 vars->line_speed = SPEED_2500;
1664                                 break;
1665
1666                         case LINK_10GTFD:
1667                                 vars->line_speed = SPEED_10000;
1668                                 break;
1669
1670                         case LINK_12GTFD:
1671                                 vars->line_speed = SPEED_12000;
1672                                 break;
1673
1674                         case LINK_12_5GTFD:
1675                                 vars->line_speed = SPEED_12500;
1676                                 break;
1677
1678                         case LINK_13GTFD:
1679                                 vars->line_speed = SPEED_13000;
1680                                 break;
1681
1682                         case LINK_15GTFD:
1683                                 vars->line_speed = SPEED_15000;
1684                                 break;
1685
1686                         case LINK_16GTFD:
1687                                 vars->line_speed = SPEED_16000;
1688                                 break;
1689
1690                         default:
1691                                 break;
1692                 }
1693                 vars->flow_ctrl = 0;
1694                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1695                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1696
1697                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1698                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1699
1700                 if (!vars->flow_ctrl)
1701                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1702
1703                 if (vars->line_speed &&
1704                     ((vars->line_speed == SPEED_10) ||
1705                      (vars->line_speed == SPEED_100))) {
1706                         vars->phy_flags |= PHY_SGMII_FLAG;
1707                 } else {
1708                         vars->phy_flags &= ~PHY_SGMII_FLAG;
1709                 }
1710
1711                 /* anything 10 and over uses the bmac */
1712                 link_10g = ((vars->line_speed == SPEED_10000) ||
1713                             (vars->line_speed == SPEED_12000) ||
1714                             (vars->line_speed == SPEED_12500) ||
1715                             (vars->line_speed == SPEED_13000) ||
1716                             (vars->line_speed == SPEED_15000) ||
1717                             (vars->line_speed == SPEED_16000));
1718                 if (link_10g)
1719                         vars->mac_type = MAC_TYPE_BMAC;
1720                 else
1721                         vars->mac_type = MAC_TYPE_EMAC;
1722
1723         } else { /* link down */
1724                 DP(NETIF_MSG_LINK, "phy link down\n");
1725
1726                 vars->phy_link_up = 0;
1727
1728                 vars->line_speed = 0;
1729                 vars->duplex = DUPLEX_FULL;
1730                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1731
1732                 /* indicate no mac active */
1733                 vars->mac_type = MAC_TYPE_NONE;
1734         }
1735
1736         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x\n",
1737                  vars->link_status, vars->phy_link_up);
1738         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
1739                  vars->line_speed, vars->duplex, vars->flow_ctrl);
1740 }
1741
1742
1743 static void bnx2x_set_master_ln(struct link_params *params,
1744                                 struct bnx2x_phy *phy)
1745 {
1746         struct bnx2x *bp = params->bp;
1747         u16 new_master_ln, ser_lane;
1748         ser_lane = ((params->lane_config &
1749                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1750                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1751
1752         /* set the master_ln for AN */
1753         CL22_RD_OVER_CL45(bp, phy,
1754                           MDIO_REG_BANK_XGXS_BLOCK2,
1755                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1756                           &new_master_ln);
1757
1758         CL22_WR_OVER_CL45(bp, phy,
1759                           MDIO_REG_BANK_XGXS_BLOCK2 ,
1760                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1761                           (new_master_ln | ser_lane));
1762 }
1763
1764 static u8 bnx2x_reset_unicore(struct link_params *params,
1765                               struct bnx2x_phy *phy,
1766                               u8 set_serdes)
1767 {
1768         struct bnx2x *bp = params->bp;
1769         u16 mii_control;
1770         u16 i;
1771         CL22_RD_OVER_CL45(bp, phy,
1772                           MDIO_REG_BANK_COMBO_IEEE0,
1773                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1774
1775         /* reset the unicore */
1776         CL22_WR_OVER_CL45(bp, phy,
1777                           MDIO_REG_BANK_COMBO_IEEE0,
1778                           MDIO_COMBO_IEEE0_MII_CONTROL,
1779                           (mii_control |
1780                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1781         if (set_serdes)
1782                 bnx2x_set_serdes_access(bp, params->port);
1783
1784         /* wait for the reset to self clear */
1785         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1786                 udelay(5);
1787
1788                 /* the reset erased the previous bank value */
1789                 CL22_RD_OVER_CL45(bp, phy,
1790                                   MDIO_REG_BANK_COMBO_IEEE0,
1791                                   MDIO_COMBO_IEEE0_MII_CONTROL,
1792                                   &mii_control);
1793
1794                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1795                         udelay(5);
1796                         return 0;
1797                 }
1798         }
1799
1800         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
1801                               " Port %d\n",
1802                          params->port);
1803         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1804         return -EINVAL;
1805
1806 }
1807
1808 static void bnx2x_set_swap_lanes(struct link_params *params,
1809                                  struct bnx2x_phy *phy)
1810 {
1811         struct bnx2x *bp = params->bp;
1812         /*
1813          *  Each two bits represents a lane number:
1814          *  No swap is 0123 => 0x1b no need to enable the swap
1815          */
1816         u16 ser_lane, rx_lane_swap, tx_lane_swap;
1817
1818         ser_lane = ((params->lane_config &
1819                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1820                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1821         rx_lane_swap = ((params->lane_config &
1822                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1823                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1824         tx_lane_swap = ((params->lane_config &
1825                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1826                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1827
1828         if (rx_lane_swap != 0x1b) {
1829                 CL22_WR_OVER_CL45(bp, phy,
1830                                   MDIO_REG_BANK_XGXS_BLOCK2,
1831                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1832                                   (rx_lane_swap |
1833                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1834                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1835         } else {
1836                 CL22_WR_OVER_CL45(bp, phy,
1837                                   MDIO_REG_BANK_XGXS_BLOCK2,
1838                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1839         }
1840
1841         if (tx_lane_swap != 0x1b) {
1842                 CL22_WR_OVER_CL45(bp, phy,
1843                                   MDIO_REG_BANK_XGXS_BLOCK2,
1844                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1845                                   (tx_lane_swap |
1846                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1847         } else {
1848                 CL22_WR_OVER_CL45(bp, phy,
1849                                   MDIO_REG_BANK_XGXS_BLOCK2,
1850                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1851         }
1852 }
1853
1854 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1855                                          struct link_params *params)
1856 {
1857         struct bnx2x *bp = params->bp;
1858         u16 control2;
1859         CL22_RD_OVER_CL45(bp, phy,
1860                           MDIO_REG_BANK_SERDES_DIGITAL,
1861                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1862                           &control2);
1863         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1864                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1865         else
1866                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1867         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1868                 phy->speed_cap_mask, control2);
1869         CL22_WR_OVER_CL45(bp, phy,
1870                           MDIO_REG_BANK_SERDES_DIGITAL,
1871                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1872                           control2);
1873
1874         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
1875              (phy->speed_cap_mask &
1876                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1877                 DP(NETIF_MSG_LINK, "XGXS\n");
1878
1879                 CL22_WR_OVER_CL45(bp, phy,
1880                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
1881                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1882                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1883
1884                 CL22_RD_OVER_CL45(bp, phy,
1885                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
1886                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1887                                   &control2);
1888
1889
1890                 control2 |=
1891                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1892
1893                 CL22_WR_OVER_CL45(bp, phy,
1894                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
1895                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1896                                   control2);
1897
1898                 /* Disable parallel detection of HiG */
1899                 CL22_WR_OVER_CL45(bp, phy,
1900                                   MDIO_REG_BANK_XGXS_BLOCK2,
1901                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1902                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1903                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1904         }
1905 }
1906
1907 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1908                               struct link_params *params,
1909                               struct link_vars *vars,
1910                               u8 enable_cl73)
1911 {
1912         struct bnx2x *bp = params->bp;
1913         u16 reg_val;
1914
1915         /* CL37 Autoneg */
1916         CL22_RD_OVER_CL45(bp, phy,
1917                           MDIO_REG_BANK_COMBO_IEEE0,
1918                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1919
1920         /* CL37 Autoneg Enabled */
1921         if (vars->line_speed == SPEED_AUTO_NEG)
1922                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1923         else /* CL37 Autoneg Disabled */
1924                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1925                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1926
1927         CL22_WR_OVER_CL45(bp, phy,
1928                           MDIO_REG_BANK_COMBO_IEEE0,
1929                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1930
1931         /* Enable/Disable Autodetection */
1932
1933         CL22_RD_OVER_CL45(bp, phy,
1934                           MDIO_REG_BANK_SERDES_DIGITAL,
1935                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1936         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1937                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1938         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
1939         if (vars->line_speed == SPEED_AUTO_NEG)
1940                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1941         else
1942                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1943
1944         CL22_WR_OVER_CL45(bp, phy,
1945                           MDIO_REG_BANK_SERDES_DIGITAL,
1946                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1947
1948         /* Enable TetonII and BAM autoneg */
1949         CL22_RD_OVER_CL45(bp, phy,
1950                           MDIO_REG_BANK_BAM_NEXT_PAGE,
1951                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1952                           &reg_val);
1953         if (vars->line_speed == SPEED_AUTO_NEG) {
1954                 /* Enable BAM aneg Mode and TetonII aneg Mode */
1955                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1956                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1957         } else {
1958                 /* TetonII and BAM Autoneg Disabled */
1959                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1960                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1961         }
1962         CL22_WR_OVER_CL45(bp, phy,
1963                           MDIO_REG_BANK_BAM_NEXT_PAGE,
1964                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1965                           reg_val);
1966
1967         if (enable_cl73) {
1968                 /* Enable Cl73 FSM status bits */
1969                 CL22_WR_OVER_CL45(bp, phy,
1970                                   MDIO_REG_BANK_CL73_USERB0,
1971                                   MDIO_CL73_USERB0_CL73_UCTRL,
1972                                   0xe);
1973
1974                 /* Enable BAM Station Manager*/
1975                 CL22_WR_OVER_CL45(bp, phy,
1976                         MDIO_REG_BANK_CL73_USERB0,
1977                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1978                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1979                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1980                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1981
1982                 /* Advertise CL73 link speeds */
1983                 CL22_RD_OVER_CL45(bp, phy,
1984                                   MDIO_REG_BANK_CL73_IEEEB1,
1985                                   MDIO_CL73_IEEEB1_AN_ADV2,
1986                                   &reg_val);
1987                 if (phy->speed_cap_mask &
1988                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1989                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
1990                 if (phy->speed_cap_mask &
1991                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1992                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
1993
1994                 CL22_WR_OVER_CL45(bp, phy,
1995                                   MDIO_REG_BANK_CL73_IEEEB1,
1996                                   MDIO_CL73_IEEEB1_AN_ADV2,
1997                                   reg_val);
1998
1999                 /* CL73 Autoneg Enabled */
2000                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2001
2002         } else /* CL73 Autoneg Disabled */
2003                 reg_val = 0;
2004
2005         CL22_WR_OVER_CL45(bp, phy,
2006                           MDIO_REG_BANK_CL73_IEEEB0,
2007                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2008 }
2009
2010 /* program SerDes, forced speed */
2011 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2012                                  struct link_params *params,
2013                                  struct link_vars *vars)
2014 {
2015         struct bnx2x *bp = params->bp;
2016         u16 reg_val;
2017
2018         /* program duplex, disable autoneg and sgmii*/
2019         CL22_RD_OVER_CL45(bp, phy,
2020                           MDIO_REG_BANK_COMBO_IEEE0,
2021                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2022         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2023                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2024                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
2025         if (phy->req_duplex == DUPLEX_FULL)
2026                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2027         CL22_WR_OVER_CL45(bp, phy,
2028                           MDIO_REG_BANK_COMBO_IEEE0,
2029                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2030
2031         /*
2032          * program speed
2033          *  - needed only if the speed is greater than 1G (2.5G or 10G)
2034          */
2035         CL22_RD_OVER_CL45(bp, phy,
2036                           MDIO_REG_BANK_SERDES_DIGITAL,
2037                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2038         /* clearing the speed value before setting the right speed */
2039         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2040
2041         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2042                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2043
2044         if (!((vars->line_speed == SPEED_1000) ||
2045               (vars->line_speed == SPEED_100) ||
2046               (vars->line_speed == SPEED_10))) {
2047
2048                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2049                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2050                 if (vars->line_speed == SPEED_10000)
2051                         reg_val |=
2052                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
2053                 if (vars->line_speed == SPEED_13000)
2054                         reg_val |=
2055                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
2056         }
2057
2058         CL22_WR_OVER_CL45(bp, phy,
2059                           MDIO_REG_BANK_SERDES_DIGITAL,
2060                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
2061
2062 }
2063
2064 static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2065                                              struct link_params *params)
2066 {
2067         struct bnx2x *bp = params->bp;
2068         u16 val = 0;
2069
2070         /* configure the 48 bits for BAM AN */
2071
2072         /* set extended capabilities */
2073         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2074                 val |= MDIO_OVER_1G_UP1_2_5G;
2075         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2076                 val |= MDIO_OVER_1G_UP1_10G;
2077         CL22_WR_OVER_CL45(bp, phy,
2078                           MDIO_REG_BANK_OVER_1G,
2079                           MDIO_OVER_1G_UP1, val);
2080
2081         CL22_WR_OVER_CL45(bp, phy,
2082                           MDIO_REG_BANK_OVER_1G,
2083                           MDIO_OVER_1G_UP3, 0x400);
2084 }
2085
2086 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2087                                      struct link_params *params, u16 *ieee_fc)
2088 {
2089         struct bnx2x *bp = params->bp;
2090         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
2091         /*
2092          * Resolve pause mode and advertisement.
2093          * Please refer to Table 28B-3 of the 802.3ab-1999 spec
2094          */
2095
2096         switch (phy->req_flow_ctrl) {
2097         case BNX2X_FLOW_CTRL_AUTO:
2098                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
2099                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2100                 else
2101                         *ieee_fc |=
2102                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2103                 break;
2104         case BNX2X_FLOW_CTRL_TX:
2105                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2106                 break;
2107
2108         case BNX2X_FLOW_CTRL_RX:
2109         case BNX2X_FLOW_CTRL_BOTH:
2110                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2111                 break;
2112
2113         case BNX2X_FLOW_CTRL_NONE:
2114         default:
2115                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
2116                 break;
2117         }
2118         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
2119 }
2120
2121 static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2122                                              struct link_params *params,
2123                                              u16 ieee_fc)
2124 {
2125         struct bnx2x *bp = params->bp;
2126         u16 val;
2127         /* for AN, we are always publishing full duplex */
2128
2129         CL22_WR_OVER_CL45(bp, phy,
2130                           MDIO_REG_BANK_COMBO_IEEE0,
2131                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
2132         CL22_RD_OVER_CL45(bp, phy,
2133                           MDIO_REG_BANK_CL73_IEEEB1,
2134                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
2135         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2136         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
2137         CL22_WR_OVER_CL45(bp, phy,
2138                           MDIO_REG_BANK_CL73_IEEEB1,
2139                           MDIO_CL73_IEEEB1_AN_ADV1, val);
2140 }
2141
2142 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2143                                   struct link_params *params,
2144                                   u8 enable_cl73)
2145 {
2146         struct bnx2x *bp = params->bp;
2147         u16 mii_control;
2148
2149         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
2150         /* Enable and restart BAM/CL37 aneg */
2151
2152         if (enable_cl73) {
2153                 CL22_RD_OVER_CL45(bp, phy,
2154                                   MDIO_REG_BANK_CL73_IEEEB0,
2155                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2156                                   &mii_control);
2157
2158                 CL22_WR_OVER_CL45(bp, phy,
2159                                   MDIO_REG_BANK_CL73_IEEEB0,
2160                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2161                                   (mii_control |
2162                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2163                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2164         } else {
2165
2166                 CL22_RD_OVER_CL45(bp, phy,
2167                                   MDIO_REG_BANK_COMBO_IEEE0,
2168                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2169                                   &mii_control);
2170                 DP(NETIF_MSG_LINK,
2171                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2172                          mii_control);
2173                 CL22_WR_OVER_CL45(bp, phy,
2174                                   MDIO_REG_BANK_COMBO_IEEE0,
2175                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2176                                   (mii_control |
2177                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2178                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2179         }
2180 }
2181
2182 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2183                                            struct link_params *params,
2184                                            struct link_vars *vars)
2185 {
2186         struct bnx2x *bp = params->bp;
2187         u16 control1;
2188
2189         /* in SGMII mode, the unicore is always slave */
2190
2191         CL22_RD_OVER_CL45(bp, phy,
2192                           MDIO_REG_BANK_SERDES_DIGITAL,
2193                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2194                           &control1);
2195         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2196         /* set sgmii mode (and not fiber) */
2197         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2198                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2199                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2200         CL22_WR_OVER_CL45(bp, phy,
2201                           MDIO_REG_BANK_SERDES_DIGITAL,
2202                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2203                           control1);
2204
2205         /* if forced speed */
2206         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
2207                 /* set speed, disable autoneg */
2208                 u16 mii_control;
2209
2210                 CL22_RD_OVER_CL45(bp, phy,
2211                                   MDIO_REG_BANK_COMBO_IEEE0,
2212                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2213                                   &mii_control);
2214                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2215                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2216                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2217
2218                 switch (vars->line_speed) {
2219                 case SPEED_100:
2220                         mii_control |=
2221                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2222                         break;
2223                 case SPEED_1000:
2224                         mii_control |=
2225                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2226                         break;
2227                 case SPEED_10:
2228                         /* there is nothing to set for 10M */
2229                         break;
2230                 default:
2231                         /* invalid speed for SGMII */
2232                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2233                                   vars->line_speed);
2234                         break;
2235                 }
2236
2237                 /* setting the full duplex */
2238                 if (phy->req_duplex == DUPLEX_FULL)
2239                         mii_control |=
2240                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2241                 CL22_WR_OVER_CL45(bp, phy,
2242                                   MDIO_REG_BANK_COMBO_IEEE0,
2243                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2244                                   mii_control);
2245
2246         } else { /* AN mode */
2247                 /* enable and restart AN */
2248                 bnx2x_restart_autoneg(phy, params, 0);
2249         }
2250 }
2251
2252
2253 /*
2254  * link management
2255  */
2256
2257 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
2258 {                                               /*  LD      LP   */
2259         switch (pause_result) {                 /* ASYM P ASYM P */
2260         case 0xb:                               /*   1  0   1  1 */
2261                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
2262                 break;
2263
2264         case 0xe:                               /*   1  1   1  0 */
2265                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
2266                 break;
2267
2268         case 0x5:                               /*   0  1   0  1 */
2269         case 0x7:                               /*   0  1   1  1 */
2270         case 0xd:                               /*   1  1   0  1 */
2271         case 0xf:                               /*   1  1   1  1 */
2272                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
2273                 break;
2274
2275         default:
2276                 break;
2277         }
2278         if (pause_result & (1<<0))
2279                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2280         if (pause_result & (1<<1))
2281                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
2282 }
2283
2284 static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2285                                             struct link_params *params)
2286 {
2287         struct bnx2x *bp = params->bp;
2288         u16 pd_10g, status2_1000x;
2289         if (phy->req_line_speed != SPEED_AUTO_NEG)
2290                 return 0;
2291         CL22_RD_OVER_CL45(bp, phy,
2292                           MDIO_REG_BANK_SERDES_DIGITAL,
2293                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2294                           &status2_1000x);
2295         CL22_RD_OVER_CL45(bp, phy,
2296                           MDIO_REG_BANK_SERDES_DIGITAL,
2297                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2298                           &status2_1000x);
2299         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2300                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2301                          params->port);
2302                 return 1;
2303         }
2304
2305         CL22_RD_OVER_CL45(bp, phy,
2306                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
2307                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2308                           &pd_10g);
2309
2310         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2311                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2312                          params->port);
2313                 return 1;
2314         }
2315         return 0;
2316 }
2317
2318 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2319                                     struct link_params *params,
2320                                     struct link_vars *vars,
2321                                     u32 gp_status)
2322 {
2323         struct bnx2x *bp = params->bp;
2324         u16 ld_pause;   /* local driver */
2325         u16 lp_pause;   /* link partner */
2326         u16 pause_result;
2327
2328         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2329
2330         /* resolve from gp_status in case of AN complete and not sgmii */
2331         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2332                 vars->flow_ctrl = phy->req_flow_ctrl;
2333         else if (phy->req_line_speed != SPEED_AUTO_NEG)
2334                 vars->flow_ctrl = params->req_fc_auto_adv;
2335         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2336                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
2337                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
2338                         vars->flow_ctrl = params->req_fc_auto_adv;
2339                         return;
2340                 }
2341                 if ((gp_status &
2342                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2343                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2344                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2345                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2346
2347                         CL22_RD_OVER_CL45(bp, phy,
2348                                           MDIO_REG_BANK_CL73_IEEEB1,
2349                                           MDIO_CL73_IEEEB1_AN_ADV1,
2350                                           &ld_pause);
2351                         CL22_RD_OVER_CL45(bp, phy,
2352                                           MDIO_REG_BANK_CL73_IEEEB1,
2353                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
2354                                           &lp_pause);
2355                         pause_result = (ld_pause &
2356                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2357                                         >> 8;
2358                         pause_result |= (lp_pause &
2359                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2360                                         >> 10;
2361                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2362                                  pause_result);
2363                 } else {
2364                         CL22_RD_OVER_CL45(bp, phy,
2365                                           MDIO_REG_BANK_COMBO_IEEE0,
2366                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2367                                           &ld_pause);
2368                         CL22_RD_OVER_CL45(bp, phy,
2369                                 MDIO_REG_BANK_COMBO_IEEE0,
2370                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2371                                 &lp_pause);
2372                         pause_result = (ld_pause &
2373                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
2374                         pause_result |= (lp_pause &
2375                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
2376                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2377                                  pause_result);
2378                 }
2379                 bnx2x_pause_resolve(vars, pause_result);
2380         }
2381         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2382 }
2383
2384 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2385                                          struct link_params *params)
2386 {
2387         struct bnx2x *bp = params->bp;
2388         u16 rx_status, ustat_val, cl37_fsm_recieved;
2389         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2390         /* Step 1: Make sure signal is detected */
2391         CL22_RD_OVER_CL45(bp, phy,
2392                           MDIO_REG_BANK_RX0,
2393                           MDIO_RX0_RX_STATUS,
2394                           &rx_status);
2395         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2396             (MDIO_RX0_RX_STATUS_SIGDET)) {
2397                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2398                              "rx_status(0x80b0) = 0x%x\n", rx_status);
2399                 CL22_WR_OVER_CL45(bp, phy,
2400                                   MDIO_REG_BANK_CL73_IEEEB0,
2401                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2402                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2403                 return;
2404         }
2405         /* Step 2: Check CL73 state machine */
2406         CL22_RD_OVER_CL45(bp, phy,
2407                           MDIO_REG_BANK_CL73_USERB0,
2408                           MDIO_CL73_USERB0_CL73_USTAT1,
2409                           &ustat_val);
2410         if ((ustat_val &
2411              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2412               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2413             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2414               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2415                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2416                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
2417                 return;
2418         }
2419         /*
2420          * Step 3: Check CL37 Message Pages received to indicate LP
2421          * supports only CL37
2422          */
2423         CL22_RD_OVER_CL45(bp, phy,
2424                           MDIO_REG_BANK_REMOTE_PHY,
2425                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
2426                           &cl37_fsm_recieved);
2427         if ((cl37_fsm_recieved &
2428              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2429              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2430             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2431               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2432                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2433                              "misc_rx_status(0x8330) = 0x%x\n",
2434                          cl37_fsm_recieved);
2435                 return;
2436         }
2437         /*
2438          * The combined cl37/cl73 fsm state information indicating that
2439          * we are connected to a device which does not support cl73, but
2440          * does support cl37 BAM. In this case we disable cl73 and
2441          * restart cl37 auto-neg
2442          */
2443
2444         /* Disable CL73 */
2445         CL22_WR_OVER_CL45(bp, phy,
2446                           MDIO_REG_BANK_CL73_IEEEB0,
2447                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2448                           0);
2449         /* Restart CL37 autoneg */
2450         bnx2x_restart_autoneg(phy, params, 0);
2451         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2452 }
2453
2454 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2455                                   struct link_params *params,
2456                                   struct link_vars *vars,
2457                                   u32 gp_status)
2458 {
2459         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2460                 vars->link_status |=
2461                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2462
2463         if (bnx2x_direct_parallel_detect_used(phy, params))
2464                 vars->link_status |=
2465                         LINK_STATUS_PARALLEL_DETECTION_USED;
2466 }
2467
2468 static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
2469                                      struct link_params *params,
2470                                      struct link_vars *vars)
2471 {
2472         struct bnx2x *bp = params->bp;
2473         u16 new_line_speed, gp_status;
2474         u8 rc = 0;
2475
2476         /* Read gp_status */
2477         CL22_RD_OVER_CL45(bp, phy,
2478                           MDIO_REG_BANK_GP_STATUS,
2479                           MDIO_GP_STATUS_TOP_AN_STATUS1,
2480                           &gp_status);
2481
2482         if (phy->req_line_speed == SPEED_AUTO_NEG)
2483                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
2484         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2485                 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2486                          gp_status);
2487
2488                 vars->phy_link_up = 1;
2489                 vars->link_status |= LINK_STATUS_LINK_UP;
2490
2491                 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2492                         vars->duplex = DUPLEX_FULL;
2493                 else
2494                         vars->duplex = DUPLEX_HALF;
2495
2496                 if (SINGLE_MEDIA_DIRECT(params)) {
2497                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2498                         if (phy->req_line_speed == SPEED_AUTO_NEG)
2499                                 bnx2x_xgxs_an_resolve(phy, params, vars,
2500                                                       gp_status);
2501                 }
2502
2503                 switch (gp_status & GP_STATUS_SPEED_MASK) {
2504                 case GP_STATUS_10M:
2505                         new_line_speed = SPEED_10;
2506                         if (vars->duplex == DUPLEX_FULL)
2507                                 vars->link_status |= LINK_10TFD;
2508                         else
2509                                 vars->link_status |= LINK_10THD;
2510                         break;
2511
2512                 case GP_STATUS_100M:
2513                         new_line_speed = SPEED_100;
2514                         if (vars->duplex == DUPLEX_FULL)
2515                                 vars->link_status |= LINK_100TXFD;
2516                         else
2517                                 vars->link_status |= LINK_100TXHD;
2518                         break;
2519
2520                 case GP_STATUS_1G:
2521                 case GP_STATUS_1G_KX:
2522                         new_line_speed = SPEED_1000;
2523                         if (vars->duplex == DUPLEX_FULL)
2524                                 vars->link_status |= LINK_1000TFD;
2525                         else
2526                                 vars->link_status |= LINK_1000THD;
2527                         break;
2528
2529                 case GP_STATUS_2_5G:
2530                         new_line_speed = SPEED_2500;
2531                         if (vars->duplex == DUPLEX_FULL)
2532                                 vars->link_status |= LINK_2500TFD;
2533                         else
2534                                 vars->link_status |= LINK_2500THD;
2535                         break;
2536
2537                 case GP_STATUS_5G:
2538                 case GP_STATUS_6G:
2539                         DP(NETIF_MSG_LINK,
2540                                  "link speed unsupported  gp_status 0x%x\n",
2541                                   gp_status);
2542                         return -EINVAL;
2543
2544                 case GP_STATUS_10G_KX4:
2545                 case GP_STATUS_10G_HIG:
2546                 case GP_STATUS_10G_CX4:
2547                         new_line_speed = SPEED_10000;
2548                         vars->link_status |= LINK_10GTFD;
2549                         break;
2550
2551                 case GP_STATUS_12G_HIG:
2552                         new_line_speed = SPEED_12000;
2553                         vars->link_status |= LINK_12GTFD;
2554                         break;
2555
2556                 case GP_STATUS_12_5G:
2557                         new_line_speed = SPEED_12500;
2558                         vars->link_status |= LINK_12_5GTFD;
2559                         break;
2560
2561                 case GP_STATUS_13G:
2562                         new_line_speed = SPEED_13000;
2563                         vars->link_status |= LINK_13GTFD;
2564                         break;
2565
2566                 case GP_STATUS_15G:
2567                         new_line_speed = SPEED_15000;
2568                         vars->link_status |= LINK_15GTFD;
2569                         break;
2570
2571                 case GP_STATUS_16G:
2572                         new_line_speed = SPEED_16000;
2573                         vars->link_status |= LINK_16GTFD;
2574                         break;
2575
2576                 default:
2577                         DP(NETIF_MSG_LINK,
2578                                   "link speed unsupported gp_status 0x%x\n",
2579                                   gp_status);
2580                         return -EINVAL;
2581                 }
2582
2583                 vars->line_speed = new_line_speed;
2584
2585         } else { /* link_down */
2586                 DP(NETIF_MSG_LINK, "phy link down\n");
2587
2588                 vars->phy_link_up = 0;
2589
2590                 vars->duplex = DUPLEX_FULL;
2591                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2592                 vars->mac_type = MAC_TYPE_NONE;
2593
2594                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2595                     SINGLE_MEDIA_DIRECT(params)) {
2596                         /* Check signal is detected */
2597                         bnx2x_check_fallback_to_cl37(phy, params);
2598                 }
2599         }
2600
2601         DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %x line_speed %x\n",
2602                  gp_status, vars->phy_link_up, vars->line_speed);
2603         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
2604                    vars->duplex, vars->flow_ctrl, vars->link_status);
2605         return rc;
2606 }
2607
2608 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2609 {
2610         struct bnx2x *bp = params->bp;
2611         struct bnx2x_phy *phy = &params->phy[INT_PHY];
2612         u16 lp_up2;
2613         u16 tx_driver;
2614         u16 bank;
2615
2616         /* read precomp */
2617         CL22_RD_OVER_CL45(bp, phy,
2618                           MDIO_REG_BANK_OVER_1G,
2619                           MDIO_OVER_1G_LP_UP2, &lp_up2);
2620
2621         /* bits [10:7] at lp_up2, positioned at [15:12] */
2622         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2623                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2624                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2625
2626         if (lp_up2 == 0)
2627                 return;
2628
2629         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2630               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2631                 CL22_RD_OVER_CL45(bp, phy,
2632                                   bank,
2633                                   MDIO_TX0_TX_DRIVER, &tx_driver);
2634
2635                 /* replace tx_driver bits [15:12] */
2636                 if (lp_up2 !=
2637                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2638                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2639                         tx_driver |= lp_up2;
2640                         CL22_WR_OVER_CL45(bp, phy,
2641                                           bank,
2642                                           MDIO_TX0_TX_DRIVER, tx_driver);
2643                 }
2644         }
2645 }
2646
2647 static u8 bnx2x_emac_program(struct link_params *params,
2648                              struct link_vars *vars)
2649 {
2650         struct bnx2x *bp = params->bp;
2651         u8 port = params->port;
2652         u16 mode = 0;
2653
2654         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2655         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2656                        EMAC_REG_EMAC_MODE,
2657                        (EMAC_MODE_25G_MODE |
2658                         EMAC_MODE_PORT_MII_10M |
2659                         EMAC_MODE_HALF_DUPLEX));
2660         switch (vars->line_speed) {
2661         case SPEED_10:
2662                 mode |= EMAC_MODE_PORT_MII_10M;
2663                 break;
2664
2665         case SPEED_100:
2666                 mode |= EMAC_MODE_PORT_MII;
2667                 break;
2668
2669         case SPEED_1000:
2670                 mode |= EMAC_MODE_PORT_GMII;
2671                 break;
2672
2673         case SPEED_2500:
2674                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2675                 break;
2676
2677         default:
2678                 /* 10G not valid for EMAC */
2679                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2680                            vars->line_speed);
2681                 return -EINVAL;
2682         }
2683
2684         if (vars->duplex == DUPLEX_HALF)
2685                 mode |= EMAC_MODE_HALF_DUPLEX;
2686         bnx2x_bits_en(bp,
2687                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2688                       mode);
2689
2690         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
2691         return 0;
2692 }
2693
2694 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2695                                   struct link_params *params)
2696 {
2697
2698         u16 bank, i = 0;
2699         struct bnx2x *bp = params->bp;
2700
2701         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2702               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2703                         CL22_WR_OVER_CL45(bp, phy,
2704                                           bank,
2705                                           MDIO_RX0_RX_EQ_BOOST,
2706                                           phy->rx_preemphasis[i]);
2707         }
2708
2709         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2710                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2711                         CL22_WR_OVER_CL45(bp, phy,
2712                                           bank,
2713                                           MDIO_TX0_TX_DRIVER,
2714                                           phy->tx_preemphasis[i]);
2715         }
2716 }
2717
2718 static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2719                                     struct link_params *params,
2720                                     struct link_vars *vars)
2721 {
2722         struct bnx2x *bp = params->bp;
2723         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2724                           (params->loopback_mode == LOOPBACK_XGXS));
2725         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2726                 if (SINGLE_MEDIA_DIRECT(params) &&
2727                     (params->feature_config_flags &
2728                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2729                         bnx2x_set_preemphasis(phy, params);
2730
2731                 /* forced speed requested? */
2732                 if (vars->line_speed != SPEED_AUTO_NEG ||
2733                     (SINGLE_MEDIA_DIRECT(params) &&
2734                      params->loopback_mode == LOOPBACK_EXT)) {
2735                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2736
2737                         /* disable autoneg */
2738                         bnx2x_set_autoneg(phy, params, vars, 0);
2739
2740                         /* program speed and duplex */
2741                         bnx2x_program_serdes(phy, params, vars);
2742
2743                 } else { /* AN_mode */
2744                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2745
2746                         /* AN enabled */
2747                         bnx2x_set_brcm_cl37_advertisment(phy, params);
2748
2749                         /* program duplex & pause advertisement (for aneg) */
2750                         bnx2x_set_ieee_aneg_advertisment(phy, params,
2751                                                          vars->ieee_fc);
2752
2753                         /* enable autoneg */
2754                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2755
2756                         /* enable and restart AN */
2757                         bnx2x_restart_autoneg(phy, params, enable_cl73);
2758                 }
2759
2760         } else { /* SGMII mode */
2761                 DP(NETIF_MSG_LINK, "SGMII\n");
2762
2763                 bnx2x_initialize_sgmii_process(phy, params, vars);
2764         }
2765 }
2766
2767 static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2768                             struct link_params *params,
2769                             struct link_vars *vars)
2770 {
2771         u8 rc;
2772         vars->phy_flags |= PHY_SGMII_FLAG;
2773         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2774         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2775         rc = bnx2x_reset_unicore(params, phy, 1);
2776         /* reset the SerDes and wait for reset bit return low */
2777         if (rc != 0)
2778                 return rc;
2779         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2780
2781         return rc;
2782 }
2783
2784 static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2785                           struct link_params *params,
2786                           struct link_vars *vars)
2787 {
2788         u8 rc;
2789         vars->phy_flags = PHY_XGXS_FLAG;
2790         if ((phy->req_line_speed &&
2791              ((phy->req_line_speed == SPEED_100) ||
2792               (phy->req_line_speed == SPEED_10))) ||
2793             (!phy->req_line_speed &&
2794              (phy->speed_cap_mask >=
2795               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2796              (phy->speed_cap_mask <
2797               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2798              ))
2799                 vars->phy_flags |= PHY_SGMII_FLAG;
2800         else
2801                 vars->phy_flags &= ~PHY_SGMII_FLAG;
2802
2803         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2804         bnx2x_set_aer_mmd_xgxs(params, phy);
2805         bnx2x_set_master_ln(params, phy);
2806
2807         rc = bnx2x_reset_unicore(params, phy, 0);
2808         /* reset the SerDes and wait for reset bit return low */
2809         if (rc != 0)
2810                 return rc;
2811
2812         bnx2x_set_aer_mmd_xgxs(params, phy);
2813
2814         /* setting the masterLn_def again after the reset */
2815         bnx2x_set_master_ln(params, phy);
2816         bnx2x_set_swap_lanes(params, phy);
2817
2818         return rc;
2819 }
2820
2821 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2822                                      struct bnx2x_phy *phy,
2823                                      struct link_params *params)
2824 {
2825         u16 cnt, ctrl;
2826         /* Wait for soft reset to get cleared upto 1 sec */
2827         for (cnt = 0; cnt < 1000; cnt++) {
2828                 bnx2x_cl45_read(bp, phy,
2829                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2830                 if (!(ctrl & (1<<15)))
2831                         break;
2832                 msleep(1);
2833         }
2834
2835         if (cnt == 1000)
2836                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
2837                                       " Port %d\n",
2838                          params->port);
2839         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2840         return cnt;
2841 }
2842
2843 static void bnx2x_link_int_enable(struct link_params *params)
2844 {
2845         u8 port = params->port;
2846         u32 mask;
2847         struct bnx2x *bp = params->bp;
2848
2849         /* Setting the status to report on link up for either XGXS or SerDes */
2850         if (params->switch_cfg == SWITCH_CFG_10G) {
2851                 mask = (NIG_MASK_XGXS0_LINK10G |
2852                         NIG_MASK_XGXS0_LINK_STATUS);
2853                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2854                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2855                         params->phy[INT_PHY].type !=
2856                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2857                         mask |= NIG_MASK_MI_INT;
2858                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2859                 }
2860
2861         } else { /* SerDes */
2862                 mask = NIG_MASK_SERDES0_LINK_STATUS;
2863                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2864                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2865                         params->phy[INT_PHY].type !=
2866                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2867                         mask |= NIG_MASK_MI_INT;
2868                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2869                 }
2870         }
2871         bnx2x_bits_en(bp,
2872                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2873                       mask);
2874
2875         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2876                  (params->switch_cfg == SWITCH_CFG_10G),
2877                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2878         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2879                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2880                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2881                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2882         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2883            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2884            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
2885 }
2886
2887 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2888                                      u8 exp_mi_int)
2889 {
2890         u32 latch_status = 0;
2891
2892         /*
2893          * Disable the MI INT ( external phy int ) by writing 1 to the
2894          * status register. Link down indication is high-active-signal,
2895          * so in this case we need to write the status to clear the XOR
2896          */
2897         /* Read Latched signals */
2898         latch_status = REG_RD(bp,
2899                                     NIG_REG_LATCH_STATUS_0 + port*8);
2900         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
2901         /* Handle only those with latched-signal=up.*/
2902         if (exp_mi_int)
2903                 bnx2x_bits_en(bp,
2904                               NIG_REG_STATUS_INTERRUPT_PORT0
2905                               + port*4,
2906                               NIG_STATUS_EMAC0_MI_INT);
2907         else
2908                 bnx2x_bits_dis(bp,
2909                                NIG_REG_STATUS_INTERRUPT_PORT0
2910                                + port*4,
2911                                NIG_STATUS_EMAC0_MI_INT);
2912
2913         if (latch_status & 1) {
2914
2915                 /* For all latched-signal=up : Re-Arm Latch signals */
2916                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
2917                        (latch_status & 0xfffe) | (latch_status & 1));
2918         }
2919         /* For all latched-signal=up,Write original_signal to status */
2920 }
2921
2922 static void bnx2x_link_int_ack(struct link_params *params,
2923                                struct link_vars *vars, u8 is_10g)
2924 {
2925         struct bnx2x *bp = params->bp;
2926         u8 port = params->port;
2927
2928         /*
2929          * First reset all status we assume only one line will be
2930          * change at a time
2931          */
2932         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2933                        (NIG_STATUS_XGXS0_LINK10G |
2934                         NIG_STATUS_XGXS0_LINK_STATUS |
2935                         NIG_STATUS_SERDES0_LINK_STATUS));
2936         if (vars->phy_link_up) {
2937                 if (is_10g) {
2938                         /*
2939                          * Disable the 10G link interrupt by writing 1 to the
2940                          * status register
2941                          */
2942                         DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2943                         bnx2x_bits_en(bp,
2944                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2945                                       NIG_STATUS_XGXS0_LINK10G);
2946
2947                 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2948                         /*
2949                          * Disable the link interrupt by writing 1 to the
2950                          * relevant lane in the status register
2951                          */
2952                         u32 ser_lane = ((params->lane_config &
2953                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2954                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2955
2956                         DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2957                                  vars->line_speed);
2958                         bnx2x_bits_en(bp,
2959                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2960                                       ((1 << ser_lane) <<
2961                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
2962
2963                 } else { /* SerDes */
2964                         DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2965                         /*
2966                          * Disable the link interrupt by writing 1 to the status
2967                          * register
2968                          */
2969                         bnx2x_bits_en(bp,
2970                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2971                                       NIG_STATUS_SERDES0_LINK_STATUS);
2972                 }
2973
2974         }
2975 }
2976
2977 static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2978 {
2979         u8 *str_ptr = str;
2980         u32 mask = 0xf0000000;
2981         u8 shift = 8*4;
2982         u8 digit;
2983         u8 remove_leading_zeros = 1;
2984         if (*len < 10) {
2985                 /* Need more than 10chars for this format */
2986                 *str_ptr = '\0';
2987                 (*len)--;
2988                 return -EINVAL;
2989         }
2990         while (shift > 0) {
2991
2992                 shift -= 4;
2993                 digit = ((num & mask) >> shift);
2994                 if (digit == 0 && remove_leading_zeros) {
2995                         mask = mask >> 4;
2996                         continue;
2997                 } else if (digit < 0xa)
2998                         *str_ptr = digit + '0';
2999                 else
3000                         *str_ptr = digit - 0xa + 'a';
3001                 remove_leading_zeros = 0;
3002                 str_ptr++;
3003                 (*len)--;
3004                 mask = mask >> 4;
3005                 if (shift == 4*4) {
3006                         *str_ptr = '.';
3007                         str_ptr++;
3008                         (*len)--;
3009                         remove_leading_zeros = 1;
3010                 }
3011         }
3012         return 0;
3013 }
3014
3015
3016 static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
3017 {
3018         str[0] = '\0';
3019         (*len)--;
3020         return 0;
3021 }
3022
3023 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3024                               u8 *version, u16 len)
3025 {
3026         struct bnx2x *bp;
3027         u32 spirom_ver = 0;
3028         u8 status = 0;
3029         u8 *ver_p = version;
3030         u16 remain_len = len;
3031         if (version == NULL || params == NULL)
3032                 return -EINVAL;
3033         bp = params->bp;
3034
3035         /* Extract first external phy*/
3036         version[0] = '\0';
3037         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
3038
3039         if (params->phy[EXT_PHY1].format_fw_ver) {
3040                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3041                                                               ver_p,
3042                                                               &remain_len);
3043                 ver_p += (len - remain_len);
3044         }
3045         if ((params->num_phys == MAX_PHYS) &&
3046             (params->phy[EXT_PHY2].ver_addr != 0)) {
3047                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
3048                 if (params->phy[EXT_PHY2].format_fw_ver) {
3049                         *ver_p = '/';
3050                         ver_p++;
3051                         remain_len--;
3052                         status |= params->phy[EXT_PHY2].format_fw_ver(
3053                                 spirom_ver,
3054                                 ver_p,
3055                                 &remain_len);
3056                         ver_p = version + (len - remain_len);
3057                 }
3058         }
3059         *ver_p = '\0';
3060         return status;
3061 }
3062
3063 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3064                                     struct link_params *params)
3065 {
3066         u8 port = params->port;
3067         struct bnx2x *bp = params->bp;
3068
3069         if (phy->req_line_speed != SPEED_1000) {
3070                 u32 md_devad;
3071
3072                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3073
3074                 /* change the uni_phy_addr in the nig */
3075                 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3076                                        port*0x18));
3077
3078                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3079
3080                 bnx2x_cl45_write(bp, phy,
3081                                  5,
3082                                  (MDIO_REG_BANK_AER_BLOCK +
3083                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
3084                                  0x2800);
3085
3086                 bnx2x_cl45_write(bp, phy,
3087                                  5,
3088                                  (MDIO_REG_BANK_CL73_IEEEB0 +
3089                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3090                                  0x6041);
3091                 msleep(200);
3092                 /* set aer mmd back */
3093                 bnx2x_set_aer_mmd_xgxs(params, phy);
3094
3095                 /* and md_devad */
3096                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3097         } else {
3098                 u16 mii_ctrl;
3099                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3100                 bnx2x_cl45_read(bp, phy, 5,
3101                                 (MDIO_REG_BANK_COMBO_IEEE0 +
3102                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3103                                 &mii_ctrl);
3104                 bnx2x_cl45_write(bp, phy, 5,
3105                                  (MDIO_REG_BANK_COMBO_IEEE0 +
3106                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3107                                  mii_ctrl |
3108                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3109         }
3110 }
3111
3112 u8 bnx2x_set_led(struct link_params *params,
3113                  struct link_vars *vars, u8 mode, u32 speed)
3114 {
3115         u8 port = params->port;
3116         u16 hw_led_mode = params->hw_led_mode;
3117         u8 rc = 0, phy_idx;
3118         u32 tmp;
3119         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3120         struct bnx2x *bp = params->bp;
3121         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3122         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3123                  speed, hw_led_mode);
3124         /* In case */
3125         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3126                 if (params->phy[phy_idx].set_link_led) {
3127                         params->phy[phy_idx].set_link_led(
3128                                 &params->phy[phy_idx], params, mode);
3129                 }
3130         }
3131
3132         switch (mode) {
3133         case LED_MODE_FRONT_PANEL_OFF:
3134         case LED_MODE_OFF:
3135                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3136                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3137                        SHARED_HW_CFG_LED_MAC1);
3138
3139                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3140                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3141                 break;
3142
3143         case LED_MODE_OPER:
3144                 /*
3145                  * For all other phys, OPER mode is same as ON, so in case
3146                  * link is down, do nothing
3147                  */
3148                 if (!vars->link_up)
3149                         break;
3150         case LED_MODE_ON:
3151                 if (params->phy[EXT_PHY1].type ==
3152                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 &&
3153                     CHIP_IS_E2(bp) && params->num_phys == 2) {
3154                         /*
3155                          * This is a work-around for E2+8727 Configurations
3156                          */
3157                         if (mode == LED_MODE_ON ||
3158                                 speed == SPEED_10000){
3159                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3160                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3161
3162                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3163                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3164                                         (tmp | EMAC_LED_OVERRIDE));
3165                                 return rc;
3166                         }
3167                 } else if (SINGLE_MEDIA_DIRECT(params)) {
3168                         /*
3169                          * This is a work-around for HW issue found when link
3170                          * is up in CL73
3171                          */
3172                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3173                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3174                 } else {
3175                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
3176                 }
3177
3178                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
3179                 /* Set blinking rate to ~15.9Hz */
3180                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3181                        LED_BLINK_RATE_VAL);
3182                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3183                        port*4, 1);
3184                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3185                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
3186
3187                 if (CHIP_IS_E1(bp) &&
3188                     ((speed == SPEED_2500) ||
3189                      (speed == SPEED_1000) ||
3190                      (speed == SPEED_100) ||
3191                      (speed == SPEED_10))) {
3192                         /*
3193                          * On Everest 1 Ax chip versions for speeds less than
3194                          * 10G LED scheme is different
3195                          */
3196                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3197                                + port*4, 1);
3198                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3199                                port*4, 0);
3200                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3201                                port*4, 1);
3202                 }
3203                 break;
3204
3205         default:
3206                 rc = -EINVAL;
3207                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3208                          mode);
3209                 break;
3210         }
3211         return rc;
3212
3213 }
3214
3215 /*
3216  * This function comes to reflect the actual link state read DIRECTLY from the
3217  * HW
3218  */
3219 u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3220                    u8 is_serdes)
3221 {
3222         struct bnx2x *bp = params->bp;
3223         u16 gp_status = 0, phy_index = 0;
3224         u8 ext_phy_link_up = 0, serdes_phy_type;
3225         struct link_vars temp_vars;
3226
3227         CL22_RD_OVER_CL45(bp, &params->phy[INT_PHY],
3228                           MDIO_REG_BANK_GP_STATUS,
3229                           MDIO_GP_STATUS_TOP_AN_STATUS1,
3230                           &gp_status);
3231         /* link is up only if both local phy and external phy are up */
3232         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3233                 return -ESRCH;
3234
3235         switch (params->num_phys) {
3236         case 1:
3237                 /* No external PHY */
3238                 return 0;
3239         case 2:
3240                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3241                         &params->phy[EXT_PHY1],
3242                         params, &temp_vars);
3243                 break;
3244         case 3: /* Dual Media */
3245                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3246                       phy_index++) {
3247                         serdes_phy_type = ((params->phy[phy_index].media_type ==
3248                                             ETH_PHY_SFP_FIBER) ||
3249                                            (params->phy[phy_index].media_type ==
3250                                             ETH_PHY_XFP_FIBER));
3251
3252                         if (is_serdes != serdes_phy_type)
3253                                 continue;
3254                         if (params->phy[phy_index].read_status) {
3255                                 ext_phy_link_up |=
3256                                         params->phy[phy_index].read_status(
3257                                                 &params->phy[phy_index],
3258                                                 params, &temp_vars);
3259                         }
3260                 }
3261                 break;
3262         }
3263         if (ext_phy_link_up)
3264                 return 0;
3265         return -ESRCH;
3266 }
3267
3268 static u8 bnx2x_link_initialize(struct link_params *params,
3269                                 struct link_vars *vars)
3270 {
3271         u8 rc = 0;
3272         u8 phy_index, non_ext_phy;
3273         struct bnx2x *bp = params->bp;
3274         /*
3275          * In case of external phy existence, the line speed would be the
3276          * line speed linked up by the external phy. In case it is direct
3277          * only, then the line_speed during initialization will be
3278          * equal to the req_line_speed
3279          */
3280         vars->line_speed = params->phy[INT_PHY].req_line_speed;
3281
3282         /*
3283          * Initialize the internal phy in case this is a direct board
3284          * (no external phys), or this board has external phy which requires
3285          * to first.
3286          */
3287
3288         if (params->phy[INT_PHY].config_init)
3289                 params->phy[INT_PHY].config_init(
3290                         &params->phy[INT_PHY],
3291                         params, vars);
3292
3293         /* init ext phy and enable link state int */
3294         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3295                        (params->loopback_mode == LOOPBACK_XGXS));
3296
3297         if (non_ext_phy ||
3298             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3299             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3300                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3301                 if (vars->line_speed == SPEED_AUTO_NEG)
3302                         bnx2x_set_parallel_detection(phy, params);
3303                 bnx2x_init_internal_phy(phy, params, vars);
3304         }
3305
3306         /* Init external phy*/
3307         if (!non_ext_phy)
3308                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3309                       phy_index++) {
3310                         /*
3311                          * No need to initialize second phy in case of first
3312                          * phy only selection. In case of second phy, we do
3313                          * need to initialize the first phy, since they are
3314                          * connected.
3315                          */
3316                         if (phy_index == EXT_PHY2 &&
3317                             (bnx2x_phy_selection(params) ==
3318                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
3319                                 DP(NETIF_MSG_LINK, "Ignoring second phy\n");
3320                                 continue;
3321                         }
3322                         params->phy[phy_index].config_init(
3323                                 &params->phy[phy_index],
3324                                 params, vars);
3325                 }
3326
3327         /* Reset the interrupt indication after phy was initialized */
3328         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3329                        params->port*4,
3330                        (NIG_STATUS_XGXS0_LINK10G |
3331                         NIG_STATUS_XGXS0_LINK_STATUS |
3332                         NIG_STATUS_SERDES0_LINK_STATUS |
3333                         NIG_MASK_MI_INT));
3334         return rc;
3335 }
3336
3337 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3338                                  struct link_params *params)
3339 {
3340         /* reset the SerDes/XGXS */
3341         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3342                (0x1ff << (params->port*16)));
3343 }
3344
3345 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3346                                         struct link_params *params)
3347 {
3348         struct bnx2x *bp = params->bp;
3349         u8 gpio_port;
3350         /* HW reset */
3351         if (CHIP_IS_E2(bp))
3352                 gpio_port = BP_PATH(bp);
3353         else
3354                 gpio_port = params->port;
3355         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3356                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
3357                        gpio_port);
3358         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3359                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
3360                        gpio_port);
3361         DP(NETIF_MSG_LINK, "reset external PHY\n");
3362 }
3363
3364 static u8 bnx2x_update_link_down(struct link_params *params,
3365                                struct link_vars *vars)
3366 {
3367         struct bnx2x *bp = params->bp;
3368         u8 port = params->port;
3369
3370         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
3371         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
3372
3373         /* indicate no mac active */
3374         vars->mac_type = MAC_TYPE_NONE;
3375
3376         /* update shared memory */
3377         vars->link_status = 0;
3378         vars->line_speed = 0;
3379         bnx2x_update_mng(params, vars->link_status);
3380
3381         /* activate nig drain */
3382         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3383
3384         /* disable emac */
3385         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3386
3387         msleep(10);
3388
3389         /* reset BigMac */
3390         bnx2x_bmac_rx_disable(bp, params->port);
3391         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3392                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3393         return 0;
3394 }
3395
3396 static u8 bnx2x_update_link_up(struct link_params *params,
3397                              struct link_vars *vars,
3398                              u8 link_10g)
3399 {
3400         struct bnx2x *bp = params->bp;
3401         u8 port = params->port;
3402         u8 rc = 0;
3403
3404         vars->link_status |= LINK_STATUS_LINK_UP;
3405
3406         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3407                 vars->link_status |=
3408                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
3409
3410         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3411                 vars->link_status |=
3412                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
3413
3414         if (link_10g) {
3415                 bnx2x_bmac_enable(params, vars, 0);
3416                 bnx2x_set_led(params, vars,
3417                               LED_MODE_OPER, SPEED_10000);
3418         } else {
3419                 rc = bnx2x_emac_program(params, vars);
3420
3421                 bnx2x_emac_enable(params, vars, 0);
3422
3423                 /* AN complete? */
3424                 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3425                     && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3426                     SINGLE_MEDIA_DIRECT(params))
3427                         bnx2x_set_gmii_tx_driver(params);
3428         }
3429
3430         /* PBF - link up */
3431         if (!(CHIP_IS_E2(bp)))
3432                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3433                                        vars->line_speed);
3434
3435         /* disable drain */
3436         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
3437
3438         /* update shared memory */
3439         bnx2x_update_mng(params, vars->link_status);
3440         msleep(20);
3441         return rc;
3442 }
3443 /*
3444  * The bnx2x_link_update function should be called upon link
3445  * interrupt.
3446  * Link is considered up as follows:
3447  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3448  *   to be up
3449  * - SINGLE_MEDIA - The link between the 577xx and the external
3450  *   phy (XGXS) need to up as well as the external link of the
3451  *   phy (PHY_EXT1)
3452  * - DUAL_MEDIA - The link between the 577xx and the first
3453  *   external phy needs to be up, and at least one of the 2
3454  *   external phy link must be up.
3455  */
3456 u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3457 {
3458         struct bnx2x *bp = params->bp;
3459         struct link_vars phy_vars[MAX_PHYS];
3460         u8 port = params->port;
3461         u8 link_10g, phy_index;
3462         u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
3463         u8 is_mi_int = 0;
3464         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3465         u8 active_external_phy = INT_PHY;
3466         vars->link_status = 0;
3467         for (phy_index = INT_PHY; phy_index < params->num_phys;
3468               phy_index++) {
3469                 phy_vars[phy_index].flow_ctrl = 0;
3470                 phy_vars[phy_index].link_status = 0;
3471                 phy_vars[phy_index].line_speed = 0;
3472                 phy_vars[phy_index].duplex = DUPLEX_FULL;
3473                 phy_vars[phy_index].phy_link_up = 0;
3474                 phy_vars[phy_index].link_up = 0;
3475         }
3476
3477         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3478                  port, (vars->phy_flags & PHY_XGXS_FLAG),
3479                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3480
3481         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3482                                 port*0x18) > 0);
3483         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3484                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3485                  is_mi_int,
3486                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3487
3488         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3489           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3490           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3491
3492         /* disable emac */
3493         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3494
3495         /*
3496          * Step 1:
3497          * Check external link change only for external phys, and apply
3498          * priority selection between them in case the link on both phys
3499          * is up. Note that the instead of the common vars, a temporary
3500          * vars argument is used since each phy may have different link/
3501          * speed/duplex result
3502          */
3503         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3504               phy_index++) {
3505                 struct bnx2x_phy *phy = &params->phy[phy_index];
3506                 if (!phy->read_status)
3507                         continue;
3508                 /* Read link status and params of this ext phy */
3509                 cur_link_up = phy->read_status(phy, params,
3510                                                &phy_vars[phy_index]);
3511                 if (cur_link_up) {
3512                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3513                                    phy_index);
3514                 } else {
3515                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3516                                    phy_index);
3517                         continue;
3518                 }
3519
3520                 if (!ext_phy_link_up) {
3521                         ext_phy_link_up = 1;
3522                         active_external_phy = phy_index;
3523                 } else {
3524                         switch (bnx2x_phy_selection(params)) {
3525                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3526                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3527                         /*
3528                          * In this option, the first PHY makes sure to pass the
3529                          * traffic through itself only.
3530                          * Its not clear how to reset the link on the second phy
3531                          */
3532                                 active_external_phy = EXT_PHY1;
3533                                 break;
3534                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3535                         /*
3536                          * In this option, the first PHY makes sure to pass the
3537                          * traffic through the second PHY.
3538                          */
3539                                 active_external_phy = EXT_PHY2;
3540                                 break;
3541                         default:
3542                         /*
3543                          * Link indication on both PHYs with the following cases
3544                          * is invalid:
3545                          * - FIRST_PHY means that second phy wasn't initialized,
3546                          * hence its link is expected to be down
3547                          * - SECOND_PHY means that first phy should not be able
3548                          * to link up by itself (using configuration)
3549                          * - DEFAULT should be overriden during initialiazation
3550                          */
3551                                 DP(NETIF_MSG_LINK, "Invalid link indication"
3552                                            "mpc=0x%x. DISABLING LINK !!!\n",
3553                                            params->multi_phy_config);
3554                                 ext_phy_link_up = 0;
3555                                 break;
3556                         }
3557                 }
3558         }
3559         prev_line_speed = vars->line_speed;
3560         /*
3561          * Step 2:
3562          * Read the status of the internal phy. In case of
3563          * DIRECT_SINGLE_MEDIA board, this link is the external link,
3564          * otherwise this is the link between the 577xx and the first
3565          * external phy
3566          */
3567         if (params->phy[INT_PHY].read_status)
3568                 params->phy[INT_PHY].read_status(
3569                         &params->phy[INT_PHY],
3570                         params, vars);
3571         /*
3572          * The INT_PHY flow control reside in the vars. This include the
3573          * case where the speed or flow control are not set to AUTO.
3574          * Otherwise, the active external phy flow control result is set
3575          * to the vars. The ext_phy_line_speed is needed to check if the
3576          * speed is different between the internal phy and external phy.
3577          * This case may be result of intermediate link speed change.
3578          */
3579         if (active_external_phy > INT_PHY) {
3580                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3581                 /*
3582                  * Link speed is taken from the XGXS. AN and FC result from
3583                  * the external phy.
3584                  */
3585                 vars->link_status |= phy_vars[active_external_phy].link_status;
3586
3587                 /*
3588                  * if active_external_phy is first PHY and link is up - disable
3589                  * disable TX on second external PHY
3590                  */
3591                 if (active_external_phy == EXT_PHY1) {
3592                         if (params->phy[EXT_PHY2].phy_specific_func) {
3593                                 DP(NETIF_MSG_LINK, "Disabling TX on"
3594                                                    " EXT_PHY2\n");
3595                                 params->phy[EXT_PHY2].phy_specific_func(
3596                                         &params->phy[EXT_PHY2],
3597                                         params, DISABLE_TX);
3598                         }
3599                 }
3600
3601                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3602                 vars->duplex = phy_vars[active_external_phy].duplex;
3603                 if (params->phy[active_external_phy].supported &
3604                     SUPPORTED_FIBRE)
3605                         vars->link_status |= LINK_STATUS_SERDES_LINK;
3606                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3607                            active_external_phy);
3608         }
3609
3610         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3611               phy_index++) {
3612                 if (params->phy[phy_index].flags &
3613                     FLAGS_REARM_LATCH_SIGNAL) {
3614                         bnx2x_rearm_latch_signal(bp, port,
3615                                                  phy_index ==
3616                                                  active_external_phy);
3617                         break;
3618                 }
3619         }
3620         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3621                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3622                    vars->link_status, ext_phy_line_speed);
3623         /*
3624          * Upon link speed change set the NIG into drain mode. Comes to
3625          * deals with possible FIFO glitch due to clk change when speed
3626          * is decreased without link down indicator
3627          */
3628
3629         if (vars->phy_link_up) {
3630                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3631                     (ext_phy_line_speed != vars->line_speed)) {
3632                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
3633                                    " different than the external"
3634                                    " link speed %d\n", vars->line_speed,
3635                                    ext_phy_line_speed);
3636                         vars->phy_link_up = 0;
3637                 } else if (prev_line_speed != vars->line_speed) {
3638                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
3639                                0);
3640                         msleep(1);
3641                 }
3642         }
3643
3644         /* anything 10 and over uses the bmac */
3645         link_10g = ((vars->line_speed == SPEED_10000) ||
3646                     (vars->line_speed == SPEED_12000) ||
3647                     (vars->line_speed == SPEED_12500) ||
3648                     (vars->line_speed == SPEED_13000) ||
3649                     (vars->line_speed == SPEED_15000) ||
3650                     (vars->line_speed == SPEED_16000));
3651
3652         bnx2x_link_int_ack(params, vars, link_10g);
3653
3654         /*
3655          * In case external phy link is up, and internal link is down
3656          * (not initialized yet probably after link initialization, it
3657          * needs to be initialized.
3658          * Note that after link down-up as result of cable plug, the xgxs
3659          * link would probably become up again without the need
3660          * initialize it
3661          */
3662         if (!(SINGLE_MEDIA_DIRECT(params))) {
3663                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3664                            " init_preceding = %d\n", ext_phy_link_up,
3665                            vars->phy_link_up,
3666                            params->phy[EXT_PHY1].flags &
3667                            FLAGS_INIT_XGXS_FIRST);
3668                 if (!(params->phy[EXT_PHY1].flags &
3669                       FLAGS_INIT_XGXS_FIRST)
3670                     && ext_phy_link_up && !vars->phy_link_up) {
3671                         vars->line_speed = ext_phy_line_speed;
3672                         if (vars->line_speed < SPEED_1000)
3673                                 vars->phy_flags |= PHY_SGMII_FLAG;
3674                         else
3675                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
3676                         bnx2x_init_internal_phy(&params->phy[INT_PHY],
3677                                                 params,
3678                                                 vars);
3679                 }
3680         }
3681         /*
3682          * Link is up only if both local phy and external phy (in case of
3683          * non-direct board) are up
3684          */
3685         vars->link_up = (vars->phy_link_up &&
3686                          (ext_phy_link_up ||
3687                           SINGLE_MEDIA_DIRECT(params)));
3688
3689         if (vars->link_up)
3690                 rc = bnx2x_update_link_up(params, vars, link_10g);
3691         else
3692                 rc = bnx2x_update_link_down(params, vars);
3693
3694         return rc;
3695 }
3696
3697
3698 /*****************************************************************************/
3699 /*                          External Phy section                             */
3700 /*****************************************************************************/
3701 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3702 {
3703         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3704                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3705         msleep(1);
3706         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3707                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3708 }
3709
3710 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3711                                       u32 spirom_ver, u32 ver_addr)
3712 {
3713         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3714                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
3715
3716         if (ver_addr)
3717                 REG_WR(bp, ver_addr, spirom_ver);
3718 }
3719
3720 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3721                                       struct bnx2x_phy *phy,
3722                                       u8 port)
3723 {
3724         u16 fw_ver1, fw_ver2;
3725
3726         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3727                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3728         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3729                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3730         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3731                                   phy->ver_addr);
3732 }
3733
3734 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3735                                     struct bnx2x_phy *phy,
3736                                     struct link_vars *vars)
3737 {
3738         u16 val;
3739         struct bnx2x *bp = params->bp;
3740         /* read modify write pause advertizing */
3741         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3742
3743         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3744
3745         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3746         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3747         if ((vars->ieee_fc &
3748             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3749             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3750                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3751         }
3752         if ((vars->ieee_fc &
3753             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3754             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3755                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3756         }
3757         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3758         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3759 }
3760
3761 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3762                                    struct link_params *params,
3763                                    struct link_vars *vars)
3764 {
3765         struct bnx2x *bp = params->bp;
3766         u16 ld_pause;           /* local */
3767         u16 lp_pause;           /* link partner */
3768         u16 pause_result;
3769         u8 ret = 0;
3770         /* read twice */
3771
3772         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3773
3774         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3775                 vars->flow_ctrl = phy->req_flow_ctrl;
3776         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3777                 vars->flow_ctrl = params->req_fc_auto_adv;
3778         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3779                 ret = 1;
3780                 bnx2x_cl45_read(bp, phy,
3781                                 MDIO_AN_DEVAD,
3782                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3783                 bnx2x_cl45_read(bp, phy,
3784                                 MDIO_AN_DEVAD,
3785                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3786                 pause_result = (ld_pause &
3787                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3788                 pause_result |= (lp_pause &
3789                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3790                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3791                    pause_result);
3792                 bnx2x_pause_resolve(vars, pause_result);
3793         }
3794         return ret;
3795 }
3796
3797 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3798                                        struct bnx2x_phy *phy,
3799                                        struct link_vars *vars)
3800 {
3801         u16 val;
3802         bnx2x_cl45_read(bp, phy,
3803                         MDIO_AN_DEVAD,
3804                         MDIO_AN_REG_STATUS, &val);
3805         bnx2x_cl45_read(bp, phy,
3806                         MDIO_AN_DEVAD,
3807                         MDIO_AN_REG_STATUS, &val);
3808         if (val & (1<<5))
3809                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3810         if ((val & (1<<0)) == 0)
3811                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3812 }
3813
3814 /******************************************************************/
3815 /*              common BCM8073/BCM8727 PHY SECTION                */
3816 /******************************************************************/
3817 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3818                                   struct link_params *params,
3819                                   struct link_vars *vars)
3820 {
3821         struct bnx2x *bp = params->bp;
3822         if (phy->req_line_speed == SPEED_10 ||
3823             phy->req_line_speed == SPEED_100) {
3824                 vars->flow_ctrl = phy->req_flow_ctrl;
3825                 return;
3826         }
3827
3828         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3829             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3830                 u16 pause_result;
3831                 u16 ld_pause;           /* local */
3832                 u16 lp_pause;           /* link partner */
3833                 bnx2x_cl45_read(bp, phy,
3834                                 MDIO_AN_DEVAD,
3835                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3836
3837                 bnx2x_cl45_read(bp, phy,
3838                                 MDIO_AN_DEVAD,
3839                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3840                 pause_result = (ld_pause &
3841                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3842                 pause_result |= (lp_pause &
3843                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3844
3845                 bnx2x_pause_resolve(vars, pause_result);
3846                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3847                            pause_result);
3848         }
3849 }
3850 static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3851                                               struct bnx2x_phy *phy,
3852                                               u8 port)
3853 {
3854         u32 count = 0;
3855         u16 fw_ver1, fw_msgout;
3856         u8 rc = 0;
3857
3858         /* Boot port from external ROM  */
3859         /* EDC grst */
3860         bnx2x_cl45_write(bp, phy,
3861                          MDIO_PMA_DEVAD,
3862                          MDIO_PMA_REG_GEN_CTRL,
3863                          0x0001);
3864
3865         /* ucode reboot and rst */
3866         bnx2x_cl45_write(bp, phy,
3867                          MDIO_PMA_DEVAD,
3868                          MDIO_PMA_REG_GEN_CTRL,
3869                          0x008c);
3870
3871         bnx2x_cl45_write(bp, phy,
3872                          MDIO_PMA_DEVAD,
3873                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3874
3875         /* Reset internal microprocessor */
3876         bnx2x_cl45_write(bp, phy,
3877                          MDIO_PMA_DEVAD,
3878                          MDIO_PMA_REG_GEN_CTRL,
3879                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3880
3881         /* Release srst bit */
3882         bnx2x_cl45_write(bp, phy,
3883                          MDIO_PMA_DEVAD,
3884                          MDIO_PMA_REG_GEN_CTRL,
3885                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3886
3887         /* Delay 100ms per the PHY specifications */
3888         msleep(100);
3889
3890         /* 8073 sometimes taking longer to download */
3891         do {
3892                 count++;
3893                 if (count > 300) {
3894                         DP(NETIF_MSG_LINK,
3895                                  "bnx2x_8073_8727_external_rom_boot port %x:"
3896                                  "Download failed. fw version = 0x%x\n",
3897                                  port, fw_ver1);
3898                         rc = -EINVAL;
3899                         break;
3900                 }
3901
3902                 bnx2x_cl45_read(bp, phy,
3903                                 MDIO_PMA_DEVAD,
3904                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3905                 bnx2x_cl45_read(bp, phy,
3906                                 MDIO_PMA_DEVAD,
3907                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3908
3909                 msleep(1);
3910         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3911                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3912                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
3913
3914         /* Clear ser_boot_ctl bit */
3915         bnx2x_cl45_write(bp, phy,
3916                          MDIO_PMA_DEVAD,
3917                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3918         bnx2x_save_bcm_spirom_ver(bp, phy, port);
3919
3920         DP(NETIF_MSG_LINK,
3921                  "bnx2x_8073_8727_external_rom_boot port %x:"
3922                  "Download complete. fw version = 0x%x\n",
3923                  port, fw_ver1);
3924
3925         return rc;
3926 }
3927
3928 /******************************************************************/
3929 /*                      BCM8073 PHY SECTION                       */
3930 /******************************************************************/
3931 static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3932 {
3933         /* This is only required for 8073A1, version 102 only */
3934         u16 val;
3935
3936         /* Read 8073 HW revision*/
3937         bnx2x_cl45_read(bp, phy,
3938                         MDIO_PMA_DEVAD,
3939                         MDIO_PMA_REG_8073_CHIP_REV, &val);
3940
3941         if (val != 1) {
3942                 /* No need to workaround in 8073 A1 */
3943                 return 0;
3944         }
3945
3946         bnx2x_cl45_read(bp, phy,
3947                         MDIO_PMA_DEVAD,
3948                         MDIO_PMA_REG_ROM_VER2, &val);
3949
3950         /* SNR should be applied only for version 0x102 */
3951         if (val != 0x102)
3952                 return 0;
3953
3954         return 1;
3955 }
3956
3957 static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3958 {
3959         u16 val, cnt, cnt1 ;
3960
3961         bnx2x_cl45_read(bp, phy,
3962                         MDIO_PMA_DEVAD,
3963                         MDIO_PMA_REG_8073_CHIP_REV, &val);
3964
3965         if (val > 0) {
3966                 /* No need to workaround in 8073 A1 */
3967                 return 0;
3968         }
3969         /* XAUI workaround in 8073 A0: */
3970
3971         /*
3972          * After loading the boot ROM and restarting Autoneg, poll
3973          * Dev1, Reg $C820:
3974          */
3975
3976         for (cnt = 0; cnt < 1000; cnt++) {
3977                 bnx2x_cl45_read(bp, phy,
3978                                 MDIO_PMA_DEVAD,
3979                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3980                                 &val);
3981                   /*
3982                    * If bit [14] = 0 or bit [13] = 0, continue on with
3983                    * system initialization (XAUI work-around not required, as
3984                    * these bits indicate 2.5G or 1G link up).
3985                    */
3986                 if (!(val & (1<<14)) || !(val & (1<<13))) {
3987                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
3988                         return 0;
3989                 } else if (!(val & (1<<15))) {
3990                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
3991                         /*
3992                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
3993                          * MSB (bit15) goes to 1 (indicating that the XAUI
3994                          * workaround has completed), then continue on with
3995                          * system initialization.
3996                          */
3997                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
3998                                 bnx2x_cl45_read(bp, phy,
3999                                         MDIO_PMA_DEVAD,
4000                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
4001                                 if (val & (1<<15)) {
4002                                         DP(NETIF_MSG_LINK,
4003                                           "XAUI workaround has completed\n");
4004                                         return 0;
4005                                  }
4006                                  msleep(3);
4007                         }
4008                         break;
4009                 }
4010                 msleep(3);
4011         }
4012         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4013         return -EINVAL;
4014 }
4015
4016 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4017 {
4018         /* Force KR or KX */
4019         bnx2x_cl45_write(bp, phy,
4020                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4021         bnx2x_cl45_write(bp, phy,
4022                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4023         bnx2x_cl45_write(bp, phy,
4024                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4025         bnx2x_cl45_write(bp, phy,
4026                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4027 }
4028
4029 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
4030                                       struct bnx2x_phy *phy,
4031                                       struct link_vars *vars)
4032 {
4033         u16 cl37_val;
4034         struct bnx2x *bp = params->bp;
4035         bnx2x_cl45_read(bp, phy,
4036                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
4037
4038         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4039         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4040         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4041         if ((vars->ieee_fc &
4042             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4043             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4044                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4045         }
4046         if ((vars->ieee_fc &
4047             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4048             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4049                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4050         }
4051         if ((vars->ieee_fc &
4052             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4053             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4054                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4055         }
4056         DP(NETIF_MSG_LINK,
4057                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4058
4059         bnx2x_cl45_write(bp, phy,
4060                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
4061         msleep(500);
4062 }
4063
4064 static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
4065                                  struct link_params *params,
4066                                  struct link_vars *vars)
4067 {
4068         struct bnx2x *bp = params->bp;
4069         u16 val = 0, tmp1;
4070         u8 gpio_port;
4071         DP(NETIF_MSG_LINK, "Init 8073\n");
4072
4073         if (CHIP_IS_E2(bp))
4074                 gpio_port = BP_PATH(bp);
4075         else
4076                 gpio_port = params->port;
4077         /* Restore normal power mode*/
4078         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4079                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4080
4081         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4082                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4083
4084         /* enable LASI */
4085         bnx2x_cl45_write(bp, phy,
4086                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4087         bnx2x_cl45_write(bp, phy,
4088                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,  0x0004);
4089
4090         bnx2x_8073_set_pause_cl37(params, phy, vars);
4091
4092         bnx2x_cl45_read(bp, phy,
4093                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4094
4095         bnx2x_cl45_read(bp, phy,
4096                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4097
4098         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
4099
4100         /* Swap polarity if required - Must be done only in non-1G mode */
4101         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4102                 /* Configure the 8073 to swap _P and _N of the KR lines */
4103                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4104                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4105                 bnx2x_cl45_read(bp, phy,
4106                                 MDIO_PMA_DEVAD,
4107                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4108                 bnx2x_cl45_write(bp, phy,
4109                                  MDIO_PMA_DEVAD,
4110                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4111                                  (val | (3<<9)));
4112         }
4113
4114
4115         /* Enable CL37 BAM */
4116         if (REG_RD(bp, params->shmem_base +
4117                          offsetof(struct shmem_region, dev_info.
4118                                   port_hw_config[params->port].default_cfg)) &
4119             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4120
4121                 bnx2x_cl45_read(bp, phy,
4122                                 MDIO_AN_DEVAD,
4123                                 MDIO_AN_REG_8073_BAM, &val);
4124                 bnx2x_cl45_write(bp, phy,
4125                                  MDIO_AN_DEVAD,
4126                                  MDIO_AN_REG_8073_BAM, val | 1);
4127                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4128         }
4129         if (params->loopback_mode == LOOPBACK_EXT) {
4130                 bnx2x_807x_force_10G(bp, phy);
4131                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4132                 return 0;
4133         } else {
4134                 bnx2x_cl45_write(bp, phy,
4135                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4136         }
4137         if (phy->req_line_speed != SPEED_AUTO_NEG) {
4138                 if (phy->req_line_speed == SPEED_10000) {
4139                         val = (1<<7);
4140                 } else if (phy->req_line_speed ==  SPEED_2500) {
4141                         val = (1<<5);
4142                         /*
4143                          * Note that 2.5G works only when used with 1G
4144                          * advertisment
4145                          */
4146                 } else
4147                         val = (1<<5);
4148         } else {
4149                 val = 0;
4150                 if (phy->speed_cap_mask &
4151                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4152                         val |= (1<<7);
4153
4154                 /* Note that 2.5G works only when used with 1G advertisment */
4155                 if (phy->speed_cap_mask &
4156                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4157                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4158                         val |= (1<<5);
4159                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4160         }
4161
4162         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4163         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
4164
4165         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4166              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4167             (phy->req_line_speed == SPEED_2500)) {
4168                 u16 phy_ver;
4169                 /* Allow 2.5G for A1 and above */
4170                 bnx2x_cl45_read(bp, phy,
4171                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4172                                 &phy_ver);
4173                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4174                 if (phy_ver > 0)
4175                         tmp1 |= 1;
4176                 else
4177                         tmp1 &= 0xfffe;
4178         } else {
4179                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4180                 tmp1 &= 0xfffe;
4181         }
4182
4183         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4184         /* Add support for CL37 (passive mode) II */
4185
4186         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4187         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4188                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4189                                   0x20 : 0x40)));
4190
4191         /* Add support for CL37 (passive mode) III */
4192         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4193
4194         /*
4195          * The SNR will improve about 2db by changing BW and FEE main
4196          * tap. Rest commands are executed after link is up
4197          * Change FFE main cursor to 5 in EDC register
4198          */
4199         if (bnx2x_8073_is_snr_needed(bp, phy))
4200                 bnx2x_cl45_write(bp, phy,
4201                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4202                                  0xFB0C);
4203
4204         /* Enable FEC (Forware Error Correction) Request in the AN */
4205         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4206         tmp1 |= (1<<15);
4207         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
4208
4209         bnx2x_ext_phy_set_pause(params, phy, vars);
4210
4211         /* Restart autoneg */
4212         msleep(500);
4213         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4214         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4215                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4216         return 0;
4217 }
4218
4219 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4220                                  struct link_params *params,
4221                                  struct link_vars *vars)
4222 {
4223         struct bnx2x *bp = params->bp;
4224         u8 link_up = 0;
4225         u16 val1, val2;
4226         u16 link_status = 0;
4227         u16 an1000_status = 0;
4228
4229         bnx2x_cl45_read(bp, phy,
4230                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4231
4232         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4233
4234         /* clear the interrupt LASI status register */
4235         bnx2x_cl45_read(bp, phy,
4236                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4237         bnx2x_cl45_read(bp, phy,
4238                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4239         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4240         /* Clear MSG-OUT */
4241         bnx2x_cl45_read(bp, phy,
4242                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4243
4244         /* Check the LASI */
4245         bnx2x_cl45_read(bp, phy,
4246                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4247
4248         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4249
4250         /* Check the link status */
4251         bnx2x_cl45_read(bp, phy,
4252                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4253         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4254
4255         bnx2x_cl45_read(bp, phy,
4256                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4257         bnx2x_cl45_read(bp, phy,
4258                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4259         link_up = ((val1 & 4) == 4);
4260         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4261
4262         if (link_up &&
4263              ((phy->req_line_speed != SPEED_10000))) {
4264                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4265                         return 0;
4266         }
4267         bnx2x_cl45_read(bp, phy,
4268                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4269         bnx2x_cl45_read(bp, phy,
4270                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4271
4272         /* Check the link status on 1.1.2 */
4273         bnx2x_cl45_read(bp, phy,
4274                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4275         bnx2x_cl45_read(bp, phy,
4276                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4277         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4278                    "an_link_status=0x%x\n", val2, val1, an1000_status);
4279
4280         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4281         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4282                 /*
4283                  * The SNR will improve about 2dbby changing the BW and FEE main
4284                  * tap. The 1st write to change FFE main tap is set before
4285                  * restart AN. Change PLL Bandwidth in EDC register
4286                  */
4287                 bnx2x_cl45_write(bp, phy,
4288                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4289                                  0x26BC);
4290
4291                 /* Change CDR Bandwidth in EDC register */
4292                 bnx2x_cl45_write(bp, phy,
4293                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4294                                  0x0333);
4295         }
4296         bnx2x_cl45_read(bp, phy,
4297                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4298                         &link_status);
4299
4300         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4301         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4302                 link_up = 1;
4303                 vars->line_speed = SPEED_10000;
4304                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4305                            params->port);
4306         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4307                 link_up = 1;
4308                 vars->line_speed = SPEED_2500;
4309                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4310                            params->port);
4311         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4312                 link_up = 1;
4313                 vars->line_speed = SPEED_1000;
4314                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4315                            params->port);
4316         } else {
4317                 link_up = 0;
4318                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4319                            params->port);
4320         }
4321
4322         if (link_up) {
4323                 /* Swap polarity if required */
4324                 if (params->lane_config &
4325                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4326                         /* Configure the 8073 to swap P and N of the KR lines */
4327                         bnx2x_cl45_read(bp, phy,
4328                                         MDIO_XS_DEVAD,
4329                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
4330                         /*
4331                          * Set bit 3 to invert Rx in 1G mode and clear this bit
4332                          * when it`s in 10G mode.
4333                          */
4334                         if (vars->line_speed == SPEED_1000) {
4335                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4336                                               "the 8073\n");
4337                                 val1 |= (1<<3);
4338                         } else
4339                                 val1 &= ~(1<<3);
4340
4341                         bnx2x_cl45_write(bp, phy,
4342                                          MDIO_XS_DEVAD,
4343                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
4344                                          val1);
4345                 }
4346                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4347                 bnx2x_8073_resolve_fc(phy, params, vars);
4348                 vars->duplex = DUPLEX_FULL;
4349         }
4350         return link_up;
4351 }
4352
4353 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4354                                   struct link_params *params)
4355 {
4356         struct bnx2x *bp = params->bp;
4357         u8 gpio_port;
4358         if (CHIP_IS_E2(bp))
4359                 gpio_port = BP_PATH(bp);
4360         else
4361                 gpio_port = params->port;
4362         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4363            gpio_port);
4364         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4365                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
4366                        gpio_port);
4367 }
4368
4369 /******************************************************************/
4370 /*                      BCM8705 PHY SECTION                       */
4371 /******************************************************************/
4372 static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
4373                                  struct link_params *params,
4374                                  struct link_vars *vars)
4375 {
4376         struct bnx2x *bp = params->bp;
4377         DP(NETIF_MSG_LINK, "init 8705\n");
4378         /* Restore normal power mode*/
4379         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4380                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4381         /* HW reset */
4382         bnx2x_ext_phy_hw_reset(bp, params->port);
4383         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4384         bnx2x_wait_reset_complete(bp, phy, params);
4385
4386         bnx2x_cl45_write(bp, phy,
4387                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4388         bnx2x_cl45_write(bp, phy,
4389                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4390         bnx2x_cl45_write(bp, phy,
4391                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4392         bnx2x_cl45_write(bp, phy,
4393                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4394         /* BCM8705 doesn't have microcode, hence the 0 */
4395         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4396         return 0;
4397 }
4398
4399 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4400                                  struct link_params *params,
4401                                  struct link_vars *vars)
4402 {
4403         u8 link_up = 0;
4404         u16 val1, rx_sd;
4405         struct bnx2x *bp = params->bp;
4406         DP(NETIF_MSG_LINK, "read status 8705\n");
4407         bnx2x_cl45_read(bp, phy,
4408                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4409         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4410
4411         bnx2x_cl45_read(bp, phy,
4412                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4413         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4414
4415         bnx2x_cl45_read(bp, phy,
4416                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4417
4418         bnx2x_cl45_read(bp, phy,
4419                       MDIO_PMA_DEVAD, 0xc809, &val1);
4420         bnx2x_cl45_read(bp, phy,
4421                       MDIO_PMA_DEVAD, 0xc809, &val1);
4422
4423         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4424         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4425         if (link_up) {
4426                 vars->line_speed = SPEED_10000;
4427                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4428         }
4429         return link_up;
4430 }
4431
4432 /******************************************************************/
4433 /*                      SFP+ module Section                       */
4434 /******************************************************************/
4435 static u8 bnx2x_get_gpio_port(struct link_params *params)
4436 {
4437         u8 gpio_port;
4438         u32 swap_val, swap_override;
4439         struct bnx2x *bp = params->bp;
4440         if (CHIP_IS_E2(bp))
4441                 gpio_port = BP_PATH(bp);
4442         else
4443                 gpio_port = params->port;
4444         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4445         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4446         return gpio_port ^ (swap_val && swap_override);
4447 }
4448 static void bnx2x_sfp_set_transmitter(struct link_params *params,
4449                                       struct bnx2x_phy *phy,
4450                                       u8 tx_en)
4451 {
4452         u16 val;
4453         u8 port = params->port;
4454         struct bnx2x *bp = params->bp;
4455         u32 tx_en_mode;
4456
4457         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
4458         tx_en_mode = REG_RD(bp, params->shmem_base +
4459                             offsetof(struct shmem_region,
4460                                      dev_info.port_hw_config[port].sfp_ctrl)) &
4461                 PORT_HW_CFG_TX_LASER_MASK;
4462         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
4463                            "mode = %x\n", tx_en, port, tx_en_mode);
4464         switch (tx_en_mode) {
4465         case PORT_HW_CFG_TX_LASER_MDIO:
4466
4467                 bnx2x_cl45_read(bp, phy,
4468                                 MDIO_PMA_DEVAD,
4469                                 MDIO_PMA_REG_PHY_IDENTIFIER,
4470                                 &val);
4471
4472                 if (tx_en)
4473                         val &= ~(1<<15);
4474                 else
4475                         val |= (1<<15);
4476
4477                 bnx2x_cl45_write(bp, phy,
4478                                  MDIO_PMA_DEVAD,
4479                                  MDIO_PMA_REG_PHY_IDENTIFIER,
4480                                  val);
4481         break;
4482         case PORT_HW_CFG_TX_LASER_GPIO0:
4483         case PORT_HW_CFG_TX_LASER_GPIO1:
4484         case PORT_HW_CFG_TX_LASER_GPIO2:
4485         case PORT_HW_CFG_TX_LASER_GPIO3:
4486         {
4487                 u16 gpio_pin;
4488                 u8 gpio_port, gpio_mode;
4489                 if (tx_en)
4490                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
4491                 else
4492                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
4493
4494                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
4495                 gpio_port = bnx2x_get_gpio_port(params);
4496                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
4497                 break;
4498         }
4499         default:
4500                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
4501                 break;
4502         }
4503 }
4504
4505 static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4506                                             struct link_params *params,
4507                                             u16 addr, u8 byte_cnt, u8 *o_buf)
4508 {
4509         struct bnx2x *bp = params->bp;
4510         u16 val = 0;
4511         u16 i;
4512         if (byte_cnt > 16) {
4513                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4514                             " is limited to 0xf\n");
4515                 return -EINVAL;
4516         }
4517         /* Set the read command byte count */
4518         bnx2x_cl45_write(bp, phy,
4519                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4520                          (byte_cnt | 0xa000));
4521
4522         /* Set the read command address */
4523         bnx2x_cl45_write(bp, phy,
4524                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4525                          addr);
4526
4527         /* Activate read command */
4528         bnx2x_cl45_write(bp, phy,
4529                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4530                          0x2c0f);
4531
4532         /* Wait up to 500us for command complete status */
4533         for (i = 0; i < 100; i++) {
4534                 bnx2x_cl45_read(bp, phy,
4535                                 MDIO_PMA_DEVAD,
4536                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4537                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4538                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4539                         break;
4540                 udelay(5);
4541         }
4542
4543         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4544                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4545                 DP(NETIF_MSG_LINK,
4546                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4547                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4548                 return -EINVAL;
4549         }
4550
4551         /* Read the buffer */
4552         for (i = 0; i < byte_cnt; i++) {
4553                 bnx2x_cl45_read(bp, phy,
4554                                 MDIO_PMA_DEVAD,
4555                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4556                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4557         }
4558
4559         for (i = 0; i < 100; i++) {
4560                 bnx2x_cl45_read(bp, phy,
4561                                 MDIO_PMA_DEVAD,
4562                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4563                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4564                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4565                         return 0;
4566                 msleep(1);
4567         }
4568         return -EINVAL;
4569 }
4570
4571 static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4572                                             struct link_params *params,
4573                                             u16 addr, u8 byte_cnt, u8 *o_buf)
4574 {
4575         struct bnx2x *bp = params->bp;
4576         u16 val, i;
4577
4578         if (byte_cnt > 16) {
4579                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4580                             " is limited to 0xf\n");
4581                 return -EINVAL;
4582         }
4583
4584         /* Need to read from 1.8000 to clear it */
4585         bnx2x_cl45_read(bp, phy,
4586                         MDIO_PMA_DEVAD,
4587                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4588                         &val);
4589
4590         /* Set the read command byte count */
4591         bnx2x_cl45_write(bp, phy,
4592                          MDIO_PMA_DEVAD,
4593                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4594                          ((byte_cnt < 2) ? 2 : byte_cnt));
4595
4596         /* Set the read command address */
4597         bnx2x_cl45_write(bp, phy,
4598                          MDIO_PMA_DEVAD,
4599                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4600                          addr);
4601         /* Set the destination address */
4602         bnx2x_cl45_write(bp, phy,
4603                          MDIO_PMA_DEVAD,
4604                          0x8004,
4605                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4606
4607         /* Activate read command */
4608         bnx2x_cl45_write(bp, phy,
4609                          MDIO_PMA_DEVAD,
4610                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4611                          0x8002);
4612         /*
4613          * Wait appropriate time for two-wire command to finish before
4614          * polling the status register
4615          */
4616         msleep(1);
4617
4618         /* Wait up to 500us for command complete status */
4619         for (i = 0; i < 100; i++) {
4620                 bnx2x_cl45_read(bp, phy,
4621                                 MDIO_PMA_DEVAD,
4622                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4623                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4624                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4625                         break;
4626                 udelay(5);
4627         }
4628
4629         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4630                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4631                 DP(NETIF_MSG_LINK,
4632                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4633                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4634                 return -EFAULT;
4635         }
4636
4637         /* Read the buffer */
4638         for (i = 0; i < byte_cnt; i++) {
4639                 bnx2x_cl45_read(bp, phy,
4640                                 MDIO_PMA_DEVAD,
4641                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4642                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4643         }
4644
4645         for (i = 0; i < 100; i++) {
4646                 bnx2x_cl45_read(bp, phy,
4647                                 MDIO_PMA_DEVAD,
4648                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4649                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4650                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4651                         return 0;
4652                 msleep(1);
4653         }
4654
4655         return -EINVAL;
4656 }
4657
4658 u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4659                                 struct link_params *params, u16 addr,
4660                                 u8 byte_cnt, u8 *o_buf)
4661 {
4662         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4663                 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4664                                                          byte_cnt, o_buf);
4665         else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4666                 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4667                                                          byte_cnt, o_buf);
4668         return -EINVAL;
4669 }
4670
4671 static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4672                              struct link_params *params,
4673                              u16 *edc_mode)
4674 {
4675         struct bnx2x *bp = params->bp;
4676         u8 val, check_limiting_mode = 0;
4677         *edc_mode = EDC_MODE_LIMITING;
4678
4679         /* First check for copper cable */
4680         if (bnx2x_read_sfp_module_eeprom(phy,
4681                                          params,
4682                                          SFP_EEPROM_CON_TYPE_ADDR,
4683                                          1,
4684                                          &val) != 0) {
4685                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4686                 return -EINVAL;
4687         }
4688
4689         switch (val) {
4690         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4691         {
4692                 u8 copper_module_type;
4693
4694                 /*
4695                  * Check if its active cable (includes SFP+ module)
4696                  * of passive cable
4697                  */
4698                 if (bnx2x_read_sfp_module_eeprom(phy,
4699                                                params,
4700                                                SFP_EEPROM_FC_TX_TECH_ADDR,
4701                                                1,
4702                                                &copper_module_type) !=
4703                     0) {
4704                         DP(NETIF_MSG_LINK,
4705                                 "Failed to read copper-cable-type"
4706                                 " from SFP+ EEPROM\n");
4707                         return -EINVAL;
4708                 }
4709
4710                 if (copper_module_type &
4711                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4712                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4713                         check_limiting_mode = 1;
4714                 } else if (copper_module_type &
4715                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4716                                 DP(NETIF_MSG_LINK, "Passive Copper"
4717                                             " cable detected\n");
4718                                 *edc_mode =
4719                                       EDC_MODE_PASSIVE_DAC;
4720                 } else {
4721                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4722                                      "type 0x%x !!!\n", copper_module_type);
4723                         return -EINVAL;
4724                 }
4725                 break;
4726         }
4727         case SFP_EEPROM_CON_TYPE_VAL_LC:
4728                 DP(NETIF_MSG_LINK, "Optic module detected\n");
4729                 check_limiting_mode = 1;
4730                 break;
4731         default:
4732                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4733                          val);
4734                 return -EINVAL;
4735         }
4736
4737         if (check_limiting_mode) {
4738                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4739                 if (bnx2x_read_sfp_module_eeprom(phy,
4740                                                  params,
4741                                                  SFP_EEPROM_OPTIONS_ADDR,
4742                                                  SFP_EEPROM_OPTIONS_SIZE,
4743                                                  options) != 0) {
4744                         DP(NETIF_MSG_LINK, "Failed to read Option"
4745                                 " field from module EEPROM\n");
4746                         return -EINVAL;
4747                 }
4748                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4749                         *edc_mode = EDC_MODE_LINEAR;
4750                 else
4751                         *edc_mode = EDC_MODE_LIMITING;
4752         }
4753         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
4754         return 0;
4755 }
4756 /*
4757  * This function read the relevant field from the module (SFP+), and verify it
4758  * is compliant with this board
4759  */
4760 static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4761                                   struct link_params *params)
4762 {
4763         struct bnx2x *bp = params->bp;
4764         u32 val, cmd;
4765         u32 fw_resp, fw_cmd_param;
4766         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4767         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
4768         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
4769         val = REG_RD(bp, params->shmem_base +
4770                          offsetof(struct shmem_region, dev_info.
4771                                   port_feature_config[params->port].config));
4772         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4773             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4774                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4775                 return 0;
4776         }
4777
4778         if (params->feature_config_flags &
4779             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4780                 /* Use specific phy request */
4781                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4782         } else if (params->feature_config_flags &
4783                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4784                 /* Use first phy request only in case of non-dual media*/
4785                 if (DUAL_MEDIA(params)) {
4786                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4787                            "verification\n");
4788                         return -EINVAL;
4789                 }
4790                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4791         } else {
4792                 /* No support in OPT MDL detection */
4793                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4794                           "verification\n");
4795                 return -EINVAL;
4796         }
4797
4798         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4799         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
4800         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4801                 DP(NETIF_MSG_LINK, "Approved module\n");
4802                 return 0;
4803         }
4804
4805         /* format the warning message */
4806         if (bnx2x_read_sfp_module_eeprom(phy,
4807                                          params,
4808                                          SFP_EEPROM_VENDOR_NAME_ADDR,
4809                                          SFP_EEPROM_VENDOR_NAME_SIZE,
4810                                          (u8 *)vendor_name))
4811                 vendor_name[0] = '\0';
4812         else
4813                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4814         if (bnx2x_read_sfp_module_eeprom(phy,
4815                                          params,
4816                                          SFP_EEPROM_PART_NO_ADDR,
4817                                          SFP_EEPROM_PART_NO_SIZE,
4818                                          (u8 *)vendor_pn))
4819                 vendor_pn[0] = '\0';
4820         else
4821                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4822
4823         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
4824                               " Port %d from %s part number %s\n",
4825                          params->port, vendor_name, vendor_pn);
4826         phy->flags |= FLAGS_SFP_NOT_APPROVED;
4827         return -EINVAL;
4828 }
4829
4830 static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4831                                                 struct link_params *params)
4832
4833 {
4834         u8 val;
4835         struct bnx2x *bp = params->bp;
4836         u16 timeout;
4837         /*
4838          * Initialization time after hot-plug may take up to 300ms for
4839          * some phys type ( e.g. JDSU )
4840          */
4841
4842         for (timeout = 0; timeout < 60; timeout++) {
4843                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4844                     == 0) {
4845                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
4846                                      "took %d ms\n", timeout * 5);
4847                         return 0;
4848                 }
4849                 msleep(5);
4850         }
4851         return -EINVAL;
4852 }
4853
4854 static void bnx2x_8727_power_module(struct bnx2x *bp,
4855                                     struct bnx2x_phy *phy,
4856                                     u8 is_power_up) {
4857         /* Make sure GPIOs are not using for LED mode */
4858         u16 val;
4859         /*
4860          * In the GPIO register, bit 4 is use to determine if the GPIOs are
4861          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4862          * output
4863          * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4864          * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4865          * where the 1st bit is the over-current(only input), and 2nd bit is
4866          * for power( only output )
4867          *
4868          * In case of NOC feature is disabled and power is up, set GPIO control
4869          *  as input to enable listening of over-current indication
4870          */
4871         if (phy->flags & FLAGS_NOC)
4872                 return;
4873         if (!(phy->flags &
4874               FLAGS_NOC) && is_power_up)
4875                 val = (1<<4);
4876         else
4877                 /*
4878                  * Set GPIO control to OUTPUT, and set the power bit
4879                  * to according to the is_power_up
4880                  */
4881                 val = ((!(is_power_up)) << 1);
4882
4883         bnx2x_cl45_write(bp, phy,
4884                          MDIO_PMA_DEVAD,
4885                          MDIO_PMA_REG_8727_GPIO_CTRL,
4886                          val);
4887 }
4888
4889 static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4890                                        struct bnx2x_phy *phy,
4891                                        u16 edc_mode)
4892 {
4893         u16 cur_limiting_mode;
4894
4895         bnx2x_cl45_read(bp, phy,
4896                         MDIO_PMA_DEVAD,
4897                         MDIO_PMA_REG_ROM_VER2,
4898                         &cur_limiting_mode);
4899         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4900                  cur_limiting_mode);
4901
4902         if (edc_mode == EDC_MODE_LIMITING) {
4903                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
4904                 bnx2x_cl45_write(bp, phy,
4905                                  MDIO_PMA_DEVAD,
4906                                  MDIO_PMA_REG_ROM_VER2,
4907                                  EDC_MODE_LIMITING);
4908         } else { /* LRM mode ( default )*/
4909
4910                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4911
4912                 /*
4913                  * Changing to LRM mode takes quite few seconds. So do it only
4914                  * if current mode is limiting (default is LRM)
4915                  */
4916                 if (cur_limiting_mode != EDC_MODE_LIMITING)
4917                         return 0;
4918
4919                 bnx2x_cl45_write(bp, phy,
4920                                  MDIO_PMA_DEVAD,
4921                                  MDIO_PMA_REG_LRM_MODE,
4922                                  0);
4923                 bnx2x_cl45_write(bp, phy,
4924                                  MDIO_PMA_DEVAD,
4925                                  MDIO_PMA_REG_ROM_VER2,
4926                                  0x128);
4927                 bnx2x_cl45_write(bp, phy,
4928                                  MDIO_PMA_DEVAD,
4929                                  MDIO_PMA_REG_MISC_CTRL0,
4930                                  0x4008);
4931                 bnx2x_cl45_write(bp, phy,
4932                                  MDIO_PMA_DEVAD,
4933                                  MDIO_PMA_REG_LRM_MODE,
4934                                  0xaaaa);
4935         }
4936         return 0;
4937 }
4938
4939 static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4940                                        struct bnx2x_phy *phy,
4941                                        u16 edc_mode)
4942 {
4943         u16 phy_identifier;
4944         u16 rom_ver2_val;
4945         bnx2x_cl45_read(bp, phy,
4946                         MDIO_PMA_DEVAD,
4947                         MDIO_PMA_REG_PHY_IDENTIFIER,
4948                         &phy_identifier);
4949
4950         bnx2x_cl45_write(bp, phy,
4951                          MDIO_PMA_DEVAD,
4952                          MDIO_PMA_REG_PHY_IDENTIFIER,
4953                          (phy_identifier & ~(1<<9)));
4954
4955         bnx2x_cl45_read(bp, phy,
4956                         MDIO_PMA_DEVAD,
4957                         MDIO_PMA_REG_ROM_VER2,
4958                         &rom_ver2_val);
4959         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4960         bnx2x_cl45_write(bp, phy,
4961                          MDIO_PMA_DEVAD,
4962                          MDIO_PMA_REG_ROM_VER2,
4963                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4964
4965         bnx2x_cl45_write(bp, phy,
4966                          MDIO_PMA_DEVAD,
4967                          MDIO_PMA_REG_PHY_IDENTIFIER,
4968                          (phy_identifier | (1<<9)));
4969
4970         return 0;
4971 }
4972
4973 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
4974                                      struct link_params *params,
4975                                      u32 action)
4976 {
4977         struct bnx2x *bp = params->bp;
4978
4979         switch (action) {
4980         case DISABLE_TX:
4981                 bnx2x_sfp_set_transmitter(params, phy, 0);
4982                 break;
4983         case ENABLE_TX:
4984                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
4985                         bnx2x_sfp_set_transmitter(params, phy, 1);
4986                 break;
4987         default:
4988                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
4989                    action);
4990                 return;
4991         }
4992 }
4993
4994 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
4995                                            u8 gpio_mode)
4996 {
4997         struct bnx2x *bp = params->bp;
4998
4999         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
5000                             offsetof(struct shmem_region,
5001                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
5002                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
5003         switch (fault_led_gpio) {
5004         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
5005                 return;
5006         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
5007         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
5008         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
5009         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
5010         {
5011                 u8 gpio_port = bnx2x_get_gpio_port(params);
5012                 u16 gpio_pin = fault_led_gpio -
5013                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
5014                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
5015                                    "pin %x port %x mode %x\n",
5016                                gpio_pin, gpio_port, gpio_mode);
5017                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
5018         }
5019         break;
5020         default:
5021                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
5022                                fault_led_gpio);
5023         }
5024 }
5025
5026 static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5027                                      struct link_params *params)
5028 {
5029         struct bnx2x *bp = params->bp;
5030         u16 edc_mode;
5031         u8 rc = 0;
5032
5033         u32 val = REG_RD(bp, params->shmem_base +
5034                              offsetof(struct shmem_region, dev_info.
5035                                      port_feature_config[params->port].config));
5036
5037         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5038                  params->port);
5039
5040         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5041                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5042                 return -EINVAL;
5043         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
5044                 /* check SFP+ module compatibility */
5045                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5046                 rc = -EINVAL;
5047                 /* Turn on fault module-detected led */
5048                 bnx2x_set_sfp_module_fault_led(params,
5049                                                MISC_REGISTERS_GPIO_HIGH);
5050
5051                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
5052                     ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5053                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
5054                         /* Shutdown SFP+ module */
5055                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
5056                         bnx2x_8727_power_module(bp, phy, 0);
5057                         return rc;
5058                 }
5059         } else {
5060                 /* Turn off fault module-detected led */
5061                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
5062         }
5063
5064         /* power up the SFP module */
5065         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
5066                 bnx2x_8727_power_module(bp, phy, 1);
5067
5068         /*
5069          * Check and set limiting mode / LRM mode on 8726. On 8727 it
5070          * is done automatically
5071          */
5072         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
5073                 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
5074         else
5075                 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
5076         /*
5077          * Enable transmit for this module if the module is approved, or
5078          * if unapproved modules should also enable the Tx laser
5079          */
5080         if (rc == 0 ||
5081             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5082             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5083                 bnx2x_sfp_set_transmitter(params, phy, 1);
5084         else
5085                 bnx2x_sfp_set_transmitter(params, phy, 0);
5086
5087         return rc;
5088 }
5089
5090 void bnx2x_handle_module_detect_int(struct link_params *params)
5091 {
5092         struct bnx2x *bp = params->bp;
5093         struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5094         u32 gpio_val;
5095         u8 port = params->port;
5096
5097         /* Set valid module led off */
5098         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
5099
5100         /* Get current gpio val reflecting module plugged in / out*/
5101         gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
5102
5103         /* Call the handling function in case module is detected */
5104         if (gpio_val == 0) {
5105
5106                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5107                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5108                                    port);
5109
5110                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5111                         bnx2x_sfp_module_detection(phy, params);
5112                 else
5113                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5114         } else {
5115                 u32 val = REG_RD(bp, params->shmem_base +
5116                                  offsetof(struct shmem_region, dev_info.
5117                                           port_feature_config[params->port].
5118                                           config));
5119
5120                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5121                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5122                                    port);
5123                 /*
5124                  * Module was plugged out.
5125                  * Disable transmit for this module
5126                  */
5127                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5128                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5129                         bnx2x_sfp_set_transmitter(params, phy, 0);
5130         }
5131 }
5132
5133 /******************************************************************/
5134 /*              common BCM8706/BCM8726 PHY SECTION                */
5135 /******************************************************************/
5136 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5137                                       struct link_params *params,
5138                                       struct link_vars *vars)
5139 {
5140         u8 link_up = 0;
5141         u16 val1, val2, rx_sd, pcs_status;
5142         struct bnx2x *bp = params->bp;
5143         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5144         /* Clear RX Alarm*/
5145         bnx2x_cl45_read(bp, phy,
5146                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5147         /* clear LASI indication*/
5148         bnx2x_cl45_read(bp, phy,
5149                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5150         bnx2x_cl45_read(bp, phy,
5151                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5152         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
5153
5154         bnx2x_cl45_read(bp, phy,
5155                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5156         bnx2x_cl45_read(bp, phy,
5157                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5158         bnx2x_cl45_read(bp, phy,
5159                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5160         bnx2x_cl45_read(bp, phy,
5161                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5162
5163         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5164                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
5165         /*
5166          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
5167          * are set, or if the autoneg bit 1 is set
5168          */
5169         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5170         if (link_up) {
5171                 if (val2 & (1<<1))
5172                         vars->line_speed = SPEED_1000;
5173                 else
5174                         vars->line_speed = SPEED_10000;
5175                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5176                 vars->duplex = DUPLEX_FULL;
5177         }
5178         return link_up;
5179 }
5180
5181 /******************************************************************/
5182 /*                      BCM8706 PHY SECTION                       */
5183 /******************************************************************/
5184 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5185                                  struct link_params *params,
5186                                  struct link_vars *vars)
5187 {
5188         u32 tx_en_mode;
5189         u16 cnt, val, tmp1;
5190         struct bnx2x *bp = params->bp;
5191         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5192                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5193         /* HW reset */
5194         bnx2x_ext_phy_hw_reset(bp, params->port);
5195         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5196         bnx2x_wait_reset_complete(bp, phy, params);
5197
5198         /* Wait until fw is loaded */
5199         for (cnt = 0; cnt < 100; cnt++) {
5200                 bnx2x_cl45_read(bp, phy,
5201                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5202                 if (val)
5203                         break;
5204                 msleep(10);
5205         }
5206         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5207         if ((params->feature_config_flags &
5208              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5209                 u8 i;
5210                 u16 reg;
5211                 for (i = 0; i < 4; i++) {
5212                         reg = MDIO_XS_8706_REG_BANK_RX0 +
5213                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
5214                                    MDIO_XS_8706_REG_BANK_RX0);
5215                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5216                         /* Clear first 3 bits of the control */
5217                         val &= ~0x7;
5218                         /* Set control bits according to configuration */
5219                         val |= (phy->rx_preemphasis[i] & 0x7);
5220                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5221                                    " reg 0x%x <-- val 0x%x\n", reg, val);
5222                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5223                 }
5224         }
5225         /* Force speed */
5226         if (phy->req_line_speed == SPEED_10000) {
5227                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
5228
5229                 bnx2x_cl45_write(bp, phy,
5230                                  MDIO_PMA_DEVAD,
5231                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5232                 bnx2x_cl45_write(bp, phy,
5233                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5234         } else {
5235                 /* Force 1Gbps using autoneg with 1G advertisment */
5236
5237                 /* Allow CL37 through CL73 */
5238                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5239                 bnx2x_cl45_write(bp, phy,
5240                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5241
5242                 /* Enable Full-Duplex advertisment on CL37 */
5243                 bnx2x_cl45_write(bp, phy,
5244                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5245                 /* Enable CL37 AN */
5246                 bnx2x_cl45_write(bp, phy,
5247                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5248                 /* 1G support */
5249                 bnx2x_cl45_write(bp, phy,
5250                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
5251
5252                 /* Enable clause 73 AN */
5253                 bnx2x_cl45_write(bp, phy,
5254                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5255                 bnx2x_cl45_write(bp, phy,
5256                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5257                                  0x0400);
5258                 bnx2x_cl45_write(bp, phy,
5259                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5260                                  0x0004);
5261         }
5262         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5263
5264         /*
5265          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5266          * power mode, if TX Laser is disabled
5267          */
5268
5269         tx_en_mode = REG_RD(bp, params->shmem_base +
5270                             offsetof(struct shmem_region,
5271                                 dev_info.port_hw_config[params->port].sfp_ctrl))
5272                         & PORT_HW_CFG_TX_LASER_MASK;
5273
5274         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5275                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5276                 bnx2x_cl45_read(bp, phy,
5277                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
5278                 tmp1 |= 0x1;
5279                 bnx2x_cl45_write(bp, phy,
5280                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
5281         }
5282
5283         return 0;
5284 }
5285
5286 static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
5287                                  struct link_params *params,
5288                                  struct link_vars *vars)
5289 {
5290         return bnx2x_8706_8726_read_status(phy, params, vars);
5291 }
5292
5293 /******************************************************************/
5294 /*                      BCM8726 PHY SECTION                       */
5295 /******************************************************************/
5296 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5297                                        struct link_params *params)
5298 {
5299         struct bnx2x *bp = params->bp;
5300         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5301         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5302 }
5303
5304 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5305                                          struct link_params *params)
5306 {
5307         struct bnx2x *bp = params->bp;
5308         /* Need to wait 100ms after reset */
5309         msleep(100);
5310
5311         /* Micro controller re-boot */
5312         bnx2x_cl45_write(bp, phy,
5313                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
5314
5315         /* Set soft reset */
5316         bnx2x_cl45_write(bp, phy,
5317                          MDIO_PMA_DEVAD,
5318                          MDIO_PMA_REG_GEN_CTRL,
5319                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
5320
5321         bnx2x_cl45_write(bp, phy,
5322                          MDIO_PMA_DEVAD,
5323                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
5324
5325         bnx2x_cl45_write(bp, phy,
5326                          MDIO_PMA_DEVAD,
5327                          MDIO_PMA_REG_GEN_CTRL,
5328                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5329
5330         /* wait for 150ms for microcode load */
5331         msleep(150);
5332
5333         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5334         bnx2x_cl45_write(bp, phy,
5335                          MDIO_PMA_DEVAD,
5336                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5337
5338         msleep(200);
5339         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5340 }
5341
5342 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
5343                                  struct link_params *params,
5344                                  struct link_vars *vars)
5345 {
5346         struct bnx2x *bp = params->bp;
5347         u16 val1;
5348         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
5349         if (link_up) {
5350                 bnx2x_cl45_read(bp, phy,
5351                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5352                                 &val1);
5353                 if (val1 & (1<<15)) {
5354                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
5355                         link_up = 0;
5356                         vars->line_speed = 0;
5357                 }
5358         }
5359         return link_up;
5360 }
5361
5362
5363 static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
5364                                  struct link_params *params,
5365                                  struct link_vars *vars)
5366 {
5367         struct bnx2x *bp = params->bp;
5368         u32 val;
5369         u32 swap_val, swap_override, aeu_gpio_mask, offset;
5370         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
5371
5372         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5373         bnx2x_wait_reset_complete(bp, phy, params);
5374
5375         bnx2x_8726_external_rom_boot(phy, params);
5376
5377         /*