bnx2x: replace FW to 6.2.5
[linux-2.6.git] / drivers / net / bnx2x / bnx2x_hsi.h
1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2010 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9 #ifndef BNX2X_HSI_H
10 #define BNX2X_HSI_H
11
12 #include "bnx2x_fw_defs.h"
13
14 struct license_key {
15         u32 reserved[6];
16
17 #if defined(__BIG_ENDIAN)
18         u16 max_iscsi_init_conn;
19         u16 max_iscsi_trgt_conn;
20 #elif defined(__LITTLE_ENDIAN)
21         u16 max_iscsi_trgt_conn;
22         u16 max_iscsi_init_conn;
23 #endif
24
25         u32 reserved_a[6];
26 };
27
28
29 #define PORT_0                          0
30 #define PORT_1                          1
31 #define PORT_MAX                        2
32
33 /****************************************************************************
34  * Shared HW configuration                                                  *
35  ****************************************************************************/
36 struct shared_hw_cfg {                                   /* NVRAM Offset */
37         /* Up to 16 bytes of NULL-terminated string */
38         u8  part_num[16];                                       /* 0x104 */
39
40         u32 config;                                             /* 0x114 */
41 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
42 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT            0
43 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V             0x00000000
44 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V             0x00000001
45 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
46
47 #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
48
49 #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
50
51 #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
52 #define SHARED_HW_CFG_MFW_SELECT_SHIFT              8
53         /* Whatever MFW found in NVM
54            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
55 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT            0x00000000
56 #define SHARED_HW_CFG_MFW_SELECT_NC_SI              0x00000100
57 #define SHARED_HW_CFG_MFW_SELECT_UMP                0x00000200
58 #define SHARED_HW_CFG_MFW_SELECT_IPMI               0x00000300
59         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
60           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
61 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
62         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
63           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
64 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
65         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
66           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
67 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
68
69 #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
70 #define SHARED_HW_CFG_LED_MODE_SHIFT                16
71 #define SHARED_HW_CFG_LED_MAC1                      0x00000000
72 #define SHARED_HW_CFG_LED_PHY1                      0x00010000
73 #define SHARED_HW_CFG_LED_PHY2                      0x00020000
74 #define SHARED_HW_CFG_LED_PHY3                      0x00030000
75 #define SHARED_HW_CFG_LED_MAC2                      0x00040000
76 #define SHARED_HW_CFG_LED_PHY4                      0x00050000
77 #define SHARED_HW_CFG_LED_PHY5                      0x00060000
78 #define SHARED_HW_CFG_LED_PHY6                      0x00070000
79 #define SHARED_HW_CFG_LED_MAC3                      0x00080000
80 #define SHARED_HW_CFG_LED_PHY7                      0x00090000
81 #define SHARED_HW_CFG_LED_PHY9                      0x000a0000
82 #define SHARED_HW_CFG_LED_PHY11                     0x000b0000
83 #define SHARED_HW_CFG_LED_MAC4                      0x000c0000
84 #define SHARED_HW_CFG_LED_PHY8                      0x000d0000
85 #define SHARED_HW_CFG_LED_EXTPHY1                   0x000e0000
86
87
88 #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
89 #define SHARED_HW_CFG_AN_ENABLE_SHIFT               24
90 #define SHARED_HW_CFG_AN_ENABLE_CL37                0x01000000
91 #define SHARED_HW_CFG_AN_ENABLE_CL73                0x02000000
92 #define SHARED_HW_CFG_AN_ENABLE_BAM                 0x04000000
93 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
94 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
95 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY          0x20000000
96
97         u32 config2;                                            /* 0x118 */
98         /* one time auto detect grace period (in sec) */
99 #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
100 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT            0
101
102 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
103
104         /* The default value for the core clock is 250MHz and it is
105            achieved by setting the clock change to 4 */
106 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
107 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT            9
108
109 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ           0x00000000
110 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ           0x00001000
111
112 #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
113
114         /*  The fan failure mechanism is usually related to the PHY type
115           since the power consumption of the board is determined by the PHY.
116           Currently, fan is required for most designs with SFX7101, BCM8727
117           and BCM8481. If a fan is not required for a board which uses one
118           of those PHYs, this field should be set to "Disabled". If a fan is
119           required for a different PHY type, this option should be set to
120           "Enabled".
121           The fan failure indication is expected on
122           SPIO5 */
123 #define SHARED_HW_CFG_FAN_FAILURE_MASK                        0x00180000
124 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT                       19
125 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE                    0x00000000
126 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED                    0x00080000
127 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED                     0x00100000
128
129         /* Set the MDC/MDIO access for the first external phy */
130 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
131 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT        26
132 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE     0x00000000
133 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0        0x04000000
134 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1        0x08000000
135 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH         0x0c000000
136 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED      0x10000000
137
138         /* Set the MDC/MDIO access for the second external phy */
139 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
140 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT        29
141 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE     0x00000000
142 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0        0x20000000
143 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1        0x40000000
144 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH         0x60000000
145 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED      0x80000000
146         u32 power_dissipated;                                   /* 0x11c */
147 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
148 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT           24
149
150 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
151 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT        16
152 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE      0x00000000
153 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT         0x00010000
154 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT        0x00020000
155 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT       0x00030000
156
157         u32 ump_nc_si_config;                                   /* 0x120 */
158 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
159 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT      0
160 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC        0x00000000
161 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY        0x00000001
162 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII        0x00000000
163 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII       0x00000002
164
165 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
166 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT      8
167
168 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
169 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
170 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
171 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
172
173         u32 board;                                              /* 0x124 */
174 #define SHARED_HW_CFG_BOARD_REV_MASK                0x00FF0000
175 #define SHARED_HW_CFG_BOARD_REV_SHIFT               16
176
177 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0F000000
178 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT         24
179
180 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xF0000000
181 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT         28
182
183         u32 reserved;                                           /* 0x128 */
184
185 };
186
187
188 /****************************************************************************
189  * Port HW configuration                                                    *
190  ****************************************************************************/
191 struct port_hw_cfg {                        /* port 0: 0x12c  port 1: 0x2bc */
192
193         u32 pci_id;
194 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
195 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
196
197         u32 pci_sub_id;
198 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
199 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
200
201         u32 power_dissipated;
202 #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
203 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT              24
204 #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
205 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT              16
206 #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
207 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT              8
208 #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
209 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT              0
210
211         u32 power_consumed;
212 #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
213 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT             24
214 #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
215 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT             16
216 #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
217 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT             8
218 #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
219 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT             0
220
221         u32 mac_upper;
222 #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
223 #define PORT_HW_CFG_UPPERMAC_SHIFT                  0
224         u32 mac_lower;
225
226         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
227         u32 iscsi_mac_lower;
228
229         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
230         u32 rdma_mac_lower;
231
232         u32 serdes_config;
233 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK           0x0000FFFF
234 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT          0
235
236 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK              0xFFFF0000
237 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT             16
238
239
240         u32 Reserved0[16];                                  /* 0x158 */
241
242         /*  for external PHY, or forced mode or during AN */
243         u16 xgxs_config_rx[4];                              /* 0x198 */
244
245         u16 xgxs_config_tx[4];                              /* 0x1A0 */
246
247         u32 Reserved1[56];                                  /* 0x1A8 */
248         u32 default_cfg;                                    /* 0x288 */
249         /*  Enable BAM on KR */
250 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK                     0x00100000
251 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                    20
252 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                 0x00000000
253 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                  0x00100000
254
255         u32 speed_capability_mask2;                         /* 0x28C */
256 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK                 0x0000FFFF
257 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT                0
258 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL             0x00000001
259 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__                    0x00000002
260 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___                   0x00000004
261 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL            0x00000008
262 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G                   0x00000010
263 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G             0x00000020
264 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G                  0x00000040
265 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G                  0x00000080
266 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G            0x00000100
267 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G                  0x00000200
268 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G                  0x00000400
269 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G                  0x00000800
270
271 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK                 0xFFFF0000
272 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT                16
273 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL             0x00010000
274 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__                    0x00020000
275 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___                   0x00040000
276 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL            0x00080000
277 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G                   0x00100000
278 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G             0x00200000
279 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G                  0x00400000
280 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G                  0x00800000
281 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G            0x01000000
282 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G                  0x02000000
283 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G                  0x04000000
284 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G                  0x08000000
285
286         /* In the case where two media types (e.g. copper and fiber) are
287           present and electrically active at the same time, PHY Selection
288           will determine which of the two PHYs will be designated as the
289           Active PHY and used for a connection to the network.  */
290         u32 multi_phy_config;                           /* 0x290 */
291 #define PORT_HW_CFG_PHY_SELECTION_MASK               0x00000007
292 #define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
293 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
294 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
295 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
296 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
297 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
298
299         /* When enabled, all second phy nvram parameters will be swapped
300           with the first phy parameters */
301 #define PORT_HW_CFG_PHY_SWAPPED_MASK                 0x00000008
302 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
303 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
304 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
305
306
307         /* Address of the second external phy */
308         u32 external_phy_config2;                               /* 0x294 */
309 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
310 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT        0
311
312         /* The second XGXS external PHY type */
313 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
314 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT        8
315 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT       0x00000000
316 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071      0x00000100
317 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072      0x00000200
318 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073      0x00000300
319 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705      0x00000400
320 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706      0x00000500
321 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726      0x00000600
322 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481      0x00000700
323 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101      0x00000800
324 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727      0x00000900
325 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC  0x00000a00
326 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823     0x00000b00
327 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640     0x00000c00
328 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833     0x00000d00
329 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE      0x0000fd00
330 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN     0x0000ff00
331
332         /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
333           8706, 8726 and 8727) not all 4 values are needed. */
334         u16 xgxs_config2_rx[4];                         /* 0x296 */
335         u16 xgxs_config2_tx[4];                         /* 0x2A0 */
336
337         u32 lane_config;
338 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
339 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT             0
340
341 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
342 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT          0
343 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
344 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT          8
345 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
346 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT      14
347         /* AN and forced */
348 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123          0x00001b1b
349         /* forced only */
350 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210          0x00001be4
351         /* forced only */
352 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120          0x0000d8d8
353         /* forced only */
354 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210          0x0000e4e4
355
356         u32 external_phy_config;
357 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
358 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT       24
359 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT      0x00000000
360 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
361 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
362
363 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
364 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT       16
365
366 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
367 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT         8
368 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT        0x00000000
369 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071       0x00000100
370 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072       0x00000200
371 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073       0x00000300
372 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705       0x00000400
373 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706       0x00000500
374 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726       0x00000600
375 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481       0x00000700
376 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101       0x00000800
377 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727       0x00000900
378 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC   0x00000a00
379 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823      0x00000b00
380 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE       0x0000fd00
381 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN      0x0000ff00
382
383 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
384 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT         0
385
386         u32 speed_capability_mask;
387 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
388 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT       16
389 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
390 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
391 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
392 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
393 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G          0x00100000
394 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G        0x00200000
395 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G         0x00400000
396 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G         0x00800000
397 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G       0x01000000
398 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G         0x02000000
399 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G         0x04000000
400 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G         0x08000000
401 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
402
403 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
404 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT       0
405 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
406 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
407 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
408 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
409 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G          0x00000010
410 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G        0x00000020
411 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G         0x00000040
412 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G         0x00000080
413 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G       0x00000100
414 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G         0x00000200
415 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G         0x00000400
416 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G         0x00000800
417 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
418
419         u32 reserved[2];
420
421 };
422
423
424 /****************************************************************************
425  * Shared Feature configuration                                             *
426  ****************************************************************************/
427 struct shared_feat_cfg {                                 /* NVRAM Offset */
428
429         u32 config;                                             /* 0x450 */
430 #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
431
432         /*  Use the values from options 47 and 48 instead of the HW default
433           values */
434 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED     0x00000000
435 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED      0x00000002
436
437 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK                    0x00000700
438 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT                   8
439 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED              0x00000000
440 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF               0x00000100
441 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4                   0x00000200
442 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT           0x00000300
443
444 };
445
446
447 /****************************************************************************
448  * Port Feature configuration                                               *
449  ****************************************************************************/
450 struct port_feat_cfg {                      /* port 0: 0x454  port 1: 0x4c8 */
451
452         u32 config;
453 #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
454 #define PORT_FEATURE_BAR1_SIZE_SHIFT                0
455 #define PORT_FEATURE_BAR1_SIZE_DISABLED             0x00000000
456 #define PORT_FEATURE_BAR1_SIZE_64K                  0x00000001
457 #define PORT_FEATURE_BAR1_SIZE_128K                 0x00000002
458 #define PORT_FEATURE_BAR1_SIZE_256K                 0x00000003
459 #define PORT_FEATURE_BAR1_SIZE_512K                 0x00000004
460 #define PORT_FEATURE_BAR1_SIZE_1M                   0x00000005
461 #define PORT_FEATURE_BAR1_SIZE_2M                   0x00000006
462 #define PORT_FEATURE_BAR1_SIZE_4M                   0x00000007
463 #define PORT_FEATURE_BAR1_SIZE_8M                   0x00000008
464 #define PORT_FEATURE_BAR1_SIZE_16M                  0x00000009
465 #define PORT_FEATURE_BAR1_SIZE_32M                  0x0000000a
466 #define PORT_FEATURE_BAR1_SIZE_64M                  0x0000000b
467 #define PORT_FEATURE_BAR1_SIZE_128M                 0x0000000c
468 #define PORT_FEATURE_BAR1_SIZE_256M                 0x0000000d
469 #define PORT_FEATURE_BAR1_SIZE_512M                 0x0000000e
470 #define PORT_FEATURE_BAR1_SIZE_1G                   0x0000000f
471 #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
472 #define PORT_FEATURE_BAR2_SIZE_SHIFT                4
473 #define PORT_FEATURE_BAR2_SIZE_DISABLED             0x00000000
474 #define PORT_FEATURE_BAR2_SIZE_64K                  0x00000010
475 #define PORT_FEATURE_BAR2_SIZE_128K                 0x00000020
476 #define PORT_FEATURE_BAR2_SIZE_256K                 0x00000030
477 #define PORT_FEATURE_BAR2_SIZE_512K                 0x00000040
478 #define PORT_FEATURE_BAR2_SIZE_1M                   0x00000050
479 #define PORT_FEATURE_BAR2_SIZE_2M                   0x00000060
480 #define PORT_FEATURE_BAR2_SIZE_4M                   0x00000070
481 #define PORT_FEATURE_BAR2_SIZE_8M                   0x00000080
482 #define PORT_FEATURE_BAR2_SIZE_16M                  0x00000090
483 #define PORT_FEATURE_BAR2_SIZE_32M                  0x000000a0
484 #define PORT_FEATURE_BAR2_SIZE_64M                  0x000000b0
485 #define PORT_FEATURE_BAR2_SIZE_128M                 0x000000c0
486 #define PORT_FEATURE_BAR2_SIZE_256M                 0x000000d0
487 #define PORT_FEATURE_BAR2_SIZE_512M                 0x000000e0
488 #define PORT_FEATURE_BAR2_SIZE_1G                   0x000000f0
489 #define PORT_FEATURE_EN_SIZE_MASK                   0x07000000
490 #define PORT_FEATURE_EN_SIZE_SHIFT                  24
491 #define PORT_FEATURE_WOL_ENABLED                    0x01000000
492 #define PORT_FEATURE_MBA_ENABLED                    0x02000000
493 #define PORT_FEATURE_MFW_ENABLED                    0x04000000
494
495         /* Reserved bits: 28-29 */
496         /*  Check the optic vendor via i2c against a list of approved modules
497           in a separate nvram image */
498 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK                   0xE0000000
499 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT                  29
500 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT         0x00000000
501 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER       0x20000000
502 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG            0x40000000
503 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN             0x60000000
504
505
506         u32 wol_config;
507         /* Default is used when driver sets to "auto" mode */
508 #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
509 #define PORT_FEATURE_WOL_DEFAULT_SHIFT              0
510 #define PORT_FEATURE_WOL_DEFAULT_DISABLE            0x00000000
511 #define PORT_FEATURE_WOL_DEFAULT_MAGIC              0x00000001
512 #define PORT_FEATURE_WOL_DEFAULT_ACPI               0x00000002
513 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
514 #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
515 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
516 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
517
518         u32 mba_config;
519 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000003
520 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT      0
521 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0x00000000
522 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        0x00000001
523 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      0x00000002
524 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
525 #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
526 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
527 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
528 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S              0x00000000
529 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B              0x00000800
530 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
531 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT         12
532 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0x00000000
533 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K            0x00001000
534 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K            0x00002000
535 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K            0x00003000
536 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K           0x00004000
537 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K           0x00005000
538 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K           0x00006000
539 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K          0x00007000
540 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K          0x00008000
541 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K          0x00009000
542 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M            0x0000a000
543 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M            0x0000b000
544 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M            0x0000c000
545 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M            0x0000d000
546 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M           0x0000e000
547 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M           0x0000f000
548 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
549 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT          20
550 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
551 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT       24
552 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0x00000000
553 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x01000000
554 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x02000000
555 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x03000000
556 #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
557 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT           26
558 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO            0x00000000
559 #define PORT_FEATURE_MBA_LINK_SPEED_10HD            0x04000000
560 #define PORT_FEATURE_MBA_LINK_SPEED_10FD            0x08000000
561 #define PORT_FEATURE_MBA_LINK_SPEED_100HD           0x0c000000
562 #define PORT_FEATURE_MBA_LINK_SPEED_100FD           0x10000000
563 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS           0x14000000
564 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS         0x18000000
565 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4      0x1c000000
566 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4      0x20000000
567 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR       0x24000000
568 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS          0x28000000
569 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS        0x2c000000
570 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS          0x30000000
571 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS          0x34000000
572 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS          0x38000000
573
574         u32 bmc_config;
575 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT      0x00000000
576 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN           0x00000001
577
578         u32 mba_vlan_cfg;
579 #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
580 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT             0
581 #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
582
583         u32 resource_cfg;
584 #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
585 #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
586 #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
587 #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
588 #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
589
590         u32 smbus_config;
591         /* Obsolete */
592 #define PORT_FEATURE_SMBUS_EN                       0x00000001
593 #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
594 #define PORT_FEATURE_SMBUS_ADDR_SHIFT               1
595
596         u32 reserved1;
597
598         u32 link_config;    /* Used as HW defaults for the driver */
599 #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
600 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT         24
601         /* (forced) low speed switch (< 10G) */
602 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH           0x00000000
603         /* (forced) high speed switch (>= 10G) */
604 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH          0x01000000
605 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT         0x02000000
606 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
607
608 #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
609 #define PORT_FEATURE_LINK_SPEED_SHIFT               16
610 #define PORT_FEATURE_LINK_SPEED_AUTO                0x00000000
611 #define PORT_FEATURE_LINK_SPEED_10M_FULL            0x00010000
612 #define PORT_FEATURE_LINK_SPEED_10M_HALF            0x00020000
613 #define PORT_FEATURE_LINK_SPEED_100M_HALF           0x00030000
614 #define PORT_FEATURE_LINK_SPEED_100M_FULL           0x00040000
615 #define PORT_FEATURE_LINK_SPEED_1G                  0x00050000
616 #define PORT_FEATURE_LINK_SPEED_2_5G                0x00060000
617 #define PORT_FEATURE_LINK_SPEED_10G_CX4             0x00070000
618 #define PORT_FEATURE_LINK_SPEED_10G_KX4             0x00080000
619 #define PORT_FEATURE_LINK_SPEED_10G_KR              0x00090000
620 #define PORT_FEATURE_LINK_SPEED_12G                 0x000a0000
621 #define PORT_FEATURE_LINK_SPEED_12_5G               0x000b0000
622 #define PORT_FEATURE_LINK_SPEED_13G                 0x000c0000
623 #define PORT_FEATURE_LINK_SPEED_15G                 0x000d0000
624 #define PORT_FEATURE_LINK_SPEED_16G                 0x000e0000
625
626 #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
627 #define PORT_FEATURE_FLOW_CONTROL_SHIFT             8
628 #define PORT_FEATURE_FLOW_CONTROL_AUTO              0x00000000
629 #define PORT_FEATURE_FLOW_CONTROL_TX                0x00000100
630 #define PORT_FEATURE_FLOW_CONTROL_RX                0x00000200
631 #define PORT_FEATURE_FLOW_CONTROL_BOTH              0x00000300
632 #define PORT_FEATURE_FLOW_CONTROL_NONE              0x00000400
633
634         /* The default for MCP link configuration,
635         uses the same defines as link_config */
636         u32 mfw_wol_link_cfg;
637         /* The default for the driver of the second external phy,
638         uses the same defines as link_config */
639         u32 link_config2;                                       /* 0x47C */
640
641         /* The default for MCP of the second external phy,
642         uses the same defines as link_config */
643         u32 mfw_wol_link_cfg2;                          /* 0x480 */
644
645         u32 Reserved2[17];                                      /* 0x484 */
646
647 };
648
649
650 /****************************************************************************
651  * Device Information                                                       *
652  ****************************************************************************/
653 struct shm_dev_info {                                               /* size */
654
655         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
656
657         struct shared_hw_cfg     shared_hw_config;                    /* 40 */
658
659         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
660
661         struct shared_feat_cfg   shared_feature_config;                /* 4 */
662
663         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
664
665 };
666
667
668 #define FUNC_0                          0
669 #define FUNC_1                          1
670 #define FUNC_2                          2
671 #define FUNC_3                          3
672 #define FUNC_4                          4
673 #define FUNC_5                          5
674 #define FUNC_6                          6
675 #define FUNC_7                          7
676 #define E1_FUNC_MAX                     2
677 #define E1H_FUNC_MAX                    8
678 #define E2_FUNC_MAX         4   /* per path */
679
680 #define VN_0                            0
681 #define VN_1                            1
682 #define VN_2                            2
683 #define VN_3                            3
684 #define E1VN_MAX                        1
685 #define E1HVN_MAX                       4
686
687 #define E2_VF_MAX                       64
688 /* This value (in milliseconds) determines the frequency of the driver
689  * issuing the PULSE message code.  The firmware monitors this periodic
690  * pulse to determine when to switch to an OS-absent mode. */
691 #define DRV_PULSE_PERIOD_MS             250
692
693 /* This value (in milliseconds) determines how long the driver should
694  * wait for an acknowledgement from the firmware before timing out.  Once
695  * the firmware has timed out, the driver will assume there is no firmware
696  * running and there won't be any firmware-driver synchronization during a
697  * driver reset. */
698 #define FW_ACK_TIME_OUT_MS              5000
699
700 #define FW_ACK_POLL_TIME_MS             1
701
702 #define FW_ACK_NUM_OF_POLL      (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
703
704 /* LED Blink rate that will achieve ~15.9Hz */
705 #define LED_BLINK_RATE_VAL              480
706
707 /****************************************************************************
708  * Driver <-> FW Mailbox                                                    *
709  ****************************************************************************/
710 struct drv_port_mb {
711
712         u32 link_status;
713         /* Driver should update this field on any link change event */
714
715 #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
716 #define LINK_STATUS_LINK_UP                             0x00000001
717 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
718 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
719 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
720 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
721 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
722 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
723 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
724 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
725 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
726 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
727 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
728 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
729 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
730 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
731 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
732 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD             (11<<1)
733 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD             (11<<1)
734 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD           (12<<1)
735 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD           (12<<1)
736 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD             (13<<1)
737 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD             (13<<1)
738 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD             (14<<1)
739 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD             (14<<1)
740 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD             (15<<1)
741 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD             (15<<1)
742
743 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
744 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
745
746 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
747 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
748 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
749
750 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
751 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
752 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
753 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
754 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
755 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
756 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
757
758 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
759 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
760
761 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
762 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
763
764 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
765 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
766 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
767 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
768 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
769
770 #define LINK_STATUS_SERDES_LINK                         0x00100000
771
772 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
773 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
774 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
775 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE         0x01000000
776 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE       0x02000000
777 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE         0x04000000
778 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE         0x08000000
779 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE         0x10000000
780
781         u32 port_stx;
782
783         u32 stat_nig_timer;
784
785         /* MCP firmware does not use this field */
786         u32 ext_phy_fw_version;
787
788 };
789
790
791 struct drv_func_mb {
792
793         u32 drv_mb_header;
794 #define DRV_MSG_CODE_MASK                               0xffff0000
795 #define DRV_MSG_CODE_LOAD_REQ                           0x10000000
796 #define DRV_MSG_CODE_LOAD_DONE                          0x11000000
797 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN                  0x20000000
798 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS                 0x20010000
799 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP                 0x20020000
800 #define DRV_MSG_CODE_UNLOAD_DONE                        0x21000000
801 #define DRV_MSG_CODE_DCC_OK                             0x30000000
802 #define DRV_MSG_CODE_DCC_FAILURE                        0x31000000
803 #define DRV_MSG_CODE_DIAG_ENTER_REQ                     0x50000000
804 #define DRV_MSG_CODE_DIAG_EXIT_REQ                      0x60000000
805 #define DRV_MSG_CODE_VALIDATE_KEY                       0x70000000
806 #define DRV_MSG_CODE_GET_CURR_KEY                       0x80000000
807 #define DRV_MSG_CODE_GET_UPGRADE_KEY                    0x81000000
808 #define DRV_MSG_CODE_GET_MANUF_KEY                      0x82000000
809 #define DRV_MSG_CODE_LOAD_L2B_PRAM                      0x90000000
810         /*
811          * The optic module verification commands require bootcode
812          * v5.0.6 or later
813          */
814 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
815 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
816         /*
817          * The specific optic module verification command requires bootcode
818          * v5.2.12 or later
819          */
820 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL      0xa1000000
821 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL      0x00050234
822
823 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG                 0xb0000000
824 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK                    0xb2000000
825 #define DRV_MSG_CODE_SET_MF_BW                          0xe0000000
826 #define REQ_BC_VER_4_SET_MF_BW                          0x00060202
827 #define DRV_MSG_CODE_SET_MF_BW_ACK                      0xe1000000
828 #define BIOS_MSG_CODE_LIC_CHALLENGE                     0xff010000
829 #define BIOS_MSG_CODE_LIC_RESPONSE                      0xff020000
830 #define BIOS_MSG_CODE_VIRT_MAC_PRIM                     0xff030000
831 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI                    0xff040000
832
833 #define DRV_MSG_SEQ_NUMBER_MASK                         0x0000ffff
834
835         u32 drv_mb_param;
836
837         u32 fw_mb_header;
838 #define FW_MSG_CODE_MASK                                0xffff0000
839 #define FW_MSG_CODE_DRV_LOAD_COMMON                     0x10100000
840 #define FW_MSG_CODE_DRV_LOAD_PORT                       0x10110000
841 #define FW_MSG_CODE_DRV_LOAD_FUNCTION                   0x10120000
842         /* Load common chip is supported from bc 6.0.0  */
843 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
844 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
845 #define FW_MSG_CODE_DRV_LOAD_REFUSED                    0x10200000
846 #define FW_MSG_CODE_DRV_LOAD_DONE                       0x11100000
847 #define FW_MSG_CODE_DRV_UNLOAD_COMMON                   0x20100000
848 #define FW_MSG_CODE_DRV_UNLOAD_PORT                     0x20110000
849 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION                 0x20120000
850 #define FW_MSG_CODE_DRV_UNLOAD_DONE                     0x21100000
851 #define FW_MSG_CODE_DCC_DONE                            0x30100000
852 #define FW_MSG_CODE_DIAG_ENTER_DONE                     0x50100000
853 #define FW_MSG_CODE_DIAG_REFUSE                         0x50200000
854 #define FW_MSG_CODE_DIAG_EXIT_DONE                      0x60100000
855 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS                0x70100000
856 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE                0x70200000
857 #define FW_MSG_CODE_GET_KEY_DONE                        0x80100000
858 #define FW_MSG_CODE_NO_KEY                              0x80f00000
859 #define FW_MSG_CODE_LIC_INFO_NOT_READY                  0x80f80000
860 #define FW_MSG_CODE_L2B_PRAM_LOADED                     0x90100000
861 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE             0x90210000
862 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE             0x90220000
863 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE             0x90230000
864 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE             0x90240000
865 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS                0xa0100000
866 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG              0xa0200000
867 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED             0xa0300000
868
869 #define FW_MSG_CODE_LIC_CHALLENGE                       0xff010000
870 #define FW_MSG_CODE_LIC_RESPONSE                        0xff020000
871 #define FW_MSG_CODE_VIRT_MAC_PRIM                       0xff030000
872 #define FW_MSG_CODE_VIRT_MAC_ISCSI                      0xff040000
873
874 #define FW_MSG_SEQ_NUMBER_MASK                          0x0000ffff
875
876         u32 fw_mb_param;
877
878         u32 drv_pulse_mb;
879 #define DRV_PULSE_SEQ_MASK                              0x00007fff
880 #define DRV_PULSE_SYSTEM_TIME_MASK                      0xffff0000
881         /* The system time is in the format of
882          * (year-2001)*12*32 + month*32 + day. */
883 #define DRV_PULSE_ALWAYS_ALIVE                          0x00008000
884         /* Indicate to the firmware not to go into the
885          * OS-absent when it is not getting driver pulse.
886          * This is used for debugging as well for PXE(MBA). */
887
888         u32 mcp_pulse_mb;
889 #define MCP_PULSE_SEQ_MASK                              0x00007fff
890 #define MCP_PULSE_ALWAYS_ALIVE                          0x00008000
891         /* Indicates to the driver not to assert due to lack
892          * of MCP response */
893 #define MCP_EVENT_MASK                                  0xffff0000
894 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ                0x00010000
895
896         u32 iscsi_boot_signature;
897         u32 iscsi_boot_block_offset;
898
899         u32 drv_status;
900 #define DRV_STATUS_PMF                                  0x00000001
901 #define DRV_STATUS_SET_MF_BW                            0x00000004
902
903 #define DRV_STATUS_DCC_EVENT_MASK                       0x0000ff00
904 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF                0x00000100
905 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION             0x00000200
906 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS               0x00000400
907 #define DRV_STATUS_DCC_RESERVED1                        0x00000800
908 #define DRV_STATUS_DCC_SET_PROTOCOL                     0x00001000
909 #define DRV_STATUS_DCC_SET_PRIORITY                     0x00002000
910 #define DRV_STATUS_DCBX_EVENT_MASK                      0x000f0000
911 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS             0x00010000
912
913         u32 virt_mac_upper;
914 #define VIRT_MAC_SIGN_MASK                              0xffff0000
915 #define VIRT_MAC_SIGNATURE                              0x564d0000
916         u32 virt_mac_lower;
917
918 };
919
920
921 /****************************************************************************
922  * Management firmware state                                                *
923  ****************************************************************************/
924 /* Allocate 440 bytes for management firmware */
925 #define MGMTFW_STATE_WORD_SIZE                              110
926
927 struct mgmtfw_state {
928         u32 opaque[MGMTFW_STATE_WORD_SIZE];
929 };
930
931
932 /****************************************************************************
933  * Multi-Function configuration                                             *
934  ****************************************************************************/
935 struct shared_mf_cfg {
936
937         u32 clp_mb;
938 #define SHARED_MF_CLP_SET_DEFAULT                   0x00000000
939         /* set by CLP */
940 #define SHARED_MF_CLP_EXIT                          0x00000001
941         /* set by MCP */
942 #define SHARED_MF_CLP_EXIT_DONE                     0x00010000
943
944 };
945
946 struct port_mf_cfg {
947
948         u32 dynamic_cfg;        /* device control channel */
949 #define PORT_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
950 #define PORT_MF_CFG_E1HOV_TAG_SHIFT                 0
951 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT               PORT_MF_CFG_E1HOV_TAG_MASK
952
953         u32 reserved[3];
954
955 };
956
957 struct func_mf_cfg {
958
959         u32 config;
960         /* E/R/I/D */
961         /* function 0 of each port cannot be hidden */
962 #define FUNC_MF_CFG_FUNC_HIDE                       0x00000001
963
964 #define FUNC_MF_CFG_PROTOCOL_MASK                   0x00000007
965 #define FUNC_MF_CFG_PROTOCOL_ETHERNET               0x00000002
966 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA     0x00000004
967 #define FUNC_MF_CFG_PROTOCOL_ISCSI                  0x00000006
968 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
969         FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
970
971 #define FUNC_MF_CFG_FUNC_DISABLED                   0x00000008
972
973         /* PRI */
974         /* 0 - low priority, 3 - high priority */
975 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK          0x00000300
976 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT         8
977 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT       0x00000000
978
979         /* MINBW, MAXBW */
980         /* value range - 0..100, increments in 100Mbps */
981 #define FUNC_MF_CFG_MIN_BW_MASK                     0x00ff0000
982 #define FUNC_MF_CFG_MIN_BW_SHIFT                    16
983 #define FUNC_MF_CFG_MIN_BW_DEFAULT                  0x00000000
984 #define FUNC_MF_CFG_MAX_BW_MASK                     0xff000000
985 #define FUNC_MF_CFG_MAX_BW_SHIFT                    24
986 #define FUNC_MF_CFG_MAX_BW_DEFAULT                  0x64000000
987
988         u32 mac_upper;          /* MAC */
989 #define FUNC_MF_CFG_UPPERMAC_MASK                   0x0000ffff
990 #define FUNC_MF_CFG_UPPERMAC_SHIFT                  0
991 #define FUNC_MF_CFG_UPPERMAC_DEFAULT                FUNC_MF_CFG_UPPERMAC_MASK
992         u32 mac_lower;
993 #define FUNC_MF_CFG_LOWERMAC_DEFAULT                0xffffffff
994
995         u32 e1hov_tag;  /* VNI */
996 #define FUNC_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
997 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT                 0
998 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT               FUNC_MF_CFG_E1HOV_TAG_MASK
999
1000         u32 reserved[2];
1001
1002 };
1003
1004 /* This structure is not applicable and should not be accessed on 57711 */
1005 struct func_ext_cfg {
1006         u32 func_cfg;
1007 #define MACP_FUNC_CFG_FLAGS_MASK                              0x000000FF
1008 #define MACP_FUNC_CFG_FLAGS_SHIFT                             0
1009 #define MACP_FUNC_CFG_FLAGS_ENABLED                           0x00000001
1010 #define MACP_FUNC_CFG_FLAGS_ETHERNET                          0x00000002
1011 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD                     0x00000004
1012 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD                      0x00000008
1013
1014         u32 iscsi_mac_addr_upper;
1015         u32 iscsi_mac_addr_lower;
1016
1017         u32 fcoe_mac_addr_upper;
1018         u32 fcoe_mac_addr_lower;
1019
1020         u32 fcoe_wwn_port_name_upper;
1021         u32 fcoe_wwn_port_name_lower;
1022
1023         u32 fcoe_wwn_node_name_upper;
1024         u32 fcoe_wwn_node_name_lower;
1025
1026         u32 preserve_data;
1027 #define MF_FUNC_CFG_PRESERVE_L2_MAC                          (1<<0)
1028 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC                       (1<<1)
1029 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC                        (1<<2)
1030 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P                      (1<<3)
1031 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N                      (1<<4)
1032 };
1033
1034 struct mf_cfg {
1035
1036         struct shared_mf_cfg    shared_mf_config;
1037         struct port_mf_cfg      port_mf_config[PORT_MAX];
1038         struct func_mf_cfg      func_mf_config[E1H_FUNC_MAX];
1039
1040         struct func_ext_cfg func_ext_config[E1H_FUNC_MAX];
1041 };
1042
1043
1044 /****************************************************************************
1045  * Shared Memory Region                                                     *
1046  ****************************************************************************/
1047 struct shmem_region {                          /*   SharedMem Offset (size) */
1048
1049         u32                     validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
1050 #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
1051 #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
1052         /* validity bits */
1053 #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
1054 #define SHR_MEM_VALIDITY_MB                         0x00200000
1055 #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
1056 #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
1057         /* One licensing bit should be set */
1058 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
1059 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
1060 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
1061 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
1062         /* Active MFW */
1063 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
1064 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
1065 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
1066 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
1067 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
1068 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
1069
1070         struct shm_dev_info     dev_info;                /* 0x8     (0x438) */
1071
1072         struct license_key      drv_lic_key[PORT_MAX];  /* 0x440 (52*2=0x68) */
1073
1074         /* FW information (for internal FW use) */
1075         u32                     fw_info_fio_offset;    /* 0x4a8       (0x4) */
1076         struct mgmtfw_state     mgmtfw_state;          /* 0x4ac     (0x1b8) */
1077
1078         struct drv_port_mb      port_mb[PORT_MAX];     /* 0x664 (16*2=0x20) */
1079         struct drv_func_mb      func_mb[];             /* 0x684
1080                                              (44*2/4/8=0x58/0xb0/0x160) */
1081
1082 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1083
1084 struct fw_flr_ack {
1085         u32     pf_ack;
1086         u32     vf_ack[1];
1087         u32     iov_dis_ack;
1088 };
1089
1090 struct fw_flr_mb {
1091         u32     aggint;
1092         u32     opgen_addr;
1093         struct  fw_flr_ack ack;
1094 };
1095
1096 /**** SUPPORT FOR SHMEM ARRRAYS ***
1097  * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1098  * define arrays with storage types smaller then unsigned dwords.
1099  * The macros below add generic support for SHMEM arrays with numeric elements
1100  * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1101  * array with individual bit-filed elements accessed using shifts and masks.
1102  *
1103  */
1104
1105 /* eb is the bitwidth of a single element */
1106 #define SHMEM_ARRAY_MASK(eb)            ((1<<(eb))-1)
1107 #define SHMEM_ARRAY_ENTRY(i, eb)        ((i)/(32/(eb)))
1108
1109 /* the bit-position macro allows the used to flip the order of the arrays
1110  * elements on a per byte or word boundary.
1111  *
1112  * example: an array with 8 entries each 4 bit wide. This array will fit into
1113  * a single dword. The diagrmas below show the array order of the nibbles.
1114  *
1115  * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1116  *
1117  *              |               |               |               |
1118  *   0  |   1   |   2   |   3   |   4   |   5   |   6   |   7   |
1119  *              |               |               |               |
1120  *
1121  * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1122  *
1123  *              |               |               |               |
1124  *   1  |   0   |   3   |   2   |   5   |   4   |   7   |   6   |
1125  *              |               |               |               |
1126  *
1127  * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1128  *
1129  *              |               |               |               |
1130  *   3  |   2   |   1   |   0   |   7   |   6   |   5   |   4   |
1131  *              |               |               |               |
1132  */
1133 #define SHMEM_ARRAY_BITPOS(i, eb, fb)   \
1134         ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1135         (((i)%((fb)/(eb))) * (eb)))
1136
1137 #define SHMEM_ARRAY_GET(a, i, eb, fb)                                      \
1138         ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
1139         SHMEM_ARRAY_MASK(eb))
1140
1141 #define SHMEM_ARRAY_SET(a, i, eb, fb, val)                                 \
1142 do {                                                                       \
1143         a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<           \
1144         SHMEM_ARRAY_BITPOS(i, eb, fb));                            \
1145         a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
1146         SHMEM_ARRAY_BITPOS(i, eb, fb));                            \
1147 } while (0)
1148
1149
1150 /****START OF DCBX STRUCTURES DECLARATIONS****/
1151 #define DCBX_MAX_NUM_PRI_PG_ENTRIES     8
1152 #define DCBX_PRI_PG_BITWIDTH            4
1153 #define DCBX_PRI_PG_FBITS               8
1154 #define DCBX_PRI_PG_GET(a, i)           \
1155         SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1156 #define DCBX_PRI_PG_SET(a, i, val)      \
1157         SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1158 #define DCBX_MAX_NUM_PG_BW_ENTRIES      8
1159 #define DCBX_BW_PG_BITWIDTH             8
1160 #define DCBX_PG_BW_GET(a, i)            \
1161         SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1162 #define DCBX_PG_BW_SET(a, i, val)       \
1163         SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1164 #define DCBX_STRICT_PRI_PG              15
1165 #define DCBX_MAX_APP_PROTOCOL           16
1166 #define FCOE_APP_IDX                    0
1167 #define ISCSI_APP_IDX                   1
1168 #define PREDEFINED_APP_IDX_MAX          2
1169
1170 struct dcbx_ets_feature {
1171         u32 enabled;
1172         u32  pg_bw_tbl[2];
1173         u32  pri_pg_tbl[1];
1174 };
1175
1176 struct dcbx_pfc_feature {
1177 #ifdef __BIG_ENDIAN
1178         u8 pri_en_bitmap;
1179 #define DCBX_PFC_PRI_0 0x01
1180 #define DCBX_PFC_PRI_1 0x02
1181 #define DCBX_PFC_PRI_2 0x04
1182 #define DCBX_PFC_PRI_3 0x08
1183 #define DCBX_PFC_PRI_4 0x10
1184 #define DCBX_PFC_PRI_5 0x20
1185 #define DCBX_PFC_PRI_6 0x40
1186 #define DCBX_PFC_PRI_7 0x80
1187         u8 pfc_caps;
1188         u8 reserved;
1189         u8 enabled;
1190 #elif defined(__LITTLE_ENDIAN)
1191         u8 enabled;
1192         u8 reserved;
1193         u8 pfc_caps;
1194         u8 pri_en_bitmap;
1195 #define DCBX_PFC_PRI_0 0x01
1196 #define DCBX_PFC_PRI_1 0x02
1197 #define DCBX_PFC_PRI_2 0x04
1198 #define DCBX_PFC_PRI_3 0x08
1199 #define DCBX_PFC_PRI_4 0x10
1200 #define DCBX_PFC_PRI_5 0x20
1201 #define DCBX_PFC_PRI_6 0x40
1202 #define DCBX_PFC_PRI_7 0x80
1203 #endif
1204 };
1205
1206 struct dcbx_app_priority_entry {
1207 #ifdef __BIG_ENDIAN
1208         u16     app_id;
1209         u8      pri_bitmap;
1210         u8      appBitfield;
1211 #define DCBX_APP_ENTRY_VALID         0x01
1212 #define DCBX_APP_ENTRY_SF_MASK       0x30
1213 #define DCBX_APP_ENTRY_SF_SHIFT      4
1214 #define DCBX_APP_SF_ETH_TYPE         0x10
1215 #define DCBX_APP_SF_PORT             0x20
1216 #elif defined(__LITTLE_ENDIAN)
1217         u8 appBitfield;
1218 #define DCBX_APP_ENTRY_VALID         0x01
1219 #define DCBX_APP_ENTRY_SF_MASK       0x30
1220 #define DCBX_APP_ENTRY_SF_SHIFT      4
1221 #define DCBX_APP_SF_ETH_TYPE         0x10
1222 #define DCBX_APP_SF_PORT             0x20
1223         u8      pri_bitmap;
1224         u16     app_id;
1225 #endif
1226 };
1227
1228 struct dcbx_app_priority_feature {
1229 #ifdef __BIG_ENDIAN
1230         u8 reserved;
1231         u8 default_pri;
1232         u8 tc_supported;
1233         u8 enabled;
1234 #elif defined(__LITTLE_ENDIAN)
1235         u8 enabled;
1236         u8 tc_supported;
1237         u8 default_pri;
1238         u8 reserved;
1239 #endif
1240         struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1241 };
1242
1243 struct dcbx_features {
1244         struct dcbx_ets_feature ets;
1245         struct dcbx_pfc_feature pfc;
1246         struct dcbx_app_priority_feature app;
1247 };
1248
1249 struct lldp_params {
1250 #ifdef __BIG_ENDIAN
1251         u8      msg_fast_tx_interval;
1252         u8      msg_tx_hold;
1253         u8      msg_tx_interval;
1254         u8      admin_status;
1255 #define LLDP_TX_ONLY  0x01
1256 #define LLDP_RX_ONLY  0x02
1257 #define LLDP_TX_RX    0x03
1258 #define LLDP_DISABLED 0x04
1259         u8      reserved1;
1260         u8      tx_fast;
1261         u8      tx_crd_max;
1262         u8      tx_crd;
1263 #elif defined(__LITTLE_ENDIAN)
1264         u8      admin_status;
1265 #define LLDP_TX_ONLY  0x01
1266 #define LLDP_RX_ONLY  0x02
1267 #define LLDP_TX_RX    0x03
1268 #define LLDP_DISABLED 0x04
1269         u8      msg_tx_interval;
1270         u8      msg_tx_hold;
1271         u8      msg_fast_tx_interval;
1272         u8      tx_crd;
1273         u8      tx_crd_max;
1274         u8      tx_fast;
1275         u8      reserved1;
1276 #endif
1277 #define REM_CHASSIS_ID_STAT_LEN 4
1278 #define REM_PORT_ID_STAT_LEN 4
1279         u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1280         u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1281 };
1282
1283 struct lldp_dcbx_stat {
1284 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1285 #define LOCAL_PORT_ID_STAT_LEN 2
1286         u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1287         u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1288         u32 num_tx_dcbx_pkts;
1289         u32 num_rx_dcbx_pkts;
1290 };
1291
1292 struct lldp_admin_mib {
1293         u32     ver_cfg_flags;
1294 #define DCBX_ETS_CONFIG_TX_ENABLED      0x00000001
1295 #define DCBX_PFC_CONFIG_TX_ENABLED      0x00000002
1296 #define DCBX_APP_CONFIG_TX_ENABLED      0x00000004
1297 #define DCBX_ETS_RECO_TX_ENABLED        0x00000008
1298 #define DCBX_ETS_RECO_VALID             0x00000010
1299 #define DCBX_ETS_WILLING                0x00000020
1300 #define DCBX_PFC_WILLING                0x00000040
1301 #define DCBX_APP_WILLING                0x00000080
1302 #define DCBX_VERSION_CEE                0x00000100
1303 #define DCBX_VERSION_IEEE               0x00000200
1304 #define DCBX_DCBX_ENABLED               0x00000400
1305 #define DCBX_CEE_VERSION_MASK           0x0000f000
1306 #define DCBX_CEE_VERSION_SHIFT          12
1307 #define DCBX_CEE_MAX_VERSION_MASK       0x000f0000
1308 #define DCBX_CEE_MAX_VERSION_SHIFT      16
1309         struct dcbx_features    features;
1310 };
1311
1312 struct lldp_remote_mib {
1313         u32 prefix_seq_num;
1314         u32 flags;
1315 #define DCBX_ETS_TLV_RX     0x00000001
1316 #define DCBX_PFC_TLV_RX     0x00000002
1317 #define DCBX_APP_TLV_RX     0x00000004
1318 #define DCBX_ETS_RX_ERROR   0x00000010
1319 #define DCBX_PFC_RX_ERROR   0x00000020
1320 #define DCBX_APP_RX_ERROR   0x00000040
1321 #define DCBX_ETS_REM_WILLING    0x00000100
1322 #define DCBX_PFC_REM_WILLING    0x00000200
1323 #define DCBX_APP_REM_WILLING    0x00000400
1324 #define DCBX_REMOTE_ETS_RECO_VALID  0x00001000
1325         struct dcbx_features features;
1326         u32 suffix_seq_num;
1327 };
1328
1329 struct lldp_local_mib {
1330         u32 prefix_seq_num;
1331         u32 error;
1332 #define DCBX_LOCAL_ETS_ERROR     0x00000001
1333 #define DCBX_LOCAL_PFC_ERROR     0x00000002
1334 #define DCBX_LOCAL_APP_ERROR     0x00000004
1335 #define DCBX_LOCAL_PFC_MISMATCH  0x00000010
1336 #define DCBX_LOCAL_APP_MISMATCH  0x00000020
1337         struct dcbx_features   features;
1338         u32 suffix_seq_num;
1339 };
1340 /***END OF DCBX STRUCTURES DECLARATIONS***/
1341
1342 struct shmem2_region {
1343
1344         u32                     size;
1345
1346         u32                     dcc_support;
1347 #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
1348 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
1349 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
1350 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
1351 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
1352 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
1353 #define SHMEM_DCC_SUPPORT_DEFAULT                   SHMEM_DCC_SUPPORT_NONE
1354         u32 ext_phy_fw_version2[PORT_MAX];
1355         /*
1356          * For backwards compatibility, if the mf_cfg_addr does not exist
1357          * (the size filed is smaller than 0xc) the mf_cfg resides at the
1358          * end of struct shmem_region
1359      */
1360         u32     mf_cfg_addr;
1361 #define SHMEM_MF_CFG_ADDR_NONE                      0x00000000
1362
1363         struct fw_flr_mb flr_mb;
1364         u32     dcbx_lldp_params_offset;
1365 #define SHMEM_LLDP_DCBX_PARAMS_NONE                 0x00000000
1366         u32     dcbx_neg_res_offset;
1367 #define SHMEM_DCBX_NEG_RES_NONE                     0x00000000
1368         u32     dcbx_remote_mib_offset;
1369 #define SHMEM_DCBX_REMOTE_MIB_NONE                  0x00000000
1370         /*
1371          * The other shmemX_base_addr holds the other path's shmem address
1372          * required for example in case of common phy init, or for path1 to know
1373          * the address of mcp debug trace which is located in offset from shmem
1374          * of path0
1375          */
1376         u32 other_shmem_base_addr;
1377         u32 other_shmem2_base_addr;
1378         u32     reserved1[E2_VF_MAX / 32];
1379         u32     reserved2[E2_FUNC_MAX][E2_VF_MAX / 32];
1380         u32     dcbx_lldp_dcbx_stat_offset;
1381 #define SHMEM_LLDP_DCBX_STAT_NONE                  0x00000000
1382 };
1383
1384
1385 struct emac_stats {
1386     u32     rx_stat_ifhcinoctets;
1387     u32     rx_stat_ifhcinbadoctets;
1388     u32     rx_stat_etherstatsfragments;
1389     u32     rx_stat_ifhcinucastpkts;
1390     u32     rx_stat_ifhcinmulticastpkts;
1391     u32     rx_stat_ifhcinbroadcastpkts;
1392     u32     rx_stat_dot3statsfcserrors;
1393     u32     rx_stat_dot3statsalignmenterrors;
1394     u32     rx_stat_dot3statscarriersenseerrors;
1395     u32     rx_stat_xonpauseframesreceived;
1396     u32     rx_stat_xoffpauseframesreceived;
1397     u32     rx_stat_maccontrolframesreceived;
1398     u32     rx_stat_xoffstateentered;
1399     u32     rx_stat_dot3statsframestoolong;
1400     u32     rx_stat_etherstatsjabbers;
1401     u32     rx_stat_etherstatsundersizepkts;
1402     u32     rx_stat_etherstatspkts64octets;
1403     u32     rx_stat_etherstatspkts65octetsto127octets;
1404     u32     rx_stat_etherstatspkts128octetsto255octets;
1405     u32     rx_stat_etherstatspkts256octetsto511octets;
1406     u32     rx_stat_etherstatspkts512octetsto1023octets;
1407     u32     rx_stat_etherstatspkts1024octetsto1522octets;
1408     u32     rx_stat_etherstatspktsover1522octets;
1409
1410     u32     rx_stat_falsecarriererrors;
1411
1412     u32     tx_stat_ifhcoutoctets;
1413     u32     tx_stat_ifhcoutbadoctets;
1414     u32     tx_stat_etherstatscollisions;
1415     u32     tx_stat_outxonsent;
1416     u32     tx_stat_outxoffsent;
1417     u32     tx_stat_flowcontroldone;
1418     u32     tx_stat_dot3statssinglecollisionframes;
1419     u32     tx_stat_dot3statsmultiplecollisionframes;
1420     u32     tx_stat_dot3statsdeferredtransmissions;
1421     u32     tx_stat_dot3statsexcessivecollisions;
1422     u32     tx_stat_dot3statslatecollisions;
1423     u32     tx_stat_ifhcoutucastpkts;
1424     u32     tx_stat_ifhcoutmulticastpkts;
1425     u32     tx_stat_ifhcoutbroadcastpkts;
1426     u32     tx_stat_etherstatspkts64octets;
1427     u32     tx_stat_etherstatspkts65octetsto127octets;
1428     u32     tx_stat_etherstatspkts128octetsto255octets;
1429     u32     tx_stat_etherstatspkts256octetsto511octets;
1430     u32     tx_stat_etherstatspkts512octetsto1023octets;
1431     u32     tx_stat_etherstatspkts1024octetsto1522octets;
1432     u32     tx_stat_etherstatspktsover1522octets;
1433     u32     tx_stat_dot3statsinternalmactransmiterrors;
1434 };
1435
1436
1437 struct bmac1_stats {
1438     u32     tx_stat_gtpkt_lo;
1439     u32     tx_stat_gtpkt_hi;
1440     u32     tx_stat_gtxpf_lo;
1441     u32     tx_stat_gtxpf_hi;
1442     u32     tx_stat_gtfcs_lo;
1443     u32     tx_stat_gtfcs_hi;
1444     u32     tx_stat_gtmca_lo;
1445     u32     tx_stat_gtmca_hi;
1446     u32     tx_stat_gtbca_lo;
1447     u32     tx_stat_gtbca_hi;
1448     u32     tx_stat_gtfrg_lo;
1449     u32     tx_stat_gtfrg_hi;
1450     u32     tx_stat_gtovr_lo;
1451     u32     tx_stat_gtovr_hi;
1452     u32     tx_stat_gt64_lo;
1453     u32     tx_stat_gt64_hi;
1454     u32     tx_stat_gt127_lo;
1455     u32     tx_stat_gt127_hi;
1456     u32     tx_stat_gt255_lo;
1457     u32     tx_stat_gt255_hi;
1458     u32     tx_stat_gt511_lo;
1459     u32     tx_stat_gt511_hi;
1460     u32     tx_stat_gt1023_lo;
1461     u32     tx_stat_gt1023_hi;
1462     u32     tx_stat_gt1518_lo;
1463     u32     tx_stat_gt1518_hi;
1464     u32     tx_stat_gt2047_lo;
1465     u32     tx_stat_gt2047_hi;
1466     u32     tx_stat_gt4095_lo;
1467     u32     tx_stat_gt4095_hi;
1468     u32     tx_stat_gt9216_lo;
1469     u32     tx_stat_gt9216_hi;
1470     u32     tx_stat_gt16383_lo;
1471     u32     tx_stat_gt16383_hi;
1472     u32     tx_stat_gtmax_lo;
1473     u32     tx_stat_gtmax_hi;
1474     u32     tx_stat_gtufl_lo;
1475     u32     tx_stat_gtufl_hi;
1476     u32     tx_stat_gterr_lo;
1477     u32     tx_stat_gterr_hi;
1478     u32     tx_stat_gtbyt_lo;
1479     u32     tx_stat_gtbyt_hi;
1480
1481     u32     rx_stat_gr64_lo;
1482     u32     rx_stat_gr64_hi;
1483     u32     rx_stat_gr127_lo;
1484     u32     rx_stat_gr127_hi;
1485     u32     rx_stat_gr255_lo;
1486     u32     rx_stat_gr255_hi;
1487     u32     rx_stat_gr511_lo;
1488     u32     rx_stat_gr511_hi;
1489     u32     rx_stat_gr1023_lo;
1490     u32     rx_stat_gr1023_hi;
1491     u32     rx_stat_gr1518_lo;
1492     u32     rx_stat_gr1518_hi;
1493     u32     rx_stat_gr2047_lo;
1494     u32     rx_stat_gr2047_hi;
1495     u32     rx_stat_gr4095_lo;
1496     u32     rx_stat_gr4095_hi;
1497     u32     rx_stat_gr9216_lo;
1498     u32     rx_stat_gr9216_hi;
1499     u32     rx_stat_gr16383_lo;
1500     u32     rx_stat_gr16383_hi;
1501     u32     rx_stat_grmax_lo;
1502     u32     rx_stat_grmax_hi;
1503     u32     rx_stat_grpkt_lo;
1504     u32     rx_stat_grpkt_hi;
1505     u32     rx_stat_grfcs_lo;
1506     u32     rx_stat_grfcs_hi;
1507     u32     rx_stat_grmca_lo;
1508     u32     rx_stat_grmca_hi;
1509     u32     rx_stat_grbca_lo;
1510     u32     rx_stat_grbca_hi;
1511     u32     rx_stat_grxcf_lo;
1512     u32     rx_stat_grxcf_hi;
1513     u32     rx_stat_grxpf_lo;
1514     u32     rx_stat_grxpf_hi;
1515     u32     rx_stat_grxuo_lo;
1516     u32     rx_stat_grxuo_hi;
1517     u32     rx_stat_grjbr_lo;
1518     u32     rx_stat_grjbr_hi;
1519     u32     rx_stat_grovr_lo;
1520     u32     rx_stat_grovr_hi;
1521     u32     rx_stat_grflr_lo;
1522     u32     rx_stat_grflr_hi;
1523     u32     rx_stat_grmeg_lo;
1524     u32     rx_stat_grmeg_hi;
1525     u32     rx_stat_grmeb_lo;
1526     u32     rx_stat_grmeb_hi;
1527     u32     rx_stat_grbyt_lo;
1528     u32     rx_stat_grbyt_hi;
1529     u32     rx_stat_grund_lo;
1530     u32     rx_stat_grund_hi;
1531     u32     rx_stat_grfrg_lo;
1532     u32     rx_stat_grfrg_hi;
1533     u32     rx_stat_grerb_lo;
1534     u32     rx_stat_grerb_hi;
1535     u32     rx_stat_grfre_lo;
1536     u32     rx_stat_grfre_hi;
1537     u32     rx_stat_gripj_lo;
1538     u32     rx_stat_gripj_hi;
1539 };
1540
1541 struct bmac2_stats {
1542         u32     tx_stat_gtpk_lo; /* gtpok */
1543         u32     tx_stat_gtpk_hi; /* gtpok */
1544         u32     tx_stat_gtxpf_lo; /* gtpf */
1545         u32     tx_stat_gtxpf_hi; /* gtpf */
1546         u32     tx_stat_gtpp_lo; /* NEW BMAC2 */
1547         u32     tx_stat_gtpp_hi; /* NEW BMAC2 */
1548         u32     tx_stat_gtfcs_lo;
1549         u32     tx_stat_gtfcs_hi;
1550         u32     tx_stat_gtuca_lo; /* NEW BMAC2 */
1551         u32     tx_stat_gtuca_hi; /* NEW BMAC2 */
1552         u32     tx_stat_gtmca_lo;
1553         u32     tx_stat_gtmca_hi;
1554         u32     tx_stat_gtbca_lo;
1555         u32     tx_stat_gtbca_hi;
1556         u32     tx_stat_gtovr_lo;
1557         u32     tx_stat_gtovr_hi;
1558         u32     tx_stat_gtfrg_lo;
1559         u32     tx_stat_gtfrg_hi;
1560         u32     tx_stat_gtpkt1_lo; /* gtpkt */
1561         u32     tx_stat_gtpkt1_hi; /* gtpkt */
1562         u32     tx_stat_gt64_lo;
1563         u32     tx_stat_gt64_hi;
1564         u32     tx_stat_gt127_lo;
1565         u32     tx_stat_gt127_hi;
1566         u32     tx_stat_gt255_lo;
1567         u32     tx_stat_gt255_hi;
1568         u32     tx_stat_gt511_lo;
1569         u32     tx_stat_gt511_hi;
1570         u32     tx_stat_gt1023_lo;
1571         u32     tx_stat_gt1023_hi;
1572         u32     tx_stat_gt1518_lo;
1573         u32     tx_stat_gt1518_hi;
1574         u32     tx_stat_gt2047_lo;
1575         u32     tx_stat_gt2047_hi;
1576         u32     tx_stat_gt4095_lo;
1577         u32     tx_stat_gt4095_hi;
1578         u32     tx_stat_gt9216_lo;
1579         u32     tx_stat_gt9216_hi;
1580         u32     tx_stat_gt16383_lo;
1581         u32     tx_stat_gt16383_hi;
1582         u32     tx_stat_gtmax_lo;
1583         u32     tx_stat_gtmax_hi;
1584         u32     tx_stat_gtufl_lo;
1585         u32     tx_stat_gtufl_hi;
1586         u32     tx_stat_gterr_lo;
1587         u32     tx_stat_gterr_hi;
1588         u32     tx_stat_gtbyt_lo;
1589         u32     tx_stat_gtbyt_hi;
1590
1591         u32     rx_stat_gr64_lo;
1592         u32     rx_stat_gr64_hi;
1593         u32     rx_stat_gr127_lo;
1594         u32     rx_stat_gr127_hi;
1595         u32     rx_stat_gr255_lo;
1596         u32     rx_stat_gr255_hi;
1597         u32     rx_stat_gr511_lo;
1598         u32     rx_stat_gr511_hi;
1599         u32     rx_stat_gr1023_lo;
1600         u32     rx_stat_gr1023_hi;
1601         u32     rx_stat_gr1518_lo;
1602         u32     rx_stat_gr1518_hi;
1603         u32     rx_stat_gr2047_lo;
1604         u32     rx_stat_gr2047_hi;
1605         u32     rx_stat_gr4095_lo;
1606         u32     rx_stat_gr4095_hi;
1607         u32     rx_stat_gr9216_lo;
1608         u32     rx_stat_gr9216_hi;
1609         u32     rx_stat_gr16383_lo;
1610         u32     rx_stat_gr16383_hi;
1611         u32     rx_stat_grmax_lo;
1612         u32     rx_stat_grmax_hi;
1613         u32     rx_stat_grpkt_lo;
1614         u32     rx_stat_grpkt_hi;
1615         u32     rx_stat_grfcs_lo;
1616         u32     rx_stat_grfcs_hi;
1617         u32     rx_stat_gruca_lo;
1618         u32     rx_stat_gruca_hi;
1619         u32     rx_stat_grmca_lo;
1620         u32     rx_stat_grmca_hi;
1621         u32     rx_stat_grbca_lo;
1622         u32     rx_stat_grbca_hi;
1623         u32     rx_stat_grxpf_lo; /* grpf */
1624         u32     rx_stat_grxpf_hi; /* grpf */
1625         u32     rx_stat_grpp_lo;
1626         u32     rx_stat_grpp_hi;
1627         u32     rx_stat_grxuo_lo; /* gruo */
1628         u32     rx_stat_grxuo_hi; /* gruo */
1629         u32     rx_stat_grjbr_lo;
1630         u32     rx_stat_grjbr_hi;
1631         u32     rx_stat_grovr_lo;
1632         u32     rx_stat_grovr_hi;
1633         u32     rx_stat_grxcf_lo; /* grcf */
1634         u32     rx_stat_grxcf_hi; /* grcf */
1635         u32     rx_stat_grflr_lo;
1636         u32     rx_stat_grflr_hi;
1637         u32     rx_stat_grpok_lo;
1638         u32     rx_stat_grpok_hi;
1639         u32     rx_stat_grmeg_lo;
1640         u32     rx_stat_grmeg_hi;
1641         u32     rx_stat_grmeb_lo;
1642         u32     rx_stat_grmeb_hi;
1643         u32     rx_stat_grbyt_lo;
1644         u32     rx_stat_grbyt_hi;
1645         u32     rx_stat_grund_lo;
1646         u32     rx_stat_grund_hi;
1647         u32     rx_stat_grfrg_lo;
1648         u32     rx_stat_grfrg_hi;
1649         u32     rx_stat_grerb_lo; /* grerrbyt */
1650         u32     rx_stat_grerb_hi; /* grerrbyt */
1651         u32     rx_stat_grfre_lo; /* grfrerr */
1652         u32     rx_stat_grfre_hi; /* grfrerr */
1653         u32     rx_stat_gripj_lo;
1654         u32     rx_stat_gripj_hi;
1655 };
1656
1657 union mac_stats {
1658         struct emac_stats        emac_stats;
1659         struct bmac1_stats       bmac1_stats;
1660         struct bmac2_stats       bmac2_stats;
1661 };
1662
1663
1664 struct mac_stx {
1665     /* in_bad_octets */
1666     u32     rx_stat_ifhcinbadoctets_hi;
1667     u32     rx_stat_ifhcinbadoctets_lo;
1668
1669     /* out_bad_octets */
1670     u32     tx_stat_ifhcoutbadoctets_hi;
1671     u32     tx_stat_ifhcoutbadoctets_lo;
1672
1673     /* crc_receive_errors */
1674     u32     rx_stat_dot3statsfcserrors_hi;
1675     u32     rx_stat_dot3statsfcserrors_lo;
1676     /* alignment_errors */
1677     u32     rx_stat_dot3statsalignmenterrors_hi;
1678     u32     rx_stat_dot3statsalignmenterrors_lo;
1679     /* carrier_sense_errors */
1680     u32     rx_stat_dot3statscarriersenseerrors_hi;
1681     u32     rx_stat_dot3statscarriersenseerrors_lo;
1682     /* false_carrier_detections */
1683     u32     rx_stat_falsecarriererrors_hi;
1684     u32     rx_stat_falsecarriererrors_lo;
1685
1686     /* runt_packets_received */
1687     u32     rx_stat_etherstatsundersizepkts_hi;
1688     u32     rx_stat_etherstatsundersizepkts_lo;
1689     /* jabber_packets_received */
1690     u32     rx_stat_dot3statsframestoolong_hi;
1691     u32     rx_stat_dot3statsframestoolong_lo;
1692
1693     /* error_runt_packets_received */
1694     u32     rx_stat_etherstatsfragments_hi;
1695     u32     rx_stat_etherstatsfragments_lo;
1696     /* error_jabber_packets_received */
1697     u32     rx_stat_etherstatsjabbers_hi;
1698     u32     rx_stat_etherstatsjabbers_lo;
1699
1700     /* control_frames_received */
1701     u32     rx_stat_maccontrolframesreceived_hi;
1702     u32     rx_stat_maccontrolframesreceived_lo;
1703     u32     rx_stat_bmac_xpf_hi;
1704     u32     rx_stat_bmac_xpf_lo;
1705     u32     rx_stat_bmac_xcf_hi;
1706     u32     rx_stat_bmac_xcf_lo;
1707
1708     /* xoff_state_entered */
1709     u32     rx_stat_xoffstateentered_hi;
1710     u32     rx_stat_xoffstateentered_lo;
1711     /* pause_xon_frames_received */
1712     u32     rx_stat_xonpauseframesreceived_hi;
1713     u32     rx_stat_xonpauseframesreceived_lo;
1714     /* pause_xoff_frames_received */
1715     u32     rx_stat_xoffpauseframesreceived_hi;
1716     u32     rx_stat_xoffpauseframesreceived_lo;
1717     /* pause_xon_frames_transmitted */
1718     u32     tx_stat_outxonsent_hi;
1719     u32     tx_stat_outxonsent_lo;
1720     /* pause_xoff_frames_transmitted */
1721     u32     tx_stat_outxoffsent_hi;
1722     u32     tx_stat_outxoffsent_lo;
1723     /* flow_control_done */
1724     u32     tx_stat_flowcontroldone_hi;
1725     u32     tx_stat_flowcontroldone_lo;
1726
1727     /* ether_stats_collisions */
1728     u32     tx_stat_etherstatscollisions_hi;
1729     u32     tx_stat_etherstatscollisions_lo;
1730     /* single_collision_transmit_frames */
1731     u32     tx_stat_dot3statssinglecollisionframes_hi;
1732     u32     tx_stat_dot3statssinglecollisionframes_lo;
1733     /* multiple_collision_transmit_frames */
1734     u32     tx_stat_dot3statsmultiplecollisionframes_hi;
1735     u32     tx_stat_dot3statsmultiplecollisionframes_lo;
1736     /* deferred_transmissions */
1737     u32     tx_stat_dot3statsdeferredtransmissions_hi;
1738     u32     tx_stat_dot3statsdeferredtransmissions_lo;
1739     /* excessive_collision_frames */
1740     u32     tx_stat_dot3statsexcessivecollisions_hi;
1741     u32     tx_stat_dot3statsexcessivecollisions_lo;
1742     /* late_collision_frames */
1743     u32     tx_stat_dot3statslatecollisions_hi;
1744     u32     tx_stat_dot3statslatecollisions_lo;
1745
1746     /* frames_transmitted_64_bytes */
1747     u32     tx_stat_etherstatspkts64octets_hi;
1748     u32     tx_stat_etherstatspkts64octets_lo;
1749     /* frames_transmitted_65_127_bytes */
1750     u32     tx_stat_etherstatspkts65octetsto127octets_hi;
1751     u32     tx_stat_etherstatspkts65octetsto127octets_lo;
1752     /* frames_transmitted_128_255_bytes */
1753     u32     tx_stat_etherstatspkts128octetsto255octets_hi;
1754     u32     tx_stat_etherstatspkts128octetsto255octets_lo;
1755     /* frames_transmitted_256_511_bytes */
1756     u32     tx_stat_etherstatspkts256octetsto511octets_hi;
1757     u32     tx_stat_etherstatspkts256octetsto511octets_lo;
1758     /* frames_transmitted_512_1023_bytes */
1759     u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
1760     u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
1761     /* frames_transmitted_1024_1522_bytes */
1762     u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
1763     u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
1764     /* frames_transmitted_1523_9022_bytes */
1765     u32     tx_stat_etherstatspktsover1522octets_hi;
1766     u32     tx_stat_etherstatspktsover1522octets_lo;
1767     u32     tx_stat_bmac_2047_hi;
1768     u32     tx_stat_bmac_2047_lo;
1769     u32     tx_stat_bmac_4095_hi;
1770     u32     tx_stat_bmac_4095_lo;
1771     u32     tx_stat_bmac_9216_hi;
1772     u32     tx_stat_bmac_9216_lo;
1773     u32     tx_stat_bmac_16383_hi;
1774     u32     tx_stat_bmac_16383_lo;
1775
1776     /* internal_mac_transmit_errors */
1777     u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
1778     u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
1779
1780     /* if_out_discards */
1781     u32     tx_stat_bmac_ufl_hi;
1782     u32     tx_stat_bmac_ufl_lo;
1783 };
1784
1785
1786 #define MAC_STX_IDX_MAX                     2
1787
1788 struct host_port_stats {
1789     u32            host_port_stats_start;
1790
1791     struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1792
1793     u32            brb_drop_hi;
1794     u32            brb_drop_lo;
1795
1796     u32            host_port_stats_end;
1797 };
1798
1799
1800 struct host_func_stats {
1801     u32     host_func_stats_start;
1802
1803     u32     total_bytes_received_hi;
1804     u32     total_bytes_received_lo;
1805
1806     u32     total_bytes_transmitted_hi;
1807     u32     total_bytes_transmitted_lo;
1808
1809     u32     total_unicast_packets_received_hi;
1810     u32     total_unicast_packets_received_lo;
1811
1812     u32     total_multicast_packets_received_hi;
1813     u32     total_multicast_packets_received_lo;
1814
1815     u32     total_broadcast_packets_received_hi;
1816     u32     total_broadcast_packets_received_lo;
1817
1818     u32     total_unicast_packets_transmitted_hi;
1819     u32     total_unicast_packets_transmitted_lo;
1820
1821     u32     total_multicast_packets_transmitted_hi;
1822     u32     total_multicast_packets_transmitted_lo;
1823
1824     u32     total_broadcast_packets_transmitted_hi;
1825     u32     total_broadcast_packets_transmitted_lo;
1826
1827     u32     valid_bytes_received_hi;
1828     u32     valid_bytes_received_lo;
1829
1830     u32     host_func_stats_end;
1831 };
1832
1833
1834 #define BCM_5710_FW_MAJOR_VERSION                       6
1835 #define BCM_5710_FW_MINOR_VERSION                       2
1836 #define BCM_5710_FW_REVISION_VERSION                    5
1837 #define BCM_5710_FW_ENGINEERING_VERSION                 0
1838 #define BCM_5710_FW_COMPILE_FLAGS                       1
1839
1840
1841 /*
1842  * attention bits
1843  */
1844 struct atten_sp_status_block {
1845         __le32 attn_bits;
1846         __le32 attn_bits_ack;
1847         u8 status_block_id;
1848         u8 reserved0;
1849         __le16 attn_bits_index;
1850         __le32 reserved1;
1851 };
1852
1853
1854 /*
1855  * common data for all protocols
1856  */
1857 struct doorbell_hdr {
1858         u8 header;
1859 #define DOORBELL_HDR_RX (0x1<<0)
1860 #define DOORBELL_HDR_RX_SHIFT 0
1861 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1862 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1863 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1864 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1865 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1866 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1867 };
1868
1869 /*
1870  * doorbell message sent to the chip
1871  */
1872 struct doorbell {
1873 #if defined(__BIG_ENDIAN)
1874         u16 zero_fill2;
1875         u8 zero_fill1;
1876         struct doorbell_hdr header;
1877 #elif defined(__LITTLE_ENDIAN)
1878         struct doorbell_hdr header;
1879         u8 zero_fill1;
1880         u16 zero_fill2;
1881 #endif
1882 };
1883
1884
1885 /*
1886  * doorbell message sent to the chip
1887  */
1888 struct doorbell_set_prod {
1889 #if defined(__BIG_ENDIAN)
1890         u16 prod;
1891         u8 zero_fill1;
1892         struct doorbell_hdr header;
1893 #elif defined(__LITTLE_ENDIAN)
1894         struct doorbell_hdr header;
1895         u8 zero_fill1;
1896         u16 prod;
1897 #endif
1898 };
1899
1900
1901 /*
1902  * 3 lines. status block
1903  */
1904 struct hc_status_block_e1x {
1905         __le16 index_values[HC_SB_MAX_INDICES_E1X];
1906         __le16 running_index[HC_SB_MAX_SM];
1907         u32 rsrv;
1908 };
1909
1910 /*
1911  * host status block
1912  */
1913 struct host_hc_status_block_e1x {
1914         struct hc_status_block_e1x sb;
1915 };
1916
1917
1918 /*
1919  * 3 lines. status block
1920  */
1921 struct hc_status_block_e2 {
1922         __le16 index_values[HC_SB_MAX_INDICES_E2];
1923         __le16 running_index[HC_SB_MAX_SM];
1924         u32 reserved;
1925 };
1926
1927 /*
1928  * host status block
1929  */
1930 struct host_hc_status_block_e2 {
1931         struct hc_status_block_e2 sb;
1932 };
1933
1934
1935 /*
1936  * 5 lines. slow-path status block
1937  */
1938 struct hc_sp_status_block {
1939         __le16 index_values[HC_SP_SB_MAX_INDICES];
1940         __le16 running_index;
1941         __le16 rsrv;
1942         u32 rsrv1;
1943 };
1944
1945 /*
1946  * host status block
1947  */
1948 struct host_sp_status_block {
1949         struct atten_sp_status_block atten_status_block;
1950         struct hc_sp_status_block sp_sb;
1951 };
1952
1953
1954 /*
1955  * IGU driver acknowledgment register
1956  */
1957 struct igu_ack_register {
1958 #if defined(__BIG_ENDIAN)
1959         u16 sb_id_and_flags;
1960 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1961 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1962 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1963 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1964 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1965 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1966 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1967 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1968 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1969 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1970         u16 status_block_index;
1971 #elif defined(__LITTLE_ENDIAN)
1972         u16 status_block_index;
1973         u16 sb_id_and_flags;
1974 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1975 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1976 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1977 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1978 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1979 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1980 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1981 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1982 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1983 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1984 #endif
1985 };
1986
1987
1988 /*
1989  * IGU driver acknowledgement register
1990  */
1991 struct igu_backward_compatible {
1992         u32 sb_id_and_flags;
1993 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
1994 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
1995 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
1996 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
1997 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
1998 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
1999 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
2000 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
2001 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
2002 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
2003 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
2004 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
2005         u32 reserved_2;
2006 };
2007
2008
2009 /*
2010  * IGU driver acknowledgement register
2011  */
2012 struct igu_regular {
2013         u32 sb_id_and_flags;
2014 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
2015 #define IGU_REGULAR_SB_INDEX_SHIFT 0
2016 #define IGU_REGULAR_RESERVED0 (0x1<<20)
2017 #define IGU_REGULAR_RESERVED0_SHIFT 20
2018 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
2019 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
2020 #define IGU_REGULAR_BUPDATE (0x1<<24)
2021 #define IGU_REGULAR_BUPDATE_SHIFT 24
2022 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
2023 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
2024 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
2025 #define IGU_REGULAR_RESERVED_1_SHIFT 27
2026 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
2027 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
2028 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
2029 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
2030 #define IGU_REGULAR_BCLEANUP (0x1<<31)
2031 #define IGU_REGULAR_BCLEANUP_SHIFT 31
2032         u32 reserved_2;
2033 };
2034
2035 /*
2036  * IGU driver acknowledgement register
2037  */
2038 union igu_consprod_reg {
2039         struct igu_regular regular;
2040         struct igu_backward_compatible backward_compatible;
2041 };
2042
2043
2044 /*
2045  * Control register for the IGU command register
2046  */
2047 struct igu_ctrl_reg {
2048         u32 ctrl_data;
2049 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
2050 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
2051 #define IGU_CTRL_REG_FID (0x7F<<12)
2052 #define IGU_CTRL_REG_FID_SHIFT 12
2053 #define IGU_CTRL_REG_RESERVED (0x1<<19)
2054 #define IGU_CTRL_REG_RESERVED_SHIFT 19
2055 #define IGU_CTRL_REG_TYPE (0x1<<20)
2056 #define IGU_CTRL_REG_TYPE_SHIFT 20
2057 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
2058 #define IGU_CTRL_REG_UNUSED_SHIFT 21
2059 };
2060
2061
2062 /*
2063  * Parser parsing flags field
2064  */
2065 struct parsing_flags {
2066         __le16 flags;
2067 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
2068 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
2069 #define PARSING_FLAGS_VLAN (0x1<<1)
2070 #define PARSING_FLAGS_VLAN_SHIFT 1
2071 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
2072 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
2073 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
2074 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
2075 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
2076 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
2077 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
2078 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
2079 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
2080 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
2081 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
2082 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
2083 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
2084 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
2085 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
2086 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
2087 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
2088 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
2089 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
2090 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
2091 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
2092 #define PARSING_FLAGS_RESERVED0_SHIFT 14
2093 };
2094
2095
2096 struct regpair {
2097         __le32 lo;
2098         __le32 hi;
2099 };
2100
2101
2102 /*
2103  * dmae command structure
2104  */
2105 struct dmae_command {
2106         u32 opcode;
2107 #define DMAE_COMMAND_SRC (0x1<<0)
2108 #define DMAE_COMMAND_SRC_SHIFT 0
2109 #define DMAE_COMMAND_DST (0x3<<1)
2110 #define DMAE_COMMAND_DST_SHIFT 1
2111 #define DMAE_COMMAND_C_DST (0x1<<3)
2112 #define DMAE_COMMAND_C_DST_SHIFT 3
2113 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2114 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2115 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2116 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2117 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2118 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2119 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2120 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2121 #define DMAE_COMMAND_PORT (0x1<<11)
2122 #define DMAE_COMMAND_PORT_SHIFT 11
2123 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2124 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2125 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2126 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2127 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2128 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2129 #define DMAE_COMMAND_E1HVN (0x3<<15)
2130 #define DMAE_COMMAND_E1HVN_SHIFT 15
2131 #define DMAE_COMMAND_DST_VN (0x3<<17)
2132 #define DMAE_COMMAND_DST_VN_SHIFT 17
2133 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2134 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2135 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2136 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2137 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2138 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2139         u32 src_addr_lo;
2140         u32 src_addr_hi;
2141         u32 dst_addr_lo;
2142         u32 dst_addr_hi;
2143 #if defined(__BIG_ENDIAN)
2144         u16 reserved1;
2145         u16 len;
2146 #elif defined(__LITTLE_ENDIAN)
2147         u16 len;
2148         u16 reserved1;
2149 #endif
2150         u32 comp_addr_lo;
2151         u32 comp_addr_hi;
2152         u32 comp_val;
2153         u32 crc32;
2154         u32 crc32_c;
2155 #if defined(__BIG_ENDIAN)
2156         u16 crc16_c;
2157         u16 crc16;
2158 #elif defined(__LITTLE_ENDIAN)
2159         u16 crc16;
2160         u16 crc16_c;
2161 #endif
2162 #if defined(__BIG_ENDIAN)
2163         u16 reserved3;
2164         u16 crc_t10;
2165 #elif defined(__LITTLE_ENDIAN)
2166         u16 crc_t10;
2167         u16 reserved3;
2168 #endif
2169 #if defined(__BIG_ENDIAN)
2170         u16 xsum8;
2171         u16 xsum16;
2172 #elif defined(__LITTLE_ENDIAN)
2173         u16 xsum16;
2174         u16 xsum8;
2175 #endif
2176 };
2177
2178
2179 struct double_regpair {
2180         u32 regpair0_lo;
2181         u32 regpair0_hi;
2182         u32 regpair1_lo;
2183         u32 regpair1_hi;
2184 };
2185
2186
2187 /*
2188  * SDM operation gen command (generate aggregative interrupt)
2189  */
2190 struct sdm_op_gen {
2191         __le32 command;
2192 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
2193 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
2194 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
2195 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
2196 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
2197 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
2198 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
2199 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
2200 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
2201 #define SDM_OP_GEN_RESERVED_SHIFT 17
2202 };
2203
2204 /*
2205  * The eth Rx Buffer Descriptor
2206  */
2207 struct eth_rx_bd {
2208         __le32 addr_lo;
2209         __le32 addr_hi;
2210 };
2211
2212 /*
2213  * The eth Rx SGE Descriptor
2214  */
2215 struct eth_rx_sge {
2216         __le32 addr_lo;
2217         __le32 addr_hi;
2218 };
2219
2220
2221
2222 /*
2223  * The eth storm context of Ustorm
2224  */
2225 struct ustorm_eth_st_context {
2226         u32 reserved0[48];
2227 };
2228
2229 /*
2230  * The eth storm context of Tstorm
2231  */
2232 struct tstorm_eth_st_context {
2233         u32 __reserved0[28];
2234 };
2235
2236 /*
2237  * The eth aggregative context of Xstorm
2238  */
2239 struct xstorm_eth_ag_context {
2240         u32 reserved0;
2241 #if defined(__BIG_ENDIAN)
2242         u8 cdu_reserved;
2243         u8 reserved2;
2244         u16 reserved1;
2245 #elif defined(__LITTLE_ENDIAN)
2246         u16 reserved1;
2247         u8 reserved2;
2248         u8 cdu_reserved;
2249 #endif
2250         u32 reserved3[30];
2251 };
2252
2253 /*
2254  * The eth aggregative context of Tstorm
2255  */
2256 struct tstorm_eth_ag_context {
2257         u32 __reserved0[14];
2258 };
2259
2260
2261 /*
2262  * The eth aggregative context of Cstorm
2263  */
2264 struct cstorm_eth_ag_context {
2265         u32 __reserved0[10];
2266 };
2267
2268
2269 /*
2270  * The eth aggregative context of Ustorm
2271  */
2272 struct ustorm_eth_ag_context {
2273         u32 __reserved0;
2274 #if defined(__BIG_ENDIAN)
2275         u8 cdu_usage;
2276         u8 __reserved2;
2277         u16 __reserved1;
2278 #elif defined(__LITTLE_ENDIAN)
2279         u16 __reserved1;
2280         u8 __reserved2;
2281         u8 cdu_usage;
2282 #endif
2283         u32 __reserved3[6];
2284 };
2285
2286 /*
2287  * Timers connection context
2288  */
2289 struct timers_block_context {
2290         u32 __reserved_0;
2291         u32 __reserved_1;
2292         u32 __reserved_2;
2293         u32 flags;
2294 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
2295 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
2296 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
2297 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
2298 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
2299 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
2300 };
2301
2302 /*
2303  * structure for easy accessibility to assembler
2304  */
2305 struct eth_tx_bd_flags {
2306         u8 as_bitfield;
2307 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
2308 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
2309 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
2310 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
2311 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
2312 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
2313 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
2314 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
2315 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
2316 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
2317 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
2318 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
2319 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
2320 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
2321 };
2322
2323 /*
2324  * The eth Tx Buffer Descriptor
2325  */
2326 struct eth_tx_start_bd {
2327         __le32 addr_lo;
2328         __le32 addr_hi;
2329         __le16 nbd;
2330         __le16 nbytes;
2331         __le16 vlan_or_ethertype;
2332         struct eth_tx_bd_flags bd_flags;
2333         u8 general_data;
2334 #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
2335 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
2336 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
2337 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
2338 };
2339
2340 /*
2341  * Tx regular BD structure
2342  */
2343 struct eth_tx_bd {
2344         __le32 addr_lo;
2345         __le32 addr_hi;
2346         __le16 total_pkt_bytes;
2347         __le16 nbytes;
2348         u8 reserved[4];
2349 };
2350
2351 /*
2352  * Tx parsing BD structure for ETH E1/E1h
2353  */
2354 struct eth_tx_parse_bd_e1x {
2355         u8 global_data;
2356 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
2357 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
2358 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
2359 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
2360 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
2361 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
2362 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
2363 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
2364 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
2365 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
2366         u8 tcp_flags;
2367 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
2368 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
2369 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
2370 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
2371 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
2372 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
2373 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
2374 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
2375 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
2376 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
2377 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
2378 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
2379 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
2380 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
2381 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
2382 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
2383         u8 ip_hlen_w;
2384         s8 reserved;
2385         __le16 total_hlen_w;
2386         __le16 tcp_pseudo_csum;
2387         __le16 lso_mss;
2388         __le16 ip_id;
2389         __le32 tcp_send_seq;
2390 };
2391
2392 /*
2393  * Tx parsing BD structure for ETH E2
2394  */
2395 struct eth_tx_parse_bd_e2 {
2396         __le16 dst_mac_addr_lo;
2397         __le16 dst_mac_addr_mid;
2398         __le16 dst_mac_addr_hi;
2399         __le16 src_mac_addr_lo;
2400         __le16 src_mac_addr_mid;
2401         __le16 src_mac_addr_hi;
2402         __le32 parsing_data;
2403 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
2404 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
2405 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
2406 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
2407 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
2408 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
2409 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
2410 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
2411 };
2412
2413 /*
2414  * The last BD in the BD memory will hold a pointer to the next BD memory
2415  */
2416 struct eth_tx_next_bd {
2417         __le32 addr_lo;
2418         __le32 addr_hi;
2419         u8 reserved[8];
2420 };
2421
2422 /*
2423  * union for 4 Bd types
2424  */
2425 union eth_tx_bd_types {
2426         struct eth_tx_start_bd start_bd;
2427         struct eth_tx_bd reg_bd;
2428         struct eth_tx_parse_bd_e1x parse_bd_e1x;
2429         struct eth_tx_parse_bd_e2 parse_bd_e2;
2430         struct eth_tx_next_bd next_bd;
2431 };
2432
2433
2434 /*
2435  * The eth storm context of Xstorm
2436  */
2437 struct xstorm_eth_st_context {
2438         u32 reserved0[60];
2439 };
2440
2441 /*
2442  * The eth storm context of Cstorm
2443  */
2444 struct cstorm_eth_st_context {
2445         u32 __reserved0[4];
2446 };
2447
2448 /*
2449  * Ethernet connection context
2450  */
2451 struct eth_context {
2452         struct ustorm_eth_st_context ustorm_st_context;
2453         struct tstorm_eth_st_context tstorm_st_context;
2454         struct xstorm_eth_ag_context xstorm_ag_context;
2455         struct tstorm_eth_ag_context tstorm_ag_context;
2456         struct cstorm_eth_ag_context cstorm_ag_context;
2457         struct ustorm_eth_ag_context ustorm_ag_context;
2458         struct timers_block_context timers_context;
2459         struct xstorm_eth_st_context xstorm_st_context;
2460         struct cstorm_eth_st_context cstorm_st_context;
2461 };
2462
2463
2464 /*
2465  * Ethernet doorbell
2466  */
2467 struct eth_tx_doorbell {
2468 #if defined(__BIG_ENDIAN)
2469         u16 npackets;
2470         u8 params;
2471 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2472 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2473 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2474 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2475 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2476 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2477         struct doorbell_hdr hdr;
2478 #elif defined(__LITTLE_ENDIAN)
2479         struct doorbell_hdr hdr;
2480         u8 params;
2481 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2482 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2483 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2484 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2485 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2486 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2487         u16 npackets;
2488 #endif
2489 };
2490
2491
2492 /*
2493  * client init fc data
2494  */
2495 struct client_init_fc_data {
2496         __le16 cqe_pause_thr_low;
2497         __le16 cqe_pause_thr_high;
2498         __le16 bd_pause_thr_low;
2499         __le16 bd_pause_thr_high;
2500         __le16 sge_pause_thr_low;
2501         __le16 sge_pause_thr_high;
2502         __le16 rx_cos_mask;
2503         u8 safc_group_num;
2504         u8 safc_group_en_flg;
2505         u8 traffic_type;
2506         u8 reserved0;
2507         __le16 reserved1;
2508         __le32 reserved2;
2509 };
2510
2511
2512 /*
2513  * client init ramrod data
2514  */
2515 struct client_init_general_data {
2516         u8 client_id;
2517         u8 statistics_counter_id;
2518         u8 statistics_en_flg;
2519         u8 is_fcoe_flg;
2520         u8 activate_flg;
2521         u8 sp_client_id;
2522         __le16 reserved0;
2523         __le32 reserved1[2];
2524 };
2525
2526
2527 /*
2528  * client init rx data
2529  */
2530 struct client_init_rx_data {
2531         u8 tpa_en_flg;
2532         u8 vmqueue_mode_en_flg;
2533         u8 extra_data_over_sgl_en_flg;
2534         u8 cache_line_alignment_log_size;
2535         u8 enable_dynamic_hc;
2536         u8 max_sges_for_packet;
2537         u8 client_qzone_id;
2538         u8 drop_ip_cs_err_flg;
2539         u8 drop_tcp_cs_err_flg;
2540         u8 drop_ttl0_flg;
2541         u8 drop_udp_cs_err_flg;
2542         u8 inner_vlan_removal_enable_flg;
2543         u8 outer_vlan_removal_enable_flg;
2544         u8 status_block_id;
2545         u8 rx_sb_index_number;
2546         u8 reserved0[3];
2547         __le16 bd_buff_size;
2548         __le16 sge_buff_size;
2549         __le16 mtu;
2550         struct regpair bd_page_base;
2551         struct regpair sge_page_base;
2552         struct regpair cqe_page_base;
2553         u8 is_leading_rss;
2554         u8 is_approx_mcast;
2555         __le16 max_agg_size;
2556         __le32 reserved2[3];
2557 };
2558
2559 /*
2560  * client init tx data
2561  */
2562 struct client_init_tx_data {
2563         u8 enforce_security_flg;
2564         u8 tx_status_block_id;
2565         u8 tx_sb_index_number;
2566         u8 reserved0;
2567         __le16 mtu;
2568         __le16 reserved1;
2569         struct regpair tx_bd_page_base;
2570         __le32 reserved2[2];
2571 };
2572
2573 /*
2574  * client init ramrod data
2575  */
2576 struct client_init_ramrod_data {
2577         struct client_init_general_data general;
2578         struct client_init_rx_data rx;
2579         struct client_init_tx_data tx;
2580         struct client_init_fc_data fc;
2581 };
2582
2583
2584 /*
2585  * The data contain client ID need to the ramrod
2586  */
2587 struct eth_common_ramrod_data {
2588         u32 client_id;
2589         u32 reserved1;
2590 };
2591
2592
2593 /*
2594  * union for sgl and raw data.
2595  */
2596 union eth_sgl_or_raw_data {
2597         __le16 sgl[8];
2598         u32 raw_data[4];
2599 };
2600
2601 /*
2602  * regular eth FP CQE parameters struct
2603  */
2604 struct eth_fast_path_rx_cqe {
2605         u8 type_error_flags;
2606 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2607 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2608 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2609 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2610 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2611 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2612 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2613 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2614 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2615 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2616 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2617 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2618 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x3<<6)
2619 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 6
2620         u8 status_flags;
2621 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2622 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2623 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2624 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2625 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2626 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2627 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2628 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2629 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2630 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2631 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2632 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2633         u8 placement_offset;
2634         u8 queue_index;
2635         __le32 rss_hash_result;
2636         __le16 vlan_tag;
2637         __le16 pkt_len;
2638         __le16 len_on_bd;
2639         struct parsing_flags pars_flags;
2640         union eth_sgl_or_raw_data sgl_or_raw_data;
2641 };
2642
2643
2644 /*
2645  * The data for RSS setup ramrod
2646  */
2647 struct eth_halt_ramrod_data {
2648         u32 client_id;
2649         u32 reserved0;
2650 };
2651
2652 /*
2653  * The data for statistics query ramrod
2654  */
2655 struct common_query_ramrod_data {
2656 #if defined(__BIG_ENDIAN)
2657         u8 reserved0;
2658         u8 collect_port;
2659         u16 drv_counter;
2660 #elif defined(__LITTLE_ENDIAN)
2661         u16 drv_counter;
2662         u8 collect_port;
2663         u8 reserved0;
2664 #endif
2665         u32 ctr_id_vector;
2666 };
2667
2668
2669 /*
2670  * Place holder for ramrods protocol specific data
2671  */
2672 struct ramrod_data {
2673         __le32 data_lo;
2674         __le32 data_hi;
2675 };
2676
2677 /*
2678  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2679  */
2680 union eth_ramrod_data {
2681         struct ramrod_data general;
2682 };
2683
2684
2685 /*
2686  * Eth Rx Cqe structure- general structure for ramrods
2687  */
2688 struct common_ramrod_eth_rx_cqe {
2689         u8 ramrod_type;
2690 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2691 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2692 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1)
2693 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1
2694 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2)
2695 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2
2696         u8 conn_type;
2697         __le16 reserved1;
2698         __le32 conn_and_cmd_data;
2699 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2700 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2701 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2702 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2703         struct ramrod_data protocol_data;
2704         __le32 reserved2[4];
2705 };
2706
2707 /*
2708  * Rx Last CQE in page (in ETH)
2709  */
2710 struct eth_rx_cqe_next_page {
2711         __le32 addr_lo;
2712         __le32 addr_hi;
2713         __le32 reserved[6];
2714 };
2715
2716 /*
2717  * union for all eth rx cqe types (fix their sizes)
2718  */
2719 union eth_rx_cqe {
2720         struct eth_fast_path_rx_cqe fast_path_cqe;
2721         struct common_ramrod_eth_rx_cqe ramrod_cqe;
2722         struct eth_rx_cqe_next_page next_page_cqe;
2723 };
2724
2725
2726 /*
2727  * common data for all protocols
2728  */
2729 struct spe_hdr {
2730         __le32 conn_and_cmd_data;
2731 #define SPE_HDR_CID (0xFFFFFF<<0)
2732 #define SPE_HDR_CID_SHIFT 0
2733 #define SPE_HDR_CMD_ID (0xFF<<24)
2734 #define SPE_HDR_CMD_ID_SHIFT 24
2735         __le16 type;
2736 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2737 #define SPE_HDR_CONN_TYPE_SHIFT 0
2738 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
2739 #define SPE_HDR_FUNCTION_ID_SHIFT 8
2740         __le16 reserved1;
2741 };
2742
2743 /*
2744  * Ethernet slow path element
2745  */
2746 union eth_specific_data {
2747         u8 protocol_data[8];
2748         struct regpair client_init_ramrod_init_data;
2749         struct eth_halt_ramrod_data halt_ramrod_data;
2750         struct regpair update_data_addr;
2751         struct eth_common_ramrod_data common_ramrod_data;
2752 };
2753
2754 /*
2755  * Ethernet slow path element
2756  */
2757 struct eth_spe {
2758         struct spe_hdr hdr;
2759         union eth_specific_data data;
2760 };
2761
2762
2763 /*
2764  * array of 13 bds as appears in the eth xstorm context
2765  */
2766 struct eth_tx_bds_array {
2767         union eth_tx_bd_types bds[13];
2768 };
2769
2770
2771 /*
2772  * Common configuration parameters per function in Tstorm
2773  */
2774 struct tstorm_eth_function_common_config {
2775 #if defined(__BIG_ENDIAN)
2776         u8 reserved1;
2777         u8 rss_result_mask;
2778         u16 config_flags;
2779 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2780 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2781 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2782 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2783 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2784 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2785 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2786 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2787 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2788 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2789 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2790 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2791 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2792 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2793 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2794 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2795 #elif defined(__LITTLE_ENDIAN)
2796         u16 config_flags;
2797 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2798 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2799 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2800 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2801 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2802 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2803 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2804 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2805 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2806 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2807 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2808 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2809 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2810 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2811 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2812 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2813         u8 rss_result_mask;
2814         u8 reserved1;
2815 #endif
2816         u16 vlan_id[2];
2817 };
2818
2819 /*
2820  * RSS idirection table update configuration
2821  */
2822 struct rss_update_config {
2823 #if defined(__BIG_ENDIAN)
2824         u16 toe_rss_bitmap;
2825         u16 flags;
2826 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2827 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2828 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2829 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2830 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2831 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2832 #elif defined(__LITTLE_ENDIAN)
2833         u16 flags;
2834 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2835 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2836 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2837 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2838 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2839 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2840         u16 toe_rss_bitmap;
2841 #endif
2842         u32 reserved1;
2843 };
2844
2845 /*
2846  * parameters for eth update ramrod
2847  */
2848 struct eth_update_ramrod_data {
2849         struct tstorm_eth_function_common_config func_config;
2850         u8 indirectionTable[128];
2851         struct rss_update_config rss_config;
2852 };
2853
2854
2855 /*
2856  * MAC filtering configuration command header
2857  */
2858 struct mac_configuration_hdr {
2859         u8 length;
2860         u8 offset;
2861         u16 client_id;
2862         u16 echo;
2863         u16 reserved1;
2864 };
2865
2866 /*
2867  * MAC address in list for ramrod
2868  */
2869 struct mac_configuration_entry {
2870         __le16 lsb_mac_addr;
2871         __le16 middle_mac_addr;
2872         __le16 msb_mac_addr;
2873         __le16 vlan_id;
2874         u8 pf_id;
2875         u8 flags;
2876 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
2877 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
2878 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
2879 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
2880 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
2881 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
2882 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
2883 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
2884 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
2885 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
2886 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
2887 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
2888         u16 reserved0;
2889         u32 clients_bit_vector;
2890 };
2891
2892 /*
2893  * MAC filtering configuration command
2894  */
2895 struct mac_configuration_cmd {
2896         struct mac_configuration_hdr hdr;
2897         struct mac_configuration_entry config_table[64];
2898 };
2899
2900
2901 /*
2902  * approximate-match multicast filtering for E1H per function in Tstorm
2903  */
2904 struct tstorm_eth_approximate_match_multicast_filtering {
2905         u32 mcast_add_hash_bit_array[8];
2906 };
2907
2908
2909 /*
2910  * MAC filtering configuration parameters per port in Tstorm
2911  */
2912 struct tstorm_eth_mac_filter_config {
2913         u32 ucast_drop_all;
2914         u32 ucast_accept_all;
2915         u32 mcast_drop_all;
2916         u32 mcast_accept_all;
2917         u32 bcast_drop_all;
2918         u32 bcast_accept_all;
2919         u32 vlan_filter[2];
2920         u32 unmatched_unicast;
2921         u32 reserved;
2922 };
2923
2924
2925 /*
2926  * common flag to indicate existance of TPA.
2927  */
2928 struct tstorm_eth_tpa_exist {
2929 #if defined(__BIG_ENDIAN)
2930         u16 reserved1;
2931         u8 reserved0;
2932         u8 tpa_exist;
2933 #elif defined(__LITTLE_ENDIAN)
2934         u8 tpa_exist;
2935         u8 reserved0;
2936         u16 reserved1;
2937 #endif
2938         u32 reserved2;
2939 };
2940
2941
2942 /*
2943  * Three RX producers for ETH
2944  */
2945 struct ustorm_eth_rx_producers {
2946 #if defined(__BIG_ENDIAN)
2947         u16 bd_prod;
2948         u16 cqe_prod;
2949 #elif defined(__LITTLE_ENDIAN)
2950         u16 cqe_prod;
2951         u16 bd_prod;
2952 #endif
2953 #if defined(__BIG_ENDIAN)
2954         u16 reserved;
2955         u16 sge_prod;
2956 #elif defined(__LITTLE_ENDIAN)
2957         u16 sge_prod;
2958         u16 reserved;
2959 #endif
2960 };
2961
2962
2963 /*
2964  * cfc delete event data
2965  */
2966 struct cfc_del_event_data {
2967         u32 cid;
2968         u8 error;
2969         u8 reserved0;
2970         u16 reserved1;
2971         u32 reserved2;
2972 };
2973
2974
2975 /*
2976  * per-port SAFC demo variables
2977  */
2978 struct cmng_flags_per_port {
2979         u8 con_number[NUM_OF_PROTOCOLS];
2980         u32 cmng_enables;
2981 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2982 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2983 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2984 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2985 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2986 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2987 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2988 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2989 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2990 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2991 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<5)
2992 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 5
2993 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x3FFFFFF<<6)
2994 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 6
2995 };
2996
2997
2998 /*
2999  * per-port rate shaping variables
3000  */
3001 struct rate_shaping_vars_per_port {
3002         u32 rs_periodic_timeout;
3003         u32 rs_threshold;
3004 };
3005
3006 /*
3007  * per-port fairness variables
3008  */
3009 struct fairness_vars_per_port {
3010         u32 upper_bound;
3011         u32 fair_threshold;
3012         u32 fairness_timeout;
3013 };
3014
3015 /*
3016  * per-port SAFC variables
3017  */
3018 struct safc_struct_per_port {
3019 #if defined(__BIG_ENDIAN)
3020         u16 __reserved1;
3021         u8 __reserved0;
3022         u8 safc_timeout_usec;
3023 #elif defined(__LITTLE_ENDIAN)
3024         u8 safc_timeout_usec;
3025         u8 __reserved0;
3026         u16 __reserved1;
3027 #endif
3028         u8 cos_to_traffic_types[MAX_COS_NUMBER];
3029         u32 __reserved2;
3030         u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
3031 };
3032
3033 /*
3034  * per-port PFC variables
3035  */
3036 struct pfc_struct_per_port {
3037         u8 priority_to_traffic_types[MAX_PFC_PRIORITIES];
3038 #if defined(__BIG_ENDIAN)
3039         u16 pfc_pause_quanta_in_nanosec;
3040         u8 __reserved0;
3041         u8 priority_non_pausable_mask;
3042 #elif defined(__LITTLE_ENDIAN)
3043         u8 priority_non_pausable_mask;
3044         u8 __reserved0;
3045         u16 pfc_pause_quanta_in_nanosec;
3046 #endif
3047 };
3048
3049 /*
3050  * Priority and cos
3051  */
3052 struct priority_cos {
3053 #if defined(__BIG_ENDIAN)
3054         u16 reserved1;
3055         u8 cos;
3056         u8 priority;
3057 #elif defined(__LITTLE_ENDIAN)
3058         u8 priority;
3059         u8 cos;
3060         u16 reserved1;
3061 #endif
3062         u32 reserved2;
3063 };
3064
3065 /*
3066  * Per-port congestion management variables
3067  */
3068 struct cmng_struct_per_port {
3069         struct rate_shaping_vars_per_port rs_vars;
3070         struct fairness_vars_per_port fair_vars;
3071         struct safc_struct_per_port safc_vars;
3072         struct pfc_struct_per_port pfc_vars;
3073 #if defined(__BIG_ENDIAN)
3074         u16 __reserved1;
3075         u8 dcb_enabled;
3076         u8 llfc_mode;
3077 #elif defined(__LITTLE_ENDIAN)
3078         u8 llfc_mode;
3079         u8 dcb_enabled;
3080         u16 __reserved1;
3081 #endif
3082         struct priority_cos
3083                 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
3084         struct cmng_flags_per_port flags;
3085 };
3086
3087
3088
3089 /*
3090  * Dynamic HC counters set by the driver
3091  */
3092 struct hc_dynamic_drv_counter {
3093         u32 val[HC_SB_MAX_DYNAMIC_INDICES];
3094 };
3095
3096 /*
3097  * zone A per-queue data
3098  */
3099 struct cstorm_queue_zone_data {
3100         struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
3101         struct regpair reserved[2];
3102 };
3103
3104 /*
3105  * Dynamic host coalescing init parameters
3106  */
3107 struct dynamic_hc_config {
3108         u32 threshold[3];
3109         u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
3110         u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
3111         u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
3112         u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
3113         u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
3114 };
3115
3116
3117 /*
3118  * Protocol-common statistics collected by the Xstorm (per client)
3119  */
3120 struct xstorm_per_client_stats {
3121         __le32 reserved0;
3122         __le32 unicast_pkts_sent;
3123         struct regpair unicast_bytes_sent;
3124         struct regpair multicast_bytes_sent;
3125         __le32 multicast_pkts_sent;
3126         __le32 broadcast_pkts_sent;
3127         struct regpair broadcast_bytes_sent;
3128         __le16 stats_counter;
3129         __le16 reserved1;
3130         __le32 reserved2;
3131 };
3132
3133 /*
3134  * Common statistics collected by the Xstorm (per port)
3135  */
3136 struct xstorm_common_stats {
3137         struct xstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3138 };
3139
3140 /*
3141  * Protocol-common statistics collected by the Tstorm (per port)
3142  */
3143 struct tstorm_per_port_stats {
3144         __le32 mac_filter_discard;
3145         __le32 xxoverflow_discard;
3146         __le32 brb_truncate_discard;
3147         __le32 mac_discard;
3148 };
3149
3150 /*
3151  * Protocol-common statistics collected by the Tstorm (per client)
3152  */
3153 struct tstorm_per_client_stats {
3154         struct regpair rcv_unicast_bytes;
3155         struct regpair rcv_broadcast_bytes;
3156         struct regpair rcv_multicast_bytes;
3157         struct regpair rcv_error_bytes;
3158         __le32 checksum_discard;
3159         __le32 packets_too_big_discard;
3160         __le32 rcv_unicast_pkts;
3161         __le32 rcv_broadcast_pkts;
3162         __le32 rcv_multicast_pkts;
3163         __le32 no_buff_discard;
3164         __le32 ttl0_discard;
3165         __le16 stats_counter;
3166         __le16 reserved0;
3167 };
3168
3169 /*
3170  * Protocol-common statistics collected by the Tstorm
3171  */
3172 struct tstorm_common_stats {
3173         struct tstorm_per_port_stats port_statistics;
3174         struct tstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3175 };
3176
3177 /*
3178  * Protocol-common statistics collected by the Ustorm (per client)
3179  */
3180 struct ustorm_per_client_stats {
3181         struct regpair ucast_no_buff_bytes;
3182         struct regpair mcast_no_buff_bytes;
3183         struct regpair bcast_no_buff_bytes;
3184         __le32 ucast_no_buff_pkts;
3185         __le32 mcast_no_buff_pkts;
3186         __le32 bcast_no_buff_pkts;
3187         __le16 stats_counter;
3188         __le16 reserved0;
3189 };
3190
3191 /*
3192  * Protocol-common statistics collected by the Ustorm
3193  */
3194 struct ustorm_common_stats {
3195         struct ustorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3196 };
3197
3198 /*
3199  * Eth statistics query structure for the eth_stats_query ramrod
3200  */
3201 struct eth_stats_query {
3202         struct xstorm_common_stats xstorm_common;
3203         struct tstorm_common_stats tstorm_common;
3204         struct ustorm_common_stats ustorm_common;
3205 };
3206
3207
3208 /*
3209  * set mac event data
3210  */
3211 struct set_mac_event_data {
3212         u16 echo;
3213         u16 reserved0;
3214         u32 reserved1;
3215         u32 reserved2;
3216 };
3217
3218 /*
3219  * union for all event ring message types
3220  */
3221 union event_data {
3222         struct set_mac_event_data set_mac_event;
3223         struct cfc_del_event_data cfc_del_event;
3224 };
3225
3226
3227 /*
3228  * per PF event ring data
3229  */
3230 struct event_ring_data {
3231         struct regpair base_addr;
3232 #if defined(__BIG_ENDIAN)
3233         u8 index_id;
3234         u8 sb_id;
3235         u16 producer;
3236 #elif defined(__LITTLE_ENDIAN)
3237         u16 producer;
3238         u8 sb_id;
3239         u8 index_id;
3240 #endif
3241         u32 reserved0;
3242 };
3243
3244
3245 /*
3246  * event ring message element (each element is 128 bits)
3247  */
3248 struct event_ring_msg {
3249         u8 opcode;
3250         u8 reserved0;
3251         u16 reserved1;
3252         union event_data data;
3253 };
3254
3255 /*
3256  * event ring next page element (128 bits)
3257  */
3258 struct event_ring_next {
3259         struct regpair addr;
3260         u32 reserved[2];
3261 };
3262
3263 /*
3264  * union for event ring element types (each element is 128 bits)
3265  */
3266 union event_ring_elem {
3267         struct event_ring_msg message;
3268         struct event_ring_next next_page;
3269 };
3270
3271
3272 /*
3273  * per-vnic fairness variables
3274  */
3275 struct fairness_vars_per_vn {
3276         u32 cos_credit_delta[MAX_COS_NUMBER];
3277         u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
3278         u32 vn_credit_delta;
3279         u32 __reserved0;
3280 };
3281
3282
3283 /*
3284  * The data for flow control configuration
3285  */
3286 struct flow_control_configuration {
3287         struct priority_cos
3288                 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
3289 #if defined(__BIG_ENDIAN)
3290         u16 reserved1;
3291         u8 dcb_version;
3292         u8 dcb_enabled;
3293 #elif defined(__LITTLE_ENDIAN)
3294         u8 dcb_enabled;
3295         u8 dcb_version;
3296         u16 reserved1;
3297 #endif
3298         u32 reserved2;
3299 };
3300
3301
3302 /*
3303  * FW version stored in the Xstorm RAM
3304  */
3305 struct fw_version {
3306 #if defined(__BIG_ENDIAN)
3307         u8 engineering;
3308         u8 revision;
3309         u8 minor;
3310         u8 major;
3311 #elif defined(__LITTLE_ENDIAN)
3312         u8 major;
3313         u8 minor;
3314         u8 revision;
3315         u8 engineering;
3316 #endif
3317         u32 flags;
3318 #define FW_VERSION_OPTIMIZED (0x1<<0)
3319 #define FW_VERSION_OPTIMIZED_SHIFT 0
3320 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
3321 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
3322 #define FW_VERSION_CHIP_VERSION (0x3<<2)
3323 #define FW_VERSION_CHIP_VERSION_SHIFT 2
3324 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
3325 #define __FW_VERSION_RESERVED_SHIFT 4
3326 };
3327
3328
3329 /*
3330  * Dynamic Host-Coalescing - Driver(host) counters
3331  */
3332 struct hc_dynamic_sb_drv_counters {
3333         u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
3334 };
3335
3336
3337 /*
3338  * 2 bytes. configuration/state parameters for a single protocol index
3339  */
3340 struct hc_index_data {
3341 #if defined(__BIG_ENDIAN)
3342         u8 flags;
3343 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3344 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3345 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3346 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3347 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3348 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3349 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3350 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3351         u8 timeout;
3352 #elif defined(__LITTLE_ENDIAN)
3353         u8 timeout;
3354         u8 flags;
3355 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3356 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3357 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3358 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3359 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3360 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3361 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3362 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3363 #endif
3364 };
3365
3366
3367 /*
3368  * HC state-machine
3369  */
3370 struct hc_status_block_sm {
3371 #if defined(__BIG_ENDIAN)
3372         u8 igu_seg_id;
3373         u8 igu_sb_id;
3374         u8 timer_value;
3375         u8 __flags;
3376 #elif defined(__LITTLE_ENDIAN)
3377         u8 __flags;
3378         u8 timer_value;
3379         u8 igu_sb_id;
3380         u8 igu_seg_id;
3381 #endif
3382         u32 time_to_expire;
3383 };
3384
3385 /*
3386  * hold PCI identification variables- used in various places in firmware
3387  */
3388 struct pci_entity {
3389 #if defined(__BIG_ENDIAN)
3390         u8 vf_valid;
3391         u8 vf_id;
3392         u8 vnic_id;
3393         u8 pf_id;
3394 #elif defined(__LITTLE_ENDIAN)
3395         u8 pf_id;
3396         u8 vnic_id;
3397         u8 vf_id;
3398         u8 vf_valid;
3399 #endif
3400 };
3401
3402 /*
3403  * The fast-path status block meta-data, common to all chips
3404  */
3405 struct hc_sb_data {
3406         struct regpair host_sb_addr;
3407         struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
3408         struct pci_entity p_func;
3409 #if defined(__BIG_ENDIAN)
3410         u8 rsrv0;
3411         u8 dhc_qzone_id;
3412         u8 __dynamic_hc_level;
3413         u8 same_igu_sb_1b;
3414 #elif defined(__LITTLE_ENDIAN)
3415         u8 same_igu_sb_1b;
3416         u8 __dynamic_hc_level;
3417         u8 dhc_qzone_id;
3418         u8 rsrv0;
3419 #endif
3420         struct regpair rsrv1[2];
3421 };
3422
3423
3424 /*
3425  * The fast-path status block meta-data
3426  */
3427 struct hc_sp_status_block_data {
3428         struct regpair host_sb_addr;
3429 #if defined(__BIG_ENDIAN)
3430         u16 rsrv;
3431         u8 igu_seg_id;
3432         u8 igu_sb_id;
3433 #elif defined(__LITTLE_ENDIAN)
3434         u8 igu_sb_id;
3435         u8 igu_seg_id;
3436         u16 rsrv;
3437 #endif
3438         struct pci_entity p_func;
3439 };
3440
3441
3442 /*
3443  * The fast-path status block meta-data
3444  */
3445 struct hc_status_block_data_e1x {
3446         struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
3447         struct hc_sb_data common;
3448 };
3449
3450
3451 /*
3452  * The fast-path status block meta-data
3453  */
3454 struct hc_status_block_data_e2 {
3455         struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
3456         struct hc_sb_data common;
3457 };
3458
3459
3460 /*
3461  * FW version stored in first line of pram
3462  */
3463 struct pram_fw_version {
3464         u8 major;
3465         u8 minor;
3466         u8 revision;
3467         u8 engineering;
3468         u8 flags;
3469 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
3470 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
3471 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
3472 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
3473 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
3474 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
3475 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
3476 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
3477 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
3478 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
3479 };
3480
3481
3482 /*
3483  * Ethernet slow path element
3484  */
3485 union protocol_common_specific_data {
3486         u8 protocol_data[8];
3487         struct regpair phy_address;
3488         struct regpair mac_config_addr;
3489         struct common_query_ramrod_data query_ramrod_data;
3490 };
3491
3492 /*
3493  * The send queue element
3494  */
3495 struct protocol_common_spe {
3496         struct spe_hdr hdr;
3497         union protocol_common_specific_data data;
3498 };
3499
3500
3501 /*
3502  * a single rate shaping counter. can be used as protocol or vnic counter
3503  */
3504 struct rate_shaping_counter {
3505         u32 quota;
3506 #if defined(__BIG_ENDIAN)
3507         u16 __reserved0;
3508         u16 rate;
3509 #elif defined(__LITTLE_ENDIAN)
3510         u16 rate;
3511         u16 __reserved0;
3512 #endif
3513 };
3514
3515
3516 /*
3517  * per-vnic rate shaping variables
3518  */
3519 struct rate_shaping_vars_per_vn {
3520         struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
3521         struct rate_shaping_counter vn_counter;
3522 };
3523
3524
3525 /*
3526  * The send queue element
3527  */
3528 struct slow_path_element {
3529         struct spe_hdr hdr;
3530         struct regpair protocol_data;
3531 };
3532
3533
3534 /*
3535  * eth/toe flags that indicate if to query
3536  */
3537 struct stats_indication_flags {
3538         u32 collect_eth;
3539         u32 collect_toe;
3540 };
3541
3542
3543 /*
3544  * per-port PFC variables
3545  */
3546 struct storm_pfc_struct_per_port {
3547 #if defined(__BIG_ENDIAN)
3548         u16 mid_mac_addr;
3549         u16 msb_mac_addr;
3550 #elif defined(__LITTLE_ENDIAN)
3551         u16 msb_mac_addr;
3552         u16 mid_mac_addr;
3553 #endif
3554 #if defined(__BIG_ENDIAN)
3555         u16 pfc_pause_quanta_in_nanosec;
3556         u16 lsb_mac_addr;
3557 #elif defined(__LITTLE_ENDIAN)
3558         u16 lsb_mac_addr;
3559         u16 pfc_pause_quanta_in_nanosec;
3560 #endif
3561 };
3562
3563 /*
3564  * Per-port congestion management variables
3565  */
3566 struct storm_cmng_struct_per_port {
3567         struct storm_pfc_struct_per_port pfc_vars;
3568 };
3569
3570
3571 /*
3572  * zone A per-queue data
3573  */
3574 struct tstorm_queue_zone_data {
3575         struct regpair reserved[4];
3576 };
3577
3578
3579 /*
3580  * zone B per-VF data
3581  */
3582 struct tstorm_vf_zone_data {
3583         struct regpair reserved;
3584 };
3585
3586
3587 /*
3588  * zone A per-queue data
3589  */
3590 struct ustorm_queue_zone_data {
3591         struct ustorm_eth_rx_producers eth_rx_producers;
3592         struct regpair reserved[3];
3593 };
3594
3595
3596 /*
3597  * zone B per-VF data
3598  */
3599 struct ustorm_vf_zone_data {
3600         struct regpair reserved;
3601 };
3602
3603
3604 /*
3605  * data per VF-PF channel
3606  */
3607 struct vf_pf_channel_data {
3608 #if defined(__BIG_ENDIAN)
3609         u16 reserved0;
3610         u8 valid;
3611         u8 state;
3612 #elif defined(__LITTLE_ENDIAN)
3613         u8 state;
3614         u8 valid;
3615         u16 reserved0;
3616 #endif
3617         u32 reserved1;
3618 };
3619
3620
3621 /*
3622  * zone A per-queue data
3623  */
3624 struct xstorm_queue_zone_data {
3625         struct regpair reserved[4];
3626 };
3627
3628
3629 /*
3630  * zone B per-VF data
3631  */
3632 struct xstorm_vf_zone_data {
3633         struct regpair reserved;
3634 };
3635
3636 #endif /* BNX2X_HSI_H */