[BNX2X]: Spelling fixes
[linux-2.6.git] / drivers / net / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Eliezer Tamir <eliezert@broadcom.com>
10  * Based on code from Michael Chan's bnx2 driver
11  */
12
13 #ifndef BNX2X_H
14 #define BNX2X_H
15
16 /* error/debug prints */
17
18 #define DRV_MODULE_NAME         "bnx2x"
19 #define PFX DRV_MODULE_NAME     ": "
20
21 /* for messages that are currently off */
22 #define BNX2X_MSG_OFF                   0
23 #define BNX2X_MSG_MCP                   0x10000 /* was: NETIF_MSG_HW */
24 #define BNX2X_MSG_STATS                 0x20000 /* was: NETIF_MSG_TIMER */
25 #define NETIF_MSG_NVM                   0x40000 /* was: NETIF_MSG_HW */
26 #define NETIF_MSG_DMAE                  0x80000 /* was: NETIF_MSG_HW */
27
28 #define DP_LEVEL                        KERN_NOTICE     /* was: KERN_DEBUG */
29
30 /* regular debug print */
31 #define DP(__mask, __fmt, __args...) do { \
32         if (bp->msglevel & (__mask)) \
33                 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
34                 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
35         } while (0)
36
37 /* for errors (never masked) */
38 #define BNX2X_ERR(__fmt, __args...) do { \
39         printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
40                 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
41         } while (0)
42
43 /* before we have a dev->name use dev_info() */
44 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
45         if (bp->msglevel & NETIF_MSG_PROBE) \
46                 dev_info(&bp->pdev->dev, __fmt, ##__args); \
47         } while (0)
48
49
50 #ifdef BNX2X_STOP_ON_ERROR
51 #define bnx2x_panic() do { \
52                 bp->panic = 1; \
53                 BNX2X_ERR("driver assert\n"); \
54                 bnx2x_disable_int(bp); \
55                 bnx2x_panic_dump(bp); \
56         } while (0)
57 #else
58 #define bnx2x_panic() do { \
59                 BNX2X_ERR("driver assert\n"); \
60                 bnx2x_panic_dump(bp); \
61         } while (0)
62 #endif
63
64
65 #define U64_LO(x)                       (((u64)x) & 0xffffffff)
66 #define U64_HI(x)                       (((u64)x) >> 32)
67 #define HILO_U64(hi, lo)                (((u64)hi << 32) + lo)
68
69
70 #define REG_ADDR(bp, offset)            (bp->regview + offset)
71
72 #define REG_RD(bp, offset)              readl(REG_ADDR(bp, offset))
73 #define REG_RD8(bp, offset)             readb(REG_ADDR(bp, offset))
74 #define REG_RD64(bp, offset)            readq(REG_ADDR(bp, offset))
75
76 #define REG_WR(bp, offset, val)         writel((u32)val, REG_ADDR(bp, offset))
77 #define REG_WR8(bp, offset, val)        writeb((u8)val, REG_ADDR(bp, offset))
78 #define REG_WR16(bp, offset, val)       writew((u16)val, REG_ADDR(bp, offset))
79 #define REG_WR32(bp, offset, val)       REG_WR(bp, offset, val)
80
81 #define REG_RD_IND(bp, offset)          bnx2x_reg_rd_ind(bp, offset)
82 #define REG_WR_IND(bp, offset, val)     bnx2x_reg_wr_ind(bp, offset, val)
83
84 #define REG_WR_DMAE(bp, offset, val, len32) \
85         do { \
86                 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
87                 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
88                                  offset, len32); \
89         } while (0)
90
91 #define SHMEM_RD(bp, type) \
92         REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))
93 #define SHMEM_WR(bp, type, val) \
94         REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)
95
96 #define NIG_WR(reg, val)        REG_WR(bp, reg, val)
97 #define EMAC_WR(reg, val)       REG_WR(bp, emac_base + reg, val)
98 #define BMAC_WR(reg, val)       REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
99
100
101 #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
102
103 #define for_each_nondefault_queue(bp, var) \
104                                 for (var = 1; var < bp->num_queues; var++)
105 #define is_multi(bp)            (bp->num_queues > 1)
106
107
108 struct regp {
109         u32 lo;
110         u32 hi;
111 };
112
113 struct bmac_stats {
114         struct regp tx_gtpkt;
115         struct regp tx_gtxpf;
116         struct regp tx_gtfcs;
117         struct regp tx_gtmca;
118         struct regp tx_gtgca;
119         struct regp tx_gtfrg;
120         struct regp tx_gtovr;
121         struct regp tx_gt64;
122         struct regp tx_gt127;
123         struct regp tx_gt255;   /* 10 */
124         struct regp tx_gt511;
125         struct regp tx_gt1023;
126         struct regp tx_gt1518;
127         struct regp tx_gt2047;
128         struct regp tx_gt4095;
129         struct regp tx_gt9216;
130         struct regp tx_gt16383;
131         struct regp tx_gtmax;
132         struct regp tx_gtufl;
133         struct regp tx_gterr;   /* 20 */
134         struct regp tx_gtbyt;
135
136         struct regp rx_gr64;
137         struct regp rx_gr127;
138         struct regp rx_gr255;
139         struct regp rx_gr511;
140         struct regp rx_gr1023;
141         struct regp rx_gr1518;
142         struct regp rx_gr2047;
143         struct regp rx_gr4095;
144         struct regp rx_gr9216;  /* 30 */
145         struct regp rx_gr16383;
146         struct regp rx_grmax;
147         struct regp rx_grpkt;
148         struct regp rx_grfcs;
149         struct regp rx_grmca;
150         struct regp rx_grbca;
151         struct regp rx_grxcf;
152         struct regp rx_grxpf;
153         struct regp rx_grxuo;
154         struct regp rx_grjbr;   /* 40 */
155         struct regp rx_grovr;
156         struct regp rx_grflr;
157         struct regp rx_grmeg;
158         struct regp rx_grmeb;
159         struct regp rx_grbyt;
160         struct regp rx_grund;
161         struct regp rx_grfrg;
162         struct regp rx_grerb;
163         struct regp rx_grfre;
164         struct regp rx_gripj;   /* 50 */
165 };
166
167 struct emac_stats {
168         u32 rx_ifhcinoctets                        ;
169         u32 rx_ifhcinbadoctets                     ;
170         u32 rx_etherstatsfragments                 ;
171         u32 rx_ifhcinucastpkts                     ;
172         u32 rx_ifhcinmulticastpkts                 ;
173         u32 rx_ifhcinbroadcastpkts                 ;
174         u32 rx_dot3statsfcserrors                  ;
175         u32 rx_dot3statsalignmenterrors            ;
176         u32 rx_dot3statscarriersenseerrors         ;
177         u32 rx_xonpauseframesreceived              ;    /* 10 */
178         u32 rx_xoffpauseframesreceived             ;
179         u32 rx_maccontrolframesreceived            ;
180         u32 rx_xoffstateentered                    ;
181         u32 rx_dot3statsframestoolong              ;
182         u32 rx_etherstatsjabbers                   ;
183         u32 rx_etherstatsundersizepkts             ;
184         u32 rx_etherstatspkts64octets              ;
185         u32 rx_etherstatspkts65octetsto127octets   ;
186         u32 rx_etherstatspkts128octetsto255octets  ;
187         u32 rx_etherstatspkts256octetsto511octets  ;    /* 20 */
188         u32 rx_etherstatspkts512octetsto1023octets ;
189         u32 rx_etherstatspkts1024octetsto1522octets;
190         u32 rx_etherstatspktsover1522octets        ;
191
192         u32 rx_falsecarriererrors                  ;
193
194         u32 tx_ifhcoutoctets                       ;
195         u32 tx_ifhcoutbadoctets                    ;
196         u32 tx_etherstatscollisions                ;
197         u32 tx_outxonsent                          ;
198         u32 tx_outxoffsent                         ;
199         u32 tx_flowcontroldone                     ;    /* 30 */
200         u32 tx_dot3statssinglecollisionframes      ;
201         u32 tx_dot3statsmultiplecollisionframes    ;
202         u32 tx_dot3statsdeferredtransmissions      ;
203         u32 tx_dot3statsexcessivecollisions        ;
204         u32 tx_dot3statslatecollisions             ;
205         u32 tx_ifhcoutucastpkts                    ;
206         u32 tx_ifhcoutmulticastpkts                ;
207         u32 tx_ifhcoutbroadcastpkts                ;
208         u32 tx_etherstatspkts64octets              ;
209         u32 tx_etherstatspkts65octetsto127octets   ;    /* 40 */
210         u32 tx_etherstatspkts128octetsto255octets  ;
211         u32 tx_etherstatspkts256octetsto511octets  ;
212         u32 tx_etherstatspkts512octetsto1023octets ;
213         u32 tx_etherstatspkts1024octetsto1522octet ;
214         u32 tx_etherstatspktsover1522octets        ;
215         u32 tx_dot3statsinternalmactransmiterrors  ;    /* 46 */
216 };
217
218 union mac_stats {
219         struct emac_stats emac;
220         struct bmac_stats bmac;
221 };
222
223 struct nig_stats {
224         u32 brb_discard;
225         u32 brb_packet;
226         u32 brb_truncate;
227         u32 flow_ctrl_discard;
228         u32 flow_ctrl_octets;
229         u32 flow_ctrl_packet;
230         u32 mng_discard;
231         u32 mng_octet_inp;
232         u32 mng_octet_out;
233         u32 mng_packet_inp;
234         u32 mng_packet_out;
235         u32 pbf_octets;
236         u32 pbf_packet;
237         u32 safc_inp;
238         u32 done;
239         u32 pad;
240 };
241
242 struct bnx2x_eth_stats {
243         u32 pad;        /* to make long counters u64 aligned */
244         u32 mac_stx_start;
245         u32 total_bytes_received_hi;
246         u32 total_bytes_received_lo;
247         u32 total_bytes_transmitted_hi;
248         u32 total_bytes_transmitted_lo;
249         u32 total_unicast_packets_received_hi;
250         u32 total_unicast_packets_received_lo;
251         u32 total_multicast_packets_received_hi;
252         u32 total_multicast_packets_received_lo;
253         u32 total_broadcast_packets_received_hi;
254         u32 total_broadcast_packets_received_lo;
255         u32 total_unicast_packets_transmitted_hi;
256         u32 total_unicast_packets_transmitted_lo;
257         u32 total_multicast_packets_transmitted_hi;
258         u32 total_multicast_packets_transmitted_lo;
259         u32 total_broadcast_packets_transmitted_hi;
260         u32 total_broadcast_packets_transmitted_lo;
261         u32 crc_receive_errors;
262         u32 alignment_errors;
263         u32 false_carrier_detections;
264         u32 runt_packets_received;
265         u32 jabber_packets_received;
266         u32 pause_xon_frames_received;
267         u32 pause_xoff_frames_received;
268         u32 pause_xon_frames_transmitted;
269         u32 pause_xoff_frames_transmitted;
270         u32 single_collision_transmit_frames;
271         u32 multiple_collision_transmit_frames;
272         u32 late_collision_frames;
273         u32 excessive_collision_frames;
274         u32 control_frames_received;
275         u32 frames_received_64_bytes;
276         u32 frames_received_65_127_bytes;
277         u32 frames_received_128_255_bytes;
278         u32 frames_received_256_511_bytes;
279         u32 frames_received_512_1023_bytes;
280         u32 frames_received_1024_1522_bytes;
281         u32 frames_received_1523_9022_bytes;
282         u32 frames_transmitted_64_bytes;
283         u32 frames_transmitted_65_127_bytes;
284         u32 frames_transmitted_128_255_bytes;
285         u32 frames_transmitted_256_511_bytes;
286         u32 frames_transmitted_512_1023_bytes;
287         u32 frames_transmitted_1024_1522_bytes;
288         u32 frames_transmitted_1523_9022_bytes;
289         u32 valid_bytes_received_hi;
290         u32 valid_bytes_received_lo;
291         u32 error_runt_packets_received;
292         u32 error_jabber_packets_received;
293         u32 mac_stx_end;
294
295         u32 pad2;
296         u32 stat_IfHCInBadOctets_hi;
297         u32 stat_IfHCInBadOctets_lo;
298         u32 stat_IfHCOutBadOctets_hi;
299         u32 stat_IfHCOutBadOctets_lo;
300         u32 stat_Dot3statsFramesTooLong;
301         u32 stat_Dot3statsInternalMacTransmitErrors;
302         u32 stat_Dot3StatsCarrierSenseErrors;
303         u32 stat_Dot3StatsDeferredTransmissions;
304         u32 stat_FlowControlDone;
305         u32 stat_XoffStateEntered;
306
307         u32 x_total_sent_bytes_hi;
308         u32 x_total_sent_bytes_lo;
309         u32 x_total_sent_pkts;
310
311         u32 t_rcv_unicast_bytes_hi;
312         u32 t_rcv_unicast_bytes_lo;
313         u32 t_rcv_broadcast_bytes_hi;
314         u32 t_rcv_broadcast_bytes_lo;
315         u32 t_rcv_multicast_bytes_hi;
316         u32 t_rcv_multicast_bytes_lo;
317         u32 t_total_rcv_pkt;
318
319         u32 checksum_discard;
320         u32 packets_too_big_discard;
321         u32 no_buff_discard;
322         u32 ttl0_discard;
323         u32 mac_discard;
324         u32 mac_filter_discard;
325         u32 xxoverflow_discard;
326         u32 brb_truncate_discard;
327
328         u32 brb_discard;
329         u32 brb_packet;
330         u32 brb_truncate;
331         u32 flow_ctrl_discard;
332         u32 flow_ctrl_octets;
333         u32 flow_ctrl_packet;
334         u32 mng_discard;
335         u32 mng_octet_inp;
336         u32 mng_octet_out;
337         u32 mng_packet_inp;
338         u32 mng_packet_out;
339         u32 pbf_octets;
340         u32 pbf_packet;
341         u32 safc_inp;
342         u32 driver_xoff;
343         u32 number_of_bugs_found_in_stats_spec; /* just kidding */
344 };
345
346 #define MAC_STX_NA                      0xffffffff
347
348 #ifdef BNX2X_MULTI
349 #define MAX_CONTEXT                     16
350 #else
351 #define MAX_CONTEXT                     1
352 #endif
353
354 union cdu_context {
355         struct eth_context eth;
356         char pad[1024];
357 };
358
359 #define MAX_DMAE_C                      5
360
361 /* DMA memory not used in fastpath */
362 struct bnx2x_slowpath {
363         union cdu_context               context[MAX_CONTEXT];
364         struct eth_stats_query          fw_stats;
365         struct mac_configuration_cmd    mac_config;
366         struct mac_configuration_cmd    mcast_config;
367
368         /* used by dmae command executer */
369         struct dmae_command             dmae[MAX_DMAE_C];
370
371         union mac_stats                 mac_stats;
372         struct nig_stats                nig;
373         struct bnx2x_eth_stats          eth_stats;
374
375         u32                             wb_comp;
376 #define BNX2X_WB_COMP_VAL               0xe0d0d0ae
377         u32                             wb_data[4];
378 };
379
380 #define bnx2x_sp(bp, var)               (&bp->slowpath->var)
381 #define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
382 #define bnx2x_sp_mapping(bp, var) \
383                 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
384
385
386 struct sw_rx_bd {
387         struct sk_buff  *skb;
388         DECLARE_PCI_UNMAP_ADDR(mapping)
389 };
390
391 struct sw_tx_bd {
392         struct sk_buff  *skb;
393         u16             first_bd;
394 };
395
396 struct bnx2x_fastpath {
397
398         struct napi_struct      napi;
399
400         struct host_status_block *status_blk;
401         dma_addr_t              status_blk_mapping;
402
403         struct eth_tx_db_data   *hw_tx_prods;
404         dma_addr_t              tx_prods_mapping;
405
406         struct sw_tx_bd         *tx_buf_ring;
407
408         struct eth_tx_bd        *tx_desc_ring;
409         dma_addr_t              tx_desc_mapping;
410
411         struct sw_rx_bd         *rx_buf_ring;
412
413         struct eth_rx_bd        *rx_desc_ring;
414         dma_addr_t              rx_desc_mapping;
415
416         union eth_rx_cqe        *rx_comp_ring;
417         dma_addr_t              rx_comp_mapping;
418
419         int                     state;
420 #define BNX2X_FP_STATE_CLOSED           0
421 #define BNX2X_FP_STATE_IRQ              0x80000
422 #define BNX2X_FP_STATE_OPENING          0x90000
423 #define BNX2X_FP_STATE_OPEN             0xa0000
424 #define BNX2X_FP_STATE_HALTING          0xb0000
425 #define BNX2X_FP_STATE_HALTED           0xc0000
426 #define BNX2X_FP_STATE_DELETED          0xd0000
427 #define BNX2X_FP_STATE_CLOSE_IRQ        0xe0000
428
429         int                     index;
430
431         u16                     tx_pkt_prod;
432         u16                     tx_pkt_cons;
433         u16                     tx_bd_prod;
434         u16                     tx_bd_cons;
435         u16                     *tx_cons_sb;
436
437         u16                     fp_c_idx;
438         u16                     fp_u_idx;
439
440         u16                     rx_bd_prod;
441         u16                     rx_bd_cons;
442         u16                     rx_comp_prod;
443         u16                     rx_comp_cons;
444         u16                     *rx_cons_sb;
445
446         unsigned long           tx_pkt,
447                                 rx_pkt,
448                                 rx_calls;
449
450         struct bnx2x            *bp; /* parent */
451 };
452
453 #define bnx2x_fp(bp, nr, var)           (bp->fp[nr].var)
454
455
456 /* attn group wiring */
457 #define MAX_DYNAMIC_ATTN_GRPS           8
458
459 struct attn_route {
460         u32     sig[4];
461 };
462
463 struct bnx2x {
464         /* Fields used in the tx and intr/napi performance paths
465          * are grouped together in the beginning of the structure
466          */
467         struct bnx2x_fastpath   *fp;
468         void __iomem            *regview;
469         void __iomem            *doorbells;
470
471         struct net_device       *dev;
472         struct pci_dev          *pdev;
473
474         atomic_t                intr_sem;
475         struct msix_entry       msix_table[MAX_CONTEXT+1];
476
477         int                     tx_ring_size;
478
479 #ifdef BCM_VLAN
480         struct vlan_group       *vlgrp;
481 #endif
482
483         u32                     rx_csum;
484         u32                     rx_offset;
485         u32                     rx_buf_use_size;        /* useable size */
486         u32                     rx_buf_size;            /* with alignment */
487 #define ETH_OVREHEAD                    (ETH_HLEN + 8)  /* 8 for CRC + VLAN */
488 #define ETH_MIN_PACKET_SIZE             60
489 #define ETH_MAX_PACKET_SIZE             1500
490 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
491
492         struct host_def_status_block *def_status_blk;
493 #define DEF_SB_ID               16
494         u16                     def_c_idx;
495         u16                     def_u_idx;
496         u16                     def_t_idx;
497         u16                     def_x_idx;
498         u16                     def_att_idx;
499         u32                     attn_state;
500         struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
501         u32                     aeu_mask;
502         u32                     nig_mask;
503
504         /* slow path ring */
505         struct eth_spe          *spq;
506         dma_addr_t              spq_mapping;
507         u16                     spq_prod_idx;
508         u16                     dsb_sp_prod_idx;
509         struct eth_spe          *spq_prod_bd;
510         struct eth_spe          *spq_last_bd;
511         u16                     *dsb_sp_prod;
512         u16                     spq_left; /* serialize spq */
513         spinlock_t              spq_lock;
514
515         /* Flag for marking that there is either
516          * STAT_QUERY or CFC DELETE ramrod pending
517          */
518         u8                      stat_pending;
519
520         /* End of fields used in the performance code paths */
521
522         int                     panic;
523         int                     msglevel;
524
525         u32                     flags;
526 #define PCIX_FLAG                       1
527 #define PCI_32BIT_FLAG                  2
528 #define ONE_TDMA_FLAG                   4       /* no longer used */
529 #define NO_WOL_FLAG                     8
530 #define USING_DAC_FLAG                  0x10
531 #define USING_MSIX_FLAG                 0x20
532 #define ASF_ENABLE_FLAG                 0x40
533
534         int                     port;
535
536         int                     pm_cap;
537         int                     pcie_cap;
538
539         /* Used to synchronize phy accesses */
540         spinlock_t              phy_lock;
541
542         struct work_struct      reset_task;
543         u16                     in_reset_task;
544
545         struct work_struct      sp_task;
546
547         struct timer_list       timer;
548         int                     timer_interval;
549         int                     current_interval;
550
551         u32                     shmem_base;
552
553         u32                     chip_id;
554 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
555 #define CHIP_ID(bp)                     (((bp)->chip_id) & 0xfffffff0)
556
557 #define CHIP_NUM(bp)                    (((bp)->chip_id) & 0xffff0000)
558 #define CHIP_NUM_5710                   0x57100000
559
560 #define CHIP_REV(bp)                    (((bp)->chip_id) & 0x0000f000)
561 #define CHIP_REV_Ax                     0x00000000
562 #define CHIP_REV_Bx                     0x00001000
563 #define CHIP_REV_Cx                     0x00002000
564 #define CHIP_REV_EMUL                   0x0000e000
565 #define CHIP_REV_FPGA                   0x0000f000
566 #define CHIP_REV_IS_SLOW(bp)            ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
567                                          (CHIP_REV(bp) == CHIP_REV_FPGA))
568
569 #define CHIP_METAL(bp)                  (((bp)->chip_id) & 0x00000ff0)
570 #define CHIP_BOND_ID(bp)                (((bp)->chip_id) & 0x0000000f)
571
572         u16                     fw_seq;
573         u16                     fw_drv_pulse_wr_seq;
574         u32                     fw_mb;
575
576         u32                     hw_config;
577         u32                     serdes_config;
578         u32                     lane_config;
579         u32                     ext_phy_config;
580 #define XGXS_EXT_PHY_TYPE(bp)           (bp->ext_phy_config & \
581                                          PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
582 #define SERDES_EXT_PHY_TYPE(bp)         (bp->ext_phy_config & \
583                                          PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
584
585         u32                     speed_cap_mask;
586         u32                     link_config;
587 #define SWITCH_CFG_1G                   PORT_FEATURE_CON_SWITCH_1G_SWITCH
588 #define SWITCH_CFG_10G                  PORT_FEATURE_CON_SWITCH_10G_SWITCH
589 #define SWITCH_CFG_AUTO_DETECT          PORT_FEATURE_CON_SWITCH_AUTO_DETECT
590 #define SWITCH_CFG_ONE_TIME_DETECT      \
591                                 PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
592
593         u8                      ser_lane;
594         u8                      rx_lane_swap;
595         u8                      tx_lane_swap;
596
597         u8                      link_up;
598
599         u32                     supported;
600 /* link settings - missing defines */
601 #define SUPPORTED_2500baseT_Full        (1 << 15)
602 #define SUPPORTED_CX4                   (1 << 16)
603
604         u32                     phy_flags;
605 /*#define PHY_SERDES_FLAG                       0x1*/
606 #define PHY_BMAC_FLAG                   0x2
607 #define PHY_EMAC_FLAG                   0x4
608 #define PHY_XGXS_FLAG                   0x8
609 #define PHY_SGMII_FLAG                  0x10
610 #define PHY_INT_MODE_MASK_FLAG          0x300
611 #define PHY_INT_MODE_AUTO_POLLING_FLAG  0x100
612 #define PHY_INT_MODE_LINK_READY_FLAG    0x200
613
614         u32                     phy_addr;
615         u32                     phy_id;
616
617         u32                     autoneg;
618 #define AUTONEG_CL37                    SHARED_HW_CFG_AN_ENABLE_CL37
619 #define AUTONEG_CL73                    SHARED_HW_CFG_AN_ENABLE_CL73
620 #define AUTONEG_BAM                     SHARED_HW_CFG_AN_ENABLE_BAM
621 #define AUTONEG_PARALLEL                \
622                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
623 #define AUTONEG_SGMII_FIBER_AUTODET     \
624                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
625 #define AUTONEG_REMOTE_PHY              SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
626
627         u32                     req_autoneg;
628 #define AUTONEG_SPEED                   0x1
629 #define AUTONEG_FLOW_CTRL               0x2
630
631         u32                     req_line_speed;
632 /* link settings - missing defines */
633 #define SPEED_12000                     12000
634 #define SPEED_12500                     12500
635 #define SPEED_13000                     13000
636 #define SPEED_15000                     15000
637 #define SPEED_16000                     16000
638
639         u32                     req_duplex;
640         u32                     req_flow_ctrl;
641 #define FLOW_CTRL_AUTO                  PORT_FEATURE_FLOW_CONTROL_AUTO
642 #define FLOW_CTRL_TX                    PORT_FEATURE_FLOW_CONTROL_TX
643 #define FLOW_CTRL_RX                    PORT_FEATURE_FLOW_CONTROL_RX
644 #define FLOW_CTRL_BOTH                  PORT_FEATURE_FLOW_CONTROL_BOTH
645 #define FLOW_CTRL_NONE                  PORT_FEATURE_FLOW_CONTROL_NONE
646
647         u32                     pause_mode;
648 #define PAUSE_NONE                      0
649 #define PAUSE_SYMMETRIC                 1
650 #define PAUSE_ASYMMETRIC                2
651 #define PAUSE_BOTH                      3
652
653         u32                     advertising;
654 /* link settings - missing defines */
655 #define ADVERTISED_2500baseT_Full       (1 << 15)
656 #define ADVERTISED_CX4                  (1 << 16)
657
658         u32                     link_status;
659         u32                     line_speed;
660         u32                     duplex;
661         u32                     flow_ctrl;
662
663         u32                     bc_ver;
664
665         int                     flash_size;
666 #define NVRAM_1MB_SIZE                  0x20000 /* 1M bit in bytes */
667 #define NVRAM_TIMEOUT_COUNT             30000
668 #define NVRAM_PAGE_SIZE                 256
669
670         int                     rx_ring_size;
671
672         u16                     tx_quick_cons_trip_int;
673         u16                     tx_quick_cons_trip;
674         u16                     tx_ticks_int;
675         u16                     tx_ticks;
676
677         u16                     rx_quick_cons_trip_int;
678         u16                     rx_quick_cons_trip;
679         u16                     rx_ticks_int;
680         u16                     rx_ticks;
681
682         u32                     stats_ticks;
683
684         int                     state;
685 #define BNX2X_STATE_CLOSED              0x0
686 #define BNX2X_STATE_OPENING_WAIT4_LOAD  0x1000
687 #define BNX2X_STATE_OPENING_WAIT4_PORT  0x2000
688 #define BNX2X_STATE_OPEN                0x3000
689 #define BNX2X_STATE_CLOSING_WAIT4_HALT  0x4000
690 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
691 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
692 #define BNX2X_STATE_ERROR               0xF000
693
694         int                     num_queues;
695
696         u32                     rx_mode;
697 #define BNX2X_RX_MODE_NONE              0
698 #define BNX2X_RX_MODE_NORMAL            1
699 #define BNX2X_RX_MODE_ALLMULTI          2
700 #define BNX2X_RX_MODE_PROMISC           3
701 #define BNX2X_MAX_MULTICAST             64
702 #define BNX2X_MAX_EMUL_MULTI            16
703
704         dma_addr_t              def_status_blk_mapping;
705
706         struct bnx2x_slowpath   *slowpath;
707         dma_addr_t              slowpath_mapping;
708
709 #ifdef BCM_ISCSI
710         void                    *t1;
711         dma_addr_t              t1_mapping;
712         void                    *t2;
713         dma_addr_t              t2_mapping;
714         void                    *timers;
715         dma_addr_t              timers_mapping;
716         void                    *qm;
717         dma_addr_t              qm_mapping;
718 #endif
719
720         char                    *name;
721         u16                     bus_speed_mhz;
722         u8                      wol;
723         u8                      pad;
724
725         /* used to synchronize stats collecting */
726         int                     stats_state;
727 #define STATS_STATE_DISABLE             0
728 #define STATS_STATE_ENABLE              1
729 #define STATS_STATE_STOP                2 /* stop stats on next iteration */
730
731         /* used by dmae command loader */
732         struct dmae_command     dmae;
733         int                     executer_idx;
734
735         u32                     old_brb_discard;
736         struct bmac_stats       old_bmac;
737         struct tstorm_per_client_stats old_tclient;
738         struct z_stream_s       *strm;
739         void                    *gunzip_buf;
740         dma_addr_t              gunzip_mapping;
741         int                     gunzip_outlen;
742 #define FW_BUF_SIZE                     0x8000
743
744 };
745
746
747 /* DMAE command defines */
748 #define DMAE_CMD_SRC_PCI                0
749 #define DMAE_CMD_SRC_GRC                DMAE_COMMAND_SRC
750
751 #define DMAE_CMD_DST_PCI                (1 << DMAE_COMMAND_DST_SHIFT)
752 #define DMAE_CMD_DST_GRC                (2 << DMAE_COMMAND_DST_SHIFT)
753
754 #define DMAE_CMD_C_DST_PCI              0
755 #define DMAE_CMD_C_DST_GRC              (1 << DMAE_COMMAND_C_DST_SHIFT)
756
757 #define DMAE_CMD_C_ENABLE               DMAE_COMMAND_C_TYPE_ENABLE
758
759 #define DMAE_CMD_ENDIANITY_NO_SWAP      (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
760 #define DMAE_CMD_ENDIANITY_B_SWAP       (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
761 #define DMAE_CMD_ENDIANITY_DW_SWAP      (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
762 #define DMAE_CMD_ENDIANITY_B_DW_SWAP    (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
763
764 #define DMAE_CMD_PORT_0                 0
765 #define DMAE_CMD_PORT_1                 DMAE_COMMAND_PORT
766
767 #define DMAE_CMD_SRC_RESET              DMAE_COMMAND_SRC_RESET
768 #define DMAE_CMD_DST_RESET              DMAE_COMMAND_DST_RESET
769
770 #define DMAE_LEN32_MAX                  0x400
771
772
773 /* MC hsi */
774 #define RX_COPY_THRESH                  92
775 #define BCM_PAGE_BITS                   12
776 #define BCM_PAGE_SIZE                   (1 << BCM_PAGE_BITS)
777
778 #define NUM_TX_RINGS                    16
779 #define TX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
780 #define MAX_TX_DESC_CNT                 (TX_DESC_CNT - 1)
781 #define NUM_TX_BD                       (TX_DESC_CNT * NUM_TX_RINGS)
782 #define MAX_TX_BD                       (NUM_TX_BD - 1)
783 #define MAX_TX_AVAIL                    (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
784 #define NEXT_TX_IDX(x)          ((((x) & MAX_TX_DESC_CNT) == \
785                                  (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
786 #define TX_BD(x)                        ((x) & MAX_TX_BD)
787 #define TX_BD_POFF(x)                   ((x) & MAX_TX_DESC_CNT)
788
789 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
790 #define NUM_RX_RINGS                    8
791 #define RX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
792 #define MAX_RX_DESC_CNT                 (RX_DESC_CNT - 2)
793 #define RX_DESC_MASK                    (RX_DESC_CNT - 1)
794 #define NUM_RX_BD                       (RX_DESC_CNT * NUM_RX_RINGS)
795 #define MAX_RX_BD                       (NUM_RX_BD - 1)
796 #define MAX_RX_AVAIL                    (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
797 #define NEXT_RX_IDX(x)          ((((x) & RX_DESC_MASK) == \
798                                  (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
799 #define RX_BD(x)                        ((x) & MAX_RX_BD)
800
801 #define NUM_RCQ_RINGS                   (NUM_RX_RINGS * 2)
802 #define RCQ_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
803 #define MAX_RCQ_DESC_CNT                (RCQ_DESC_CNT - 1)
804 #define NUM_RCQ_BD                      (RCQ_DESC_CNT * NUM_RCQ_RINGS)
805 #define MAX_RCQ_BD                      (NUM_RCQ_BD - 1)
806 #define MAX_RCQ_AVAIL                   (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
807 #define NEXT_RCQ_IDX(x)         ((((x) & MAX_RCQ_DESC_CNT) == \
808                                  (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
809 #define RCQ_BD(x)                       ((x) & MAX_RCQ_BD)
810
811
812 /* used on a CID received from the HW */
813 #define SW_CID(x)                       (le32_to_cpu(x) & \
814                                          (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
815 #define CQE_CMD(x)                      (le32_to_cpu(x) >> \
816                                         COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
817
818 #define BD_UNMAP_ADDR(bd)               HILO_U64(le32_to_cpu((bd)->addr_hi), \
819                                                  le32_to_cpu((bd)->addr_lo))
820 #define BD_UNMAP_LEN(bd)                (le16_to_cpu((bd)->nbytes))
821
822
823 #define STROM_ASSERT_ARRAY_SIZE         50
824
825
826 #define MDIO_INDIRECT_REG_ADDR          0x1f
827 #define MDIO_SET_REG_BANK(bp, reg_bank) \
828                 bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
829
830 #define MDIO_ACCESS_TIMEOUT             1000
831
832
833 /* must be used on a CID before placing it on a HW ring */
834 #define HW_CID(bp, x)                   (x | (bp->port << 23))
835
836 #define SP_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_spe))
837 #define MAX_SP_DESC_CNT                 (SP_DESC_CNT - 1)
838
839 #define ATTN_NIG_FOR_FUNC               (1L << 8)
840 #define ATTN_SW_TIMER_4_FUNC            (1L << 9)
841 #define GPIO_2_FUNC                     (1L << 10)
842 #define GPIO_3_FUNC                     (1L << 11)
843 #define GPIO_4_FUNC                     (1L << 12)
844 #define ATTN_GENERAL_ATTN_1             (1L << 13)
845 #define ATTN_GENERAL_ATTN_2             (1L << 14)
846 #define ATTN_GENERAL_ATTN_3             (1L << 15)
847 #define ATTN_GENERAL_ATTN_4             (1L << 13)
848 #define ATTN_GENERAL_ATTN_5             (1L << 14)
849 #define ATTN_GENERAL_ATTN_6             (1L << 15)
850
851 #define ATTN_HARD_WIRED_MASK            0xff00
852 #define ATTENTION_ID                    4
853
854
855 #define BNX2X_BTR                       3
856 #define MAX_SPQ_PENDING                 8
857
858
859 #define BNX2X_NUM_STATS                 31
860 #define BNX2X_NUM_TESTS                 2
861
862
863 #define DPM_TRIGER_TYPE                 0x40
864 #define DOORBELL(bp, cid, val) \
865         do { \
866                 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
867                        DPM_TRIGER_TYPE); \
868         } while (0)
869
870
871 /* stuff added to make the code fit 80Col */
872
873 #define TPA_TYPE_START                  ETH_FAST_PATH_RX_CQE_START_FLG
874 #define TPA_TYPE_END                    ETH_FAST_PATH_RX_CQE_END_FLG
875 #define TPA_TYPE(cqe)           (cqe->fast_path_cqe.error_type_flags & \
876                                  (TPA_TYPE_START | TPA_TYPE_END))
877 #define BNX2X_RX_SUM_OK(cqe) \
878                         (!(cqe->fast_path_cqe.status_flags & \
879                          (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
880                           ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
881
882 #define BNX2X_RX_SUM_FIX(cqe) \
883                         ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
884                           PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
885                          (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
886
887
888 #define MDIO_AN_CL73_OR_37_COMPLETE \
889                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
890                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
891
892 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
893                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
894 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
895                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
896 #define GP_STATUS_SPEED_MASK \
897                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
898 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
899 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
900 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
901 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
902 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
903 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
904 #define GP_STATUS_10G_HIG \
905                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
906 #define GP_STATUS_10G_CX4 \
907                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
908 #define GP_STATUS_12G_HIG \
909                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
910 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
911 #define GP_STATUS_13G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
912 #define GP_STATUS_15G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
913 #define GP_STATUS_16G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
914 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
915 #define GP_STATUS_10G_KX4 \
916                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
917
918 #define LINK_10THD                      LINK_STATUS_SPEED_AND_DUPLEX_10THD
919 #define LINK_10TFD                      LINK_STATUS_SPEED_AND_DUPLEX_10TFD
920 #define LINK_100TXHD                    LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
921 #define LINK_100T4                      LINK_STATUS_SPEED_AND_DUPLEX_100T4
922 #define LINK_100TXFD                    LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
923 #define LINK_1000THD                    LINK_STATUS_SPEED_AND_DUPLEX_1000THD
924 #define LINK_1000TFD                    LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
925 #define LINK_1000XFD                    LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
926 #define LINK_2500THD                    LINK_STATUS_SPEED_AND_DUPLEX_2500THD
927 #define LINK_2500TFD                    LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
928 #define LINK_2500XFD                    LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
929 #define LINK_10GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
930 #define LINK_10GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
931 #define LINK_12GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
932 #define LINK_12GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
933 #define LINK_12_5GTFD                   LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
934 #define LINK_12_5GXFD                   LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
935 #define LINK_13GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
936 #define LINK_13GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
937 #define LINK_15GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
938 #define LINK_15GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
939 #define LINK_16GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
940 #define LINK_16GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
941
942 #define NIG_STATUS_INTERRUPT_XGXS0_LINK10G \
943                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
944 #define NIG_XGXS0_LINK_STATUS \
945                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
946 #define NIG_XGXS0_LINK_STATUS_SIZE \
947                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
948 #define NIG_SERDES0_LINK_STATUS \
949                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
950 #define NIG_MASK_MI_INT \
951                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
952 #define NIG_MASK_XGXS0_LINK10G \
953                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
954 #define NIG_MASK_XGXS0_LINK_STATUS \
955                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
956 #define NIG_MASK_SERDES0_LINK_STATUS \
957                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
958
959 #define XGXS_RESET_BITS \
960         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
961          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
962          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
963          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
964          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
965
966 #define SERDES_RESET_BITS \
967         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
968          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
969          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
970          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
971
972
973 #define BNX2X_MC_ASSERT_BITS \
974         (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
975          GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
976          GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
977          GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
978
979 #define BNX2X_MCP_ASSERT \
980         GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
981
982 #define BNX2X_DOORQ_ASSERT \
983         AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
984
985 #define HW_INTERRUT_ASSERT_SET_0 \
986                                 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
987                                  AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
988                                  AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
989                                  AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
990 #define HW_PRTY_ASSERT_SET_0    (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
991                                  AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
992                                  AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
993                                  AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
994                                  AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
995 #define HW_INTERRUT_ASSERT_SET_1 \
996                                 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
997                                  AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
998                                  AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
999                                  AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1000                                  AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1001                                  AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1002                                  AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1003                                  AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1004                                  AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1005                                  AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1006                                  AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1007 #define HW_PRTY_ASSERT_SET_1    (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1008                                  AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1009                                  AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1010                                  AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1011                                 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1012                             AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1013                                  AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1014                                  AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1015                                  AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1016                                  AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1017                                  AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1018 #define HW_INTERRUT_ASSERT_SET_2 \
1019                                 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1020                                  AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1021                                  AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1022                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1023                                  AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1024 #define HW_PRTY_ASSERT_SET_2    (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1025                                  AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1026                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1027                                  AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1028                                  AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1029                                  AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1030                                  AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1031
1032
1033 #define ETH_RX_ERROR_FALGS      (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
1034                                  ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
1035                                  ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
1036
1037
1038 #define MULTI_FLAGS \
1039         (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY     | \
1040          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1041          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY     | \
1042          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1043          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1044
1045 #define MULTI_MASK      0x7f
1046
1047
1048 #define U_SB_ETH_RX_CQ_INDEX            HC_INDEX_U_ETH_RX_CQ_CONS
1049 #define C_SB_ETH_TX_CQ_INDEX            HC_INDEX_C_ETH_TX_CQ_CONS
1050 #define C_DEF_SB_SP_INDEX               HC_INDEX_DEF_C_ETH_SLOW_PATH
1051
1052 #define BNX2X_RX_SB_INDEX \
1053         &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
1054
1055 #define BNX2X_TX_SB_INDEX \
1056         &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
1057
1058 #define BNX2X_SP_DSB_INDEX \
1059 &bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
1060
1061
1062 #define CAM_IS_INVALID(x) \
1063 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1064
1065 #define CAM_INVALIDATE(x) \
1066 x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE
1067
1068
1069 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1070
1071 #endif /* bnx2x.h */