[BNX2]: Fix occasional NETDEV WATCHDOG on 5709.
[linux-2.6.git] / drivers / net / bnx2.h
1 /* bnx2.h: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12
13 #ifndef BNX2_H
14 #define BNX2_H
15
16 /* Hardware data structures and register definitions automatically
17  * generated from RTL code. Do not modify.
18  */
19
20 /*
21  *  tx_bd definition
22  */
23 struct tx_bd {
24         u32 tx_bd_haddr_hi;
25         u32 tx_bd_haddr_lo;
26         u32 tx_bd_mss_nbytes;
27         u32 tx_bd_vlan_tag_flags;
28                 #define TX_BD_FLAGS_CONN_FAULT          (1<<0)
29                 #define TX_BD_FLAGS_TCP_UDP_CKSUM       (1<<1)
30                 #define TX_BD_FLAGS_IP_CKSUM            (1<<2)
31                 #define TX_BD_FLAGS_VLAN_TAG            (1<<3)
32                 #define TX_BD_FLAGS_COAL_NOW            (1<<4)
33                 #define TX_BD_FLAGS_DONT_GEN_CRC        (1<<5)
34                 #define TX_BD_FLAGS_END                 (1<<6)
35                 #define TX_BD_FLAGS_START               (1<<7)
36                 #define TX_BD_FLAGS_SW_OPTION_WORD      (0x1f<<8)
37                 #define TX_BD_FLAGS_SW_FLAGS            (1<<13)
38                 #define TX_BD_FLAGS_SW_SNAP             (1<<14)
39                 #define TX_BD_FLAGS_SW_LSO              (1<<15)
40
41 };
42
43
44 /*
45  *  rx_bd definition
46  */
47 struct rx_bd {
48         u32 rx_bd_haddr_hi;
49         u32 rx_bd_haddr_lo;
50         u32 rx_bd_len;
51         u32 rx_bd_flags;
52                 #define RX_BD_FLAGS_NOPUSH              (1<<0)
53                 #define RX_BD_FLAGS_DUMMY               (1<<1)
54                 #define RX_BD_FLAGS_END                 (1<<2)
55                 #define RX_BD_FLAGS_START               (1<<3)
56
57 };
58
59 #define BNX2_RX_ALIGN                   16
60
61 /*
62  *  status_block definition
63  */
64 struct status_block {
65         u32 status_attn_bits;
66                 #define STATUS_ATTN_BITS_LINK_STATE             (1L<<0)
67                 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT     (1L<<1)
68                 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT       (1L<<2)
69                 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT      (1L<<3)
70                 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT     (1L<<4)
71                 #define STATUS_ATTN_BITS_TX_DMA_ABORT           (1L<<5)
72                 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT       (1L<<6)
73                 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT     (1L<<7)
74                 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT    (1L<<8)
75                 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT        (1L<<9)
76                 #define STATUS_ATTN_BITS_RX_MBUF_ABORT          (1L<<10)
77                 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT        (1L<<11)
78                 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT     (1L<<12)
79                 #define STATUS_ATTN_BITS_RX_V2P_ABORT           (1L<<13)
80                 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT      (1L<<14)
81                 #define STATUS_ATTN_BITS_RX_DMA_ABORT           (1L<<15)
82                 #define STATUS_ATTN_BITS_COMPLETION_ABORT       (1L<<16)
83                 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT    (1L<<17)
84                 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT    (1L<<18)
85                 #define STATUS_ATTN_BITS_CONTEXT_ABORT          (1L<<19)
86                 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT    (1L<<20)
87                 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT    (1L<<21)
88                 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT   (1L<<22)
89                 #define STATUS_ATTN_BITS_MAC_ABORT              (1L<<23)
90                 #define STATUS_ATTN_BITS_TIMER_ABORT            (1L<<24)
91                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
92                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
93                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
94                 #define STATUS_ATTN_BITS_EPB_ERROR              (1L<<30)
95                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
96
97         u32 status_attn_bits_ack;
98 #if defined(__BIG_ENDIAN)
99         u16 status_tx_quick_consumer_index0;
100         u16 status_tx_quick_consumer_index1;
101         u16 status_tx_quick_consumer_index2;
102         u16 status_tx_quick_consumer_index3;
103         u16 status_rx_quick_consumer_index0;
104         u16 status_rx_quick_consumer_index1;
105         u16 status_rx_quick_consumer_index2;
106         u16 status_rx_quick_consumer_index3;
107         u16 status_rx_quick_consumer_index4;
108         u16 status_rx_quick_consumer_index5;
109         u16 status_rx_quick_consumer_index6;
110         u16 status_rx_quick_consumer_index7;
111         u16 status_rx_quick_consumer_index8;
112         u16 status_rx_quick_consumer_index9;
113         u16 status_rx_quick_consumer_index10;
114         u16 status_rx_quick_consumer_index11;
115         u16 status_rx_quick_consumer_index12;
116         u16 status_rx_quick_consumer_index13;
117         u16 status_rx_quick_consumer_index14;
118         u16 status_rx_quick_consumer_index15;
119         u16 status_completion_producer_index;
120         u16 status_cmd_consumer_index;
121         u16 status_idx;
122         u8 status_unused;
123         u8 status_blk_num;
124 #elif defined(__LITTLE_ENDIAN)
125         u16 status_tx_quick_consumer_index1;
126         u16 status_tx_quick_consumer_index0;
127         u16 status_tx_quick_consumer_index3;
128         u16 status_tx_quick_consumer_index2;
129         u16 status_rx_quick_consumer_index1;
130         u16 status_rx_quick_consumer_index0;
131         u16 status_rx_quick_consumer_index3;
132         u16 status_rx_quick_consumer_index2;
133         u16 status_rx_quick_consumer_index5;
134         u16 status_rx_quick_consumer_index4;
135         u16 status_rx_quick_consumer_index7;
136         u16 status_rx_quick_consumer_index6;
137         u16 status_rx_quick_consumer_index9;
138         u16 status_rx_quick_consumer_index8;
139         u16 status_rx_quick_consumer_index11;
140         u16 status_rx_quick_consumer_index10;
141         u16 status_rx_quick_consumer_index13;
142         u16 status_rx_quick_consumer_index12;
143         u16 status_rx_quick_consumer_index15;
144         u16 status_rx_quick_consumer_index14;
145         u16 status_cmd_consumer_index;
146         u16 status_completion_producer_index;
147         u8 status_blk_num;
148         u8 status_unused;
149         u16 status_idx;
150 #endif
151 };
152
153
154 /*
155  *  statistics_block definition
156  */
157 struct statistics_block {
158         u32 stat_IfHCInOctets_hi;
159         u32 stat_IfHCInOctets_lo;
160         u32 stat_IfHCInBadOctets_hi;
161         u32 stat_IfHCInBadOctets_lo;
162         u32 stat_IfHCOutOctets_hi;
163         u32 stat_IfHCOutOctets_lo;
164         u32 stat_IfHCOutBadOctets_hi;
165         u32 stat_IfHCOutBadOctets_lo;
166         u32 stat_IfHCInUcastPkts_hi;
167         u32 stat_IfHCInUcastPkts_lo;
168         u32 stat_IfHCInMulticastPkts_hi;
169         u32 stat_IfHCInMulticastPkts_lo;
170         u32 stat_IfHCInBroadcastPkts_hi;
171         u32 stat_IfHCInBroadcastPkts_lo;
172         u32 stat_IfHCOutUcastPkts_hi;
173         u32 stat_IfHCOutUcastPkts_lo;
174         u32 stat_IfHCOutMulticastPkts_hi;
175         u32 stat_IfHCOutMulticastPkts_lo;
176         u32 stat_IfHCOutBroadcastPkts_hi;
177         u32 stat_IfHCOutBroadcastPkts_lo;
178         u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
179         u32 stat_Dot3StatsCarrierSenseErrors;
180         u32 stat_Dot3StatsFCSErrors;
181         u32 stat_Dot3StatsAlignmentErrors;
182         u32 stat_Dot3StatsSingleCollisionFrames;
183         u32 stat_Dot3StatsMultipleCollisionFrames;
184         u32 stat_Dot3StatsDeferredTransmissions;
185         u32 stat_Dot3StatsExcessiveCollisions;
186         u32 stat_Dot3StatsLateCollisions;
187         u32 stat_EtherStatsCollisions;
188         u32 stat_EtherStatsFragments;
189         u32 stat_EtherStatsJabbers;
190         u32 stat_EtherStatsUndersizePkts;
191         u32 stat_EtherStatsOverrsizePkts;
192         u32 stat_EtherStatsPktsRx64Octets;
193         u32 stat_EtherStatsPktsRx65Octetsto127Octets;
194         u32 stat_EtherStatsPktsRx128Octetsto255Octets;
195         u32 stat_EtherStatsPktsRx256Octetsto511Octets;
196         u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
197         u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
198         u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
199         u32 stat_EtherStatsPktsTx64Octets;
200         u32 stat_EtherStatsPktsTx65Octetsto127Octets;
201         u32 stat_EtherStatsPktsTx128Octetsto255Octets;
202         u32 stat_EtherStatsPktsTx256Octetsto511Octets;
203         u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
204         u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
205         u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
206         u32 stat_XonPauseFramesReceived;
207         u32 stat_XoffPauseFramesReceived;
208         u32 stat_OutXonSent;
209         u32 stat_OutXoffSent;
210         u32 stat_FlowControlDone;
211         u32 stat_MacControlFramesReceived;
212         u32 stat_XoffStateEntered;
213         u32 stat_IfInFramesL2FilterDiscards;
214         u32 stat_IfInRuleCheckerDiscards;
215         u32 stat_IfInFTQDiscards;
216         u32 stat_IfInMBUFDiscards;
217         u32 stat_IfInRuleCheckerP4Hit;
218         u32 stat_CatchupInRuleCheckerDiscards;
219         u32 stat_CatchupInFTQDiscards;
220         u32 stat_CatchupInMBUFDiscards;
221         u32 stat_CatchupInRuleCheckerP4Hit;
222         u32 stat_GenStat00;
223         u32 stat_GenStat01;
224         u32 stat_GenStat02;
225         u32 stat_GenStat03;
226         u32 stat_GenStat04;
227         u32 stat_GenStat05;
228         u32 stat_GenStat06;
229         u32 stat_GenStat07;
230         u32 stat_GenStat08;
231         u32 stat_GenStat09;
232         u32 stat_GenStat10;
233         u32 stat_GenStat11;
234         u32 stat_GenStat12;
235         u32 stat_GenStat13;
236         u32 stat_GenStat14;
237         u32 stat_GenStat15;
238         u32 stat_FwRxDrop;
239 };
240
241
242 /*
243  *  l2_fhdr definition
244  */
245 struct l2_fhdr {
246         u32 l2_fhdr_status;
247                 #define L2_FHDR_STATUS_RULE_CLASS       (0x7<<0)
248                 #define L2_FHDR_STATUS_RULE_P2          (1<<3)
249                 #define L2_FHDR_STATUS_RULE_P3          (1<<4)
250                 #define L2_FHDR_STATUS_RULE_P4          (1<<5)
251                 #define L2_FHDR_STATUS_L2_VLAN_TAG      (1<<6)
252                 #define L2_FHDR_STATUS_L2_LLC_SNAP      (1<<7)
253                 #define L2_FHDR_STATUS_RSS_HASH         (1<<8)
254                 #define L2_FHDR_STATUS_IP_DATAGRAM      (1<<13)
255                 #define L2_FHDR_STATUS_TCP_SEGMENT      (1<<14)
256                 #define L2_FHDR_STATUS_UDP_DATAGRAM     (1<<15)
257
258                 #define L2_FHDR_ERRORS_BAD_CRC          (1<<17)
259                 #define L2_FHDR_ERRORS_PHY_DECODE       (1<<18)
260                 #define L2_FHDR_ERRORS_ALIGNMENT        (1<<19)
261                 #define L2_FHDR_ERRORS_TOO_SHORT        (1<<20)
262                 #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<21)
263                 #define L2_FHDR_ERRORS_TCP_XSUM         (1<<28)
264                 #define L2_FHDR_ERRORS_UDP_XSUM         (1<<31)
265
266         u32 l2_fhdr_hash;
267 #if defined(__BIG_ENDIAN)
268         u16 l2_fhdr_pkt_len;
269         u16 l2_fhdr_vlan_tag;
270         u16 l2_fhdr_ip_xsum;
271         u16 l2_fhdr_tcp_udp_xsum;
272 #elif defined(__LITTLE_ENDIAN)
273         u16 l2_fhdr_vlan_tag;
274         u16 l2_fhdr_pkt_len;
275         u16 l2_fhdr_tcp_udp_xsum;
276         u16 l2_fhdr_ip_xsum;
277 #endif
278 };
279
280
281 /*
282  *  l2_context definition
283  */
284 #define BNX2_L2CTX_TYPE                                 0x00000000
285 #define BNX2_L2CTX_TYPE_SIZE_L2                          ((0xc0/0x20)<<16)
286 #define BNX2_L2CTX_TYPE_TYPE                             (0xf<<28)
287 #define BNX2_L2CTX_TYPE_TYPE_EMPTY                       (0<<28)
288 #define BNX2_L2CTX_TYPE_TYPE_L2                          (1<<28)
289
290 #define BNX2_L2CTX_TX_HOST_BIDX                         0x00000088
291 #define BNX2_L2CTX_EST_NBD                              0x00000088
292 #define BNX2_L2CTX_CMD_TYPE                             0x00000088
293 #define BNX2_L2CTX_CMD_TYPE_TYPE                         (0xf<<24)
294 #define BNX2_L2CTX_CMD_TYPE_TYPE_L2                      (0<<24)
295 #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP                     (1<<24)
296
297 #define BNX2_L2CTX_TX_HOST_BSEQ                         0x00000090
298 #define BNX2_L2CTX_TSCH_BSEQ                            0x00000094
299 #define BNX2_L2CTX_TBDR_BSEQ                            0x00000098
300 #define BNX2_L2CTX_TBDR_BOFF                            0x0000009c
301 #define BNX2_L2CTX_TBDR_BIDX                            0x0000009c
302 #define BNX2_L2CTX_TBDR_BHADDR_HI                       0x000000a0
303 #define BNX2_L2CTX_TBDR_BHADDR_LO                       0x000000a4
304 #define BNX2_L2CTX_TXP_BOFF                             0x000000a8
305 #define BNX2_L2CTX_TXP_BIDX                             0x000000a8
306 #define BNX2_L2CTX_TXP_BSEQ                             0x000000ac
307
308 #define BNX2_L2CTX_TYPE_XI                              0x00000080
309 #define BNX2_L2CTX_CMD_TYPE_XI                          0x00000240
310 #define BNX2_L2CTX_TBDR_BHADDR_HI_XI                    0x00000258
311 #define BNX2_L2CTX_TBDR_BHADDR_LO_XI                    0x0000025c
312
313 /*
314  *  l2_bd_chain_context definition
315  */
316 #define BNX2_L2CTX_BD_PRE_READ                          0x00000000
317 #define BNX2_L2CTX_CTX_SIZE                             0x00000000
318 #define BNX2_L2CTX_CTX_TYPE                             0x00000000
319 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2                      ((0x20/20)<<16)
320 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE              (0xf<<28)
321 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED    (0<<28)
322 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE        (1<<28)
323
324 #define BNX2_L2CTX_HOST_BDIDX                           0x00000004
325 #define BNX2_L2CTX_HOST_BSEQ                            0x00000008
326 #define BNX2_L2CTX_NX_BSEQ                              0x0000000c
327 #define BNX2_L2CTX_NX_BDHADDR_HI                        0x00000010
328 #define BNX2_L2CTX_NX_BDHADDR_LO                        0x00000014
329 #define BNX2_L2CTX_NX_BDIDX                             0x00000018
330
331
332 /*
333  *  pci_config_l definition
334  *  offset: 0000
335  */
336 #define BNX2_PCICFG_MISC_CONFIG                         0x00000068
337 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
338 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
339 #define BNX2_PCICFG_MISC_CONFIG_RESERVED1                (1L<<4)
340 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
341 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
342 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
343 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
344 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
345 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN         (1L<<10)
346 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN         (1L<<11)
347 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN         (1L<<12)
348 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
349 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
350 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
351
352 #define BNX2_PCICFG_MISC_STATUS                         0x0000006c
353 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE               (1L<<0)
354 #define BNX2_PCICFG_MISC_STATUS_32BIT_DET                (1L<<1)
355 #define BNX2_PCICFG_MISC_STATUS_M66EN                    (1L<<2)
356 #define BNX2_PCICFG_MISC_STATUS_PCIX_DET                 (1L<<3)
357 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED               (0x3L<<4)
358 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66            (0L<<4)
359 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
360 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
361 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
362 #define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE         (1L<<8)
363
364 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS              0x00000070
365 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
366 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ         (0L<<0)
367 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ         (1L<<0)
368 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ         (2L<<0)
369 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ         (3L<<0)
370 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ         (4L<<0)
371 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ         (5L<<0)
372 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ         (6L<<0)
373 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ        (7L<<0)
374 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW   (0xfL<<0)
375 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE      (1L<<6)
376 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT  (1L<<7)
377 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC      (0x7L<<8)
378 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF        (0L<<8)
379 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
380 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
381 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
382 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER     (1L<<11)
383 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
384 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
385 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
386 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50         (2L<<12)
387 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
388 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
389 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
390 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17   (1L<<17)
391 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
392 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19   (1L<<19)
393 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
394
395 #define BNX2_PCICFG_REG_WINDOW_ADDRESS                  0x00000078
396 #define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL               (0xfffffL<<2)
397
398 #define BNX2_PCICFG_REG_WINDOW                          0x00000080
399 #define BNX2_PCICFG_INT_ACK_CMD                         0x00000084
400 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
401 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
402 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
403 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
404 #define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM            (0xfL<<24)
405
406 #define BNX2_PCICFG_STATUS_BIT_SET_CMD                  0x00000088
407 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD                0x0000008c
408 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR                  0x00000090
409 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA                  0x00000094
410
411
412 /*
413  *  pci_reg definition
414  *  offset: 0x400
415  */
416 #define BNX2_PCI_GRC_WINDOW_ADDR                        0x00000400
417 #define BNX2_PCI_GRC_WINDOW_ADDR_VALUE                   (0x1ffL<<13)
418 #define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN                 (1L<<31)
419
420 #define BNX2_PCI_CONFIG_1                               0x00000404
421 #define BNX2_PCI_CONFIG_1_RESERVED0                      (0xffL<<0)
422 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
423 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
424 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
425 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32               (2L<<8)
426 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64               (3L<<8)
427 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128              (4L<<8)
428 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256              (5L<<8)
429 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512              (6L<<8)
430 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024             (7L<<8)
431 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY                 (0x7L<<11)
432 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF             (0L<<11)
433 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16              (1L<<11)
434 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32              (2L<<11)
435 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64              (3L<<11)
436 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128             (4L<<11)
437 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
438 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
439 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
440 #define BNX2_PCI_CONFIG_1_RESERVED1                      (0x3ffffL<<14)
441
442 #define BNX2_PCI_CONFIG_2                               0x00000408
443 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
444 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED             (0L<<0)
445 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K                  (1L<<0)
446 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K                 (2L<<0)
447 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K                 (3L<<0)
448 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K                 (4L<<0)
449 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M                   (5L<<0)
450 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M                   (6L<<0)
451 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M                   (7L<<0)
452 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M                   (8L<<0)
453 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M                  (9L<<0)
454 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M                  (10L<<0)
455 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M                  (11L<<0)
456 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M                 (12L<<0)
457 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M                 (13L<<0)
458 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M                 (14L<<0)
459 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G                   (15L<<0)
460 #define BNX2_PCI_CONFIG_2_BAR1_64ENA                     (1L<<4)
461 #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY                  (1L<<5)
462 #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY                (1L<<6)
463 #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE                 (1L<<7)
464 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE                   (0xffL<<8)
465 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED          (0L<<8)
466 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K                (1L<<8)
467 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K                (2L<<8)
468 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K                (3L<<8)
469 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K                (4L<<8)
470 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K               (5L<<8)
471 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K               (6L<<8)
472 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K               (7L<<8)
473 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K              (8L<<8)
474 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K              (9L<<8)
475 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K              (10L<<8)
476 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M                (11L<<8)
477 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M                (12L<<8)
478 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M                (13L<<8)
479 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M                (14L<<8)
480 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M               (15L<<8)
481 #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT                (0x1fL<<16)
482 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT                 (0x3L<<21)
483 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512             (0L<<21)
484 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K              (1L<<21)
485 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K              (2L<<21)
486 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K              (3L<<21)
487 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
488 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
489 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
490 #define BNX2_PCI_CONFIG_2_RESERVED0                      (0x3fL<<26)
491 #define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI                (1L<<16)
492 #define BNX2_PCI_CONFIG_2_RESERVED0_XI                   (0x7fffL<<17)
493
494 #define BNX2_PCI_CONFIG_3                               0x0000040c
495 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
496 #define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE                (0xffL<<8)
497 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
498 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
499 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
500 #define BNX2_PCI_CONFIG_3_PM_STATE                       (0x3L<<27)
501 #define BNX2_PCI_CONFIG_3_VAUX_PRESET                    (1L<<30)
502 #define BNX2_PCI_CONFIG_3_PCI_POWER                      (1L<<31)
503
504 #define BNX2_PCI_PM_DATA_A                              0x00000410
505 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG                 (0xffL<<0)
506 #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG                 (0xffL<<8)
507 #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG                 (0xffL<<16)
508 #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG                 (0xffL<<24)
509
510 #define BNX2_PCI_PM_DATA_B                              0x00000414
511 #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG                 (0xffL<<0)
512 #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG                 (0xffL<<8)
513 #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG                 (0xffL<<16)
514 #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG                 (0xffL<<24)
515
516 #define BNX2_PCI_SWAP_DIAG0                             0x00000418
517 #define BNX2_PCI_SWAP_DIAG1                             0x0000041c
518 #define BNX2_PCI_EXP_ROM_ADDR                           0x00000420
519 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS                    (0x3fffffL<<2)
520 #define BNX2_PCI_EXP_ROM_ADDR_REQ                        (1L<<31)
521
522 #define BNX2_PCI_EXP_ROM_DATA                           0x00000424
523 #define BNX2_PCI_VPD_INTF                               0x00000428
524 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
525
526 #define BNX2_PCI_VPD_ADDR_FLAG                          0x0000042c
527 #define BNX2_PCI_VPD_ADDR_FLAG_MSK                      0x0000ffff
528 #define BNX2_PCI_VPD_ADDR_FLAG_SL                       0L
529 #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fffL<<2)
530 #define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1L<<15)
531
532 #define BNX2_PCI_VPD_DATA                               0x00000430
533 #define BNX2_PCI_ID_VAL1                                0x00000434
534 #define BNX2_PCI_ID_VAL1_DEVICE_ID                       (0xffffL<<0)
535 #define BNX2_PCI_ID_VAL1_VENDOR_ID                       (0xffffL<<16)
536
537 #define BNX2_PCI_ID_VAL2                                0x00000438
538 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID             (0xffffL<<0)
539 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID                    (0xffffL<<16)
540
541 #define BNX2_PCI_ID_VAL3                                0x0000043c
542 #define BNX2_PCI_ID_VAL3_CLASS_CODE                      (0xffffffL<<0)
543 #define BNX2_PCI_ID_VAL3_REVISION_ID                     (0xffL<<24)
544
545 #define BNX2_PCI_ID_VAL4                                0x00000440
546 #define BNX2_PCI_ID_VAL4_CAP_ENA                         (0xfL<<0)
547 #define BNX2_PCI_ID_VAL4_CAP_ENA_0                       (0L<<0)
548 #define BNX2_PCI_ID_VAL4_CAP_ENA_1                       (1L<<0)
549 #define BNX2_PCI_ID_VAL4_CAP_ENA_2                       (2L<<0)
550 #define BNX2_PCI_ID_VAL4_CAP_ENA_3                       (3L<<0)
551 #define BNX2_PCI_ID_VAL4_CAP_ENA_4                       (4L<<0)
552 #define BNX2_PCI_ID_VAL4_CAP_ENA_5                       (5L<<0)
553 #define BNX2_PCI_ID_VAL4_CAP_ENA_6                       (6L<<0)
554 #define BNX2_PCI_ID_VAL4_CAP_ENA_7                       (7L<<0)
555 #define BNX2_PCI_ID_VAL4_CAP_ENA_8                       (8L<<0)
556 #define BNX2_PCI_ID_VAL4_CAP_ENA_9                       (9L<<0)
557 #define BNX2_PCI_ID_VAL4_CAP_ENA_10                      (10L<<0)
558 #define BNX2_PCI_ID_VAL4_CAP_ENA_11                      (11L<<0)
559 #define BNX2_PCI_ID_VAL4_CAP_ENA_12                      (12L<<0)
560 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
561 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
562 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
563 #define BNX2_PCI_ID_VAL4_RESERVED0                       (0x3L<<4)
564 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
565 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
566 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
567 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
568 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
569 #define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP                 (1L<<8)
570 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
571 #define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP                   (0x7L<<12)
572 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
573 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
574 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
575 #define BNX2_PCI_ID_VAL4_RESERVED2                       (0x7L<<18)
576 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21         (0x3L<<21)
577 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21              (0x3L<<23)
578 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0          (1L<<25)
579 #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10           (0x3L<<26)
580 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0               (1L<<28)
581 #define BNX2_PCI_ID_VAL4_RESERVED3                       (0x7L<<29)
582 #define BNX2_PCI_ID_VAL4_RESERVED3_XI                    (0xffffL<<16)
583
584 #define BNX2_PCI_ID_VAL5                                0x00000444
585 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
586 #define BNX2_PCI_ID_VAL5_D2_SUPPORT                      (1L<<1)
587 #define BNX2_PCI_ID_VAL5_PME_IN_D0                       (1L<<2)
588 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
589 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
590 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
591 #define BNX2_PCI_ID_VAL5_RESERVED0_TE                    (0x3ffffffL<<6)
592 #define BNX2_PCI_ID_VAL5_PM_VERSION_XI                   (0x7L<<6)
593 #define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI                (1L<<9)
594 #define BNX2_PCI_ID_VAL5_RESERVED0_XI                    (0x3fffffL<<10)
595
596 #define BNX2_PCI_PCIX_EXTENDED_STATUS                   0x00000448
597 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
598 #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST         (1L<<9)
599 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS       (0xfL<<16)
600 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX         (0xffL<<24)
601
602 #define BNX2_PCI_ID_VAL6                                0x0000044c
603 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
604 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
605 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
606 #define BNX2_PCI_ID_VAL6_RESERVED0                       (0xffL<<24)
607
608 #define BNX2_PCI_MSI_DATA                               0x00000450
609 #define BNX2_PCI_MSI_DATA_MSI_DATA                       (0xffffL<<0)
610
611 #define BNX2_PCI_MSI_ADDR_H                             0x00000454
612 #define BNX2_PCI_MSI_ADDR_L                             0x00000458
613 #define BNX2_PCI_MSI_ADDR_L_VAL                          (0x3fffffffL<<2)
614
615 #define BNX2_PCI_CFG_ACCESS_CMD                         0x0000045c
616 #define BNX2_PCI_CFG_ACCESS_CMD_ADR                      (0x3fL<<2)
617 #define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ                   (1L<<27)
618 #define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ                   (0xfL<<28)
619
620 #define BNX2_PCI_CFG_ACCESS_DATA                        0x00000460
621 #define BNX2_PCI_MSI_MASK                               0x00000464
622 #define BNX2_PCI_MSI_MASK_MSI_MASK                       (0xffffffffL<<0)
623
624 #define BNX2_PCI_MSI_PEND                               0x00000468
625 #define BNX2_PCI_MSI_PEND_MSI_PEND                       (0xffffffffL<<0)
626
627 #define BNX2_PCI_PM_DATA_C                              0x0000046c
628 #define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG                 (0xffL<<0)
629 #define BNX2_PCI_PM_DATA_C_RESERVED0                     (0xffffffL<<8)
630
631 #define BNX2_PCI_MSIX_CONTROL                           0x000004c0
632 #define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ               (0x7ffL<<0)
633 #define BNX2_PCI_MSIX_CONTROL_RESERVED0                  (0x1fffffL<<11)
634
635 #define BNX2_PCI_MSIX_TBL_OFF_BIR                       0x000004c4
636 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR           (0x7L<<0)
637 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF           (0x1fffffffL<<3)
638
639 #define BNX2_PCI_MSIX_PBA_OFF_BIT                       0x000004c8
640 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR           (0x7L<<0)
641 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF           (0x1fffffffL<<3)
642
643 #define BNX2_PCI_PCIE_CAPABILITY                        0x000004d0
644 #define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM       (0x1fL<<0)
645 #define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1         (1L<<5)
646
647 #define BNX2_PCI_DEVICE_CAPABILITY                      0x000004d4
648 #define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED  (0x7L<<0)
649 #define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT  (1L<<5)
650 #define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY        (0x7L<<6)
651 #define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY         (0x7L<<9)
652 #define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT    (1L<<15)
653
654 #define BNX2_PCI_LINK_CAPABILITY                        0x000004dc
655 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED          (0xfL<<0)
656 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001     (1L<<0)
657 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010     (1L<<0)
658 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH          (0x1fL<<4)
659 #define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT          (1L<<9)
660 #define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT            (0x3L<<10)
661 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT            (0x7L<<12)
662 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101        (5L<<12)
663 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110        (6L<<12)
664 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT             (0x7L<<15)
665 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001         (1L<<15)
666 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010         (2L<<15)
667 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT       (0x7L<<18)
668 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101   (5L<<18)
669 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110   (6L<<18)
670 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT        (0x7L<<21)
671 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001    (1L<<21)
672 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010    (2L<<21)
673 #define BNX2_PCI_LINK_CAPABILITY_PORT_NUM                (0xffL<<24)
674
675 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2               0x000004e4
676 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP     (0xfL<<0)
677 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP    (1L<<4)
678 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED       (0x7ffffffL<<5)
679
680 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2                 0x000004e8
681 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED         (0xffffffffL<<0)
682
683 #define BNX2_PCI_GRC_WINDOW1_ADDR                       0x00000610
684 #define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE                  (0x1ffL<<13)
685
686 #define BNX2_PCI_GRC_WINDOW2_ADDR                       0x00000614
687 #define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE                  (0x1ffL<<13)
688
689 #define BNX2_PCI_GRC_WINDOW3_ADDR                       0x00000618
690 #define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE                  (0x1ffL<<13)
691
692
693 /*
694  *  misc_reg definition
695  *  offset: 0x800
696  */
697 #define BNX2_MISC_COMMAND                               0x00000800
698 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
699 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
700 #define BNX2_MISC_COMMAND_SW_RESET                       (1L<<4)
701 #define BNX2_MISC_COMMAND_POR_RESET                      (1L<<5)
702 #define BNX2_MISC_COMMAND_HD_RESET                       (1L<<6)
703 #define BNX2_MISC_COMMAND_CMN_SW_RESET                   (1L<<7)
704 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
705 #define BNX2_MISC_COMMAND_CS16_ERR                       (1L<<9)
706 #define BNX2_MISC_COMMAND_CS16_ERR_LOC                   (0xfL<<12)
707 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
708 #define BNX2_MISC_COMMAND_POWERDOWN_EVENT                (1L<<23)
709 #define BNX2_MISC_COMMAND_SW_SHUTDOWN                    (1L<<24)
710 #define BNX2_MISC_COMMAND_SHUTDOWN_EN                    (1L<<25)
711 #define BNX2_MISC_COMMAND_DINTEG_ATTN_EN                 (1L<<26)
712 #define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23               (1L<<27)
713 #define BNX2_MISC_COMMAND_PCIE_DIS                       (1L<<28)
714
715 #define BNX2_MISC_CFG                                   0x00000804
716 #define BNX2_MISC_CFG_GRC_TMOUT                          (1L<<0)
717 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
718 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
719 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
720 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW                    (2L<<1)
721 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
722 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
723 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
724 #define BNX2_MISC_CFG_RESERVED5_TE                       (1L<<5)
725 #define BNX2_MISC_CFG_RESERVED6_TE                       (1L<<6)
726 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
727 #define BNX2_MISC_CFG_LEDMODE                            (0x7L<<8)
728 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
729 #define BNX2_MISC_CFG_LEDMODE_PHY1_TE                    (1L<<8)
730 #define BNX2_MISC_CFG_LEDMODE_PHY2_TE                    (2L<<8)
731 #define BNX2_MISC_CFG_LEDMODE_PHY3_TE                    (3L<<8)
732 #define BNX2_MISC_CFG_LEDMODE_PHY4_TE                    (4L<<8)
733 #define BNX2_MISC_CFG_LEDMODE_PHY5_TE                    (5L<<8)
734 #define BNX2_MISC_CFG_LEDMODE_PHY6_TE                    (6L<<8)
735 #define BNX2_MISC_CFG_LEDMODE_PHY7_TE                    (7L<<8)
736 #define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE                   (1L<<11)
737 #define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE                   (1L<<12)
738 #define BNX2_MISC_CFG_LEDMODE_XI                         (0xfL<<8)
739 #define BNX2_MISC_CFG_LEDMODE_MAC_XI                     (0L<<8)
740 #define BNX2_MISC_CFG_LEDMODE_PHY1_XI                    (1L<<8)
741 #define BNX2_MISC_CFG_LEDMODE_PHY2_XI                    (2L<<8)
742 #define BNX2_MISC_CFG_LEDMODE_PHY3_XI                    (3L<<8)
743 #define BNX2_MISC_CFG_LEDMODE_MAC2_XI                    (4L<<8)
744 #define BNX2_MISC_CFG_LEDMODE_PHY4_XI                    (5L<<8)
745 #define BNX2_MISC_CFG_LEDMODE_PHY5_XI                    (6L<<8)
746 #define BNX2_MISC_CFG_LEDMODE_PHY6_XI                    (7L<<8)
747 #define BNX2_MISC_CFG_LEDMODE_MAC3_XI                    (8L<<8)
748 #define BNX2_MISC_CFG_LEDMODE_PHY7_XI                    (9L<<8)
749 #define BNX2_MISC_CFG_LEDMODE_PHY8_XI                    (10L<<8)
750 #define BNX2_MISC_CFG_LEDMODE_PHY9_XI                    (11L<<8)
751 #define BNX2_MISC_CFG_LEDMODE_MAC4_XI                    (12L<<8)
752 #define BNX2_MISC_CFG_LEDMODE_PHY10_XI                   (13L<<8)
753 #define BNX2_MISC_CFG_LEDMODE_PHY11_XI                   (14L<<8)
754 #define BNX2_MISC_CFG_LEDMODE_UNUSED_XI                  (15L<<8)
755 #define BNX2_MISC_CFG_PORT_SELECT_XI                     (1L<<13)
756 #define BNX2_MISC_CFG_PARITY_MODE_XI                     (1L<<14)
757
758 #define BNX2_MISC_ID                                    0x00000808
759 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
760 #define BNX2_MISC_ID_BOND_ID_X                           (0L<<0)
761 #define BNX2_MISC_ID_BOND_ID_C                           (3L<<0)
762 #define BNX2_MISC_ID_BOND_ID_S                           (12L<<0)
763 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
764 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
765 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
766
767 #define BNX2_MISC_ENABLE_STATUS_BITS                    0x0000080c
768 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE         (1L<<0)
769 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE   (1L<<1)
770 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE  (1L<<2)
771 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE         (1L<<3)
772 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE       (1L<<4)
773 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE   (1L<<5)
774 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE         (1L<<6)
775 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE  (1L<<7)
776 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE         (1L<<8)
777 #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE         (1L<<9)
778 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE        (1L<<10)
779 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE    (1L<<11)
780 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE      (1L<<12)
781 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE    (1L<<13)
782 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE         (1L<<14)
783 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE       (1L<<15)
784 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE  (1L<<16)
785 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE       (1L<<17)
786 #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE   (1L<<18)
787 #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE        (1L<<19)
788 #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE        (1L<<20)
789 #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE      (1L<<21)
790 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE        (1L<<22)
791 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE        (1L<<23)
792 #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE       (1L<<24)
793 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
794 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
795 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
796 #define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE   (1L<<28)
797 #define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE  (0x7L<<29)
798
799 #define BNX2_MISC_ENABLE_SET_BITS                       0x00000810
800 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
801 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE      (1L<<1)
802 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
803 #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
804 #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE          (1L<<4)
805 #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE      (1L<<5)
806 #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
807 #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
808 #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
809 #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE            (1L<<9)
810 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
811 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
812 #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE         (1L<<12)
813 #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE       (1L<<13)
814 #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
815 #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE          (1L<<15)
816 #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
817 #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE          (1L<<17)
818 #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE      (1L<<18)
819 #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE   (1L<<19)
820 #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
821 #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE         (1L<<21)
822 #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
823 #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
824 #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
825 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
826 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
827 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
828 #define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
829 #define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
830
831 #define BNX2_MISC_ENABLE_CLR_BITS                       0x00000814
832 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
833 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE      (1L<<1)
834 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
835 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
836 #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE          (1L<<4)
837 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE      (1L<<5)
838 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
839 #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
840 #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
841 #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE            (1L<<9)
842 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
843 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
844 #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE         (1L<<12)
845 #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE       (1L<<13)
846 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
847 #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE          (1L<<15)
848 #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
849 #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE          (1L<<17)
850 #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE      (1L<<18)
851 #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE   (1L<<19)
852 #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
853 #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE         (1L<<21)
854 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
855 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
856 #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
857 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
858 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
859 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
860 #define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
861 #define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
862
863 #define BNX2_MISC_CLOCK_CONTROL_BITS                    0x00000818
864 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
865 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ       (0L<<0)
866 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ       (1L<<0)
867 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ       (2L<<0)
868 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ       (3L<<0)
869 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ       (4L<<0)
870 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ       (5L<<0)
871 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ       (6L<<0)
872 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ      (7L<<0)
873 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW         (0xfL<<0)
874 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE    (1L<<6)
875 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT        (1L<<7)
876 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC    (0x7L<<8)
877 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF      (0L<<8)
878 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
879 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
880 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
881 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI        (0x7L<<8)
882 #define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER           (1L<<11)
883 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
884 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
885 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
886 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
887 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
888 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
889 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI        (0xfL<<12)
890 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
891 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE      (1L<<17)
892 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE      (1L<<18)
893 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE      (1L<<19)
894 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE         (0xfffL<<20)
895 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI        (1L<<17)
896 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI        (0x3fL<<18)
897 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI         (0x7L<<24)
898 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI        (1L<<27)
899 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI       (0xfL<<28)
900
901 #define BNX2_MISC_SPIO                                  0x0000081c
902 #define BNX2_MISC_SPIO_VALUE                             (0xffL<<0)
903 #define BNX2_MISC_SPIO_SET                               (0xffL<<8)
904 #define BNX2_MISC_SPIO_CLR                               (0xffL<<16)
905 #define BNX2_MISC_SPIO_FLOAT                             (0xffL<<24)
906
907 #define BNX2_MISC_SPIO_INT                              0x00000820
908 #define BNX2_MISC_SPIO_INT_INT_STATE_TE                  (0xfL<<0)
909 #define BNX2_MISC_SPIO_INT_OLD_VALUE_TE                  (0xfL<<8)
910 #define BNX2_MISC_SPIO_INT_OLD_SET_TE                    (0xfL<<16)
911 #define BNX2_MISC_SPIO_INT_OLD_CLR_TE                    (0xfL<<24)
912 #define BNX2_MISC_SPIO_INT_INT_STATE_XI                  (0xffL<<0)
913 #define BNX2_MISC_SPIO_INT_OLD_VALUE_XI                  (0xffL<<8)
914 #define BNX2_MISC_SPIO_INT_OLD_SET_XI                    (0xffL<<16)
915 #define BNX2_MISC_SPIO_INT_OLD_CLR_XI                    (0xffL<<24)
916
917 #define BNX2_MISC_CONFIG_LFSR                           0x00000824
918 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
919
920 #define BNX2_MISC_LFSR_MASK_BITS                        0x00000828
921 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE     (1L<<0)
922 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE       (1L<<1)
923 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE      (1L<<2)
924 #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE     (1L<<3)
925 #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE           (1L<<4)
926 #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE       (1L<<5)
927 #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE     (1L<<6)
928 #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE      (1L<<7)
929 #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE     (1L<<8)
930 #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE             (1L<<9)
931 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE    (1L<<10)
932 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE        (1L<<11)
933 #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE          (1L<<12)
934 #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE        (1L<<13)
935 #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE     (1L<<14)
936 #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE           (1L<<15)
937 #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE      (1L<<16)
938 #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE           (1L<<17)
939 #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE       (1L<<18)
940 #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE    (1L<<19)
941 #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE    (1L<<20)
942 #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE          (1L<<21)
943 #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE    (1L<<22)
944 #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE    (1L<<23)
945 #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE   (1L<<24)
946 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
947 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
948 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
949 #define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE       (1L<<28)
950 #define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE      (0x7L<<29)
951
952 #define BNX2_MISC_ARB_REQ0                              0x0000082c
953 #define BNX2_MISC_ARB_REQ1                              0x00000830
954 #define BNX2_MISC_ARB_REQ2                              0x00000834
955 #define BNX2_MISC_ARB_REQ3                              0x00000838
956 #define BNX2_MISC_ARB_REQ4                              0x0000083c
957 #define BNX2_MISC_ARB_FREE0                             0x00000840
958 #define BNX2_MISC_ARB_FREE1                             0x00000844
959 #define BNX2_MISC_ARB_FREE2                             0x00000848
960 #define BNX2_MISC_ARB_FREE3                             0x0000084c
961 #define BNX2_MISC_ARB_FREE4                             0x00000850
962 #define BNX2_MISC_ARB_REQ_STATUS0                       0x00000854
963 #define BNX2_MISC_ARB_REQ_STATUS1                       0x00000858
964 #define BNX2_MISC_ARB_REQ_STATUS2                       0x0000085c
965 #define BNX2_MISC_ARB_REQ_STATUS3                       0x00000860
966 #define BNX2_MISC_ARB_REQ_STATUS4                       0x00000864
967 #define BNX2_MISC_ARB_GNT0                              0x00000868
968 #define BNX2_MISC_ARB_GNT0_0                             (0x7L<<0)
969 #define BNX2_MISC_ARB_GNT0_1                             (0x7L<<4)
970 #define BNX2_MISC_ARB_GNT0_2                             (0x7L<<8)
971 #define BNX2_MISC_ARB_GNT0_3                             (0x7L<<12)
972 #define BNX2_MISC_ARB_GNT0_4                             (0x7L<<16)
973 #define BNX2_MISC_ARB_GNT0_5                             (0x7L<<20)
974 #define BNX2_MISC_ARB_GNT0_6                             (0x7L<<24)
975 #define BNX2_MISC_ARB_GNT0_7                             (0x7L<<28)
976
977 #define BNX2_MISC_ARB_GNT1                              0x0000086c
978 #define BNX2_MISC_ARB_GNT1_8                             (0x7L<<0)
979 #define BNX2_MISC_ARB_GNT1_9                             (0x7L<<4)
980 #define BNX2_MISC_ARB_GNT1_10                            (0x7L<<8)
981 #define BNX2_MISC_ARB_GNT1_11                            (0x7L<<12)
982 #define BNX2_MISC_ARB_GNT1_12                            (0x7L<<16)
983 #define BNX2_MISC_ARB_GNT1_13                            (0x7L<<20)
984 #define BNX2_MISC_ARB_GNT1_14                            (0x7L<<24)
985 #define BNX2_MISC_ARB_GNT1_15                            (0x7L<<28)
986
987 #define BNX2_MISC_ARB_GNT2                              0x00000870
988 #define BNX2_MISC_ARB_GNT2_16                            (0x7L<<0)
989 #define BNX2_MISC_ARB_GNT2_17                            (0x7L<<4)
990 #define BNX2_MISC_ARB_GNT2_18                            (0x7L<<8)
991 #define BNX2_MISC_ARB_GNT2_19                            (0x7L<<12)
992 #define BNX2_MISC_ARB_GNT2_20                            (0x7L<<16)
993 #define BNX2_MISC_ARB_GNT2_21                            (0x7L<<20)
994 #define BNX2_MISC_ARB_GNT2_22                            (0x7L<<24)
995 #define BNX2_MISC_ARB_GNT2_23                            (0x7L<<28)
996
997 #define BNX2_MISC_ARB_GNT3                              0x00000874
998 #define BNX2_MISC_ARB_GNT3_24                            (0x7L<<0)
999 #define BNX2_MISC_ARB_GNT3_25                            (0x7L<<4)
1000 #define BNX2_MISC_ARB_GNT3_26                            (0x7L<<8)
1001 #define BNX2_MISC_ARB_GNT3_27                            (0x7L<<12)
1002 #define BNX2_MISC_ARB_GNT3_28                            (0x7L<<16)
1003 #define BNX2_MISC_ARB_GNT3_29                            (0x7L<<20)
1004 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
1005 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
1006
1007 #define BNX2_MISC_RESERVED1                             0x00000878
1008 #define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE         (0x3fL<<0)
1009
1010 #define BNX2_MISC_RESERVED2                             0x0000087c
1011 #define BNX2_MISC_RESERVED2_PCIE_DIS                     (1L<<0)
1012 #define BNX2_MISC_RESERVED2_LINK_IN_L23                  (1L<<1)
1013
1014 #define BNX2_MISC_SM_ASF_CONTROL                        0x00000880
1015 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
1016 #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN                  (1L<<1)
1017 #define BNX2_MISC_SM_ASF_CONTROL_WG_TO                   (1L<<2)
1018 #define BNX2_MISC_SM_ASF_CONTROL_HB_TO                   (1L<<3)
1019 #define BNX2_MISC_SM_ASF_CONTROL_PA_TO                   (1L<<4)
1020 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
1021 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
1022 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
1023 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN              (1L<<8)
1024 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE           (1L<<9)
1025 #define BNX2_MISC_SM_ASF_CONTROL_RES                     (0x3L<<10)
1026 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
1027 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
1028 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
1029 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
1030 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x7fL<<16)
1031 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x7fL<<23)
1032 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
1033 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
1034
1035 #define BNX2_MISC_SMB_IN                                0x00000884
1036 #define BNX2_MISC_SMB_IN_DAT_IN                          (0xffL<<0)
1037 #define BNX2_MISC_SMB_IN_RDY                             (1L<<8)
1038 #define BNX2_MISC_SMB_IN_DONE                            (1L<<9)
1039 #define BNX2_MISC_SMB_IN_FIRSTBYTE                       (1L<<10)
1040 #define BNX2_MISC_SMB_IN_STATUS                          (0x7L<<11)
1041 #define BNX2_MISC_SMB_IN_STATUS_OK                       (0x0L<<11)
1042 #define BNX2_MISC_SMB_IN_STATUS_PEC                      (0x1L<<11)
1043 #define BNX2_MISC_SMB_IN_STATUS_OFLOW                    (0x2L<<11)
1044 #define BNX2_MISC_SMB_IN_STATUS_STOP                     (0x3L<<11)
1045 #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT                  (0x4L<<11)
1046
1047 #define BNX2_MISC_SMB_OUT                               0x00000888
1048 #define BNX2_MISC_SMB_OUT_DAT_OUT                        (0xffL<<0)
1049 #define BNX2_MISC_SMB_OUT_RDY                            (1L<<8)
1050 #define BNX2_MISC_SMB_OUT_START                          (1L<<9)
1051 #define BNX2_MISC_SMB_OUT_LAST                           (1L<<10)
1052 #define BNX2_MISC_SMB_OUT_ACC_TYPE                       (1L<<11)
1053 #define BNX2_MISC_SMB_OUT_ENB_PEC                        (1L<<12)
1054 #define BNX2_MISC_SMB_OUT_GET_RX_LEN                     (1L<<13)
1055 #define BNX2_MISC_SMB_OUT_SMB_READ_LEN                   (0x3fL<<14)
1056 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
1057 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
1058 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
1059 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
1060 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
1061 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
1062 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
1063 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (6L<<20)
1064 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
1065 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
1066 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
1067 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
1068 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
1069 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN                 (1L<<27)
1070 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN                 (1L<<28)
1071
1072 #define BNX2_MISC_SMB_WATCHDOG                          0x0000088c
1073 #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG                  (0xffffL<<0)
1074
1075 #define BNX2_MISC_SMB_HEARTBEAT                         0x00000890
1076 #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT                (0xffffL<<0)
1077
1078 #define BNX2_MISC_SMB_POLL_ASF                          0x00000894
1079 #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF                  (0xffffL<<0)
1080
1081 #define BNX2_MISC_SMB_POLL_LEGACY                       0x00000898
1082 #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY            (0xffffL<<0)
1083
1084 #define BNX2_MISC_SMB_RETRAN                            0x0000089c
1085 #define BNX2_MISC_SMB_RETRAN_RETRAN                      (0xffL<<0)
1086
1087 #define BNX2_MISC_SMB_TIMESTAMP                         0x000008a0
1088 #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP                (0xffffffffL<<0)
1089
1090 #define BNX2_MISC_PERR_ENA0                             0x000008a4
1091 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC                (1L<<0)
1092 #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF                (1L<<1)
1093 #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD               (1L<<2)
1094 #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC                 (1L<<3)
1095 #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF                 (1L<<4)
1096 #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD                (1L<<5)
1097 #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM                 (1L<<6)
1098 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0               (1L<<7)
1099 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1               (1L<<8)
1100 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2               (1L<<9)
1101 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3               (1L<<10)
1102 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4               (1L<<11)
1103 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5               (1L<<12)
1104 #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL               (1L<<13)
1105 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0                (1L<<14)
1106 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1                (1L<<15)
1107 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2                (1L<<16)
1108 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3                (1L<<17)
1109 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4                (1L<<18)
1110 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0                (1L<<19)
1111 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1                (1L<<20)
1112 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2                (1L<<21)
1113 #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA                  (1L<<22)
1114 #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF                (1L<<23)
1115 #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD               (1L<<24)
1116 #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX                  (1L<<25)
1117 #define BNX2_MISC_PERR_ENA0_RBDC_MISC                    (1L<<26)
1118 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB                 (1L<<27)
1119 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR                (1L<<28)
1120 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
1121 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
1122 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
1123 #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI          (1L<<0)
1124 #define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI           (1L<<1)
1125 #define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI     (1L<<2)
1126 #define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI     (1L<<3)
1127 #define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI         (1L<<4)
1128 #define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI         (1L<<5)
1129 #define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI        (1L<<6)
1130 #define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI          (1L<<7)
1131 #define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI         (1L<<8)
1132 #define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI           (1L<<9)
1133 #define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI          (1L<<10)
1134 #define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI         (1L<<11)
1135 #define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI          (1L<<12)
1136 #define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI         (1L<<13)
1137 #define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI        (1L<<14)
1138 #define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI          (1L<<15)
1139 #define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI         (1L<<16)
1140 #define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI           (1L<<17)
1141 #define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI            (1L<<18)
1142 #define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI      (1L<<19)
1143 #define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI      (1L<<20)
1144 #define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI       (1L<<21)
1145 #define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI      (1L<<22)
1146 #define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI       (1L<<23)
1147 #define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI       (1L<<24)
1148 #define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI      (1L<<25)
1149 #define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI      (1L<<26)
1150 #define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI             (1L<<27)
1151 #define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI             (1L<<28)
1152 #define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI              (1L<<29)
1153 #define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI              (1L<<30)
1154 #define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI           (1L<<31)
1155
1156 #define BNX2_MISC_PERR_ENA1                             0x000008a8
1157 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
1158 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM             (1L<<1)
1159 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM             (1L<<2)
1160 #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC                (1L<<3)
1161 #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF                (1L<<4)
1162 #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD               (1L<<5)
1163 #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC               (1L<<6)
1164 #define BNX2_MISC_PERR_ENA1_TBDC_MISC                    (1L<<7)
1165 #define BNX2_MISC_PERR_ENA1_TDMA_MISC                    (1L<<8)
1166 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0               (1L<<9)
1167 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1               (1L<<10)
1168 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF               (1L<<11)
1169 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD              (1L<<12)
1170 #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB                (1L<<13)
1171 #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR                 (1L<<14)
1172 #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC                (1L<<15)
1173 #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF                (1L<<16)
1174 #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD               (1L<<17)
1175 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX               (1L<<18)
1176 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX               (1L<<19)
1177 #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX                  (1L<<20)
1178 #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX                  (1L<<21)
1179 #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC                   (1L<<22)
1180 #define BNX2_MISC_PERR_ENA1_CSQ_MISC                     (1L<<23)
1181 #define BNX2_MISC_PERR_ENA1_CPQ_MISC                     (1L<<24)
1182 #define BNX2_MISC_PERR_ENA1_MCPQ_MISC                    (1L<<25)
1183 #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC                  (1L<<26)
1184 #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC                  (1L<<27)
1185 #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC                  (1L<<28)
1186 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
1187 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
1188 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
1189 #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI              (1L<<0)
1190 #define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI        (1L<<2)
1191 #define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI          (1L<<3)
1192 #define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI           (1L<<4)
1193 #define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI      (1L<<5)
1194 #define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI      (1L<<6)
1195 #define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI             (1L<<7)
1196 #define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI              (1L<<8)
1197 #define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI             (1L<<9)
1198 #define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI              (1L<<10)
1199 #define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI             (1L<<11)
1200 #define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI              (1L<<12)
1201 #define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI             (1L<<13)
1202 #define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI              (1L<<14)
1203 #define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI            (1L<<15)
1204 #define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI             (1L<<16)
1205 #define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI              (1L<<17)
1206 #define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI             (1L<<18)
1207 #define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI             (1L<<19)
1208 #define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI             (1L<<20)
1209 #define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI             (1L<<21)
1210 #define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI            (1L<<22)
1211 #define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI            (1L<<23)
1212 #define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI               (1L<<24)
1213 #define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI               (1L<<25)
1214 #define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI          (1L<<26)
1215 #define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI       (1L<<27)
1216 #define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI           (1L<<28)
1217 #define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI            (1L<<29)
1218
1219 #define BNX2_MISC_PERR_ENA2                             0x000008ac
1220 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
1221 #define BNX2_MISC_PERR_ENA2_COMXQ_MISC                   (1L<<1)
1222 #define BNX2_MISC_PERR_ENA2_COMTQ_MISC                   (1L<<2)
1223 #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC                   (1L<<3)
1224 #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC                   (1L<<4)
1225 #define BNX2_MISC_PERR_ENA2_TXPQ_MISC                    (1L<<5)
1226 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
1227 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
1228 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
1229 #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI          (1L<<0)
1230 #define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI            (1L<<1)
1231 #define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI            (1L<<2)
1232 #define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI           (1L<<3)
1233 #define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI         (1L<<4)
1234 #define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI            (1L<<5)
1235 #define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI       (1L<<6)
1236
1237 #define BNX2_MISC_DEBUG_VECTOR_SEL                      0x000008b0
1238 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
1239 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
1240 #define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI                  (0xfffL<<15)
1241
1242 #define BNX2_MISC_VREG_CONTROL                          0x000008b4
1243 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
1244 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI               (0xfL<<0)
1245 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI        (0L<<0)
1246 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI        (1L<<0)
1247 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI        (2L<<0)
1248 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI         (3L<<0)
1249 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI         (4L<<0)
1250 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI         (5L<<0)
1251 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI         (6L<<0)
1252 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI           (7L<<0)
1253 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI        (8L<<0)
1254 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI        (9L<<0)
1255 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI        (10L<<0)
1256 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI        (11L<<0)
1257 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI       (12L<<0)
1258 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI       (13L<<0)
1259 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI       (14L<<0)
1260 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI       (15L<<0)
1261 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
1262 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14                (0L<<4)
1263 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS12                (1L<<4)
1264 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS10                (2L<<4)
1265 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS8                 (3L<<4)
1266 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS6                 (4L<<4)
1267 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS4                 (5L<<4)
1268 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS2                 (6L<<4)
1269 #define BNX2_MISC_VREG_CONTROL_2_5_NOM                   (7L<<4)
1270 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS2                (8L<<4)
1271 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS4                (9L<<4)
1272 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS6                (10L<<4)
1273 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS8                (11L<<4)
1274 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS10               (12L<<4)
1275 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS12               (13L<<4)
1276 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS14               (14L<<4)
1277 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS16               (15L<<4)
1278 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT                  (0xfL<<8)
1279 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14           (0L<<8)
1280 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12           (1L<<8)
1281 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10           (2L<<8)
1282 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8            (3L<<8)
1283 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6            (4L<<8)
1284 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4            (5L<<8)
1285 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2            (6L<<8)
1286 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM              (7L<<8)
1287 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2           (8L<<8)
1288 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4           (9L<<8)
1289 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6           (10L<<8)
1290 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8           (11L<<8)
1291 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10          (12L<<8)
1292 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12          (13L<<8)
1293 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14          (14L<<8)
1294 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16          (15L<<8)
1295
1296 #define BNX2_MISC_FINAL_CLK_CTL_VAL                     0x000008b8
1297 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
1298
1299 #define BNX2_MISC_GP_HW_CTL0                            0x000008bc
1300 #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE                    (1L<<0)
1301 #define BNX2_MISC_GP_HW_CTL0_RMII_MODE                   (1L<<1)
1302 #define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL              (1L<<2)
1303 #define BNX2_MISC_GP_HW_CTL0_RVMII_MODE                  (1L<<3)
1304 #define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE  (1L<<4)
1305 #define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE       (1L<<5)
1306 #define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE    (1L<<6)
1307 #define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI                (0x7L<<4)
1308 #define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY         (1L<<7)
1309 #define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE     (1L<<8)
1310 #define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE         (1L<<9)
1311 #define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE              (1L<<10)
1312 #define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI                (0x7L<<8)
1313 #define BNX2_MISC_GP_HW_CTL0_UP1_DEF0                    (1L<<11)
1314 #define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF          (1L<<12)
1315 #define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF               (1L<<13)
1316 #define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF          (1L<<14)
1317 #define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF         (1L<<15)
1318 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI                 (0xfL<<16)
1319 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA             (0L<<16)
1320 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA           (1L<<16)
1321 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA           (3L<<16)
1322 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA           (5L<<16)
1323 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA           (7L<<16)
1324 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN           (15L<<16)
1325 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS             (1L<<20)
1326 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS             (1L<<21)
1327 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT                (0x3L<<22)
1328 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P            (0L<<22)
1329 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P            (1L<<22)
1330 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P            (2L<<22)
1331 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P            (3L<<22)
1332 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT                (0x3L<<24)
1333 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P            (0L<<24)
1334 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P            (1L<<24)
1335 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P            (2L<<24)
1336 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P            (3L<<24)
1337 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ            (0x3L<<26)
1338 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA      (0L<<26)
1339 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA      (1L<<26)
1340 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA      (2L<<26)
1341 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA      (3L<<26)
1342 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ           (0x3L<<28)
1343 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA     (0L<<28)
1344 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA     (1L<<28)
1345 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA     (2L<<28)
1346 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA     (3L<<28)
1347 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ            (0x3L<<30)
1348 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57       (0L<<30)
1349 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45       (1L<<30)
1350 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62       (2L<<30)
1351 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66       (3L<<30)
1352
1353 #define BNX2_MISC_GP_HW_CTL1                            0x000008c0
1354 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE         (1L<<0)
1355 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE         (1L<<1)
1356 #define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE          (1L<<2)
1357 #define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE          (1L<<3)
1358 #define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI            (0xffffL<<0)
1359 #define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI            (0xffffL<<16)
1360
1361 #define BNX2_MISC_NEW_HW_CTL                            0x000008c4
1362 #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS             (1L<<0)
1363 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE              (1L<<1)
1364 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0                (1L<<2)
1365 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1                (1L<<3)
1366 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED             (0xfffL<<4)
1367 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT              (0xffffL<<16)
1368
1369 #define BNX2_MISC_NEW_CORE_CTL                          0x000008c8
1370 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS      (1L<<0)
1371 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ          (1L<<1)
1372 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN              (0x3fffL<<2)
1373 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC               (0xffffL<<16)
1374
1375 #define BNX2_MISC_ECO_HW_CTL                            0x000008cc
1376 #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN          (1L<<0)
1377 #define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT               (0x7fffL<<1)
1378 #define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD               (0xffffL<<16)
1379
1380 #define BNX2_MISC_ECO_CORE_CTL                          0x000008d0
1381 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT             (0xffffL<<0)
1382 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD             (0xffffL<<16)
1383
1384 #define BNX2_MISC_PPIO                                  0x000008d4
1385 #define BNX2_MISC_PPIO_VALUE                             (0xfL<<0)
1386 #define BNX2_MISC_PPIO_SET                               (0xfL<<8)
1387 #define BNX2_MISC_PPIO_CLR                               (0xfL<<16)
1388 #define BNX2_MISC_PPIO_FLOAT                             (0xfL<<24)
1389
1390 #define BNX2_MISC_PPIO_INT                              0x000008d8
1391 #define BNX2_MISC_PPIO_INT_INT_STATE                     (0xfL<<0)
1392 #define BNX2_MISC_PPIO_INT_OLD_VALUE                     (0xfL<<8)
1393 #define BNX2_MISC_PPIO_INT_OLD_SET                       (0xfL<<16)
1394 #define BNX2_MISC_PPIO_INT_OLD_CLR                       (0xfL<<24)
1395
1396 #define BNX2_MISC_RESET_NUMS                            0x000008dc
1397 #define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS             (0x7L<<0)
1398 #define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS             (0x7L<<4)
1399 #define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS           (0x7L<<8)
1400 #define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS              (0x7L<<12)
1401 #define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS             (0x7L<<16)
1402
1403 #define BNX2_MISC_CS16_ERR                              0x000008e0
1404 #define BNX2_MISC_CS16_ERR_ENA_PCI                       (1L<<0)
1405 #define BNX2_MISC_CS16_ERR_ENA_RDMA                      (1L<<1)
1406 #define BNX2_MISC_CS16_ERR_ENA_TDMA                      (1L<<2)
1407 #define BNX2_MISC_CS16_ERR_ENA_EMAC                      (1L<<3)
1408 #define BNX2_MISC_CS16_ERR_ENA_CTX                       (1L<<4)
1409 #define BNX2_MISC_CS16_ERR_ENA_TBDR                      (1L<<5)
1410 #define BNX2_MISC_CS16_ERR_ENA_RBDC                      (1L<<6)
1411 #define BNX2_MISC_CS16_ERR_ENA_COM                       (1L<<7)
1412 #define BNX2_MISC_CS16_ERR_ENA_CP                        (1L<<8)
1413 #define BNX2_MISC_CS16_ERR_STA_PCI                       (1L<<16)
1414 #define BNX2_MISC_CS16_ERR_STA_RDMA                      (1L<<17)
1415 #define BNX2_MISC_CS16_ERR_STA_TDMA                      (1L<<18)
1416 #define BNX2_MISC_CS16_ERR_STA_EMAC                      (1L<<19)
1417 #define BNX2_MISC_CS16_ERR_STA_CTX                       (1L<<20)
1418 #define BNX2_MISC_CS16_ERR_STA_TBDR                      (1L<<21)
1419 #define BNX2_MISC_CS16_ERR_STA_RBDC                      (1L<<22)
1420 #define BNX2_MISC_CS16_ERR_STA_COM                       (1L<<23)
1421 #define BNX2_MISC_CS16_ERR_STA_CP                        (1L<<24)
1422
1423 #define BNX2_MISC_SPIO_EVENT                            0x000008e4
1424 #define BNX2_MISC_SPIO_EVENT_ENABLE                      (0xffL<<0)
1425
1426 #define BNX2_MISC_PPIO_EVENT                            0x000008e8
1427 #define BNX2_MISC_PPIO_EVENT_ENABLE                      (0xfL<<0)
1428
1429 #define BNX2_MISC_DUAL_MEDIA_CTRL                       0x000008ec
1430 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID                (0xffL<<0)
1431 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X              (0L<<0)
1432 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C              (3L<<0)
1433 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S              (12L<<0)
1434 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP         (0x7L<<8)
1435 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN          (1L<<11)
1436 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET         (1L<<12)
1437 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET         (1L<<13)
1438 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET            (1L<<14)
1439 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET            (1L<<15)
1440 #define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST              (1L<<16)
1441 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST            (1L<<17)
1442 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST            (1L<<18)
1443 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST               (1L<<19)
1444 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST               (1L<<20)
1445 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL               (0x7L<<21)
1446 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP              (1L<<24)
1447 #define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE         (1L<<25)
1448 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ        (0xfL<<26)
1449 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ      (1L<<26)
1450 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ      (2L<<26)
1451 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ      (4L<<26)
1452 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ      (8L<<26)
1453
1454 #define BNX2_MISC_OTP_CMD1                              0x000008f0
1455 #define BNX2_MISC_OTP_CMD1_FMODE                         (0x7L<<0)
1456 #define BNX2_MISC_OTP_CMD1_FMODE_IDLE                    (0L<<0)
1457 #define BNX2_MISC_OTP_CMD1_FMODE_WRITE                   (1L<<0)
1458 #define BNX2_MISC_OTP_CMD1_FMODE_INIT                    (2L<<0)
1459 #define BNX2_MISC_OTP_CMD1_FMODE_SET                     (3L<<0)
1460 #define BNX2_MISC_OTP_CMD1_FMODE_RST                     (4L<<0)
1461 #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY                  (5L<<0)
1462 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0               (6L<<0)
1463 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1               (7L<<0)
1464 #define BNX2_MISC_OTP_CMD1_USEPINS                       (1L<<8)
1465 #define BNX2_MISC_OTP_CMD1_PROGSEL                       (1L<<9)
1466 #define BNX2_MISC_OTP_CMD1_PROGSTART                     (1L<<10)
1467 #define BNX2_MISC_OTP_CMD1_PCOUNT                        (0x7L<<16)
1468 #define BNX2_MISC_OTP_CMD1_PBYP                          (1L<<19)
1469 #define BNX2_MISC_OTP_CMD1_VSEL                          (0xfL<<20)
1470 #define BNX2_MISC_OTP_CMD1_TM                            (0x7L<<27)
1471 #define BNX2_MISC_OTP_CMD1_SADBYP                        (1L<<30)
1472 #define BNX2_MISC_OTP_CMD1_DEBUG                         (1L<<31)
1473
1474 #define BNX2_MISC_OTP_CMD2                              0x000008f4
1475 #define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR                  (0x3ffL<<0)
1476 #define BNX2_MISC_OTP_CMD2_DOSEL                         (0x7fL<<16)
1477 #define BNX2_MISC_OTP_CMD2_DOSEL_0                       (0L<<16)
1478 #define BNX2_MISC_OTP_CMD2_DOSEL_1                       (1L<<16)
1479 #define BNX2_MISC_OTP_CMD2_DOSEL_127                     (127L<<16)
1480
1481 #define BNX2_MISC_OTP_STATUS                            0x000008f8
1482 #define BNX2_MISC_OTP_STATUS_DATA                        (0xffL<<0)
1483 #define BNX2_MISC_OTP_STATUS_VALID                       (1L<<8)
1484 #define BNX2_MISC_OTP_STATUS_BUSY                        (1L<<9)
1485 #define BNX2_MISC_OTP_STATUS_BUSYSM                      (1L<<10)
1486 #define BNX2_MISC_OTP_STATUS_DONE                        (1L<<11)
1487
1488 #define BNX2_MISC_OTP_SHIFT1_CMD                        0x000008fc
1489 #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N            (1L<<0)
1490 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE              (1L<<1)
1491 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START             (1L<<2)
1492 #define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA               (1L<<3)
1493 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT            (0x1fL<<8)
1494
1495 #define BNX2_MISC_OTP_SHIFT1_DATA                       0x00000900
1496 #define BNX2_MISC_OTP_SHIFT2_CMD                        0x00000904
1497 #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N            (1L<<0)
1498 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE              (1L<<1)
1499 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START             (1L<<2)
1500 #define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA               (1L<<3)
1501 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT            (0x1fL<<8)
1502
1503 #define BNX2_MISC_OTP_SHIFT2_DATA                       0x00000908
1504 #define BNX2_MISC_BIST_CS0                              0x0000090c
1505 #define BNX2_MISC_BIST_CS0_MBIST_EN                      (1L<<0)
1506 #define BNX2_MISC_BIST_CS0_BIST_SETUP                    (0x3L<<1)
1507 #define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET             (1L<<3)
1508 #define BNX2_MISC_BIST_CS0_MBIST_DONE                    (1L<<8)
1509 #define BNX2_MISC_BIST_CS0_MBIST_GO                      (1L<<9)
1510 #define BNX2_MISC_BIST_CS0_BIST_OVERRIDE                 (1L<<31)
1511
1512 #define BNX2_MISC_BIST_MEMSTATUS0                       0x00000910
1513 #define BNX2_MISC_BIST_CS1                              0x00000914
1514 #define BNX2_MISC_BIST_CS1_MBIST_EN                      (1L<<0)
1515 #define BNX2_MISC_BIST_CS1_BIST_SETUP                    (0x3L<<1)
1516 #define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET             (1L<<3)
1517 #define BNX2_MISC_BIST_CS1_MBIST_DONE                    (1L<<8)
1518 #define BNX2_MISC_BIST_CS1_MBIST_GO                      (1L<<9)
1519
1520 #define BNX2_MISC_BIST_MEMSTATUS1                       0x00000918
1521 #define BNX2_MISC_BIST_CS2                              0x0000091c
1522 #define BNX2_MISC_BIST_CS2_MBIST_EN                      (1L<<0)
1523 #define BNX2_MISC_BIST_CS2_BIST_SETUP                    (0x3L<<1)
1524 #define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET             (1L<<3)
1525 #define BNX2_MISC_BIST_CS2_MBIST_DONE                    (1L<<8)
1526 #define BNX2_MISC_BIST_CS2_MBIST_GO                      (1L<<9)
1527
1528 #define BNX2_MISC_BIST_MEMSTATUS2                       0x00000920
1529 #define BNX2_MISC_BIST_CS3                              0x00000924
1530 #define BNX2_MISC_BIST_CS3_MBIST_EN                      (1L<<0)
1531 #define BNX2_MISC_BIST_CS3_BIST_SETUP                    (0x3L<<1)
1532 #define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET             (1L<<3)
1533 #define BNX2_MISC_BIST_CS3_MBIST_DONE                    (1L<<8)
1534 #define BNX2_MISC_BIST_CS3_MBIST_GO                      (1L<<9)
1535
1536 #define BNX2_MISC_BIST_MEMSTATUS3                       0x00000928
1537 #define BNX2_MISC_BIST_CS4                              0x0000092c
1538 #define BNX2_MISC_BIST_CS4_MBIST_EN                      (1L<<0)
1539 #define BNX2_MISC_BIST_CS4_BIST_SETUP                    (0x3L<<1)
1540 #define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET             (1L<<3)
1541 #define BNX2_MISC_BIST_CS4_MBIST_DONE                    (1L<<8)
1542 #define BNX2_MISC_BIST_CS4_MBIST_GO                      (1L<<9)
1543
1544 #define BNX2_MISC_BIST_MEMSTATUS4                       0x00000930
1545 #define BNX2_MISC_BIST_CS5                              0x00000934
1546 #define BNX2_MISC_BIST_CS5_MBIST_EN                      (1L<<0)
1547 #define BNX2_MISC_BIST_CS5_BIST_SETUP                    (0x3L<<1)
1548 #define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET             (1L<<3)
1549 #define BNX2_MISC_BIST_CS5_MBIST_DONE                    (1L<<8)
1550 #define BNX2_MISC_BIST_CS5_MBIST_GO                      (1L<<9)
1551
1552 #define BNX2_MISC_BIST_MEMSTATUS5                       0x00000938
1553 #define BNX2_MISC_MEM_TM0                               0x0000093c
1554 #define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM                 (0xfL<<0)
1555 #define BNX2_MISC_MEM_TM0_MCP_SCPAD                      (0xfL<<8)
1556 #define BNX2_MISC_MEM_TM0_UMP_TM                         (0xffL<<16)
1557 #define BNX2_MISC_MEM_TM0_HB_MEM_TM                      (0xfL<<24)
1558
1559 #define BNX2_MISC_USPLL_CTRL                            0x00000940
1560 #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS                  (1L<<0)
1561 #define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS                (1L<<1)
1562 #define BNX2_MISC_USPLL_CTRL_LCPX                        (0x3fL<<2)
1563 #define BNX2_MISC_USPLL_CTRL_RX                          (0x3L<<8)
1564 #define BNX2_MISC_USPLL_CTRL_VC_EN                       (1L<<10)
1565 #define BNX2_MISC_USPLL_CTRL_VCO_MG                      (0x3L<<11)
1566 #define BNX2_MISC_USPLL_CTRL_KVCO_XF                     (0x7L<<13)
1567 #define BNX2_MISC_USPLL_CTRL_KVCO_XS                     (0x7L<<16)
1568 #define BNX2_MISC_USPLL_CTRL_TESTD_EN                    (1L<<19)
1569 #define BNX2_MISC_USPLL_CTRL_TESTD_SEL                   (0x7L<<20)
1570 #define BNX2_MISC_USPLL_CTRL_TESTA_EN                    (1L<<23)
1571 #define BNX2_MISC_USPLL_CTRL_TESTA_SEL                   (0x3L<<24)
1572 #define BNX2_MISC_USPLL_CTRL_ATTEN_FREF                  (1L<<26)
1573 #define BNX2_MISC_USPLL_CTRL_DIGITAL_RST                 (1L<<27)
1574 #define BNX2_MISC_USPLL_CTRL_ANALOG_RST                  (1L<<28)
1575 #define BNX2_MISC_USPLL_CTRL_LOCK                        (1L<<29)
1576
1577 #define BNX2_MISC_PERR_STATUS0                          0x00000944
1578 #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR             (1L<<0)
1579 #define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR              (1L<<1)
1580 #define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR        (1L<<2)
1581 #define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR        (1L<<3)
1582 #define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR            (1L<<4)
1583 #define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR            (1L<<5)
1584 #define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR           (1L<<6)
1585 #define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR             (1L<<7)
1586 #define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR            (1L<<8)
1587 #define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR              (1L<<9)
1588 #define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR             (1L<<10)
1589 #define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR            (1L<<11)
1590 #define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR             (1L<<12)
1591 #define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR            (1L<<13)
1592 #define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR           (1L<<14)
1593 #define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR             (1L<<15)
1594 #define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR            (1L<<16)
1595 #define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR              (1L<<17)
1596 #define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR               (1L<<18)
1597 #define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR         (1L<<19)
1598 #define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR         (1L<<20)
1599 #define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR          (1L<<21)
1600 #define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR         (1L<<22)
1601 #define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR          (1L<<23)
1602 #define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR          (1L<<24)
1603 #define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR         (1L<<25)
1604 #define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR         (1L<<26)
1605 #define BNX2_MISC_PERR_STATUS0_TPBUF_PERR                (1L<<27)
1606 #define BNX2_MISC_PERR_STATUS0_THBUF_PERR                (1L<<28)
1607 #define BNX2_MISC_PERR_STATUS0_TDMA_PERR                 (1L<<29)
1608 #define BNX2_MISC_PERR_STATUS0_TBDC_PERR                 (1L<<30)
1609 #define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR              (1L<<31)
1610
1611 #define BNX2_MISC_PERR_STATUS1                          0x00000948
1612 #define BNX2_MISC_PERR_STATUS1_RBDC_PERR                 (1L<<0)
1613 #define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR           (1L<<2)
1614 #define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR             (1L<<3)
1615 #define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR              (1L<<4)
1616 #define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR         (1L<<5)
1617 #define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR         (1L<<6)
1618 #define BNX2_MISC_PERR_STATUS1_TPATQ_PERR                (1L<<7)
1619 #define BNX2_MISC_PERR_STATUS1_MCPQ_PERR                 (1L<<8)
1620 #define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR                (1L<<9)
1621 #define BNX2_MISC_PERR_STATUS1_TXPQ_PERR                 (1L<<10)
1622 #define BNX2_MISC_PERR_STATUS1_COMTQ_PERR                (1L<<11)
1623 #define BNX2_MISC_PERR_STATUS1_COMQ_PERR                 (1L<<12)
1624 #define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR                (1L<<13)
1625 #define BNX2_MISC_PERR_STATUS1_RXPQ_PERR                 (1L<<14)
1626 #define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR               (1L<<15)
1627 #define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR                (1L<<16)
1628 #define BNX2_MISC_PERR_STATUS1_TASQ_PERR                 (1L<<17)
1629 #define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR                (1L<<18)
1630 #define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR                (1L<<19)
1631 #define BNX2_MISC_PERR_STATUS1_COMXQ_PERR                (1L<<20)
1632 #define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR                (1L<<21)
1633 #define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR               (1L<<22)
1634 #define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR               (1L<<23)
1635 #define BNX2_MISC_PERR_STATUS1_CPQ_PERR                  (1L<<24)
1636 #define BNX2_MISC_PERR_STATUS1_CSQ_PERR                  (1L<<25)
1637 #define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR             (1L<<26)
1638 #define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR          (1L<<27)
1639 #define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR              (1L<<28)
1640 #define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR               (1L<<29)
1641
1642 #define BNX2_MISC_PERR_STATUS2                          0x0000094c
1643 #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR             (1L<<0)
1644 #define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR               (1L<<1)
1645 #define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR               (1L<<2)
1646 #define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR              (1L<<3)
1647 #define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR            (1L<<4)
1648 #define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR               (1L<<5)
1649 #define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR          (1L<<6)
1650
1651 #define BNX2_MISC_LCPLL_CTRL0                           0x00000950
1652 #define BNX2_MISC_LCPLL_CTRL0_OAC                        (0x7L<<0)
1653 #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY              (0L<<0)
1654 #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO                   (1L<<0)
1655 #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY                 (3L<<0)
1656 #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY                  (7L<<0)
1657 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL                   (0x7L<<3)
1658 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360               (0L<<3)
1659 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480               (1L<<3)
1660 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600               (3L<<3)
1661 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720               (7L<<3)
1662 #define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL                  (0x3L<<6)
1663 #define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE                (0x7L<<8)
1664 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL                   (0x3L<<11)
1665 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0                 (0L<<11)
1666 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1                 (1L<<11)
1667 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2                 (2L<<11)
1668 #define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART                (1L<<13)
1669 #define BNX2_MISC_LCPLL_CTRL0_RESERVED                   (1L<<14)
1670 #define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN                (1L<<15)
1671 #define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN             (1L<<16)
1672 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN          (1L<<17)
1673 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN            (1L<<18)
1674 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN           (1L<<19)
1675 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE              (1L<<20)
1676 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS              (1L<<21)
1677 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN         (1L<<22)
1678 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE            (1L<<23)
1679 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN         (1L<<24)
1680 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS            (1L<<25)
1681 #define BNX2_MISC_LCPLL_CTRL0_CAPRESTART                 (1L<<26)
1682 #define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN              (1L<<27)
1683
1684 #define BNX2_MISC_LCPLL_CTRL1                           0x00000954
1685 #define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM                 (0x1fL<<0)
1686 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN        (1L<<5)
1687 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN           (1L<<6)
1688 #define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR                 (1L<<7)
1689
1690 #define BNX2_MISC_LCPLL_STATUS                          0x00000958
1691 #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM               (1L<<0)
1692 #define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM               (1L<<1)
1693 #define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE                (1L<<2)
1694 #define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS                (1L<<3)
1695 #define BNX2_MISC_LCPLL_STATUS_PLLSTATE                  (0x7L<<4)
1696 #define BNX2_MISC_LCPLL_STATUS_CAPSTATE                  (0x7L<<7)
1697 #define BNX2_MISC_LCPLL_STATUS_CAPSELECT                 (0x1fL<<10)
1698 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR          (1L<<15)
1699 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0        (0L<<15)
1700 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1        (1L<<15)
1701
1702 #define BNX2_MISC_OSCFUNDS_CTRL                         0x0000095c
1703 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON                 (1L<<5)
1704 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF             (0L<<5)
1705 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON              (1L<<5)
1706 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM               (0x3L<<6)
1707 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0             (0L<<6)
1708 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1             (1L<<6)
1709 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2             (2L<<6)
1710 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3             (3L<<6)
1711 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ                (0x3L<<8)
1712 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0              (0L<<8)
1713 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1              (1L<<8)
1714 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2              (2L<<8)
1715 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3              (3L<<8)
1716 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ                 (0x3L<<10)
1717 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0               (0L<<10)
1718 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1               (1L<<10)
1719 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2               (2L<<10)
1720 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3               (3L<<10)
1721
1722
1723 /*
1724  *  nvm_reg definition
1725  *  offset: 0x6400
1726  */
1727 #define BNX2_NVM_COMMAND                                0x00006400
1728 #define BNX2_NVM_COMMAND_RST                             (1L<<0)
1729 #define BNX2_NVM_COMMAND_DONE                            (1L<<3)
1730 #define BNX2_NVM_COMMAND_DOIT                            (1L<<4)
1731 #define BNX2_NVM_COMMAND_WR                              (1L<<5)
1732 #define BNX2_NVM_COMMAND_ERASE                           (1L<<6)
1733 #define BNX2_NVM_COMMAND_FIRST                           (1L<<7)
1734 #define BNX2_NVM_COMMAND_LAST                            (1L<<8)
1735 #define BNX2_NVM_COMMAND_WREN                            (1L<<16)
1736 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
1737 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
1738 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
1739 #define BNX2_NVM_COMMAND_RD_ID                           (1L<<20)
1740 #define BNX2_NVM_COMMAND_RD_STATUS                       (1L<<21)
1741 #define BNX2_NVM_COMMAND_MODE_256                        (1L<<22)
1742
1743 #define BNX2_NVM_STATUS                                 0x00006404
1744 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
1745 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
1746 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
1747 #define BNX2_NVM_STATUS_SPI_FSM_STATE_XI                 (0x1fL<<0)
1748 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI        (0L<<0)
1749 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI        (1L<<0)
1750 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI        (2L<<0)
1751 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI         (3L<<0)
1752 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI         (4L<<0)
1753 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI       (5L<<0)
1754 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI         (6L<<0)
1755 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI         (7L<<0)
1756 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI         (8L<<0)
1757 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI  (9L<<0)
1758 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI  (10L<<0)
1759 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI  (11L<<0)
1760 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI   (12L<<0)
1761 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI   (13L<<0)
1762 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI   (14L<<0)
1763 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI   (15L<<0)
1764 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI   (16L<<0)
1765 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI         (17L<<0)
1766 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI     (18L<<0)
1767 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI        (19L<<0)
1768
1769 #define BNX2_NVM_WRITE                                  0x00006408
1770 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
1771 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG          (0L<<0)
1772 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK             (1L<<0)
1773 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA            (2L<<0)
1774 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK              (4L<<0)
1775 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
1776 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
1777 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
1778 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI             (1L<<0)
1779 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI             (2L<<0)
1780 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI           (4L<<0)
1781 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI           (8L<<0)
1782
1783 #define BNX2_NVM_ADDR                                   0x0000640c
1784 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
1785 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG            (0L<<0)
1786 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK               (1L<<0)
1787 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA              (2L<<0)
1788 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK                (4L<<0)
1789 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
1790 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
1791 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
1792 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI               (1L<<0)
1793 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI               (2L<<0)
1794 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI             (4L<<0)
1795 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI             (8L<<0)
1796
1797 #define BNX2_NVM_READ                                   0x00006410
1798 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
1799 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG            (0L<<0)
1800 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK               (1L<<0)
1801 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA              (2L<<0)
1802 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK                (4L<<0)
1803 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
1804 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
1805 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
1806 #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI               (1L<<0)
1807 #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI               (2L<<0)
1808 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI             (4L<<0)
1809 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI             (8L<<0)
1810
1811 #define BNX2_NVM_CFG1                                   0x00006414
1812 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
1813 #define BNX2_NVM_CFG1_BUFFER_MODE                        (1L<<1)
1814 #define BNX2_NVM_CFG1_PASS_MODE                          (1L<<2)
1815 #define BNX2_NVM_CFG1_BITBANG_MODE                       (1L<<3)
1816 #define BNX2_NVM_CFG1_STATUS_BIT                         (0x7L<<4)
1817 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY               (0L<<4)
1818 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
1819 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
1820 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
1821 #define BNX2_NVM_CFG1_STRAP_CONTROL_0                    (1L<<23)
1822 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
1823 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
1824 #define BNX2_NVM_CFG1_FW_USTRAP_1                        (1L<<26)
1825 #define BNX2_NVM_CFG1_FW_USTRAP_0                        (1L<<27)
1826 #define BNX2_NVM_CFG1_FW_USTRAP_2                        (1L<<28)
1827 #define BNX2_NVM_CFG1_FW_USTRAP_3                        (1L<<29)
1828 #define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN                   (1L<<30)
1829 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
1830
1831 #define BNX2_NVM_CFG2                                   0x00006418
1832 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
1833 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
1834 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
1835 #define BNX2_NVM_CFG2_READ_ID                            (0xffL<<24)
1836
1837 #define BNX2_NVM_CFG3                                   0x0000641c
1838 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
1839 #define BNX2_NVM_CFG3_WRITE_CMD                          (0xffL<<8)
1840 #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD                   (0xffL<<16)
1841 #define BNX2_NVM_CFG3_READ_CMD                           (0xffL<<24)
1842
1843 #define BNX2_NVM_SW_ARB                                 0x00006420
1844 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0                     (1L<<0)
1845 #define BNX2_NVM_SW_ARB_ARB_REQ_SET1                     (1L<<1)
1846 #define BNX2_NVM_SW_ARB_ARB_REQ_SET2                     (1L<<2)
1847 #define BNX2_NVM_SW_ARB_ARB_REQ_SET3                     (1L<<3)
1848 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0                     (1L<<4)
1849 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1                     (1L<<5)
1850 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2                     (1L<<6)
1851 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3                     (1L<<7)
1852 #define BNX2_NVM_SW_ARB_ARB_ARB0                         (1L<<8)
1853 #define BNX2_NVM_SW_ARB_ARB_ARB1                         (1L<<9)
1854 #define BNX2_NVM_SW_ARB_ARB_ARB2                         (1L<<10)
1855 #define BNX2_NVM_SW_ARB_ARB_ARB3                         (1L<<11)
1856 #define BNX2_NVM_SW_ARB_REQ0                             (1L<<12)
1857 #define BNX2_NVM_SW_ARB_REQ1                             (1L<<13)
1858 #define BNX2_NVM_SW_ARB_REQ2                             (1L<<14)
1859 #define BNX2_NVM_SW_ARB_REQ3                             (1L<<15)
1860
1861 #define BNX2_NVM_ACCESS_ENABLE                          0x00006424
1862 #define BNX2_NVM_ACCESS_ENABLE_EN                        (1L<<0)
1863 #define BNX2_NVM_ACCESS_ENABLE_WR_EN                     (1L<<1)
1864
1865 #define BNX2_NVM_WRITE1                                 0x00006428
1866 #define BNX2_NVM_WRITE1_WREN_CMD                         (0xffL<<0)
1867 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
1868 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
1869
1870 #define BNX2_NVM_CFG4                                   0x0000642c
1871 #define BNX2_NVM_CFG4_FLASH_SIZE                         (0x7L<<0)
1872 #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT                   (0L<<0)
1873 #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT                   (1L<<0)
1874 #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT                   (2L<<0)
1875 #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT                   (3L<<0)
1876 #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT                  (4L<<0)
1877 #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT                  (5L<<0)
1878 #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT                  (6L<<0)
1879 #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT                 (7L<<0)
1880 #define BNX2_NVM_CFG4_FLASH_VENDOR                       (1L<<3)
1881 #define BNX2_NVM_CFG4_FLASH_VENDOR_ST                    (0L<<3)
1882 #define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL                 (1L<<3)
1883 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC             (0x3L<<4)
1884 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8        (0L<<4)
1885 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9        (1L<<4)
1886 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10       (2L<<4)
1887 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11       (3L<<4)
1888 #define BNX2_NVM_CFG4_STATUS_BIT_POLARITY                (1L<<6)
1889 #define BNX2_NVM_CFG4_RESERVED                           (0x1ffffffL<<7)
1890
1891 #define BNX2_NVM_RECONFIG                               0x00006430
1892 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE               (0xfL<<0)
1893 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST            (0L<<0)
1894 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL         (1L<<0)
1895 #define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE           (0xfL<<4)
1896 #define BNX2_NVM_RECONFIG_RESERVED                       (0x7fffffL<<8)
1897 #define BNX2_NVM_RECONFIG_RECONFIG_DONE                  (1L<<31)
1898
1899
1900
1901 /*
1902  *  dma_reg definition
1903  *  offset: 0xc00
1904  */
1905 #define BNX2_DMA_COMMAND                                0x00000c00
1906 #define BNX2_DMA_COMMAND_ENABLE                          (1L<<0)
1907
1908 #define BNX2_DMA_STATUS                                 0x00000c04
1909 #define BNX2_DMA_STATUS_PAR_ERROR_STATE                  (1L<<0)
1910 #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT              (1L<<16)
1911 #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT         (1L<<17)
1912 #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT          (1L<<18)
1913 #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT     (1L<<19)
1914 #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT   (1L<<20)
1915 #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT             (1L<<21)
1916 #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT        (1L<<22)
1917 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
1918 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
1919 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
1920 #define BNX2_DMA_STATUS_GLOBAL_ERR_XI                    (1L<<0)
1921 #define BNX2_DMA_STATUS_BME_XI                           (1L<<4)
1922
1923 #define BNX2_DMA_CONFIG                                 0x00000c08
1924 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
1925 #define BNX2_DMA_CONFIG_DATA_WORD_SWAP                   (1L<<1)
1926 #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP                   (1L<<4)
1927 #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP                   (1L<<5)
1928 #define BNX2_DMA_CONFIG_ONE_DMA                          (1L<<6)
1929 #define BNX2_DMA_CONFIG_CNTL_TWO_DMA                     (1L<<7)
1930 #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE                   (1L<<8)
1931 #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA               (1L<<10)
1932 #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY                (1L<<11)
1933 #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE                 (0xfL<<12)
1934 #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE                 (0xfL<<16)
1935 #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS                 (0x7L<<20)
1936 #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP                 (1L<<23)
1937 #define BNX2_DMA_CONFIG_BIG_SIZE                         (0xfL<<24)
1938 #define BNX2_DMA_CONFIG_BIG_SIZE_NONE                    (0x0L<<24)
1939 #define BNX2_DMA_CONFIG_BIG_SIZE_64                      (0x1L<<24)
1940 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
1941 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
1942 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
1943 #define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI               (0x3L<<0)
1944 #define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI               (0x3L<<4)
1945 #define BNX2_DMA_CONFIG_MAX_PL_XI                        (0x7L<<12)
1946 #define BNX2_DMA_CONFIG_MAX_PL_128B_XI                   (0L<<12)
1947 #define BNX2_DMA_CONFIG_MAX_PL_256B_XI                   (1L<<12)
1948 #define BNX2_DMA_CONFIG_MAX_PL_512B_XI                   (2L<<12)
1949 #define BNX2_DMA_CONFIG_MAX_PL_EN_XI                     (1L<<15)
1950 #define BNX2_DMA_CONFIG_MAX_RRS_XI                       (0x7L<<16)
1951 #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI                  (0L<<16)
1952 #define BNX2_DMA_CONFIG_MAX_RRS_256B_XI                  (1L<<16)
1953 #define BNX2_DMA_CONFIG_MAX_RRS_512B_XI                  (2L<<16)
1954 #define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI                 (3L<<16)
1955 #define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI                 (4L<<16)
1956 #define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI                 (5L<<16)
1957 #define BNX2_DMA_CONFIG_MAX_RRS_EN_XI                    (1L<<19)
1958 #define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI                  (1L<<31)
1959
1960 #define BNX2_DMA_BLACKOUT                               0x00000c0c
1961 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
1962 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
1963 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
1964
1965 #define BNX2_DMA_READ_MASTER_SETTING_0                  0x00000c10
1966 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP     (1L<<0)
1967 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER  (1L<<1)
1968 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY     (1L<<2)
1969 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS        (0x7L<<4)
1970 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN     (1L<<7)
1971 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP     (1L<<8)
1972 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER  (1L<<9)
1973 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY     (1L<<10)
1974 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS        (0x7L<<12)
1975 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN     (1L<<15)
1976 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP     (1L<<16)
1977 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER  (1L<<17)
1978 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY     (1L<<18)
1979 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS        (0x7L<<20)
1980 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN     (1L<<23)
1981 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP      (1L<<24)
1982 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER   (1L<<25)
1983 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY      (1L<<26)
1984 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS         (0x7L<<28)
1985 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN      (1L<<31)
1986
1987 #define BNX2_DMA_READ_MASTER_SETTING_1                  0x00000c14
1988 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP      (1L<<0)
1989 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER   (1L<<1)
1990 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY      (1L<<2)
1991 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS         (0x7L<<4)
1992 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN      (1L<<7)
1993 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP       (1L<<8)
1994 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER    (1L<<9)
1995 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY       (1L<<10)
1996 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS  (0x7L<<12)
1997 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN       (1L<<15)
1998
1999 #define BNX2_DMA_WRITE_MASTER_SETTING_0                 0x00000c18
2000 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP      (1L<<0)
2001 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER   (1L<<1)
2002 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY      (1L<<2)
2003 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD        (1L<<3)
2004 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS         (0x7L<<4)
2005 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN      (1L<<7)
2006 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP    (1L<<8)
2007 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER         (1L<<9)
2008 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY    (1L<<10)
2009 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD      (1L<<11)
2010 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS       (0x7L<<12)
2011 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN    (1L<<15)
2012 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP     (1L<<24)
2013 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER  (1L<<25)
2014 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY     (1L<<26)
2015 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD       (1L<<27)
2016 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS        (0x7L<<28)
2017 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN     (1L<<31)
2018
2019 #define BNX2_DMA_WRITE_MASTER_SETTING_1                 0x00000c1c
2020 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP     (1L<<0)
2021 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER  (1L<<1)
2022 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY     (1L<<2)
2023 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD       (1L<<3)
2024 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS        (0x7L<<4)
2025 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN     (1L<<7)
2026 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP      (1L<<8)
2027 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER   (1L<<9)
2028 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY      (1L<<10)
2029 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD        (1L<<11)
2030 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS         (0x7L<<12)
2031 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN      (1L<<15)
2032
2033 #define BNX2_DMA_ARBITER                                0x00000c20
2034 #define BNX2_DMA_ARBITER_NUM_READS                       (0x7L<<0)
2035 #define BNX2_DMA_ARBITER_WR_ARB_MODE                     (1L<<4)
2036 #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT              (0L<<4)
2037 #define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN             (1L<<4)
2038 #define BNX2_DMA_ARBITER_RD_ARB_MODE                     (0x3L<<5)
2039 #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT              (0L<<5)
2040 #define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN             (1L<<5)
2041 #define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN         (2L<<5)
2042 #define BNX2_DMA_ARBITER_ALT_MODE_EN                     (1L<<8)
2043 #define BNX2_DMA_ARBITER_RR_MODE                         (1L<<9)
2044 #define BNX2_DMA_ARBITER_TIMER_MODE                      (1L<<10)
2045 #define BNX2_DMA_ARBITER_OUSTD_READ_REQ                  (0xfL<<12)
2046
2047 #define BNX2_DMA_ARB_TIMERS                             0x00000c24
2048 #define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME             (0xffL<<0)
2049 #define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT               (0xffL<<12)
2050 #define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT               (0xfffL<<20)
2051
2052 #define BNX2_DMA_DEBUG_VECT_PEEK                        0x00000c2c
2053 #define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffL<<0)
2054 #define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
2055 #define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
2056 #define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffL<<16)
2057 #define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
2058 #define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
2059
2060 #define BNX2_DMA_TAG_RAM_00                             0x00000c30
2061 #define BNX2_DMA_TAG_RAM_00_CHANNEL                      (0xfL<<0)
2062 #define BNX2_DMA_TAG_RAM_00_MASTER                       (0x7L<<4)
2063 #define BNX2_DMA_TAG_RAM_00_MASTER_CTX                   (0L<<4)
2064 #define BNX2_DMA_TAG_RAM_00_MASTER_RBDC                  (1L<<4)
2065 #define BNX2_DMA_TAG_RAM_00_MASTER_TBDC                  (2L<<4)
2066 #define BNX2_DMA_TAG_RAM_00_MASTER_COM                   (3L<<4)
2067 #define BNX2_DMA_TAG_RAM_00_MASTER_CP                    (4L<<4)
2068 #define BNX2_DMA_TAG_RAM_00_MASTER_TDMA                  (5L<<4)
2069 #define BNX2_DMA_TAG_RAM_00_SWAP                         (0x3L<<7)
2070 #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG                  (0L<<7)
2071 #define BNX2_DMA_TAG_RAM_00_SWAP_DATA                    (1L<<7)
2072 #define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL                 (2L<<7)
2073 #define BNX2_DMA_TAG_RAM_00_FUNCTION                     (1L<<9)
2074 #define BNX2_DMA_TAG_RAM_00_VALID                        (1L<<10)
2075
2076 #define BNX2_DMA_TAG_RAM_01                             0x00000c34
2077 #define BNX2_DMA_TAG_RAM_01_CHANNEL                      (0xfL<<0)
2078 #define BNX2_DMA_TAG_RAM_01_MASTER                       (0x7L<<4)
2079 #define BNX2_DMA_TAG_RAM_01_MASTER_CTX                   (0L<<4)
2080 #define BNX2_DMA_TAG_RAM_01_MASTER_RBDC                  (1L<<4)
2081 #define BNX2_DMA_TAG_RAM_01_MASTER_TBDC                  (2L<<4)
2082 #define BNX2_DMA_TAG_RAM_01_MASTER_COM                   (3L<<4)
2083 #define BNX2_DMA_TAG_RAM_01_MASTER_CP                    (4L<<4)
2084 #define BNX2_DMA_TAG_RAM_01_MASTER_TDMA                  (5L<<4)
2085 #define BNX2_DMA_TAG_RAM_01_SWAP                         (0x3L<<7)
2086 #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG                  (0L<<7)
2087 #define BNX2_DMA_TAG_RAM_01_SWAP_DATA                    (1L<<7)
2088 #define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL                 (2L<<7)
2089 #define BNX2_DMA_TAG_RAM_01_FUNCTION                     (1L<<9)
2090 #define BNX2_DMA_TAG_RAM_01_VALID                        (1L<<10)
2091
2092 #define BNX2_DMA_TAG_RAM_02                             0x00000c38
2093 #define BNX2_DMA_TAG_RAM_02_CHANNEL                      (0xfL<<0)
2094 #define BNX2_DMA_TAG_RAM_02_MASTER                       (0x7L<<4)
2095 #define BNX2_DMA_TAG_RAM_02_MASTER_CTX                   (0L<<4)
2096 #define BNX2_DMA_TAG_RAM_02_MASTER_RBDC                  (1L<<4)
2097 #define BNX2_DMA_TAG_RAM_02_MASTER_TBDC                  (2L<<4)
2098 #define BNX2_DMA_TAG_RAM_02_MASTER_COM                   (3L<<4)
2099 #define BNX2_DMA_TAG_RAM_02_MASTER_CP                    (4L<<4)
2100 #define BNX2_DMA_TAG_RAM_02_MASTER_TDMA                  (5L<<4)
2101 #define BNX2_DMA_TAG_RAM_02_SWAP                         (0x3L<<7)
2102 #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG                  (0L<<7)
2103 #define BNX2_DMA_TAG_RAM_02_SWAP_DATA                    (1L<<7)
2104 #define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL                 (2L<<7)
2105 #define BNX2_DMA_TAG_RAM_02_FUNCTION                     (1L<<9)
2106 #define BNX2_DMA_TAG_RAM_02_VALID                        (1L<<10)
2107
2108 #define BNX2_DMA_TAG_RAM_03                             0x00000c3c
2109 #define BNX2_DMA_TAG_RAM_03_CHANNEL                      (0xfL<<0)
2110 #define BNX2_DMA_TAG_RAM_03_MASTER                       (0x7L<<4)
2111 #define BNX2_DMA_TAG_RAM_03_MASTER_CTX                   (0L<<4)
2112 #define BNX2_DMA_TAG_RAM_03_MASTER_RBDC                  (1L<<4)
2113 #define BNX2_DMA_TAG_RAM_03_MASTER_TBDC                  (2L<<4)
2114 #define BNX2_DMA_TAG_RAM_03_MASTER_COM                   (3L<<4)
2115 #define BNX2_DMA_TAG_RAM_03_MASTER_CP                    (4L<<4)
2116 #define BNX2_DMA_TAG_RAM_03_MASTER_TDMA                  (5L<<4)
2117 #define BNX2_DMA_TAG_RAM_03_SWAP                         (0x3L<<7)
2118 #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG                  (0L<<7)
2119 #define BNX2_DMA_TAG_RAM_03_SWAP_DATA                    (1L<<7)
2120 #define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL                 (2L<<7)
2121 #define BNX2_DMA_TAG_RAM_03_FUNCTION                     (1L<<9)
2122 #define BNX2_DMA_TAG_RAM_03_VALID                        (1L<<10)
2123
2124 #define BNX2_DMA_TAG_RAM_04                             0x00000c40
2125 #define BNX2_DMA_TAG_RAM_04_CHANNEL                      (0xfL<<0)
2126 #define BNX2_DMA_TAG_RAM_04_MASTER                       (0x7L<<4)
2127 #define BNX2_DMA_TAG_RAM_04_MASTER_CTX                   (0L<<4)
2128 #define BNX2_DMA_TAG_RAM_04_MASTER_RBDC                  (1L<<4)
2129 #define BNX2_DMA_TAG_RAM_04_MASTER_TBDC                  (2L<<4)
2130 #define BNX2_DMA_TAG_RAM_04_MASTER_COM                   (3L<<4)
2131 #define BNX2_DMA_TAG_RAM_04_MASTER_CP                    (4L<<4)
2132 #define BNX2_DMA_TAG_RAM_04_MASTER_TDMA                  (5L<<4)
2133 #define BNX2_DMA_TAG_RAM_04_SWAP                         (0x3L<<7)
2134 #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG                  (0L<<7)
2135 #define BNX2_DMA_TAG_RAM_04_SWAP_DATA                    (1L<<7)
2136 #define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL                 (2L<<7)
2137 #define BNX2_DMA_TAG_RAM_04_FUNCTION                     (1L<<9)
2138 #define BNX2_DMA_TAG_RAM_04_VALID                        (1L<<10)
2139
2140 #define BNX2_DMA_TAG_RAM_05                             0x00000c44
2141 #define BNX2_DMA_TAG_RAM_05_CHANNEL                      (0xfL<<0)
2142 #define BNX2_DMA_TAG_RAM_05_MASTER                       (0x7L<<4)
2143 #define BNX2_DMA_TAG_RAM_05_MASTER_CTX                   (0L<<4)
2144 #define BNX2_DMA_TAG_RAM_05_MASTER_RBDC                  (1L<<4)
2145 #define BNX2_DMA_TAG_RAM_05_MASTER_TBDC                  (2L<<4)
2146 #define BNX2_DMA_TAG_RAM_05_MASTER_COM                   (3L<<4)
2147 #define BNX2_DMA_TAG_RAM_05_MASTER_CP                    (4L<<4)
2148 #define BNX2_DMA_TAG_RAM_05_MASTER_TDMA                  (5L<<4)
2149 #define BNX2_DMA_TAG_RAM_05_SWAP                         (0x3L<<7)
2150 #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG                  (0L<<7)
2151 #define BNX2_DMA_TAG_RAM_05_SWAP_DATA                    (1L<<7)
2152 #define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL                 (2L<<7)
2153 #define BNX2_DMA_TAG_RAM_05_FUNCTION                     (1L<<9)
2154 #define BNX2_DMA_TAG_RAM_05_VALID                        (1L<<10)
2155
2156 #define BNX2_DMA_TAG_RAM_06                             0x00000c48
2157 #define BNX2_DMA_TAG_RAM_06_CHANNEL                      (0xfL<<0)
2158 #define BNX2_DMA_TAG_RAM_06_MASTER                       (0x7L<<4)
2159 #define BNX2_DMA_TAG_RAM_06_MASTER_CTX                   (0L<<4)
2160 #define BNX2_DMA_TAG_RAM_06_MASTER_RBDC                  (1L<<4)
2161 #define BNX2_DMA_TAG_RAM_06_MASTER_TBDC                  (2L<<4)
2162 #define BNX2_DMA_TAG_RAM_06_MASTER_COM                   (3L<<4)
2163 #define BNX2_DMA_TAG_RAM_06_MASTER_CP                    (4L<<4)
2164 #define BNX2_DMA_TAG_RAM_06_MASTER_TDMA                  (5L<<4)
2165 #define BNX2_DMA_TAG_RAM_06_SWAP                         (0x3L<<7)
2166 #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG                  (0L<<7)
2167 #define BNX2_DMA_TAG_RAM_06_SWAP_DATA                    (1L<<7)
2168 #define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL                 (2L<<7)
2169 #define BNX2_DMA_TAG_RAM_06_FUNCTION                     (1L<<9)
2170 #define BNX2_DMA_TAG_RAM_06_VALID                        (1L<<10)
2171
2172 #define BNX2_DMA_TAG_RAM_07                             0x00000c4c
2173 #define BNX2_DMA_TAG_RAM_07_CHANNEL                      (0xfL<<0)
2174 #define BNX2_DMA_TAG_RAM_07_MASTER                       (0x7L<<4)
2175 #define BNX2_DMA_TAG_RAM_07_MASTER_CTX                   (0L<<4)
2176 #define BNX2_DMA_TAG_RAM_07_MASTER_RBDC                  (1L<<4)
2177 #define BNX2_DMA_TAG_RAM_07_MASTER_TBDC                  (2L<<4)
2178 #define BNX2_DMA_TAG_RAM_07_MASTER_COM                   (3L<<4)
2179 #define BNX2_DMA_TAG_RAM_07_MASTER_CP                    (4L<<4)
2180 #define BNX2_DMA_TAG_RAM_07_MASTER_TDMA                  (5L<<4)
2181 #define BNX2_DMA_TAG_RAM_07_SWAP                         (0x3L<<7)
2182 #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG                  (0L<<7)
2183 #define BNX2_DMA_TAG_RAM_07_SWAP_DATA                    (1L<<7)
2184 #define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL                 (2L<<7)
2185 #define BNX2_DMA_TAG_RAM_07_FUNCTION                     (1L<<9)
2186 #define BNX2_DMA_TAG_RAM_07_VALID                        (1L<<10)
2187
2188 #define BNX2_DMA_TAG_RAM_08                             0x00000c50
2189 #define BNX2_DMA_TAG_RAM_08_CHANNEL                      (0xfL<<0)
2190 #define BNX2_DMA_TAG_RAM_08_MASTER                       (0x7L<<4)
2191 #define BNX2_DMA_TAG_RAM_08_MASTER_CTX                   (0L<<4)
2192 #define BNX2_DMA_TAG_RAM_08_MASTER_RBDC                  (1L<<4)
2193 #define BNX2_DMA_TAG_RAM_08_MASTER_TBDC                  (2L<<4)
2194 #define BNX2_DMA_TAG_RAM_08_MASTER_COM                   (3L<<4)
2195 #define BNX2_DMA_TAG_RAM_08_MASTER_CP                    (4L<<4)
2196 #define BNX2_DMA_TAG_RAM_08_MASTER_TDMA                  (5L<<4)
2197 #define BNX2_DMA_TAG_RAM_08_SWAP                         (0x3L<<7)
2198 #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG                  (0L<<7)
2199 #define BNX2_DMA_TAG_RAM_08_SWAP_DATA                    (1L<<7)
2200 #define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL                 (2L<<7)
2201 #define BNX2_DMA_TAG_RAM_08_FUNCTION                     (1L<<9)
2202 #define BNX2_DMA_TAG_RAM_08_VALID                        (1L<<10)
2203
2204 #define BNX2_DMA_TAG_RAM_09                             0x00000c54
2205 #define BNX2_DMA_TAG_RAM_09_CHANNEL                      (0xfL<<0)
2206 #define BNX2_DMA_TAG_RAM_09_MASTER                       (0x7L<<4)
2207 #define BNX2_DMA_TAG_RAM_09_MASTER_CTX                   (0L<<4)
2208 #define BNX2_DMA_TAG_RAM_09_MASTER_RBDC                  (1L<<4)
2209 #define BNX2_DMA_TAG_RAM_09_MASTER_TBDC                  (2L<<4)
2210 #define BNX2_DMA_TAG_RAM_09_MASTER_COM                   (3L<<4)
2211 #define BNX2_DMA_TAG_RAM_09_MASTER_CP                    (4L<<4)
2212 #define BNX2_DMA_TAG_RAM_09_MASTER_TDMA                  (5L<<4)
2213 #define BNX2_DMA_TAG_RAM_09_SWAP                         (0x3L<<7)
2214 #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG                  (0L<<7)
2215 #define BNX2_DMA_TAG_RAM_09_SWAP_DATA                    (1L<<7)
2216 #define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL                 (2L<<7)
2217 #define BNX2_DMA_TAG_RAM_09_FUNCTION                     (1L<<9)
2218 #define BNX2_DMA_TAG_RAM_09_VALID                        (1L<<10)
2219
2220 #define BNX2_DMA_TAG_RAM_10                             0x00000c58
2221 #define BNX2_DMA_TAG_RAM_10_CHANNEL                      (0xfL<<0)
2222 #define BNX2_DMA_TAG_RAM_10_MASTER                       (0x7L<<4)
2223 #define BNX2_DMA_TAG_RAM_10_MASTER_CTX                   (0L<<4)
2224 #define BNX2_DMA_TAG_RAM_10_MASTER_RBDC                  (1L<<4)
2225 #define BNX2_DMA_TAG_RAM_10_MASTER_TBDC                  (2L<<4)
2226 #define BNX2_DMA_TAG_RAM_10_MASTER_COM                   (3L<<4)
2227 #define BNX2_DMA_TAG_RAM_10_MASTER_CP                    (4L<<4)
2228 #define BNX2_DMA_TAG_RAM_10_MASTER_TDMA                  (5L<<4)
2229 #define BNX2_DMA_TAG_RAM_10_SWAP                         (0x3L<<7)
2230 #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG                  (0L<<7)
2231 #define BNX2_DMA_TAG_RAM_10_SWAP_DATA                    (1L<<7)
2232 #define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL                 (2L<<7)
2233 #define BNX2_DMA_TAG_RAM_10_FUNCTION                     (1L<<9)
2234 #define BNX2_DMA_TAG_RAM_10_VALID                        (1L<<10)
2235
2236 #define BNX2_DMA_TAG_RAM_11                             0x00000c5c
2237 #define BNX2_DMA_TAG_RAM_11_CHANNEL                      (0xfL<<0)
2238 #define BNX2_DMA_TAG_RAM_11_MASTER                       (0x7L<<4)
2239 #define BNX2_DMA_TAG_RAM_11_MASTER_CTX                   (0L<<4)
2240 #define BNX2_DMA_TAG_RAM_11_MASTER_RBDC                  (1L<<4)
2241 #define BNX2_DMA_TAG_RAM_11_MASTER_TBDC                  (2L<<4)
2242 #define BNX2_DMA_TAG_RAM_11_MASTER_COM                   (3L<<4)
2243 #define BNX2_DMA_TAG_RAM_11_MASTER_CP                    (4L<<4)
2244 #define BNX2_DMA_TAG_RAM_11_MASTER_TDMA                  (5L<<4)
2245 #define BNX2_DMA_TAG_RAM_11_SWAP                         (0x3L<<7)
2246 #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG                  (0L<<7)
2247 #define BNX2_DMA_TAG_RAM_11_SWAP_DATA                    (1L<<7)
2248 #define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL                 (2L<<7)
2249 #define BNX2_DMA_TAG_RAM_11_FUNCTION                     (1L<<9)
2250 #define BNX2_DMA_TAG_RAM_11_VALID                        (1L<<10)
2251
2252 #define BNX2_DMA_RCHAN_STAT_22                          0x00000c60
2253 #define BNX2_DMA_RCHAN_STAT_30                          0x00000c64
2254 #define BNX2_DMA_RCHAN_STAT_31                          0x00000c68
2255 #define BNX2_DMA_RCHAN_STAT_32                          0x00000c6c
2256 #define BNX2_DMA_RCHAN_STAT_40                          0x00000c70
2257 #define BNX2_DMA_RCHAN_STAT_41                          0x00000c74
2258 #define BNX2_DMA_RCHAN_STAT_42                          0x00000c78
2259 #define BNX2_DMA_RCHAN_STAT_50                          0x00000c7c
2260 #define BNX2_DMA_RCHAN_STAT_51                          0x00000c80
2261 #define BNX2_DMA_RCHAN_STAT_52                          0x00000c84
2262 #define BNX2_DMA_RCHAN_STAT_60                          0x00000c88
2263 #define BNX2_DMA_RCHAN_STAT_61                          0x00000c8c
2264 #define BNX2_DMA_RCHAN_STAT_62                          0x00000c90
2265 #define BNX2_DMA_RCHAN_STAT_70                          0x00000c94
2266 #define BNX2_DMA_RCHAN_STAT_71                          0x00000c98
2267 #define BNX2_DMA_RCHAN_STAT_72                          0x00000c9c
2268 #define BNX2_DMA_WCHAN_STAT_00                          0x00000ca0
2269 #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
2270
2271 #define BNX2_DMA_WCHAN_STAT_01                          0x00000ca4
2272 #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
2273
2274 #define BNX2_DMA_WCHAN_STAT_02                          0x00000ca8
2275 #define BNX2_DMA_WCHAN_STAT_02_LENGTH                    (0xffffL<<0)
2276 #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP                 (1L<<16)
2277 #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
2278 #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
2279
2280 #define BNX2_DMA_WCHAN_STAT_10                          0x00000cac
2281 #define BNX2_DMA_WCHAN_STAT_11                          0x00000cb0
2282 #define BNX2_DMA_WCHAN_STAT_12                          0x00000cb4
2283 #define BNX2_DMA_WCHAN_STAT_20                          0x00000cb8
2284 #define BNX2_DMA_WCHAN_STAT_21                          0x00000cbc
2285 #define BNX2_DMA_WCHAN_STAT_22                          0x00000cc0
2286 #define BNX2_DMA_WCHAN_STAT_30                          0x00000cc4
2287 #define BNX2_DMA_WCHAN_STAT_31                          0x00000cc8
2288 #define BNX2_DMA_WCHAN_STAT_32                          0x00000ccc
2289 #define BNX2_DMA_WCHAN_STAT_40                          0x00000cd0
2290 #define BNX2_DMA_WCHAN_STAT_41                          0x00000cd4
2291 #define BNX2_DMA_WCHAN_STAT_42                          0x00000cd8
2292 #define BNX2_DMA_WCHAN_STAT_50                          0x00000cdc
2293 #define BNX2_DMA_WCHAN_STAT_51                          0x00000ce0
2294 #define BNX2_DMA_WCHAN_STAT_52                          0x00000ce4
2295 #define BNX2_DMA_WCHAN_STAT_60                          0x00000ce8
2296 #define BNX2_DMA_WCHAN_STAT_61                          0x00000cec
2297 #define BNX2_DMA_WCHAN_STAT_62                          0x00000cf0
2298 #define BNX2_DMA_WCHAN_STAT_70                          0x00000cf4
2299 #define BNX2_DMA_WCHAN_STAT_71                          0x00000cf8
2300 #define BNX2_DMA_WCHAN_STAT_72                          0x00000cfc
2301 #define BNX2_DMA_ARB_STAT_00                            0x00000d00
2302 #define BNX2_DMA_ARB_STAT_00_MASTER                      (0xffffL<<0)
2303 #define BNX2_DMA_ARB_STAT_00_MASTER_ENC                  (0xffL<<16)
2304 #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR                 (0xffL<<24)
2305
2306 #define BNX2_DMA_ARB_STAT_01                            0x00000d04
2307 #define BNX2_DMA_ARB_STAT_01_LPR_RPTR                    (0xfL<<0)
2308 #define BNX2_DMA_ARB_STAT_01_LPR_WPTR                    (0xfL<<4)
2309 #define BNX2_DMA_ARB_STAT_01_LPB_RPTR                    (0xfL<<8)
2310 #define BNX2_DMA_ARB_STAT_01_LPB_WPTR                    (0xfL<<12)
2311 #define BNX2_DMA_ARB_STAT_01_HPR_RPTR                    (0xfL<<16)
2312 #define BNX2_DMA_ARB_STAT_01_HPR_WPTR                    (0xfL<<20)
2313 #define BNX2_DMA_ARB_STAT_01_HPB_RPTR                    (0xfL<<24)
2314 #define BNX2_DMA_ARB_STAT_01_HPB_WPTR                    (0xfL<<28)
2315
2316 #define BNX2_DMA_FUSE_CTRL0_CMD                         0x00000f00
2317 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE               (1L<<0)
2318 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE               (1L<<1)
2319 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT                    (1L<<2)
2320 #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD                     (1L<<3)
2321 #define BNX2_DMA_FUSE_CTRL0_CMD_SEL                      (0xfL<<8)
2322
2323 #define BNX2_DMA_FUSE_CTRL0_DATA                        0x00000f04
2324 #define BNX2_DMA_FUSE_CTRL1_CMD                         0x00000f08
2325 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE               (1L<<0)
2326 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE               (1L<<1)
2327 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT                    (1L<<2)
2328 #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD                     (1L<<3)
2329 #define BNX2_DMA_FUSE_CTRL1_CMD_SEL                      (0xfL<<8)
2330
2331 #define BNX2_DMA_FUSE_CTRL1_DATA                        0x00000f0c
2332 #define BNX2_DMA_FUSE_CTRL2_CMD                         0x00000f10
2333 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE               (1L<<0)
2334 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE               (1L<<1)
2335 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT                    (1L<<2)
2336 #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD                     (1L<<3)
2337 #define BNX2_DMA_FUSE_CTRL2_CMD_SEL                      (0xfL<<8)
2338
2339 #define BNX2_DMA_FUSE_CTRL2_DATA                        0x00000f14
2340
2341
2342 /*
2343  *  context_reg definition
2344  *  offset: 0x1000
2345  */
2346 #define BNX2_CTX_COMMAND                                0x00001000
2347 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
2348 #define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT               (1L<<1)
2349 #define BNX2_CTX_COMMAND_DISABLE_PLRU                    (1L<<2)
2350 #define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ            (1L<<3)
2351 #define BNX2_CTX_COMMAND_FLUSH_AHEAD                     (0x1fL<<8)
2352 #define BNX2_CTX_COMMAND_MEM_INIT                        (1L<<13)
2353 #define BNX2_CTX_COMMAND_PAGE_SIZE                       (0xfL<<16)
2354 #define BNX2_CTX_COMMAND_PAGE_SIZE_256                   (0L<<16)
2355 #define BNX2_CTX_COMMAND_PAGE_SIZE_512                   (1L<<16)
2356 #define BNX2_CTX_COMMAND_PAGE_SIZE_1K                    (2L<<16)
2357 #define BNX2_CTX_COMMAND_PAGE_SIZE_2K                    (3L<<16)
2358 #define BNX2_CTX_COMMAND_PAGE_SIZE_4K                    (4L<<16)
2359 #define BNX2_CTX_COMMAND_PAGE_SIZE_8K                    (5L<<16)
2360 #define BNX2_CTX_COMMAND_PAGE_SIZE_16K                   (6L<<16)
2361 #define BNX2_CTX_COMMAND_PAGE_SIZE_32K                   (7L<<16)
2362 #define BNX2_CTX_COMMAND_PAGE_SIZE_64K                   (8L<<16)
2363 #define BNX2_CTX_COMMAND_PAGE_SIZE_128K                  (9L<<16)
2364 #define BNX2_CTX_COMMAND_PAGE_SIZE_256K                  (10L<<16)
2365 #define BNX2_CTX_COMMAND_PAGE_SIZE_512K                  (11L<<16)
2366 #define BNX2_CTX_COMMAND_PAGE_SIZE_1M                    (12L<<16)
2367
2368 #define BNX2_CTX_STATUS                                 0x00001004
2369 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
2370 #define BNX2_CTX_STATUS_READ_STAT                        (1L<<16)
2371 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
2372 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
2373 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
2374 #define BNX2_CTX_STATUS_EXT_READ_STAT                    (1L<<20)
2375 #define BNX2_CTX_STATUS_EXT_WRITE_STAT                   (1L<<21)
2376 #define BNX2_CTX_STATUS_MISS_STAT                        (1L<<22)
2377 #define BNX2_CTX_STATUS_HIT_STAT                         (1L<<23)
2378 #define BNX2_CTX_STATUS_DEAD_LOCK                        (1L<<24)
2379 #define BNX2_CTX_STATUS_USAGE_CNT_ERR                    (1L<<25)
2380 #define BNX2_CTX_STATUS_INVALID_PAGE                     (1L<<26)
2381
2382 #define BNX2_CTX_VIRT_ADDR                              0x00001008
2383 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
2384
2385 #define BNX2_CTX_PAGE_TBL                               0x0000100c
2386 #define BNX2_CTX_PAGE_TBL_PAGE_TBL                       (0x3fffL<<6)
2387
2388 #define BNX2_CTX_DATA_ADR                               0x00001010
2389 #define BNX2_CTX_DATA_ADR_DATA_ADR                       (0x7ffffL<<2)
2390
2391 #define BNX2_CTX_DATA                                   0x00001014
2392 #define BNX2_CTX_LOCK                                   0x00001018
2393 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
2394 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
2395 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
2396 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
2397 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
2398 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
2399 #define BNX2_CTX_LOCK_TYPE_VOID_XI                       (0L<<0)
2400 #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI                   (1L<<0)
2401 #define BNX2_CTX_LOCK_TYPE_TX_XI                         (2L<<0)
2402 #define BNX2_CTX_LOCK_TYPE_TIMER_XI                      (4L<<0)
2403 #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI                   (7L<<0)
2404 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
2405 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
2406 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
2407 #define BNX2_CTX_LOCK_MODE_UNLOCK                        (0x0L<<27)
2408 #define BNX2_CTX_LOCK_MODE_IMMEDIATE                     (0x1L<<27)
2409 #define BNX2_CTX_LOCK_MODE_SURE                          (0x2L<<27)
2410 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
2411 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
2412
2413 #define BNX2_CTX_CTX_CTRL                               0x0000101c
2414 #define BNX2_CTX_CTX_CTRL_CTX_ADDR                       (0x7ffffL<<2)
2415 #define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT                  (0x3L<<21)
2416 #define BNX2_CTX_CTX_CTRL_NO_RAM_ACC                     (1L<<23)
2417 #define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE                  (0x3L<<24)
2418 #define BNX2_CTX_CTX_CTRL_ATTR                           (1L<<26)
2419 #define BNX2_CTX_CTX_CTRL_WRITE_REQ                      (1L<<30)
2420 #define BNX2_CTX_CTX_CTRL_READ_REQ                       (1L<<31)
2421
2422 #define BNX2_CTX_CTX_DATA                               0x00001020
2423 #define BNX2_CTX_ACCESS_STATUS                          0x00001040
2424 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
2425 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
2426 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
2427 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
2428 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
2429 #define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI       (0x1fL<<0)
2430 #define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI     (0x1fL<<5)
2431 #define BNX2_CTX_ACCESS_STATUS_REQUEST_XI                (0x3fffffL<<10)
2432
2433 #define BNX2_CTX_DBG_LOCK_STATUS                        0x00001044
2434 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
2435 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
2436
2437 #define BNX2_CTX_CACHE_CTRL_STATUS                      0x00001048
2438 #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW        (1L<<0)
2439 #define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP     (1L<<1)
2440 #define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START           (1L<<6)
2441 #define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT        (0x3fL<<7)
2442 #define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED    (0x3fL<<13)
2443 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE       (1L<<19)
2444 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE       (1L<<20)
2445 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE       (1L<<21)
2446 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE       (1L<<22)
2447 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE       (1L<<23)
2448 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE       (1L<<24)
2449 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE       (1L<<25)
2450 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE       (1L<<26)
2451 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE       (1L<<27)
2452 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE       (1L<<28)
2453 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE      (1L<<29)
2454
2455 #define BNX2_CTX_CACHE_CTRL_SM_STATUS                   0x0000104c
2456 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC             (0x7L<<0)
2457 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC          (0x7L<<3)
2458 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC           (0x7L<<6)
2459 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC          (0x7L<<9)
2460 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR   (0x7fffL<<16)
2461
2462 #define BNX2_CTX_CACHE_STATUS                           0x00001050
2463 #define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES               (0x3ffL<<0)
2464 #define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES           (0x3ffL<<16)
2465
2466 #define BNX2_CTX_DMA_STATUS                             0x00001054
2467 #define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS              (0x3L<<0)
2468 #define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS              (0x3L<<2)
2469 #define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS              (0x3L<<4)
2470 #define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS              (0x3L<<6)
2471 #define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS              (0x3L<<8)
2472 #define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS              (0x3L<<10)
2473 #define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS              (0x3L<<12)
2474 #define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS              (0x3L<<14)
2475 #define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS              (0x3L<<16)
2476 #define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS              (0x3L<<18)
2477 #define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS             (0x3L<<20)
2478
2479 #define BNX2_CTX_REP_STATUS                             0x00001058
2480 #define BNX2_CTX_REP_STATUS_ERROR_ENTRY                  (0x3ffL<<0)
2481 #define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID              (0x1fL<<10)
2482 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR            (1L<<16)
2483 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR            (1L<<17)
2484 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR           (1L<<18)
2485
2486 #define BNX2_CTX_CKSUM_ERROR_STATUS                     0x0000105c
2487 #define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
2488 #define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
2489
2490 #define BNX2_CTX_CHNL_LOCK_STATUS_0                     0x00001080
2491 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
2492 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
2493 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
2494 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI              (1L<<14)
2495 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI              (0x7L<<15)
2496
2497 #define BNX2_CTX_CHNL_LOCK_STATUS_1                     0x00001084
2498 #define BNX2_CTX_CHNL_LOCK_STATUS_2                     0x00001088
2499 #define BNX2_CTX_CHNL_LOCK_STATUS_3                     0x0000108c
2500 #define BNX2_CTX_CHNL_LOCK_STATUS_4                     0x00001090
2501 #define BNX2_CTX_CHNL_LOCK_STATUS_5                     0x00001094
2502 #define BNX2_CTX_CHNL_LOCK_STATUS_6                     0x00001098
2503 #define BNX2_CTX_CHNL_LOCK_STATUS_7                     0x0000109c
2504 #define BNX2_CTX_CHNL_LOCK_STATUS_8                     0x000010a0
2505 #define BNX2_CTX_CHNL_LOCK_STATUS_9                     0x000010a4
2506
2507 #define BNX2_CTX_CACHE_DATA                             0x000010c4
2508 #define BNX2_CTX_HOST_PAGE_TBL_CTRL                     0x000010c8
2509 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR        (0x1ffL<<0)
2510 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ            (1L<<30)
2511 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ             (1L<<31)
2512
2513 #define BNX2_CTX_HOST_PAGE_TBL_DATA0                    0x000010cc
2514 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID               (1L<<0)
2515 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE               (0xffffffL<<8)
2516
2517 #define BNX2_CTX_HOST_PAGE_TBL_DATA1                    0x000010d0
2518 #define BNX2_CTX_CAM_CTRL                               0x000010d4
2519 #define BNX2_CTX_CAM_CTRL_CAM_ADDR                       (0x3ffL<<0)
2520 #define BNX2_CTX_CAM_CTRL_RESET                          (1L<<27)
2521 #define BNX2_CTX_CAM_CTRL_INVALIDATE                     (1L<<28)
2522 #define BNX2_CTX_CAM_CTRL_SEARCH                         (1L<<29)
2523 #define BNX2_CTX_CAM_CTRL_WRITE_REQ                      (1L<<30)
2524 #define BNX2_CTX_CAM_CTRL_READ_REQ                       (1L<<31)
2525
2526
2527 /*
2528  *  emac_reg definition
2529  *  offset: 0x1400
2530  */
2531 #define BNX2_EMAC_MODE                                  0x00001400
2532 #define BNX2_EMAC_MODE_RESET                             (1L<<0)
2533 #define BNX2_EMAC_MODE_HALF_DUPLEX                       (1L<<1)
2534 #define BNX2_EMAC_MODE_PORT                              (0x3L<<2)
2535 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
2536 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
2537 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
2538 #define BNX2_EMAC_MODE_PORT_MII_10M                      (3L<<2)
2539 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
2540 #define BNX2_EMAC_MODE_25G_MODE                          (1L<<5)
2541 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
2542 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
2543 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
2544 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
2545 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
2546 #define BNX2_EMAC_MODE_SERDES_MODE                       (1L<<12)
2547 #define BNX2_EMAC_MODE_BOND_OVRD                         (1L<<13)
2548 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
2549 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
2550 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
2551
2552 #define BNX2_EMAC_STATUS                                0x00001404
2553 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
2554 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
2555 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE         (1L<<13)
2556 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE           (1L<<14)
2557 #define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE            (1L<<16)
2558 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0           (1L<<17)
2559 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE    (1L<<18)
2560 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
2561 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
2562 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
2563 #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE              (1L<<31)
2564
2565 #define BNX2_EMAC_ATTENTION_ENA                         0x00001408
2566 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
2567 #define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE           (1L<<14)
2568 #define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE            (1L<<16)
2569 #define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE     (1L<<18)
2570 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
2571 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
2572 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
2573
2574 #define BNX2_EMAC_LED                                   0x0000140c
2575 #define BNX2_EMAC_LED_OVERRIDE                           (1L<<0)
2576 #define BNX2_EMAC_LED_1000MB_OVERRIDE                    (1L<<1)
2577 #define BNX2_EMAC_LED_100MB_OVERRIDE                     (1L<<2)
2578 #define BNX2_EMAC_LED_10MB_OVERRIDE                      (1L<<3)
2579 #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE                   (1L<<4)
2580 #define BNX2_EMAC_LED_BLNK_TRAFFIC                       (1L<<5)
2581 #define BNX2_EMAC_LED_TRAFFIC                            (1L<<6)
2582 #define BNX2_EMAC_LED_1000MB                             (1L<<7)
2583 #define BNX2_EMAC_LED_100MB                              (1L<<8)
2584 #define BNX2_EMAC_LED_10MB                               (1L<<9)
2585 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
2586 #define BNX2_EMAC_LED_2500MB                             (1L<<11)
2587 #define BNX2_EMAC_LED_2500MB_OVERRIDE                    (1L<<12)
2588 #define BNX2_EMAC_LED_ACTIVITY_SEL                       (0x3L<<17)
2589 #define BNX2_EMAC_LED_ACTIVITY_SEL_0                     (0L<<17)
2590 #define BNX2_EMAC_LED_ACTIVITY_SEL_1                     (1L<<17)
2591 #define BNX2_EMAC_LED_ACTIVITY_SEL_2                     (2L<<17)
2592 #define BNX2_EMAC_LED_ACTIVITY_SEL_3                     (3L<<17)
2593 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
2594 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
2595
2596 #define BNX2_EMAC_MAC_MATCH0                            0x00001410
2597 #define BNX2_EMAC_MAC_MATCH1                            0x00001414
2598 #define BNX2_EMAC_MAC_MATCH2                            0x00001418
2599 #define BNX2_EMAC_MAC_MATCH3                            0x0000141c
2600 #define BNX2_EMAC_MAC_MATCH4                            0x00001420
2601 #define BNX2_EMAC_MAC_MATCH5                            0x00001424
2602 #define BNX2_EMAC_MAC_MATCH6                            0x00001428
2603 #define BNX2_EMAC_MAC_MATCH7                            0x0000142c
2604 #define BNX2_EMAC_MAC_MATCH8                            0x00001430
2605 #define BNX2_EMAC_MAC_MATCH9                            0x00001434
2606 #define BNX2_EMAC_MAC_MATCH10                           0x00001438
2607 #define BNX2_EMAC_MAC_MATCH11                           0x0000143c
2608 #define BNX2_EMAC_MAC_MATCH12                           0x00001440
2609 #define BNX2_EMAC_MAC_MATCH13                           0x00001444
2610 #define BNX2_EMAC_MAC_MATCH14                           0x00001448
2611 #define BNX2_EMAC_MAC_MATCH15                           0x0000144c
2612 #define BNX2_EMAC_MAC_MATCH16                           0x00001450
2613 #define BNX2_EMAC_MAC_MATCH17                           0x00001454
2614 #define BNX2_EMAC_MAC_MATCH18                           0x00001458
2615 #define BNX2_EMAC_MAC_MATCH19                           0x0000145c
2616 #define BNX2_EMAC_MAC_MATCH20                           0x00001460
2617 #define BNX2_EMAC_MAC_MATCH21                           0x00001464
2618 #define BNX2_EMAC_MAC_MATCH22                           0x00001468
2619 #define BNX2_EMAC_MAC_MATCH23                           0x0000146c
2620 #define BNX2_EMAC_MAC_MATCH24                           0x00001470
2621 #define BNX2_EMAC_MAC_MATCH25                           0x00001474
2622 #define BNX2_EMAC_MAC_MATCH26                           0x00001478
2623 #define BNX2_EMAC_MAC_MATCH27                           0x0000147c
2624 #define BNX2_EMAC_MAC_MATCH28                           0x00001480
2625 #define BNX2_EMAC_MAC_MATCH29                           0x00001484
2626 #define BNX2_EMAC_MAC_MATCH30                           0x00001488
2627 #define BNX2_EMAC_MAC_MATCH31                           0x0000148c
2628 #define BNX2_EMAC_BACKOFF_SEED                          0x00001498
2629 #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED         (0x3ffL<<0)
2630
2631 #define BNX2_EMAC_RX_MTU_SIZE                           0x0000149c
2632 #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE                   (0xffffL<<0)
2633 #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA                  (1L<<31)
2634
2635 #define BNX2_EMAC_SERDES_CNTL                           0x000014a4
2636 #define BNX2_EMAC_SERDES_CNTL_RXR                        (0x7L<<0)
2637 #define BNX2_EMAC_SERDES_CNTL_RXG                        (0x3L<<3)
2638 #define BNX2_EMAC_SERDES_CNTL_RXCKSEL                    (1L<<6)
2639 #define BNX2_EMAC_SERDES_CNTL_TXBIAS                     (0x7L<<7)
2640 #define BNX2_EMAC_SERDES_CNTL_BGMAX                      (1L<<10)
2641 #define BNX2_EMAC_SERDES_CNTL_BGMIN                      (1L<<11)
2642 #define BNX2_EMAC_SERDES_CNTL_TXMODE                     (1L<<12)
2643 #define BNX2_EMAC_SERDES_CNTL_TXEDGE                     (1L<<13)
2644 #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE                (1L<<14)
2645 #define BNX2_EMAC_SERDES_CNTL_PLLTEST                    (1L<<15)
2646 #define BNX2_EMAC_SERDES_CNTL_CDET_EN                    (1L<<16)
2647 #define BNX2_EMAC_SERDES_CNTL_TBI_LBK                    (1L<<17)
2648 #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK                 (1L<<18)
2649 #define BNX2_EMAC_SERDES_CNTL_REV_PHASE                  (1L<<19)
2650 #define BNX2_EMAC_SERDES_CNTL_REGCTL12                   (0x3L<<20)
2651 #define BNX2_EMAC_SERDES_CNTL_REGCTL25                   (0x3L<<22)
2652
2653 #define BNX2_EMAC_SERDES_STATUS                         0x000014a8
2654 #define BNX2_EMAC_SERDES_STATUS_RX_STAT                  (0xffL<<0)
2655 #define BNX2_EMAC_SERDES_STATUS_COMMA_DET                (1L<<8)
2656
2657 #define BNX2_EMAC_MDIO_COMM                             0x000014ac
2658 #define BNX2_EMAC_MDIO_COMM_DATA                         (0xffffL<<0)
2659 #define BNX2_EMAC_MDIO_COMM_REG_ADDR                     (0x1fL<<16)
2660 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
2661 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
2662 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
2663 #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS              (0L<<26)
2664 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
2665 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
2666 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI          (1L<<26)
2667 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI          (1L<<26)
2668 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI           (2L<<26)
2669 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI       (2L<<26)
2670 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
2671 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45              (3L<<26)
2672 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
2673 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
2674 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
2675
2676 #define BNX2_EMAC_MDIO_STATUS                           0x000014b0
2677 #define BNX2_EMAC_MDIO_STATUS_LINK                       (1L<<0)
2678 #define BNX2_EMAC_MDIO_STATUS_10MB                       (1L<<1)
2679
2680 #define BNX2_EMAC_MDIO_MODE                             0x000014b4
2681 #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE               (1L<<1)
2682 #define BNX2_EMAC_MDIO_MODE_AUTO_POLL                    (1L<<4)
2683 #define BNX2_EMAC_MDIO_MODE_BIT_BANG                     (1L<<8)
2684 #define BNX2_EMAC_MDIO_MODE_MDIO                         (1L<<9)
2685 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
2686 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
2687 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
2688 #define BNX2_EMAC_MDIO_MODE_EXT_MDINT                    (1L<<13)
2689 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
2690 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI                 (0x3fL<<16)
2691 #define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI                 (1L<<31)
2692
2693 #define BNX2_EMAC_MDIO_AUTO_STATUS                      0x000014b8
2694 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
2695
2696 #define BNX2_EMAC_TX_MODE                               0x000014bc
2697 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
2698 #define BNX2_EMAC_TX_MODE_CS16_TEST                      (1L<<2)
2699 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
2700 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
2701 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
2702 #define BNX2_EMAC_TX_MODE_LONG_PAUSE                     (1L<<6)
2703 #define BNX2_EMAC_TX_MODE_LINK_AWARE                     (1L<<7)
2704
2705 #define BNX2_EMAC_TX_STATUS                             0x000014c0
2706 #define BNX2_EMAC_TX_STATUS_XOFFED                       (1L<<0)
2707 #define BNX2_EMAC_TX_STATUS_XOFF_SENT                    (1L<<1)
2708 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
2709 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
2710 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
2711 #define BNX2_EMAC_TX_STATUS_CS16_ERROR                   (1L<<5)
2712
2713 #define BNX2_EMAC_TX_LENGTHS                            0x000014c4
2714 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
2715 #define BNX2_EMAC_TX_LENGTHS_IPG                         (0xfL<<8)
2716 #define BNX2_EMAC_TX_LENGTHS_IPG_CRS                     (0x3L<<12)
2717
2718 #define BNX2_EMAC_RX_MODE                               0x000014c8
2719 #define BNX2_EMAC_RX_MODE_RESET                          (1L<<0)
2720 #define BNX2_EMAC_RX_MODE_FLOW_EN                        (1L<<2)
2721 #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL               (1L<<3)
2722 #define BNX2_EMAC_RX_MODE_KEEP_PAUSE                     (1L<<4)
2723 #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE                (1L<<5)
2724 #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS                   (1L<<6)
2725 #define BNX2_EMAC_RX_MODE_LLC_CHK                        (1L<<7)
2726 #define BNX2_EMAC_RX_MODE_PROMISCUOUS                    (1L<<8)
2727 #define BNX2_EMAC_RX_MODE_NO_CRC_CHK                     (1L<<9)
2728 #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG                  (1L<<10)
2729 #define BNX2_EMAC_RX_MODE_FILT_BROADCAST                 (1L<<11)
2730 #define BNX2_EMAC_RX_MODE_SORT_MODE                      (1L<<12)
2731
2732 #define BNX2_EMAC_RX_STATUS                             0x000014cc
2733 #define BNX2_EMAC_RX_STATUS_FFED                         (1L<<0)
2734 #define BNX2_EMAC_RX_STATUS_FF_RECEIVED                  (1L<<1)
2735 #define BNX2_EMAC_RX_STATUS_N_RECEIVED                   (1L<<2)
2736
2737 #define BNX2_EMAC_MULTICAST_HASH0                       0x000014d0
2738 #define BNX2_EMAC_MULTICAST_HASH1                       0x000014d4
2739 #define BNX2_EMAC_MULTICAST_HASH2                       0x000014d8
2740 #define BNX2_EMAC_MULTICAST_HASH3                       0x000014dc
2741 #define BNX2_EMAC_MULTICAST_HASH4                       0x000014e0
2742 #define BNX2_EMAC_MULTICAST_HASH5                       0x000014e4
2743 #define BNX2_EMAC_MULTICAST_HASH6                       0x000014e8
2744 #define BNX2_EMAC_MULTICAST_HASH7                       0x000014ec
2745 #define BNX2_EMAC_CKSUM_ERROR_STATUS                    0x000014f0
2746 #define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
2747 #define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
2748
2749 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS                  0x00001500
2750 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS               0x00001504
2751 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS           0x00001508
2752 #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS               0x0000150c
2753 #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS           0x00001510
2754 #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS           0x00001514
2755 #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS            0x00001518
2756 #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS      0x0000151c
2757 #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS   0x00001520
2758 #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED        0x00001524
2759 #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED       0x00001528
2760 #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED      0x0000152c
2761 #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED              0x00001530
2762 #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG        0x00001534
2763 #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS             0x00001538
2764 #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS       0x0000153c
2765 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS        0x00001540
2766 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x00001544
2767 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001548
2768 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
2769 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
2770 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
2771 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001558
2772 #define BNX2_EMAC_RXMAC_DEBUG0                          0x0000155c
2773 #define BNX2_EMAC_RXMAC_DEBUG1                          0x00001560
2774 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
2775 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE          (1L<<1)
2776 #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC                   (1L<<2)
2777 #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR                  (1L<<3)
2778 #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR               (1L<<4)
2779 #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA                 (1L<<5)
2780 #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START            (1L<<6)
2781 #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT                (0xffffL<<7)
2782 #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME                 (0xffL<<23)
2783
2784 #define BNX2_EMAC_RXMAC_DEBUG2                          0x00001564
2785 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE                  (0x7L<<0)
2786 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE             (0x0L<<0)
2787 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD              (0x1L<<0)
2788 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA             (0x2L<<0)
2789 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP            (0x3L<<0)
2790 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT              (0x4L<<0)
2791 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP             (0x5L<<0)
2792 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP            (0x6L<<0)
2793 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC               (0x7L<<0)
2794 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE                 (0xfL<<3)
2795 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE            (0x0L<<3)
2796 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0           (0x1L<<3)
2797 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1           (0x2L<<3)
2798 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2           (0x3L<<3)
2799 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3           (0x4L<<3)
2800 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT           (0x5L<<3)
2801 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT            (0x6L<<3)
2802 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS          (0x7L<<3)
2803 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST            (0x8L<<3)
2804 #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN                   (0xffL<<7)
2805 #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC                    (1L<<15)
2806 #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED                    (1L<<16)
2807 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE               (1L<<18)
2808 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE          (0L<<18)
2809 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED        (1L<<18)
2810 #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER                (0xfL<<19)
2811 #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA                    (0x1fL<<23)
2812
2813 #define BNX2_EMAC_RXMAC_DEBUG3                          0x00001568
2814 #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR                 (0xffffL<<0)
2815 #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR             (0xffffL<<16)
2816
2817 #define BNX2_EMAC_RXMAC_DEBUG4                          0x0000156c
2818 #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD                (0xffffL<<0)
2819 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE                (0x3fL<<16)
2820 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE           (0x0L<<16)
2821 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
2822 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
2823 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
2824 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
2825 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
2826 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
2827 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
2828 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
2829 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
2830 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3            (0xaL<<16)
2831 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1         (0xeL<<16)
2832 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2         (0xfL<<16)
2833 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK         (0x10L<<16)
2834 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC             (0x11L<<16)
2835 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2            (0x12L<<16)
2836 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3            (0x13L<<16)
2837 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1           (0x14L<<16)
2838 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2           (0x15L<<16)
2839 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3           (0x16L<<16)
2840 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE          (0x17L<<16)
2841 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC             (0x18L<<16)
2842 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE          (0x19L<<16)
2843 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD            (0x1aL<<16)
2844 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC            (0x1bL<<16)
2845 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH          (0x1cL<<16)
2846 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF           (0x1dL<<16)
2847 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON            (0x1eL<<16)
2848 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED         (0x1fL<<16)
2849 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED        (0x20L<<16)
2850 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE          (0x21L<<16)
2851 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL           (0x22L<<16)
2852 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1           (0x23L<<16)
2853 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2           (0x24L<<16)
2854 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3           (0x25L<<16)
2855 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE          (0x26L<<16)
2856 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE         (0x27L<<16)
2857 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL          (0x28L<<16)
2858 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE          (0x29L<<16)
2859 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP           (0x2aL<<16)
2860 #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT                  (1L<<22)
2861 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
2862 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
2863 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
2864 #define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND                 (1L<<26)
2865 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
2866 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
2867
2868 #define BNX2_EMAC_RXMAC_DEBUG5                          0x00001570
2869 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM                  (0x7L<<0)
2870 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE             (0L<<0)
2871 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF         (1L<<0)
2872 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT        (2L<<0)
2873 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC     (3L<<0)
2874 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE      (4L<<0)
2875 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL      (5L<<0)
2876 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT    (6L<<0)
2877 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1                (0x7L<<4)
2878 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW            (0x0L<<4)
2879 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT           (0x1L<<4)
2880 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF           (0x2L<<4)
2881 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF           (0x3L<<4)
2882 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF            (0x4L<<4)
2883 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF          (0x6L<<4)
2884 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF          (0x7L<<4)
2885 #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED              (1L<<7)
2886 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0                (0x7L<<8)
2887 #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL         (1L<<11)
2888 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE                (1L<<12)
2889 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA                 (1L<<13)
2890 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT                 (1L<<14)
2891 #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT                  (1L<<15)
2892 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE             (0x3L<<16)
2893 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
2894 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
2895
2896 #define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS            0x00001574
2897 #define BNX2_EMAC_RX_STAT_AC0                           0x00001580
2898 #define BNX2_EMAC_RX_STAT_AC1                           0x00001584
2899 #define BNX2_EMAC_RX_STAT_AC2                           0x00001588
2900 #define BNX2_EMAC_RX_STAT_AC3                           0x0000158c
2901 #define BNX2_EMAC_RX_STAT_AC4                           0x00001590
2902 #define BNX2_EMAC_RX_STAT_AC5                           0x00001594
2903 #define BNX2_EMAC_RX_STAT_AC6                           0x00001598
2904 #define BNX2_EMAC_RX_STAT_AC7                           0x0000159c
2905 #define BNX2_EMAC_RX_STAT_AC8                           0x000015a0
2906 #define BNX2_EMAC_RX_STAT_AC9                           0x000015a4
2907 #define BNX2_EMAC_RX_STAT_AC10                          0x000015a8
2908 #define BNX2_EMAC_RX_STAT_AC11                          0x000015ac
2909 #define BNX2_EMAC_RX_STAT_AC12                          0x000015b0
2910 #define BNX2_EMAC_RX_STAT_AC13                          0x000015b4
2911 #define BNX2_EMAC_RX_STAT_AC14                          0x000015b8
2912 #define BNX2_EMAC_RX_STAT_AC15                          0x000015bc
2913 #define BNX2_EMAC_RX_STAT_AC16                          0x000015c0
2914 #define BNX2_EMAC_RX_STAT_AC17                          0x000015c4
2915 #define BNX2_EMAC_RX_STAT_AC18                          0x000015c8
2916 #define BNX2_EMAC_RX_STAT_AC19                          0x000015cc
2917 #define BNX2_EMAC_RX_STAT_AC20                          0x000015d0
2918 #define BNX2_EMAC_RX_STAT_AC21                          0x000015d4
2919 #define BNX2_EMAC_RX_STAT_AC22                          0x000015d8
2920 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC              0x000015dc
2921 #define BNX2_EMAC_RX_STAT_AC_28                         0x000015f4
2922 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                 0x00001600
2923 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS              0x00001604
2924 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS          0x00001608
2925 #define BNX2_EMAC_TX_STAT_OUTXONSENT                    0x0000160c
2926 #define BNX2_EMAC_TX_STAT_OUTXOFFSENT                   0x00001610
2927 #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE               0x00001614
2928 #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES        0x00001618
2929 #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES      0x0000161c
2930 #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS        0x00001620
2931 #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS  0x00001624
2932 #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS       0x00001628
2933 #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS              0x0000162c
2934 #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS          0x00001630
2935 #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS          0x00001634
2936 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS        0x00001638
2937 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x0000163c
2938 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001640
2939 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
2940 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
2941 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
2942 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001650
2943 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
2944 #define BNX2_EMAC_TXMAC_DEBUG0                          0x00001658
2945 #define BNX2_EMAC_TXMAC_DEBUG1                          0x0000165c
2946 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE                 (0xfL<<0)
2947 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE            (0x0L<<0)
2948 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0          (0x1L<<0)
2949 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0           (0x4L<<0)
2950 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1           (0x5L<<0)
2951 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2           (0x6L<<0)
2952 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3           (0x7L<<0)
2953 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0           (0x8L<<0)
2954 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1           (0x9L<<0)
2955 #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE                (1L<<4)
2956 #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC                   (1L<<5)
2957 #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER                (0xfL<<6)
2958 #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE                (1L<<10)
2959 #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION            (1L<<11)
2960 #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER                 (1L<<12)
2961 #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED                  (1L<<13)
2962 #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE                  (1L<<14)
2963 #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME                  (0xfL<<15)
2964 #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME                 (0xffL<<19)
2965
2966 #define BNX2_EMAC_TXMAC_DEBUG2                          0x00001660
2967 #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF                  (0x3ffL<<0)
2968 #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT                (0xffffL<<10)
2969 #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT                 (0x1fL<<26)
2970 #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT                   (1L<<31)
2971
2972 #define BNX2_EMAC_TXMAC_DEBUG3                          0x00001664
2973 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE                  (0xfL<<0)
2974 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE             (0x0L<<0)
2975 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1             (0x1L<<0)
2976 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2             (0x2L<<0)
2977 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD              (0x3L<<0)
2978 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA             (0x4L<<0)
2979 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1             (0x5L<<0)
2980 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2             (0x6L<<0)
2981 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT              (0x7L<<0)
2982 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB            (0x8L<<0)
2983 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG            (0x9L<<0)
2984 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM              (0xaL<<0)
2985 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM             (0xbL<<0)
2986 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM             (0xcL<<0)
2987 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT            (0xdL<<0)
2988 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF          (0xeL<<0)
2989 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE                (0x7L<<4)
2990 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE           (0x0L<<4)
2991 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT           (0x1L<<4)
2992 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI            (0x2L<<4)
2993 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC             (0x3L<<4)
2994 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2            (0x4L<<4)
2995 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3            (0x5L<<4)
2996 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC             (0x6L<<4)
2997 #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE                  (1L<<7)
2998 #define BNX2_EMAC_TXMAC_DEBUG3_XOFF                      (1L<<8)
2999 #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER                (0xfL<<9)
3000 #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER            (0x1fL<<13)
3001
3002 #define BNX2_EMAC_TXMAC_DEBUG4                          0x00001668
3003 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER             (0xffffL<<0)
3004 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE               (0xfL<<16)
3005 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
3006 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
3007 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
3008 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
3009 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
3010 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
3011 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
3012 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
3013 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
3014 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
3015 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
3016 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
3017 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
3018 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
3019 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
3020 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
3021 #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER                 (1L<<23)
3022 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND               (1L<<24)
3023 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING              (1L<<25)
3024 #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC                   (1L<<26)
3025 #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING                 (1L<<27)
3026 #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN                    (1L<<28)
3027 #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING                  (1L<<29)
3028 #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE                   (1L<<30)
3029 #define BNX2_EMAC_TXMAC_DEBUG4_GO                        (1L<<31)
3030
3031 #define BNX2_EMAC_TX_STAT_AC0                           0x00001680
3032 #define BNX2_EMAC_TX_STAT_AC1                           0x00001684
3033 #define BNX2_EMAC_TX_STAT_AC2                           0x00001688
3034 #define BNX2_EMAC_TX_STAT_AC3                           0x0000168c
3035 #define BNX2_EMAC_TX_STAT_AC4                           0x00001690
3036 #define BNX2_EMAC_TX_STAT_AC5                           0x00001694
3037 #define BNX2_EMAC_TX_STAT_AC6                           0x00001698
3038 #define BNX2_EMAC_TX_STAT_AC7                           0x0000169c
3039 #define BNX2_EMAC_TX_STAT_AC8                           0x000016a0
3040 #define BNX2_EMAC_TX_STAT_AC9                           0x000016a4
3041 #define BNX2_EMAC_TX_STAT_AC10                          0x000016a8
3042 #define BNX2_EMAC_TX_STAT_AC11                          0x000016ac
3043 #define BNX2_EMAC_TX_STAT_AC12                          0x000016b0
3044 #define BNX2_EMAC_TX_STAT_AC13                          0x000016b4
3045 #define BNX2_EMAC_TX_STAT_AC14                          0x000016b8
3046 #define BNX2_EMAC_TX_STAT_AC15                          0x000016bc
3047 #define BNX2_EMAC_TX_STAT_AC16                          0x000016c0
3048 #define BNX2_EMAC_TX_STAT_AC17                          0x000016c4
3049 #define BNX2_EMAC_TX_STAT_AC18                          0x000016c8
3050 #define BNX2_EMAC_TX_STAT_AC19                          0x000016cc
3051 #define BNX2_EMAC_TX_STAT_AC20                          0x000016d0
3052 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC              0x000016d8
3053 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL                    0x000016fc
3054 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC     (0x7fL<<0)
3055 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM     (0x7fL<<16)
3056 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN     (1L<<31)
3057
3058
3059 /*
3060  *  rpm_reg definition
3061  *  offset: 0x1800
3062  */
3063 #define BNX2_RPM_COMMAND                                0x00001800
3064 #define BNX2_RPM_COMMAND_ENABLED                         (1L<<0)
3065 #define BNX2_RPM_COMMAND_OVERRUN_ABORT                   (1L<<4)
3066
3067 #define BNX2_RPM_STATUS                                 0x00001804
3068 #define BNX2_RPM_STATUS_MBUF_WAIT                        (1L<<0)
3069 #define BNX2_RPM_STATUS_FREE_WAIT                        (1L<<1)
3070
3071 #define BNX2_RPM_CONFIG                                 0x00001808
3072 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM                 (1L<<0)
3073 #define BNX2_RPM_CONFIG_ACPI_ENA                         (1L<<1)
3074 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
3075 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
3076 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
3077 #define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT               (1L<<30)
3078 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
3079
3080 #define BNX2_RPM_MGMT_PKT_CTRL                          0x0000180c
3081 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT                 (0xfL<<0)
3082 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE                 (0xfL<<4)
3083 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN           (1L<<30)
3084 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN                   (1L<<31)
3085
3086 #define BNX2_RPM_VLAN_MATCH0                            0x00001810
3087 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
3088
3089 #define BNX2_RPM_VLAN_MATCH1                            0x00001814
3090 #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE        (0xfffL<<0)
3091
3092 #define BNX2_RPM_VLAN_MATCH2                            0x00001818
3093 #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE        (0xfffL<<0)
3094
3095 #define BNX2_RPM_VLAN_MATCH3                            0x0000181c
3096 #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE        (0xfffL<<0)
3097
3098 #define BNX2_RPM_SORT_USER0                             0x00001820
3099 #define BNX2_RPM_SORT_USER0_PM_EN                        (0xffffL<<0)
3100 #define BNX2_RPM_SORT_USER0_BC_EN                        (1L<<16)
3101 #define BNX2_RPM_SORT_USER0_MC_EN                        (1L<<17)
3102 #define BNX2_RPM_SORT_USER0_MC_HSH_EN                    (1L<<18)
3103 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
3104 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
3105 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
3106 #define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH                (1L<<25)
3107 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
3108
3109 #define BNX2_RPM_SORT_USER1                             0x00001824
3110 #define BNX2_RPM_SORT_USER1_PM_EN                        (0xffffL<<0)
3111 #define BNX2_RPM_SORT_USER1_BC_EN                        (1L<<16)
3112 #define BNX2_RPM_SORT_USER1_MC_EN                        (1L<<17)
3113 #define BNX2_RPM_SORT_USER1_MC_HSH_EN                    (1L<<18)
3114 #define BNX2_RPM_SORT_USER1_PROM_EN                      (1L<<19)
3115 #define BNX2_RPM_SORT_USER1_VLAN_EN                      (0xfL<<20)
3116 #define BNX2_RPM_SORT_USER1_PROM_VLAN                    (1L<<24)
3117 #define BNX2_RPM_SORT_USER1_ENA                          (1L<<31)
3118
3119 #define BNX2_RPM_SORT_USER2                             0x00001828
3120 #define BNX2_RPM_SORT_USER2_PM_EN                        (0xffffL<<0)
3121 #define BNX2_RPM_SORT_USER2_BC_EN                        (1L<<16)
3122 #define BNX2_RPM_SORT_USER2_MC_EN                        (1L<<17)
3123 #define BNX2_RPM_SORT_USER2_MC_HSH_EN                    (1L<<18)
3124 #define BNX2_RPM_SORT_USER2_PROM_EN                      (1L<<19)
3125 #define BNX2_RPM_SORT_USER2_VLAN_EN                      (0xfL<<20)
3126 #define BNX2_RPM_SORT_USER2_PROM_VLAN                    (1L<<24)
3127 #define BNX2_RPM_SORT_USER2_ENA                          (1L<<31)
3128
3129 #define BNX2_RPM_SORT_USER3                             0x0000182c
3130 #define BNX2_RPM_SORT_USER3_PM_EN                        (0xffffL<<0)
3131 #define BNX2_RPM_SORT_USER3_BC_EN                        (1L<<16)
3132 #define BNX2_RPM_SORT_USER3_MC_EN                        (1L<<17)
3133 #define BNX2_RPM_SORT_USER3_MC_HSH_EN                    (1L<<18)
3134 #define BNX2_RPM_SORT_USER3_PROM_EN                      (1L<<19)
3135 #define BNX2_RPM_SORT_USER3_VLAN_EN                      (0xfL<<20)
3136 #define BNX2_RPM_SORT_USER3_PROM_VLAN                    (1L<<24)
3137 #define BNX2_RPM_SORT_USER3_ENA                          (1L<<31)
3138
3139 #define BNX2_RPM_STAT_L2_FILTER_DISCARDS                0x00001840
3140 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS             0x00001844
3141 #define BNX2_RPM_STAT_IFINFTQDISCARDS                   0x00001848
3142 #define BNX2_RPM_STAT_IFINMBUFDISCARD                   0x0000184c
3143 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT               0x00001850
3144 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0           0x00001854
3145 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN    (0xffL<<0)
3146 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER        (0xffL<<16)
3147 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE       (1L<<30)
3148 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN     (1L<<31)
3149
3150 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1           0x00001858
3151 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN    (0xffL<<0)
3152 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER        (0xffL<<16)
3153 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE       (1L<<30)
3154 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN     (1L<<31)
3155
3156 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2           0x0000185c
3157 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN    (0xffL<<0)
3158 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER        (0xffL<<16)
3159 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE       (1L<<30)
3160 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN     (1L<<31)
3161
3162 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3           0x00001860
3163 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN    (0xffL<<0)
3164 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER        (0xffL<<16)
3165 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE       (1L<<30)
3166 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN     (1L<<31)
3167
3168 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4           0x00001864
3169 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN    (0xffL<<0)
3170 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER        (0xffL<<16)
3171 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE       (1L<<30)
3172 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN     (1L<<31)
3173
3174 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5           0x00001868
3175 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN    (0xffL<<0)
3176 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER        (0xffL<<16)
3177 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE       (1L<<30)
3178 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN     (1L<<31)
3179
3180 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6           0x0000186c
3181 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN    (0xffL<<0)
3182 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER        (0xffL<<16)
3183 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE       (1L<<30)
3184 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN     (1L<<31)
3185
3186 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7           0x00001870
3187 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN    (0xffL<<0)
3188 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER        (0xffL<<16)
3189 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE       (1L<<30)
3190 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN     (1L<<31)
3191
3192 #define BNX2_RPM_STAT_AC0                               0x00001880
3193 #define BNX2_RPM_STAT_AC1                               0x00001884
3194 #define BNX2_RPM_STAT_AC2                               0x00001888
3195 #define BNX2_RPM_STAT_AC3                               0x0000188c
3196 #define BNX2_RPM_STAT_AC4                               0x00001890
3197 #define BNX2_RPM_RC_CNTL_16                             0x000018e0
3198 #define BNX2_RPM_RC_CNTL_16_OFFSET                       (0xffL<<0)
3199 #define BNX2_RPM_RC_CNTL_16_CLASS                        (0x7L<<8)
3200 #define BNX2_RPM_RC_CNTL_16_PRIORITY                     (1L<<11)
3201 #define BNX2_RPM_RC_CNTL_16_P4                           (1L<<12)
3202 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE                     (0x7L<<13)
3203 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START               (0L<<13)
3204 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP                  (1L<<13)
3205 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP                 (2L<<13)
3206 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP                 (3L<<13)
3207 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA                (4L<<13)
3208 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP             (5L<<13)
3209 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6              (6L<<13)
3210 #define BNX2_RPM_RC_CNTL_16_COMP                         (0x3L<<16)
3211 #define BNX2_RPM_RC_CNTL_16_COMP_EQUAL                   (0L<<16)
3212 #define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL                  (1L<<16)
3213 #define BNX2_RPM_RC_CNTL_16_COMP_GREATER                 (2L<<16)
3214 #define BNX2_RPM_RC_CNTL_16_COMP_LESS                    (3L<<16)
3215 #define BNX2_RPM_RC_CNTL_16_MAP                          (1L<<18)
3216 #define BNX2_RPM_RC_CNTL_16_SBIT                         (1L<<19)
3217 #define BNX2_RPM_RC_CNTL_16_CMDSEL                       (0x1fL<<20)
3218 #define BNX2_RPM_RC_CNTL_16_DISCARD                      (1L<<25)
3219 #define BNX2_RPM_RC_CNTL_16_MASK                         (1L<<26)
3220 #define BNX2_RPM_RC_CNTL_16_P1                           (1L<<27)
3221 #define BNX2_RPM_RC_CNTL_16_P2                           (1L<<28)
3222 #define BNX2_RPM_RC_CNTL_16_P3                           (1L<<29)
3223 #define BNX2_RPM_RC_CNTL_16_NBIT                         (1L<<30)
3224
3225 #define BNX2_RPM_RC_VALUE_MASK_16                       0x000018e4
3226 #define BNX2_RPM_RC_VALUE_MASK_16_VALUE                  (0xffffL<<0)
3227 #define BNX2_RPM_RC_VALUE_MASK_16_MASK                   (0xffffL<<16)
3228
3229 #define BNX2_RPM_RC_CNTL_17                             0x000018e8
3230 #define BNX2_RPM_RC_CNTL_17_OFFSET                       (0xffL<<0)
3231 #define BNX2_RPM_RC_CNTL_17_CLASS                        (0x7L<<8)
3232 #define BNX2_RPM_RC_CNTL_17_PRIORITY                     (1L<<11)
3233 #define BNX2_RPM_RC_CNTL_17_P4                           (1L<<12)
3234 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE                     (0x7L<<13)
3235 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START               (0L<<13)
3236 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP                  (1L<<13)
3237 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP                 (2L<<13)
3238 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP                 (3L<<13)
3239 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA                (4L<<13)
3240 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP             (5L<<13)
3241 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6              (6L<<13)
3242 #define BNX2_RPM_RC_CNTL_17_COMP                         (0x3L<<16)
3243 #define BNX2_RPM_RC_CNTL_17_COMP_EQUAL                   (0L<<16)
3244 #define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL                  (1L<<16)
3245 #define BNX2_RPM_RC_CNTL_17_COMP_GREATER                 (2L<<16)
3246 #define BNX2_RPM_RC_CNTL_17_COMP_LESS                    (3L<<16)
3247 #define BNX2_RPM_RC_CNTL_17_MAP                          (1L<<18)
3248 #define BNX2_RPM_RC_CNTL_17_SBIT                         (1L<<19)
3249 #define BNX2_RPM_RC_CNTL_17_CMDSEL                       (0x1fL<<20)
3250 #define BNX2_RPM_RC_CNTL_17_DISCARD                      (1L<<25)
3251 #define BNX2_RPM_RC_CNTL_17_MASK                         (1L<<26)
3252 #define BNX2_RPM_RC_CNTL_17_P1                           (1L<<27)
3253 #define BNX2_RPM_RC_CNTL_17_P2                           (1L<<28)
3254 #define BNX2_RPM_RC_CNTL_17_P3                           (1L<<29)
3255 #define BNX2_RPM_RC_CNTL_17_NBIT                         (1L<<30)
3256
3257 #define BNX2_RPM_RC_VALUE_MASK_17                       0x000018ec
3258 #define BNX2_RPM_RC_VALUE_MASK_17_VALUE                  (0xffffL<<0)
3259 #define BNX2_RPM_RC_VALUE_MASK_17_MASK                   (0xffffL<<16)
3260
3261 #define BNX2_RPM_RC_CNTL_18                             0x000018f0
3262 #define BNX2_RPM_RC_CNTL_18_OFFSET                       (0xffL<<0)
3263 #define BNX2_RPM_RC_CNTL_18_CLASS                        (0x7L<<8)
3264 #define BNX2_RPM_RC_CNTL_18_PRIORITY                     (1L<<11)
3265 #define BNX2_RPM_RC_CNTL_18_P4                           (1L<<12)
3266 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE                     (0x7L<<13)
3267 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START               (0L<<13)
3268 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP                  (1L<<13)
3269 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP                 (2L<<13)
3270 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP                 (3L<<13)
3271 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA                (4L<<13)
3272 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP             (5L<<13)
3273 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6              (6L<<13)
3274 #define BNX2_RPM_RC_CNTL_18_COMP                         (0x3L<<16)
3275 #define BNX2_RPM_RC_CNTL_18_COMP_EQUAL                   (0L<<16)
3276 #define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL                  (1L<<16)
3277 #define BNX2_RPM_RC_CNTL_18_COMP_GREATER                 (2L<<16)
3278 #define BNX2_RPM_RC_CNTL_18_COMP_LESS                    (3L<<16)
3279 #define BNX2_RPM_RC_CNTL_18_MAP                          (1L<<18)
3280 #define BNX2_RPM_RC_CNTL_18_SBIT                         (1L<<19)
3281 #define BNX2_RPM_RC_CNTL_18_CMDSEL                       (0x1fL<<20)
3282 #define BNX2_RPM_RC_CNTL_18_DISCARD                      (1L<<25)
3283 #define BNX2_RPM_RC_CNTL_18_MASK                         (1L<<26)
3284 #define BNX2_RPM_RC_CNTL_18_P1                           (1L<<27)
3285 #define BNX2_RPM_RC_CNTL_18_P2                           (1L<<28)
3286 #define BNX2_RPM_RC_CNTL_18_P3                           (1L<<29)
3287 #define BNX2_RPM_RC_CNTL_18_NBIT                         (1L<<30)
3288
3289 #define BNX2_RPM_RC_VALUE_MASK_18                       0x000018f4
3290 #define BNX2_RPM_RC_VALUE_MASK_18_VALUE                  (0xffffL<<0)
3291 #define BNX2_RPM_RC_VALUE_MASK_18_MASK                   (0xffffL<<16)
3292
3293 #define BNX2_RPM_RC_CNTL_19                             0x000018f8
3294 #define BNX2_RPM_RC_CNTL_19_OFFSET                       (0xffL<<0)
3295 #define BNX2_RPM_RC_CNTL_19_CLASS                        (0x7L<<8)
3296 #define BNX2_RPM_RC_CNTL_19_PRIORITY                     (1L<<11)
3297 #define BNX2_RPM_RC_CNTL_19_P4                           (1L<<12)
3298 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE                     (0x7L<<13)
3299 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START               (0L<<13)
3300 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP                  (1L<<13)
3301 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP                 (2L<<13)
3302 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP                 (3L<<13)
3303 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA                (4L<<13)
3304 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP             (5L<<13)
3305 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6              (6L<<13)
3306 #define BNX2_RPM_RC_CNTL_19_COMP                         (0x3L<<16)
3307 #define BNX2_RPM_RC_CNTL_19_COMP_EQUAL                   (0L<<16)
3308 #define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL                  (1L<<16)
3309 #define BNX2_RPM_RC_CNTL_19_COMP_GREATER                 (2L<<16)
3310 #define BNX2_RPM_RC_CNTL_19_COMP_LESS                    (3L<<16)
3311 #define BNX2_RPM_RC_CNTL_19_MAP                          (1L<<18)
3312 #define BNX2_RPM_RC_CNTL_19_SBIT                         (1L<<19)
3313 #define BNX2_RPM_RC_CNTL_19_CMDSEL                       (0x1fL<<20)
3314 #define BNX2_RPM_RC_CNTL_19_DISCARD                      (1L<<25)
3315 #define BNX2_RPM_RC_CNTL_19_MASK                         (1L<<26)
3316 #define BNX2_RPM_RC_CNTL_19_P1                           (1L<<27)
3317 #define BNX2_RPM_RC_CNTL_19_P2                           (1L<<28)
3318 #define BNX2_RPM_RC_CNTL_19_P3                           (1L<<29)
3319 #define BNX2_RPM_RC_CNTL_19_NBIT                         (1L<<30)
3320
3321 #define BNX2_RPM_RC_VALUE_MASK_19                       0x000018fc
3322 #define BNX2_RPM_RC_VALUE_MASK_19_VALUE                  (0xffffL<<0)
3323 #define BNX2_RPM_RC_VALUE_MASK_19_MASK                   (0xffffL<<16)
3324
3325 #define BNX2_RPM_RC_CNTL_0                              0x00001900
3326 #define BNX2_RPM_RC_CNTL_0_OFFSET                        (0xffL<<0)
3327 #define BNX2_RPM_RC_CNTL_0_CLASS                         (0x7L<<8)
3328 #define BNX2_RPM_RC_CNTL_0_PRIORITY                      (1L<<11)
3329 #define BNX2_RPM_RC_CNTL_0_P4                            (1L<<12)
3330 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE                      (0x7L<<13)
3331 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START                (0L<<13)
3332 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP                   (1L<<13)
3333 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP                  (2L<<13)
3334 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP                  (3L<<13)
3335 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA                 (4L<<13)
3336 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP              (5L<<13)
3337 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6               (6L<<13)
3338 #define BNX2_RPM_RC_CNTL_0_COMP                          (0x3L<<16)
3339 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL                    (0L<<16)
3340 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL                   (1L<<16)
3341 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER                  (2L<<16)
3342 #define BNX2_RPM_RC_CNTL_0_COMP_LESS                     (3L<<16)
3343 #define BNX2_RPM_RC_CNTL_0_MAP_XI                        (1L<<18)
3344 #define BNX2_RPM_RC_CNTL_0_SBIT                          (1L<<19)
3345 #define BNX2_RPM_RC_CNTL_0_CMDSEL                        (0xfL<<20)
3346 #define BNX2_RPM_RC_CNTL_0_MAP                           (1L<<24)
3347 #define BNX2_RPM_RC_CNTL_0_CMDSEL_XI                     (0x1fL<<20)
3348 #define BNX2_RPM_RC_CNTL_0_DISCARD                       (1L<<25)
3349 #define BNX2_RPM_RC_CNTL_0_MASK                          (1L<<26)
3350 #define BNX2_RPM_RC_CNTL_0_P1                            (1L<<27)
3351 #define BNX2_RPM_RC_CNTL_0_P2                            (1L<<28)
3352 #define BNX2_RPM_RC_CNTL_0_P3                            (1L<<29)
3353 #define BNX2_RPM_RC_CNTL_0_NBIT                          (1L<<30)
3354
3355 #define BNX2_RPM_RC_VALUE_MASK_0                        0x00001904
3356 #define BNX2_RPM_RC_VALUE_MASK_0_VALUE                   (0xffffL<<0)
3357 #define BNX2_RPM_RC_VALUE_MASK_0_MASK                    (0xffffL<<16)
3358
3359 #define BNX2_RPM_RC_CNTL_1                              0x00001908
3360 #define BNX2_RPM_RC_CNTL_1_A                             (0x3ffffL<<0)
3361 #define BNX2_RPM_RC_CNTL_1_B                             (0xfffL<<19)
3362 #define BNX2_RPM_RC_CNTL_1_OFFSET_XI                     (0xffL<<0)
3363 #define BNX2_RPM_RC_CNTL_1_CLASS_XI                      (0x7L<<8)
3364 #define BNX2_RPM_RC_CNTL_1_PRIORITY_XI                   (1L<<11)
3365 #define BNX2_RPM_RC_CNTL_1_P4_XI                         (1L<<12)
3366 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI                   (0x7L<<13)
3367 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI             (0L<<13)
3368 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI                (1L<<13)
3369 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI               (2L<<13)
3370 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI               (3L<<13)
3371 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI              (4L<<13)
3372 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3373 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI            (6L<<13)
3374 #define BNX2_RPM_RC_CNTL_1_COMP_XI                       (0x3L<<16)
3375 #define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI                 (0L<<16)
3376 #define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI                (1L<<16)
3377 #define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI               (2L<<16)
3378 #define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI                  (3L<<16)
3379 #define BNX2_RPM_RC_CNTL_1_MAP_XI                        (1L<<18)
3380 #define BNX2_RPM_RC_CNTL_1_SBIT_XI                       (1L<<19)
3381 #define BNX2_RPM_RC_CNTL_1_CMDSEL_XI                     (0x1fL<<20)
3382 #define BNX2_RPM_RC_CNTL_1_DISCARD_XI                    (1L<<25)
3383 #define BNX2_RPM_RC_CNTL_1_MASK_XI                       (1L<<26)
3384 #define BNX2_RPM_RC_CNTL_1_P1_XI                         (1L<<27)
3385 #define BNX2_RPM_RC_CNTL_1_P2_XI                         (1L<<28)
3386 #define BNX2_RPM_RC_CNTL_1_P3_XI                         (1L<<29)
3387 #define BNX2_RPM_RC_CNTL_1_NBIT_XI                       (1L<<30)
3388
3389 #define BNX2_RPM_RC_VALUE_MASK_1                        0x0000190c
3390 #define BNX2_RPM_RC_VALUE_MASK_1_VALUE                   (0xffffL<<0)
3391 #define BNX2_RPM_RC_VALUE_MASK_1_MASK                    (0xffffL<<16)
3392
3393 #define BNX2_RPM_RC_CNTL_2                              0x00001910
3394 #define BNX2_RPM_RC_CNTL_2_A                             (0x3ffffL<<0)
3395 #define BNX2_RPM_RC_CNTL_2_B                             (0xfffL<<19)
3396 #define BNX2_RPM_RC_CNTL_2_OFFSET_XI                     (0xffL<<0)
3397 #define BNX2_RPM_RC_CNTL_2_CLASS_XI                      (0x7L<<8)
3398 #define BNX2_RPM_RC_CNTL_2_PRIORITY_XI                   (1L<<11)
3399 #define BNX2_RPM_RC_CNTL_2_P4_XI                         (1L<<12)
3400 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI                   (0x7L<<13)
3401 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI             (0L<<13)
3402 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI                (1L<<13)
3403 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI               (2L<<13)
3404 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI               (3L<<13)
3405 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI              (4L<<13)
3406 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3407 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI            (6L<<13)
3408 #define BNX2_RPM_RC_CNTL_2_COMP_XI                       (0x3L<<16)
3409 #define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI                 (0L<<16)
3410 #define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI                (1L<<16)
3411 #define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI               (2L<<16)
3412 #define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI                  (3L<<16)
3413 #define BNX2_RPM_RC_CNTL_2_MAP_XI                        (1L<<18)
3414 #define BNX2_RPM_RC_CNTL_2_SBIT_XI                       (1L<<19)
3415 #define BNX2_RPM_RC_CNTL_2_CMDSEL_XI                     (0x1fL<<20)
3416 #define BNX2_RPM_RC_CNTL_2_DISCARD_XI                    (1L<<25)
3417 #define BNX2_RPM_RC_CNTL_2_MASK_XI                       (1L<<26)
3418 #define BNX2_RPM_RC_CNTL_2_P1_XI                         (1L<<27)
3419 #define BNX2_RPM_RC_CNTL_2_P2_XI                         (1L<<28)
3420 #define BNX2_RPM_RC_CNTL_2_P3_XI                         (1L<<29)
3421 #define BNX2_RPM_RC_CNTL_2_NBIT_XI                       (1L<<30)
3422
3423 #define BNX2_RPM_RC_VALUE_MASK_2                        0x00001914
3424 #define BNX2_RPM_RC_VALUE_MASK_2_VALUE                   (0xffffL<<0)
3425 #define BNX2_RPM_RC_VALUE_MASK_2_MASK                    (0xffffL<<16)
3426
3427 #define BNX2_RPM_RC_CNTL_3                              0x00001918
3428 #define BNX2_RPM_RC_CNTL_3_A                             (0x3ffffL<<0)
3429 #define BNX2_RPM_RC_CNTL_3_B                             (0xfffL<<19)
3430 #define BNX2_RPM_RC_CNTL_3_OFFSET_XI                     (0xffL<<0)
3431 #define BNX2_RPM_RC_CNTL_3_CLASS_XI                      (0x7L<<8)
3432 #define BNX2_RPM_RC_CNTL_3_PRIORITY_XI                   (1L<<11)
3433 #define BNX2_RPM_RC_CNTL_3_P4_XI                         (1L<<12)
3434 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI                   (0x7L<<13)
3435 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI             (0L<<13)
3436 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI                (1L<<13)
3437 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI               (2L<<13)
3438 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI               (3L<<13)
3439 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI              (4L<<13)
3440 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3441 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI            (6L<<13)
3442 #define BNX2_RPM_RC_CNTL_3_COMP_XI                       (0x3L<<16)
3443 #define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI                 (0L<<16)
3444 #define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI                (1L<<16)
3445 #define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI               (2L<<16)
3446 #define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI                  (3L<<16)
3447 #define BNX2_RPM_RC_CNTL_3_MAP_XI                        (1L<<18)
3448 #define BNX2_RPM_RC_CNTL_3_SBIT_XI                       (1L<<19)
3449 #define BNX2_RPM_RC_CNTL_3_CMDSEL_XI                     (0x1fL<<20)
3450 #define BNX2_RPM_RC_CNTL_3_DISCARD_XI                    (1L<<25)
3451 #define BNX2_RPM_RC_CNTL_3_MASK_XI                       (1L<<26)
3452 #define BNX2_RPM_RC_CNTL_3_P1_XI                         (1L<<27)
3453 #define BNX2_RPM_RC_CNTL_3_P2_XI                         (1L<<28)
3454 #define BNX2_RPM_RC_CNTL_3_P3_XI                         (1L<<29)
3455 #define BNX2_RPM_RC_CNTL_3_NBIT_XI                       (1L<<30)
3456
3457 #define BNX2_RPM_RC_VALUE_MASK_3                        0x0000191c
3458 #define BNX2_RPM_RC_VALUE_MASK_3_VALUE                   (0xffffL<<0)
3459 #define BNX2_RPM_RC_VALUE_MASK_3_MASK                    (0xffffL<<16)
3460
3461 #define BNX2_RPM_RC_CNTL_4                              0x00001920
3462 #define BNX2_RPM_RC_CNTL_4_A                             (0x3ffffL<<0)
3463 #define BNX2_RPM_RC_CNTL_4_B                             (0xfffL<<19)
3464 #define BNX2_RPM_RC_CNTL_4_OFFSET_XI                     (0xffL<<0)
3465 #define BNX2_RPM_RC_CNTL_4_CLASS_XI                      (0x7L<<8)
3466 #define BNX2_RPM_RC_CNTL_4_PRIORITY_XI                   (1L<<11)
3467 #define BNX2_RPM_RC_CNTL_4_P4_XI                         (1L<<12)
3468 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI                   (0x7L<<13)
3469 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI             (0L<<13)
3470 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI                (1L<<13)
3471 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI               (2L<<13)
3472 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI               (3L<<13)
3473 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI              (4L<<13)
3474 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3475 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI            (6L<<13)
3476 #define BNX2_RPM_RC_CNTL_4_COMP_XI                       (0x3L<<16)
3477 #define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI                 (0L<<16)
3478 #define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI                (1L<<16)
3479 #define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI               (2L<<16)
3480 #define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI                  (3L<<16)
3481 #define BNX2_RPM_RC_CNTL_4_MAP_XI                        (1L<<18)
3482 #define BNX2_RPM_RC_CNTL_4_SBIT_XI                       (1L<<19)
3483 #define BNX2_RPM_RC_CNTL_4_CMDSEL_XI                     (0x1fL<<20)
3484 #define BNX2_RPM_RC_CNTL_4_DISCARD_XI                    (1L<<25)
3485 #define BNX2_RPM_RC_CNTL_4_MASK_XI                       (1L<<26)
3486 #define BNX2_RPM_RC_CNTL_4_P1_XI                         (1L<<27)
3487 #define BNX2_RPM_RC_CNTL_4_P2_XI                         (1L<<28)
3488 #define BNX2_RPM_RC_CNTL_4_P3_XI                         (1L<<29)
3489 #define BNX2_RPM_RC_CNTL_4_NBIT_XI                       (1L<<30)
3490
3491 #define BNX2_RPM_RC_VALUE_MASK_4                        0x00001924
3492 #define BNX2_RPM_RC_VALUE_MASK_4_VALUE                   (0xffffL<<0)
3493 #define BNX2_RPM_RC_VALUE_MASK_4_MASK                    (0xffffL<<16)
3494
3495 #define BNX2_RPM_RC_CNTL_5                              0x00001928
3496 #define BNX2_RPM_RC_CNTL_5_A                             (0x3ffffL<<0)
3497 #define BNX2_RPM_RC_CNTL_5_B                             (0xfffL<<19)
3498 #define BNX2_RPM_RC_CNTL_5_OFFSET_XI                     (0xffL<<0)
3499 #define BNX2_RPM_RC_CNTL_5_CLASS_XI                      (0x7L<<8)
3500 #define BNX2_RPM_RC_CNTL_5_PRIORITY_XI                   (1L<<11)
3501 #define BNX2_RPM_RC_CNTL_5_P4_XI                         (1L<<12)
3502 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI                   (0x7L<<13)
3503 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI             (0L<<13)
3504 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI                (1L<<13)
3505 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI               (2L<<13)
3506 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI               (3L<<13)
3507 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI              (4L<<13)
3508 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3509 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI            (6L<<13)
3510 #define BNX2_RPM_RC_CNTL_5_COMP_XI                       (0x3L<<16)
3511 #define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI                 (0L<<16)
3512 #define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI                (1L<<16)
3513 #define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI               (2L<<16)
3514 #define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI                  (3L<<16)
3515 #define BNX2_RPM_RC_CNTL_5_MAP_XI                        (1L<<18)
3516 #define BNX2_RPM_RC_CNTL_5_SBIT_XI                       (1L<<19)
3517 #define BNX2_RPM_RC_CNTL_5_CMDSEL_XI                     (0x1fL<<20)
3518 #define BNX2_RPM_RC_CNTL_5_DISCARD_XI                    (1L<<25)
3519 #define BNX2_RPM_RC_CNTL_5_MASK_XI                       (1L<<26)
3520 #define BNX2_RPM_RC_CNTL_5_P1_XI                         (1L<<27)
3521 #define BNX2_RPM_RC_CNTL_5_P2_XI                         (1L<<28)
3522 #define BNX2_RPM_RC_CNTL_5_P3_XI                         (1L<<29)
3523 #define BNX2_RPM_RC_CNTL_5_NBIT_XI                       (1L<<30)
3524
3525 #define BNX2_RPM_RC_VALUE_MASK_5                        0x0000192c
3526 #define BNX2_RPM_RC_VALUE_MASK_5_VALUE                   (0xffffL<<0)
3527 #define BNX2_RPM_RC_VALUE_MASK_5_MASK                    (0xffffL<<16)
3528
3529 #define BNX2_RPM_RC_CNTL_6                              0x00001930
3530 #define BNX2_RPM_RC_CNTL_6_A                             (0x3ffffL<<0)
3531 #define BNX2_RPM_RC_CNTL_6_B                             (0xfffL<<19)
3532 #define BNX2_RPM_RC_CNTL_6_OFFSET_XI                     (0xffL<<0)
3533 #define BNX2_RPM_RC_CNTL_6_CLASS_XI                      (0x7L<<8)
3534 #define BNX2_RPM_RC_CNTL_6_PRIORITY_XI                   (1L<<11)
3535 #define BNX2_RPM_RC_CNTL_6_P4_XI                         (1L<<12)
3536 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI                   (0x7L<<13)
3537 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI             (0L<<13)
3538 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI                (1L<<13)
3539 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI               (2L<<13)
3540 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI               (3L<<13)
3541 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI              (4L<<13)
3542 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3543 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI            (6L<<13)
3544 #define BNX2_RPM_RC_CNTL_6_COMP_XI                       (0x3L<<16)
3545 #define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI                 (0L<<16)
3546 #define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI                (1L<<16)
3547 #define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI               (2L<<16)
3548 #define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI                  (3L<<16)
3549 #define BNX2_RPM_RC_CNTL_6_MAP_XI                        (1L<<18)
3550 #define BNX2_RPM_RC_CNTL_6_SBIT_XI                       (1L<<19)
3551 #define BNX2_RPM_RC_CNTL_6_CMDSEL_XI                     (0x1fL<<20)
3552 #define BNX2_RPM_RC_CNTL_6_DISCARD_XI                    (1L<<25)
3553 #define BNX2_RPM_RC_CNTL_6_MASK_XI                       (1L<<26)
3554 #define BNX2_RPM_RC_CNTL_6_P1_XI                         (1L<<27)
3555 #define BNX2_RPM_RC_CNTL_6_P2_XI                         (1L<<28)
3556 #define BNX2_RPM_RC_CNTL_6_P3_XI                         (1L<<29)
3557 #define BNX2_RPM_RC_CNTL_6_NBIT_XI                       (1L<<30)
3558
3559 #define BNX2_RPM_RC_VALUE_MASK_6                        0x00001934
3560 #define BNX2_RPM_RC_VALUE_MASK_6_VALUE                   (0xffffL<<0)
3561 #define BNX2_RPM_RC_VALUE_MASK_6_MASK                    (0xffffL<<16)
3562
3563 #define BNX2_RPM_RC_CNTL_7                              0x00001938
3564 #define BNX2_RPM_RC_CNTL_7_A                             (0x3ffffL<<0)
3565 #define BNX2_RPM_RC_CNTL_7_B                             (0xfffL<<19)
3566 #define BNX2_RPM_RC_CNTL_7_OFFSET_XI                     (0xffL<<0)
3567 #define BNX2_RPM_RC_CNTL_7_CLASS_XI                      (0x7L<<8)
3568 #define BNX2_RPM_RC_CNTL_7_PRIORITY_XI                   (1L<<11)
3569 #define BNX2_RPM_RC_CNTL_7_P4_XI                         (1L<<12)
3570 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI                   (0x7L<<13)
3571 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI             (0L<<13)
3572 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI                (1L<<13)
3573 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI               (2L<<13)
3574 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI               (3L<<13)
3575 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI              (4L<<13)
3576 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3577 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI            (6L<<13)
3578 #define BNX2_RPM_RC_CNTL_7_COMP_XI                       (0x3L<<16)
3579 #define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI                 (0L<<16)
3580 #define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI                (1L<<16)
3581 #define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI               (2L<<16)
3582 #define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI                  (3L<<16)
3583 #define BNX2_RPM_RC_CNTL_7_MAP_XI                        (1L<<18)
3584 #define BNX2_RPM_RC_CNTL_7_SBIT_XI                       (1L<<19)
3585 #define BNX2_RPM_RC_CNTL_7_CMDSEL_XI                     (0x1fL<<20)
3586 #define BNX2_RPM_RC_CNTL_7_DISCARD_XI                    (1L<<25)
3587 #define BNX2_RPM_RC_CNTL_7_MASK_XI                       (1L<<26)
3588 #define BNX2_RPM_RC_CNTL_7_P1_XI                         (1L<<27)
3589 #define BNX2_RPM_RC_CNTL_7_P2_XI                         (1L<<28)
3590 #define BNX2_RPM_RC_CNTL_7_P3_XI                         (1L<<29)
3591 #define BNX2_RPM_RC_CNTL_7_NBIT_XI                       (1L<<30)
3592
3593 #define BNX2_RPM_RC_VALUE_MASK_7                        0x0000193c
3594 #define BNX2_RPM_RC_VALUE_MASK_7_VALUE                   (0xffffL<<0)
3595 #define BNX2_RPM_RC_VALUE_MASK_7_MASK                    (0xffffL<<16)
3596
3597 #define BNX2_RPM_RC_CNTL_8                              0x00001940
3598 #define BNX2_RPM_RC_CNTL_8_A                             (0x3ffffL<<0)
3599 #define BNX2_RPM_RC_CNTL_8_B                             (0xfffL<<19)
3600 #define BNX2_RPM_RC_CNTL_8_OFFSET_XI                     (0xffL<<0)
3601 #define BNX2_RPM_RC_CNTL_8_CLASS_XI                      (0x7L<<8)
3602 #define BNX2_RPM_RC_CNTL_8_PRIORITY_XI                   (1L<<11)
3603 #define BNX2_RPM_RC_CNTL_8_P4_XI                         (1L<<12)
3604 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI                   (0x7L<<13)
3605 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI             (0L<<13)
3606 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI                (1L<<13)
3607 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI               (2L<<13)
3608 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI               (3L<<13)
3609 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI              (4L<<13)
3610 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3611 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI            (6L<<13)
3612 #define BNX2_RPM_RC_CNTL_8_COMP_XI                       (0x3L<<16)
3613 #define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI                 (0L<<16)
3614 #define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI                (1L<<16)
3615 #define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI               (2L<<16)
3616 #define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI                  (3L<<16)
3617 #define BNX2_RPM_RC_CNTL_8_MAP_XI                        (1L<<18)
3618 #define BNX2_RPM_RC_CNTL_8_SBIT_XI                       (1L<<19)
3619 #define BNX2_RPM_RC_CNTL_8_CMDSEL_XI                     (0x1fL<<20)
3620 #define BNX2_RPM_RC_CNTL_8_DISCARD_XI                    (1L<<25)
3621 #define BNX2_RPM_RC_CNTL_8_MASK_XI                       (1L<<26)
3622 #define BNX2_RPM_RC_CNTL_8_P1_XI                         (1L<<27)
3623 #define BNX2_RPM_RC_CNTL_8_P2_XI                         (1L<<28)
3624 #define BNX2_RPM_RC_CNTL_8_P3_XI                         (1L<<29)
3625 #define BNX2_RPM_RC_CNTL_8_NBIT_XI                       (1L<<30)
3626
3627 #define BNX2_RPM_RC_VALUE_MASK_8                        0x00001944
3628 #define BNX2_RPM_RC_VALUE_MASK_8_VALUE                   (0xffffL<<0)
3629 #define BNX2_RPM_RC_VALUE_MASK_8_MASK                    (0xffffL<<16)
3630
3631 #define BNX2_RPM_RC_CNTL_9                              0x00001948
3632 #define BNX2_RPM_RC_CNTL_9_A                             (0x3ffffL<<0)
3633 #define BNX2_RPM_RC_CNTL_9_B                             (0xfffL<<19)
3634 #define BNX2_RPM_RC_CNTL_9_OFFSET_XI                     (0xffL<<0)
3635 #define BNX2_RPM_RC_CNTL_9_CLASS_XI                      (0x7L<<8)
3636 #define BNX2_RPM_RC_CNTL_9_PRIORITY_XI                   (1L<<11)
3637 #define BNX2_RPM_RC_CNTL_9_P4_XI                         (1L<<12)
3638 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI                   (0x7L<<13)
3639 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI             (0L<<13)
3640 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI                (1L<<13)
3641 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI               (2L<<13)
3642 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI               (3L<<13)
3643 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI              (4L<<13)
3644 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3645 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI            (6L<<13)
3646 #define BNX2_RPM_RC_CNTL_9_COMP_XI                       (0x3L<<16)
3647 #define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI                 (0L<<16)
3648 #define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI                (1L<<16)
3649 #define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI               (2L<<16)
3650 #define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI                  (3L<<16)
3651 #define BNX2_RPM_RC_CNTL_9_MAP_XI                        (1L<<18)
3652 #define BNX2_RPM_RC_CNTL_9_SBIT_XI                       (1L<<19)
3653 #define BNX2_RPM_RC_CNTL_9_CMDSEL_XI                     (0x1fL<<20)
3654 #define BNX2_RPM_RC_CNTL_9_DISCARD_XI                    (1L<<25)
3655 #define BNX2_RPM_RC_CNTL_9_MASK_XI                       (1L<<26)
3656 #define BNX2_RPM_RC_CNTL_9_P1_XI                         (1L<<27)
3657 #define BNX2_RPM_RC_CNTL_9_P2_XI                         (1L<<28)
3658 #define BNX2_RPM_RC_CNTL_9_P3_XI                         (1L<<29)
3659 #define BNX2_RPM_RC_CNTL_9_NBIT_XI                       (1L<<30)
3660
3661 #define BNX2_RPM_RC_VALUE_MASK_9                        0x0000194c
3662 #define BNX2_RPM_RC_VALUE_MASK_9_VALUE                   (0xffffL<<0)
3663 #define BNX2_RPM_RC_VALUE_MASK_9_MASK                    (0xffffL<<16)
3664
3665 #define BNX2_RPM_RC_CNTL_10                             0x00001950
3666 #define BNX2_RPM_RC_CNTL_10_A                            (0x3ffffL<<0)
3667 #define BNX2_RPM_RC_CNTL_10_B                            (0xfffL<<19)
3668 #define BNX2_RPM_RC_CNTL_10_OFFSET_XI                    (0xffL<<0)
3669 #define BNX2_RPM_RC_CNTL_10_CLASS_XI                     (0x7L<<8)
3670 #define BNX2_RPM_RC_CNTL_10_PRIORITY_XI                  (1L<<11)
3671 #define BNX2_RPM_RC_CNTL_10_P4_XI                        (1L<<12)
3672 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI                  (0x7L<<13)
3673 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI            (0L<<13)
3674 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI               (1L<<13)
3675 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI              (2L<<13)
3676 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI              (3L<<13)
3677 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI             (4L<<13)
3678 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3679 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI           (6L<<13)
3680 #define BNX2_RPM_RC_CNTL_10_COMP_XI                      (0x3L<<16)
3681 #define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI                (0L<<16)
3682 #define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI               (1L<<16)
3683 #define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI              (2L<<16)
3684 #define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI                 (3L<<16)
3685 #define BNX2_RPM_RC_CNTL_10_MAP_XI                       (1L<<18)
3686 #define BNX2_RPM_RC_CNTL_10_SBIT_XI                      (1L<<19)
3687 #define BNX2_RPM_RC_CNTL_10_CMDSEL_XI                    (0x1fL<<20)
3688 #define BNX2_RPM_RC_CNTL_10_DISCARD_XI                   (1L<<25)
3689 #define BNX2_RPM_RC_CNTL_10_MASK_XI                      (1L<<26)
3690 #define BNX2_RPM_RC_CNTL_10_P1_XI                        (1L<<27)
3691 #define BNX2_RPM_RC_CNTL_10_P2_XI                        (1L<<28)
3692 #define BNX2_RPM_RC_CNTL_10_P3_XI                        (1L<<29)
3693 #define BNX2_RPM_RC_CNTL_10_NBIT_XI                      (1L<<30)
3694
3695 #define BNX2_RPM_RC_VALUE_MASK_10                       0x00001954
3696 #define BNX2_RPM_RC_VALUE_MASK_10_VALUE                  (0xffffL<<0)
3697 #define BNX2_RPM_RC_VALUE_MASK_10_MASK                   (0xffffL<<16)
3698
3699 #define BNX2_RPM_RC_CNTL_11                             0x00001958
3700 #define BNX2_RPM_RC_CNTL_11_A                            (0x3ffffL<<0)
3701 #define BNX2_RPM_RC_CNTL_11_B                            (0xfffL<<19)
3702 #define BNX2_RPM_RC_CNTL_11_OFFSET_XI                    (0xffL<<0)
3703 #define BNX2_RPM_RC_CNTL_11_CLASS_XI                     (0x7L<<8)
3704 #define BNX2_RPM_RC_CNTL_11_PRIORITY_XI                  (1L<<11)
3705 #define BNX2_RPM_RC_CNTL_11_P4_XI                        (1L<<12)
3706 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI                  (0x7L<<13)
3707 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI            (0L<<13)
3708 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI               (1L<<13)
3709 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI              (2L<<13)
3710 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI              (3L<<13)
3711 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI             (4L<<13)
3712 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3713 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI           (6L<<13)
3714 #define BNX2_RPM_RC_CNTL_11_COMP_XI                      (0x3L<<16)
3715 #define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI                (0L<<16)
3716 #define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI               (1L<<16)
3717 #define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI              (2L<<16)
3718 #define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI                 (3L<<16)
3719 #define BNX2_RPM_RC_CNTL_11_MAP_XI                       (1L<<18)
3720 #define BNX2_RPM_RC_CNTL_11_SBIT_XI                      (1L<<19)
3721 #define BNX2_RPM_RC_CNTL_11_CMDSEL_XI                    (0x1fL<<20)
3722 #define BNX2_RPM_RC_CNTL_11_DISCARD_XI                   (1L<<25)
3723 #define BNX2_RPM_RC_CNTL_11_MASK_XI                      (1L<<26)
3724 #define BNX2_RPM_RC_CNTL_11_P1_XI                        (1L<<27)
3725 #define BNX2_RPM_RC_CNTL_11_P2_XI                        (1L<<28)
3726 #define BNX2_RPM_RC_CNTL_11_P3_XI                        (1L<<29)
3727 #define BNX2_RPM_RC_CNTL_11_NBIT_XI                      (1L<<30)
3728
3729 #define BNX2_RPM_RC_VALUE_MASK_11                       0x0000195c
3730 #define BNX2_RPM_RC_VALUE_MASK_11_VALUE                  (0xffffL<<0)
3731 #define BNX2_RPM_RC_VALUE_MASK_11_MASK                   (0xffffL<<16)
3732
3733 #define BNX2_RPM_RC_CNTL_12                             0x00001960
3734 #define BNX2_RPM_RC_CNTL_12_A                            (0x3ffffL<<0)
3735 #define BNX2_RPM_RC_CNTL_12_B                            (0xfffL<<19)
3736 #define BNX2_RPM_RC_CNTL_12_OFFSET_XI                    (0xffL<<0)
3737 #define BNX2_RPM_RC_CNTL_12_CLASS_XI                     (0x7L<<8)
3738 #define BNX2_RPM_RC_CNTL_12_PRIORITY_XI                  (1L<<11)
3739 #define BNX2_RPM_RC_CNTL_12_P4_XI                        (1L<<12)
3740 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI                  (0x7L<<13)
3741 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI            (0L<<13)
3742 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI               (1L<<13)
3743 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI              (2L<<13)
3744 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI              (3L<<13)
3745 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI             (4L<<13)
3746 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3747 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI           (6L<<13)
3748 #define BNX2_RPM_RC_CNTL_12_COMP_XI                      (0x3L<<16)
3749 #define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI                (0L<<16)
3750 #define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI               (1L<<16)
3751 #define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI              (2L<<16)
3752 #define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI                 (3L<<16)
3753 #define BNX2_RPM_RC_CNTL_12_MAP_XI                       (1L<<18)
3754 #define BNX2_RPM_RC_CNTL_12_SBIT_XI                      (1L<<19)
3755 #define BNX2_RPM_RC_CNTL_12_CMDSEL_XI                    (0x1fL<<20)
3756 #define BNX2_RPM_RC_CNTL_12_DISCARD_XI                   (1L<<25)
3757 #define BNX2_RPM_RC_CNTL_12_MASK_XI                      (1L<<26)
3758 #define BNX2_RPM_RC_CNTL_12_P1_XI                        (1L<<27)
3759 #define BNX2_RPM_RC_CNTL_12_P2_XI                        (1L<<28)
3760 #define BNX2_RPM_RC_CNTL_12_P3_XI                        (1L<<29)
3761 #define BNX2_RPM_RC_CNTL_12_NBIT_XI                      (1L<<30)
3762
3763 #define BNX2_RPM_RC_VALUE_MASK_12                       0x00001964
3764 #define BNX2_RPM_RC_VALUE_MASK_12_VALUE                  (0xffffL<<0)
3765 #define BNX2_RPM_RC_VALUE_MASK_12_MASK                   (0xffffL<<16)
3766
3767 #define BNX2_RPM_RC_CNTL_13                             0x00001968
3768 #define BNX2_RPM_RC_CNTL_13_A                            (0x3ffffL<<0)
3769 #define BNX2_RPM_RC_CNTL_13_B                            (0xfffL<<19)
3770 #define BNX2_RPM_RC_CNTL_13_OFFSET_XI                    (0xffL<<0)
3771 #define BNX2_RPM_RC_CNTL_13_CLASS_XI                     (0x7L<<8)
3772 #define BNX2_RPM_RC_CNTL_13_PRIORITY_XI                  (1L<<11)
3773 #define BNX2_RPM_RC_CNTL_13_P4_XI                        (1L<<12)
3774 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI                  (0x7L<<13)
3775 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI            (0L<<13)
3776 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI               (1L<<13)
3777 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI              (2L<<13)
3778 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI              (3L<<13)
3779 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI             (4L<<13)
3780 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3781 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI           (6L<<13)
3782 #define BNX2_RPM_RC_CNTL_13_COMP_XI                      (0x3L<<16)
3783 #define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI                (0L<<16)
3784 #define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI               (1L<<16)
3785 #define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI              (2L<<16)
3786 #define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI                 (3L<<16)
3787 #define BNX2_RPM_RC_CNTL_13_MAP_XI                       (1L<<18)
3788 #define BNX2_RPM_RC_CNTL_13_SBIT_XI                      (1L<<19)
3789 #define BNX2_RPM_RC_CNTL_13_CMDSEL_XI                    (0x1fL<<20)
3790 #define BNX2_RPM_RC_CNTL_13_DISCARD_XI                   (1L<<25)
3791 #define BNX2_RPM_RC_CNTL_13_MASK_XI                      (1L<<26)
3792 #define BNX2_RPM_RC_CNTL_13_P1_XI                        (1L<<27)
3793 #define BNX2_RPM_RC_CNTL_13_P2_XI                        (1L<<28)
3794 #define BNX2_RPM_RC_CNTL_13_P3_XI                        (1L<<29)
3795 #define BNX2_RPM_RC_CNTL_13_NBIT_XI                      (1L<<30)
3796
3797 #define BNX2_RPM_RC_VALUE_MASK_13                       0x0000196c
3798 #define BNX2_RPM_RC_VALUE_MASK_13_VALUE                  (0xffffL<<0)
3799 #define BNX2_RPM_RC_VALUE_MASK_13_MASK                   (0xffffL<<16)
3800
3801 #define BNX2_RPM_RC_CNTL_14                             0x00001970
3802 #define BNX2_RPM_RC_CNTL_14_A                            (0x3ffffL<<0)
3803 #define BNX2_RPM_RC_CNTL_14_B                            (0xfffL<<19)
3804 #define BNX2_RPM_RC_CNTL_14_OFFSET_XI                    (0xffL<<0)
3805 #define BNX2_RPM_RC_CNTL_14_CLASS_XI                     (0x7L<<8)
3806 #define BNX2_RPM_RC_CNTL_14_PRIORITY_XI                  (1L<<11)
3807 #define BNX2_RPM_RC_CNTL_14_P4_XI                        (1L<<12)
3808 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI                  (0x7L<<13)
3809 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI            (0L<<13)
3810 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI               (1L<<13)
3811 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI              (2L<<13)
3812 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI              (3L<<13)
3813 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI             (4L<<13)
3814 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3815 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI           (6L<<13)
3816 #define BNX2_RPM_RC_CNTL_14_COMP_XI                      (0x3L<<16)
3817 #define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI                (0L<<16)
3818 #define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI               (1L<<16)
3819 #define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI              (2L<<16)
3820 #define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI                 (3L<<16)
3821 #define BNX2_RPM_RC_CNTL_14_MAP_XI                       (1L<<18)
3822 #define BNX2_RPM_RC_CNTL_14_SBIT_XI                      (1L<<19)
3823 #define BNX2_RPM_RC_CNTL_14_CMDSEL_XI                    (0x1fL<<20)
3824 #define BNX2_RPM_RC_CNTL_14_DISCARD_XI                   (1L<<25)
3825 #define BNX2_RPM_RC_CNTL_14_MASK_XI                      (1L<<26)
3826 #define BNX2_RPM_RC_CNTL_14_P1_XI                        (1L<<27)
3827 #define BNX2_RPM_RC_CNTL_14_P2_XI                        (1L<<28)
3828 #define BNX2_RPM_RC_CNTL_14_P3_XI                        (1L<<29)
3829 #define BNX2_RPM_RC_CNTL_14_NBIT_XI                      (1L<<30)
3830
3831 #define BNX2_RPM_RC_VALUE_MASK_14                       0x00001974
3832 #define BNX2_RPM_RC_VALUE_MASK_14_VALUE                  (0xffffL<<0)
3833 #define BNX2_RPM_RC_VALUE_MASK_14_MASK                   (0xffffL<<16)
3834
3835 #define BNX2_RPM_RC_CNTL_15                             0x00001978
3836 #define BNX2_RPM_RC_CNTL_15_A                            (0x3ffffL<<0)
3837 #define BNX2_RPM_RC_CNTL_15_B                            (0xfffL<<19)
3838 #define BNX2_RPM_RC_CNTL_15_OFFSET_XI                    (0xffL<<0)
3839 #define BNX2_RPM_RC_CNTL_15_CLASS_XI                     (0x7L<<8)
3840 #define BNX2_RPM_RC_CNTL_15_PRIORITY_XI                  (1L<<11)
3841 #define BNX2_RPM_RC_CNTL_15_P4_XI                        (1L<<12)
3842 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI                  (0x7L<<13)
3843 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI            (0L<<13)
3844 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI               (1L<<13)
3845 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI              (2L<<13)
3846 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI              (3L<<13)
3847 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI             (4L<<13)
3848 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3849 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI           (6L<<13)
3850 #define BNX2_RPM_RC_CNTL_15_COMP_XI                      (0x3L<<16)
3851 #define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI                (0L<<16)
3852 #define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI               (1L<<16)
3853 #define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI              (2L<<16)
3854 #define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI                 (3L<<16)
3855 #define BNX2_RPM_RC_CNTL_15_MAP_XI                       (1L<<18)
3856 #define BNX2_RPM_RC_CNTL_15_SBIT_XI                      (1L<<19)
3857 #define BNX2_RPM_RC_CNTL_15_CMDSEL_XI                    (0x1fL<<20)
3858 #define BNX2_RPM_RC_CNTL_15_DISCARD_XI                   (1L<<25)
3859 #define BNX2_RPM_RC_CNTL_15_MASK_XI                      (1L<<26)
3860 #define BNX2_RPM_RC_CNTL_15_P1_XI                        (1L<<27)
3861 #define BNX2_RPM_RC_CNTL_15_P2_XI                        (1L<<28)
3862 #define BNX2_RPM_RC_CNTL_15_P3_XI                        (1L<<29)
3863 #define BNX2_RPM_RC_CNTL_15_NBIT_XI                      (1L<<30)
3864
3865 #define BNX2_RPM_RC_VALUE_MASK_15                       0x0000197c
3866 #define BNX2_RPM_RC_VALUE_MASK_15_VALUE                  (0xffffL<<0)
3867 #define BNX2_RPM_RC_VALUE_MASK_15_MASK                   (0xffffL<<16)
3868
3869 #define BNX2_RPM_RC_CONFIG                              0x00001980
3870 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE                   (0xffffL<<0)
3871 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI                (0xfffffL<<0)
3872 #define BNX2_RPM_RC_CONFIG_DEF_CLASS                     (0x7L<<24)
3873 #define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE                (1L<<31)
3874
3875 #define BNX2_RPM_DEBUG0                                 0x00001984
3876 #define BNX2_RPM_DEBUG0_FM_BCNT                          (0xffffL<<0)
3877 #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD                  (1L<<16)
3878 #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD                   (1L<<17)
3879 #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD                   (1L<<18)
3880 #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD                    (1L<<19)
3881 #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT                    (1L<<20)
3882 #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR              (1L<<21)
3883 #define BNX2_RPM_DEBUG0_LLC_SNAP                         (1L<<22)
3884 #define BNX2_RPM_DEBUG0_FM_STARTED                       (1L<<23)
3885 #define BNX2_RPM_DEBUG0_DONE                             (1L<<24)
3886 #define BNX2_RPM_DEBUG0_WAIT_4_DONE                      (1L<<25)
3887 #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM                  (1L<<26)
3888 #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM              (1L<<27)
3889 #define BNX2_RPM_DEBUG0_IGNORE_VLAN                      (1L<<28)
3890 #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE                    (1L<<31)
3891
3892 #define BNX2_RPM_DEBUG1                                 0x00001988
3893 #define BNX2_RPM_DEBUG1_FSM_CUR_ST                       (0xffffL<<0)
3894 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE                  (0L<<0)
3895 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL          (1L<<0)
3896 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC        (2L<<0)
3897 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP           (4L<<0)
3898 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP           (8L<<0)
3899 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START              (16L<<0)
3900 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP                    (32L<<0)
3901 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP                   (64L<<0)
3902 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP                   (128L<<0)
3903 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH                    (256L<<0)
3904 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP                   (512L<<0)
3905 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD           (1024L<<0)
3906 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA                  (2048L<<0)
3907 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY             (0x2000L<<0)
3908 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT          (0x4000L<<0)
3909 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT          (0x8000L<<0)
3910 #define BNX2_RPM_DEBUG1_HDR_BCNT                         (0x7ffL<<16)
3911 #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D                  (1L<<28)
3912 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2                  (1L<<29)
3913 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1                  (1L<<30)
3914 #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD                     (1L<<31)
3915
3916 #define BNX2_RPM_DEBUG2                                 0x0000198c
3917 #define BNX2_RPM_DEBUG2_CMD_HIT_VEC                      (0xffffL<<0)
3918 #define BNX2_RPM_DEBUG2_IP_BCNT                          (0xffL<<16)
3919 #define BNX2_RPM_DEBUG2_THIS_CMD_M4                      (1L<<24)
3920 #define BNX2_RPM_DEBUG2_THIS_CMD_M3                      (1L<<25)
3921 #define BNX2_RPM_DEBUG2_THIS_CMD_M2                      (1L<<26)
3922 #define BNX2_RPM_DEBUG2_THIS_CMD_M1                      (1L<<27)
3923 #define BNX2_RPM_DEBUG2_IPIPE_EMPTY                      (1L<<28)
3924 #define BNX2_RPM_DEBUG2_FM_DISCARD                       (1L<<29)
3925 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2               (1L<<30)
3926 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1               (1L<<31)
3927
3928 #define BNX2_RPM_DEBUG3                                 0x00001990
3929 #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR                   (0x1ffL<<0)
3930 #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT             (1L<<9)
3931 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT             (1L<<10)
3932 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT              (1L<<11)
3933 #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ                (1L<<12)
3934 #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ               (1L<<13)
3935 #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL               (1L<<14)
3936 #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP                (1L<<15)
3937 #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT               (0xfL<<16)
3938 #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL             (1L<<21)
3939 #define BNX2_RPM_DEBUG3_DROP_NXT_VLD                     (1L<<22)
3940 #define BNX2_RPM_DEBUG3_DROP_NXT                         (1L<<23)
3941 #define BNX2_RPM_DEBUG3_FTQ_FSM                          (0x3L<<24)
3942 #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE                     (0x0L<<24)
3943 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK                 (0x1L<<24)
3944 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE                (0x2L<<24)
3945 #define BNX2_RPM_DEBUG3_MBWRITE_FSM                      (0x3L<<26)
3946 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF             (0x0L<<26)
3947 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF             (0x1L<<26)
3948 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA             (0x2L<<26)
3949 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA            (0x3L<<26)
3950 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF             (0x4L<<26)
3951 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK          (0x5L<<26)
3952 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD    (0x6L<<26)
3953 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE                 (0x7L<<26)
3954 #define BNX2_RPM_DEBUG3_MBFREE_FSM                       (1L<<29)
3955 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE                  (0L<<29)
3956 #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK              (1L<<29)
3957 #define BNX2_RPM_DEBUG3_MBALLOC_FSM                      (1L<<30)
3958 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF              (0x0L<<30)
3959 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF             (0x1L<<30)
3960 #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR                  (1L<<31)
3961
3962 #define BNX2_RPM_DEBUG4                                 0x00001994
3963 #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER                (0x1ffffffL<<0)
3964 #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE                  (0x7L<<25)
3965 #define BNX2_RPM_DEBUG4_MBWRITE_FSM                      (0x7L<<28)
3966 #define BNX2_RPM_DEBUG4_DFIFO_EMPTY                      (1L<<31)
3967
3968 #define BNX2_RPM_DEBUG5                                 0x00001998
3969 #define BNX2_RPM_DEBUG5_RDROP_WPTR                       (0x1fL<<0)
3970 #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR                  (0x1fL<<5)
3971 #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR                    (0x1fL<<10)
3972 #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR                    (0x1fL<<15)
3973 #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY                 (1L<<20)
3974 #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY                   (1L<<21)
3975 #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR  (1L<<22)
3976 #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT             (1L<<23)
3977 #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD                  (1L<<24)
3978 #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL            (1L<<25)
3979 #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY                 (1L<<26)
3980 #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY                 (1L<<27)
3981 #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY                 (1L<<28)
3982 #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY               (1L<<29)
3983 #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T                   (1L<<30)
3984 #define BNX2_RPM_DEBUG5_HOLDREG_RD                       (1L<<31)
3985
3986 #define BNX2_RPM_DEBUG6                                 0x0000199c
3987 #define BNX2_RPM_DEBUG6_ACPI_VEC                         (0xffffL<<0)
3988 #define BNX2_RPM_DEBUG6_VEC                              (0xffffL<<16)
3989
3990 #define BNX2_RPM_DEBUG7                                 0x000019a0
3991 #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC                (0xffffffffL<<0)
3992
3993 #define BNX2_RPM_DEBUG8                                 0x000019a4
3994 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM                      (0xfL<<0)
3995 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE                 (0L<<0)
3996 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR          (1L<<0)
3997 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR          (2L<<0)
3998 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR          (3L<<0)
3999 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF       (4L<<0)
4000 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA              (5L<<0)
4001 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR              (6L<<0)
4002 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR              (7L<<0)
4003 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR              (8L<<0)
4004 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR              (9L<<0)
4005 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF           (10L<<0)
4006 #define BNX2_RPM_DEBUG8_COMPARE_AT_W0                    (1L<<4)
4007 #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA               (1L<<5)
4008 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT              (1L<<6)
4009 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3                (1L<<7)
4010 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2                (1L<<8)
4011 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES             (1L<<9)
4012 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES             (1L<<10)
4013 #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES            (1L<<11)
4014 #define BNX2_RPM_DEBUG8_EOF_DET                          (1L<<12)
4015 #define BNX2_RPM_DEBUG8_SOF_DET                          (1L<<13)
4016 #define BNX2_RPM_DEBUG8_WAIT_4_SOF                       (1L<<14)
4017 #define BNX2_RPM_DEBUG8_ALL_DONE                         (1L<<15)
4018 #define BNX2_RPM_DEBUG8_THBUF_ADDR                       (0x7fL<<16)
4019 #define BNX2_RPM_DEBUG8_BYTE_CTR                         (0xffL<<24)
4020
4021 #define BNX2_RPM_DEBUG9                                 0x000019a8
4022 #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT                    (0x7L<<0)
4023 #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY                     (1L<<3)
4024 #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT                  (0x7L<<4)
4025 #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED         (1L<<28)
4026 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED          (1L<<29)
4027 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT                   (1L<<30)
4028 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN                  (1L<<31)
4029 #define BNX2_RPM_DEBUG9_BEMEM_R_XI                       (0x1fL<<0)
4030 #define BNX2_RPM_DEBUG9_EO_XI                            (1L<<5)
4031 #define BNX2_RPM_DEBUG9_AEOF_DE_XI                       (1L<<6)
4032 #define BNX2_RPM_DEBUG9_SO_XI                            (1L<<7)
4033 #define BNX2_RPM_DEBUG9_WD64_CT_XI                       (0x1fL<<8)
4034 #define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI                   (0x7L<<13)
4035 #define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI               (0xfL<<16)
4036 #define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI                 (0x3ffL<<20)
4037 #define BNX2_RPM_DEBUG9_DATA_IN_VL_XI                    (1L<<30)
4038 #define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI             (1L<<31)
4039
4040 #define BNX2_RPM_ACPI_DBG_BUF_W00                       0x000019c0
4041 #define BNX2_RPM_ACPI_DBG_BUF_W01                       0x000019c4
4042 #define BNX2_RPM_ACPI_DBG_BUF_W02                       0x000019c8
4043 #define BNX2_RPM_ACPI_DBG_BUF_W03                       0x000019cc
4044 #define BNX2_RPM_ACPI_DBG_BUF_W10                       0x000019d0
4045 #define BNX2_RPM_ACPI_DBG_BUF_W11                       0x000019d4
4046 #define BNX2_RPM_ACPI_DBG_BUF_W12                       0x000019d8
4047 #define BNX2_RPM_ACPI_DBG_BUF_W13                       0x000019dc
4048 #define BNX2_RPM_ACPI_DBG_BUF_W20                       0x000019e0
4049 #define BNX2_RPM_ACPI_DBG_BUF_W21                       0x000019e4
4050 #define BNX2_RPM_ACPI_DBG_BUF_W22                       0x000019e8
4051 #define BNX2_RPM_ACPI_DBG_BUF_W23                       0x000019ec
4052 #define BNX2_RPM_ACPI_DBG_BUF_W30                       0x000019f0
4053 #define BNX2_RPM_ACPI_DBG_BUF_W31                       0x000019f4
4054 #define BNX2_RPM_ACPI_DBG_BUF_W32                       0x000019f8
4055 #define BNX2_RPM_ACPI_DBG_BUF_W33                       0x000019fc
4056 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL                  0x00001a00
4057 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS      (0xffffL<<0)
4058 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD           (1L<<28)
4059 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE              (1L<<29)
4060 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT              (1L<<30)
4061 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR                (1L<<31)
4062
4063 #define BNX2_RPM_ACPI_PATTERN_CTRL                      0x00001a04
4064 #define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID            (0xfL<<0)
4065 #define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR            (1L<<30)
4066 #define BNX2_RPM_ACPI_PATTERN_CTRL_WR                    (1L<<31)
4067
4068 #define BNX2_RPM_ACPI_DATA                              0x00001a08
4069 #define BNX2_RPM_ACPI_DATA_PATTERN_BE                    (0xffffffffL<<0)
4070
4071 #define BNX2_RPM_ACPI_PATTERN_LEN0                      0x00001a0c
4072 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3          (0xffL<<0)
4073 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2          (0xffL<<8)
4074 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1          (0xffL<<16)
4075 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0          (0xffL<<24)
4076
4077 #define BNX2_RPM_ACPI_PATTERN_LEN1                      0x00001a10
4078 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7          (0xffL<<0)
4079 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6          (0xffL<<8)
4080 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5          (0xffL<<16)
4081 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4          (0xffL<<24)
4082
4083 #define BNX2_RPM_ACPI_PATTERN_CRC0                      0x00001a18
4084 #define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0          (0xffffffffL<<0)
4085
4086 #define BNX2_RPM_ACPI_PATTERN_CRC1                      0x00001a1c
4087 #define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1          (0xffffffffL<<0)
4088
4089 #define BNX2_RPM_ACPI_PATTERN_CRC2                      0x00001a20
4090 #define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2          (0xffffffffL<<0)
4091
4092 #define BNX2_RPM_ACPI_PATTERN_CRC3                      0x00001a24
4093 #define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3          (0xffffffffL<<0)
4094
4095 #define BNX2_RPM_ACPI_PATTERN_CRC4                      0x00001a28
4096 #define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4          (0xffffffffL<<0)
4097
4098 #define BNX2_RPM_ACPI_PATTERN_CRC5                      0x00001a2c
4099 #define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5          (0xffffffffL<<0)
4100
4101 #define BNX2_RPM_ACPI_PATTERN_CRC6                      0x00001a30
4102 #define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6          (0xffffffffL<<0)
4103
4104 #define BNX2_RPM_ACPI_PATTERN_CRC7                      0x00001a34
4105 #define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7          (0xffffffffL<<0)
4106
4107
4108 /*
4109  *  rbuf_reg definition
4110  *  offset: 0x200000
4111  */
4112 #define BNX2_RBUF_COMMAND                               0x00200000
4113 #define BNX2_RBUF_COMMAND_ENABLED                        (1L<<0)
4114 #define BNX2_RBUF_COMMAND_FREE_INIT                      (1L<<1)
4115 #define BNX2_RBUF_COMMAND_RAM_INIT                       (1L<<2)
4116 #define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL                (1L<<3)
4117 #define BNX2_RBUF_COMMAND_OVER_FREE                      (1L<<4)
4118 #define BNX2_RBUF_COMMAND_ALLOC_REQ                      (1L<<5)
4119 #define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE                (1L<<6)
4120 #define BNX2_RBUF_COMMAND_CU_ISOLATE_XI                  (1L<<5)
4121 #define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI               (1L<<6)
4122 #define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI         (1L<<7)
4123
4124 #define BNX2_RBUF_STATUS1                               0x00200004
4125 #define BNX2_RBUF_STATUS1_FREE_COUNT                     (0x3ffL<<0)
4126
4127 #define BNX2_RBUF_STATUS2                               0x00200008
4128 #define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x1ffL<<0)
4129 #define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x1ffL<<16)
4130
4131 #define BNX2_RBUF_CONFIG                                0x0020000c
4132 #define BNX2_RBUF_CONFIG_XOFF_TRIP                       (0x3ffL<<0)
4133 #define BNX2_RBUF_CONFIG_XON_TRIP                        (0x3ffL<<16)
4134
4135 #define BNX2_RBUF_FW_BUF_ALLOC                          0x00200010
4136 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE                     (0x1ffL<<7)
4137 #define BNX2_RBUF_FW_BUF_ALLOC_TYPE                      (1L<<16)
4138 #define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ                 (1L<<31)
4139
4140 #define BNX2_RBUF_FW_BUF_FREE                           0x00200014
4141 #define BNX2_RBUF_FW_BUF_FREE_COUNT                      (0x7fL<<0)
4142 #define BNX2_RBUF_FW_BUF_FREE_TAIL                       (0x1ffL<<7)
4143 #define BNX2_RBUF_FW_BUF_FREE_HEAD                       (0x1ffL<<16)
4144 #define BNX2_RBUF_FW_BUF_FREE_TYPE                       (1L<<25)
4145 #define BNX2_RBUF_FW_BUF_FREE_FREE_REQ                   (1L<<31)
4146
4147 #define BNX2_RBUF_FW_BUF_SEL                            0x00200018
4148 #define BNX2_RBUF_FW_BUF_SEL_COUNT                       (0x7fL<<0)
4149 #define BNX2_RBUF_FW_BUF_SEL_TAIL                        (0x1ffL<<7)
4150 #define BNX2_RBUF_FW_BUF_SEL_HEAD                        (0x1ffL<<16)
4151 #define BNX2_RBUF_FW_BUF_SEL_SEL_REQ                     (1L<<31)
4152
4153 #define BNX2_RBUF_CONFIG2                               0x0020001c
4154 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP                  (0x3ffL<<0)
4155 #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP                  (0x3ffL<<16)
4156
4157 #define BNX2_RBUF_CONFIG3                               0x00200020
4158 #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP                   (0x3ffL<<0)
4159 #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP                   (0x3ffL<<16)
4160
4161 #define BNX2_RBUF_PKT_DATA                              0x00208000
4162 #define BNX2_RBUF_CLIST_DATA                            0x00210000
4163 #define BNX2_RBUF_BUF_DATA                              0x00220000
4164
4165
4166 /*
4167  *  rv2p_reg definition
4168  *  offset: 0x2800
4169  */
4170 #define BNX2_RV2P_COMMAND                               0x00002800
4171 #define BNX2_RV2P_COMMAND_ENABLED                        (1L<<0)
4172 #define BNX2_RV2P_COMMAND_PROC1_INTRPT                   (1L<<1)
4173 #define BNX2_RV2P_COMMAND_PROC2_INTRPT                   (1L<<2)
4174 #define BNX2_RV2P_COMMAND_ABORT0                         (1L<<4)
4175 #define BNX2_RV2P_COMMAND_ABORT1                         (1L<<5)
4176 #define BNX2_RV2P_COMMAND_ABORT2                         (1L<<6)
4177 #define BNX2_RV2P_COMMAND_ABORT3                         (1L<<7)
4178 #define BNX2_RV2P_COMMAND_ABORT4                         (1L<<8)
4179 #define BNX2_RV2P_COMMAND_ABORT5                         (1L<<9)
4180 #define BNX2_RV2P_COMMAND_PROC1_RESET                    (1L<<16)
4181 #define BNX2_RV2P_COMMAND_PROC2_RESET                    (1L<<17)
4182 #define BNX2_RV2P_COMMAND_CTXIF_RESET                    (1L<<18)
4183
4184 #define BNX2_RV2P_STATUS                                0x00002804
4185 #define BNX2_RV2P_STATUS_ALWAYS_0                        (1L<<0)
4186 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT              (1L<<8)
4187 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT              (1L<<9)
4188 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT              (1L<<10)
4189 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT              (1L<<11)
4190 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT              (1L<<12)
4191 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT              (1L<<13)
4192
4193 #define BNX2_RV2P_CONFIG                                0x00002808
4194 #define BNX2_RV2P_CONFIG_STALL_PROC1                     (1L<<0)
4195 #define BNX2_RV2P_CONFIG_STALL_PROC2                     (1L<<1)
4196 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0           (1L<<8)
4197 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1           (1L<<9)
4198 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2           (1L<<10)
4199 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3           (1L<<11)
4200 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4           (1L<<12)
4201 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5           (1L<<13)
4202 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0           (1L<<16)
4203 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1           (1L<<17)
4204 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2           (1L<<18)
4205 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3           (1L<<19)
4206 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4           (1L<<20)
4207 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5           (1L<<21)
4208 #define BNX2_RV2P_CONFIG_PAGE_SIZE                       (0xfL<<24)
4209 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256                   (0L<<24)
4210 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512                   (1L<<24)
4211 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K                    (2L<<24)
4212 #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K                    (3L<<24)
4213 #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K                    (4L<<24)
4214 #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K                    (5L<<24)
4215 #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K                   (6L<<24)
4216 #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K                   (7L<<24)
4217 #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K                   (8L<<24)
4218 #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K                  (9L<<24)
4219 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K                  (10L<<24)
4220 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K                  (11L<<24)
4221 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M                    (12L<<24)
4222
4223 #define BNX2_RV2P_GEN_BFR_ADDR_0                        0x00002810
4224 #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE                   (0xffffL<<16)
4225
4226 #define BNX2_RV2P_GEN_BFR_ADDR_1                        0x00002814
4227 #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE                   (0xffffL<<16)
4228
4229 #define BNX2_RV2P_GEN_BFR_ADDR_2                        0x00002818
4230 #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE                   (0xffffL<<16)
4231
4232 #define BNX2_RV2P_GEN_BFR_ADDR_3                        0x0000281c
4233 #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE                   (0xffffL<<16)
4234
4235 #define BNX2_RV2P_INSTR_HIGH                            0x00002830
4236 #define BNX2_RV2P_INSTR_HIGH_HIGH                        (0x1fL<<0)
4237
4238 #define BNX2_RV2P_INSTR_LOW                             0x00002834
4239 #define BNX2_RV2P_INSTR_LOW_LOW                          (0xffffffffL<<0)
4240
4241 #define BNX2_RV2P_PROC1_ADDR_CMD                        0x00002838
4242 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD                     (0x3ffL<<0)
4243 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR                    (1L<<31)
4244
4245 #define BNX2_RV2P_PROC2_ADDR_CMD                        0x0000283c
4246 #define BNX2_RV2P_PROC2_ADDR_CMD_ADD                     (0x3ffL<<0)
4247 #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR                    (1L<<31)
4248
4249 #define BNX2_RV2P_PROC1_GRC_DEBUG                       0x00002840
4250 #define BNX2_RV2P_PROC2_GRC_DEBUG                       0x00002844
4251 #define BNX2_RV2P_GRC_PROC_DEBUG                        0x00002848
4252 #define BNX2_RV2P_DEBUG_VECT_PEEK                       0x0000284c
4253 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
4254 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
4255 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
4256 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
4257 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
4258 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
4259
4260 #define BNX2_RV2P_MPFE_PFE_CTL                          0x00002afc
4261 #define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT             (1L<<0)
4262 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE                  (0xfL<<4)
4263 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0                (0L<<4)
4264 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1                (1L<<4)
4265 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2                (2L<<4)
4266 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3                (3L<<4)
4267 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4                (4L<<4)
4268 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5                (5L<<4)
4269 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6                (6L<<4)
4270 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7                (7L<<4)
4271 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8                (8L<<4)
4272 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9                (9L<<4)
4273 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10               (10L<<4)
4274 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11               (11L<<4)
4275 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12               (12L<<4)
4276 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13               (13L<<4)
4277 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14               (14L<<4)
4278 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15               (15L<<4)
4279 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT                 (0xfL<<12)
4280 #define BNX2_RV2P_MPFE_PFE_CTL_OFFSET                    (0x1ffL<<16)
4281
4282 #define BNX2_RV2P_RV2PPQ                                0x00002b40
4283 #define BNX2_RV2P_PFTQ_CMD                              0x00002b78
4284 #define BNX2_RV2P_PFTQ_CMD_OFFSET                        (0x3ffL<<0)
4285 #define BNX2_RV2P_PFTQ_CMD_WR_TOP                        (1L<<10)
4286 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0                      (0L<<10)
4287 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1                      (1L<<10)
4288 #define BNX2_RV2P_PFTQ_CMD_SFT_RESET                     (1L<<25)
4289 #define BNX2_RV2P_PFTQ_CMD_RD_DATA                       (1L<<26)
4290 #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN                  (1L<<27)
4291 #define BNX2_RV2P_PFTQ_CMD_ADD_DATA                      (1L<<28)
4292 #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR                 (1L<<29)
4293 #define BNX2_RV2P_PFTQ_CMD_POP                           (1L<<30)
4294 #define BNX2_RV2P_PFTQ_CMD_BUSY                          (1L<<31)
4295
4296 #define BNX2_RV2P_PFTQ_CTL                              0x00002b7c
4297 #define BNX2_RV2P_PFTQ_CTL_INTERVENE                     (1L<<0)
4298 #define BNX2_RV2P_PFTQ_CTL_OVERFLOW                      (1L<<1)
4299 #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE               (1L<<2)
4300 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
4301 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
4302
4303 #define BNX2_RV2P_RV2PTQ                                0x00002b80
4304 #define BNX2_RV2P_TFTQ_CMD                              0x00002bb8
4305 #define BNX2_RV2P_TFTQ_CMD_OFFSET                        (0x3ffL<<0)
4306 #define BNX2_RV2P_TFTQ_CMD_WR_TOP                        (1L<<10)
4307 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0                      (0L<<10)
4308 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1                      (1L<<10)
4309 #define BNX2_RV2P_TFTQ_CMD_SFT_RESET                     (1L<<25)
4310 #define BNX2_RV2P_TFTQ_CMD_RD_DATA                       (1L<<26)
4311 #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN                  (1L<<27)
4312 #define BNX2_RV2P_TFTQ_CMD_ADD_DATA                      (1L<<28)
4313 #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR                 (1L<<29)
4314 #define BNX2_RV2P_TFTQ_CMD_POP                           (1L<<30)
4315 #define BNX2_RV2P_TFTQ_CMD_BUSY                          (1L<<31)
4316
4317 #define BNX2_RV2P_TFTQ_CTL                              0x00002bbc
4318 #define BNX2_RV2P_TFTQ_CTL_INTERVENE                     (1L<<0)
4319 #define BNX2_RV2P_TFTQ_CTL_OVERFLOW                      (1L<<1)
4320 #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE               (1L<<2)
4321 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
4322 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
4323
4324 #define BNX2_RV2P_RV2PMQ                                0x00002bc0
4325 #define BNX2_RV2P_MFTQ_CMD                              0x00002bf8
4326 #define BNX2_RV2P_MFTQ_CMD_OFFSET                        (0x3ffL<<0)
4327 #define BNX2_RV2P_MFTQ_CMD_WR_TOP                        (1L<<10)
4328 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0                      (0L<<10)
4329 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1                      (1L<<10)
4330 #define BNX2_RV2P_MFTQ_CMD_SFT_RESET                     (1L<<25)
4331 #define BNX2_RV2P_MFTQ_CMD_RD_DATA                       (1L<<26)
4332 #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN                  (1L<<27)
4333 #define BNX2_RV2P_MFTQ_CMD_ADD_DATA                      (1L<<28)
4334 #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR                 (1L<<29)
4335 #define BNX2_RV2P_MFTQ_CMD_POP                           (1L<<30)
4336 #define BNX2_RV2P_MFTQ_CMD_BUSY                          (1L<<31)
4337
4338 #define BNX2_RV2P_MFTQ_CTL                              0x00002bfc
4339 #define BNX2_RV2P_MFTQ_CTL_INTERVENE                     (1L<<0)
4340 #define BNX2_RV2P_MFTQ_CTL_OVERFLOW                      (1L<<1)
4341 #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE               (1L<<2)
4342 #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
4343 #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
4344
4345
4346
4347 /*
4348  *  mq_reg definition
4349  *  offset: 0x3c00
4350  */
4351 #define BNX2_MQ_COMMAND                                 0x00003c00
4352 #define BNX2_MQ_COMMAND_ENABLED                          (1L<<0)
4353 #define BNX2_MQ_COMMAND_INIT                             (1L<<1)
4354 #define BNX2_MQ_COMMAND_OVERFLOW                         (1L<<4)
4355 #define BNX2_MQ_COMMAND_WR_ERROR                         (1L<<5)
4356 #define BNX2_MQ_COMMAND_RD_ERROR                         (1L<<6)
4357 #define BNX2_MQ_COMMAND_IDB_CFG_ERROR                    (1L<<7)
4358 #define BNX2_MQ_COMMAND_IDB_OVERFLOW                     (1L<<10)
4359 #define BNX2_MQ_COMMAND_NO_BIN_ERROR                     (1L<<11)
4360 #define BNX2_MQ_COMMAND_NO_MAP_ERROR                     (1L<<12)
4361
4362 #define BNX2_MQ_STATUS                                  0x00003c04
4363 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT                   (1L<<16)
4364 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT                 (1L<<17)
4365 #define BNX2_MQ_STATUS_PCI_STALL_STAT                    (1L<<18)
4366 #define BNX2_MQ_STATUS_IDB_OFLOW_STAT                    (1L<<19)
4367
4368 #define BNX2_MQ_CONFIG                                  0x00003c08
4369 #define BNX2_MQ_CONFIG_TX_HIGH_PRI                       (1L<<0)
4370 #define BNX2_MQ_CONFIG_HALT_DIS                          (1L<<1)
4371 #define BNX2_MQ_CONFIG_BIN_MQ_MODE                       (1L<<2)
4372 #define BNX2_MQ_CONFIG_DIS_IDB_DROP                      (1L<<3)
4373 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE                  (0x7L<<4)
4374 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256              (0L<<4)
4375 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512              (1L<<4)
4376 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K               (2L<<4)
4377 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K               (3L<<4)
4378 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K               (4L<<4)
4379 #define BNX2_MQ_CONFIG_MAX_DEPTH                         (0x7fL<<8)
4380 #define BNX2_MQ_CONFIG_CUR_DEPTH                         (0x7fL<<20)
4381
4382 #define BNX2_MQ_ENQUEUE1                                0x00003c0c
4383 #define BNX2_MQ_ENQUEUE1_OFFSET                          (0x3fL<<2)
4384 #define BNX2_MQ_ENQUEUE1_CID                             (0x3fffL<<8)
4385 #define BNX2_MQ_ENQUEUE1_BYTE_MASK                       (0xfL<<24)
4386 #define BNX2_MQ_ENQUEUE1_KNL_MODE                        (1L<<28)
4387
4388 #define BNX2_MQ_ENQUEUE2                                0x00003c10
4389 #define BNX2_MQ_BAD_WR_ADDR                             0x00003c14
4390 #define BNX2_MQ_BAD_RD_ADDR                             0x00003c18
4391 #define BNX2_MQ_KNL_BYP_WIND_START                      0x00003c1c
4392 #define BNX2_MQ_KNL_BYP_WIND_START_VALUE                 (0xfffffL<<12)
4393
4394 #define BNX2_MQ_KNL_WIND_END                            0x00003c20
4395 #define BNX2_MQ_KNL_WIND_END_VALUE                       (0xffffffL<<8)
4396
4397 #define BNX2_MQ_KNL_WRITE_MASK1                         0x00003c24
4398 #define BNX2_MQ_KNL_TX_MASK1                            0x00003c28
4399 #define BNX2_MQ_KNL_CMD_MASK1                           0x00003c2c
4400 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1                  0x00003c30
4401 #define BNX2_MQ_KNL_RX_V2P_MASK1                        0x00003c34
4402 #define BNX2_MQ_KNL_WRITE_MASK2                         0x00003c38
4403 #define BNX2_MQ_KNL_TX_MASK2                            0x00003c3c
4404 #define BNX2_MQ_KNL_CMD_MASK2                           0x00003c40
4405 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2                  0x00003c44
4406 #define BNX2_MQ_KNL_RX_V2P_MASK2                        0x00003c48
4407 #define BNX2_MQ_KNL_BYP_WRITE_MASK1                     0x00003c4c
4408 #define BNX2_MQ_KNL_BYP_TX_MASK1                        0x00003c50
4409 #define BNX2_MQ_KNL_BYP_CMD_MASK1                       0x00003c54
4410 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1              0x00003c58
4411 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1                    0x00003c5c
4412 #define BNX2_MQ_KNL_BYP_WRITE_MASK2                     0x00003c60
4413 #define BNX2_MQ_KNL_BYP_TX_MASK2                        0x00003c64
4414 #define BNX2_MQ_KNL_BYP_CMD_MASK2                       0x00003c68
4415 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2              0x00003c6c
4416 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2                    0x00003c70
4417 #define BNX2_MQ_MEM_WR_ADDR                             0x00003c74
4418 #define BNX2_MQ_MEM_WR_ADDR_VALUE                        (0x3fL<<0)
4419
4420 #define BNX2_MQ_MEM_WR_DATA0                            0x00003c78
4421 #define BNX2_MQ_MEM_WR_DATA0_VALUE                       (0xffffffffL<<0)
4422
4423 #define BNX2_MQ_MEM_WR_DATA1                            0x00003c7c
4424 #define BNX2_MQ_MEM_WR_DATA1_VALUE                       (0xffffffffL<<0)
4425
4426 #define BNX2_MQ_MEM_WR_DATA2                            0x00003c80
4427 #define BNX2_MQ_MEM_WR_DATA2_VALUE                       (0x3fffffffL<<0)
4428 #define BNX2_MQ_MEM_WR_DATA2_VALUE_XI                    (0x7fffffffL<<0)
4429
4430 #define BNX2_MQ_MEM_RD_ADDR                             0x00003c84
4431 #define BNX2_MQ_MEM_RD_ADDR_VALUE                        (0x3fL<<0)
4432
4433 #define BNX2_MQ_MEM_RD_DATA0                            0x00003c88
4434 #define BNX2_MQ_MEM_RD_DATA0_VALUE                       (0xffffffffL<<0)
4435
4436 #define BNX2_MQ_MEM_RD_DATA1                            0x00003c8c
4437 #define BNX2_MQ_MEM_RD_DATA1_VALUE                       (0xffffffffL<<0)
4438
4439 #define BNX2_MQ_MEM_RD_DATA2                            0x00003c90
4440 #define BNX2_MQ_MEM_RD_DATA2_VALUE                       (0x3fffffffL<<0)
4441 #define BNX2_MQ_MEM_RD_DATA2_VALUE_XI                    (0x7fffffffL<<0)
4442
4443
4444 /*
4445  *  tsch_reg definition
4446  *  offset: 0x4c00
4447  */
4448 #define BNX2_TSCH_TSS_CFG                               0x00004c1c
4449 #define BNX2_TSCH_TSS_CFG_TSS_START_CID                  (0x7ffL<<8)
4450 #define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON                 (0xfL<<24)
4451
4452
4453
4454 /*
4455  *  tbdr_reg definition
4456  *  offset: 0x5000
4457  */
4458 #define BNX2_TBDR_COMMAND                               0x00005000
4459 #define BNX2_TBDR_COMMAND_ENABLE                         (1L<<0)
4460 #define BNX2_TBDR_COMMAND_SOFT_RST                       (1L<<1)
4461 #define BNX2_TBDR_COMMAND_MSTR_ABORT                     (1L<<4)
4462
4463 #define BNX2_TBDR_STATUS                                0x00005004
4464 #define BNX2_TBDR_STATUS_DMA_WAIT                        (1L<<0)
4465 #define BNX2_TBDR_STATUS_FTQ_WAIT                        (1L<<1)
4466 #define BNX2_TBDR_STATUS_FIFO_OVERFLOW                   (1L<<2)
4467 #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW                  (1L<<3)
4468 #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR                (1L<<4)
4469 #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT                   (1L<<5)
4470 #define BNX2_TBDR_STATUS_BURST_CNT                       (1L<<6)
4471
4472 #define BNX2_TBDR_CONFIG                                0x00005008
4473 #define BNX2_TBDR_CONFIG_MAX_BDS                         (0xffL<<0)
4474 #define BNX2_TBDR_CONFIG_SWAP_MODE                       (1L<<8)
4475 #define BNX2_TBDR_CONFIG_PRIORITY                        (1L<<9)
4476 #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS            (1L<<10)
4477 #define BNX2_TBDR_CONFIG_PAGE_SIZE                       (0xfL<<24)
4478 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256                   (0L<<24)
4479 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512                   (1L<<24)
4480 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K                    (2L<<24)
4481 #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K                    (3L<<24)
4482 #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K                    (4L<<24)
4483 #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K                    (5L<<24)
4484 #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K                   (6L<<24)
4485 #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K                   (7L<<24)
4486 #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K                   (8L<<24)
4487 #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K                  (9L<<24)
4488 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K                  (10L<<24)
4489 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K                  (11L<<24)
4490 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M                    (12L<<24)
4491
4492 #define BNX2_TBDR_DEBUG_VECT_PEEK                       0x0000500c
4493 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
4494 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
4495 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
4496 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
4497 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
4498 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
4499
4500 #define BNX2_TBDR_CKSUM_ERROR_STATUS                    0x00005010
4501 #define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
4502 #define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
4503
4504 #define BNX2_TBDR_TBDRQ                                 0x000053c0
4505 #define BNX2_TBDR_FTQ_CMD                               0x000053f8
4506 #define BNX2_TBDR_FTQ_CMD_OFFSET                         (0x3ffL<<0)
4507 #define BNX2_TBDR_FTQ_CMD_WR_TOP                         (1L<<10)
4508 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0                       (0L<<10)
4509 #define BNX2_TBDR_FTQ_CMD_WR_TOP_1                       (1L<<10)
4510 #define BNX2_TBDR_FTQ_CMD_SFT_RESET                      (1L<<25)
4511 #define BNX2_TBDR_FTQ_CMD_RD_DATA                        (1L<<26)
4512 #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
4513 #define BNX2_TBDR_FTQ_CMD_ADD_DATA                       (1L<<28)
4514 #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
4515 #define BNX2_TBDR_FTQ_CMD_POP                            (1L<<30)
4516 #define BNX2_TBDR_FTQ_CMD_BUSY                           (1L<<31)
4517
4518 #define BNX2_TBDR_FTQ_CTL                               0x000053fc
4519 #define BNX2_TBDR_FTQ_CTL_INTERVENE                      (1L<<0)
4520 #define BNX2_TBDR_FTQ_CTL_OVERFLOW                       (1L<<1)
4521 #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
4522 #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
4523 #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
4524
4525
4526
4527 /*
4528  *  tdma_reg definition
4529  *  offset: 0x5c00
4530  */
4531 #define BNX2_TDMA_COMMAND                               0x00005c00
4532 #define BNX2_TDMA_COMMAND_ENABLED                        (1L<<0)
4533 #define BNX2_TDMA_COMMAND_MASTER_ABORT                   (1L<<4)
4534 #define BNX2_TDMA_COMMAND_CS16_ERR                       (1L<<5)
4535 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT            (1L<<7)
4536 #define BNX2_TDMA_COMMAND_MASK_CS1                       (1L<<20)
4537 #define BNX2_TDMA_COMMAND_MASK_CS2                       (1L<<21)
4538 #define BNX2_TDMA_COMMAND_MASK_CS3                       (1L<<22)
4539 #define BNX2_TDMA_COMMAND_MASK_CS4                       (1L<<23)
4540 #define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR              (1L<<24)
4541 #define BNX2_TDMA_COMMAND_OFIFO_CLR                      (1L<<30)
4542 #define BNX2_TDMA_COMMAND_IFIFO_CLR                      (1L<<31)
4543
4544 #define BNX2_TDMA_STATUS                                0x00005c04
4545 #define BNX2_TDMA_STATUS_DMA_WAIT                        (1L<<0)
4546 #define BNX2_TDMA_STATUS_PAYLOAD_WAIT                    (1L<<1)
4547 #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT                  (1L<<2)
4548 #define BNX2_TDMA_STATUS_LOCK_WAIT                       (1L<<3)
4549 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT                   (1L<<16)
4550 #define BNX2_TDMA_STATUS_BURST_CNT                       (1L<<17)
4551 #define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH                 (0x3fL<<20)
4552 #define BNX2_TDMA_STATUS_OFIFO_OVERFLOW                  (1L<<30)
4553 #define BNX2_TDMA_STATUS_IFIFO_OVERFLOW                  (1L<<31)
4554
4555 #define BNX2_TDMA_CONFIG                                0x00005c08
4556 #define BNX2_TDMA_CONFIG_ONE_DMA                         (1L<<0)
4557 #define BNX2_TDMA_CONFIG_ONE_RECORD                      (1L<<1)
4558 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN                    (0x3L<<2)
4559 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0                  (0L<<2)
4560 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1                  (1L<<2)
4561 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2                  (2L<<2)
4562 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3                  (3L<<2)
4563 #define BNX2_TDMA_CONFIG_LIMIT_SZ                        (0xfL<<4)
4564 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64                     (0L<<4)
4565 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128                    (0x4L<<4)
4566 #define BNX2_TDMA_CONFIG_LIMIT_SZ_256                    (0x6L<<4)
4567 #define BNX2_TDMA_CONFIG_LIMIT_SZ_512                    (0x8L<<4)
4568 #define BNX2_TDMA_CONFIG_LINE_SZ                         (0xfL<<8)
4569 #define BNX2_TDMA_CONFIG_LINE_SZ_64                      (0L<<8)
4570 #define BNX2_TDMA_CONFIG_LINE_SZ_128                     (4L<<8)
4571 #define BNX2_TDMA_CONFIG_LINE_SZ_256                     (6L<<8)
4572 #define BNX2_TDMA_CONFIG_LINE_SZ_512                     (8L<<8)
4573 #define BNX2_TDMA_CONFIG_ALIGN_ENA                       (1L<<15)
4574 #define BNX2_TDMA_CONFIG_CHK_L2_BD                       (1L<<16)
4575 #define BNX2_TDMA_CONFIG_CMPL_ENTRY                      (1L<<17)
4576 #define BNX2_TDMA_CONFIG_OFIFO_CMP                       (1L<<19)
4577 #define BNX2_TDMA_CONFIG_OFIFO_CMP_3                     (0L<<19)
4578 #define BNX2_TDMA_CONFIG_OFIFO_CMP_2                     (1L<<19)
4579 #define BNX2_TDMA_CONFIG_FIFO_CMP                        (0xfL<<20)
4580 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI                  (0x7L<<20)
4581 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI                (0L<<20)
4582 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI                (1L<<20)
4583 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI                (2L<<20)
4584 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI               (3L<<20)
4585 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI               (4L<<20)
4586 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI               (5L<<20)
4587 #define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI                  (1L<<23)
4588 #define BNX2_TDMA_CONFIG_BYTES_OST_XI                    (0x7L<<24)
4589 #define BNX2_TDMA_CONFIG_BYTES_OST_512_XI                (0L<<24)
4590 #define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI               (1L<<24)
4591 #define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI               (2L<<24)
4592 #define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI               (3L<<24)
4593 #define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI               (4L<<24)
4594 #define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI              (5L<<24)
4595 #define BNX2_TDMA_CONFIG_HC_BYPASS_XI                    (1L<<27)
4596 #define BNX2_TDMA_CONFIG_LCL_MRRS_XI                     (0x7L<<28)
4597 #define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI                 (0L<<28)
4598 #define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI                 (1L<<28)
4599 #define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI                 (2L<<28)
4600 #define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI                (3L<<28)
4601 #define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI                (4L<<28)
4602 #define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI                (5L<<28)
4603 #define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI                  (1L<<31)
4604
4605 #define BNX2_TDMA_PAYLOAD_PROD                          0x00005c0c
4606 #define BNX2_TDMA_PAYLOAD_PROD_VALUE                     (0x1fffL<<3)
4607
4608 #define BNX2_TDMA_DBG_WATCHDOG                          0x00005c10
4609 #define BNX2_TDMA_DBG_TRIGGER                           0x00005c14
4610 #define BNX2_TDMA_DMAD_FSM                              0x00005c80
4611 #define BNX2_TDMA_DMAD_FSM_BD_INVLD                      (1L<<0)
4612 #define BNX2_TDMA_DMAD_FSM_PUSH                          (0xfL<<4)
4613 #define BNX2_TDMA_DMAD_FSM_ARB_TBDC                      (0x3L<<8)
4614 #define BNX2_TDMA_DMAD_FSM_ARB_CTX                       (1L<<12)
4615 #define BNX2_TDMA_DMAD_FSM_DR_INTF                       (1L<<16)
4616 #define BNX2_TDMA_DMAD_FSM_DMAD                          (0x7L<<20)
4617 #define BNX2_TDMA_DMAD_FSM_BD                            (0xfL<<24)
4618
4619 #define BNX2_TDMA_DMAD_STATUS                           0x00005c84
4620 #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY           (0x3L<<0)
4621 #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY           (0x3L<<4)
4622 #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY             (0x3L<<8)
4623 #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM                  (0xfL<<12)
4624
4625 #define BNX2_TDMA_DR_INTF_FSM                           0x00005c88
4626 #define BNX2_TDMA_DR_INTF_FSM_L2_COMP                    (0x3L<<0)
4627 #define BNX2_TDMA_DR_INTF_FSM_TPATQ                      (0x7L<<4)
4628 #define BNX2_TDMA_DR_INTF_FSM_TPBUF                      (0x3L<<8)
4629 #define BNX2_TDMA_DR_INTF_FSM_DR_BUF                     (0x7L<<12)
4630 #define BNX2_TDMA_DR_INTF_FSM_DMAD                       (0x7L<<16)
4631
4632 #define BNX2_TDMA_DR_INTF_STATUS                        0x00005c8c
4633 #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE              (0x7L<<0)
4634 #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL              (0x3L<<4)
4635 #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR              (0x7L<<8)
4636 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR                (0xfL<<12)
4637 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT              (0x7L<<16)
4638
4639 #define BNX2_TDMA_PUSH_FSM                              0x00005c90
4640 #define BNX2_TDMA_BD_IF_DEBUG                           0x00005c94
4641 #define BNX2_TDMA_DMAD_IF_DEBUG                         0x00005c98
4642 #define BNX2_TDMA_CTX_IF_DEBUG                          0x00005c9c
4643 #define BNX2_TDMA_TPBUF_IF_DEBUG                        0x00005ca0
4644 #define BNX2_TDMA_DR_IF_DEBUG                           0x00005ca4
4645 #define BNX2_TDMA_TPATQ_IF_DEBUG                        0x00005ca8
4646 #define BNX2_TDMA_TDMA_ILOCK_CKSUM                      0x00005cac
4647 #define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED            (0xffffL<<0)
4648 #define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED              (0xffffL<<16)
4649
4650 #define BNX2_TDMA_TDMA_PCIE_CKSUM                       0x00005cb0
4651 #define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED             (0xffffL<<0)
4652 #define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED               (0xffffL<<16)
4653
4654 #define BNX2_TDMA_TDMAQ                                 0x00005fc0
4655 #define BNX2_TDMA_FTQ_CMD                               0x00005ff8
4656 #define BNX2_TDMA_FTQ_CMD_OFFSET                         (0x3ffL<<0)
4657 #define BNX2_TDMA_FTQ_CMD_WR_TOP                         (1L<<10)
4658 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0                       (0L<<10)
4659 #define BNX2_TDMA_FTQ_CMD_WR_TOP_1                       (1L<<10)
4660 #define BNX2_TDMA_FTQ_CMD_SFT_RESET                      (1L<<25)
4661 #define BNX2_TDMA_FTQ_CMD_RD_DATA                        (1L<<26)
4662 #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
4663 #define BNX2_TDMA_FTQ_CMD_ADD_DATA                       (1L<<28)
4664 #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
4665 #define BNX2_TDMA_FTQ_CMD_POP                            (1L<<30)
4666 #define BNX2_TDMA_FTQ_CMD_BUSY                           (1L<<31)
4667
4668 #define BNX2_TDMA_FTQ_CTL                               0x00005ffc
4669 #define BNX2_TDMA_FTQ_CTL_INTERVENE                      (1L<<0)
4670 #define BNX2_TDMA_FTQ_CTL_OVERFLOW                       (1L<<1)
4671 #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
4672 #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
4673 #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
4674
4675
4676
4677 /*