[BNX2]: Add PHY_DIS_EARLY_DAC workaround.
[linux-2.6.git] / drivers / net / bnx2.c
1 /* bnx2.c: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004-2007 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
40 #define BCM_VLAN 1
41 #endif
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
50
51 #include "bnx2.h"
52 #include "bnx2_fw.h"
53 #include "bnx2_fw2.h"
54
55 #define FW_BUF_SIZE             0x8000
56
57 #define DRV_MODULE_NAME         "bnx2"
58 #define PFX DRV_MODULE_NAME     ": "
59 #define DRV_MODULE_VERSION      "1.6.8"
60 #define DRV_MODULE_RELDATE      "October 17, 2007"
61
62 #define RUN_AT(x) (jiffies + (x))
63
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT  (5*HZ)
66
67 static const char version[] __devinitdata =
68         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
74
75 static int disable_msi = 0;
76
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80 typedef enum {
81         BCM5706 = 0,
82         NC370T,
83         NC370I,
84         BCM5706S,
85         NC370F,
86         BCM5708,
87         BCM5708S,
88         BCM5709,
89         BCM5709S,
90 } board_t;
91
92 /* indexed by board_t, above */
93 static const struct {
94         char *name;
95 } board_info[] __devinitdata = {
96         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97         { "HP NC370T Multifunction Gigabit Server Adapter" },
98         { "HP NC370i Multifunction Gigabit Server Adapter" },
99         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100         { "HP NC370F Multifunction Gigabit Server Adapter" },
101         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
104         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
105         };
106
107 static struct pci_device_id bnx2_pci_tbl[] = {
108         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
114         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
116         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
120         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
122         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
124         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
126         { 0, }
127 };
128
129 static struct flash_spec flash_table[] =
130 {
131 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
133         /* Slow EEPROM */
134         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
135          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
136          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137          "EEPROM - slow"},
138         /* Expansion entry 0001 */
139         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
140          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
141          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142          "Entry 0001"},
143         /* Saifun SA25F010 (non-buffered flash) */
144         /* strap, cfg1, & write1 need updates */
145         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
146          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148          "Non-buffered flash (128kB)"},
149         /* Saifun SA25F020 (non-buffered flash) */
150         /* strap, cfg1, & write1 need updates */
151         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
152          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
153          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154          "Non-buffered flash (256kB)"},
155         /* Expansion entry 0100 */
156         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
157          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159          "Entry 0100"},
160         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
161         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
162          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
163          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
167          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
168          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170         /* Saifun SA25F005 (non-buffered flash) */
171         /* strap, cfg1, & write1 need updates */
172         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
173          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175          "Non-buffered flash (64kB)"},
176         /* Fast EEPROM */
177         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
178          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
179          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180          "EEPROM - fast"},
181         /* Expansion entry 1001 */
182         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
183          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
184          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185          "Entry 1001"},
186         /* Expansion entry 1010 */
187         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190          "Entry 1010"},
191         /* ATMEL AT45DB011B (buffered flash) */
192         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
193          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
194          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195          "Buffered flash (128kB)"},
196         /* Expansion entry 1100 */
197         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
198          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
199          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200          "Entry 1100"},
201         /* Expansion entry 1101 */
202         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
203          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205          "Entry 1101"},
206         /* Ateml Expansion entry 1110 */
207         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
208          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
209          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210          "Entry 1110 (Atmel)"},
211         /* ATMEL AT45DB021B (buffered flash) */
212         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
213          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215          "Buffered flash (256kB)"},
216 };
217
218 static struct flash_spec flash_5709 = {
219         .flags          = BNX2_NV_BUFFERED,
220         .page_bits      = BCM5709_FLASH_PAGE_BITS,
221         .page_size      = BCM5709_FLASH_PAGE_SIZE,
222         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
223         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
224         .name           = "5709 Buffered flash (256kB)",
225 };
226
227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
229 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
230 {
231         u32 diff;
232
233         smp_mb();
234
235         /* The ring uses 256 indices for 255 entries, one of them
236          * needs to be skipped.
237          */
238         diff = bp->tx_prod - bp->tx_cons;
239         if (unlikely(diff >= TX_DESC_CNT)) {
240                 diff &= 0xffff;
241                 if (diff == TX_DESC_CNT)
242                         diff = MAX_TX_DESC_CNT;
243         }
244         return (bp->tx_ring_size - diff);
245 }
246
247 static u32
248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249 {
250         u32 val;
251
252         spin_lock_bh(&bp->indirect_lock);
253         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
254         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255         spin_unlock_bh(&bp->indirect_lock);
256         return val;
257 }
258
259 static void
260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261 {
262         spin_lock_bh(&bp->indirect_lock);
263         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
265         spin_unlock_bh(&bp->indirect_lock);
266 }
267
268 static void
269 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
270 {
271         offset += cid_addr;
272         spin_lock_bh(&bp->indirect_lock);
273         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
274                 int i;
275
276                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
277                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
278                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
279                 for (i = 0; i < 5; i++) {
280                         u32 val;
281                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
282                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
283                                 break;
284                         udelay(5);
285                 }
286         } else {
287                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
288                 REG_WR(bp, BNX2_CTX_DATA, val);
289         }
290         spin_unlock_bh(&bp->indirect_lock);
291 }
292
293 static int
294 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
295 {
296         u32 val1;
297         int i, ret;
298
299         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
300                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
301                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
302
303                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
304                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
305
306                 udelay(40);
307         }
308
309         val1 = (bp->phy_addr << 21) | (reg << 16) |
310                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
311                 BNX2_EMAC_MDIO_COMM_START_BUSY;
312         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
313
314         for (i = 0; i < 50; i++) {
315                 udelay(10);
316
317                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
318                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
319                         udelay(5);
320
321                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
322                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
323
324                         break;
325                 }
326         }
327
328         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
329                 *val = 0x0;
330                 ret = -EBUSY;
331         }
332         else {
333                 *val = val1;
334                 ret = 0;
335         }
336
337         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
338                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
339                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
340
341                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
342                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
343
344                 udelay(40);
345         }
346
347         return ret;
348 }
349
350 static int
351 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
352 {
353         u32 val1;
354         int i, ret;
355
356         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
357                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
358                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
359
360                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
361                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
362
363                 udelay(40);
364         }
365
366         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
367                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
368                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
369         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
370
371         for (i = 0; i < 50; i++) {
372                 udelay(10);
373
374                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
375                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
376                         udelay(5);
377                         break;
378                 }
379         }
380
381         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
382                 ret = -EBUSY;
383         else
384                 ret = 0;
385
386         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
387                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
388                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
389
390                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
391                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
392
393                 udelay(40);
394         }
395
396         return ret;
397 }
398
399 static void
400 bnx2_disable_int(struct bnx2 *bp)
401 {
402         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
403                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
404         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
405 }
406
407 static void
408 bnx2_enable_int(struct bnx2 *bp)
409 {
410         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
411                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
412                BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
413
414         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
415                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
416
417         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
418 }
419
420 static void
421 bnx2_disable_int_sync(struct bnx2 *bp)
422 {
423         atomic_inc(&bp->intr_sem);
424         bnx2_disable_int(bp);
425         synchronize_irq(bp->pdev->irq);
426 }
427
428 static void
429 bnx2_netif_stop(struct bnx2 *bp)
430 {
431         bnx2_disable_int_sync(bp);
432         if (netif_running(bp->dev)) {
433                 napi_disable(&bp->napi);
434                 netif_tx_disable(bp->dev);
435                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
436         }
437 }
438
439 static void
440 bnx2_netif_start(struct bnx2 *bp)
441 {
442         if (atomic_dec_and_test(&bp->intr_sem)) {
443                 if (netif_running(bp->dev)) {
444                         netif_wake_queue(bp->dev);
445                         napi_enable(&bp->napi);
446                         bnx2_enable_int(bp);
447                 }
448         }
449 }
450
451 static void
452 bnx2_free_mem(struct bnx2 *bp)
453 {
454         int i;
455
456         for (i = 0; i < bp->ctx_pages; i++) {
457                 if (bp->ctx_blk[i]) {
458                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
459                                             bp->ctx_blk[i],
460                                             bp->ctx_blk_mapping[i]);
461                         bp->ctx_blk[i] = NULL;
462                 }
463         }
464         if (bp->status_blk) {
465                 pci_free_consistent(bp->pdev, bp->status_stats_size,
466                                     bp->status_blk, bp->status_blk_mapping);
467                 bp->status_blk = NULL;
468                 bp->stats_blk = NULL;
469         }
470         if (bp->tx_desc_ring) {
471                 pci_free_consistent(bp->pdev,
472                                     sizeof(struct tx_bd) * TX_DESC_CNT,
473                                     bp->tx_desc_ring, bp->tx_desc_mapping);
474                 bp->tx_desc_ring = NULL;
475         }
476         kfree(bp->tx_buf_ring);
477         bp->tx_buf_ring = NULL;
478         for (i = 0; i < bp->rx_max_ring; i++) {
479                 if (bp->rx_desc_ring[i])
480                         pci_free_consistent(bp->pdev,
481                                             sizeof(struct rx_bd) * RX_DESC_CNT,
482                                             bp->rx_desc_ring[i],
483                                             bp->rx_desc_mapping[i]);
484                 bp->rx_desc_ring[i] = NULL;
485         }
486         vfree(bp->rx_buf_ring);
487         bp->rx_buf_ring = NULL;
488 }
489
490 static int
491 bnx2_alloc_mem(struct bnx2 *bp)
492 {
493         int i, status_blk_size;
494
495         bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
496                                   GFP_KERNEL);
497         if (bp->tx_buf_ring == NULL)
498                 return -ENOMEM;
499
500         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
501                                                 sizeof(struct tx_bd) *
502                                                 TX_DESC_CNT,
503                                                 &bp->tx_desc_mapping);
504         if (bp->tx_desc_ring == NULL)
505                 goto alloc_mem_err;
506
507         bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
508                                   bp->rx_max_ring);
509         if (bp->rx_buf_ring == NULL)
510                 goto alloc_mem_err;
511
512         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
513                                    bp->rx_max_ring);
514
515         for (i = 0; i < bp->rx_max_ring; i++) {
516                 bp->rx_desc_ring[i] =
517                         pci_alloc_consistent(bp->pdev,
518                                              sizeof(struct rx_bd) * RX_DESC_CNT,
519                                              &bp->rx_desc_mapping[i]);
520                 if (bp->rx_desc_ring[i] == NULL)
521                         goto alloc_mem_err;
522
523         }
524
525         /* Combine status and statistics blocks into one allocation. */
526         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
527         bp->status_stats_size = status_blk_size +
528                                 sizeof(struct statistics_block);
529
530         bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
531                                               &bp->status_blk_mapping);
532         if (bp->status_blk == NULL)
533                 goto alloc_mem_err;
534
535         memset(bp->status_blk, 0, bp->status_stats_size);
536
537         bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
538                                   status_blk_size);
539
540         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
541
542         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
543                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
544                 if (bp->ctx_pages == 0)
545                         bp->ctx_pages = 1;
546                 for (i = 0; i < bp->ctx_pages; i++) {
547                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
548                                                 BCM_PAGE_SIZE,
549                                                 &bp->ctx_blk_mapping[i]);
550                         if (bp->ctx_blk[i] == NULL)
551                                 goto alloc_mem_err;
552                 }
553         }
554         return 0;
555
556 alloc_mem_err:
557         bnx2_free_mem(bp);
558         return -ENOMEM;
559 }
560
561 static void
562 bnx2_report_fw_link(struct bnx2 *bp)
563 {
564         u32 fw_link_status = 0;
565
566         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
567                 return;
568
569         if (bp->link_up) {
570                 u32 bmsr;
571
572                 switch (bp->line_speed) {
573                 case SPEED_10:
574                         if (bp->duplex == DUPLEX_HALF)
575                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
576                         else
577                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
578                         break;
579                 case SPEED_100:
580                         if (bp->duplex == DUPLEX_HALF)
581                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
582                         else
583                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
584                         break;
585                 case SPEED_1000:
586                         if (bp->duplex == DUPLEX_HALF)
587                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
588                         else
589                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
590                         break;
591                 case SPEED_2500:
592                         if (bp->duplex == DUPLEX_HALF)
593                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
594                         else
595                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
596                         break;
597                 }
598
599                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
600
601                 if (bp->autoneg) {
602                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
603
604                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
605                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
606
607                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
608                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
609                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
610                         else
611                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
612                 }
613         }
614         else
615                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
616
617         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
618 }
619
620 static char *
621 bnx2_xceiver_str(struct bnx2 *bp)
622 {
623         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
624                 ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" :
625                  "Copper"));
626 }
627
628 static void
629 bnx2_report_link(struct bnx2 *bp)
630 {
631         if (bp->link_up) {
632                 netif_carrier_on(bp->dev);
633                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
634                        bnx2_xceiver_str(bp));
635
636                 printk("%d Mbps ", bp->line_speed);
637
638                 if (bp->duplex == DUPLEX_FULL)
639                         printk("full duplex");
640                 else
641                         printk("half duplex");
642
643                 if (bp->flow_ctrl) {
644                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
645                                 printk(", receive ");
646                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
647                                         printk("& transmit ");
648                         }
649                         else {
650                                 printk(", transmit ");
651                         }
652                         printk("flow control ON");
653                 }
654                 printk("\n");
655         }
656         else {
657                 netif_carrier_off(bp->dev);
658                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
659                        bnx2_xceiver_str(bp));
660         }
661
662         bnx2_report_fw_link(bp);
663 }
664
665 static void
666 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
667 {
668         u32 local_adv, remote_adv;
669
670         bp->flow_ctrl = 0;
671         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
672                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
673
674                 if (bp->duplex == DUPLEX_FULL) {
675                         bp->flow_ctrl = bp->req_flow_ctrl;
676                 }
677                 return;
678         }
679
680         if (bp->duplex != DUPLEX_FULL) {
681                 return;
682         }
683
684         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
685             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
686                 u32 val;
687
688                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
689                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
690                         bp->flow_ctrl |= FLOW_CTRL_TX;
691                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
692                         bp->flow_ctrl |= FLOW_CTRL_RX;
693                 return;
694         }
695
696         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
697         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
698
699         if (bp->phy_flags & PHY_SERDES_FLAG) {
700                 u32 new_local_adv = 0;
701                 u32 new_remote_adv = 0;
702
703                 if (local_adv & ADVERTISE_1000XPAUSE)
704                         new_local_adv |= ADVERTISE_PAUSE_CAP;
705                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
706                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
707                 if (remote_adv & ADVERTISE_1000XPAUSE)
708                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
709                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
710                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
711
712                 local_adv = new_local_adv;
713                 remote_adv = new_remote_adv;
714         }
715
716         /* See Table 28B-3 of 802.3ab-1999 spec. */
717         if (local_adv & ADVERTISE_PAUSE_CAP) {
718                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
719                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
720                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
721                         }
722                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
723                                 bp->flow_ctrl = FLOW_CTRL_RX;
724                         }
725                 }
726                 else {
727                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
728                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
729                         }
730                 }
731         }
732         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
733                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
734                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
735
736                         bp->flow_ctrl = FLOW_CTRL_TX;
737                 }
738         }
739 }
740
741 static int
742 bnx2_5709s_linkup(struct bnx2 *bp)
743 {
744         u32 val, speed;
745
746         bp->link_up = 1;
747
748         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
749         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
750         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
751
752         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
753                 bp->line_speed = bp->req_line_speed;
754                 bp->duplex = bp->req_duplex;
755                 return 0;
756         }
757         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
758         switch (speed) {
759                 case MII_BNX2_GP_TOP_AN_SPEED_10:
760                         bp->line_speed = SPEED_10;
761                         break;
762                 case MII_BNX2_GP_TOP_AN_SPEED_100:
763                         bp->line_speed = SPEED_100;
764                         break;
765                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
766                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
767                         bp->line_speed = SPEED_1000;
768                         break;
769                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
770                         bp->line_speed = SPEED_2500;
771                         break;
772         }
773         if (val & MII_BNX2_GP_TOP_AN_FD)
774                 bp->duplex = DUPLEX_FULL;
775         else
776                 bp->duplex = DUPLEX_HALF;
777         return 0;
778 }
779
780 static int
781 bnx2_5708s_linkup(struct bnx2 *bp)
782 {
783         u32 val;
784
785         bp->link_up = 1;
786         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
787         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
788                 case BCM5708S_1000X_STAT1_SPEED_10:
789                         bp->line_speed = SPEED_10;
790                         break;
791                 case BCM5708S_1000X_STAT1_SPEED_100:
792                         bp->line_speed = SPEED_100;
793                         break;
794                 case BCM5708S_1000X_STAT1_SPEED_1G:
795                         bp->line_speed = SPEED_1000;
796                         break;
797                 case BCM5708S_1000X_STAT1_SPEED_2G5:
798                         bp->line_speed = SPEED_2500;
799                         break;
800         }
801         if (val & BCM5708S_1000X_STAT1_FD)
802                 bp->duplex = DUPLEX_FULL;
803         else
804                 bp->duplex = DUPLEX_HALF;
805
806         return 0;
807 }
808
809 static int
810 bnx2_5706s_linkup(struct bnx2 *bp)
811 {
812         u32 bmcr, local_adv, remote_adv, common;
813
814         bp->link_up = 1;
815         bp->line_speed = SPEED_1000;
816
817         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
818         if (bmcr & BMCR_FULLDPLX) {
819                 bp->duplex = DUPLEX_FULL;
820         }
821         else {
822                 bp->duplex = DUPLEX_HALF;
823         }
824
825         if (!(bmcr & BMCR_ANENABLE)) {
826                 return 0;
827         }
828
829         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
830         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
831
832         common = local_adv & remote_adv;
833         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
834
835                 if (common & ADVERTISE_1000XFULL) {
836                         bp->duplex = DUPLEX_FULL;
837                 }
838                 else {
839                         bp->duplex = DUPLEX_HALF;
840                 }
841         }
842
843         return 0;
844 }
845
846 static int
847 bnx2_copper_linkup(struct bnx2 *bp)
848 {
849         u32 bmcr;
850
851         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
852         if (bmcr & BMCR_ANENABLE) {
853                 u32 local_adv, remote_adv, common;
854
855                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
856                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
857
858                 common = local_adv & (remote_adv >> 2);
859                 if (common & ADVERTISE_1000FULL) {
860                         bp->line_speed = SPEED_1000;
861                         bp->duplex = DUPLEX_FULL;
862                 }
863                 else if (common & ADVERTISE_1000HALF) {
864                         bp->line_speed = SPEED_1000;
865                         bp->duplex = DUPLEX_HALF;
866                 }
867                 else {
868                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
869                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
870
871                         common = local_adv & remote_adv;
872                         if (common & ADVERTISE_100FULL) {
873                                 bp->line_speed = SPEED_100;
874                                 bp->duplex = DUPLEX_FULL;
875                         }
876                         else if (common & ADVERTISE_100HALF) {
877                                 bp->line_speed = SPEED_100;
878                                 bp->duplex = DUPLEX_HALF;
879                         }
880                         else if (common & ADVERTISE_10FULL) {
881                                 bp->line_speed = SPEED_10;
882                                 bp->duplex = DUPLEX_FULL;
883                         }
884                         else if (common & ADVERTISE_10HALF) {
885                                 bp->line_speed = SPEED_10;
886                                 bp->duplex = DUPLEX_HALF;
887                         }
888                         else {
889                                 bp->line_speed = 0;
890                                 bp->link_up = 0;
891                         }
892                 }
893         }
894         else {
895                 if (bmcr & BMCR_SPEED100) {
896                         bp->line_speed = SPEED_100;
897                 }
898                 else {
899                         bp->line_speed = SPEED_10;
900                 }
901                 if (bmcr & BMCR_FULLDPLX) {
902                         bp->duplex = DUPLEX_FULL;
903                 }
904                 else {
905                         bp->duplex = DUPLEX_HALF;
906                 }
907         }
908
909         return 0;
910 }
911
912 static int
913 bnx2_set_mac_link(struct bnx2 *bp)
914 {
915         u32 val;
916
917         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
918         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
919                 (bp->duplex == DUPLEX_HALF)) {
920                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
921         }
922
923         /* Configure the EMAC mode register. */
924         val = REG_RD(bp, BNX2_EMAC_MODE);
925
926         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
927                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
928                 BNX2_EMAC_MODE_25G_MODE);
929
930         if (bp->link_up) {
931                 switch (bp->line_speed) {
932                         case SPEED_10:
933                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
934                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
935                                         break;
936                                 }
937                                 /* fall through */
938                         case SPEED_100:
939                                 val |= BNX2_EMAC_MODE_PORT_MII;
940                                 break;
941                         case SPEED_2500:
942                                 val |= BNX2_EMAC_MODE_25G_MODE;
943                                 /* fall through */
944                         case SPEED_1000:
945                                 val |= BNX2_EMAC_MODE_PORT_GMII;
946                                 break;
947                 }
948         }
949         else {
950                 val |= BNX2_EMAC_MODE_PORT_GMII;
951         }
952
953         /* Set the MAC to operate in the appropriate duplex mode. */
954         if (bp->duplex == DUPLEX_HALF)
955                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
956         REG_WR(bp, BNX2_EMAC_MODE, val);
957
958         /* Enable/disable rx PAUSE. */
959         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
960
961         if (bp->flow_ctrl & FLOW_CTRL_RX)
962                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
963         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
964
965         /* Enable/disable tx PAUSE. */
966         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
967         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
968
969         if (bp->flow_ctrl & FLOW_CTRL_TX)
970                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
971         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
972
973         /* Acknowledge the interrupt. */
974         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
975
976         return 0;
977 }
978
979 static void
980 bnx2_enable_bmsr1(struct bnx2 *bp)
981 {
982         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
983             (CHIP_NUM(bp) == CHIP_NUM_5709))
984                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
985                                MII_BNX2_BLK_ADDR_GP_STATUS);
986 }
987
988 static void
989 bnx2_disable_bmsr1(struct bnx2 *bp)
990 {
991         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
992             (CHIP_NUM(bp) == CHIP_NUM_5709))
993                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
994                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
995 }
996
997 static int
998 bnx2_test_and_enable_2g5(struct bnx2 *bp)
999 {
1000         u32 up1;
1001         int ret = 1;
1002
1003         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1004                 return 0;
1005
1006         if (bp->autoneg & AUTONEG_SPEED)
1007                 bp->advertising |= ADVERTISED_2500baseX_Full;
1008
1009         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1010                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1011
1012         bnx2_read_phy(bp, bp->mii_up1, &up1);
1013         if (!(up1 & BCM5708S_UP1_2G5)) {
1014                 up1 |= BCM5708S_UP1_2G5;
1015                 bnx2_write_phy(bp, bp->mii_up1, up1);
1016                 ret = 0;
1017         }
1018
1019         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1020                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1021                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1022
1023         return ret;
1024 }
1025
1026 static int
1027 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1028 {
1029         u32 up1;
1030         int ret = 0;
1031
1032         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1033                 return 0;
1034
1035         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1036                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1037
1038         bnx2_read_phy(bp, bp->mii_up1, &up1);
1039         if (up1 & BCM5708S_UP1_2G5) {
1040                 up1 &= ~BCM5708S_UP1_2G5;
1041                 bnx2_write_phy(bp, bp->mii_up1, up1);
1042                 ret = 1;
1043         }
1044
1045         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1046                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1047                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1048
1049         return ret;
1050 }
1051
1052 static void
1053 bnx2_enable_forced_2g5(struct bnx2 *bp)
1054 {
1055         u32 bmcr;
1056
1057         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1058                 return;
1059
1060         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1061                 u32 val;
1062
1063                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1064                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1065                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1066                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1067                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1068                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1069
1070                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1071                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1072                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1073
1074         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1075                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1076                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1077         }
1078
1079         if (bp->autoneg & AUTONEG_SPEED) {
1080                 bmcr &= ~BMCR_ANENABLE;
1081                 if (bp->req_duplex == DUPLEX_FULL)
1082                         bmcr |= BMCR_FULLDPLX;
1083         }
1084         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1085 }
1086
1087 static void
1088 bnx2_disable_forced_2g5(struct bnx2 *bp)
1089 {
1090         u32 bmcr;
1091
1092         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1093                 return;
1094
1095         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1096                 u32 val;
1097
1098                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1099                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1100                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1101                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1102                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1103
1104                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1105                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1106                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1107
1108         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1109                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1110                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1111         }
1112
1113         if (bp->autoneg & AUTONEG_SPEED)
1114                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1115         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1116 }
1117
1118 static int
1119 bnx2_set_link(struct bnx2 *bp)
1120 {
1121         u32 bmsr;
1122         u8 link_up;
1123
1124         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1125                 bp->link_up = 1;
1126                 return 0;
1127         }
1128
1129         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1130                 return 0;
1131
1132         link_up = bp->link_up;
1133
1134         bnx2_enable_bmsr1(bp);
1135         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1136         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1137         bnx2_disable_bmsr1(bp);
1138
1139         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1140             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1141                 u32 val;
1142
1143                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1144                 if (val & BNX2_EMAC_STATUS_LINK)
1145                         bmsr |= BMSR_LSTATUS;
1146                 else
1147                         bmsr &= ~BMSR_LSTATUS;
1148         }
1149
1150         if (bmsr & BMSR_LSTATUS) {
1151                 bp->link_up = 1;
1152
1153                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1154                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1155                                 bnx2_5706s_linkup(bp);
1156                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1157                                 bnx2_5708s_linkup(bp);
1158                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1159                                 bnx2_5709s_linkup(bp);
1160                 }
1161                 else {
1162                         bnx2_copper_linkup(bp);
1163                 }
1164                 bnx2_resolve_flow_ctrl(bp);
1165         }
1166         else {
1167                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1168                     (bp->autoneg & AUTONEG_SPEED))
1169                         bnx2_disable_forced_2g5(bp);
1170
1171                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1172                 bp->link_up = 0;
1173         }
1174
1175         if (bp->link_up != link_up) {
1176                 bnx2_report_link(bp);
1177         }
1178
1179         bnx2_set_mac_link(bp);
1180
1181         return 0;
1182 }
1183
1184 static int
1185 bnx2_reset_phy(struct bnx2 *bp)
1186 {
1187         int i;
1188         u32 reg;
1189
1190         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1191
1192 #define PHY_RESET_MAX_WAIT 100
1193         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1194                 udelay(10);
1195
1196                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1197                 if (!(reg & BMCR_RESET)) {
1198                         udelay(20);
1199                         break;
1200                 }
1201         }
1202         if (i == PHY_RESET_MAX_WAIT) {
1203                 return -EBUSY;
1204         }
1205         return 0;
1206 }
1207
1208 static u32
1209 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1210 {
1211         u32 adv = 0;
1212
1213         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1214                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1215
1216                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1217                         adv = ADVERTISE_1000XPAUSE;
1218                 }
1219                 else {
1220                         adv = ADVERTISE_PAUSE_CAP;
1221                 }
1222         }
1223         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1224                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1225                         adv = ADVERTISE_1000XPSE_ASYM;
1226                 }
1227                 else {
1228                         adv = ADVERTISE_PAUSE_ASYM;
1229                 }
1230         }
1231         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1232                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1233                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1234                 }
1235                 else {
1236                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1237                 }
1238         }
1239         return adv;
1240 }
1241
1242 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1243
1244 static int
1245 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1246 {
1247         u32 speed_arg = 0, pause_adv;
1248
1249         pause_adv = bnx2_phy_get_pause_adv(bp);
1250
1251         if (bp->autoneg & AUTONEG_SPEED) {
1252                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1253                 if (bp->advertising & ADVERTISED_10baseT_Half)
1254                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1255                 if (bp->advertising & ADVERTISED_10baseT_Full)
1256                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1257                 if (bp->advertising & ADVERTISED_100baseT_Half)
1258                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1259                 if (bp->advertising & ADVERTISED_100baseT_Full)
1260                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1261                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1262                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1263                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1264                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1265         } else {
1266                 if (bp->req_line_speed == SPEED_2500)
1267                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1268                 else if (bp->req_line_speed == SPEED_1000)
1269                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1270                 else if (bp->req_line_speed == SPEED_100) {
1271                         if (bp->req_duplex == DUPLEX_FULL)
1272                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1273                         else
1274                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1275                 } else if (bp->req_line_speed == SPEED_10) {
1276                         if (bp->req_duplex == DUPLEX_FULL)
1277                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1278                         else
1279                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1280                 }
1281         }
1282
1283         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1284                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1285         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
1286                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1287
1288         if (port == PORT_TP)
1289                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1290                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1291
1292         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
1293
1294         spin_unlock_bh(&bp->phy_lock);
1295         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1296         spin_lock_bh(&bp->phy_lock);
1297
1298         return 0;
1299 }
1300
1301 static int
1302 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1303 {
1304         u32 adv, bmcr;
1305         u32 new_adv = 0;
1306
1307         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1308                 return (bnx2_setup_remote_phy(bp, port));
1309
1310         if (!(bp->autoneg & AUTONEG_SPEED)) {
1311                 u32 new_bmcr;
1312                 int force_link_down = 0;
1313
1314                 if (bp->req_line_speed == SPEED_2500) {
1315                         if (!bnx2_test_and_enable_2g5(bp))
1316                                 force_link_down = 1;
1317                 } else if (bp->req_line_speed == SPEED_1000) {
1318                         if (bnx2_test_and_disable_2g5(bp))
1319                                 force_link_down = 1;
1320                 }
1321                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1322                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1323
1324                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1325                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1326                 new_bmcr |= BMCR_SPEED1000;
1327
1328                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1329                         if (bp->req_line_speed == SPEED_2500)
1330                                 bnx2_enable_forced_2g5(bp);
1331                         else if (bp->req_line_speed == SPEED_1000) {
1332                                 bnx2_disable_forced_2g5(bp);
1333                                 new_bmcr &= ~0x2000;
1334                         }
1335
1336                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1337                         if (bp->req_line_speed == SPEED_2500)
1338                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1339                         else
1340                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1341                 }
1342
1343                 if (bp->req_duplex == DUPLEX_FULL) {
1344                         adv |= ADVERTISE_1000XFULL;
1345                         new_bmcr |= BMCR_FULLDPLX;
1346                 }
1347                 else {
1348                         adv |= ADVERTISE_1000XHALF;
1349                         new_bmcr &= ~BMCR_FULLDPLX;
1350                 }
1351                 if ((new_bmcr != bmcr) || (force_link_down)) {
1352                         /* Force a link down visible on the other side */
1353                         if (bp->link_up) {
1354                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1355                                                ~(ADVERTISE_1000XFULL |
1356                                                  ADVERTISE_1000XHALF));
1357                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1358                                         BMCR_ANRESTART | BMCR_ANENABLE);
1359
1360                                 bp->link_up = 0;
1361                                 netif_carrier_off(bp->dev);
1362                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1363                                 bnx2_report_link(bp);
1364                         }
1365                         bnx2_write_phy(bp, bp->mii_adv, adv);
1366                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1367                 } else {
1368                         bnx2_resolve_flow_ctrl(bp);
1369                         bnx2_set_mac_link(bp);
1370                 }
1371                 return 0;
1372         }
1373
1374         bnx2_test_and_enable_2g5(bp);
1375
1376         if (bp->advertising & ADVERTISED_1000baseT_Full)
1377                 new_adv |= ADVERTISE_1000XFULL;
1378
1379         new_adv |= bnx2_phy_get_pause_adv(bp);
1380
1381         bnx2_read_phy(bp, bp->mii_adv, &adv);
1382         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1383
1384         bp->serdes_an_pending = 0;
1385         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1386                 /* Force a link down visible on the other side */
1387                 if (bp->link_up) {
1388                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1389                         spin_unlock_bh(&bp->phy_lock);
1390                         msleep(20);
1391                         spin_lock_bh(&bp->phy_lock);
1392                 }
1393
1394                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1395                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1396                         BMCR_ANENABLE);
1397                 /* Speed up link-up time when the link partner
1398                  * does not autonegotiate which is very common
1399                  * in blade servers. Some blade servers use
1400                  * IPMI for kerboard input and it's important
1401                  * to minimize link disruptions. Autoneg. involves
1402                  * exchanging base pages plus 3 next pages and
1403                  * normally completes in about 120 msec.
1404                  */
1405                 bp->current_interval = SERDES_AN_TIMEOUT;
1406                 bp->serdes_an_pending = 1;
1407                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1408         } else {
1409                 bnx2_resolve_flow_ctrl(bp);
1410                 bnx2_set_mac_link(bp);
1411         }
1412
1413         return 0;
1414 }
1415
1416 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1417         (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ?                       \
1418                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1419                 (ADVERTISED_1000baseT_Full)
1420
1421 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1422         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1423         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1424         ADVERTISED_1000baseT_Full)
1425
1426 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1427         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1428
1429 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1430
1431 static void
1432 bnx2_set_default_remote_link(struct bnx2 *bp)
1433 {
1434         u32 link;
1435
1436         if (bp->phy_port == PORT_TP)
1437                 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
1438         else
1439                 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
1440
1441         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1442                 bp->req_line_speed = 0;
1443                 bp->autoneg |= AUTONEG_SPEED;
1444                 bp->advertising = ADVERTISED_Autoneg;
1445                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1446                         bp->advertising |= ADVERTISED_10baseT_Half;
1447                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1448                         bp->advertising |= ADVERTISED_10baseT_Full;
1449                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1450                         bp->advertising |= ADVERTISED_100baseT_Half;
1451                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1452                         bp->advertising |= ADVERTISED_100baseT_Full;
1453                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1454                         bp->advertising |= ADVERTISED_1000baseT_Full;
1455                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1456                         bp->advertising |= ADVERTISED_2500baseX_Full;
1457         } else {
1458                 bp->autoneg = 0;
1459                 bp->advertising = 0;
1460                 bp->req_duplex = DUPLEX_FULL;
1461                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1462                         bp->req_line_speed = SPEED_10;
1463                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1464                                 bp->req_duplex = DUPLEX_HALF;
1465                 }
1466                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1467                         bp->req_line_speed = SPEED_100;
1468                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1469                                 bp->req_duplex = DUPLEX_HALF;
1470                 }
1471                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1472                         bp->req_line_speed = SPEED_1000;
1473                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1474                         bp->req_line_speed = SPEED_2500;
1475         }
1476 }
1477
1478 static void
1479 bnx2_set_default_link(struct bnx2 *bp)
1480 {
1481         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1482                 return bnx2_set_default_remote_link(bp);
1483
1484         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1485         bp->req_line_speed = 0;
1486         if (bp->phy_flags & PHY_SERDES_FLAG) {
1487                 u32 reg;
1488
1489                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1490
1491                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
1492                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1493                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1494                         bp->autoneg = 0;
1495                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1496                         bp->req_duplex = DUPLEX_FULL;
1497                 }
1498         } else
1499                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1500 }
1501
1502 static void
1503 bnx2_send_heart_beat(struct bnx2 *bp)
1504 {
1505         u32 msg;
1506         u32 addr;
1507
1508         spin_lock(&bp->indirect_lock);
1509         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1510         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1511         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1512         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1513         spin_unlock(&bp->indirect_lock);
1514 }
1515
1516 static void
1517 bnx2_remote_phy_event(struct bnx2 *bp)
1518 {
1519         u32 msg;
1520         u8 link_up = bp->link_up;
1521         u8 old_port;
1522
1523         msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1524
1525         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1526                 bnx2_send_heart_beat(bp);
1527
1528         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1529
1530         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1531                 bp->link_up = 0;
1532         else {
1533                 u32 speed;
1534
1535                 bp->link_up = 1;
1536                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1537                 bp->duplex = DUPLEX_FULL;
1538                 switch (speed) {
1539                         case BNX2_LINK_STATUS_10HALF:
1540                                 bp->duplex = DUPLEX_HALF;
1541                         case BNX2_LINK_STATUS_10FULL:
1542                                 bp->line_speed = SPEED_10;
1543                                 break;
1544                         case BNX2_LINK_STATUS_100HALF:
1545                                 bp->duplex = DUPLEX_HALF;
1546                         case BNX2_LINK_STATUS_100BASE_T4:
1547                         case BNX2_LINK_STATUS_100FULL:
1548                                 bp->line_speed = SPEED_100;
1549                                 break;
1550                         case BNX2_LINK_STATUS_1000HALF:
1551                                 bp->duplex = DUPLEX_HALF;
1552                         case BNX2_LINK_STATUS_1000FULL:
1553                                 bp->line_speed = SPEED_1000;
1554                                 break;
1555                         case BNX2_LINK_STATUS_2500HALF:
1556                                 bp->duplex = DUPLEX_HALF;
1557                         case BNX2_LINK_STATUS_2500FULL:
1558                                 bp->line_speed = SPEED_2500;
1559                                 break;
1560                         default:
1561                                 bp->line_speed = 0;
1562                                 break;
1563                 }
1564
1565                 spin_lock(&bp->phy_lock);
1566                 bp->flow_ctrl = 0;
1567                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1568                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1569                         if (bp->duplex == DUPLEX_FULL)
1570                                 bp->flow_ctrl = bp->req_flow_ctrl;
1571                 } else {
1572                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1573                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1574                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1575                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1576                 }
1577
1578                 old_port = bp->phy_port;
1579                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1580                         bp->phy_port = PORT_FIBRE;
1581                 else
1582                         bp->phy_port = PORT_TP;
1583
1584                 if (old_port != bp->phy_port)
1585                         bnx2_set_default_link(bp);
1586
1587                 spin_unlock(&bp->phy_lock);
1588         }
1589         if (bp->link_up != link_up)
1590                 bnx2_report_link(bp);
1591
1592         bnx2_set_mac_link(bp);
1593 }
1594
1595 static int
1596 bnx2_set_remote_link(struct bnx2 *bp)
1597 {
1598         u32 evt_code;
1599
1600         evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
1601         switch (evt_code) {
1602                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1603                         bnx2_remote_phy_event(bp);
1604                         break;
1605                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1606                 default:
1607                         bnx2_send_heart_beat(bp);
1608                         break;
1609         }
1610         return 0;
1611 }
1612
1613 static int
1614 bnx2_setup_copper_phy(struct bnx2 *bp)
1615 {
1616         u32 bmcr;
1617         u32 new_bmcr;
1618
1619         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1620
1621         if (bp->autoneg & AUTONEG_SPEED) {
1622                 u32 adv_reg, adv1000_reg;
1623                 u32 new_adv_reg = 0;
1624                 u32 new_adv1000_reg = 0;
1625
1626                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1627                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1628                         ADVERTISE_PAUSE_ASYM);
1629
1630                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1631                 adv1000_reg &= PHY_ALL_1000_SPEED;
1632
1633                 if (bp->advertising & ADVERTISED_10baseT_Half)
1634                         new_adv_reg |= ADVERTISE_10HALF;
1635                 if (bp->advertising & ADVERTISED_10baseT_Full)
1636                         new_adv_reg |= ADVERTISE_10FULL;
1637                 if (bp->advertising & ADVERTISED_100baseT_Half)
1638                         new_adv_reg |= ADVERTISE_100HALF;
1639                 if (bp->advertising & ADVERTISED_100baseT_Full)
1640                         new_adv_reg |= ADVERTISE_100FULL;
1641                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1642                         new_adv1000_reg |= ADVERTISE_1000FULL;
1643
1644                 new_adv_reg |= ADVERTISE_CSMA;
1645
1646                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1647
1648                 if ((adv1000_reg != new_adv1000_reg) ||
1649                         (adv_reg != new_adv_reg) ||
1650                         ((bmcr & BMCR_ANENABLE) == 0)) {
1651
1652                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1653                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1654                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1655                                 BMCR_ANENABLE);
1656                 }
1657                 else if (bp->link_up) {
1658                         /* Flow ctrl may have changed from auto to forced */
1659                         /* or vice-versa. */
1660
1661                         bnx2_resolve_flow_ctrl(bp);
1662                         bnx2_set_mac_link(bp);
1663                 }
1664                 return 0;
1665         }
1666
1667         new_bmcr = 0;
1668         if (bp->req_line_speed == SPEED_100) {
1669                 new_bmcr |= BMCR_SPEED100;
1670         }
1671         if (bp->req_duplex == DUPLEX_FULL) {
1672                 new_bmcr |= BMCR_FULLDPLX;
1673         }
1674         if (new_bmcr != bmcr) {
1675                 u32 bmsr;
1676
1677                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1678                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1679
1680                 if (bmsr & BMSR_LSTATUS) {
1681                         /* Force link down */
1682                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1683                         spin_unlock_bh(&bp->phy_lock);
1684                         msleep(50);
1685                         spin_lock_bh(&bp->phy_lock);
1686
1687                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1688                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1689                 }
1690
1691                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1692
1693                 /* Normally, the new speed is setup after the link has
1694                  * gone down and up again. In some cases, link will not go
1695                  * down so we need to set up the new speed here.
1696                  */
1697                 if (bmsr & BMSR_LSTATUS) {
1698                         bp->line_speed = bp->req_line_speed;
1699                         bp->duplex = bp->req_duplex;
1700                         bnx2_resolve_flow_ctrl(bp);
1701                         bnx2_set_mac_link(bp);
1702                 }
1703         } else {
1704                 bnx2_resolve_flow_ctrl(bp);
1705                 bnx2_set_mac_link(bp);
1706         }
1707         return 0;
1708 }
1709
1710 static int
1711 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1712 {
1713         if (bp->loopback == MAC_LOOPBACK)
1714                 return 0;
1715
1716         if (bp->phy_flags & PHY_SERDES_FLAG) {
1717                 return (bnx2_setup_serdes_phy(bp, port));
1718         }
1719         else {
1720                 return (bnx2_setup_copper_phy(bp));
1721         }
1722 }
1723
1724 static int
1725 bnx2_init_5709s_phy(struct bnx2 *bp)
1726 {
1727         u32 val;
1728
1729         bp->mii_bmcr = MII_BMCR + 0x10;
1730         bp->mii_bmsr = MII_BMSR + 0x10;
1731         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1732         bp->mii_adv = MII_ADVERTISE + 0x10;
1733         bp->mii_lpa = MII_LPA + 0x10;
1734         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1735
1736         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1737         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1738
1739         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1740         bnx2_reset_phy(bp);
1741
1742         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1743
1744         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1745         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1746         val |= MII_BNX2_SD_1000XCTL1_FIBER;
1747         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1748
1749         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1750         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1751         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1752                 val |= BCM5708S_UP1_2G5;
1753         else
1754                 val &= ~BCM5708S_UP1_2G5;
1755         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1756
1757         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1758         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1759         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1760         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1761
1762         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1763
1764         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1765               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1766         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1767
1768         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1769
1770         return 0;
1771 }
1772
1773 static int
1774 bnx2_init_5708s_phy(struct bnx2 *bp)
1775 {
1776         u32 val;
1777
1778         bnx2_reset_phy(bp);
1779
1780         bp->mii_up1 = BCM5708S_UP1;
1781
1782         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1783         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1784         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1785
1786         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1787         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1788         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1789
1790         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1791         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1792         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1793
1794         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1795                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1796                 val |= BCM5708S_UP1_2G5;
1797                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1798         }
1799
1800         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1801             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1802             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1803                 /* increase tx signal amplitude */
1804                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1805                                BCM5708S_BLK_ADDR_TX_MISC);
1806                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1807                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1808                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1809                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1810         }
1811
1812         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1813               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1814
1815         if (val) {
1816                 u32 is_backplane;
1817
1818                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1819                                           BNX2_SHARED_HW_CFG_CONFIG);
1820                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1821                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1822                                        BCM5708S_BLK_ADDR_TX_MISC);
1823                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1824                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1825                                        BCM5708S_BLK_ADDR_DIG);
1826                 }
1827         }
1828         return 0;
1829 }
1830
1831 static int
1832 bnx2_init_5706s_phy(struct bnx2 *bp)
1833 {
1834         bnx2_reset_phy(bp);
1835
1836         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1837
1838         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1839                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1840
1841         if (bp->dev->mtu > 1500) {
1842                 u32 val;
1843
1844                 /* Set extended packet length bit */
1845                 bnx2_write_phy(bp, 0x18, 0x7);
1846                 bnx2_read_phy(bp, 0x18, &val);
1847                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1848
1849                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1850                 bnx2_read_phy(bp, 0x1c, &val);
1851                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1852         }
1853         else {
1854                 u32 val;
1855
1856                 bnx2_write_phy(bp, 0x18, 0x7);
1857                 bnx2_read_phy(bp, 0x18, &val);
1858                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1859
1860                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1861                 bnx2_read_phy(bp, 0x1c, &val);
1862                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1863         }
1864
1865         return 0;
1866 }
1867
1868 static int
1869 bnx2_init_copper_phy(struct bnx2 *bp)
1870 {
1871         u32 val;
1872
1873         bnx2_reset_phy(bp);
1874
1875         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1876                 bnx2_write_phy(bp, 0x18, 0x0c00);
1877                 bnx2_write_phy(bp, 0x17, 0x000a);
1878                 bnx2_write_phy(bp, 0x15, 0x310b);
1879                 bnx2_write_phy(bp, 0x17, 0x201f);
1880                 bnx2_write_phy(bp, 0x15, 0x9506);
1881                 bnx2_write_phy(bp, 0x17, 0x401f);
1882                 bnx2_write_phy(bp, 0x15, 0x14e2);
1883                 bnx2_write_phy(bp, 0x18, 0x0400);
1884         }
1885
1886         if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1887                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1888                                MII_BNX2_DSP_EXPAND_REG | 0x8);
1889                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1890                 val &= ~(1 << 8);
1891                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1892         }
1893
1894         if (bp->dev->mtu > 1500) {
1895                 /* Set extended packet length bit */
1896                 bnx2_write_phy(bp, 0x18, 0x7);
1897                 bnx2_read_phy(bp, 0x18, &val);
1898                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1899
1900                 bnx2_read_phy(bp, 0x10, &val);
1901                 bnx2_write_phy(bp, 0x10, val | 0x1);
1902         }
1903         else {
1904                 bnx2_write_phy(bp, 0x18, 0x7);
1905                 bnx2_read_phy(bp, 0x18, &val);
1906                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1907
1908                 bnx2_read_phy(bp, 0x10, &val);
1909                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1910         }
1911
1912         /* ethernet@wirespeed */
1913         bnx2_write_phy(bp, 0x18, 0x7007);
1914         bnx2_read_phy(bp, 0x18, &val);
1915         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1916         return 0;
1917 }
1918
1919
1920 static int
1921 bnx2_init_phy(struct bnx2 *bp)
1922 {
1923         u32 val;
1924         int rc = 0;
1925
1926         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1927         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1928
1929         bp->mii_bmcr = MII_BMCR;
1930         bp->mii_bmsr = MII_BMSR;
1931         bp->mii_bmsr1 = MII_BMSR;
1932         bp->mii_adv = MII_ADVERTISE;
1933         bp->mii_lpa = MII_LPA;
1934
1935         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1936
1937         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1938                 goto setup_phy;
1939
1940         bnx2_read_phy(bp, MII_PHYSID1, &val);
1941         bp->phy_id = val << 16;
1942         bnx2_read_phy(bp, MII_PHYSID2, &val);
1943         bp->phy_id |= val & 0xffff;
1944
1945         if (bp->phy_flags & PHY_SERDES_FLAG) {
1946                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1947                         rc = bnx2_init_5706s_phy(bp);
1948                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1949                         rc = bnx2_init_5708s_phy(bp);
1950                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1951                         rc = bnx2_init_5709s_phy(bp);
1952         }
1953         else {
1954                 rc = bnx2_init_copper_phy(bp);
1955         }
1956
1957 setup_phy:
1958         if (!rc)
1959                 rc = bnx2_setup_phy(bp, bp->phy_port);
1960
1961         return rc;
1962 }
1963
1964 static int
1965 bnx2_set_mac_loopback(struct bnx2 *bp)
1966 {
1967         u32 mac_mode;
1968
1969         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1970         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1971         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1972         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1973         bp->link_up = 1;
1974         return 0;
1975 }
1976
1977 static int bnx2_test_link(struct bnx2 *);
1978
1979 static int
1980 bnx2_set_phy_loopback(struct bnx2 *bp)
1981 {
1982         u32 mac_mode;
1983         int rc, i;
1984
1985         spin_lock_bh(&bp->phy_lock);
1986         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
1987                             BMCR_SPEED1000);
1988         spin_unlock_bh(&bp->phy_lock);
1989         if (rc)
1990                 return rc;
1991
1992         for (i = 0; i < 10; i++) {
1993                 if (bnx2_test_link(bp) == 0)
1994                         break;
1995                 msleep(100);
1996         }
1997
1998         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1999         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2000                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2001                       BNX2_EMAC_MODE_25G_MODE);
2002
2003         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2004         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2005         bp->link_up = 1;
2006         return 0;
2007 }
2008
2009 static int
2010 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2011 {
2012         int i;
2013         u32 val;
2014
2015         bp->fw_wr_seq++;
2016         msg_data |= bp->fw_wr_seq;
2017
2018         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2019
2020         /* wait for an acknowledgement. */
2021         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2022                 msleep(10);
2023
2024                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
2025
2026                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2027                         break;
2028         }
2029         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2030                 return 0;
2031
2032         /* If we timed out, inform the firmware that this is the case. */
2033         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2034                 if (!silent)
2035                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2036                                             "%x\n", msg_data);
2037
2038                 msg_data &= ~BNX2_DRV_MSG_CODE;
2039                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2040
2041                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2042
2043                 return -EBUSY;
2044         }
2045
2046         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2047                 return -EIO;
2048
2049         return 0;
2050 }
2051
2052 static int
2053 bnx2_init_5709_context(struct bnx2 *bp)
2054 {
2055         int i, ret = 0;
2056         u32 val;
2057
2058         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2059         val |= (BCM_PAGE_BITS - 8) << 16;
2060         REG_WR(bp, BNX2_CTX_COMMAND, val);
2061         for (i = 0; i < 10; i++) {
2062                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2063                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2064                         break;
2065                 udelay(2);
2066         }
2067         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2068                 return -EBUSY;
2069
2070         for (i = 0; i < bp->ctx_pages; i++) {
2071                 int j;
2072
2073                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2074                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2075                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2076                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2077                        (u64) bp->ctx_blk_mapping[i] >> 32);
2078                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2079                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2080                 for (j = 0; j < 10; j++) {
2081
2082                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2083                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2084                                 break;
2085                         udelay(5);
2086                 }
2087                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2088                         ret = -EBUSY;
2089                         break;
2090                 }
2091         }
2092         return ret;
2093 }
2094
2095 static void
2096 bnx2_init_context(struct bnx2 *bp)
2097 {
2098         u32 vcid;
2099
2100         vcid = 96;
2101         while (vcid) {
2102                 u32 vcid_addr, pcid_addr, offset;
2103                 int i;
2104
2105                 vcid--;
2106
2107                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2108                         u32 new_vcid;
2109
2110                         vcid_addr = GET_PCID_ADDR(vcid);
2111                         if (vcid & 0x8) {
2112                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2113                         }
2114                         else {
2115                                 new_vcid = vcid;
2116                         }
2117                         pcid_addr = GET_PCID_ADDR(new_vcid);
2118                 }
2119                 else {
2120                         vcid_addr = GET_CID_ADDR(vcid);
2121                         pcid_addr = vcid_addr;
2122                 }
2123
2124                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2125                         vcid_addr += (i << PHY_CTX_SHIFT);
2126                         pcid_addr += (i << PHY_CTX_SHIFT);
2127
2128                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
2129                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2130
2131                         /* Zero out the context. */
2132                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2133                                 CTX_WR(bp, 0x00, offset, 0);
2134
2135                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2136                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2137                 }
2138         }
2139 }
2140
2141 static int
2142 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2143 {
2144         u16 *good_mbuf;
2145         u32 good_mbuf_cnt;
2146         u32 val;
2147
2148         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2149         if (good_mbuf == NULL) {
2150                 printk(KERN_ERR PFX "Failed to allocate memory in "
2151                                     "bnx2_alloc_bad_rbuf\n");
2152                 return -ENOMEM;
2153         }
2154
2155         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2156                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2157
2158         good_mbuf_cnt = 0;
2159
2160         /* Allocate a bunch of mbufs and save the good ones in an array. */
2161         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2162         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2163                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
2164
2165                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
2166
2167                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2168
2169                 /* The addresses with Bit 9 set are bad memory blocks. */
2170                 if (!(val & (1 << 9))) {
2171                         good_mbuf[good_mbuf_cnt] = (u16) val;
2172                         good_mbuf_cnt++;
2173                 }
2174
2175                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2176         }
2177
2178         /* Free the good ones back to the mbuf pool thus discarding
2179          * all the bad ones. */
2180         while (good_mbuf_cnt) {
2181                 good_mbuf_cnt--;
2182
2183                 val = good_mbuf[good_mbuf_cnt];
2184                 val = (val << 9) | val | 1;
2185
2186                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
2187         }
2188         kfree(good_mbuf);
2189         return 0;
2190 }
2191
2192 static void
2193 bnx2_set_mac_addr(struct bnx2 *bp)
2194 {
2195         u32 val;
2196         u8 *mac_addr = bp->dev->dev_addr;
2197
2198         val = (mac_addr[0] << 8) | mac_addr[1];
2199
2200         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2201
2202         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2203                 (mac_addr[4] << 8) | mac_addr[5];
2204
2205         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2206 }
2207
2208 static inline int
2209 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
2210 {
2211         struct sk_buff *skb;
2212         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2213         dma_addr_t mapping;
2214         struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2215         unsigned long align;
2216
2217         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2218         if (skb == NULL) {
2219                 return -ENOMEM;
2220         }
2221
2222         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2223                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2224
2225         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2226                 PCI_DMA_FROMDEVICE);
2227
2228         rx_buf->skb = skb;
2229         pci_unmap_addr_set(rx_buf, mapping, mapping);
2230
2231         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2232         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2233
2234         bp->rx_prod_bseq += bp->rx_buf_use_size;
2235
2236         return 0;
2237 }
2238
2239 static int
2240 bnx2_phy_event_is_set(struct bnx2 *bp, u32 event)
2241 {
2242         struct status_block *sblk = bp->status_blk;
2243         u32 new_link_state, old_link_state;
2244         int is_set = 1;
2245
2246         new_link_state = sblk->status_attn_bits & event;
2247         old_link_state = sblk->status_attn_bits_ack & event;
2248         if (new_link_state != old_link_state) {
2249                 if (new_link_state)
2250                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2251                 else
2252                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2253         } else
2254                 is_set = 0;
2255
2256         return is_set;
2257 }
2258
2259 static void
2260 bnx2_phy_int(struct bnx2 *bp)
2261 {
2262         if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) {
2263                 spin_lock(&bp->phy_lock);
2264                 bnx2_set_link(bp);
2265                 spin_unlock(&bp->phy_lock);
2266         }
2267         if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_TIMER_ABORT))
2268                 bnx2_set_remote_link(bp);
2269
2270 }
2271
2272 static void
2273 bnx2_tx_int(struct bnx2 *bp)
2274 {
2275         struct status_block *sblk = bp->status_blk;
2276         u16 hw_cons, sw_cons, sw_ring_cons;
2277         int tx_free_bd = 0;
2278
2279         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
2280         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2281                 hw_cons++;
2282         }
2283         sw_cons = bp->tx_cons;
2284
2285         while (sw_cons != hw_cons) {
2286                 struct sw_bd *tx_buf;
2287                 struct sk_buff *skb;
2288                 int i, last;
2289
2290                 sw_ring_cons = TX_RING_IDX(sw_cons);
2291
2292                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2293                 skb = tx_buf->skb;
2294
2295                 /* partial BD completions possible with TSO packets */
2296                 if (skb_is_gso(skb)) {
2297                         u16 last_idx, last_ring_idx;
2298
2299                         last_idx = sw_cons +
2300                                 skb_shinfo(skb)->nr_frags + 1;
2301                         last_ring_idx = sw_ring_cons +
2302                                 skb_shinfo(skb)->nr_frags + 1;
2303                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2304                                 last_idx++;
2305                         }
2306                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2307                                 break;
2308                         }
2309                 }
2310
2311                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2312                         skb_headlen(skb), PCI_DMA_TODEVICE);
2313
2314                 tx_buf->skb = NULL;
2315                 last = skb_shinfo(skb)->nr_frags;
2316
2317                 for (i = 0; i < last; i++) {
2318                         sw_cons = NEXT_TX_BD(sw_cons);
2319
2320                         pci_unmap_page(bp->pdev,
2321                                 pci_unmap_addr(
2322                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2323                                         mapping),
2324                                 skb_shinfo(skb)->frags[i].size,
2325                                 PCI_DMA_TODEVICE);
2326                 }
2327
2328                 sw_cons = NEXT_TX_BD(sw_cons);
2329
2330                 tx_free_bd += last + 1;
2331
2332                 dev_kfree_skb(skb);
2333
2334                 hw_cons = bp->hw_tx_cons =
2335                         sblk->status_tx_quick_consumer_index0;
2336
2337                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2338                         hw_cons++;
2339                 }
2340         }
2341
2342         bp->tx_cons = sw_cons;
2343         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2344          * before checking for netif_queue_stopped().  Without the
2345          * memory barrier, there is a small possibility that bnx2_start_xmit()
2346          * will miss it and cause the queue to be stopped forever.
2347          */
2348         smp_mb();
2349
2350         if (unlikely(netif_queue_stopped(bp->dev)) &&
2351                      (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
2352                 netif_tx_lock(bp->dev);
2353                 if ((netif_queue_stopped(bp->dev)) &&
2354                     (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
2355                         netif_wake_queue(bp->dev);
2356                 netif_tx_unlock(bp->dev);
2357         }
2358 }
2359
2360 static inline void
2361 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
2362         u16 cons, u16 prod)
2363 {
2364         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2365         struct rx_bd *cons_bd, *prod_bd;
2366
2367         cons_rx_buf = &bp->rx_buf_ring[cons];
2368         prod_rx_buf = &bp->rx_buf_ring[prod];
2369
2370         pci_dma_sync_single_for_device(bp->pdev,
2371                 pci_unmap_addr(cons_rx_buf, mapping),
2372                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2373
2374         bp->rx_prod_bseq += bp->rx_buf_use_size;
2375
2376         prod_rx_buf->skb = skb;
2377
2378         if (cons == prod)
2379                 return;
2380
2381         pci_unmap_addr_set(prod_rx_buf, mapping,
2382                         pci_unmap_addr(cons_rx_buf, mapping));
2383
2384         cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2385         prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2386         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2387         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2388 }
2389
2390 static int
2391 bnx2_rx_int(struct bnx2 *bp, int budget)
2392 {
2393         struct status_block *sblk = bp->status_blk;
2394         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2395         struct l2_fhdr *rx_hdr;
2396         int rx_pkt = 0;
2397
2398         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
2399         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2400                 hw_cons++;
2401         }
2402         sw_cons = bp->rx_cons;
2403         sw_prod = bp->rx_prod;
2404
2405         /* Memory barrier necessary as speculative reads of the rx
2406          * buffer can be ahead of the index in the status block
2407          */
2408         rmb();
2409         while (sw_cons != hw_cons) {
2410                 unsigned int len;
2411                 u32 status;
2412                 struct sw_bd *rx_buf;
2413                 struct sk_buff *skb;
2414                 dma_addr_t dma_addr;
2415
2416                 sw_ring_cons = RX_RING_IDX(sw_cons);
2417                 sw_ring_prod = RX_RING_IDX(sw_prod);
2418
2419                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2420                 skb = rx_buf->skb;
2421
2422                 rx_buf->skb = NULL;
2423
2424                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2425
2426                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2427                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2428
2429                 rx_hdr = (struct l2_fhdr *) skb->data;
2430                 len = rx_hdr->l2_fhdr_pkt_len - 4;
2431
2432                 if ((status = rx_hdr->l2_fhdr_status) &
2433                         (L2_FHDR_ERRORS_BAD_CRC |
2434                         L2_FHDR_ERRORS_PHY_DECODE |
2435                         L2_FHDR_ERRORS_ALIGNMENT |
2436                         L2_FHDR_ERRORS_TOO_SHORT |
2437                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2438
2439                         goto reuse_rx;
2440                 }
2441
2442                 /* Since we don't have a jumbo ring, copy small packets
2443                  * if mtu > 1500
2444                  */
2445                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
2446                         struct sk_buff *new_skb;
2447
2448                         new_skb = netdev_alloc_skb(bp->dev, len + 2);
2449                         if (new_skb == NULL)
2450                                 goto reuse_rx;
2451
2452                         /* aligned copy */
2453                         skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2454                                       new_skb->data, len + 2);
2455                         skb_reserve(new_skb, 2);
2456                         skb_put(new_skb, len);
2457
2458                         bnx2_reuse_rx_skb(bp, skb,
2459                                 sw_ring_cons, sw_ring_prod);
2460
2461                         skb = new_skb;
2462                 }
2463                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
2464                         pci_unmap_single(bp->pdev, dma_addr,
2465                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
2466
2467                         skb_reserve(skb, bp->rx_offset);
2468                         skb_put(skb, len);
2469                 }
2470                 else {
2471 reuse_rx:
2472                         bnx2_reuse_rx_skb(bp, skb,
2473                                 sw_ring_cons, sw_ring_prod);
2474                         goto next_rx;
2475                 }
2476
2477                 skb->protocol = eth_type_trans(skb, bp->dev);
2478
2479                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2480                         (ntohs(skb->protocol) != 0x8100)) {
2481
2482                         dev_kfree_skb(skb);
2483                         goto next_rx;
2484
2485                 }
2486
2487                 skb->ip_summed = CHECKSUM_NONE;
2488                 if (bp->rx_csum &&
2489                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2490                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2491
2492                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2493                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2494                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2495                 }
2496
2497 #ifdef BCM_VLAN
2498                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
2499                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2500                                 rx_hdr->l2_fhdr_vlan_tag);
2501                 }
2502                 else
2503 #endif
2504                         netif_receive_skb(skb);
2505
2506                 bp->dev->last_rx = jiffies;
2507                 rx_pkt++;
2508
2509 next_rx:
2510                 sw_cons = NEXT_RX_BD(sw_cons);
2511                 sw_prod = NEXT_RX_BD(sw_prod);
2512
2513                 if ((rx_pkt == budget))
2514                         break;
2515
2516                 /* Refresh hw_cons to see if there is new work */
2517                 if (sw_cons == hw_cons) {
2518                         hw_cons = bp->hw_rx_cons =
2519                                 sblk->status_rx_quick_consumer_index0;
2520                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
2521                                 hw_cons++;
2522                         rmb();
2523                 }
2524         }
2525         bp->rx_cons = sw_cons;
2526         bp->rx_prod = sw_prod;
2527
2528         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2529
2530         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2531
2532         mmiowb();
2533
2534         return rx_pkt;
2535
2536 }
2537
2538 /* MSI ISR - The only difference between this and the INTx ISR
2539  * is that the MSI interrupt is always serviced.
2540  */
2541 static irqreturn_t
2542 bnx2_msi(int irq, void *dev_instance)
2543 {
2544         struct net_device *dev = dev_instance;
2545         struct bnx2 *bp = netdev_priv(dev);
2546
2547         prefetch(bp->status_blk);
2548         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2549                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2550                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2551
2552         /* Return here if interrupt is disabled. */
2553         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2554                 return IRQ_HANDLED;
2555
2556         netif_rx_schedule(dev, &bp->napi);
2557
2558         return IRQ_HANDLED;
2559 }
2560
2561 static irqreturn_t
2562 bnx2_msi_1shot(int irq, void *dev_instance)
2563 {
2564         struct net_device *dev = dev_instance;
2565         struct bnx2 *bp = netdev_priv(dev);
2566
2567         prefetch(bp->status_blk);
2568
2569         /* Return here if interrupt is disabled. */
2570         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2571                 return IRQ_HANDLED;
2572
2573         netif_rx_schedule(dev, &bp->napi);
2574
2575         return IRQ_HANDLED;
2576 }
2577
2578 static irqreturn_t
2579 bnx2_interrupt(int irq, void *dev_instance)
2580 {
2581         struct net_device *dev = dev_instance;
2582         struct bnx2 *bp = netdev_priv(dev);
2583         struct status_block *sblk = bp->status_blk;
2584
2585         /* When using INTx, it is possible for the interrupt to arrive
2586          * at the CPU before the status block posted prior to the
2587          * interrupt. Reading a register will flush the status block.
2588          * When using MSI, the MSI message will always complete after
2589          * the status block write.
2590          */
2591         if ((sblk->status_idx == bp->last_status_idx) &&
2592             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2593              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2594                 return IRQ_NONE;
2595
2596         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2597                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2598                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2599
2600         /* Read back to deassert IRQ immediately to avoid too many
2601          * spurious interrupts.
2602          */
2603         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2604
2605         /* Return here if interrupt is shared and is disabled. */
2606         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2607                 return IRQ_HANDLED;
2608
2609         if (netif_rx_schedule_prep(dev, &bp->napi)) {
2610                 bp->last_status_idx = sblk->status_idx;
2611                 __netif_rx_schedule(dev, &bp->napi);
2612         }
2613
2614         return IRQ_HANDLED;
2615 }
2616
2617 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
2618                                  STATUS_ATTN_BITS_TIMER_ABORT)
2619
2620 static inline int
2621 bnx2_has_work(struct bnx2 *bp)
2622 {
2623         struct status_block *sblk = bp->status_blk;
2624
2625         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
2626             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
2627                 return 1;
2628
2629         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2630             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2631                 return 1;
2632
2633         return 0;
2634 }
2635
2636 static int bnx2_poll_work(struct bnx2 *bp, int work_done, int budget)
2637 {
2638         struct status_block *sblk = bp->status_blk;
2639         u32 status_attn_bits = sblk->status_attn_bits;
2640         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2641
2642         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2643             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2644
2645                 bnx2_phy_int(bp);
2646
2647                 /* This is needed to take care of transient status
2648                  * during link changes.
2649                  */
2650                 REG_WR(bp, BNX2_HC_COMMAND,
2651                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2652                 REG_RD(bp, BNX2_HC_COMMAND);
2653         }
2654
2655         if (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
2656                 bnx2_tx_int(bp);
2657
2658         if (sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons)
2659                 work_done += bnx2_rx_int(bp, budget - work_done);
2660
2661         return work_done;
2662 }
2663
2664 static int bnx2_poll(struct napi_struct *napi, int budget)
2665 {
2666         struct bnx2 *bp = container_of(napi, struct bnx2, napi);
2667         int work_done = 0;
2668         struct status_block *sblk = bp->status_blk;
2669
2670         while (1) {
2671                 work_done = bnx2_poll_work(bp, work_done, budget);
2672
2673                 if (unlikely(work_done >= budget))
2674                         break;
2675
2676                 /* bp->last_status_idx is used below to tell the hw how
2677                  * much work has been processed, so we must read it before
2678                  * checking for more work.
2679                  */
2680                 bp->last_status_idx = sblk->status_idx;
2681                 rmb();
2682                 if (likely(!bnx2_has_work(bp))) {
2683                         netif_rx_complete(bp->dev, napi);
2684                         if (likely(bp->flags & USING_MSI_FLAG)) {
2685                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2686                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2687                                        bp->last_status_idx);
2688                                 break;
2689                         }
2690                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2691                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2692                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2693                                bp->last_status_idx);
2694
2695                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2696                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2697                                bp->last_status_idx);
2698                         break;
2699                 }
2700         }
2701
2702         return work_done;
2703 }
2704
2705 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2706  * from set_multicast.
2707  */
2708 static void
2709 bnx2_set_rx_mode(struct net_device *dev)
2710 {
2711         struct bnx2 *bp = netdev_priv(dev);
2712         u32 rx_mode, sort_mode;
2713         int i;
2714
2715         spin_lock_bh(&bp->phy_lock);
2716
2717         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2718                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2719         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2720 #ifdef BCM_VLAN
2721         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2722                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2723 #else
2724         if (!(bp->flags & ASF_ENABLE_FLAG))
2725                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2726 #endif
2727         if (dev->flags & IFF_PROMISC) {
2728                 /* Promiscuous mode. */
2729                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2730                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2731                              BNX2_RPM_SORT_USER0_PROM_VLAN;
2732         }
2733         else if (dev->flags & IFF_ALLMULTI) {
2734                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2735                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2736                                0xffffffff);
2737                 }
2738                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2739         }
2740         else {
2741                 /* Accept one or more multicast(s). */
2742                 struct dev_mc_list *mclist;
2743                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2744                 u32 regidx;
2745                 u32 bit;
2746                 u32 crc;
2747
2748                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2749
2750                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2751                      i++, mclist = mclist->next) {
2752
2753                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2754                         bit = crc & 0xff;
2755                         regidx = (bit & 0xe0) >> 5;
2756                         bit &= 0x1f;
2757                         mc_filter[regidx] |= (1 << bit);
2758                 }
2759
2760                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2761                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2762                                mc_filter[i]);
2763                 }
2764
2765                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2766         }
2767
2768         if (rx_mode != bp->rx_mode) {
2769                 bp->rx_mode = rx_mode;
2770                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2771         }
2772
2773         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2774         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2775         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2776
2777         spin_unlock_bh(&bp->phy_lock);
2778 }
2779
2780 static void
2781 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2782         u32 rv2p_proc)
2783 {
2784         int i;
2785         u32 val;
2786
2787
2788         for (i = 0; i < rv2p_code_len; i += 8) {
2789                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2790                 rv2p_code++;
2791                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2792                 rv2p_code++;
2793
2794                 if (rv2p_proc == RV2P_PROC1) {
2795                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2796                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2797                 }
2798                 else {
2799                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2800                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2801                 }
2802         }
2803
2804         /* Reset the processor, un-stall is done later. */
2805         if (rv2p_proc == RV2P_PROC1) {
2806                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2807         }
2808         else {
2809                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2810         }
2811 }
2812
2813 static int
2814 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2815 {
2816         u32 offset;
2817         u32 val;
2818         int rc;
2819
2820         /* Halt the CPU. */
2821         val = REG_RD_IND(bp, cpu_reg->mode);
2822         val |= cpu_reg->mode_value_halt;
2823         REG_WR_IND(bp, cpu_reg->mode, val);
2824         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2825
2826         /* Load the Text area. */
2827         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2828         if (fw->gz_text) {
2829                 int j;
2830
2831                 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
2832                                        fw->gz_text_len);
2833                 if (rc < 0)
2834                         return rc;
2835
2836                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2837                         REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2838                 }
2839         }
2840
2841         /* Load the Data area. */
2842         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2843         if (fw->data) {
2844                 int j;
2845
2846                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2847                         REG_WR_IND(bp, offset, fw->data[j]);
2848                 }
2849         }
2850
2851         /* Load the SBSS area. */
2852         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2853         if (fw->sbss_len) {
2854                 int j;
2855
2856                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2857                         REG_WR_IND(bp, offset, 0);
2858                 }
2859         }
2860
2861         /* Load the BSS area. */
2862         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2863         if (fw->bss_len) {
2864                 int j;
2865
2866                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2867                         REG_WR_IND(bp, offset, 0);
2868                 }
2869         }
2870
2871         /* Load the Read-Only area. */
2872         offset = cpu_reg->spad_base +
2873                 (fw->rodata_addr - cpu_reg->mips_view_base);
2874         if (fw->rodata) {
2875                 int j;
2876
2877                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2878                         REG_WR_IND(bp, offset, fw->rodata[j]);
2879                 }
2880         }
2881
2882         /* Clear the pre-fetch instruction. */
2883         REG_WR_IND(bp, cpu_reg->inst, 0);
2884         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2885
2886         /* Start the CPU. */
2887         val = REG_RD_IND(bp, cpu_reg->mode);
2888         val &= ~cpu_reg->mode_value_halt;
2889         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2890         REG_WR_IND(bp, cpu_reg->mode, val);
2891
2892         return 0;
2893 }
2894
2895 static int
2896 bnx2_init_cpus(struct bnx2 *bp)
2897 {
2898         struct cpu_reg cpu_reg;
2899         struct fw_info *fw;
2900         int rc;
2901         void *text;
2902
2903         /* Initialize the RV2P processor. */
2904         text = vmalloc(FW_BUF_SIZE);
2905         if (!text)
2906                 return -ENOMEM;
2907         rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1));
2908         if (rc < 0)
2909                 goto init_cpu_err;
2910
2911         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
2912
2913         rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2));
2914         if (rc < 0)
2915                 goto init_cpu_err;
2916
2917         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
2918
2919         /* Initialize the RX Processor. */
2920         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2921         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2922         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2923         cpu_reg.state = BNX2_RXP_CPU_STATE;
2924         cpu_reg.state_value_clear = 0xffffff;
2925         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2926         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2927         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2928         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2929         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2930         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2931         cpu_reg.mips_view_base = 0x8000000;
2932
2933         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2934                 fw = &bnx2_rxp_fw_09;
2935         else
2936                 fw = &bnx2_rxp_fw_06;
2937
2938         fw->text = text;
2939         rc = load_cpu_fw(bp, &cpu_reg, fw);
2940         if (rc)
2941                 goto init_cpu_err;
2942
2943         /* Initialize the TX Processor. */
2944         cpu_reg.mode = BNX2_TXP_CPU_MODE;
2945         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2946         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2947         cpu_reg.state = BNX2_TXP_CPU_STATE;
2948         cpu_reg.state_value_clear = 0xffffff;
2949         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2950         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2951         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2952         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2953         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2954         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2955         cpu_reg.mips_view_base = 0x8000000;
2956
2957         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2958                 fw = &bnx2_txp_fw_09;
2959         else
2960                 fw = &bnx2_txp_fw_06;
2961
2962         fw->text = text;
2963         rc = load_cpu_fw(bp, &cpu_reg, fw);
2964         if (rc)
2965                 goto init_cpu_err;
2966
2967         /* Initialize the TX Patch-up Processor. */
2968         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2969         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2970         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2971         cpu_reg.state = BNX2_TPAT_CPU_STATE;
2972         cpu_reg.state_value_clear = 0xffffff;
2973         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2974         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2975         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2976         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2977         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2978         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2979         cpu_reg.mips_view_base = 0x8000000;
2980
2981         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2982                 fw = &bnx2_tpat_fw_09;
2983         else
2984                 fw = &bnx2_tpat_fw_06;
2985
2986         fw->text = text;
2987         rc = load_cpu_fw(bp, &cpu_reg, fw);
2988         if (rc)
2989                 goto init_cpu_err;
2990
2991         /* Initialize the Completion Processor. */
2992         cpu_reg.mode = BNX2_COM_CPU_MODE;
2993         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2994         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2995         cpu_reg.state = BNX2_COM_CPU_STATE;
2996         cpu_reg.state_value_clear = 0xffffff;
2997         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2998         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2999         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3000         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3001         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3002         cpu_reg.spad_base = BNX2_COM_SCRATCH;
3003         cpu_reg.mips_view_base = 0x8000000;
3004
3005         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3006                 fw = &bnx2_com_fw_09;
3007         else
3008                 fw = &bnx2_com_fw_06;
3009
3010         fw->text = text;
3011         rc = load_cpu_fw(bp, &cpu_reg, fw);
3012         if (rc)
3013                 goto init_cpu_err;
3014
3015         /* Initialize the Command Processor. */
3016         cpu_reg.mode = BNX2_CP_CPU_MODE;
3017         cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3018         cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3019         cpu_reg.state = BNX2_CP_CPU_STATE;
3020         cpu_reg.state_value_clear = 0xffffff;
3021         cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3022         cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3023         cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3024         cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3025         cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3026         cpu_reg.spad_base = BNX2_CP_SCRATCH;
3027         cpu_reg.mips_view_base = 0x8000000;
3028
3029         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3030                 fw = &bnx2_cp_fw_09;
3031
3032                 fw->text = text;
3033                 rc = load_cpu_fw(bp, &cpu_reg, fw);
3034                 if (rc)
3035                         goto init_cpu_err;
3036         }
3037 init_cpu_err:
3038         vfree(text);
3039         return rc;
3040 }
3041
3042 static int
3043 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3044 {
3045         u16 pmcsr;
3046
3047         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3048
3049         switch (state) {
3050         case PCI_D0: {
3051                 u32 val;
3052
3053                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3054                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3055                         PCI_PM_CTRL_PME_STATUS);
3056
3057                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3058                         /* delay required during transition out of D3hot */
3059                         msleep(20);
3060
3061                 val = REG_RD(bp, BNX2_EMAC_MODE);
3062                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3063                 val &= ~BNX2_EMAC_MODE_MPKT;
3064                 REG_WR(bp, BNX2_EMAC_MODE, val);
3065
3066                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3067                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3068                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3069                 break;
3070         }
3071         case PCI_D3hot: {
3072                 int i;
3073                 u32 val, wol_msg;
3074
3075                 if (bp->wol) {
3076                         u32 advertising;
3077                         u8 autoneg;
3078
3079                         autoneg = bp->autoneg;
3080                         advertising = bp->advertising;
3081
3082                         if (bp->phy_port == PORT_TP) {
3083                                 bp->autoneg = AUTONEG_SPEED;
3084                                 bp->advertising = ADVERTISED_10baseT_Half |
3085                                         ADVERTISED_10baseT_Full |
3086                                         ADVERTISED_100baseT_Half |
3087                                         ADVERTISED_100baseT_Full |
3088                                         ADVERTISED_Autoneg;
3089                         }
3090
3091                         spin_lock_bh(&bp->phy_lock);
3092                         bnx2_setup_phy(bp, bp->phy_port);
3093                         spin_unlock_bh(&bp->phy_lock);
3094
3095                         bp->autoneg = autoneg;
3096                         bp->advertising = advertising;
3097
3098                         bnx2_set_mac_addr(bp);
3099
3100                         val = REG_RD(bp, BNX2_EMAC_MODE);
3101
3102                         /* Enable port mode. */
3103                         val &= ~BNX2_EMAC_MODE_PORT;
3104                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3105                                BNX2_EMAC_MODE_ACPI_RCVD |
3106                                BNX2_EMAC_MODE_MPKT;
3107                         if (bp->phy_port == PORT_TP)
3108                                 val |= BNX2_EMAC_MODE_PORT_MII;
3109                         else {
3110                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3111                                 if (bp->line_speed == SPEED_2500)
3112                                         val |= BNX2_EMAC_MODE_25G_MODE;
3113                         }
3114
3115                         REG_WR(bp, BNX2_EMAC_MODE, val);
3116
3117                         /* receive all multicast */
3118                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3119                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3120                                        0xffffffff);
3121                         }
3122                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3123                                BNX2_EMAC_RX_MODE_SORT_MODE);
3124
3125                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3126                               BNX2_RPM_SORT_USER0_MC_EN;
3127                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3128                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3129                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3130                                BNX2_RPM_SORT_USER0_ENA);
3131
3132                         /* Need to enable EMAC and RPM for WOL. */
3133                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3134                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3135                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3136                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3137
3138                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3139                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3140                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3141
3142                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3143                 }
3144                 else {
3145                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3146                 }
3147
3148                 if (!(bp->flags & NO_WOL_FLAG))
3149                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3150
3151                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3152                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3153                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3154
3155                         if (bp->wol)
3156                                 pmcsr |= 3;
3157                 }
3158                 else {
3159                         pmcsr |= 3;
3160                 }
3161                 if (bp->wol) {
3162                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3163                 }
3164                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3165                                       pmcsr);
3166
3167                 /* No more memory access after this point until
3168                  * device is brought back to D0.
3169                  */
3170                 udelay(50);
3171                 break;
3172         }
3173         default:
3174                 return -EINVAL;
3175         }
3176         return 0;
3177 }
3178
3179 static int
3180 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3181 {
3182         u32 val;
3183         int j;
3184
3185         /* Request access to the flash interface. */
3186         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3187         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3188                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3189                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3190                         break;
3191
3192                 udelay(5);
3193         }
3194
3195         if (j >= NVRAM_TIMEOUT_COUNT)
3196                 return -EBUSY;
3197
3198         return 0;
3199 }
3200
3201 static int
3202 bnx2_release_nvram_lock(struct bnx2 *bp)
3203 {
3204         int j;
3205         u32 val;
3206
3207         /* Relinquish nvram interface. */
3208         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3209
3210         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3211                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3212                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3213                         break;
3214
3215                 udelay(5);
3216         }
3217
3218         if (j >= NVRAM_TIMEOUT_COUNT)
3219                 return -EBUSY;
3220
3221         return 0;
3222 }
3223
3224
3225 static int
3226 bnx2_enable_nvram_write(struct bnx2 *bp)
3227 {
3228         u32 val;
3229
3230         val = REG_RD(bp, BNX2_MISC_CFG);
3231         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3232
3233         if (bp->flash_info->flags & BNX2_NV_WREN) {
3234                 int j;
3235
3236                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3237                 REG_WR(bp, BNX2_NVM_COMMAND,
3238                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3239
3240                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3241                         udelay(5);
3242
3243                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3244                         if (val & BNX2_NVM_COMMAND_DONE)
3245                                 break;
3246                 }
3247
3248                 if (j >= NVRAM_TIMEOUT_COUNT)
3249                         return -EBUSY;
3250         }
3251         return 0;
3252 }
3253
3254 static void
3255 bnx2_disable_nvram_write(struct bnx2 *bp)
3256 {
3257         u32 val;
3258
3259         val = REG_RD(bp, BNX2_MISC_CFG);
3260         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3261 }
3262
3263
3264 static void
3265 bnx2_enable_nvram_access(struct bnx2 *bp)
3266 {
3267         u32 val;
3268
3269         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3270         /* Enable both bits, even on read. */
3271         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3272                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3273 }
3274
3275 static void
3276 bnx2_disable_nvram_access(struct bnx2 *bp)
3277 {
3278         u32 val;
3279
3280         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3281         /* Disable both bits, even after read. */
3282         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3283                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3284                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3285 }
3286
3287 static int
3288 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3289 {
3290         u32 cmd;
3291         int j;
3292
3293         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3294                 /* Buffered flash, no erase needed */
3295                 return 0;
3296
3297         /* Build an erase command */
3298         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3299               BNX2_NVM_COMMAND_DOIT;
3300
3301         /* Need to clear DONE bit separately. */
3302         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3303
3304         /* Address of the NVRAM to read from. */
3305         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3306
3307         /* Issue an erase command. */
3308         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3309
3310         /* Wait for completion. */
3311         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3312                 u32 val;
3313
3314                 udelay(5);
3315
3316                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3317                 if (val & BNX2_NVM_COMMAND_DONE)
3318                         break;
3319         }
3320
3321         if (j >= NVRAM_TIMEOUT_COUNT)
3322                 return -EBUSY;
3323
3324         return 0;
3325 }
3326
3327 static int
3328 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3329 {
3330         u32 cmd;
3331         int j;
3332
3333         /* Build the command word. */
3334         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3335
3336         /* Calculate an offset of a buffered flash, not needed for 5709. */
3337         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3338                 offset = ((offset / bp->flash_info->page_size) <<
3339                            bp->flash_info->page_bits) +
3340                           (offset % bp->flash_info->page_size);
3341         }
3342
3343         /* Need to clear DONE bit separately. */
3344         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3345
3346         /* Address of the NVRAM to read from. */
3347         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3348
3349         /* Issue a read command. */
3350         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3351
3352         /* Wait for completion. */
3353         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3354                 u32 val;
3355
3356                 udelay(5);
3357
3358                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3359                 if (val & BNX2_NVM_COMMAND_DONE) {
3360                         val = REG_RD(bp, BNX2_NVM_READ);
3361
3362                         val = be32_to_cpu(val);
3363                         memcpy(ret_val, &val, 4);
3364                         break;
3365                 }
3366         }
3367         if (j >= NVRAM_TIMEOUT_COUNT)
3368                 return -EBUSY;
3369
3370         return 0;
3371 }
3372
3373
3374 static int
3375 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3376 {
3377         u32 cmd, val32;
3378         int j;
3379
3380         /* Build the command word. */
3381         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3382
3383         /* Calculate an offset of a buffered flash, not needed for 5709. */
3384         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3385                 offset = ((offset / bp->flash_info->page_size) <<
3386                           bp->flash_info->page_bits) +
3387                          (offset % bp->flash_info->page_size);
3388         }
3389
3390         /* Need to clear DONE bit separately. */
3391         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3392
3393         memcpy(&val32, val, 4);
3394         val32 = cpu_to_be32(val32);
3395
3396         /* Write the data. */
3397         REG_WR(bp, BNX2_NVM_WRITE, val32);
3398
3399         /* Address of the NVRAM to write to. */
3400         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3401
3402         /* Issue the write command. */
3403         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3404
3405         /* Wait for completion. */
3406         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3407                 udelay(5);
3408
3409                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3410                         break;
3411         }
3412         if (j >= NVRAM_TIMEOUT_COUNT)
3413                 return -EBUSY;
3414
3415         return 0;
3416 }
3417
3418 static int
3419 bnx2_init_nvram(struct bnx2 *bp)
3420 {
3421         u32 val;
3422         int j, entry_count, rc = 0;
3423         struct flash_spec *flash;
3424
3425         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3426                 bp->flash_info = &flash_5709;
3427                 goto get_flash_size;
3428         }
3429
3430         /* Determine the selected interface. */
3431         val = REG_RD(bp, BNX2_NVM_CFG1);
3432
3433         entry_count = ARRAY_SIZE(flash_table);
3434
3435         if (val & 0x40000000) {
3436
3437                 /* Flash interface has been reconfigured */
3438                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3439                      j++, flash++) {
3440                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3441                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3442                                 bp->flash_info = flash;
3443                                 break;
3444                         }
3445                 }
3446         }
3447         else {
3448                 u32 mask;
3449                 /* Not yet been reconfigured */
3450
3451                 if (val & (1 << 23))
3452                         mask = FLASH_BACKUP_STRAP_MASK;
3453                 else
3454                         mask = FLASH_STRAP_MASK;
3455
3456                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3457                         j++, flash++) {
3458
3459                         if ((val & mask) == (flash->strapping & mask)) {
3460                                 bp->flash_info = flash;
3461
3462                                 /* Request access to the flash interface. */
3463                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3464                                         return rc;
3465
3466                                 /* Enable access to flash interface */
3467                                 bnx2_enable_nvram_access(bp);
3468
3469                                 /* Reconfigure the flash interface */
3470                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3471                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3472                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3473                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3474
3475                                 /* Disable access to flash interface */
3476                                 bnx2_disable_nvram_access(bp);
3477                                 bnx2_release_nvram_lock(bp);
3478
3479                                 break;
3480                         }
3481                 }
3482         } /* if (val & 0x40000000) */
3483
3484         if (j == entry_count) {
3485                 bp->flash_info = NULL;
3486                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3487                 return -ENODEV;
3488         }
3489
3490 get_flash_size:
3491         val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
3492         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3493         if (val)
3494                 bp->flash_size = val;
3495         else
3496                 bp->flash_size = bp->flash_info->total_size;
3497
3498         return rc;
3499 }
3500
3501 static int
3502 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3503                 int buf_size)
3504 {
3505         int rc = 0;
3506         u32 cmd_flags, offset32, len32, extra;
3507
3508         if (buf_size == 0)
3509                 return 0;
3510
3511         /* Request access to the flash interface. */
3512         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3513                 return rc;
3514
3515         /* Enable access to flash interface */
3516         bnx2_enable_nvram_access(bp);
3517
3518         len32 = buf_size;
3519         offset32 = offset;
3520         extra = 0;
3521
3522         cmd_flags = 0;
3523
3524         if (offset32 & 3) {
3525                 u8 buf[4];
3526                 u32 pre_len;
3527
3528                 offset32 &= ~3;
3529                 pre_len = 4 - (offset & 3);
3530
3531                 if (pre_len >= len32) {
3532                         pre_len = len32;
3533                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3534                                     BNX2_NVM_COMMAND_LAST;
3535                 }
3536                 else {
3537                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3538                 }
3539
3540                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3541
3542                 if (rc)
3543                         return rc;
3544
3545                 memcpy(ret_buf, buf + (offset & 3), pre_len);
3546
3547                 offset32 += 4;
3548                 ret_buf += pre_len;
3549                 len32 -= pre_len;
3550         }
3551         if (len32 & 3) {
3552                 extra = 4 - (len32 & 3);
3553                 len32 = (len32 + 4) & ~3;
3554         }
3555
3556         if (len32 == 4) {
3557                 u8 buf[4];
3558
3559                 if (cmd_flags)
3560                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3561                 else
3562                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3563                                     BNX2_NVM_COMMAND_LAST;
3564
3565                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3566
3567                 memcpy(ret_buf, buf, 4 - extra);
3568         }
3569         else if (len32 > 0) {
3570                 u8 buf[4];
3571
3572                 /* Read the first word. */
3573                 if (cmd_flags)
3574                         cmd_flags = 0;
3575                 else
3576                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3577
3578                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3579
3580                 /* Advance to the next dword. */
3581                 offset32 += 4;
3582                 ret_buf += 4;
3583                 len32 -= 4;
3584
3585                 while (len32 > 4 && rc == 0) {
3586                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3587
3588                         /* Advance to the next dword. */
3589                         offset32 += 4;
3590                         ret_buf += 4;
3591                         len32 -= 4;
3592                 }
3593
3594                 if (rc)
3595                         return rc;
3596
3597                 cmd_flags = BNX2_NVM_COMMAND_LAST;
3598                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3599
3600                 memcpy(ret_buf, buf, 4 - extra);
3601         }
3602
3603         /* Disable access to flash interface */
3604         bnx2_disable_nvram_access(bp);
3605
3606         bnx2_release_nvram_lock(bp);
3607
3608         return rc;
3609 }
3610
3611 static int
3612 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3613                 int buf_size)
3614 {
3615         u32 written, offset32, len32;
3616         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
3617         int rc = 0;
3618         int align_start, align_end;
3619
3620         buf = data_buf;
3621         offset32 = offset;
3622         len32 = buf_size;
3623         align_start = align_end = 0;
3624
3625         if ((align_start = (offset32 & 3))) {
3626                 offset32 &= ~3;
3627                 len32 += align_start;
3628                 if (len32 < 4)
3629                         len32 = 4;
3630                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3631                         return rc;
3632         }
3633
3634         if (len32 & 3) {
3635                 align_end = 4 - (len32 & 3);
3636                 len32 += align_end;
3637                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3638                         return rc;
3639         }
3640
3641         if (align_start || align_end) {
3642                 align_buf = kmalloc(len32, GFP_KERNEL);
3643                 if (align_buf == NULL)
3644                         return -ENOMEM;
3645                 if (align_start) {
3646                         memcpy(align_buf, start, 4);
3647                 }
3648                 if (align_end) {
3649                         memcpy(align_buf + len32 - 4, end, 4);
3650                 }
3651                 memcpy(align_buf + align_start, data_buf, buf_size);
3652                 buf = align_buf;
3653         }
3654
3655         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3656                 flash_buffer = kmalloc(264, GFP_KERNEL);
3657                 if (flash_buffer == NULL) {
3658                         rc = -ENOMEM;
3659                         goto nvram_write_end;
3660                 }
3661         }
3662
3663         written = 0;
3664         while ((written < len32) && (rc == 0)) {
3665                 u32 page_start, page_end, data_start, data_end;
3666                 u32 addr, cmd_flags;
3667                 int i;
3668
3669                 /* Find the page_start addr */
3670                 page_start = offset32 + written;
3671                 page_start -= (page_start % bp->flash_info->page_size);
3672                 /* Find the page_end addr */
3673                 page_end = page_start + bp->flash_info->page_size;
3674                 /* Find the data_start addr */
3675                 data_start = (written == 0) ? offset32 : page_start;
3676                 /* Find the data_end addr */
3677                 data_end = (page_end > offset32 + len32) ?
3678                         (offset32 + len32) : page_end;
3679
3680                 /* Request access to the flash interface. */
3681                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3682                         goto nvram_write_end;
3683
3684                 /* Enable access to flash interface */
3685                 bnx2_enable_nvram_access(bp);
3686
3687                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3688                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3689                         int j;
3690
3691                         /* Read the whole page into the buffer
3692                          * (non-buffer flash only) */
3693                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
3694                                 if (j == (bp->flash_info->page_size - 4)) {
3695                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
3696                                 }
3697                                 rc = bnx2_nvram_read_dword(bp,
3698                                         page_start + j,
3699                                         &flash_buffer[j],
3700                                         cmd_flags);
3701
3702                                 if (rc)
3703                                         goto nvram_write_end;
3704
3705                                 cmd_flags = 0;
3706                         }
3707                 }
3708
3709                 /* Enable writes to flash interface (unlock write-protect) */
3710                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3711                         goto nvram_write_end;
3712
3713                 /* Loop to write back the buffer data from page_start to
3714                  * data_start */
3715                 i = 0;
3716                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3717                         /* Erase the page */
3718                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3719                                 goto nvram_write_end;
3720
3721                         /* Re-enable the write again for the actual write */
3722                         bnx2_enable_nvram_write(bp);
3723
3724                         for (addr = page_start; addr < data_start;
3725                                 addr += 4, i += 4) {
3726
3727                                 rc = bnx2_nvram_write_dword(bp, addr,
3728                                         &flash_buffer[i], cmd_flags);
3729
3730                                 if (rc != 0)
3731                                         goto nvram_write_end;
3732
3733                                 cmd_flags = 0;
3734                         }
3735                 }
3736
3737                 /* Loop to write the new data from data_start to data_end */
3738                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3739                         if ((addr == page_end - 4) ||
3740                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
3741                                  (addr == data_end - 4))) {
3742
3743                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3744                         }
3745                         rc = bnx2_nvram_write_dword(bp, addr, buf,
3746                                 cmd_flags);
3747
3748                         if (rc != 0)
3749                                 goto nvram_write_end;
3750
3751                         cmd_flags = 0;
3752                         buf += 4;
3753                 }
3754
3755                 /* Loop to write back the buffer data from data_end
3756                  * to page_end */
3757                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3758                         for (addr = data_end; addr < page_end;
3759                                 addr += 4, i += 4) {
3760
3761                                 if (addr == page_end-4) {
3762                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3763                                 }
3764                                 rc = bnx2_nvram_write_dword(bp, addr,
3765                                         &flash_buffer[i], cmd_flags);
3766
3767                                 if (rc != 0)
3768                                         goto nvram_write_end;
3769
3770                                 cmd_flags = 0;
3771                         }
3772                 }
3773
3774                 /* Disable writes to flash interface (lock write-protect) */
3775                 bnx2_disable_nvram_write(bp);
3776
3777                 /* Disable access to flash interface */
3778                 bnx2_disable_nvram_access(bp);
3779                 bnx2_release_nvram_lock(bp);
3780
3781                 /* Increment written */
3782                 written += data_end - data_start;
3783         }
3784
3785 nvram_write_end:
3786         kfree(flash_buffer);
3787         kfree(align_buf);
3788         return rc;
3789 }
3790
3791 static void
3792 bnx2_init_remote_phy(struct bnx2 *bp)
3793 {
3794         u32 val;
3795
3796         bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG;
3797         if (!(bp->phy_flags & PHY_SERDES_FLAG))
3798                 return;
3799
3800         val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
3801         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
3802                 return;
3803
3804         if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
3805                 bp->phy_flags |= REMOTE_PHY_CAP_FLAG;
3806
3807                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
3808                 if (val & BNX2_LINK_STATUS_SERDES_LINK)
3809                         bp->phy_port = PORT_FIBRE;
3810                 else
3811                         bp->phy_port = PORT_TP;
3812
3813                 if (netif_running(bp->dev)) {
3814                         u32 sig;
3815
3816                         if (val & BNX2_LINK_STATUS_LINK_UP) {
3817                                 bp->link_up = 1;
3818                                 netif_carrier_on(bp->dev);
3819                         } else {
3820                                 bp->link_up = 0;
3821                                 netif_carrier_off(bp->dev);
3822                         }
3823                         sig = BNX2_DRV_ACK_CAP_SIGNATURE |
3824                               BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
3825                         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
3826                                    sig);
3827                 }
3828         }
3829 }
3830
3831 static int
3832 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3833 {
3834         u32 val;
3835         int i, rc = 0;
3836         u8 old_port;
3837
3838         /* Wait for the current PCI transaction to complete before
3839          * issuing a reset. */
3840         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3841                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3842                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3843                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3844                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3845         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3846         udelay(5);
3847
3848         /* Wait for the firmware to tell us it is ok to issue a reset. */
3849         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3850
3851         /* Deposit a driver reset signature so the firmware knows that
3852          * this is a soft reset. */
3853         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3854                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
3855
3856         /* Do a dummy read to force the chip to complete all current transaction
3857          * before we issue a reset. */
3858         val = REG_RD(bp, BNX2_MISC_ID);
3859
3860         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3861                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
3862                 REG_RD(bp, BNX2_MISC_COMMAND);
3863                 udelay(5);
3864
3865                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3866                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3867
3868                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
3869
3870         } else {
3871                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3872                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3873                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3874
3875                 /* Chip reset. */
3876                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3877
3878                 /* Reading back any register after chip reset will hang the
3879                  * bus on 5706 A0 and A1.  The msleep below provides plenty
3880                  * of margin for write posting.
3881                  */
3882                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3883                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
3884                         msleep(20);
3885
3886                 /* Reset takes approximate 30 usec */
3887                 for (i = 0; i < 10; i++) {
3888                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3889                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3890                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3891                                 break;
3892                         udelay(10);
3893                 }
3894
3895                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3896                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3897                         printk(KERN_ERR PFX "Chip reset did not complete\n");
3898                         return -EBUSY;
3899                 }
3900         }
3901
3902         /* Make sure byte swapping is properly configured. */
3903         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3904         if (val != 0x01020304) {
3905                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3906                 return -ENODEV;
3907         }
3908
3909         /* Wait for the firmware to finish its initialization. */
3910         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3911         if (rc)
3912                 return rc;
3913
3914         spin_lock_bh(&bp->phy_lock);
3915         old_port = bp->phy_port;
3916         bnx2_init_remote_phy(bp);
3917         if ((bp->phy_flags & REMOTE_PHY_CAP_FLAG) && old_port != bp->phy_port)
3918                 bnx2_set_default_remote_link(bp);
3919         spin_unlock_bh(&bp->phy_lock);
3920
3921         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3922                 /* Adjust the voltage regular to two steps lower.  The default
3923                  * of this register is 0x0000000e. */
3924                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3925
3926                 /* Remove bad rbuf memory from the free pool. */
3927                 rc = bnx2_alloc_bad_rbuf(bp);
3928         }
3929
3930         return rc;
3931 }
3932
3933 static int
3934 bnx2_init_chip(struct bnx2 *bp)
3935 {
3936         u32 val;
3937         int rc;
3938
3939         /* Make sure the interrupt is not active. */
3940         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3941
3942         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3943               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3944 #ifdef __BIG_ENDIAN
3945               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3946 #endif
3947               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3948               DMA_READ_CHANS << 12 |
3949               DMA_WRITE_CHANS << 16;
3950
3951         val |= (0x2 << 20) | (1 << 11);
3952
3953         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3954                 val |= (1 << 23);
3955
3956         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3957             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3958                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3959
3960         REG_WR(bp, BNX2_DMA_CONFIG, val);
3961
3962         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3963                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3964                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3965                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3966         }
3967
3968         if (bp->flags & PCIX_FLAG) {
3969                 u16 val16;
3970
3971                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3972                                      &val16);
3973                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3974                                       val16 & ~PCI_X_CMD_ERO);
3975         }
3976
3977         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3978                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3979                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3980                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3981
3982         /* Initialize context mapping and zero out the quick contexts.  The
3983          * context block must have already been enabled. */
3984         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3985                 rc = bnx2_init_5709_context(bp);
3986                 if (rc)
3987                         return rc;
3988         } else
3989                 bnx2_init_context(bp);
3990
3991         if ((rc = bnx2_init_cpus(bp)) != 0)
3992                 return rc;
3993
3994         bnx2_init_nvram(bp);
3995
3996         bnx2_set_mac_addr(bp);
3997
3998         val = REG_RD(bp, BNX2_MQ_CONFIG);
3999         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4000         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4001         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4002                 val |= BNX2_MQ_CONFIG_HALT_DIS;
4003
4004         REG_WR(bp, BNX2_MQ_CONFIG, val);
4005
4006         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4007         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4008         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4009
4010         val = (BCM_PAGE_BITS - 8) << 24;
4011         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4012
4013         /* Configure page size. */
4014         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4015         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4016         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4017         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4018
4019         val = bp->mac_addr[0] +
4020               (bp->mac_addr[1] << 8) +
4021               (bp->mac_addr[2] << 16) +
4022               bp->mac_addr[3] +
4023               (bp->mac_addr[4] << 8) +
4024               (bp->mac_addr[5] << 16);
4025         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4026
4027         /* Program the MTU.  Also include 4 bytes for CRC32. */
4028         val = bp->dev->mtu + ETH_HLEN + 4;
4029         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4030                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4031         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4032
4033         bp->last_status_idx = 0;
4034         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4035
4036         /* Set up how to generate a link change interrupt. */
4037         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4038
4039         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4040                (u64) bp->status_blk_mapping & 0xffffffff);
4041         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4042
4043         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4044                (u64) bp->stats_blk_mapping & 0xffffffff);
4045         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4046                (u64) bp->stats_blk_mapping >> 32);
4047
4048         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4049                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4050
4051         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4052                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4053
4054         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4055                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4056
4057         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4058
4059         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4060
4061         REG_WR(bp, BNX2_HC_COM_TICKS,
4062                (bp->com_ticks_int << 16) | bp->com_ticks);
4063
4064         REG_WR(bp, BNX2_HC_CMD_TICKS,
4065                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4066
4067         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4068                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4069         else
4070                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4071         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4072
4073         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4074                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4075         else {
4076                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4077                       BNX2_HC_CONFIG_COLLECT_STATS;
4078         }
4079
4080         if (bp->flags & ONE_SHOT_MSI_FLAG)
4081                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4082
4083         REG_WR(bp, BNX2_HC_CONFIG, val);
4084
4085         /* Clear internal stats counters. */
4086         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4087
4088         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4089
4090         /* Initialize the receive filter. */
4091         bnx2_set_rx_mode(bp->dev);
4092
4093         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4094                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4095                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4096                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4097         }
4098         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4099                           0);
4100
4101         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4102         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4103
4104         udelay(20);
4105
4106         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4107
4108         return rc;
4109 }
4110
4111 static void
4112 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4113 {
4114         u32 val, offset0, offset1, offset2, offset3;
4115
4116         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4117                 offset0 = BNX2_L2CTX_TYPE_XI;
4118                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4119                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4120                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4121         } else {
4122                 offset0 = BNX2_L2CTX_TYPE;
4123                 offset1 = BNX2_L2CTX_CMD_TYPE;
4124                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4125                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4126         }
4127         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4128         CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
4129
4130         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4131         CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
4132
4133         val = (u64) bp->tx_desc_mapping >> 32;
4134         CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
4135
4136         val = (u64) bp->tx_desc_mapping & 0xffffffff;
4137         CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
4138 }
4139
4140 static void
4141 bnx2_init_tx_ring(struct bnx2 *bp)
4142 {
4143         struct tx_bd *txbd;
4144         u32 cid;
4145
4146         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4147
4148         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4149
4150         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4151         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4152
4153         bp->tx_prod = 0;
4154         bp->tx_cons = 0;
4155         bp->hw_tx_cons = 0;
4156         bp->tx_prod_bseq = 0;
4157
4158         cid = TX_CID;
4159         bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4160         bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4161
4162         bnx2_init_tx_context(bp, cid);
4163 }
4164
4165 static void
4166 bnx2_init_rx_ring(struct bnx2 *bp)
4167 {
4168         struct rx_bd *rxbd;
4169         int i;
4170         u16 prod, ring_prod;
4171         u32 val;
4172
4173         /* 8 for CRC and VLAN */
4174         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4175         /* hw alignment */
4176         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4177
4178         ring_prod = prod = bp->rx_prod = 0;
4179         bp->rx_cons = 0;
4180         bp->hw_rx_cons = 0;
4181         bp->rx_prod_bseq = 0;
4182
4183         for (i = 0; i < bp->rx_max_ring; i++) {
4184                 int j;
4185
4186                 rxbd = &bp->rx_desc_ring[i][0];
4187                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4188                         rxbd->rx_bd_len = bp->rx_buf_use_size;
4189                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4190                 }
4191                 if (i == (bp->rx_max_ring - 1))
4192                         j = 0;
4193                 else
4194                         j = i + 1;
4195                 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
4196                 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
4197                                        0xffffffff;
4198         }
4199
4200         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
4201         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
4202         val |= 0x02 << 8;
4203         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
4204
4205         val = (u64) bp->rx_desc_mapping[0] >> 32;
4206         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
4207
4208         val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4209         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
4210
4211         for (i = 0; i < bp->rx_ring_size; i++) {
4212                 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
4213                         break;
4214                 }
4215                 prod = NEXT_RX_BD(prod);
4216                 ring_prod = RX_RING_IDX(prod);
4217         }
4218         bp->rx_prod = prod;
4219
4220         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4221
4222         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
4223 }
4224
4225 static void
4226 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4227 {
4228         u32 num_rings, max;
4229
4230         bp->rx_ring_size = size;
4231         num_rings = 1;
4232         while (size > MAX_RX_DESC_CNT) {
4233                 size -= MAX_RX_DESC_CNT;
4234                 num_rings++;
4235         }
4236         /* round to next power of 2 */
4237         max = MAX_RX_RINGS;
4238         while ((max & num_rings) == 0)
4239                 max >>= 1;
4240
4241         if (num_rings != max)
4242                 max <<= 1;
4243
4244         bp->rx_max_ring = max;
4245         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4246 }
4247
4248 static void
4249 bnx2_free_tx_skbs(struct bnx2 *bp)
4250 {
4251         int i;
4252
4253         if (bp->tx_buf_ring == NULL)
4254                 return;
4255
4256         for (i = 0; i < TX_DESC_CNT; ) {
4257                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4258                 struct sk_buff *skb = tx_buf->skb;
4259                 int j, last;
4260
4261                 if (skb == NULL) {
4262                         i++;
4263                         continue;
4264                 }
4265
4266                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4267                         skb_headlen(skb), PCI_DMA_TODEVICE);
4268
4269                 tx_buf->skb = NULL;
4270
4271                 last = skb_shinfo(skb)->nr_frags;
4272                 for (j = 0; j < last; j++) {
4273                         tx_buf = &bp->tx_buf_ring[i + j + 1];
4274                         pci_unmap_page(bp->pdev,
4275                                 pci_unmap_addr(tx_buf, mapping),
4276                                 skb_shinfo(skb)->frags[j].size,
4277                                 PCI_DMA_TODEVICE);
4278                 }
4279                 dev_kfree_skb(skb);
4280                 i += j + 1;
4281         }
4282
4283 }
4284
4285 static void
4286 bnx2_free_rx_skbs(struct bnx2 *bp)
4287 {
4288         int i;
4289
4290         if (bp->rx_buf_ring == NULL)
4291                 return;
4292
4293         for (i = 0; i < bp->rx_max_ring_idx; i++) {
4294                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4295                 struct sk_buff *skb = rx_buf->skb;
4296
4297                 if (skb == NULL)
4298                         continue;
4299
4300                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4301                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4302
4303                 rx_buf->skb = NULL;
4304
4305                 dev_kfree_skb(skb);
4306         }
4307 }
4308
4309 static void
4310 bnx2_free_skbs(struct bnx2 *bp)
4311 {
4312         bnx2_free_tx_skbs(bp);
4313         bnx2_free_rx_skbs(bp);
4314 }
4315
4316 static int
4317 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4318 {
4319         int rc;
4320
4321         rc = bnx2_reset_chip(bp, reset_code);
4322         bnx2_free_skbs(bp);
4323         if (rc)
4324                 return rc;
4325
4326         if ((rc = bnx2_init_chip(bp)) != 0)
4327                 return rc;
4328
4329         bnx2_init_tx_ring(bp);
4330         bnx2_init_rx_ring(bp);
4331         return 0;
4332 }
4333
4334 static int
4335 bnx2_init_nic(struct bnx2 *bp)
4336 {
4337         int rc;
4338
4339         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4340                 return rc;
4341
4342         spin_lock_bh(&bp->phy_lock);
4343         bnx2_init_phy(bp);
4344         bnx2_set_link(bp);
4345         spin_unlock_bh(&bp->phy_lock);
4346         return 0;
4347 }
4348
4349 static int
4350 bnx2_test_registers(struct bnx2 *bp)
4351 {
4352         int ret;
4353         int i, is_5709;
4354         static const struct {
4355                 u16   offset;
4356                 u16   flags;
4357 #define BNX2_FL_NOT_5709        1
4358                 u32   rw_mask;
4359                 u32   ro_mask;
4360         } reg_tbl[] = {
4361                 { 0x006c, 0, 0x00000000, 0x0000003f },
4362                 { 0x0090, 0, 0xffffffff, 0x00000000 },
4363                 { 0x0094, 0, 0x00000000, 0x00000000 },
4364
4365                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4366                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4367                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4368                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4369                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4370                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4371                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4372                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4373                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4374
4375                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4376                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4377                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4378                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4379                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4380                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4381
4382                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4383                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4384                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
4385
4386                 { 0x1000, 0, 0x00000000, 0x00000001 },
4387                 { 0x1004, 0, 0x00000000, 0x000f0001 },
4388
4389                 { 0x1408, 0, 0x01c00800, 0x00000000 },
4390                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4391                 { 0x14a8, 0, 0x00000000, 0x000001ff },
4392                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4393                 { 0x14b0, 0, 0x00000002, 0x00000001 },
4394                 { 0x14b8, 0, 0x00000000, 0x00000000 },
4395                 { 0x14c0, 0, 0x00000000, 0x00000009 },
4396                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4397                 { 0x14cc, 0, 0x00000000, 0x00000001 },
4398                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4399
4400                 { 0x1800, 0, 0x00000000, 0x00000001 },
4401                 { 0x1804, 0, 0x00000000, 0x00000003 },
4402
4403                 { 0x2800, 0, 0x00000000, 0x00000001 },
4404                 { 0x2804, 0, 0x00000000, 0x00003f01 },
4405                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4406                 { 0x2810, 0, 0xffff0000, 0x00000000 },
4407                 { 0x2814, 0, 0xffff0000, 0x00000000 },
4408                 { 0x2818, 0, 0xffff0000, 0x00000000 },
4409                 { 0x281c, 0, 0xffff0000, 0x00000000 },
4410                 { 0x2834, 0, 0xffffffff, 0x00000000 },
4411                 { 0x2840, 0, 0x00000000, 0xffffffff },
4412                 { 0x2844, 0, 0x00000000, 0xffffffff },
4413                 { 0x2848, 0, 0xffffffff, 0x00000000 },
4414                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4415
4416                 { 0x2c00, 0, 0x00000000, 0x00000011 },
4417                 { 0x2c04, 0, 0x00000000, 0x00030007 },
4418
4419                 { 0x3c00, 0, 0x00000000, 0x00000001 },
4420                 { 0x3c04, 0, 0x00000000, 0x00070000 },
4421                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4422                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4423                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4424                 { 0x3c14, 0, 0x00000000, 0xffffffff },
4425                 { 0x3c18, 0, 0x00000000, 0xffffffff },
4426                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4427                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4428
4429                 { 0x5004, 0, 0x00000000, 0x0000007f },
4430                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4431
4432                 { 0x5c00, 0, 0x00000000, 0x00000001 },
4433                 { 0x5c04, 0, 0x00000000, 0x0003000f },
4434                 { 0x5c08, 0, 0x00000003, 0x00000000 },
4435                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4436                 { 0x5c10, 0, 0x00000000, 0xffffffff },
4437                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4438                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4439                 { 0x5c88, 0, 0x00000000, 0x00077373 },
4440                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4441
4442                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4443                 { 0x680c, 0, 0xffffffff, 0x00000000 },
4444                 { 0x6810, 0, 0xffffffff, 0x00000000 },
4445                 { 0x6814, 0, 0xffffffff, 0x00000000 },
4446                 { 0x6818, 0, 0xffffffff, 0x00000000 },
4447                 { 0x681c, 0, 0xffffffff, 0x00000000 },
4448                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4449                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4450                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4451                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4452                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4453                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4454                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4455                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4456                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4457                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4458                 { 0x684c, 0, 0xffffffff, 0x00000000 },
4459                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4460                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4461                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4462                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4463                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4464                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4465
4466                 { 0xffff, 0, 0x00000000, 0x00000000 },
4467         };
4468
4469         ret = 0;
4470         is_5709 = 0;
4471         if (CHIP_NUM(bp) == CHIP_NUM_5709)
4472                 is_5709 = 1;
4473
4474         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
4475                 u32 offset, rw_mask, ro_mask, save_val, val;
4476                 u16 flags = reg_tbl[i].flags;
4477
4478                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
4479                         continue;
4480
4481                 offset = (u32) reg_tbl[i].offset;
4482                 rw_mask = reg_tbl[i].rw_mask;
4483                 ro_mask = reg_tbl[i].ro_mask;
4484
4485                 save_val = readl(bp->regview + offset);
4486
4487                 writel(0, bp->regview + offset);
4488
4489                 val = readl(bp->regview + offset);
4490                 if ((val & rw_mask) != 0) {
4491                         goto reg_test_err;
4492                 }
4493
4494                 if ((val & ro_mask) != (save_val & ro_mask)) {
4495                         goto reg_test_err;
4496                 }
4497
4498                 writel(0xffffffff, bp->regview + offset);
4499
4500                 val = readl(bp->regview + offset);
4501                 if ((val & rw_mask) != rw_mask) {
4502                         goto reg_test_err;
4503                 }
4504
4505                 if ((val & ro_mask) != (save_val & ro_mask)) {
4506                         goto reg_test_err;
4507                 }
4508
4509                 writel(save_val, bp->regview + offset);
4510                 continue;
4511
4512 reg_test_err:
4513                 writel(save_val, bp->regview + offset);
4514                 ret = -ENODEV;
4515                 break;
4516         }
4517         return ret;
4518 }
4519
4520 static int
4521 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
4522 {
4523         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
4524                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
4525         int i;
4526
4527         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
4528                 u32 offset;
4529
4530                 for (offset = 0; offset < size; offset += 4) {
4531
4532                         REG_WR_IND(bp, start + offset, test_pattern[i]);
4533
4534                         if (REG_RD_IND(bp, start + offset) !=
4535                                 test_pattern[i]) {
4536                                 return -ENODEV;
4537                         }
4538                 }
4539         }
4540         return 0;
4541 }
4542
4543 static int
4544 bnx2_test_memory(struct bnx2 *bp)
4545 {
4546         int ret = 0;
4547         int i;
4548         static struct mem_entry {
4549                 u32   offset;
4550                 u32   len;
4551         } mem_tbl_5706[] = {
4552                 { 0x60000,  0x4000 },
4553                 { 0xa0000,  0x3000 },
4554                 { 0xe0000,  0x4000 },
4555                 { 0x120000, 0x4000 },
4556                 { 0x1a0000, 0x4000 },
4557                 { 0x160000, 0x4000 },
4558                 { 0xffffffff, 0    },
4559         },
4560         mem_tbl_5709[] = {
4561                 { 0x60000,  0x4000 },
4562                 { 0xa0000,  0x3000 },
4563                 { 0xe0000,  0x4000 },
4564                 { 0x120000, 0x4000 },
4565                 { 0x1a0000, 0x4000 },
4566                 { 0xffffffff, 0    },
4567         };
4568         struct mem_entry *mem_tbl;
4569
4570         if (CHIP_NUM(bp) == CHIP_NUM_5709)
4571                 mem_tbl = mem_tbl_5709;
4572         else
4573                 mem_tbl = mem_tbl_5706;
4574
4575         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
4576                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
4577                         mem_tbl[i].len)) != 0) {
4578                         return ret;
4579                 }
4580         }
4581
4582         return ret;
4583 }
4584
4585 #define BNX2_MAC_LOOPBACK       0
4586 #define BNX2_PHY_LOOPBACK       1
4587
4588 static int
4589 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
4590 {
4591         unsigned int pkt_size, num_pkts, i;
4592         struct sk_buff *skb, *rx_skb;
4593         unsigned char *packet;
4594         u16 rx_start_idx, rx_idx;
4595         dma_addr_t map;
4596         struct tx_bd *txbd;
4597         struct sw_bd *rx_buf;
4598         struct l2_fhdr *rx_hdr;
4599         int ret = -ENODEV;
4600
4601         if (loopback_mode == BNX2_MAC_LOOPBACK) {
4602                 bp->loopback = MAC_LOOPBACK;
4603                 bnx2_set_mac_loopback(bp);
4604         }
4605         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
4606                 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4607                         return 0;
4608
4609                 bp->loopback = PHY_LOOPBACK;
4610                 bnx2_set_phy_loopback(bp);
4611         }
4612         else
4613                 return -EINVAL;
4614
4615         pkt_size = 1514;
4616         skb = netdev_alloc_skb(bp->dev, pkt_size);
4617         if (!skb)
4618                 return -ENOMEM;
4619         packet = skb_put(skb, pkt_size);
4620         memcpy(packet, bp->dev->dev_addr, 6);
4621         memset(packet + 6, 0x0, 8);
4622         for (i = 14; i < pkt_size; i++)
4623                 packet[i] = (unsigned char) (i & 0xff);
4624
4625         map = pci_map_single(bp->pdev, skb->data, pkt_size,
4626                 PCI_DMA_TODEVICE);
4627
4628         REG_WR(bp, BNX2_HC_COMMAND,
4629                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4630
4631         REG_RD(bp, BNX2_HC_COMMAND);
4632
4633         udelay(5);
4634         rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
4635
4636         num_pkts = 0;
4637
4638         txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
4639
4640         txbd->tx_bd_haddr_hi = (u64) map >> 32;
4641         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
4642         txbd->tx_bd_mss_nbytes = pkt_size;
4643         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
4644
4645         num_pkts++;
4646         bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
4647         bp->tx_prod_bseq += pkt_size;
4648
4649         REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
4650         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4651
4652         udelay(100);
4653
4654         REG_WR(bp, BNX2_HC_COMMAND,
4655                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4656
4657         REG_RD(bp, BNX2_HC_COMMAND);
4658
4659         udelay(5);
4660
4661         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4662         dev_kfree_skb(skb);
4663
4664         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4665                 goto loopback_test_done;
4666         }
4667
4668         rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4669         if (rx_idx != rx_start_idx + num_pkts) {
4670                 goto loopback_test_done;
4671         }
4672
4673         rx_buf = &bp->rx_buf_ring[rx_start_idx];
4674         rx_skb = rx_buf->skb;
4675
4676         rx_hdr = (struct l2_fhdr *) rx_skb->data;
4677         skb_reserve(rx_skb, bp->rx_offset);
4678
4679         pci_dma_sync_single_for_cpu(bp->pdev,
4680                 pci_unmap_addr(rx_buf, mapping),
4681                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4682
4683         if (rx_hdr->l2_fhdr_status &
4684                 (L2_FHDR_ERRORS_BAD_CRC |
4685                 L2_FHDR_ERRORS_PHY_DECODE |
4686                 L2_FHDR_ERRORS_ALIGNMENT |
4687                 L2_FHDR_ERRORS_TOO_SHORT |
4688                 L2_FHDR_ERRORS_GIANT_FRAME)) {
4689
4690                 goto loopback_test_done;
4691         }
4692
4693         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4694                 goto loopback_test_done;
4695         }
4696
4697         for (i = 14; i < pkt_size; i++) {
4698                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4699                         goto loopback_test_done;
4700                 }
4701         }
4702
4703         ret = 0;
4704
4705 loopback_test_done:
4706         bp->loopback = 0;
4707         return ret;
4708 }
4709
4710 #define BNX2_MAC_LOOPBACK_FAILED        1
4711 #define BNX2_PHY_LOOPBACK_FAILED        2
4712 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
4713                                          BNX2_PHY_LOOPBACK_FAILED)
4714
4715 static int
4716 bnx2_test_loopback(struct bnx2 *bp)
4717 {
4718         int rc = 0;
4719
4720         if (!netif_running(bp->dev))
4721                 return BNX2_LOOPBACK_FAILED;
4722
4723         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4724         spin_lock_bh(&bp->phy_lock);
4725         bnx2_init_phy(bp);
4726         spin_unlock_bh(&bp->phy_lock);
4727         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4728                 rc |= BNX2_MAC_LOOPBACK_FAILED;
4729         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4730                 rc |= BNX2_PHY_LOOPBACK_FAILED;
4731         return rc;
4732 }
4733
4734 #define NVRAM_SIZE 0x200
4735 #define CRC32_RESIDUAL 0xdebb20e3
4736
4737 static int
4738 bnx2_test_nvram(struct bnx2 *bp)
4739 {
4740         u32 buf[NVRAM_SIZE / 4];
4741         u8 *data = (u8 *) buf;
4742         int rc = 0;
4743         u32 magic, csum;
4744
4745         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4746                 goto test_nvram_done;
4747
4748         magic = be32_to_cpu(buf[0]);
4749         if (magic != 0x669955aa) {
4750                 rc = -ENODEV;
4751                 goto test_nvram_done;
4752         }
4753
4754         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4755                 goto test_nvram_done;
4756
4757         csum = ether_crc_le(0x100, data);
4758         if (csum != CRC32_RESIDUAL) {
4759                 rc = -ENODEV;
4760                 goto test_nvram_done;
4761         }
4762
4763         csum = ether_crc_le(0x100, data + 0x100);
4764         if (csum != CRC32_RESIDUAL) {
4765                 rc = -ENODEV;
4766         }
4767
4768 test_nvram_done:
4769         return rc;
4770 }
4771
4772 static int
4773 bnx2_test_link(struct bnx2 *bp)
4774 {
4775         u32 bmsr;
4776
4777         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
4778                 if (bp->link_up)
4779                         return 0;
4780                 return -ENODEV;
4781         }
4782         spin_lock_bh(&bp->phy_lock);
4783         bnx2_enable_bmsr1(bp);
4784         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4785         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4786         bnx2_disable_bmsr1(bp);
4787         spin_unlock_bh(&bp->phy_lock);
4788
4789         if (bmsr & BMSR_LSTATUS) {
4790                 return 0;
4791         }
4792         return -ENODEV;
4793 }
4794
4795 static int
4796 bnx2_test_intr(struct bnx2 *bp)
4797 {
4798         int i;
4799         u16 status_idx;
4800
4801         if (!netif_running(bp->dev))
4802                 return -ENODEV;
4803
4804         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4805
4806         /* This register is not touched during run-time. */
4807         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
4808         REG_RD(bp, BNX2_HC_COMMAND);
4809
4810         for (i = 0; i < 10; i++) {
4811                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4812                         status_idx) {
4813
4814                         break;
4815                 }
4816
4817                 msleep_interruptible(10);
4818         }
4819         if (i < 10)
4820                 return 0;
4821
4822         return -ENODEV;
4823 }
4824
4825 static void
4826 bnx2_5706_serdes_timer(struct bnx2 *bp)
4827 {
4828         spin_lock(&bp->phy_lock);
4829         if (bp->serdes_an_pending)
4830                 bp->serdes_an_pending--;
4831         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4832                 u32 bmcr;
4833
4834                 bp->current_interval = bp->timer_interval;
4835
4836                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4837
4838                 if (bmcr & BMCR_ANENABLE) {
4839                         u32 phy1, phy2;
4840
4841                         bnx2_write_phy(bp, 0x1c, 0x7c00);
4842                         bnx2_read_phy(bp, 0x1c, &phy1);
4843
4844                         bnx2_write_phy(bp, 0x17, 0x0f01);
4845                         bnx2_read_phy(bp, 0x15, &phy2);
4846                         bnx2_write_phy(bp, 0x17, 0x0f01);
4847                         bnx2_read_phy(bp, 0x15, &phy2);
4848
4849                         if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
4850                                 !(phy2 & 0x20)) {       /* no CONFIG */
4851
4852                                 bmcr &= ~BMCR_ANENABLE;
4853                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4854                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4855                                 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
4856                         }
4857                 }
4858         }
4859         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4860                  (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4861                 u32 phy2;
4862
4863                 bnx2_write_phy(bp, 0x17, 0x0f01);
4864                 bnx2_read_phy(bp, 0x15, &phy2);
4865                 if (phy2 & 0x20) {
4866                         u32 bmcr;
4867
4868                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4869                         bmcr |= BMCR_ANENABLE;
4870                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4871
4872                         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4873                 }
4874         } else
4875                 bp->current_interval = bp->timer_interval;
4876
4877         spin_unlock(&bp->phy_lock);
4878 }
4879
4880 static void
4881 bnx2_5708_serdes_timer(struct bnx2 *bp)
4882 {
4883         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4884                 return;
4885
4886         if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
4887                 bp->serdes_an_pending = 0;
4888                 return;
4889         }
4890
4891         spin_lock(&bp->phy_lock);
4892         if (bp->serdes_an_pending)
4893                 bp->serdes_an_pending--;
4894         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4895                 u32 bmcr;
4896
4897                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4898                 if (bmcr & BMCR_ANENABLE) {
4899                         bnx2_enable_forced_2g5(bp);
4900                         bp->current_interval = SERDES_FORCED_TIMEOUT;
4901                 } else {
4902                         bnx2_disable_forced_2g5(bp);
4903                         bp->serdes_an_pending = 2;
4904                         bp->current_interval = bp->timer_interval;
4905                 }
4906
4907         } else
4908                 bp->current_interval = bp->timer_interval;
4909
4910         spin_unlock(&bp->phy_lock);
4911 }
4912
4913 static void
4914 bnx2_timer(unsigned long data)
4915 {
4916         struct bnx2 *bp = (struct bnx2 *) data;
4917
4918         if (!netif_running(bp->dev))
4919                 return;
4920
4921         if (atomic_read(&bp->intr_sem) != 0)
4922                 goto bnx2_restart_timer;
4923
4924         bnx2_send_heart_beat(bp);
4925
4926         bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4927
4928         /* workaround occasional corrupted counters */
4929         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
4930                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
4931                                             BNX2_HC_COMMAND_STATS_NOW);
4932
4933         if (bp->phy_flags & PHY_SERDES_FLAG) {
4934                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4935                         bnx2_5706_serdes_timer(bp);
4936                 else
4937                         bnx2_5708_serdes_timer(bp);
4938         }
4939
4940 bnx2_restart_timer:
4941         mod_timer(&bp->timer, jiffies + bp->current_interval);
4942 }
4943
4944 static int
4945 bnx2_request_irq(struct bnx2 *bp)
4946 {
4947         struct net_device *dev = bp->dev;
4948         int rc = 0;
4949
4950         if (bp->flags & USING_MSI_FLAG) {
4951                 irq_handler_t   fn = bnx2_msi;
4952
4953                 if (bp->flags & ONE_SHOT_MSI_FLAG)
4954                         fn = bnx2_msi_1shot;
4955
4956                 rc = request_irq(bp->pdev->irq, fn, 0, dev->name, dev);
4957         } else
4958                 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4959                                  IRQF_SHARED, dev->name, dev);
4960         return rc;
4961 }
4962
4963 static void
4964 bnx2_free_irq(struct bnx2 *bp)
4965 {
4966         struct net_device *dev = bp->dev;
4967
4968         if (bp->flags & USING_MSI_FLAG) {
4969                 free_irq(bp->pdev->irq, dev);
4970                 pci_disable_msi(bp->pdev);
4971                 bp->flags &= ~(USING_MSI_FLAG | ONE_SHOT_MSI_FLAG);
4972         } else
4973                 free_irq(bp->pdev->irq, dev);
4974 }
4975
4976 /* Called with rtnl_lock */
4977 static int
4978 bnx2_open(struct net_device *dev)
4979 {
4980         struct bnx2 *bp = netdev_priv(dev);
4981         int rc;
4982
4983         netif_carrier_off(dev);
4984
4985         bnx2_set_power_state(bp, PCI_D0);
4986         bnx2_disable_int(bp);
4987
4988         rc = bnx2_alloc_mem(bp);
4989         if (rc)
4990                 return rc;
4991
4992         napi_enable(&bp->napi);
4993
4994         if ((bp->flags & MSI_CAP_FLAG) && !disable_msi) {
4995                 if (pci_enable_msi(bp->pdev) == 0) {
4996                         bp->flags |= USING_MSI_FLAG;
4997                         if (CHIP_NUM(bp) == CHIP_NUM_5709)
4998                                 bp->flags |= ONE_SHOT_MSI_FLAG;
4999                 }
5000         }
5001         rc = bnx2_request_irq(bp);
5002
5003         if (rc) {
5004                 napi_disable(&bp->napi);
5005                 bnx2_free_mem(bp);
5006                 return rc;
5007         }
5008
5009         rc = bnx2_init_nic(bp);
5010
5011         if (rc) {
5012                 napi_disable(&bp->napi);
5013                 bnx2_free_irq(bp);
5014                 bnx2_free_skbs(bp);
5015                 bnx2_free_mem(bp);
5016                 return rc;
5017         }
5018
5019         mod_timer(&bp->timer, jiffies + bp->current_interval);
5020
5021         atomic_set(&bp->intr_sem, 0);
5022
5023         bnx2_enable_int(bp);
5024
5025         if (bp->flags & USING_MSI_FLAG) {
5026                 /* Test MSI to make sure it is working
5027                  * If MSI test fails, go back to INTx mode
5028                  */
5029                 if (bnx2_test_intr(bp) != 0) {
5030                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5031                                " using MSI, switching to INTx mode. Please"
5032                                " report this failure to the PCI maintainer"
5033                                " and include system chipset information.\n",
5034                                bp->dev->name);
5035
5036                         bnx2_disable_int(bp);
5037                         bnx2_free_irq(bp);
5038
5039                         rc = bnx2_init_nic(bp);
5040
5041                         if (!rc)
5042                                 rc = bnx2_request_irq(bp);
5043
5044                         if (rc) {
5045                                 napi_disable(&bp->napi);
5046                                 bnx2_free_skbs(bp);
5047                                 bnx2_free_mem(bp);
5048                                 del_timer_sync(&bp->timer);
5049                                 return rc;
5050                         }
5051                         bnx2_enable_int(bp);
5052                 }
5053         }
5054         if (bp->flags & USING_MSI_FLAG) {
5055                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5056         }
5057
5058         netif_start_queue(dev);
5059
5060         return 0;
5061 }
5062
5063 static void
5064 bnx2_reset_task(struct work_struct *work)
5065 {
5066         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5067
5068         if (!netif_running(bp->dev))
5069                 return;
5070
5071         bp->in_reset_task = 1;
5072         bnx2_netif_stop(bp);
5073
5074         bnx2_init_nic(bp);
5075
5076         atomic_set(&bp->intr_sem, 1);
5077         bnx2_netif_start(bp);
5078         bp->in_reset_task = 0;
5079 }
5080
5081 static void
5082 bnx2_tx_timeout(struct net_device *dev)
5083 {
5084         struct bnx2 *bp = netdev_priv(dev);
5085
5086         /* This allows the netif to be shutdown gracefully before resetting */
5087         schedule_work(&bp->reset_task);
5088 }
5089
5090 #ifdef BCM_VLAN
5091 /* Called with rtnl_lock */
5092 static void
5093 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5094 {
5095         struct bnx2 *bp = netdev_priv(dev);
5096
5097         bnx2_netif_stop(bp);
5098
5099         bp->vlgrp = vlgrp;
5100         bnx2_set_rx_mode(dev);
5101
5102         bnx2_netif_start(bp);
5103 }
5104 #endif
5105
5106 /* Called with netif_tx_lock.
5107  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5108  * netif_wake_queue().
5109  */
5110 static int
5111 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5112 {
5113         struct bnx2 *bp = netdev_priv(dev);
5114         dma_addr_t mapping;
5115         struct tx_bd *txbd;
5116         struct sw_bd *tx_buf;
5117         u32 len, vlan_tag_flags, last_frag, mss;
5118         u16 prod, ring_prod;
5119         int i;
5120
5121         if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
5122                 netif_stop_queue(dev);
5123                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5124                         dev->name);
5125
5126                 return NETDEV_TX_BUSY;
5127         }
5128         len = skb_headlen(skb);
5129         prod = bp->tx_prod;
5130         ring_prod = TX_RING_IDX(prod);
5131
5132         vlan_tag_flags = 0;
5133         if (skb->ip_summed == CHECKSUM_PARTIAL) {
5134                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5135         }
5136
5137         if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
5138                 vlan_tag_flags |=
5139                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5140         }
5141         if ((mss = skb_shinfo(skb)->gso_size)) {
5142                 u32 tcp_opt_len, ip_tcp_len;
5143                 struct iphdr *iph;
5144
5145                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5146
5147                 tcp_opt_len = tcp_optlen(skb);
5148
5149                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5150                         u32 tcp_off = skb_transport_offset(skb) -
5151                                       sizeof(struct ipv6hdr) - ETH_HLEN;
5152
5153                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5154                                           TX_BD_FLAGS_SW_FLAGS;
5155                         if (likely(tcp_off == 0))
5156                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5157                         else {
5158                                 tcp_off >>= 3;
5159                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
5160                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
5161                                                   ((tcp_off & 0x10) <<
5162                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
5163                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5164                         }
5165                 } else {
5166                         if (skb_header_cloned(skb) &&
5167                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5168                                 dev_kfree_skb(skb);
5169                                 return NETDEV_TX_OK;
5170                         }
5171
5172                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5173
5174                         iph = ip_hdr(skb);
5175                         iph->check = 0;
5176                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5177                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5178                                                                  iph->daddr, 0,
5179                                                                  IPPROTO_TCP,
5180                                                                  0);
5181                         if (tcp_opt_len || (iph->ihl > 5)) {
5182                                 vlan_tag_flags |= ((iph->ihl - 5) +
5183                                                    (tcp_opt_len >> 2)) << 8;
5184                         }
5185                 }
5186         } else
5187                 mss = 0;
5188
5189         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5190
5191         tx_buf = &bp->tx_buf_ring[ring_prod];
5192         tx_buf->skb = skb;
5193         pci_unmap_addr_set(tx_buf, mapping, mapping);
5194
5195         txbd = &bp->tx_desc_ring[ring_prod];
5196
5197         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5198         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5199         txbd->tx_bd_mss_nbytes = len | (mss << 16);
5200         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5201
5202         last_frag = skb_shinfo(skb)->nr_frags;
5203
5204         for (i = 0; i < last_frag; i++) {
5205                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5206
5207                 prod = NEXT_TX_BD(prod);
5208                 ring_prod = TX_RING_IDX(prod);
5209                 txbd = &bp->tx_desc_ring[ring_prod];
5210
5211                 len = frag->size;
5212                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5213                         len, PCI_DMA_TODEVICE);
5214                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5215                                 mapping, mapping);
5216
5217                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5218                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5219                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5220                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5221
5222         }
5223         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5224
5225         prod = NEXT_TX_BD(prod);
5226         bp->tx_prod_bseq += skb->len;
5227
5228         REG_WR16(bp, bp->tx_bidx_addr, prod);
5229         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5230
5231         mmiowb();
5232
5233         bp->tx_prod = prod;
5234         dev->trans_start = jiffies;
5235
5236         if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
5237                 netif_stop_queue(dev);
5238                 if (bnx2_tx_avail(bp) > bp->tx_wake_thresh)
5239                         netif_wake_queue(dev);
5240         }
5241
5242         return NETDEV_TX_OK;
5243 }
5244
5245 /* Called with rtnl_lock */
5246 static int
5247 bnx2_close(struct net_device *dev)
5248 {
5249         struct bnx2 *bp = netdev_priv(dev);
5250         u32 reset_code;
5251
5252         /* Calling flush_scheduled_work() may deadlock because
5253          * linkwatch_event() may be on the workqueue and it will try to get
5254          * the rtnl_lock which we are holding.
5255          */
5256         while (bp->in_reset_task)
5257                 msleep(1);
5258
5259         bnx2_disable_int_sync(bp);
5260         napi_disable(&bp->napi);
5261         del_timer_sync(&bp->timer);
5262         if (bp->flags & NO_WOL_FLAG)
5263                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5264         else if (bp->wol)
5265                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5266         else
5267                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5268         bnx2_reset_chip(bp, reset_code);
5269         bnx2_free_irq(bp);
5270         bnx2_free_skbs(bp);
5271         bnx2_free_mem(bp);
5272         bp->link_up = 0;
5273         netif_carrier_off(bp->dev);
5274         bnx2_set_power_state(bp, PCI_D3hot);
5275         return 0;
5276 }
5277
5278 #define GET_NET_STATS64(ctr)                                    \
5279         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
5280         (unsigned long) (ctr##_lo)
5281
5282 #define GET_NET_STATS32(ctr)            \
5283         (ctr##_lo)
5284
5285 #if (BITS_PER_LONG == 64)
5286 #define GET_NET_STATS   GET_NET_STATS64
5287 #else
5288 #define GET_NET_STATS   GET_NET_STATS32
5289 #endif
5290
5291 static struct net_device_stats *
5292 bnx2_get_stats(struct net_device *dev)
5293 {
5294         struct bnx2 *bp = netdev_priv(dev);
5295         struct statistics_block *stats_blk = bp->stats_blk;
5296         struct net_device_stats *net_stats = &bp->net_stats;
5297
5298         if (bp->stats_blk == NULL) {
5299                 return net_stats;
5300         }
5301         net_stats->rx_packets =
5302                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5303                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5304                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5305
5306         net_stats->tx_packets =
5307                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5308                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5309                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5310
5311         net_stats->rx_bytes =
5312                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5313
5314         net_stats->tx_bytes =
5315                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5316
5317         net_stats->multicast =
5318                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5319
5320         net_stats->collisions =
5321                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5322
5323         net_stats->rx_length_errors =
5324                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5325                 stats_blk->stat_EtherStatsOverrsizePkts);
5326
5327         net_stats->rx_over_errors =
5328                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5329
5330         net_stats->rx_frame_errors =
5331                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5332
5333         net_stats->rx_crc_errors =
5334                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5335
5336         net_stats->rx_errors = net_stats->rx_length_errors +
5337                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5338                 net_stats->rx_crc_errors;
5339
5340         net_stats->tx_aborted_errors =
5341                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5342                 stats_blk->stat_Dot3StatsLateCollisions);
5343
5344         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5345             (CHIP_ID(bp) == CHIP_ID_5708_A0))
5346                 net_stats->tx_carrier_errors = 0;
5347         else {
5348                 net_stats->tx_carrier_errors =
5349                         (unsigned long)
5350                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
5351         }
5352
5353         net_stats->tx_errors =
5354                 (unsigned long)
5355                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
5356                 +
5357                 net_stats->tx_aborted_errors +
5358                 net_stats->tx_carrier_errors;
5359
5360         net_stats->rx_missed_errors =
5361                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
5362                 stats_blk->stat_FwRxDrop);
5363
5364         return net_stats;
5365 }
5366
5367 /* All ethtool functions called with rtnl_lock */
5368
5369 static int
5370 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5371 {
5372         struct bnx2 *bp = netdev_priv(dev);
5373         int support_serdes = 0, support_copper = 0;
5374
5375         cmd->supported = SUPPORTED_Autoneg;
5376         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5377                 support_serdes = 1;
5378                 support_copper = 1;
5379         } else if (bp->phy_port == PORT_FIBRE)
5380                 support_serdes = 1;
5381         else
5382                 support_copper = 1;
5383
5384         if (support_serdes) {
5385                 cmd->supported |= SUPPORTED_1000baseT_Full |
5386                         SUPPORTED_FIBRE;
5387                 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
5388                         cmd->supported |= SUPPORTED_2500baseX_Full;
5389
5390         }
5391         if (support_copper) {
5392                 cmd->supported |= SUPPORTED_10baseT_Half |
5393                         SUPPORTED_10baseT_Full |
5394                         SUPPORTED_100baseT_Half |
5395                         SUPPORTED_100baseT_Full |
5396                         SUPPORTED_1000baseT_Full |
5397                         SUPPORTED_TP;
5398
5399         }
5400
5401         spin_lock_bh(&bp->phy_lock);
5402         cmd->port = bp->phy_port;
5403         cmd->advertising = bp->advertising;
5404
5405         if (bp->autoneg & AUTONEG_SPEED) {
5406                 cmd->autoneg = AUTONEG_ENABLE;
5407         }
5408         else {
5409                 cmd->autoneg = AUTONEG_DISABLE;
5410         }
5411
5412         if (netif_carrier_ok(dev)) {
5413                 cmd->speed = bp->line_speed;
5414                 cmd->duplex = bp->duplex;
5415         }
5416         else {
5417                 cmd->speed = -1;
5418                 cmd->duplex = -1;
5419         }
5420         spin_unlock_bh(&bp->phy_lock);
5421
5422         cmd->transceiver = XCVR_INTERNAL;
5423         cmd->phy_address = bp->phy_addr;
5424
5425         return 0;
5426 }
5427
5428 static int
5429 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5430 {
5431         struct bnx2 *bp = netdev_priv(dev);
5432         u8 autoneg = bp->autoneg;
5433         u8 req_duplex = bp->req_duplex;
5434         u16 req_line_speed = bp->req_line_speed;
5435         u32 advertising = bp->advertising;
5436         int err = -EINVAL;
5437
5438         spin_lock_bh(&bp->phy_lock);
5439
5440         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
5441                 goto err_out_unlock;
5442
5443         if (cmd->port != bp->phy_port && !(bp->phy_flags & REMOTE_PHY_CAP_FLAG))
5444                 goto err_out_unlock;
5445
5446         if (cmd->autoneg == AUTONEG_ENABLE) {
5447                 autoneg |= AUTONEG_SPEED;
5448
5449                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
5450
5451                 /* allow advertising 1 speed */
5452                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
5453                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
5454                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
5455                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
5456
5457                         if (cmd->port == PORT_FIBRE)
5458                                 goto err_out_unlock;
5459
5460                         advertising = cmd->advertising;
5461
5462                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
5463                         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ||
5464                             (cmd->port == PORT_TP))
5465                                 goto err_out_unlock;
5466                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
5467                         advertising = cmd->advertising;
5468                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
5469                         goto err_out_unlock;
5470                 else {
5471                         if (cmd->port == PORT_FIBRE)
5472                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
5473                         else
5474                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
5475                 }
5476                 advertising |= ADVERTISED_Autoneg;
5477         }
5478         else {
5479                 if (cmd->port == PORT_FIBRE) {
5480                         if ((cmd->speed != SPEED_1000 &&
5481                              cmd->speed != SPEED_2500) ||
5482                             (cmd->duplex != DUPLEX_FULL))
5483                                 goto err_out_unlock;
5484
5485                         if (cmd->speed == SPEED_2500 &&
5486                             !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
5487                                 goto err_out_unlock;
5488                 }
5489                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
5490                         goto err_out_unlock;
5491
5492                 autoneg &= ~AUTONEG_SPEED;
5493                 req_line_speed = cmd->speed;
5494                 req_duplex = cmd->duplex;
5495                 advertising = 0;
5496         }
5497
5498         bp->autoneg = autoneg;
5499         bp->advertising = advertising;
5500         bp->req_line_speed = req_line_speed;
5501         bp->req_duplex = req_duplex;
5502
5503         err = bnx2_setup_phy(bp, cmd->port);
5504
5505 err_out_unlock:
5506         spin_unlock_bh(&bp->phy_lock);
5507
5508         return err;
5509 }
5510
5511 static void
5512 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
5513 {
5514         struct bnx2 *bp = netdev_priv(dev);
5515
5516         strcpy(info->driver, DRV_MODULE_NAME);
5517         strcpy(info->version, DRV_MODULE_VERSION);
5518         strcpy(info->bus_info, pci_name(bp->pdev));
5519         strcpy(info->fw_version, bp->fw_version);
5520 }
5521
5522 #define BNX2_REGDUMP_LEN                (32 * 1024)
5523
5524 static int
5525 bnx2_get_regs_len(struct net_device *dev)
5526 {
5527         return BNX2_REGDUMP_LEN;
5528 }
5529
5530 static void
5531 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
5532 {
5533         u32 *p = _p, i, offset;
5534         u8 *orig_p = _p;
5535         struct bnx2 *bp = netdev_priv(dev);
5536         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
5537                                  0x0800, 0x0880, 0x0c00, 0x0c10,
5538                                  0x0c30, 0x0d08, 0x1000, 0x101c,
5539                                  0x1040, 0x1048, 0x1080, 0x10a4,
5540                                  0x1400, 0x1490, 0x1498, 0x14f0,
5541                                  0x1500, 0x155c, 0x1580, 0x15dc,
5542                                  0x1600, 0x1658, 0x1680, 0x16d8,
5543                                  0x1800, 0x1820, 0x1840, 0x1854,
5544                                  0x1880, 0x1894, 0x1900, 0x1984,
5545                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
5546                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
5547                                  0x2000, 0x2030, 0x23c0, 0x2400,
5548                                  0x2800, 0x2820, 0x2830, 0x2850,
5549                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
5550                                  0x3c00, 0x3c94, 0x4000, 0x4010,
5551                                  0x4080, 0x4090, 0x43c0, 0x4458,
5552                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
5553                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
5554                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
5555                                  0x5fc0, 0x6000, 0x6400, 0x6428,
5556                                  0x6800, 0x6848, 0x684c, 0x6860,
5557                                  0x6888, 0x6910, 0x8000 };
5558
5559         regs->version = 0;
5560
5561         memset(p, 0, BNX2_REGDUMP_LEN);
5562
5563         if (!netif_running(bp->dev))
5564                 return;
5565
5566         i = 0;
5567         offset = reg_boundaries[0];
5568         p += offset;
5569         while (offset < BNX2_REGDUMP_LEN) {
5570                 *p++ = REG_RD(bp, offset);
5571                 offset += 4;
5572                 if (offset == reg_boundaries[i + 1]) {
5573                         offset = reg_boundaries[i + 2];
5574                         p = (u32 *) (orig_p + offset);
5575                         i += 2;
5576                 }
5577         }
5578 }
5579
5580 static void
5581 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5582 {
5583         struct bnx2 *bp = netdev_priv(dev);
5584
5585         if (bp->flags & NO_WOL_FLAG) {
5586                 wol->supported = 0;
5587                 wol->wolopts = 0;
5588         }
5589         else {
5590                 wol->supported = WAKE_MAGIC;
5591                 if (bp->wol)
5592                         wol->wolopts = WAKE_MAGIC;
5593                 else
5594                         wol->wolopts = 0;
5595         }
5596         memset(&wol->sopass, 0, sizeof(wol->sopass));
5597 }
5598
5599 static int
5600 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5601 {
5602         struct bnx2 *bp = netdev_priv(dev);
5603
5604         if (wol->wolopts & ~WAKE_MAGIC)
5605                 return -EINVAL;
5606
5607         if (wol->wolopts & WAKE_MAGIC) {
5608                 if (bp->flags & NO_WOL_FLAG)
5609                         return -EINVAL;
5610
5611                 bp->wol = 1;
5612         }
5613         else {
5614                 bp->wol = 0;
5615         }
5616         return 0;
5617 }
5618
5619 static int
5620 bnx2_nway_reset(struct net_device *dev)
5621 {
5622         struct bnx2 *bp = netdev_priv(dev);
5623         u32 bmcr;
5624
5625         if (!(bp->autoneg & AUTONEG_SPEED)) {
5626                 return -EINVAL;
5627         }
5628
5629         spin_lock_bh(&bp->phy_lock);
5630
5631         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5632                 int rc;
5633
5634                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
5635                 spin_unlock_bh(&bp->phy_lock);
5636                 return rc;
5637         }
5638
5639         /* Force a link down visible on the other side */
5640         if (bp->phy_flags & PHY_SERDES_FLAG) {
5641                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
5642                 spin_unlock_bh(&bp->phy_lock);
5643
5644                 msleep(20);
5645
5646                 spin_lock_bh(&bp->phy_lock);
5647
5648                 bp->current_interval = SERDES_AN_TIMEOUT;
5649                 bp->serdes_an_pending = 1;
5650                 mod_timer(&bp->timer, jiffies + bp->current_interval);
5651         }
5652
5653         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5654         bmcr &= ~BMCR_LOOPBACK;
5655         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
5656
5657         spin_unlock_bh(&bp->phy_lock);
5658
5659         return 0;
5660 }
5661
5662 static int
5663 bnx2_get_eeprom_len(struct net_device *dev)
5664 {
5665         struct bnx2 *bp = netdev_priv(dev);
5666
5667         if (bp->flash_info == NULL)
5668                 return 0;
5669
5670         return (int) bp->flash_size;
5671 }
5672
5673 static int
5674 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5675                 u8 *eebuf)
5676 {
5677         struct bnx2 *bp = netdev_priv(dev);
5678         int rc;
5679
5680         /* parameters already validated in ethtool_get_eeprom */
5681
5682         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
5683
5684         return rc;
5685 }
5686
5687 static int
5688 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5689                 u8 *eebuf)
5690 {
5691         struct bnx2 *bp = netdev_priv(dev);
5692         int rc;
5693
5694         /* parameters already validated in ethtool_set_eeprom */
5695
5696         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
5697
5698         return rc;
5699 }
5700
5701 static int
5702 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5703 {
5704         struct bnx2 *bp = netdev_priv(dev);
5705
5706         memset(coal, 0, sizeof(struct ethtool_coalesce));
5707
5708         coal->rx_coalesce_usecs = bp->rx_ticks;
5709         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
5710         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
5711         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
5712
5713         coal->tx_coalesce_usecs = bp->tx_ticks;
5714         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
5715         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
5716         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
5717
5718         coal->stats_block_coalesce_usecs = bp->stats_ticks;
5719
5720         return 0;
5721 }
5722
5723 static int
5724 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5725 {
5726         struct bnx2 *bp = netdev_priv(dev);
5727
5728         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
5729         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
5730
5731         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
5732         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
5733
5734         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
5735         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
5736
5737         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
5738         if (bp->rx_quick_cons_trip_int > 0xff)
5739                 bp->rx_quick_cons_trip_int = 0xff;
5740
5741         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
5742         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
5743
5744         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
5745         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
5746
5747         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
5748         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
5749
5750         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
5751         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
5752                 0xff;
5753
5754         bp->stats_ticks = coal->stats_block_coalesce_usecs;
5755         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5756                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
5757                         bp->stats_ticks = USEC_PER_SEC;
5758         }
5759         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
5760                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
5761         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
5762
5763         if (netif_running(bp->dev)) {
5764                 bnx2_netif_stop(bp);
5765                 bnx2_init_nic(bp);
5766                 bnx2_netif_start(bp);
5767         }
5768
5769         return 0;
5770 }
5771
5772 static void
5773 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5774 {
5775         struct bnx2 *bp = netdev_priv(dev);
5776
5777         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
5778         ering->rx_mini_max_pending = 0;
5779         ering->rx_jumbo_max_pending = 0;
5780
5781         ering->rx_pending = bp->rx_ring_size;
5782         ering->rx_mini_pending = 0;
5783         ering->rx_jumbo_pending = 0;
5784
5785         ering->tx_max_pending = MAX_TX_DESC_CNT;
5786         ering->tx_pending = bp->tx_ring_size;
5787 }
5788
5789 static int
5790 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5791 {
5792         struct bnx2 *bp = netdev_priv(dev);
5793
5794         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5795                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5796                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5797
5798                 return -EINVAL;
5799         }
5800         if (netif_running(bp->dev)) {
5801                 bnx2_netif_stop(bp);
5802                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5803                 bnx2_free_skbs(bp);
5804                 bnx2_free_mem(bp);
5805         }
5806
5807         bnx2_set_rx_ring_size(bp, ering->rx_pending);
5808         bp->tx_ring_size = ering->tx_pending;
5809
5810         if (netif_running(bp->dev)) {
5811                 int rc;
5812
5813                 rc = bnx2_alloc_mem(bp);
5814                 if (rc)
5815                         return rc;
5816                 bnx2_init_nic(bp);
5817                 bnx2_netif_start(bp);
5818         }
5819
5820         return 0;
5821 }
5822
5823 static void
5824 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5825 {
5826         struct bnx2 *bp = netdev_priv(dev);
5827
5828         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5829         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5830         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5831 }
5832
5833 static int
5834 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5835 {
5836         struct bnx2 *bp = netdev_priv(dev);
5837
5838         bp->req_flow_ctrl = 0;
5839         if (epause->rx_pause)
5840                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5841         if (epause->tx_pause)
5842                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5843
5844         if (epause->autoneg) {
5845                 bp->autoneg |= AUTONEG_FLOW_CTRL;
5846         }
5847         else {
5848                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5849         }
5850
5851         spin_lock_bh(&bp->phy_lock);
5852
5853         bnx2_setup_phy(bp, bp->phy_port);
5854
5855         spin_unlock_bh(&bp->phy_lock);
5856
5857         return 0;
5858 }
5859
5860 static u32
5861 bnx2_get_rx_csum(struct net_device *dev)
5862 {
5863         struct bnx2 *bp = netdev_priv(dev);
5864
5865         return bp->rx_csum;
5866 }
5867
5868 static int
5869 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5870 {
5871         struct bnx2 *bp = netdev_priv(dev);
5872
5873         bp->rx_csum = data;
5874         return 0;
5875 }
5876
5877 static int
5878 bnx2_set_tso(struct net_device *dev, u32 data)
5879 {
5880         struct bnx2 *bp = netdev_priv(dev);
5881
5882         if (data) {
5883                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5884                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5885                         dev->features |= NETIF_F_TSO6;
5886         } else
5887                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
5888                                    NETIF_F_TSO_ECN);
5889         return 0;
5890 }
5891
5892 #define BNX2_NUM_STATS 46
5893
5894 static struct {
5895         char string[ETH_GSTRING_LEN];
5896 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5897         { "rx_bytes" },
5898         { "rx_error_bytes" },
5899         { "tx_bytes" },
5900         { "tx_error_bytes" },
5901         { "rx_ucast_packets" },
5902         { "rx_mcast_packets" },
5903         { "rx_bcast_packets" },
5904         { "tx_ucast_packets" },
5905         { "tx_mcast_packets" },
5906         { "tx_bcast_packets" },
5907         { "tx_mac_errors" },
5908         { "tx_carrier_errors" },
5909         { "rx_crc_errors" },
5910         { "rx_align_errors" },
5911         { "tx_single_collisions" },
5912         { "tx_multi_collisions" },
5913         { "tx_deferred" },
5914         { "tx_excess_collisions" },
5915         { "tx_late_collisions" },
5916         { "tx_total_collisions" },
5917         { "rx_fragments" },
5918         { "rx_jabbers" },
5919         { "rx_undersize_packets" },
5920         { "rx_oversize_packets" },
5921         { "rx_64_byte_packets" },
5922         { "rx_65_to_127_byte_packets" },
5923         { "rx_128_to_255_byte_packets" },
5924         { "rx_256_to_511_byte_packets" },
5925         { "rx_512_to_1023_byte_packets" },
5926         { "rx_1024_to_1522_byte_packets" },
5927         { "rx_1523_to_9022_byte_packets" },
5928         { "tx_64_byte_packets" },
5929         { "tx_65_to_127_byte_packets" },
5930         { "tx_128_to_255_byte_packets" },
5931         { "tx_256_to_511_byte_packets" },
5932         { "tx_512_to_1023_byte_packets" },
5933         { "tx_1024_to_1522_byte_packets" },
5934         { "tx_1523_to_9022_byte_packets" },
5935         { "rx_xon_frames" },
5936         { "rx_xoff_frames" },
5937         { "tx_xon_frames" },
5938         { "tx_xoff_frames" },
5939         { "rx_mac_ctrl_frames" },
5940         { "rx_filtered_packets" },
5941         { "rx_discards" },
5942         { "rx_fw_discards" },
5943 };
5944
5945 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5946
5947 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5948     STATS_OFFSET32(stat_IfHCInOctets_hi),
5949     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5950     STATS_OFFSET32(stat_IfHCOutOctets_hi),
5951     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5952     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5953     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5954     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5955     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5956     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5957     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5958     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5959     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5960     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5961     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5962     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5963     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5964     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5965     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5966     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5967     STATS_OFFSET32(stat_EtherStatsCollisions),
5968     STATS_OFFSET32(stat_EtherStatsFragments),
5969     STATS_OFFSET32(stat_EtherStatsJabbers),
5970     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5971     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5972     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5973     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5974     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5975     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5976     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5977     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5978     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5979     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5980     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5981     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5982     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5983     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5984     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5985     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5986     STATS_OFFSET32(stat_XonPauseFramesReceived),
5987     STATS_OFFSET32(stat_XoffPauseFramesReceived),
5988     STATS_OFFSET32(stat_OutXonSent),
5989     STATS_OFFSET32(stat_OutXoffSent),
5990     STATS_OFFSET32(stat_MacControlFramesReceived),
5991     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5992     STATS_OFFSET32(stat_IfInMBUFDiscards),
5993     STATS_OFFSET32(stat_FwRxDrop),
5994 };
5995
5996 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5997  * skipped because of errata.
5998  */
5999 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6000         8,0,8,8,8,8,8,8,8,8,
6001         4,0,4,4,4,4,4,4,4,4,
6002         4,4,4,4,4,4,4,4,4,4,
6003         4,4,4,4,4,4,4,4,4,4,
6004         4,4,4,4,4,4,
6005 };
6006
6007 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6008         8,0,8,8,8,8,8,8,8,8,
6009         4,4,4,4,4,4,4,4,4,4,
6010         4,4,4,4,4,4,4,4,4,4,
6011         4,4,4,4,4,4,4,4,4,4,
6012         4,4,4,4,4,4,
6013 };
6014
6015 #define BNX2_NUM_TESTS 6
6016
6017 static struct {
6018         char string[ETH_GSTRING_LEN];
6019 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6020         { "register_test (offline)" },
6021         { "memory_test (offline)" },
6022         { "loopback_test (offline)" },
6023         { "nvram_test (online)" },
6024         { "interrupt_test (online)" },
6025         { "link_test (online)" },
6026 };
6027
6028 static int
6029 bnx2_get_sset_count(struct net_device *dev, int sset)
6030 {
6031         switch (sset) {
6032         case ETH_SS_TEST:
6033                 return BNX2_NUM_TESTS;
6034         case ETH_SS_STATS:
6035                 return BNX2_NUM_STATS;
6036         default:
6037                 return -EOPNOTSUPP;
6038         }
6039 }
6040
6041 static void
6042 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6043 {
6044         struct bnx2 *bp = netdev_priv(dev);
6045
6046         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6047         if (etest->flags & ETH_TEST_FL_OFFLINE) {
6048                 int i;
6049
6050                 bnx2_netif_stop(bp);
6051                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6052                 bnx2_free_skbs(bp);
6053
6054                 if (bnx2_test_registers(bp) != 0) {
6055                         buf[0] = 1;
6056                         etest->flags |= ETH_TEST_FL_FAILED;
6057                 }
6058                 if (bnx2_test_memory(bp) != 0) {
6059                         buf[1] = 1;
6060                         etest->flags |= ETH_TEST_FL_FAILED;
6061                 }
6062                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6063                         etest->flags |= ETH_TEST_FL_FAILED;
6064
6065                 if (!netif_running(bp->dev)) {
6066                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6067                 }
6068                 else {
6069                         bnx2_init_nic(bp);
6070                         bnx2_netif_start(bp);
6071                 }
6072
6073                 /* wait for link up */
6074                 for (i = 0; i < 7; i++) {
6075                         if (bp->link_up)
6076                                 break;
6077                         msleep_interruptible(1000);
6078                 }
6079         }
6080
6081         if (bnx2_test_nvram(bp) != 0) {
6082                 buf[3] = 1;
6083                 etest->flags |= ETH_TEST_FL_FAILED;
6084         }
6085         if (bnx2_test_intr(bp) != 0) {
6086                 buf[4] = 1;
6087                 etest->flags |= ETH_TEST_FL_FAILED;
6088         }
6089
6090         if (bnx2_test_link(bp) != 0) {
6091                 buf[5] = 1;
6092                 etest->flags |= ETH_TEST_FL_FAILED;
6093
6094         }
6095 }
6096
6097 static void
6098 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6099 {
6100         switch (stringset) {
6101         case ETH_SS_STATS:
6102                 memcpy(buf, bnx2_stats_str_arr,
6103                         sizeof(bnx2_stats_str_arr));
6104                 break;
6105         case ETH_SS_TEST:
6106                 memcpy(buf, bnx2_tests_str_arr,
6107                         sizeof(bnx2_tests_str_arr));
6108                 break;
6109         }
6110 }
6111
6112 static void
6113 bnx2_get_ethtool_stats(struct net_device *dev,
6114                 struct ethtool_stats *stats, u64 *buf)
6115 {
6116         struct bnx2 *bp = netdev_priv(dev);
6117         int i;
6118         u32 *hw_stats = (u32 *) bp->stats_blk;
6119         u8 *stats_len_arr = NULL;
6120
6121         if (hw_stats == NULL) {
6122                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);