[BNX2]: remove atomics in tx
[linux-2.6.git] / drivers / net / bnx2.c
1 /* bnx2.c: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004, 2005 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12 #include "bnx2.h"
13 #include "bnx2_fw.h"
14
15 #define DRV_MODULE_NAME         "bnx2"
16 #define PFX DRV_MODULE_NAME     ": "
17 #define DRV_MODULE_VERSION      "1.2.19"
18 #define DRV_MODULE_RELDATE      "May 23, 2005"
19
20 #define RUN_AT(x) (jiffies + (x))
21
22 /* Time in jiffies before concluding the transmitter is hung. */
23 #define TX_TIMEOUT  (5*HZ)
24
25 static char version[] __devinitdata =
26         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
30 MODULE_LICENSE("GPL");
31 MODULE_VERSION(DRV_MODULE_VERSION);
32
33 static int disable_msi = 0;
34
35 module_param(disable_msi, int, 0);
36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38 typedef enum {
39         BCM5706 = 0,
40         NC370T,
41         NC370I,
42         BCM5706S,
43         NC370F,
44 } board_t;
45
46 /* indexed by board_t, above */
47 static struct {
48         char *name;
49 } board_info[] __devinitdata = {
50         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
51         { "HP NC370T Multifunction Gigabit Server Adapter" },
52         { "HP NC370i Multifunction Gigabit Server Adapter" },
53         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
54         { "HP NC370F Multifunction Gigabit Server Adapter" },
55         };
56
57 static struct pci_device_id bnx2_pci_tbl[] = {
58         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
59           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
60         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
61           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
62         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
64         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
65           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
66         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
67           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
68         { 0, }
69 };
70
71 static struct flash_spec flash_table[] =
72 {
73         /* Slow EEPROM */
74         {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
75          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
76          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
77          "EEPROM - slow"},
78         /* Fast EEPROM */
79         {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
80          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
81          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
82          "EEPROM - fast"},
83         /* ATMEL AT45DB011B (buffered flash) */
84         {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
85          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
86          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
87          "Buffered flash"},
88         /* Saifun SA25F005 (non-buffered flash) */
89         /* strap, cfg1, & write1 need updates */
90         {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
91          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
92          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
93          "Non-buffered flash (64kB)"},
94         /* Saifun SA25F010 (non-buffered flash) */
95         /* strap, cfg1, & write1 need updates */
96         {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
97          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
98          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
99          "Non-buffered flash (128kB)"},
100         /* Saifun SA25F020 (non-buffered flash) */
101         /* strap, cfg1, & write1 need updates */
102         {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
103          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
104          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
105          "Non-buffered flash (256kB)"},
106 };
107
108 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
109
110 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
111 {
112         u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
113
114         if (diff > MAX_TX_DESC_CNT)
115                 diff = (diff & MAX_TX_DESC_CNT) - 1;
116         return (bp->tx_ring_size - diff);
117 }
118
119 static u32
120 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
121 {
122         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
123         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
124 }
125
126 static void
127 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
128 {
129         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
130         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
131 }
132
133 static void
134 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
135 {
136         offset += cid_addr;
137         REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
138         REG_WR(bp, BNX2_CTX_DATA, val);
139 }
140
141 static int
142 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
143 {
144         u32 val1;
145         int i, ret;
146
147         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
148                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
149                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
150
151                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
152                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
153
154                 udelay(40);
155         }
156
157         val1 = (bp->phy_addr << 21) | (reg << 16) |
158                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
159                 BNX2_EMAC_MDIO_COMM_START_BUSY;
160         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
161
162         for (i = 0; i < 50; i++) {
163                 udelay(10);
164
165                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
166                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
167                         udelay(5);
168
169                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
170                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
171
172                         break;
173                 }
174         }
175
176         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
177                 *val = 0x0;
178                 ret = -EBUSY;
179         }
180         else {
181                 *val = val1;
182                 ret = 0;
183         }
184
185         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
186                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
187                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
188
189                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
190                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
191
192                 udelay(40);
193         }
194
195         return ret;
196 }
197
198 static int
199 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
200 {
201         u32 val1;
202         int i, ret;
203
204         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
205                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
206                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
207
208                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
209                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
210
211                 udelay(40);
212         }
213
214         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
215                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
216                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
217         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
218     
219         for (i = 0; i < 50; i++) {
220                 udelay(10);
221
222                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
223                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
224                         udelay(5);
225                         break;
226                 }
227         }
228
229         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
230                 ret = -EBUSY;
231         else
232                 ret = 0;
233
234         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
235                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
236                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
237
238                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
239                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
240
241                 udelay(40);
242         }
243
244         return ret;
245 }
246
247 static void
248 bnx2_disable_int(struct bnx2 *bp)
249 {
250         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
251                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
252         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
253 }
254
255 static void
256 bnx2_enable_int(struct bnx2 *bp)
257 {
258         u32 val;
259
260         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
261                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
262
263         val = REG_RD(bp, BNX2_HC_COMMAND);
264         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
265 }
266
267 static void
268 bnx2_disable_int_sync(struct bnx2 *bp)
269 {
270         atomic_inc(&bp->intr_sem);
271         bnx2_disable_int(bp);
272         synchronize_irq(bp->pdev->irq);
273 }
274
275 static void
276 bnx2_netif_stop(struct bnx2 *bp)
277 {
278         bnx2_disable_int_sync(bp);
279         if (netif_running(bp->dev)) {
280                 netif_poll_disable(bp->dev);
281                 netif_tx_disable(bp->dev);
282                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
283         }
284 }
285
286 static void
287 bnx2_netif_start(struct bnx2 *bp)
288 {
289         if (atomic_dec_and_test(&bp->intr_sem)) {
290                 if (netif_running(bp->dev)) {
291                         netif_wake_queue(bp->dev);
292                         netif_poll_enable(bp->dev);
293                         bnx2_enable_int(bp);
294                 }
295         }
296 }
297
298 static void
299 bnx2_free_mem(struct bnx2 *bp)
300 {
301         if (bp->stats_blk) {
302                 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
303                                     bp->stats_blk, bp->stats_blk_mapping);
304                 bp->stats_blk = NULL;
305         }
306         if (bp->status_blk) {
307                 pci_free_consistent(bp->pdev, sizeof(struct status_block),
308                                     bp->status_blk, bp->status_blk_mapping);
309                 bp->status_blk = NULL;
310         }
311         if (bp->tx_desc_ring) {
312                 pci_free_consistent(bp->pdev,
313                                     sizeof(struct tx_bd) * TX_DESC_CNT,
314                                     bp->tx_desc_ring, bp->tx_desc_mapping);
315                 bp->tx_desc_ring = NULL;
316         }
317         if (bp->tx_buf_ring) {
318                 kfree(bp->tx_buf_ring);
319                 bp->tx_buf_ring = NULL;
320         }
321         if (bp->rx_desc_ring) {
322                 pci_free_consistent(bp->pdev,
323                                     sizeof(struct rx_bd) * RX_DESC_CNT,
324                                     bp->rx_desc_ring, bp->rx_desc_mapping);
325                 bp->rx_desc_ring = NULL;
326         }
327         if (bp->rx_buf_ring) {
328                 kfree(bp->rx_buf_ring);
329                 bp->rx_buf_ring = NULL;
330         }
331 }
332
333 static int
334 bnx2_alloc_mem(struct bnx2 *bp)
335 {
336         bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
337                                      GFP_KERNEL);
338         if (bp->tx_buf_ring == NULL)
339                 return -ENOMEM;
340
341         memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
342         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
343                                                 sizeof(struct tx_bd) *
344                                                 TX_DESC_CNT,
345                                                 &bp->tx_desc_mapping);
346         if (bp->tx_desc_ring == NULL)
347                 goto alloc_mem_err;
348
349         bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
350                                      GFP_KERNEL);
351         if (bp->rx_buf_ring == NULL)
352                 goto alloc_mem_err;
353
354         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
355         bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
356                                                 sizeof(struct rx_bd) *
357                                                 RX_DESC_CNT,
358                                                 &bp->rx_desc_mapping);
359         if (bp->rx_desc_ring == NULL)
360                 goto alloc_mem_err;
361
362         bp->status_blk = pci_alloc_consistent(bp->pdev,
363                                               sizeof(struct status_block),
364                                               &bp->status_blk_mapping);
365         if (bp->status_blk == NULL)
366                 goto alloc_mem_err;
367
368         memset(bp->status_blk, 0, sizeof(struct status_block));
369
370         bp->stats_blk = pci_alloc_consistent(bp->pdev,
371                                              sizeof(struct statistics_block),
372                                              &bp->stats_blk_mapping);
373         if (bp->stats_blk == NULL)
374                 goto alloc_mem_err;
375
376         memset(bp->stats_blk, 0, sizeof(struct statistics_block));
377
378         return 0;
379
380 alloc_mem_err:
381         bnx2_free_mem(bp);
382         return -ENOMEM;
383 }
384
385 static void
386 bnx2_report_link(struct bnx2 *bp)
387 {
388         if (bp->link_up) {
389                 netif_carrier_on(bp->dev);
390                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
391
392                 printk("%d Mbps ", bp->line_speed);
393
394                 if (bp->duplex == DUPLEX_FULL)
395                         printk("full duplex");
396                 else
397                         printk("half duplex");
398
399                 if (bp->flow_ctrl) {
400                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
401                                 printk(", receive ");
402                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
403                                         printk("& transmit ");
404                         }
405                         else {
406                                 printk(", transmit ");
407                         }
408                         printk("flow control ON");
409                 }
410                 printk("\n");
411         }
412         else {
413                 netif_carrier_off(bp->dev);
414                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
415         }
416 }
417
418 static void
419 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
420 {
421         u32 local_adv, remote_adv;
422
423         bp->flow_ctrl = 0;
424         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 
425                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
426
427                 if (bp->duplex == DUPLEX_FULL) {
428                         bp->flow_ctrl = bp->req_flow_ctrl;
429                 }
430                 return;
431         }
432
433         if (bp->duplex != DUPLEX_FULL) {
434                 return;
435         }
436
437         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
438         bnx2_read_phy(bp, MII_LPA, &remote_adv);
439
440         if (bp->phy_flags & PHY_SERDES_FLAG) {
441                 u32 new_local_adv = 0;
442                 u32 new_remote_adv = 0;
443
444                 if (local_adv & ADVERTISE_1000XPAUSE)
445                         new_local_adv |= ADVERTISE_PAUSE_CAP;
446                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
447                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
448                 if (remote_adv & ADVERTISE_1000XPAUSE)
449                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
450                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
451                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
452
453                 local_adv = new_local_adv;
454                 remote_adv = new_remote_adv;
455         }
456
457         /* See Table 28B-3 of 802.3ab-1999 spec. */
458         if (local_adv & ADVERTISE_PAUSE_CAP) {
459                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
460                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
461                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
462                         }
463                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
464                                 bp->flow_ctrl = FLOW_CTRL_RX;
465                         }
466                 }
467                 else {
468                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
469                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
470                         }
471                 }
472         }
473         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
474                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
475                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
476
477                         bp->flow_ctrl = FLOW_CTRL_TX;
478                 }
479         }
480 }
481
482 static int
483 bnx2_serdes_linkup(struct bnx2 *bp)
484 {
485         u32 bmcr, local_adv, remote_adv, common;
486
487         bp->link_up = 1;
488         bp->line_speed = SPEED_1000;
489
490         bnx2_read_phy(bp, MII_BMCR, &bmcr);
491         if (bmcr & BMCR_FULLDPLX) {
492                 bp->duplex = DUPLEX_FULL;
493         }
494         else {
495                 bp->duplex = DUPLEX_HALF;
496         }
497
498         if (!(bmcr & BMCR_ANENABLE)) {
499                 return 0;
500         }
501
502         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
503         bnx2_read_phy(bp, MII_LPA, &remote_adv);
504
505         common = local_adv & remote_adv;
506         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
507
508                 if (common & ADVERTISE_1000XFULL) {
509                         bp->duplex = DUPLEX_FULL;
510                 }
511                 else {
512                         bp->duplex = DUPLEX_HALF;
513                 }
514         }
515
516         return 0;
517 }
518
519 static int
520 bnx2_copper_linkup(struct bnx2 *bp)
521 {
522         u32 bmcr;
523
524         bnx2_read_phy(bp, MII_BMCR, &bmcr);
525         if (bmcr & BMCR_ANENABLE) {
526                 u32 local_adv, remote_adv, common;
527
528                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
529                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
530
531                 common = local_adv & (remote_adv >> 2);
532                 if (common & ADVERTISE_1000FULL) {
533                         bp->line_speed = SPEED_1000;
534                         bp->duplex = DUPLEX_FULL;
535                 }
536                 else if (common & ADVERTISE_1000HALF) {
537                         bp->line_speed = SPEED_1000;
538                         bp->duplex = DUPLEX_HALF;
539                 }
540                 else {
541                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
542                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
543
544                         common = local_adv & remote_adv;
545                         if (common & ADVERTISE_100FULL) {
546                                 bp->line_speed = SPEED_100;
547                                 bp->duplex = DUPLEX_FULL;
548                         }
549                         else if (common & ADVERTISE_100HALF) {
550                                 bp->line_speed = SPEED_100;
551                                 bp->duplex = DUPLEX_HALF;
552                         }
553                         else if (common & ADVERTISE_10FULL) {
554                                 bp->line_speed = SPEED_10;
555                                 bp->duplex = DUPLEX_FULL;
556                         }
557                         else if (common & ADVERTISE_10HALF) {
558                                 bp->line_speed = SPEED_10;
559                                 bp->duplex = DUPLEX_HALF;
560                         }
561                         else {
562                                 bp->line_speed = 0;
563                                 bp->link_up = 0;
564                         }
565                 }
566         }
567         else {
568                 if (bmcr & BMCR_SPEED100) {
569                         bp->line_speed = SPEED_100;
570                 }
571                 else {
572                         bp->line_speed = SPEED_10;
573                 }
574                 if (bmcr & BMCR_FULLDPLX) {
575                         bp->duplex = DUPLEX_FULL;
576                 }
577                 else {
578                         bp->duplex = DUPLEX_HALF;
579                 }
580         }
581
582         return 0;
583 }
584
585 static int
586 bnx2_set_mac_link(struct bnx2 *bp)
587 {
588         u32 val;
589
590         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
591         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
592                 (bp->duplex == DUPLEX_HALF)) {
593                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
594         }
595
596         /* Configure the EMAC mode register. */
597         val = REG_RD(bp, BNX2_EMAC_MODE);
598
599         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
600                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
601
602         if (bp->link_up) {
603                 if (bp->line_speed != SPEED_1000)
604                         val |= BNX2_EMAC_MODE_PORT_MII;
605                 else
606                         val |= BNX2_EMAC_MODE_PORT_GMII;
607         }
608         else {
609                 val |= BNX2_EMAC_MODE_PORT_GMII;
610         }
611
612         /* Set the MAC to operate in the appropriate duplex mode. */
613         if (bp->duplex == DUPLEX_HALF)
614                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
615         REG_WR(bp, BNX2_EMAC_MODE, val);
616
617         /* Enable/disable rx PAUSE. */
618         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
619
620         if (bp->flow_ctrl & FLOW_CTRL_RX)
621                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
622         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
623
624         /* Enable/disable tx PAUSE. */
625         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
626         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
627
628         if (bp->flow_ctrl & FLOW_CTRL_TX)
629                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
630         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
631
632         /* Acknowledge the interrupt. */
633         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
634
635         return 0;
636 }
637
638 static int
639 bnx2_set_link(struct bnx2 *bp)
640 {
641         u32 bmsr;
642         u8 link_up;
643
644         if (bp->loopback == MAC_LOOPBACK) {
645                 bp->link_up = 1;
646                 return 0;
647         }
648
649         link_up = bp->link_up;
650
651         bnx2_read_phy(bp, MII_BMSR, &bmsr);
652         bnx2_read_phy(bp, MII_BMSR, &bmsr);
653
654         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
655             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
656                 u32 val;
657
658                 val = REG_RD(bp, BNX2_EMAC_STATUS);
659                 if (val & BNX2_EMAC_STATUS_LINK)
660                         bmsr |= BMSR_LSTATUS;
661                 else
662                         bmsr &= ~BMSR_LSTATUS;
663         }
664
665         if (bmsr & BMSR_LSTATUS) {
666                 bp->link_up = 1;
667
668                 if (bp->phy_flags & PHY_SERDES_FLAG) {
669                         bnx2_serdes_linkup(bp);
670                 }
671                 else {
672                         bnx2_copper_linkup(bp);
673                 }
674                 bnx2_resolve_flow_ctrl(bp);
675         }
676         else {
677                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
678                         (bp->autoneg & AUTONEG_SPEED)) {
679
680                         u32 bmcr;
681
682                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
683                         if (!(bmcr & BMCR_ANENABLE)) {
684                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
685                                         BMCR_ANENABLE);
686                         }
687                 }
688                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
689                 bp->link_up = 0;
690         }
691
692         if (bp->link_up != link_up) {
693                 bnx2_report_link(bp);
694         }
695
696         bnx2_set_mac_link(bp);
697
698         return 0;
699 }
700
701 static int
702 bnx2_reset_phy(struct bnx2 *bp)
703 {
704         int i;
705         u32 reg;
706
707         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
708
709 #define PHY_RESET_MAX_WAIT 100
710         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
711                 udelay(10);
712
713                 bnx2_read_phy(bp, MII_BMCR, &reg);
714                 if (!(reg & BMCR_RESET)) {
715                         udelay(20);
716                         break;
717                 }
718         }
719         if (i == PHY_RESET_MAX_WAIT) {
720                 return -EBUSY;
721         }
722         return 0;
723 }
724
725 static u32
726 bnx2_phy_get_pause_adv(struct bnx2 *bp)
727 {
728         u32 adv = 0;
729
730         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
731                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
732
733                 if (bp->phy_flags & PHY_SERDES_FLAG) {
734                         adv = ADVERTISE_1000XPAUSE;
735                 }
736                 else {
737                         adv = ADVERTISE_PAUSE_CAP;
738                 }
739         }
740         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
741                 if (bp->phy_flags & PHY_SERDES_FLAG) {
742                         adv = ADVERTISE_1000XPSE_ASYM;
743                 }
744                 else {
745                         adv = ADVERTISE_PAUSE_ASYM;
746                 }
747         }
748         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
749                 if (bp->phy_flags & PHY_SERDES_FLAG) {
750                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
751                 }
752                 else {
753                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
754                 }
755         }
756         return adv;
757 }
758
759 static int
760 bnx2_setup_serdes_phy(struct bnx2 *bp)
761 {
762         u32 adv, bmcr;
763         u32 new_adv = 0;
764
765         if (!(bp->autoneg & AUTONEG_SPEED)) {
766                 u32 new_bmcr;
767
768                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
769                 new_bmcr = bmcr & ~BMCR_ANENABLE;
770                 new_bmcr |= BMCR_SPEED1000;
771                 if (bp->req_duplex == DUPLEX_FULL) {
772                         new_bmcr |= BMCR_FULLDPLX;
773                 }
774                 else {
775                         new_bmcr &= ~BMCR_FULLDPLX;
776                 }
777                 if (new_bmcr != bmcr) {
778                         /* Force a link down visible on the other side */
779                         if (bp->link_up) {
780                                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
781                                 adv &= ~(ADVERTISE_1000XFULL |
782                                         ADVERTISE_1000XHALF);
783                                 bnx2_write_phy(bp, MII_ADVERTISE, adv);
784                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
785                                         BMCR_ANRESTART | BMCR_ANENABLE);
786
787                                 bp->link_up = 0;
788                                 netif_carrier_off(bp->dev);
789                         }
790                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
791                 }
792                 return 0;
793         }
794
795         if (bp->advertising & ADVERTISED_1000baseT_Full)
796                 new_adv |= ADVERTISE_1000XFULL;
797
798         new_adv |= bnx2_phy_get_pause_adv(bp);
799
800         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
801         bnx2_read_phy(bp, MII_BMCR, &bmcr);
802
803         bp->serdes_an_pending = 0;
804         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
805                 /* Force a link down visible on the other side */
806                 if (bp->link_up) {
807                         int i;
808
809                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
810                         for (i = 0; i < 110; i++) {
811                                 udelay(100);
812                         }
813                 }
814
815                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
816                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
817                         BMCR_ANENABLE);
818                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
819                         /* Speed up link-up time when the link partner
820                          * does not autonegotiate which is very common
821                          * in blade servers. Some blade servers use
822                          * IPMI for kerboard input and it's important
823                          * to minimize link disruptions. Autoneg. involves
824                          * exchanging base pages plus 3 next pages and
825                          * normally completes in about 120 msec.
826                          */
827                         bp->current_interval = SERDES_AN_TIMEOUT;
828                         bp->serdes_an_pending = 1;
829                         mod_timer(&bp->timer, jiffies + bp->current_interval);
830                 }
831         }
832
833         return 0;
834 }
835
836 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
837         (ADVERTISED_1000baseT_Full)
838
839 #define ETHTOOL_ALL_COPPER_SPEED                                        \
840         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
841         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
842         ADVERTISED_1000baseT_Full)
843
844 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
845         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
846         
847 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
848
849 static int
850 bnx2_setup_copper_phy(struct bnx2 *bp)
851 {
852         u32 bmcr;
853         u32 new_bmcr;
854
855         bnx2_read_phy(bp, MII_BMCR, &bmcr);
856
857         if (bp->autoneg & AUTONEG_SPEED) {
858                 u32 adv_reg, adv1000_reg;
859                 u32 new_adv_reg = 0;
860                 u32 new_adv1000_reg = 0;
861
862                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
863                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
864                         ADVERTISE_PAUSE_ASYM);
865
866                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
867                 adv1000_reg &= PHY_ALL_1000_SPEED;
868
869                 if (bp->advertising & ADVERTISED_10baseT_Half)
870                         new_adv_reg |= ADVERTISE_10HALF;
871                 if (bp->advertising & ADVERTISED_10baseT_Full)
872                         new_adv_reg |= ADVERTISE_10FULL;
873                 if (bp->advertising & ADVERTISED_100baseT_Half)
874                         new_adv_reg |= ADVERTISE_100HALF;
875                 if (bp->advertising & ADVERTISED_100baseT_Full)
876                         new_adv_reg |= ADVERTISE_100FULL;
877                 if (bp->advertising & ADVERTISED_1000baseT_Full)
878                         new_adv1000_reg |= ADVERTISE_1000FULL;
879                 
880                 new_adv_reg |= ADVERTISE_CSMA;
881
882                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
883
884                 if ((adv1000_reg != new_adv1000_reg) ||
885                         (adv_reg != new_adv_reg) ||
886                         ((bmcr & BMCR_ANENABLE) == 0)) {
887
888                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
889                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
890                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
891                                 BMCR_ANENABLE);
892                 }
893                 else if (bp->link_up) {
894                         /* Flow ctrl may have changed from auto to forced */
895                         /* or vice-versa. */
896
897                         bnx2_resolve_flow_ctrl(bp);
898                         bnx2_set_mac_link(bp);
899                 }
900                 return 0;
901         }
902
903         new_bmcr = 0;
904         if (bp->req_line_speed == SPEED_100) {
905                 new_bmcr |= BMCR_SPEED100;
906         }
907         if (bp->req_duplex == DUPLEX_FULL) {
908                 new_bmcr |= BMCR_FULLDPLX;
909         }
910         if (new_bmcr != bmcr) {
911                 u32 bmsr;
912                 int i = 0;
913
914                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
915                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
916                 
917                 if (bmsr & BMSR_LSTATUS) {
918                         /* Force link down */
919                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
920                         do {
921                                 udelay(100);
922                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
923                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
924                                 i++;
925                         } while ((bmsr & BMSR_LSTATUS) && (i < 620));
926                 }
927
928                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
929
930                 /* Normally, the new speed is setup after the link has
931                  * gone down and up again. In some cases, link will not go
932                  * down so we need to set up the new speed here.
933                  */
934                 if (bmsr & BMSR_LSTATUS) {
935                         bp->line_speed = bp->req_line_speed;
936                         bp->duplex = bp->req_duplex;
937                         bnx2_resolve_flow_ctrl(bp);
938                         bnx2_set_mac_link(bp);
939                 }
940         }
941         return 0;
942 }
943
944 static int
945 bnx2_setup_phy(struct bnx2 *bp)
946 {
947         if (bp->loopback == MAC_LOOPBACK)
948                 return 0;
949
950         if (bp->phy_flags & PHY_SERDES_FLAG) {
951                 return (bnx2_setup_serdes_phy(bp));
952         }
953         else {
954                 return (bnx2_setup_copper_phy(bp));
955         }
956 }
957
958 static int
959 bnx2_init_serdes_phy(struct bnx2 *bp)
960 {
961         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
962
963         if (CHIP_NUM(bp) == CHIP_NUM_5706) {
964                 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
965         }
966
967         if (bp->dev->mtu > 1500) {
968                 u32 val;
969
970                 /* Set extended packet length bit */
971                 bnx2_write_phy(bp, 0x18, 0x7);
972                 bnx2_read_phy(bp, 0x18, &val);
973                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
974
975                 bnx2_write_phy(bp, 0x1c, 0x6c00);
976                 bnx2_read_phy(bp, 0x1c, &val);
977                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
978         }
979         else {
980                 u32 val;
981
982                 bnx2_write_phy(bp, 0x18, 0x7);
983                 bnx2_read_phy(bp, 0x18, &val);
984                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
985
986                 bnx2_write_phy(bp, 0x1c, 0x6c00);
987                 bnx2_read_phy(bp, 0x1c, &val);
988                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
989         }
990
991         return 0;
992 }
993
994 static int
995 bnx2_init_copper_phy(struct bnx2 *bp)
996 {
997         bp->phy_flags |= PHY_CRC_FIX_FLAG;
998
999         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1000                 bnx2_write_phy(bp, 0x18, 0x0c00);
1001                 bnx2_write_phy(bp, 0x17, 0x000a);
1002                 bnx2_write_phy(bp, 0x15, 0x310b);
1003                 bnx2_write_phy(bp, 0x17, 0x201f);
1004                 bnx2_write_phy(bp, 0x15, 0x9506);
1005                 bnx2_write_phy(bp, 0x17, 0x401f);
1006                 bnx2_write_phy(bp, 0x15, 0x14e2);
1007                 bnx2_write_phy(bp, 0x18, 0x0400);
1008         }
1009
1010         if (bp->dev->mtu > 1500) {
1011                 u32 val;
1012
1013                 /* Set extended packet length bit */
1014                 bnx2_write_phy(bp, 0x18, 0x7);
1015                 bnx2_read_phy(bp, 0x18, &val);
1016                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1017
1018                 bnx2_read_phy(bp, 0x10, &val);
1019                 bnx2_write_phy(bp, 0x10, val | 0x1);
1020         }
1021         else {
1022                 u32 val;
1023
1024                 bnx2_write_phy(bp, 0x18, 0x7);
1025                 bnx2_read_phy(bp, 0x18, &val);
1026                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1027
1028                 bnx2_read_phy(bp, 0x10, &val);
1029                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1030         }
1031
1032         return 0;
1033 }
1034
1035
1036 static int
1037 bnx2_init_phy(struct bnx2 *bp)
1038 {
1039         u32 val;
1040         int rc = 0;
1041
1042         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1043         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1044
1045         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1046
1047         bnx2_reset_phy(bp);
1048
1049         bnx2_read_phy(bp, MII_PHYSID1, &val);
1050         bp->phy_id = val << 16;
1051         bnx2_read_phy(bp, MII_PHYSID2, &val);
1052         bp->phy_id |= val & 0xffff;
1053
1054         if (bp->phy_flags & PHY_SERDES_FLAG) {
1055                 rc = bnx2_init_serdes_phy(bp);
1056         }
1057         else {
1058                 rc = bnx2_init_copper_phy(bp);
1059         }
1060
1061         bnx2_setup_phy(bp);
1062
1063         return rc;
1064 }
1065
1066 static int
1067 bnx2_set_mac_loopback(struct bnx2 *bp)
1068 {
1069         u32 mac_mode;
1070
1071         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1072         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1073         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1074         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1075         bp->link_up = 1;
1076         return 0;
1077 }
1078
1079 static int
1080 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1081 {
1082         int i;
1083         u32 val;
1084
1085         if (bp->fw_timed_out)
1086                 return -EBUSY;
1087
1088         bp->fw_wr_seq++;
1089         msg_data |= bp->fw_wr_seq;
1090
1091         REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1092
1093         /* wait for an acknowledgement. */
1094         for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1095                 udelay(5);
1096
1097                 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1098
1099                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1100                         break;
1101         }
1102
1103         /* If we timed out, inform the firmware that this is the case. */
1104         if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1105                 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1106
1107                 msg_data &= ~BNX2_DRV_MSG_CODE;
1108                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1109
1110                 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1111
1112                 bp->fw_timed_out = 1;
1113
1114                 return -EBUSY;
1115         }
1116
1117         return 0;
1118 }
1119
1120 static void
1121 bnx2_init_context(struct bnx2 *bp)
1122 {
1123         u32 vcid;
1124
1125         vcid = 96;
1126         while (vcid) {
1127                 u32 vcid_addr, pcid_addr, offset;
1128
1129                 vcid--;
1130
1131                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1132                         u32 new_vcid;
1133
1134                         vcid_addr = GET_PCID_ADDR(vcid);
1135                         if (vcid & 0x8) {
1136                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1137                         }
1138                         else {
1139                                 new_vcid = vcid;
1140                         }
1141                         pcid_addr = GET_PCID_ADDR(new_vcid);
1142                 }
1143                 else {
1144                         vcid_addr = GET_CID_ADDR(vcid);
1145                         pcid_addr = vcid_addr;
1146                 }
1147
1148                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1149                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1150
1151                 /* Zero out the context. */
1152                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1153                         CTX_WR(bp, 0x00, offset, 0);
1154                 }
1155
1156                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1157                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1158         }
1159 }
1160
1161 static int
1162 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1163 {
1164         u16 *good_mbuf;
1165         u32 good_mbuf_cnt;
1166         u32 val;
1167
1168         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1169         if (good_mbuf == NULL) {
1170                 printk(KERN_ERR PFX "Failed to allocate memory in "
1171                                     "bnx2_alloc_bad_rbuf\n");
1172                 return -ENOMEM;
1173         }
1174
1175         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1176                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1177
1178         good_mbuf_cnt = 0;
1179
1180         /* Allocate a bunch of mbufs and save the good ones in an array. */
1181         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1182         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1183                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1184
1185                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1186
1187                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1188
1189                 /* The addresses with Bit 9 set are bad memory blocks. */
1190                 if (!(val & (1 << 9))) {
1191                         good_mbuf[good_mbuf_cnt] = (u16) val;
1192                         good_mbuf_cnt++;
1193                 }
1194
1195                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1196         }
1197
1198         /* Free the good ones back to the mbuf pool thus discarding
1199          * all the bad ones. */
1200         while (good_mbuf_cnt) {
1201                 good_mbuf_cnt--;
1202
1203                 val = good_mbuf[good_mbuf_cnt];
1204                 val = (val << 9) | val | 1;
1205
1206                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1207         }
1208         kfree(good_mbuf);
1209         return 0;
1210 }
1211
1212 static void
1213 bnx2_set_mac_addr(struct bnx2 *bp) 
1214 {
1215         u32 val;
1216         u8 *mac_addr = bp->dev->dev_addr;
1217
1218         val = (mac_addr[0] << 8) | mac_addr[1];
1219
1220         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1221
1222         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 
1223                 (mac_addr[4] << 8) | mac_addr[5];
1224
1225         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1226 }
1227
1228 static inline int
1229 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1230 {
1231         struct sk_buff *skb;
1232         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1233         dma_addr_t mapping;
1234         struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1235         unsigned long align;
1236
1237         skb = dev_alloc_skb(bp->rx_buf_size);
1238         if (skb == NULL) {
1239                 return -ENOMEM;
1240         }
1241
1242         if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1243                 skb_reserve(skb, 8 - align);
1244         }
1245
1246         skb->dev = bp->dev;
1247         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1248                 PCI_DMA_FROMDEVICE);
1249
1250         rx_buf->skb = skb;
1251         pci_unmap_addr_set(rx_buf, mapping, mapping);
1252
1253         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1254         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1255
1256         bp->rx_prod_bseq += bp->rx_buf_use_size;
1257
1258         return 0;
1259 }
1260
1261 static void
1262 bnx2_phy_int(struct bnx2 *bp)
1263 {
1264         u32 new_link_state, old_link_state;
1265
1266         new_link_state = bp->status_blk->status_attn_bits &
1267                 STATUS_ATTN_BITS_LINK_STATE;
1268         old_link_state = bp->status_blk->status_attn_bits_ack &
1269                 STATUS_ATTN_BITS_LINK_STATE;
1270         if (new_link_state != old_link_state) {
1271                 if (new_link_state) {
1272                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1273                                 STATUS_ATTN_BITS_LINK_STATE);
1274                 }
1275                 else {
1276                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1277                                 STATUS_ATTN_BITS_LINK_STATE);
1278                 }
1279                 bnx2_set_link(bp);
1280         }
1281 }
1282
1283 static void
1284 bnx2_tx_int(struct bnx2 *bp)
1285 {
1286         u16 hw_cons, sw_cons, sw_ring_cons;
1287         int tx_free_bd = 0;
1288
1289         hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1290         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1291                 hw_cons++;
1292         }
1293         sw_cons = bp->tx_cons;
1294
1295         while (sw_cons != hw_cons) {
1296                 struct sw_bd *tx_buf;
1297                 struct sk_buff *skb;
1298                 int i, last;
1299
1300                 sw_ring_cons = TX_RING_IDX(sw_cons);
1301
1302                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1303                 skb = tx_buf->skb;
1304 #ifdef BCM_TSO 
1305                 /* partial BD completions possible with TSO packets */
1306                 if (skb_shinfo(skb)->tso_size) {
1307                         u16 last_idx, last_ring_idx;
1308
1309                         last_idx = sw_cons +
1310                                 skb_shinfo(skb)->nr_frags + 1;
1311                         last_ring_idx = sw_ring_cons +
1312                                 skb_shinfo(skb)->nr_frags + 1;
1313                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1314                                 last_idx++;
1315                         }
1316                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1317                                 break;
1318                         }
1319                 }
1320 #endif
1321                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1322                         skb_headlen(skb), PCI_DMA_TODEVICE);
1323
1324                 tx_buf->skb = NULL;
1325                 last = skb_shinfo(skb)->nr_frags;
1326
1327                 for (i = 0; i < last; i++) {
1328                         sw_cons = NEXT_TX_BD(sw_cons);
1329
1330                         pci_unmap_page(bp->pdev,
1331                                 pci_unmap_addr(
1332                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1333                                         mapping),
1334                                 skb_shinfo(skb)->frags[i].size,
1335                                 PCI_DMA_TODEVICE);
1336                 }
1337
1338                 sw_cons = NEXT_TX_BD(sw_cons);
1339
1340                 tx_free_bd += last + 1;
1341
1342                 dev_kfree_skb_irq(skb);
1343
1344                 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1345                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1346                         hw_cons++;
1347                 }
1348         }
1349
1350         bp->tx_cons = sw_cons;
1351
1352         if (unlikely(netif_queue_stopped(bp->dev))) {
1353                 unsigned long flags;
1354
1355                 spin_lock_irqsave(&bp->tx_lock, flags);
1356                 if ((netif_queue_stopped(bp->dev)) &&
1357                     (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1358
1359                         netif_wake_queue(bp->dev);
1360                 }
1361                 spin_unlock_irqrestore(&bp->tx_lock, flags);
1362         }
1363 }
1364
1365 static inline void
1366 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1367         u16 cons, u16 prod)
1368 {
1369         struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1370         struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1371         struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1372         struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1373
1374         pci_dma_sync_single_for_device(bp->pdev,
1375                 pci_unmap_addr(cons_rx_buf, mapping),
1376                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1377
1378         prod_rx_buf->skb = cons_rx_buf->skb;
1379         pci_unmap_addr_set(prod_rx_buf, mapping,
1380                         pci_unmap_addr(cons_rx_buf, mapping));
1381
1382         memcpy(prod_bd, cons_bd, 8);
1383
1384         bp->rx_prod_bseq += bp->rx_buf_use_size;
1385
1386 }
1387
1388 static int
1389 bnx2_rx_int(struct bnx2 *bp, int budget)
1390 {
1391         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1392         struct l2_fhdr *rx_hdr;
1393         int rx_pkt = 0;
1394
1395         hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1396         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1397                 hw_cons++;
1398         }
1399         sw_cons = bp->rx_cons;
1400         sw_prod = bp->rx_prod;
1401
1402         /* Memory barrier necessary as speculative reads of the rx
1403          * buffer can be ahead of the index in the status block
1404          */
1405         rmb();
1406         while (sw_cons != hw_cons) {
1407                 unsigned int len;
1408                 u16 status;
1409                 struct sw_bd *rx_buf;
1410                 struct sk_buff *skb;
1411
1412                 sw_ring_cons = RX_RING_IDX(sw_cons);
1413                 sw_ring_prod = RX_RING_IDX(sw_prod);
1414
1415                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1416                 skb = rx_buf->skb;
1417                 pci_dma_sync_single_for_cpu(bp->pdev,
1418                         pci_unmap_addr(rx_buf, mapping),
1419                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1420
1421                 rx_hdr = (struct l2_fhdr *) skb->data;
1422                 len = rx_hdr->l2_fhdr_pkt_len - 4;
1423
1424                 if (rx_hdr->l2_fhdr_errors &
1425                         (L2_FHDR_ERRORS_BAD_CRC |
1426                         L2_FHDR_ERRORS_PHY_DECODE |
1427                         L2_FHDR_ERRORS_ALIGNMENT |
1428                         L2_FHDR_ERRORS_TOO_SHORT |
1429                         L2_FHDR_ERRORS_GIANT_FRAME)) {
1430
1431                         goto reuse_rx;
1432                 }
1433
1434                 /* Since we don't have a jumbo ring, copy small packets
1435                  * if mtu > 1500
1436                  */
1437                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1438                         struct sk_buff *new_skb;
1439
1440                         new_skb = dev_alloc_skb(len + 2);
1441                         if (new_skb == NULL)
1442                                 goto reuse_rx;
1443
1444                         /* aligned copy */
1445                         memcpy(new_skb->data,
1446                                 skb->data + bp->rx_offset - 2,
1447                                 len + 2);
1448
1449                         skb_reserve(new_skb, 2);
1450                         skb_put(new_skb, len);
1451                         new_skb->dev = bp->dev;
1452
1453                         bnx2_reuse_rx_skb(bp, skb,
1454                                 sw_ring_cons, sw_ring_prod);
1455
1456                         skb = new_skb;
1457                 }
1458                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1459                         pci_unmap_single(bp->pdev,
1460                                 pci_unmap_addr(rx_buf, mapping),
1461                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1462
1463                         skb_reserve(skb, bp->rx_offset);
1464                         skb_put(skb, len);
1465                 }
1466                 else {
1467 reuse_rx:
1468                         bnx2_reuse_rx_skb(bp, skb,
1469                                 sw_ring_cons, sw_ring_prod);
1470                         goto next_rx;
1471                 }
1472
1473                 skb->protocol = eth_type_trans(skb, bp->dev);
1474
1475                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1476                         (htons(skb->protocol) != 0x8100)) {
1477
1478                         dev_kfree_skb_irq(skb);
1479                         goto next_rx;
1480
1481                 }
1482
1483                 status = rx_hdr->l2_fhdr_status;
1484                 skb->ip_summed = CHECKSUM_NONE;
1485                 if (bp->rx_csum &&
1486                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1487                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
1488
1489                         u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1490
1491                         if (cksum == 0xffff)
1492                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1493                 }
1494
1495 #ifdef BCM_VLAN
1496                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1497                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1498                                 rx_hdr->l2_fhdr_vlan_tag);
1499                 }
1500                 else
1501 #endif
1502                         netif_receive_skb(skb);
1503
1504                 bp->dev->last_rx = jiffies;
1505                 rx_pkt++;
1506
1507 next_rx:
1508                 rx_buf->skb = NULL;
1509
1510                 sw_cons = NEXT_RX_BD(sw_cons);
1511                 sw_prod = NEXT_RX_BD(sw_prod);
1512
1513                 if ((rx_pkt == budget))
1514                         break;
1515         }
1516         bp->rx_cons = sw_cons;
1517         bp->rx_prod = sw_prod;
1518
1519         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1520
1521         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1522
1523         mmiowb();
1524
1525         return rx_pkt;
1526
1527 }
1528
1529 /* MSI ISR - The only difference between this and the INTx ISR
1530  * is that the MSI interrupt is always serviced.
1531  */
1532 static irqreturn_t
1533 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1534 {
1535         struct net_device *dev = dev_instance;
1536         struct bnx2 *bp = dev->priv;
1537
1538         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1539                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1540                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1541
1542         /* Return here if interrupt is disabled. */
1543         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1544                 return IRQ_RETVAL(1);
1545         }
1546
1547         if (netif_rx_schedule_prep(dev)) {
1548                 __netif_rx_schedule(dev);
1549         }
1550
1551         return IRQ_RETVAL(1);
1552 }
1553
1554 static irqreturn_t
1555 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1556 {
1557         struct net_device *dev = dev_instance;
1558         struct bnx2 *bp = dev->priv;
1559
1560         /* When using INTx, it is possible for the interrupt to arrive
1561          * at the CPU before the status block posted prior to the
1562          * interrupt. Reading a register will flush the status block.
1563          * When using MSI, the MSI message will always complete after
1564          * the status block write.
1565          */
1566         if ((bp->status_blk->status_idx == bp->last_status_idx) ||
1567             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1568              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1569                 return IRQ_RETVAL(0);
1570
1571         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1572                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1573                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1574
1575         /* Return here if interrupt is shared and is disabled. */
1576         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1577                 return IRQ_RETVAL(1);
1578         }
1579
1580         if (netif_rx_schedule_prep(dev)) {
1581                 __netif_rx_schedule(dev);
1582         }
1583
1584         return IRQ_RETVAL(1);
1585 }
1586
1587 static int
1588 bnx2_poll(struct net_device *dev, int *budget)
1589 {
1590         struct bnx2 *bp = dev->priv;
1591         int rx_done = 1;
1592
1593         bp->last_status_idx = bp->status_blk->status_idx;
1594
1595         rmb();
1596         if ((bp->status_blk->status_attn_bits &
1597                 STATUS_ATTN_BITS_LINK_STATE) !=
1598                 (bp->status_blk->status_attn_bits_ack &
1599                 STATUS_ATTN_BITS_LINK_STATE)) {
1600
1601                 unsigned long flags;
1602
1603                 spin_lock_irqsave(&bp->phy_lock, flags);
1604                 bnx2_phy_int(bp);
1605                 spin_unlock_irqrestore(&bp->phy_lock, flags);
1606         }
1607
1608         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1609                 bnx2_tx_int(bp);
1610         }
1611
1612         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1613                 int orig_budget = *budget;
1614                 int work_done;
1615
1616                 if (orig_budget > dev->quota)
1617                         orig_budget = dev->quota;
1618                 
1619                 work_done = bnx2_rx_int(bp, orig_budget);
1620                 *budget -= work_done;
1621                 dev->quota -= work_done;
1622                 
1623                 if (work_done >= orig_budget) {
1624                         rx_done = 0;
1625                 }
1626         }
1627         
1628         if (rx_done) {
1629                 netif_rx_complete(dev);
1630                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1631                         BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1632                         bp->last_status_idx);
1633                 return 0;
1634         }
1635
1636         return 1;
1637 }
1638
1639 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1640  * from set_multicast.
1641  */
1642 static void
1643 bnx2_set_rx_mode(struct net_device *dev)
1644 {
1645         struct bnx2 *bp = dev->priv;
1646         u32 rx_mode, sort_mode;
1647         int i;
1648         unsigned long flags;
1649
1650         spin_lock_irqsave(&bp->phy_lock, flags);
1651
1652         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1653                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1654         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1655 #ifdef BCM_VLAN
1656         if (!bp->vlgrp) {
1657                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1658         }
1659 #else
1660         rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1661 #endif
1662         if (dev->flags & IFF_PROMISC) {
1663                 /* Promiscuous mode. */
1664                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1665                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1666         }
1667         else if (dev->flags & IFF_ALLMULTI) {
1668                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1669                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1670                                0xffffffff);
1671                 }
1672                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1673         }
1674         else {
1675                 /* Accept one or more multicast(s). */
1676                 struct dev_mc_list *mclist;
1677                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1678                 u32 regidx;
1679                 u32 bit;
1680                 u32 crc;
1681
1682                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1683
1684                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1685                      i++, mclist = mclist->next) {
1686
1687                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1688                         bit = crc & 0xff;
1689                         regidx = (bit & 0xe0) >> 5;
1690                         bit &= 0x1f;
1691                         mc_filter[regidx] |= (1 << bit);
1692                 }
1693
1694                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1695                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1696                                mc_filter[i]);
1697                 }
1698
1699                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1700         }
1701
1702         if (rx_mode != bp->rx_mode) {
1703                 bp->rx_mode = rx_mode;
1704                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1705         }
1706
1707         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1708         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1709         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1710
1711         spin_unlock_irqrestore(&bp->phy_lock, flags);
1712 }
1713
1714 static void
1715 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1716         u32 rv2p_proc)
1717 {
1718         int i;
1719         u32 val;
1720
1721
1722         for (i = 0; i < rv2p_code_len; i += 8) {
1723                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1724                 rv2p_code++;
1725                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1726                 rv2p_code++;
1727
1728                 if (rv2p_proc == RV2P_PROC1) {
1729                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1730                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1731                 }
1732                 else {
1733                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1734                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1735                 }
1736         }
1737
1738         /* Reset the processor, un-stall is done later. */
1739         if (rv2p_proc == RV2P_PROC1) {
1740                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1741         }
1742         else {
1743                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1744         }
1745 }
1746
1747 static void
1748 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1749 {
1750         u32 offset;
1751         u32 val;
1752
1753         /* Halt the CPU. */
1754         val = REG_RD_IND(bp, cpu_reg->mode);
1755         val |= cpu_reg->mode_value_halt;
1756         REG_WR_IND(bp, cpu_reg->mode, val);
1757         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1758
1759         /* Load the Text area. */
1760         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1761         if (fw->text) {
1762                 int j;
1763
1764                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1765                         REG_WR_IND(bp, offset, fw->text[j]);
1766                 }
1767         }
1768
1769         /* Load the Data area. */
1770         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1771         if (fw->data) {
1772                 int j;
1773
1774                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1775                         REG_WR_IND(bp, offset, fw->data[j]);
1776                 }
1777         }
1778
1779         /* Load the SBSS area. */
1780         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1781         if (fw->sbss) {
1782                 int j;
1783
1784                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1785                         REG_WR_IND(bp, offset, fw->sbss[j]);
1786                 }
1787         }
1788
1789         /* Load the BSS area. */
1790         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1791         if (fw->bss) {
1792                 int j;
1793
1794                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1795                         REG_WR_IND(bp, offset, fw->bss[j]);
1796                 }
1797         }
1798
1799         /* Load the Read-Only area. */
1800         offset = cpu_reg->spad_base +
1801                 (fw->rodata_addr - cpu_reg->mips_view_base);
1802         if (fw->rodata) {
1803                 int j;
1804
1805                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1806                         REG_WR_IND(bp, offset, fw->rodata[j]);
1807                 }
1808         }
1809
1810         /* Clear the pre-fetch instruction. */
1811         REG_WR_IND(bp, cpu_reg->inst, 0);
1812         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1813
1814         /* Start the CPU. */
1815         val = REG_RD_IND(bp, cpu_reg->mode);
1816         val &= ~cpu_reg->mode_value_halt;
1817         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1818         REG_WR_IND(bp, cpu_reg->mode, val);
1819 }
1820
1821 static void
1822 bnx2_init_cpus(struct bnx2 *bp)
1823 {
1824         struct cpu_reg cpu_reg;
1825         struct fw_info fw;
1826
1827         /* Initialize the RV2P processor. */
1828         load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1829         load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1830
1831         /* Initialize the RX Processor. */
1832         cpu_reg.mode = BNX2_RXP_CPU_MODE;
1833         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1834         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1835         cpu_reg.state = BNX2_RXP_CPU_STATE;
1836         cpu_reg.state_value_clear = 0xffffff;
1837         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1838         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1839         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1840         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1841         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1842         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1843         cpu_reg.mips_view_base = 0x8000000;
1844     
1845         fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1846         fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1847         fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1848         fw.start_addr = bnx2_RXP_b06FwStartAddr;
1849
1850         fw.text_addr = bnx2_RXP_b06FwTextAddr;
1851         fw.text_len = bnx2_RXP_b06FwTextLen;
1852         fw.text_index = 0;
1853         fw.text = bnx2_RXP_b06FwText;
1854
1855         fw.data_addr = bnx2_RXP_b06FwDataAddr;
1856         fw.data_len = bnx2_RXP_b06FwDataLen;
1857         fw.data_index = 0;
1858         fw.data = bnx2_RXP_b06FwData;
1859
1860         fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1861         fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1862         fw.sbss_index = 0;
1863         fw.sbss = bnx2_RXP_b06FwSbss;
1864
1865         fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1866         fw.bss_len = bnx2_RXP_b06FwBssLen;
1867         fw.bss_index = 0;
1868         fw.bss = bnx2_RXP_b06FwBss;
1869
1870         fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1871         fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1872         fw.rodata_index = 0;
1873         fw.rodata = bnx2_RXP_b06FwRodata;
1874
1875         load_cpu_fw(bp, &cpu_reg, &fw);
1876
1877         /* Initialize the TX Processor. */
1878         cpu_reg.mode = BNX2_TXP_CPU_MODE;
1879         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1880         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1881         cpu_reg.state = BNX2_TXP_CPU_STATE;
1882         cpu_reg.state_value_clear = 0xffffff;
1883         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1884         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1885         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1886         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1887         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1888         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1889         cpu_reg.mips_view_base = 0x8000000;
1890     
1891         fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1892         fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1893         fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1894         fw.start_addr = bnx2_TXP_b06FwStartAddr;
1895
1896         fw.text_addr = bnx2_TXP_b06FwTextAddr;
1897         fw.text_len = bnx2_TXP_b06FwTextLen;
1898         fw.text_index = 0;
1899         fw.text = bnx2_TXP_b06FwText;
1900
1901         fw.data_addr = bnx2_TXP_b06FwDataAddr;
1902         fw.data_len = bnx2_TXP_b06FwDataLen;
1903         fw.data_index = 0;
1904         fw.data = bnx2_TXP_b06FwData;
1905
1906         fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1907         fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1908         fw.sbss_index = 0;
1909         fw.sbss = bnx2_TXP_b06FwSbss;
1910
1911         fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1912         fw.bss_len = bnx2_TXP_b06FwBssLen;
1913         fw.bss_index = 0;
1914         fw.bss = bnx2_TXP_b06FwBss;
1915
1916         fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1917         fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1918         fw.rodata_index = 0;
1919         fw.rodata = bnx2_TXP_b06FwRodata;
1920
1921         load_cpu_fw(bp, &cpu_reg, &fw);
1922
1923         /* Initialize the TX Patch-up Processor. */
1924         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1925         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1926         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1927         cpu_reg.state = BNX2_TPAT_CPU_STATE;
1928         cpu_reg.state_value_clear = 0xffffff;
1929         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1930         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1931         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1932         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1933         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1934         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1935         cpu_reg.mips_view_base = 0x8000000;
1936     
1937         fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1938         fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1939         fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1940         fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1941
1942         fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1943         fw.text_len = bnx2_TPAT_b06FwTextLen;
1944         fw.text_index = 0;
1945         fw.text = bnx2_TPAT_b06FwText;
1946
1947         fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1948         fw.data_len = bnx2_TPAT_b06FwDataLen;
1949         fw.data_index = 0;
1950         fw.data = bnx2_TPAT_b06FwData;
1951
1952         fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1953         fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1954         fw.sbss_index = 0;
1955         fw.sbss = bnx2_TPAT_b06FwSbss;
1956
1957         fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1958         fw.bss_len = bnx2_TPAT_b06FwBssLen;
1959         fw.bss_index = 0;
1960         fw.bss = bnx2_TPAT_b06FwBss;
1961
1962         fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1963         fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1964         fw.rodata_index = 0;
1965         fw.rodata = bnx2_TPAT_b06FwRodata;
1966
1967         load_cpu_fw(bp, &cpu_reg, &fw);
1968
1969         /* Initialize the Completion Processor. */
1970         cpu_reg.mode = BNX2_COM_CPU_MODE;
1971         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1972         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1973         cpu_reg.state = BNX2_COM_CPU_STATE;
1974         cpu_reg.state_value_clear = 0xffffff;
1975         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1976         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1977         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1978         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1979         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1980         cpu_reg.spad_base = BNX2_COM_SCRATCH;
1981         cpu_reg.mips_view_base = 0x8000000;
1982     
1983         fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1984         fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1985         fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1986         fw.start_addr = bnx2_COM_b06FwStartAddr;
1987
1988         fw.text_addr = bnx2_COM_b06FwTextAddr;
1989         fw.text_len = bnx2_COM_b06FwTextLen;
1990         fw.text_index = 0;
1991         fw.text = bnx2_COM_b06FwText;
1992
1993         fw.data_addr = bnx2_COM_b06FwDataAddr;
1994         fw.data_len = bnx2_COM_b06FwDataLen;
1995         fw.data_index = 0;
1996         fw.data = bnx2_COM_b06FwData;
1997
1998         fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1999         fw.sbss_len = bnx2_COM_b06FwSbssLen;
2000         fw.sbss_index = 0;
2001         fw.sbss = bnx2_COM_b06FwSbss;
2002
2003         fw.bss_addr = bnx2_COM_b06FwBssAddr;
2004         fw.bss_len = bnx2_COM_b06FwBssLen;
2005         fw.bss_index = 0;
2006         fw.bss = bnx2_COM_b06FwBss;
2007
2008         fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2009         fw.rodata_len = bnx2_COM_b06FwRodataLen;
2010         fw.rodata_index = 0;
2011         fw.rodata = bnx2_COM_b06FwRodata;
2012
2013         load_cpu_fw(bp, &cpu_reg, &fw);
2014
2015 }
2016
2017 static int
2018 bnx2_set_power_state(struct bnx2 *bp, int state)
2019 {
2020         u16 pmcsr;
2021
2022         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2023
2024         switch (state) {
2025         case 0: {
2026                 u32 val;
2027
2028                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2029                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2030                         PCI_PM_CTRL_PME_STATUS);
2031
2032                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2033                         /* delay required during transition out of D3hot */
2034                         msleep(20);
2035
2036                 val = REG_RD(bp, BNX2_EMAC_MODE);
2037                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2038                 val &= ~BNX2_EMAC_MODE_MPKT;
2039                 REG_WR(bp, BNX2_EMAC_MODE, val);
2040
2041                 val = REG_RD(bp, BNX2_RPM_CONFIG);
2042                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2043                 REG_WR(bp, BNX2_RPM_CONFIG, val);
2044                 break;
2045         }
2046         case 3: {
2047                 int i;
2048                 u32 val, wol_msg;
2049
2050                 if (bp->wol) {
2051                         u32 advertising;
2052                         u8 autoneg;
2053
2054                         autoneg = bp->autoneg;
2055                         advertising = bp->advertising;
2056
2057                         bp->autoneg = AUTONEG_SPEED;
2058                         bp->advertising = ADVERTISED_10baseT_Half |
2059                                 ADVERTISED_10baseT_Full |
2060                                 ADVERTISED_100baseT_Half |
2061                                 ADVERTISED_100baseT_Full |
2062                                 ADVERTISED_Autoneg;
2063
2064                         bnx2_setup_copper_phy(bp);
2065
2066                         bp->autoneg = autoneg;
2067                         bp->advertising = advertising;
2068
2069                         bnx2_set_mac_addr(bp);
2070
2071                         val = REG_RD(bp, BNX2_EMAC_MODE);
2072
2073                         /* Enable port mode. */
2074                         val &= ~BNX2_EMAC_MODE_PORT;
2075                         val |= BNX2_EMAC_MODE_PORT_MII |
2076                                BNX2_EMAC_MODE_MPKT_RCVD |
2077                                BNX2_EMAC_MODE_ACPI_RCVD |
2078                                BNX2_EMAC_MODE_FORCE_LINK |
2079                                BNX2_EMAC_MODE_MPKT;
2080
2081                         REG_WR(bp, BNX2_EMAC_MODE, val);
2082
2083                         /* receive all multicast */
2084                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2085                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2086                                        0xffffffff);
2087                         }
2088                         REG_WR(bp, BNX2_EMAC_RX_MODE,
2089                                BNX2_EMAC_RX_MODE_SORT_MODE);
2090
2091                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2092                               BNX2_RPM_SORT_USER0_MC_EN;
2093                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2094                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2095                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2096                                BNX2_RPM_SORT_USER0_ENA);
2097
2098                         /* Need to enable EMAC and RPM for WOL. */
2099                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2100                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2101                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2102                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2103
2104                         val = REG_RD(bp, BNX2_RPM_CONFIG);
2105                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2106                         REG_WR(bp, BNX2_RPM_CONFIG, val);
2107
2108                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2109                 }
2110                 else {
2111                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2112                 }
2113
2114                 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2115
2116                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2117                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2118                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2119
2120                         if (bp->wol)
2121                                 pmcsr |= 3;
2122                 }
2123                 else {
2124                         pmcsr |= 3;
2125                 }
2126                 if (bp->wol) {
2127                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2128                 }
2129                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2130                                       pmcsr);
2131
2132                 /* No more memory access after this point until
2133                  * device is brought back to D0.
2134                  */
2135                 udelay(50);
2136                 break;
2137         }
2138         default:
2139                 return -EINVAL;
2140         }
2141         return 0;
2142 }
2143
2144 static int
2145 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2146 {
2147         u32 val;
2148         int j;
2149
2150         /* Request access to the flash interface. */
2151         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2152         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2153                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2154                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2155                         break;
2156
2157                 udelay(5);
2158         }
2159
2160         if (j >= NVRAM_TIMEOUT_COUNT)
2161                 return -EBUSY;
2162
2163         return 0;
2164 }
2165
2166 static int
2167 bnx2_release_nvram_lock(struct bnx2 *bp)
2168 {
2169         int j;
2170         u32 val;
2171
2172         /* Relinquish nvram interface. */
2173         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2174
2175         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2176                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2177                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2178                         break;
2179
2180                 udelay(5);
2181         }
2182
2183         if (j >= NVRAM_TIMEOUT_COUNT)
2184                 return -EBUSY;
2185
2186         return 0;
2187 }
2188
2189
2190 static int
2191 bnx2_enable_nvram_write(struct bnx2 *bp)
2192 {
2193         u32 val;
2194
2195         val = REG_RD(bp, BNX2_MISC_CFG);
2196         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2197
2198         if (!bp->flash_info->buffered) {
2199                 int j;
2200
2201                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2202                 REG_WR(bp, BNX2_NVM_COMMAND,
2203                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2204
2205                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2206                         udelay(5);
2207
2208                         val = REG_RD(bp, BNX2_NVM_COMMAND);
2209                         if (val & BNX2_NVM_COMMAND_DONE)
2210                                 break;
2211                 }
2212
2213                 if (j >= NVRAM_TIMEOUT_COUNT)
2214                         return -EBUSY;
2215         }
2216         return 0;
2217 }
2218
2219 static void
2220 bnx2_disable_nvram_write(struct bnx2 *bp)
2221 {
2222         u32 val;
2223
2224         val = REG_RD(bp, BNX2_MISC_CFG);
2225         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2226 }
2227
2228
2229 static void
2230 bnx2_enable_nvram_access(struct bnx2 *bp)
2231 {
2232         u32 val;
2233
2234         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2235         /* Enable both bits, even on read. */
2236         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
2237                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2238 }
2239
2240 static void
2241 bnx2_disable_nvram_access(struct bnx2 *bp)
2242 {
2243         u32 val;
2244
2245         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2246         /* Disable both bits, even after read. */
2247         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
2248                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2249                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
2250 }
2251
2252 static int
2253 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2254 {
2255         u32 cmd;
2256         int j;
2257
2258         if (bp->flash_info->buffered)
2259                 /* Buffered flash, no erase needed */
2260                 return 0;
2261
2262         /* Build an erase command */
2263         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2264               BNX2_NVM_COMMAND_DOIT;
2265
2266         /* Need to clear DONE bit separately. */
2267         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2268
2269         /* Address of the NVRAM to read from. */
2270         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2271
2272         /* Issue an erase command. */
2273         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2274
2275         /* Wait for completion. */
2276         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2277                 u32 val;
2278
2279                 udelay(5);
2280
2281                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2282                 if (val & BNX2_NVM_COMMAND_DONE)
2283                         break;
2284         }
2285
2286         if (j >= NVRAM_TIMEOUT_COUNT)
2287                 return -EBUSY;
2288
2289         return 0;
2290 }
2291
2292 static int
2293 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2294 {
2295         u32 cmd;
2296         int j;
2297
2298         /* Build the command word. */
2299         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2300
2301         /* Calculate an offset of a buffered flash. */
2302         if (bp->flash_info->buffered) {
2303                 offset = ((offset / bp->flash_info->page_size) <<
2304                            bp->flash_info->page_bits) +
2305                           (offset % bp->flash_info->page_size);
2306         }
2307
2308         /* Need to clear DONE bit separately. */
2309         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2310
2311         /* Address of the NVRAM to read from. */
2312         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2313
2314         /* Issue a read command. */
2315         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2316
2317         /* Wait for completion. */
2318         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2319                 u32 val;
2320
2321                 udelay(5);
2322
2323                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2324                 if (val & BNX2_NVM_COMMAND_DONE) {
2325                         val = REG_RD(bp, BNX2_NVM_READ);
2326
2327                         val = be32_to_cpu(val);
2328                         memcpy(ret_val, &val, 4);
2329                         break;
2330                 }
2331         }
2332         if (j >= NVRAM_TIMEOUT_COUNT)
2333                 return -EBUSY;
2334
2335         return 0;
2336 }
2337
2338
2339 static int
2340 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2341 {
2342         u32 cmd, val32;
2343         int j;
2344
2345         /* Build the command word. */
2346         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2347
2348         /* Calculate an offset of a buffered flash. */
2349         if (bp->flash_info->buffered) {
2350                 offset = ((offset / bp->flash_info->page_size) <<
2351                           bp->flash_info->page_bits) +
2352                          (offset % bp->flash_info->page_size);
2353         }
2354
2355         /* Need to clear DONE bit separately. */
2356         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2357
2358         memcpy(&val32, val, 4);
2359         val32 = cpu_to_be32(val32);
2360
2361         /* Write the data. */
2362         REG_WR(bp, BNX2_NVM_WRITE, val32);
2363
2364         /* Address of the NVRAM to write to. */
2365         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2366
2367         /* Issue the write command. */
2368         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2369
2370         /* Wait for completion. */
2371         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2372                 udelay(5);
2373
2374                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2375                         break;
2376         }
2377         if (j >= NVRAM_TIMEOUT_COUNT)
2378                 return -EBUSY;
2379
2380         return 0;
2381 }
2382
2383 static int
2384 bnx2_init_nvram(struct bnx2 *bp)
2385 {
2386         u32 val;
2387         int j, entry_count, rc;
2388         struct flash_spec *flash;
2389
2390         /* Determine the selected interface. */
2391         val = REG_RD(bp, BNX2_NVM_CFG1);
2392
2393         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2394
2395         rc = 0;
2396         if (val & 0x40000000) {
2397
2398                 /* Flash interface has been reconfigured */
2399                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2400                         j++, flash++) {
2401
2402                         if (val == flash->config1) {
2403                                 bp->flash_info = flash;
2404                                 break;
2405                         }
2406                 }
2407         }
2408         else {
2409                 /* Not yet been reconfigured */
2410
2411                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2412                         j++, flash++) {
2413
2414                         if ((val & FLASH_STRAP_MASK) == flash->strapping) {
2415                                 bp->flash_info = flash;
2416
2417                                 /* Request access to the flash interface. */
2418                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2419                                         return rc;
2420
2421                                 /* Enable access to flash interface */
2422                                 bnx2_enable_nvram_access(bp);
2423
2424                                 /* Reconfigure the flash interface */
2425                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2426                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2427                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2428                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2429
2430                                 /* Disable access to flash interface */
2431                                 bnx2_disable_nvram_access(bp);
2432                                 bnx2_release_nvram_lock(bp);
2433
2434                                 break;
2435                         }
2436                 }
2437         } /* if (val & 0x40000000) */
2438
2439         if (j == entry_count) {
2440                 bp->flash_info = NULL;
2441                 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2442                 rc = -ENODEV;
2443         }
2444
2445         return rc;
2446 }
2447
2448 static int
2449 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2450                 int buf_size)
2451 {
2452         int rc = 0;
2453         u32 cmd_flags, offset32, len32, extra;
2454
2455         if (buf_size == 0)
2456                 return 0;
2457
2458         /* Request access to the flash interface. */
2459         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2460                 return rc;
2461
2462         /* Enable access to flash interface */
2463         bnx2_enable_nvram_access(bp);
2464
2465         len32 = buf_size;
2466         offset32 = offset;
2467         extra = 0;
2468
2469         cmd_flags = 0;
2470
2471         if (offset32 & 3) {
2472                 u8 buf[4];
2473                 u32 pre_len;
2474
2475                 offset32 &= ~3;
2476                 pre_len = 4 - (offset & 3);
2477
2478                 if (pre_len >= len32) {
2479                         pre_len = len32;
2480                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2481                                     BNX2_NVM_COMMAND_LAST;
2482                 }
2483                 else {
2484                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2485                 }
2486
2487                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2488
2489                 if (rc)
2490                         return rc;
2491
2492                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2493
2494                 offset32 += 4;
2495                 ret_buf += pre_len;
2496                 len32 -= pre_len;
2497         }
2498         if (len32 & 3) {
2499                 extra = 4 - (len32 & 3);
2500                 len32 = (len32 + 4) & ~3;
2501         }
2502
2503         if (len32 == 4) {
2504                 u8 buf[4];
2505
2506                 if (cmd_flags)
2507                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2508                 else
2509                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2510                                     BNX2_NVM_COMMAND_LAST;
2511
2512                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2513
2514                 memcpy(ret_buf, buf, 4 - extra);
2515         }
2516         else if (len32 > 0) {
2517                 u8 buf[4];
2518
2519                 /* Read the first word. */
2520                 if (cmd_flags)
2521                         cmd_flags = 0;
2522                 else
2523                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2524
2525                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2526
2527                 /* Advance to the next dword. */
2528                 offset32 += 4;
2529                 ret_buf += 4;
2530                 len32 -= 4;
2531
2532                 while (len32 > 4 && rc == 0) {
2533                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2534
2535                         /* Advance to the next dword. */
2536                         offset32 += 4;
2537                         ret_buf += 4;
2538                         len32 -= 4;
2539                 }
2540
2541                 if (rc)
2542                         return rc;
2543
2544                 cmd_flags = BNX2_NVM_COMMAND_LAST;
2545                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2546
2547                 memcpy(ret_buf, buf, 4 - extra);
2548         }
2549
2550         /* Disable access to flash interface */
2551         bnx2_disable_nvram_access(bp);
2552
2553         bnx2_release_nvram_lock(bp);
2554
2555         return rc;
2556 }
2557
2558 static int
2559 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2560                 int buf_size)
2561 {
2562         u32 written, offset32, len32;
2563         u8 *buf, start[4], end[4];
2564         int rc = 0;
2565         int align_start, align_end;
2566
2567         buf = data_buf;
2568         offset32 = offset;
2569         len32 = buf_size;
2570         align_start = align_end = 0;
2571
2572         if ((align_start = (offset32 & 3))) {
2573                 offset32 &= ~3;
2574                 len32 += align_start;
2575                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2576                         return rc;
2577         }
2578
2579         if (len32 & 3) {
2580                 if ((len32 > 4) || !align_start) {
2581                         align_end = 4 - (len32 & 3);
2582                         len32 += align_end;
2583                         if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2584                                 end, 4))) {
2585                                 return rc;
2586                         }
2587                 }
2588         }
2589
2590         if (align_start || align_end) {
2591                 buf = kmalloc(len32, GFP_KERNEL);
2592                 if (buf == 0)
2593                         return -ENOMEM;
2594                 if (align_start) {
2595                         memcpy(buf, start, 4);
2596                 }
2597                 if (align_end) {
2598                         memcpy(buf + len32 - 4, end, 4);
2599                 }
2600                 memcpy(buf + align_start, data_buf, buf_size);
2601         }
2602
2603         written = 0;
2604         while ((written < len32) && (rc == 0)) {
2605                 u32 page_start, page_end, data_start, data_end;
2606                 u32 addr, cmd_flags;
2607                 int i;
2608                 u8 flash_buffer[264];
2609
2610                 /* Find the page_start addr */
2611                 page_start = offset32 + written;
2612                 page_start -= (page_start % bp->flash_info->page_size);
2613                 /* Find the page_end addr */
2614                 page_end = page_start + bp->flash_info->page_size;
2615                 /* Find the data_start addr */
2616                 data_start = (written == 0) ? offset32 : page_start;
2617                 /* Find the data_end addr */
2618                 data_end = (page_end > offset32 + len32) ? 
2619                         (offset32 + len32) : page_end;
2620
2621                 /* Request access to the flash interface. */
2622                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2623                         goto nvram_write_end;
2624
2625                 /* Enable access to flash interface */
2626                 bnx2_enable_nvram_access(bp);
2627
2628                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2629                 if (bp->flash_info->buffered == 0) {
2630                         int j;
2631
2632                         /* Read the whole page into the buffer
2633                          * (non-buffer flash only) */
2634                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
2635                                 if (j == (bp->flash_info->page_size - 4)) {
2636                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
2637                                 }
2638                                 rc = bnx2_nvram_read_dword(bp,
2639                                         page_start + j, 
2640                                         &flash_buffer[j], 
2641                                         cmd_flags);
2642
2643                                 if (rc)
2644                                         goto nvram_write_end;
2645
2646                                 cmd_flags = 0;
2647                         }
2648                 }
2649
2650                 /* Enable writes to flash interface (unlock write-protect) */
2651                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2652                         goto nvram_write_end;
2653
2654                 /* Erase the page */
2655                 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2656                         goto nvram_write_end;
2657
2658                 /* Re-enable the write again for the actual write */
2659                 bnx2_enable_nvram_write(bp);
2660
2661                 /* Loop to write back the buffer data from page_start to
2662                  * data_start */
2663                 i = 0;
2664                 if (bp->flash_info->buffered == 0) {
2665                         for (addr = page_start; addr < data_start;
2666                                 addr += 4, i += 4) {
2667                                 
2668                                 rc = bnx2_nvram_write_dword(bp, addr,
2669                                         &flash_buffer[i], cmd_flags);
2670
2671                                 if (rc != 0)
2672                                         goto nvram_write_end;
2673
2674                                 cmd_flags = 0;
2675                         }
2676                 }
2677
2678                 /* Loop to write the new data from data_start to data_end */
2679                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2680                         if ((addr == page_end - 4) ||
2681                                 ((bp->flash_info->buffered) &&
2682                                  (addr == data_end - 4))) {
2683
2684                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2685                         }
2686                         rc = bnx2_nvram_write_dword(bp, addr, buf,
2687                                 cmd_flags);
2688
2689                         if (rc != 0)
2690                                 goto nvram_write_end;
2691
2692                         cmd_flags = 0;
2693                         buf += 4;
2694                 }
2695
2696                 /* Loop to write back the buffer data from data_end
2697                  * to page_end */
2698                 if (bp->flash_info->buffered == 0) {
2699                         for (addr = data_end; addr < page_end;
2700                                 addr += 4, i += 4) {
2701                         
2702                                 if (addr == page_end-4) {
2703                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2704                                 }
2705                                 rc = bnx2_nvram_write_dword(bp, addr,
2706                                         &flash_buffer[i], cmd_flags);
2707
2708                                 if (rc != 0)
2709                                         goto nvram_write_end;
2710
2711                                 cmd_flags = 0;
2712                         }
2713                 }
2714
2715                 /* Disable writes to flash interface (lock write-protect) */
2716                 bnx2_disable_nvram_write(bp);
2717
2718                 /* Disable access to flash interface */
2719                 bnx2_disable_nvram_access(bp);
2720                 bnx2_release_nvram_lock(bp);
2721
2722                 /* Increment written */
2723                 written += data_end - data_start;
2724         }
2725
2726 nvram_write_end:
2727         if (align_start || align_end)
2728                 kfree(buf);
2729         return rc;
2730 }
2731
2732 static int
2733 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2734 {
2735         u32 val;
2736         int i, rc = 0;
2737
2738         /* Wait for the current PCI transaction to complete before
2739          * issuing a reset. */
2740         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2741                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2742                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2743                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2744                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2745         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2746         udelay(5);
2747
2748         /* Deposit a driver reset signature so the firmware knows that
2749          * this is a soft reset. */
2750         REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2751                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
2752
2753         bp->fw_timed_out = 0;
2754
2755         /* Wait for the firmware to tell us it is ok to issue a reset. */
2756         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2757
2758         /* Do a dummy read to force the chip to complete all current transaction
2759          * before we issue a reset. */
2760         val = REG_RD(bp, BNX2_MISC_ID);
2761
2762         val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2763               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2764               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2765
2766         /* Chip reset. */
2767         REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2768
2769         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2770             (CHIP_ID(bp) == CHIP_ID_5706_A1))
2771                 msleep(15);
2772
2773         /* Reset takes approximate 30 usec */
2774         for (i = 0; i < 10; i++) {
2775                 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2776                 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2777                             BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2778                         break;
2779                 }
2780                 udelay(10);
2781         }
2782
2783         if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2784                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2785                 printk(KERN_ERR PFX "Chip reset did not complete\n");
2786                 return -EBUSY;
2787         }
2788
2789         /* Make sure byte swapping is properly configured. */
2790         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2791         if (val != 0x01020304) {
2792                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2793                 return -ENODEV;
2794         }
2795
2796         bp->fw_timed_out = 0;
2797
2798         /* Wait for the firmware to finish its initialization. */
2799         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2800
2801         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2802                 /* Adjust the voltage regular to two steps lower.  The default
2803                  * of this register is 0x0000000e. */
2804                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2805
2806                 /* Remove bad rbuf memory from the free pool. */
2807                 rc = bnx2_alloc_bad_rbuf(bp);
2808         }
2809
2810         return rc;
2811 }
2812
2813 static int
2814 bnx2_init_chip(struct bnx2 *bp)
2815 {
2816         u32 val;
2817
2818         /* Make sure the interrupt is not active. */
2819         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2820
2821         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
2822               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
2823 #ifdef __BIG_ENDIAN
2824               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | 
2825 #endif
2826               BNX2_DMA_CONFIG_CNTL_WORD_SWAP | 
2827               DMA_READ_CHANS << 12 |
2828               DMA_WRITE_CHANS << 16;
2829
2830         val |= (0x2 << 20) | (1 << 11);
2831
2832         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
2833                 val |= (1 << 23);
2834
2835         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
2836             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
2837                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
2838
2839         REG_WR(bp, BNX2_DMA_CONFIG, val);
2840
2841         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2842                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
2843                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
2844                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
2845         }
2846
2847         if (bp->flags & PCIX_FLAG) {
2848                 u16 val16;
2849
2850                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2851                                      &val16);
2852                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2853                                       val16 & ~PCI_X_CMD_ERO);
2854         }
2855
2856         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2857                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2858                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2859                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2860
2861         /* Initialize context mapping and zero out the quick contexts.  The
2862          * context block must have already been enabled. */
2863         bnx2_init_context(bp);
2864
2865         bnx2_init_cpus(bp);
2866         bnx2_init_nvram(bp);
2867
2868         bnx2_set_mac_addr(bp);
2869
2870         val = REG_RD(bp, BNX2_MQ_CONFIG);
2871         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
2872         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
2873         REG_WR(bp, BNX2_MQ_CONFIG, val);
2874
2875         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
2876         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
2877         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
2878
2879         val = (BCM_PAGE_BITS - 8) << 24;
2880         REG_WR(bp, BNX2_RV2P_CONFIG, val);
2881
2882         /* Configure page size. */
2883         val = REG_RD(bp, BNX2_TBDR_CONFIG);
2884         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2885         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
2886         REG_WR(bp, BNX2_TBDR_CONFIG, val);
2887
2888         val = bp->mac_addr[0] +
2889               (bp->mac_addr[1] << 8) +
2890               (bp->mac_addr[2] << 16) +
2891               bp->mac_addr[3] +
2892               (bp->mac_addr[4] << 8) +
2893               (bp->mac_addr[5] << 16);
2894         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
2895
2896         /* Program the MTU.  Also include 4 bytes for CRC32. */
2897         val = bp->dev->mtu + ETH_HLEN + 4;
2898         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
2899                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
2900         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
2901
2902         bp->last_status_idx = 0;
2903         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
2904
2905         /* Set up how to generate a link change interrupt. */
2906         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2907
2908         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
2909                (u64) bp->status_blk_mapping & 0xffffffff);
2910         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
2911
2912         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
2913                (u64) bp->stats_blk_mapping & 0xffffffff);
2914         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
2915                (u64) bp->stats_blk_mapping >> 32);
2916
2917         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, 
2918                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
2919
2920         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
2921                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
2922
2923         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
2924                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
2925
2926         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
2927
2928         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
2929
2930         REG_WR(bp, BNX2_HC_COM_TICKS,
2931                (bp->com_ticks_int << 16) | bp->com_ticks);
2932
2933         REG_WR(bp, BNX2_HC_CMD_TICKS,
2934                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
2935
2936         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
2937         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
2938
2939         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
2940                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
2941         else {
2942                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
2943                        BNX2_HC_CONFIG_TX_TMR_MODE |
2944                        BNX2_HC_CONFIG_COLLECT_STATS);
2945         }
2946
2947         /* Clear internal stats counters. */
2948         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
2949
2950         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
2951
2952         /* Initialize the receive filter. */
2953         bnx2_set_rx_mode(bp->dev);
2954
2955         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
2956
2957         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
2958         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
2959
2960         udelay(20);
2961
2962         return 0;
2963 }
2964
2965
2966 static void
2967 bnx2_init_tx_ring(struct bnx2 *bp)
2968 {
2969         struct tx_bd *txbd;
2970         u32 val;
2971
2972         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2973                 
2974         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
2975         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
2976
2977         bp->tx_prod = 0;
2978         bp->tx_cons = 0;
2979         bp->tx_prod_bseq = 0;
2980         
2981         val = BNX2_L2CTX_TYPE_TYPE_L2;
2982         val |= BNX2_L2CTX_TYPE_SIZE_L2;
2983         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2984
2985         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2986         val |= 8 << 16;
2987         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2988
2989         val = (u64) bp->tx_desc_mapping >> 32;
2990         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
2991
2992         val = (u64) bp->tx_desc_mapping & 0xffffffff;
2993         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2994 }
2995
2996 static void
2997 bnx2_init_rx_ring(struct bnx2 *bp)
2998 {
2999         struct rx_bd *rxbd;
3000         int i;
3001         u16 prod, ring_prod; 
3002         u32 val;
3003
3004         /* 8 for CRC and VLAN */
3005         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3006         /* 8 for alignment */
3007         bp->rx_buf_size = bp->rx_buf_use_size + 8;
3008
3009         ring_prod = prod = bp->rx_prod = 0;
3010         bp->rx_cons = 0;
3011         bp->rx_prod_bseq = 0;
3012                 
3013         rxbd = &bp->rx_desc_ring[0];
3014         for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3015                 rxbd->rx_bd_len = bp->rx_buf_use_size;
3016                 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3017         }
3018
3019         rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3020         rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3021
3022         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3023         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3024         val |= 0x02 << 8;
3025         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3026
3027         val = (u64) bp->rx_desc_mapping >> 32;
3028         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3029
3030         val = (u64) bp->rx_desc_mapping & 0xffffffff;
3031         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3032
3033         for ( ;ring_prod < bp->rx_ring_size; ) {
3034                 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3035                         break;
3036                 }
3037                 prod = NEXT_RX_BD(prod);
3038                 ring_prod = RX_RING_IDX(prod);
3039         }
3040         bp->rx_prod = prod;
3041
3042         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3043
3044         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3045 }
3046
3047 static void
3048 bnx2_free_tx_skbs(struct bnx2 *bp)
3049 {
3050         int i;
3051
3052         if (bp->tx_buf_ring == NULL)
3053                 return;
3054
3055         for (i = 0; i < TX_DESC_CNT; ) {
3056                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3057                 struct sk_buff *skb = tx_buf->skb;
3058                 int j, last;
3059
3060                 if (skb == NULL) {
3061                         i++;
3062                         continue;
3063                 }
3064
3065                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3066                         skb_headlen(skb), PCI_DMA_TODEVICE);
3067
3068                 tx_buf->skb = NULL;
3069
3070                 last = skb_shinfo(skb)->nr_frags;
3071                 for (j = 0; j < last; j++) {
3072                         tx_buf = &bp->tx_buf_ring[i + j + 1];
3073                         pci_unmap_page(bp->pdev,
3074                                 pci_unmap_addr(tx_buf, mapping),
3075                                 skb_shinfo(skb)->frags[j].size,
3076                                 PCI_DMA_TODEVICE);
3077                 }
3078                 dev_kfree_skb_any(skb);
3079                 i += j + 1;
3080         }
3081
3082 }
3083
3084 static void
3085 bnx2_free_rx_skbs(struct bnx2 *bp)
3086 {
3087         int i;
3088
3089         if (bp->rx_buf_ring == NULL)
3090                 return;
3091
3092         for (i = 0; i < RX_DESC_CNT; i++) {
3093                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3094                 struct sk_buff *skb = rx_buf->skb;
3095
3096                 if (skb == 0)
3097                         continue;
3098
3099                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3100                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3101
3102                 rx_buf->skb = NULL;
3103
3104                 dev_kfree_skb_any(skb);
3105         }
3106 }
3107
3108 static void
3109 bnx2_free_skbs(struct bnx2 *bp)
3110 {
3111         bnx2_free_tx_skbs(bp);
3112         bnx2_free_rx_skbs(bp);
3113 }
3114
3115 static int
3116 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3117 {
3118         int rc;
3119
3120         rc = bnx2_reset_chip(bp, reset_code);
3121         bnx2_free_skbs(bp);
3122         if (rc)
3123                 return rc;
3124
3125         bnx2_init_chip(bp);
3126         bnx2_init_tx_ring(bp);
3127         bnx2_init_rx_ring(bp);
3128         return 0;
3129 }
3130
3131 static int
3132 bnx2_init_nic(struct bnx2 *bp)
3133 {
3134         int rc;
3135
3136         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3137                 return rc;
3138
3139         bnx2_init_phy(bp);
3140         bnx2_set_link(bp);
3141         return 0;
3142 }
3143
3144 static int
3145 bnx2_test_registers(struct bnx2 *bp)
3146 {
3147         int ret;
3148         int i;
3149         static struct {
3150                 u16   offset;
3151                 u16   flags;
3152                 u32   rw_mask;
3153                 u32   ro_mask;
3154         } reg_tbl[] = {
3155                 { 0x006c, 0, 0x00000000, 0x0000003f },
3156                 { 0x0090, 0, 0xffffffff, 0x00000000 },
3157                 { 0x0094, 0, 0x00000000, 0x00000000 },
3158
3159                 { 0x0404, 0, 0x00003f00, 0x00000000 },
3160                 { 0x0418, 0, 0x00000000, 0xffffffff },
3161                 { 0x041c, 0, 0x00000000, 0xffffffff },
3162                 { 0x0420, 0, 0x00000000, 0x80ffffff },
3163                 { 0x0424, 0, 0x00000000, 0x00000000 },
3164                 { 0x0428, 0, 0x00000000, 0x00000001 },
3165                 { 0x0450, 0, 0x00000000, 0x0000ffff },
3166                 { 0x0454, 0, 0x00000000, 0xffffffff },
3167                 { 0x0458, 0, 0x00000000, 0xffffffff },
3168
3169                 { 0x0808, 0, 0x00000000, 0xffffffff },
3170                 { 0x0854, 0, 0x00000000, 0xffffffff },
3171                 { 0x0868, 0, 0x00000000, 0x77777777 },
3172                 { 0x086c, 0, 0x00000000, 0x77777777 },
3173                 { 0x0870, 0, 0x00000000, 0x77777777 },
3174                 { 0x0874, 0, 0x00000000, 0x77777777 },
3175
3176                 { 0x0c00, 0, 0x00000000, 0x00000001 },
3177                 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3178                 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3179                 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3180                 { 0x0c30, 0, 0x00000000, 0xffffffff },
3181                 { 0x0c34, 0, 0x00000000, 0xffffffff },
3182                 { 0x0c38, 0, 0x00000000, 0xffffffff },
3183                 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3184                 { 0x0c40, 0, 0x00000000, 0xffffffff },
3185                 { 0x0c44, 0, 0x00000000, 0xffffffff },
3186                 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3187                 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3188                 { 0x0c50, 0, 0x00000000, 0xffffffff },
3189                 { 0x0c54, 0, 0x00000000, 0xffffffff },
3190                 { 0x0c58, 0, 0x00000000, 0xffffffff },
3191                 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3192                 { 0x0c60, 0, 0x00000000, 0xffffffff },
3193                 { 0x0c64, 0, 0x00000000, 0xffffffff },
3194                 { 0x0c68, 0, 0x00000000, 0xffffffff },
3195                 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3196                 { 0x0c70, 0, 0x00000000, 0xffffffff },
3197                 { 0x0c74, 0, 0x00000000, 0xffffffff },
3198                 { 0x0c78, 0, 0x00000000, 0xffffffff },
3199                 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3200                 { 0x0c80, 0, 0x00000000, 0xffffffff },
3201                 { 0x0c84, 0, 0x00000000, 0xffffffff },
3202                 { 0x0c88, 0, 0x00000000, 0xffffffff },
3203                 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3204                 { 0x0c90, 0, 0x00000000, 0xffffffff },
3205                 { 0x0c94, 0, 0x00000000, 0xffffffff },
3206                 { 0x0c98, 0, 0x00000000, 0xffffffff },
3207                 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3208                 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3209                 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3210                 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3211                 { 0x0cac, 0, 0x00000000, 0xffffffff },
3212                 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3213                 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3214                 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3215                 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3216                 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3217                 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3218                 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3219                 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3220                 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3221                 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3222                 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3223                 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3224                 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3225                 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3226                 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3227                 { 0x0cec, 0, 0x00000000, 0xffffffff },
3228                 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3229                 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3230                 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3231                 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3232                 { 0x0d00, 0, 0x00000000, 0xffffffff },
3233                 { 0x0d04, 0, 0x00000000, 0xffffffff },
3234
3235                 { 0x1000, 0, 0x00000000, 0x00000001 },
3236                 { 0x1004, 0, 0x00000000, 0x000f0001 },
3237                 { 0x1044, 0, 0x00000000, 0xffc003ff },
3238                 { 0x1080, 0, 0x00000000, 0x0001ffff },
3239                 { 0x1084, 0, 0x00000000, 0xffffffff },
3240                 { 0x1088, 0, 0x00000000, 0xffffffff },
3241                 { 0x108c, 0, 0x00000000, 0xffffffff },
3242                 { 0x1090, 0, 0x00000000, 0xffffffff },
3243                 { 0x1094, 0, 0x00000000, 0xffffffff },
3244                 { 0x1098, 0, 0x00000000, 0xffffffff },
3245                 { 0x109c, 0, 0x00000000, 0xffffffff },
3246                 { 0x10a0, 0, 0x00000000, 0xffffffff },
3247
3248                 { 0x1408, 0, 0x01c00800, 0x00000000 },
3249                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3250                 { 0x14a8, 0, 0x00000000, 0x000001ff },
3251                 { 0x14ac, 0, 0x4fffffff, 0x10000000 },
3252                 { 0x14b0, 0, 0x00000002, 0x00000001 },
3253                 { 0x14b8, 0, 0x00000000, 0x00000000 },
3254                 { 0x14c0, 0, 0x00000000, 0x00000009 },
3255                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3256                 { 0x14cc, 0, 0x00000000, 0x00000001 },
3257                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3258                 { 0x1500, 0, 0x00000000, 0xffffffff },
3259                 { 0x1504, 0, 0x00000000, 0xffffffff },
3260                 { 0x1508, 0, 0x00000000, 0xffffffff },
3261                 { 0x150c, 0, 0x00000000, 0xffffffff },
3262                 { 0x1510, 0, 0x00000000, 0xffffffff },
3263                 { 0x1514, 0, 0x00000000, 0xffffffff },
3264                 { 0x1518, 0, 0x00000000, 0xffffffff },
3265                 { 0x151c, 0, 0x00000000, 0xffffffff },
3266                 { 0x1520, 0, 0x00000000, 0xffffffff },
3267                 { 0x1524, 0, 0x00000000, 0xffffffff },
3268                 { 0x1528, 0, 0x00000000, 0xffffffff },
3269                 { 0x152c, 0, 0x00000000, 0xffffffff },
3270                 { 0x1530, 0, 0x00000000, 0xffffffff },
3271                 { 0x1534, 0, 0x00000000, 0xffffffff },
3272                 { 0x1538, 0, 0x00000000, 0xffffffff },
3273                 { 0x153c, 0, 0x00000000, 0xffffffff },
3274                 { 0x1540, 0, 0x00000000, 0xffffffff },
3275                 { 0x1544, 0, 0x00000000, 0xffffffff },
3276                 { 0x1548, 0, 0x00000000, 0xffffffff },
3277                 { 0x154c, 0, 0x00000000, 0xffffffff },
3278                 { 0x1550, 0, 0x00000000, 0xffffffff },
3279                 { 0x1554, 0, 0x00000000, 0xffffffff },
3280                 { 0x1558, 0, 0x00000000, 0xffffffff },
3281                 { 0x1600, 0, 0x00000000, 0xffffffff },
3282                 { 0x1604, 0, 0x00000000, 0xffffffff },
3283                 { 0x1608, 0, 0x00000000, 0xffffffff },
3284                 { 0x160c, 0, 0x00000000, 0xffffffff },
3285                 { 0x1610, 0, 0x00000000, 0xffffffff },
3286                 { 0x1614, 0, 0x00000000, 0xffffffff },
3287                 { 0x1618, 0, 0x00000000, 0xffffffff },
3288                 { 0x161c, 0, 0x00000000, 0xffffffff },
3289                 { 0x1620, 0, 0x00000000, 0xffffffff },
3290                 { 0x1624, 0, 0x00000000, 0xffffffff },
3291                 { 0x1628, 0, 0x00000000, 0xffffffff },
3292                 { 0x162c, 0, 0x00000000, 0xffffffff },
3293                 { 0x1630, 0, 0x00000000, 0xffffffff },
3294                 { 0x1634, 0, 0x00000000, 0xffffffff },
3295                 { 0x1638, 0, 0x00000000, 0xffffffff },
3296                 { 0x163c, 0, 0x00000000, 0xffffffff },
3297                 { 0x1640, 0, 0x00000000, 0xffffffff },
3298                 { 0x1644, 0, 0x00000000, 0xffffffff },
3299                 { 0x1648, 0, 0x00000000, 0xffffffff },
3300                 { 0x164c, 0, 0x00000000, 0xffffffff },
3301                 { 0x1650, 0, 0x00000000, 0xffffffff },
3302                 { 0x1654, 0, 0x00000000, 0xffffffff },
3303
3304                 { 0x1800, 0, 0x00000000, 0x00000001 },
3305                 { 0x1804, 0, 0x00000000, 0x00000003 },
3306                 { 0x1840, 0, 0x00000000, 0xffffffff },
3307                 { 0x1844, 0, 0x00000000, 0xffffffff },
3308                 { 0x1848, 0, 0x00000000, 0xffffffff },
3309                 { 0x184c, 0, 0x00000000, 0xffffffff },
3310                 { 0x1850, 0, 0x00000000, 0xffffffff },
3311                 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3312                 { 0x1904, 0, 0xffffffff, 0x00000000 },
3313                 { 0x190c, 0, 0xffffffff, 0x00000000 },
3314                 { 0x1914, 0, 0xffffffff, 0x00000000 },
3315                 { 0x191c, 0, 0xffffffff, 0x00000000 },
3316                 { 0x1924, 0, 0xffffffff, 0x00000000 },
3317                 { 0x192c, 0, 0xffffffff, 0x00000000 },
3318                 { 0x1934, 0, 0xffffffff, 0x00000000 },
3319                 { 0x193c, 0, 0xffffffff, 0x00000000 },
3320                 { 0x1944, 0, 0xffffffff, 0x00000000 },
3321                 { 0x194c, 0, 0xffffffff, 0x00000000 },
3322                 { 0x1954, 0, 0xffffffff, 0x00000000 },
3323                 { 0x195c, 0, 0xffffffff, 0x00000000 },
3324                 { 0x1964, 0, 0xffffffff, 0x00000000 },
3325                 { 0x196c, 0, 0xffffffff, 0x00000000 },
3326                 { 0x1974, 0, 0xffffffff, 0x00000000 },
3327                 { 0x197c, 0, 0xffffffff, 0x00000000 },
3328                 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3329
3330                 { 0x1c00, 0, 0x00000000, 0x00000001 },
3331                 { 0x1c04, 0, 0x00000000, 0x00000003 },
3332                 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3333                 { 0x1c40, 0, 0x00000000, 0xffffffff },
3334                 { 0x1c44, 0, 0x00000000, 0xffffffff },
3335                 { 0x1c48, 0, 0x00000000, 0xffffffff },
3336                 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3337                 { 0x1c50, 0, 0x00000000, 0xffffffff },
3338                 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3339                 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3340                 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3341                 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3342                 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3343                 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3344                 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3345                 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3346                 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3347                 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3348                 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3349                 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3350                 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3351                 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3352                 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3353                 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3354                 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3355                 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3356
3357                 { 0x2004, 0, 0x00000000, 0x0337000f },
3358                 { 0x2008, 0, 0xffffffff, 0x00000000 },
3359                 { 0x200c, 0, 0xffffffff, 0x00000000 },
3360                 { 0x2010, 0, 0xffffffff, 0x00000000 },
3361                 { 0x2014, 0, 0x801fff80, 0x00000000 },
3362                 { 0x2018, 0, 0x000003ff, 0x00000000 },
3363
3364                 { 0x2800, 0, 0x00000000, 0x00000001 },
3365                 { 0x2804, 0, 0x00000000, 0x00003f01 },
3366                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3367                 { 0x2810, 0, 0xffff0000, 0x00000000 },
3368                 { 0x2814, 0, 0xffff0000, 0x00000000 },
3369                 { 0x2818, 0, 0xffff0000, 0x00000000 },
3370                 { 0x281c, 0, 0xffff0000, 0x00000000 },
3371                 { 0x2834, 0, 0xffffffff, 0x00000000 },
3372                 { 0x2840, 0, 0x00000000, 0xffffffff },
3373                 { 0x2844, 0, 0x00000000, 0xffffffff },
3374                 { 0x2848, 0, 0xffffffff, 0x00000000 },
3375                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3376
3377                 { 0x2c00, 0, 0x00000000, 0x00000011 },
3378                 { 0x2c04, 0, 0x00000000, 0x00030007 },
3379
3380                 { 0x3000, 0, 0x00000000, 0x00000001 },
3381                 { 0x3004, 0, 0x00000000, 0x007007ff },
3382                 { 0x3008, 0, 0x00000003, 0x00000000 },
3383                 { 0x300c, 0, 0xffffffff, 0x00000000 },
3384                 { 0x3010, 0, 0xffffffff, 0x00000000 },
3385                 { 0x3014, 0, 0xffffffff, 0x00000000 },
3386                 { 0x3034, 0, 0xffffffff, 0x00000000 },
3387                 { 0x3038, 0, 0xffffffff, 0x00000000 },
3388                 { 0x3050, 0, 0x00000001, 0x00000000 },
3389
3390                 { 0x3c00, 0, 0x00000000, 0x00000001 },
3391                 { 0x3c04, 0, 0x00000000, 0x00070000 },
3392                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3393                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3394                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3395                 { 0x3c14, 0, 0x00000000, 0xffffffff },
3396                 { 0x3c18, 0, 0x00000000, 0xffffffff },
3397                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3398                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3399                 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3400                 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3401                 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3402                 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3403                 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3404                 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3405                 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3406                 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3407                 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3408                 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3409                 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3410                 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3411                 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3412                 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3413                 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3414                 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3415                 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3416                 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3417                 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3418                 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3419                 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3420                 { 0x3c78, 0, 0x00000000, 0x00000000 },
3421                 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3422                 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3423                 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3424                 { 0x3c88, 0, 0x00000000, 0xffffffff },
3425                 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3426
3427                 { 0x4000, 0, 0x00000000, 0x00000001 },
3428                 { 0x4004, 0, 0x00000000, 0x00030000 },
3429                 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3430                 { 0x400c, 0, 0xffffffff, 0x00000000 },
3431                 { 0x4088, 0, 0x00000000, 0x00070303 },
3432
3433                 { 0x4400, 0, 0x00000000, 0x00000001 },
3434                 { 0x4404, 0, 0x00000000, 0x00003f01 },
3435                 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3436                 { 0x440c, 0, 0xffffffff, 0x00000000 },
3437                 { 0x4410, 0, 0xffff,     0x0000 },
3438                 { 0x4414, 0, 0xffff,     0x0000 },
3439                 { 0x4418, 0, 0xffff,     0x0000 },
3440                 { 0x441c, 0, 0xffff,     0x0000 },
3441                 { 0x4428, 0, 0xffffffff, 0x00000000 },
3442                 { 0x442c, 0, 0xffffffff, 0x00000000 },
3443                 { 0x4430, 0, 0xffffffff, 0x00000000 },
3444                 { 0x4434, 0, 0xffffffff, 0x00000000 },
3445                 { 0x4438, 0, 0xffffffff, 0x00000000 },
3446                 { 0x443c, 0, 0xffffffff, 0x00000000 },
3447                 { 0x4440, 0, 0xffffffff, 0x00000000 },
3448                 { 0x4444, 0, 0xffffffff, 0x00000000 },
3449
3450                 { 0x4c00, 0, 0x00000000, 0x00000001 },
3451                 { 0x4c04, 0, 0x00000000, 0x0000003f },
3452                 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3453                 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3454                 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3455                 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3456                 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3457                 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3458                 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3459                 { 0x4c50, 0, 0x00000000, 0xffffffff },
3460
3461                 { 0x5004, 0, 0x00000000, 0x0000007f },
3462                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3463                 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3464
3465                 { 0x5400, 0, 0x00000008, 0x00000001 },
3466                 { 0x5404, 0, 0x00000000, 0x0000003f },
3467                 { 0x5408, 0, 0x0000001f, 0x00000000 },
3468                 { 0x540c, 0, 0xffffffff, 0x00000000 },
3469                 { 0x5410, 0, 0xffffffff, 0x00000000 },
3470                 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3471                 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3472                 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3473                 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3474                 { 0x5428, 0, 0x000000ff, 0x00000000 },
3475                 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3476                 { 0x5430, 0, 0x001fff80, 0x00000000 },
3477                 { 0x5438, 0, 0xffffffff, 0x00000000 },
3478                 { 0x543c, 0, 0xffffffff, 0x00000000 },
3479                 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3480
3481                 { 0x5c00, 0, 0x00000000, 0x00000001 },
3482                 { 0x5c04, 0, 0x00000000, 0x0003000f },
3483                 { 0x5c08, 0, 0x00000003, 0x00000000 },
3484                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3485                 { 0x5c10, 0, 0x00000000, 0xffffffff },
3486                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3487                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3488                 { 0x5c88, 0, 0x00000000, 0x00077373 },
3489                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3490
3491                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3492                 { 0x680c, 0, 0xffffffff, 0x00000000 },
3493                 { 0x6810, 0, 0xffffffff, 0x00000000 },
3494                 { 0x6814, 0, 0xffffffff, 0x00000000 },
3495                 { 0x6818, 0, 0xffffffff, 0x00000000 },
3496                 { 0x681c, 0, 0xffffffff, 0x00000000 },
3497                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3498                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3499                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3500                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3501                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3502                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3503                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3504                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3505                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3506                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3507                 { 0x684c, 0, 0xffffffff, 0x00000000 },
3508                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3509                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3510                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3511                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3512                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3513                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3514
3515                 { 0xffff, 0, 0x00000000, 0x00000000 },
3516         };
3517
3518         ret = 0;
3519         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3520                 u32 offset, rw_mask, ro_mask, save_val, val;
3521
3522                 offset = (u32) reg_tbl[i].offset;
3523                 rw_mask = reg_tbl[i].rw_mask;
3524                 ro_mask = reg_tbl[i].ro_mask;
3525
3526                 save_val = readl(bp->regview + offset);
3527
3528                 writel(0, bp->regview + offset);
3529
3530                 val = readl(bp->regview + offset);
3531                 if ((val & rw_mask) != 0) {
3532                         goto reg_test_err;
3533                 }
3534
3535                 if ((val & ro_mask) != (save_val & ro_mask)) {
3536                         goto reg_test_err;
3537                 }
3538
3539                 writel(0xffffffff, bp->regview + offset);
3540
3541                 val = readl(bp->regview + offset);
3542                 if ((val & rw_mask) != rw_mask) {
3543                         goto reg_test_err;
3544                 }
3545
3546                 if ((val & ro_mask) != (save_val & ro_mask)) {
3547                         goto reg_test_err;
3548                 }
3549
3550                 writel(save_val, bp->regview + offset);
3551                 continue;
3552
3553 reg_test_err:
3554                 writel(save_val, bp->regview + offset);
3555                 ret = -ENODEV;
3556                 break;
3557         }
3558         return ret;
3559 }
3560
3561 static int
3562 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3563 {
3564         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3565                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3566         int i;
3567
3568         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3569                 u32 offset;
3570
3571                 for (offset = 0; offset < size; offset += 4) {
3572
3573                         REG_WR_IND(bp, start + offset, test_pattern[i]);
3574
3575                         if (REG_RD_IND(bp, start + offset) !=
3576                                 test_pattern[i]) {
3577                                 return -ENODEV;
3578                         }
3579                 }
3580         }
3581         return 0;
3582 }
3583
3584 static int
3585 bnx2_test_memory(struct bnx2 *bp)
3586 {
3587         int ret = 0;
3588         int i;
3589         static struct {
3590                 u32   offset;
3591                 u32   len;
3592         } mem_tbl[] = {
3593                 { 0x60000,  0x4000 },
3594                 { 0xa0000,  0x4000 },
3595                 { 0xe0000,  0x4000 },
3596                 { 0x120000, 0x4000 },
3597                 { 0x1a0000, 0x4000 },
3598                 { 0x160000, 0x4000 },
3599                 { 0xffffffff, 0    },
3600         };
3601
3602         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3603                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3604                         mem_tbl[i].len)) != 0) {
3605                         return ret;
3606                 }
3607         }
3608         
3609         return ret;
3610 }
3611
3612 static int
3613 bnx2_test_loopback(struct bnx2 *bp)
3614 {
3615         unsigned int pkt_size, num_pkts, i;
3616         struct sk_buff *skb, *rx_skb;
3617         unsigned char *packet;
3618         u16 rx_start_idx, rx_idx, send_idx;
3619         u32 send_bseq, val;
3620         dma_addr_t map;
3621         struct tx_bd *txbd;
3622         struct sw_bd *rx_buf;
3623         struct l2_fhdr *rx_hdr;
3624         int ret = -ENODEV;
3625
3626         if (!netif_running(bp->dev))
3627                 return -ENODEV;
3628
3629         bp->loopback = MAC_LOOPBACK;
3630         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3631         bnx2_set_mac_loopback(bp);
3632
3633         pkt_size = 1514;
3634         skb = dev_alloc_skb(pkt_size);
3635         packet = skb_put(skb, pkt_size);
3636         memcpy(packet, bp->mac_addr, 6);
3637         memset(packet + 6, 0x0, 8);
3638         for (i = 14; i < pkt_size; i++)
3639                 packet[i] = (unsigned char) (i & 0xff);
3640
3641         map = pci_map_single(bp->pdev, skb->data, pkt_size,
3642                 PCI_DMA_TODEVICE);
3643
3644         val = REG_RD(bp, BNX2_HC_COMMAND);
3645         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3646         REG_RD(bp, BNX2_HC_COMMAND);
3647
3648         udelay(5);
3649         rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3650
3651         send_idx = 0;
3652         send_bseq = 0;
3653         num_pkts = 0;
3654
3655         txbd = &bp->tx_desc_ring[send_idx];
3656
3657         txbd->tx_bd_haddr_hi = (u64) map >> 32;
3658         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3659         txbd->tx_bd_mss_nbytes = pkt_size;
3660         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3661
3662         num_pkts++;
3663         send_idx = NEXT_TX_BD(send_idx);
3664
3665         send_bseq += pkt_size;
3666
3667         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3668         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3669
3670
3671         udelay(100);
3672
3673         val = REG_RD(bp, BNX2_HC_COMMAND);
3674         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3675         REG_RD(bp, BNX2_HC_COMMAND);
3676
3677         udelay(5);
3678
3679         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3680         dev_kfree_skb_irq(skb);
3681
3682         if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3683                 goto loopback_test_done;
3684         }
3685
3686         rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3687         if (rx_idx != rx_start_idx + num_pkts) {
3688                 goto loopback_test_done;
3689         }
3690
3691         rx_buf = &bp->rx_buf_ring[rx_start_idx];
3692         rx_skb = rx_buf->skb;
3693
3694         rx_hdr = (struct l2_fhdr *) rx_skb->data;
3695         skb_reserve(rx_skb, bp->rx_offset);
3696
3697         pci_dma_sync_single_for_cpu(bp->pdev,
3698                 pci_unmap_addr(rx_buf, mapping),
3699                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3700
3701         if (rx_hdr->l2_fhdr_errors &
3702                 (L2_FHDR_ERRORS_BAD_CRC |
3703                 L2_FHDR_ERRORS_PHY_DECODE |
3704                 L2_FHDR_ERRORS_ALIGNMENT |
3705                 L2_FHDR_ERRORS_TOO_SHORT |
3706                 L2_FHDR_ERRORS_GIANT_FRAME)) {
3707
3708                 goto loopback_test_done;
3709         }
3710
3711         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3712                 goto loopback_test_done;
3713         }
3714
3715         for (i = 14; i < pkt_size; i++) {
3716                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3717                         goto loopback_test_done;
3718                 }
3719         }
3720
3721         ret = 0;
3722
3723 loopback_test_done:
3724         bp->loopback = 0;
3725         return ret;
3726 }
3727
3728 #define NVRAM_SIZE 0x200
3729 #define CRC32_RESIDUAL 0xdebb20e3
3730
3731 static int
3732 bnx2_test_nvram(struct bnx2 *bp)
3733 {
3734         u32 buf[NVRAM_SIZE / 4];
3735         u8 *data = (u8 *) buf;
3736         int rc = 0;
3737         u32 magic, csum;
3738
3739         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3740                 goto test_nvram_done;
3741
3742         magic = be32_to_cpu(buf[0]);
3743         if (magic != 0x669955aa) {
3744                 rc = -ENODEV;
3745                 goto test_nvram_done;
3746         }
3747
3748         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3749                 goto test_nvram_done;
3750
3751         csum = ether_crc_le(0x100, data);
3752         if (csum != CRC32_RESIDUAL) {
3753                 rc = -ENODEV;
3754                 goto test_nvram_done;
3755         }
3756
3757         csum = ether_crc_le(0x100, data + 0x100);
3758         if (csum != CRC32_RESIDUAL) {
3759                 rc = -ENODEV;
3760         }
3761
3762 test_nvram_done:
3763         return rc;
3764 }
3765
3766 static int
3767 bnx2_test_link(struct bnx2 *bp)
3768 {
3769         u32 bmsr;
3770
3771         spin_lock_irq(&bp->phy_lock);
3772         bnx2_read_phy(bp, MII_BMSR, &bmsr);
3773         bnx2_read_phy(bp, MII_BMSR, &bmsr);
3774         spin_unlock_irq(&bp->phy_lock);
3775                 
3776         if (bmsr & BMSR_LSTATUS) {
3777                 return 0;
3778         }
3779         return -ENODEV;
3780 }
3781
3782 static int
3783 bnx2_test_intr(struct bnx2 *bp)
3784 {
3785         int i;
3786         u32 val;
3787         u16 status_idx;
3788
3789         if (!netif_running(bp->dev))
3790                 return -ENODEV;
3791
3792         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3793
3794         /* This register is not touched during run-time. */
3795         val = REG_RD(bp, BNX2_HC_COMMAND);
3796         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3797         REG_RD(bp, BNX2_HC_COMMAND);
3798
3799         for (i = 0; i < 10; i++) {
3800                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3801                         status_idx) {
3802
3803                         break;
3804                 }
3805
3806                 msleep_interruptible(10);
3807         }
3808         if (i < 10)
3809                 return 0;
3810
3811         return -ENODEV;
3812 }
3813
3814 static void
3815 bnx2_timer(unsigned long data)
3816 {
3817         struct bnx2 *bp = (struct bnx2 *) data;
3818         u32 msg;
3819
3820         if (!netif_running(bp->dev))
3821                 return;
3822
3823         if (atomic_read(&bp->intr_sem) != 0)
3824                 goto bnx2_restart_timer;
3825
3826         msg = (u32) ++bp->fw_drv_pulse_wr_seq;
3827         REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
3828
3829         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
3830             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
3831                 unsigned long flags;
3832
3833                 spin_lock_irqsave(&bp->phy_lock, flags);
3834                 if (bp->serdes_an_pending) {
3835                         bp->serdes_an_pending--;
3836                 }
3837                 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
3838                         u32 bmcr;
3839
3840                         bp->current_interval = bp->timer_interval;
3841
3842                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
3843
3844                         if (bmcr & BMCR_ANENABLE) {
3845                                 u32 phy1, phy2;
3846
3847                                 bnx2_write_phy(bp, 0x1c, 0x7c00);
3848                                 bnx2_read_phy(bp, 0x1c, &phy1);
3849
3850                                 bnx2_write_phy(bp, 0x17, 0x0f01);
3851                                 bnx2_read_phy(bp, 0x15, &phy2);
3852                                 bnx2_write_phy(bp, 0x17, 0x0f01);
3853                                 bnx2_read_phy(bp, 0x15, &phy2);
3854
3855                                 if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
3856                                         !(phy2 & 0x20)) {       /* no CONFIG */
3857
3858                                         bmcr &= ~BMCR_ANENABLE;
3859                                         bmcr |= BMCR_SPEED1000 |
3860                                                 BMCR_FULLDPLX;
3861                                         bnx2_write_phy(bp, MII_BMCR, bmcr);
3862                                         bp->phy_flags |=
3863                                                 PHY_PARALLEL_DETECT_FLAG;
3864                                 }
3865                         }
3866                 }
3867                 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
3868                         (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
3869                         u32 phy2;
3870
3871                         bnx2_write_phy(bp, 0x17, 0x0f01);
3872                         bnx2_read_phy(bp, 0x15, &phy2);
3873                         if (phy2 & 0x20) {
3874                                 u32 bmcr;
3875
3876                                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3877                                 bmcr |= BMCR_ANENABLE;
3878                                 bnx2_write_phy(bp, MII_BMCR, bmcr);
3879
3880                                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
3881
3882                         }
3883                 }
3884                 else
3885                         bp->current_interval = bp->timer_interval;
3886
3887                 spin_unlock_irqrestore(&bp->phy_lock, flags);
3888         }
3889
3890 bnx2_restart_timer:
3891         mod_timer(&bp->timer, jiffies + bp->current_interval);
3892 }
3893
3894 /* Called with rtnl_lock */
3895 static int
3896 bnx2_open(struct net_device *dev)
3897 {
3898         struct bnx2 *bp = dev->priv;
3899         int rc;
3900
3901         bnx2_set_power_state(bp, 0);
3902         bnx2_disable_int(bp);
3903
3904         rc = bnx2_alloc_mem(bp);
3905         if (rc)
3906                 return rc;
3907
3908         if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
3909                 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
3910                 !disable_msi) {
3911
3912                 if (pci_enable_msi(bp->pdev) == 0) {
3913                         bp->flags |= USING_MSI_FLAG;
3914                         rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
3915                                         dev);
3916                 }
3917                 else {
3918                         rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3919                                         SA_SHIRQ, dev->name, dev);
3920                 }
3921         }
3922         else {
3923                 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
3924                                 dev->name, dev);
3925         }
3926         if (rc) {
3927                 bnx2_free_mem(bp);
3928                 return rc;
3929         }
3930
3931         rc = bnx2_init_nic(bp);
3932
3933         if (rc) {
3934                 free_irq(bp->pdev->irq, dev);
3935                 if (bp->flags & USING_MSI_FLAG) {
3936                         pci_disable_msi(bp->pdev);
3937                         bp->flags &= ~USING_MSI_FLAG;
3938                 }
3939                 bnx2_free_skbs(bp);
3940                 bnx2_free_mem(bp);
3941                 return rc;
3942         }
3943         
3944         mod_timer(&bp->timer, jiffies + bp->current_interval);
3945
3946         atomic_set(&bp->intr_sem, 0);
3947
3948         bnx2_enable_int(bp);
3949
3950         if (bp->flags & USING_MSI_FLAG) {
3951                 /* Test MSI to make sure it is working
3952                  * If MSI test fails, go back to INTx mode
3953                  */
3954                 if (bnx2_test_intr(bp) != 0) {
3955                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
3956                                " using MSI, switching to INTx mode. Please"
3957                                " report this failure to the PCI maintainer"
3958                                " and include system chipset information.\n",
3959                                bp->dev->name);
3960
3961                         bnx2_disable_int(bp);
3962                         free_irq(bp->pdev->irq, dev);
3963                         pci_disable_msi(bp->pdev);
3964                         bp->flags &= ~USING_MSI_FLAG;
3965
3966                         rc = bnx2_init_nic(bp);
3967
3968                         if (!rc) {
3969                                 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3970                                         SA_SHIRQ, dev->name, dev);
3971                         }
3972                         if (rc) {
3973                                 bnx2_free_skbs(bp);
3974                                 bnx2_free_mem(bp);
3975                                 del_timer_sync(&bp->timer);
3976                                 return rc;
3977                         }
3978                         bnx2_enable_int(bp);
3979                 }
3980         }
3981         if (bp->flags & USING_MSI_FLAG) {
3982                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
3983         }
3984
3985         netif_start_queue(dev);
3986
3987         return 0;
3988 }
3989
3990 static void
3991 bnx2_reset_task(void *data)
3992 {
3993         struct bnx2 *bp = data;
3994
3995         if (!netif_running(bp->dev))
3996                 return;
3997
3998         bp->in_reset_task = 1;
3999         bnx2_netif_stop(bp);
4000
4001         bnx2_init_nic(bp);
4002
4003         atomic_set(&bp->intr_sem, 1);
4004         bnx2_netif_start(bp);
4005         bp->in_reset_task = 0;
4006 }
4007
4008 static void
4009 bnx2_tx_timeout(struct net_device *dev)
4010 {
4011         struct bnx2 *bp = dev->priv;
4012
4013         /* This allows the netif to be shutdown gracefully before resetting */
4014         schedule_work(&bp->reset_task);
4015 }
4016
4017 #ifdef BCM_VLAN
4018 /* Called with rtnl_lock */
4019 static void
4020 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4021 {
4022         struct bnx2 *bp = dev->priv;
4023
4024         bnx2_netif_stop(bp);
4025
4026         bp->vlgrp = vlgrp;
4027         bnx2_set_rx_mode(dev);
4028
4029         bnx2_netif_start(bp);
4030 }
4031
4032 /* Called with rtnl_lock */
4033 static void
4034 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4035 {
4036         struct bnx2 *bp = dev->priv;
4037
4038         bnx2_netif_stop(bp);
4039
4040         if (bp->vlgrp)
4041                 bp->vlgrp->vlan_devices[vid] = NULL;
4042         bnx2_set_rx_mode(dev);
4043
4044         bnx2_netif_start(bp);
4045 }
4046 #endif
4047
4048 /* Called with dev->xmit_lock.
4049  * hard_start_xmit is pseudo-lockless - a lock is only required when
4050  * the tx queue is full. This way, we get the benefit of lockless
4051  * operations most of the time without the complexities to handle
4052  * netif_stop_queue/wake_queue race conditions.
4053  */
4054 static int
4055 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4056 {
4057         struct bnx2 *bp = dev->priv;
4058         dma_addr_t mapping;
4059         struct tx_bd *txbd;
4060         struct sw_bd *tx_buf;
4061         u32 len, vlan_tag_flags, last_frag, mss;
4062         u16 prod, ring_prod;
4063         int i;
4064
4065         if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4066                 netif_stop_queue(dev);
4067                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4068                         dev->name);
4069
4070                 return NETDEV_TX_BUSY;
4071         }
4072         len = skb_headlen(skb);
4073         prod = bp->tx_prod;
4074         ring_prod = TX_RING_IDX(prod);
4075
4076         vlan_tag_flags = 0;
4077         if (skb->ip_summed == CHECKSUM_HW) {
4078                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4079         }
4080
4081         if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4082                 vlan_tag_flags |=
4083                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4084         }
4085 #ifdef BCM_TSO 
4086         if ((mss = skb_shinfo(skb)->tso_size) &&
4087                 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4088                 u32 tcp_opt_len, ip_tcp_len;
4089
4090                 if (skb_header_cloned(skb) &&
4091                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4092                         dev_kfree_skb(skb);
4093                         return NETDEV_TX_OK;
4094                 }
4095
4096                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4097                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4098
4099                 tcp_opt_len = 0;
4100                 if (skb->h.th->doff > 5) {
4101                         tcp_opt_len = (skb->h.th->doff - 5) << 2;
4102                 }
4103                 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4104
4105                 skb->nh.iph->check = 0;
4106                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4107                 skb->h.th->check =
4108                         ~csum_tcpudp_magic(skb->nh.iph->saddr,
4109                                             skb->nh.iph->daddr,
4110                                             0, IPPROTO_TCP, 0);
4111
4112                 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4113                         vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4114                                 (tcp_opt_len >> 2)) << 8;
4115                 }
4116         }
4117         else
4118 #endif
4119         {
4120                 mss = 0;
4121         }
4122
4123         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4124         
4125         tx_buf = &bp->tx_buf_ring[ring_prod];
4126         tx_buf->skb = skb;
4127         pci_unmap_addr_set(tx_buf, mapping, mapping);
4128
4129         txbd = &bp->tx_desc_ring[ring_prod];
4130
4131         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4132         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4133         txbd->tx_bd_mss_nbytes = len | (mss << 16);
4134         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4135
4136         last_frag = skb_shinfo(skb)->nr_frags;
4137
4138         for (i = 0; i < last_frag; i++) {
4139                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4140
4141                 prod = NEXT_TX_BD(prod);
4142                 ring_prod = TX_RING_IDX(prod);
4143                 txbd = &bp->tx_desc_ring[ring_prod];
4144
4145                 len = frag->size;
4146                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4147                         len, PCI_DMA_TODEVICE);
4148                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4149                                 mapping, mapping);
4150
4151                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4152                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4153                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4154                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4155
4156         }
4157         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4158
4159         prod = NEXT_TX_BD(prod);
4160         bp->tx_prod_bseq += skb->len;
4161
4162         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4163         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4164
4165         mmiowb();
4166
4167         bp->tx_prod = prod;
4168         dev->trans_start = jiffies;
4169
4170         if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4171                 unsigned long flags;
4172
4173                 spin_lock_irqsave(&bp->tx_lock, flags);
4174                 netif_stop_queue(dev);
4175                 
4176                 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4177                         netif_wake_queue(dev);
4178                 spin_unlock_irqrestore(&bp->tx_lock, flags);
4179         }
4180
4181         return NETDEV_TX_OK;
4182 }
4183
4184 /* Called with rtnl_lock */
4185 static int
4186 bnx2_close(struct net_device *dev)
4187 {
4188         struct bnx2 *bp = dev->priv;
4189         u32 reset_code;
4190
4191         /* Calling flush_scheduled_work() may deadlock because
4192          * linkwatch_event() may be on the workqueue and it will try to get
4193          * the rtnl_lock which we are holding.
4194          */
4195         while (bp->in_reset_task)
4196                 msleep(1);
4197
4198         bnx2_netif_stop(bp);
4199         del_timer_sync(&bp->timer);
4200         if (bp->wol)
4201                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4202         else
4203                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4204         bnx2_reset_chip(bp, reset_code);
4205         free_irq(bp->pdev->irq, dev);
4206         if (bp->flags & USING_MSI_FLAG) {
4207                 pci_disable_msi(bp->pdev);
4208                 bp->flags &= ~USING_MSI_FLAG;
4209         }
4210         bnx2_free_skbs(bp);
4211         bnx2_free_mem(bp);
4212         bp->link_up = 0;
4213         netif_carrier_off(bp->dev);
4214         bnx2_set_power_state(bp, 3);
4215         return 0;
4216 }
4217
4218 #define GET_NET_STATS64(ctr)                                    \
4219         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
4220         (unsigned long) (ctr##_lo)
4221
4222 #define GET_NET_STATS32(ctr)            \
4223         (ctr##_lo)
4224
4225 #if (BITS_PER_LONG == 64)
4226 #define GET_NET_STATS   GET_NET_STATS64
4227 #else
4228 #define GET_NET_STATS   GET_NET_STATS32
4229 #endif
4230
4231 static struct net_device_stats *
4232 bnx2_get_stats(struct net_device *dev)
4233 {
4234         struct bnx2 *bp = dev->priv;
4235         struct statistics_block *stats_blk = bp->stats_blk;
4236         struct net_device_stats *net_stats = &bp->net_stats;
4237
4238         if (bp->stats_blk == NULL) {
4239                 return net_stats;
4240         }
4241         net_stats->rx_packets =
4242                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4243                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4244                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4245
4246         net_stats->tx_packets =
4247                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4248                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4249                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4250
4251         net_stats->rx_bytes =
4252                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4253
4254         net_stats->tx_bytes =
4255                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4256
4257         net_stats->multicast = 
4258                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4259
4260         net_stats->collisions = 
4261                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4262
4263         net_stats->rx_length_errors = 
4264                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4265                 stats_blk->stat_EtherStatsOverrsizePkts);
4266
4267         net_stats->rx_over_errors = 
4268                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4269
4270         net_stats->rx_frame_errors = 
4271                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4272
4273         net_stats->rx_crc_errors = 
4274                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4275
4276         net_stats->rx_errors = net_stats->rx_length_errors +
4277                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4278                 net_stats->rx_crc_errors;
4279
4280         net_stats->tx_aborted_errors =
4281                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4282                 stats_blk->stat_Dot3StatsLateCollisions);
4283
4284         if (CHIP_NUM(bp) == CHIP_NUM_5706)
4285                 net_stats->tx_carrier_errors = 0;
4286         else {
4287                 net_stats->tx_carrier_errors =
4288                         (unsigned long)
4289                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
4290         }
4291
4292         net_stats->tx_errors =
4293                 (unsigned long) 
4294                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4295                 +
4296                 net_stats->tx_aborted_errors +
4297                 net_stats->tx_carrier_errors;
4298
4299         return net_stats;
4300 }
4301
4302 /* All ethtool functions called with rtnl_lock */
4303
4304 static int
4305 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4306 {
4307         struct bnx2 *bp = dev->priv;
4308
4309         cmd->supported = SUPPORTED_Autoneg;
4310         if (bp->phy_flags & PHY_SERDES_FLAG) {
4311                 cmd->supported |= SUPPORTED_1000baseT_Full |
4312                         SUPPORTED_FIBRE;
4313
4314                 cmd->port = PORT_FIBRE;
4315         }
4316         else {
4317                 cmd->supported |= SUPPORTED_10baseT_Half |
4318                         SUPPORTED_10baseT_Full |
4319                         SUPPORTED_100baseT_Half |
4320                         SUPPORTED_100baseT_Full |
4321                         SUPPORTED_1000baseT_Full |
4322                         SUPPORTED_TP;
4323
4324                 cmd->port = PORT_TP;
4325         }
4326
4327         cmd->advertising = bp->advertising;
4328
4329         if (bp->autoneg & AUTONEG_SPEED) {
4330                 cmd->autoneg = AUTONEG_ENABLE;
4331         }
4332         else {
4333                 cmd->autoneg = AUTONEG_DISABLE;
4334         }
4335
4336         if (netif_carrier_ok(dev)) {
4337                 cmd->speed = bp->line_speed;
4338                 cmd->duplex = bp->duplex;
4339         }
4340         else {
4341                 cmd->speed = -1;
4342                 cmd->duplex = -1;
4343         }
4344
4345         cmd->transceiver = XCVR_INTERNAL;
4346         cmd->phy_address = bp->phy_addr;
4347
4348         return 0;
4349 }
4350   
4351 static int
4352 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4353 {
4354         struct bnx2 *bp = dev->priv;
4355         u8 autoneg = bp->autoneg;
4356         u8 req_duplex = bp->req_duplex;
4357         u16 req_line_speed = bp->req_line_speed;
4358         u32 advertising = bp->advertising;
4359
4360         if (cmd->autoneg == AUTONEG_ENABLE) {
4361                 autoneg |= AUTONEG_SPEED;
4362
4363                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; 
4364
4365                 /* allow advertising 1 speed */
4366                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4367                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
4368                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
4369                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
4370
4371                         if (bp->phy_flags & PHY_SERDES_FLAG)
4372                                 return -EINVAL;
4373
4374                         advertising = cmd->advertising;
4375
4376                 }
4377                 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4378                         advertising = cmd->advertising;
4379                 }
4380                 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4381                         return -EINVAL;
4382                 }
4383                 else {
4384                         if (bp->phy_flags & PHY_SERDES_FLAG) {
4385                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4386                         }
4387                         else {
4388                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
4389                         }
4390                 }
4391                 advertising |= ADVERTISED_Autoneg;
4392         }
4393         else {
4394                 if (bp->phy_flags & PHY_SERDES_FLAG) {
4395                         if ((cmd->speed != SPEED_1000) ||
4396                                 (cmd->duplex != DUPLEX_FULL)) {
4397                                 return -EINVAL;
4398                         }
4399                 }
4400                 else if (cmd->speed == SPEED_1000) {
4401                         return -EINVAL;
4402                 }
4403                 autoneg &= ~AUTONEG_SPEED;
4404                 req_line_speed = cmd->speed;
4405                 req_duplex = cmd->duplex;
4406                 advertising = 0;
4407         }
4408
4409         bp->autoneg = autoneg;
4410         bp->advertising = advertising;
4411         bp->req_line_speed = req_line_speed;
4412         bp->req_duplex = req_duplex;
4413
4414         spin_lock_irq(&bp->phy_lock);
4415
4416         bnx2_setup_phy(bp);
4417
4418         spin_unlock_irq(&bp->phy_lock);
4419
4420         return 0;
4421 }
4422
4423 static void
4424 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4425 {
4426         struct bnx2 *bp = dev->priv;
4427
4428         strcpy(info->driver, DRV_MODULE_NAME);
4429         strcpy(info->version, DRV_MODULE_VERSION);
4430         strcpy(info->bus_info, pci_name(bp->pdev));
4431         info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4432         info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4433         info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4434         info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4435         info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4436         info->fw_version[7] = 0;
4437 }
4438
4439 static void
4440 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4441 {
4442         struct bnx2 *bp = dev->priv;
4443
4444         if (bp->flags & NO_WOL_FLAG) {
4445                 wol->supported = 0;
4446                 wol->wolopts = 0;
4447         }
4448         else {
4449                 wol->supported = WAKE_MAGIC;
4450                 if (bp->wol)
4451                         wol->wolopts = WAKE_MAGIC;
4452                 else
4453                         wol->wolopts = 0;
4454         }
4455         memset(&wol->sopass, 0, sizeof(wol->sopass));
4456 }
4457
4458 static int
4459 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4460 {
4461         struct bnx2 *bp = dev->priv;
4462
4463         if (wol->wolopts & ~WAKE_MAGIC)
4464                 return -EINVAL;
4465
4466         if (wol->wolopts & WAKE_MAGIC) {
4467                 if (bp->flags & NO_WOL_FLAG)
4468                         return -EINVAL;
4469
4470                 bp->wol = 1;
4471         }
4472         else {
4473                 bp->wol = 0;
4474         }
4475         return 0;
4476 }
4477
4478 static int
4479 bnx2_nway_reset(struct net_device *dev)
4480 {
4481         struct bnx2 *bp = dev->priv;
4482         u32 bmcr;
4483
4484         if (!(bp->autoneg & AUTONEG_SPEED)) {
4485                 return -EINVAL;
4486         }
4487
4488         spin_lock_irq(&bp->phy_lock);
4489
4490         /* Force a link down visible on the other side */
4491         if (bp->phy_flags & PHY_SERDES_FLAG) {
4492                 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4493                 spin_unlock_irq(&bp->phy_lock);
4494
4495                 msleep(20);
4496
4497                 spin_lock_irq(&bp->phy_lock);
4498                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4499                         bp->current_interval = SERDES_AN_TIMEOUT;
4500                         bp->serdes_an_pending = 1;
4501                         mod_timer(&bp->timer, jiffies + bp->current_interval);
4502                 }
4503         }
4504
4505         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4506         bmcr &= ~BMCR_LOOPBACK;
4507         bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4508
4509         spin_unlock_irq(&bp->phy_lock);
4510
4511         return 0;
4512 }
4513
4514 static int
4515 bnx2_get_eeprom_len(struct net_device *dev)
4516 {
4517         struct bnx2 *bp = dev->priv;
4518
4519         if (bp->flash_info == 0)
4520                 return 0;
4521
4522         return (int) bp->flash_info->total_size;
4523 }
4524
4525 static int
4526 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4527                 u8 *eebuf)
4528 {
4529         struct bnx2 *bp = dev->priv;
4530         int rc;
4531
4532         if (eeprom->offset > bp->flash_info->total_size)
4533                 return -EINVAL;
4534
4535         if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4536                 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4537
4538         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4539
4540         return rc;
4541 }
4542
4543 static int
4544 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4545                 u8 *eebuf)
4546 {
4547         struct bnx2 *bp = dev->priv;
4548         int rc;
4549
4550         if (eeprom->offset > bp->flash_info->total_size)
4551                 return -EINVAL;
4552
4553         if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4554                 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4555
4556         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4557
4558         return rc;
4559 }
4560
4561 static int
4562 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4563 {
4564         struct bnx2 *bp = dev->priv;
4565
4566         memset(coal, 0, sizeof(struct ethtool_coalesce));
4567
4568         coal->rx_coalesce_usecs = bp->rx_ticks;
4569         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4570         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4571         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4572
4573         coal->tx_coalesce_usecs = bp->tx_ticks;
4574         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4575         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4576         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4577
4578         coal->stats_block_coalesce_usecs = bp->stats_ticks;
4579
4580         return 0;
4581 }
4582
4583 static int
4584 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4585 {
4586         struct bnx2 *bp = dev->priv;
4587
4588         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4589         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4590
4591         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; 
4592         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4593
4594         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4595         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4596
4597         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4598         if (bp->rx_quick_cons_trip_int > 0xff)
4599                 bp->rx_quick_cons_trip_int = 0xff;
4600
4601         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4602         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4603
4604         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4605         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4606
4607         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4608         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4609
4610         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4611         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4612                 0xff;
4613
4614         bp->stats_ticks = coal->stats_block_coalesce_usecs;
4615         if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4616         bp->stats_ticks &= 0xffff00;
4617
4618         if (netif_running(bp->dev)) {
4619                 bnx2_netif_stop(bp);
4620                 bnx2_init_nic(bp);
4621                 bnx2_netif_start(bp);
4622         }
4623
4624         return 0;
4625 }
4626
4627 static void
4628 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4629 {
4630         struct bnx2 *bp = dev->priv;
4631
4632         ering->rx_max_pending = MAX_RX_DESC_CNT;
4633         ering->rx_mini_max_pending = 0;
4634         ering->rx_jumbo_max_pending = 0;
4635
4636         ering->rx_pending = bp->rx_ring_size;
4637         ering->rx_mini_pending = 0;
4638         ering->rx_jumbo_pending = 0;
4639
4640         ering->tx_max_pending = MAX_TX_DESC_CNT;
4641         ering->tx_pending = bp->tx_ring_size;
4642 }
4643
4644 static int
4645 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4646 {
4647         struct bnx2 *bp = dev->priv;
4648
4649         if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4650                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4651                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4652
4653                 return -EINVAL;
4654         }
4655         bp->rx_ring_size = ering->rx_pending;
4656         bp->tx_ring_size = ering->tx_pending;
4657
4658         if (netif_running(bp->dev)) {
4659                 bnx2_netif_stop(bp);
4660                 bnx2_init_nic(bp);
4661                 bnx2_netif_start(bp);
4662         }
4663
4664         return 0;
4665 }
4666
4667 static void
4668 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4669 {
4670         struct bnx2 *bp = dev->priv;
4671
4672         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4673         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4674         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4675 }
4676
4677 static int
4678 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4679 {
4680         struct bnx2 *bp = dev->priv;
4681
4682         bp->req_flow_ctrl = 0;
4683         if (epause->rx_pause)
4684                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4685         if (epause->tx_pause)
4686                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4687
4688         if (epause->autoneg) {
4689                 bp->autoneg |= AUTONEG_FLOW_CTRL;
4690         }
4691         else {
4692                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4693         }
4694
4695         spin_lock_irq(&bp->phy_lock);
4696
4697         bnx2_setup_phy(bp);
4698
4699         spin_unlock_irq(&bp->phy_lock);
4700
4701         return 0;
4702 }
4703
4704 static u32
4705 bnx2_get_rx_csum(struct net_device *dev)
4706 {
4707         struct bnx2 *bp = dev->priv;
4708
4709         return bp->rx_csum;
4710 }
4711
4712 static int
4713 bnx2_set_rx_csum(struct net_device *dev, u32 data)
4714 {
4715         struct bnx2 *bp = dev->priv;
4716
4717         bp->rx_csum = data;
4718         return 0;
4719 }
4720
4721 #define BNX2_NUM_STATS 45
4722
4723 static struct {
4724         char string[ETH_GSTRING_LEN];
4725 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4726         { "rx_bytes" },
4727         { "rx_error_bytes" },
4728         { "tx_bytes" },
4729         { "tx_error_bytes" },
4730         { "rx_ucast_packets" },
4731         { "rx_mcast_packets" },
4732         { "rx_bcast_packets" },
4733         { "tx_ucast_packets" },
4734         { "tx_mcast_packets" },
4735         { "tx_bcast_packets" },
4736         { "tx_mac_errors" },
4737         { "tx_carrier_errors" },
4738         { "rx_crc_errors" },
4739         { "rx_align_errors" },
4740         { "tx_single_collisions" },
4741         { "tx_multi_collisions" },
4742         { "tx_deferred" },
4743         { "tx_excess_collisions" },
4744         { "tx_late_collisions" },
4745         { "tx_total_collisions" },
4746         { "rx_fragments" },
4747         { "rx_jabbers" },
4748         { "rx_undersize_packets" },
4749         { "rx_oversize_packets" },
4750         { "rx_64_byte_packets" },
4751         { "rx_65_to_127_byte_packets" },
4752         { "rx_128_to_255_byte_packets" },
4753         { "rx_256_to_511_byte_packets" },
4754         { "rx_512_to_1023_byte_packets" },
4755         { "rx_1024_to_1522_byte_packets" },
4756         { "rx_1523_to_9022_byte_packets" },
4757         { "tx_64_byte_packets" },
4758         { "tx_65_to_127_byte_packets" },
4759         { "tx_128_to_255_byte_packets" },
4760         { "tx_256_to_511_byte_packets" },
4761         { "tx_512_to_1023_byte_packets" },
4762         { "tx_1024_to_1522_byte_packets" },
4763         { "tx_1523_to_9022_byte_packets" },
4764         { "rx_xon_frames" },
4765         { "rx_xoff_frames" },
4766         { "tx_xon_frames" },
4767         { "tx_xoff_frames" },
4768         { "rx_mac_ctrl_frames" },
4769         { "rx_filtered_packets" },
4770         { "rx_discards" },
4771 };
4772
4773 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4774
4775 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
4776     STATS_OFFSET32(stat_IfHCInOctets_hi),
4777     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4778     STATS_OFFSET32(stat_IfHCOutOctets_hi),
4779     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4780     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4781     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4782     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4783     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4784     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4785     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4786     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4787     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),                 
4788     STATS_OFFSET32(stat_Dot3StatsFCSErrors),                          
4789     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),                    
4790     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),              
4791     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),            
4792     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),              
4793     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),                
4794     STATS_OFFSET32(stat_Dot3StatsLateCollisions),                     
4795     STATS_OFFSET32(stat_EtherStatsCollisions),                        
4796     STATS_OFFSET32(stat_EtherStatsFragments),                         
4797     STATS_OFFSET32(stat_EtherStatsJabbers),                           
4798     STATS_OFFSET32(stat_EtherStatsUndersizePkts),                     
4799     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),                     
4800     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),                    
4801     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),         
4802     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),        
4803     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),        
4804     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),       
4805     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),      
4806     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),      
4807     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),                    
4808     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),         
4809     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),        
4810     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),        
4811     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),       
4812     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),      
4813     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),      
4814     STATS_OFFSET32(stat_XonPauseFramesReceived),                      
4815     STATS_OFFSET32(stat_XoffPauseFramesReceived),                     
4816     STATS_OFFSET32(stat_OutXonSent),                                  
4817     STATS_OFFSET32(stat_OutXoffSent),                                 
4818     STATS_OFFSET32(stat_MacControlFramesReceived),                    
4819     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),                  
4820     STATS_OFFSET32(stat_IfInMBUFDiscards),                            
4821 };
4822
4823 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4824  * skipped because of errata.
4825  */               
4826 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
4827         8,0,8,8,8,8,8,8,8,8,
4828         4,0,4,4,4,4,4,4,4,4,
4829         4,4,4,4,4,4,4,4,4,4,
4830         4,4,4,4,4,4,4,4,4,4,
4831         4,4,4,4,4,
4832 };
4833
4834 #define BNX2_NUM_TESTS 6
4835
4836 static struct {
4837         char string[ETH_GSTRING_LEN];
4838 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
4839         { "register_test (offline)" },
4840         { "memory_test (offline)" },
4841         { "loopback_test (offline)" },
4842         { "nvram_test (online)" },
4843         { "interrupt_test (online)" },
4844         { "link_test (online)" },
4845 };
4846
4847 static int
4848 bnx2_self_test_count(struct net_device *dev)
4849 {
4850         return BNX2_NUM_TESTS;
4851 }
4852
4853 static void
4854 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
4855 {
4856         struct bnx2 *bp = dev->priv;
4857
4858         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
4859         if (etest->flags & ETH_TEST_FL_OFFLINE) {
4860                 bnx2_netif_stop(bp);
4861                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
4862                 bnx2_free_skbs(bp);
4863
4864                 if (bnx2_test_registers(bp) != 0) {
4865                         buf[0] = 1;
4866                         etest->flags |= ETH_TEST_FL_FAILED;
4867                 }
4868                 if (bnx2_test_memory(bp) != 0) {
4869                         buf[1] = 1;
4870                         etest->flags |= ETH_TEST_FL_FAILED;
4871                 }
4872                 if (bnx2_test_loopback(bp) != 0) {
4873                         buf[2] = 1;
4874                         etest->flags |= ETH_TEST_FL_FAILED;
4875                 }
4876
4877                 if (!netif_running(bp->dev)) {
4878                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4879                 }
4880                 else {
4881                         bnx2_init_nic(bp);
4882                         bnx2_netif_start(bp);
4883                 }
4884
4885                 /* wait for link up */
4886                 msleep_interruptible(3000);
4887                 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
4888                         msleep_interruptible(4000);
4889         }
4890
4891         if (bnx2_test_nvram(bp) != 0) {
4892                 buf[3] = 1;
4893                 etest->flags |= ETH_TEST_FL_FAILED;
4894         }
4895         if (bnx2_test_intr(bp) != 0) {
4896                 buf[4] = 1;
4897                 etest->flags |= ETH_TEST_FL_FAILED;
4898         }
4899
4900         if (bnx2_test_link(bp) != 0) {
4901                 buf[5] = 1;
4902                 etest->flags |= ETH_TEST_FL_FAILED;
4903
4904         }
4905 }
4906
4907 static void
4908 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
4909 {
4910         switch (stringset) {
4911         case ETH_SS_STATS:
4912                 memcpy(buf, bnx2_stats_str_arr,
4913                         sizeof(bnx2_stats_str_arr));
4914                 break;
4915         case ETH_SS_TEST:
4916                 memcpy(buf, bnx2_tests_str_arr,
4917                         sizeof(bnx2_tests_str_arr));
4918                 break;
4919         }
4920 }
4921
4922 static int
4923 bnx2_get_stats_count(struct net_device *dev)
4924 {
4925         return BNX2_NUM_STATS;
4926 }
4927
4928 static void
4929 bnx2_get_ethtool_stats(struct net_device *dev,
4930                 struct ethtool_stats *stats, u64 *buf)
4931 {
4932         struct bnx2 *bp = dev->priv;
4933         int i;
4934         u32 *hw_stats = (u32 *) bp->stats_blk;
4935         u8 *stats_len_arr = NULL;
4936
4937         if (hw_stats == NULL) {
4938                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
4939                 return;
4940         }
4941
4942         if (CHIP_NUM(bp) == CHIP_NUM_5706)
4943                 stats_len_arr = bnx2_5706_stats_len_arr;
4944
4945         for (i = 0; i < BNX2_NUM_STATS; i++) {
4946                 if (stats_len_arr[i] == 0) {
4947                         /* skip this counter */
4948                         buf[i] = 0;
4949                         continue;
4950                 }
4951                 if (stats_len_arr[i] == 4) {
4952                         /* 4-byte counter */
4953                         buf[i] = (u64)
4954                                 *(hw_stats + bnx2_stats_offset_arr[i]);
4955                         continue;
4956                 }
4957                 /* 8-byte counter */
4958                 buf[i] = (((u64) *(hw_stats +
4959                                         bnx2_stats_offset_arr[i])) << 32) +
4960                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
4961         }
4962 }
4963
4964 static int
4965 bnx2_phys_id(struct net_device *dev, u32 data)
4966 {
4967         struct bnx2 *bp = dev->priv;
4968         int i;
4969         u32 save;
4970
4971         if (data == 0)
4972                 data = 2;
4973
4974         save = REG_RD(bp, BNX2_MISC_CFG);
4975         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
4976
4977         for (i = 0; i < (data * 2); i++) {
4978                 if ((i % 2) == 0) {
4979                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
4980                 }
4981                 else {
4982                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
4983                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
4984                                 BNX2_EMAC_LED_100MB_OVERRIDE |
4985                                 BNX2_EMAC_LED_10MB_OVERRIDE |
4986                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
4987                                 BNX2_EMAC_LED_TRAFFIC);
4988                 }
4989                 msleep_interruptible(500);
4990                 if (signal_pending(current))
4991                         break;
4992         }
4993         REG_WR(bp, BNX2_EMAC_LED, 0);
4994         REG_WR(bp, BNX2_MISC_CFG, save);
4995         return 0;
4996 }
4997
4998 static struct ethtool_ops bnx2_ethtool_ops = {
4999         .get_settings           = bnx2_get_settings,
5000         .set_settings           = bnx2_set_settings,
5001         .get_drvinfo            = bnx2_get_drvinfo,
5002         .get_wol                = bnx2_get_wol,
5003         .set_wol                = bnx2_set_wol,
5004         .nway_reset             = bnx2_nway_reset,
5005         .get_link               = ethtool_op_get_link,
5006         .get_eeprom_len         = bnx2_get_eeprom_len,
5007         .get_eeprom             = bnx2_get_eeprom,
5008         .set_eeprom             = bnx2_set_eeprom,
5009         .get_coalesce           = bnx2_get_coalesce,
5010         .set_coalesce           = bnx2_set_coalesce,
5011         .get_ringparam          = bnx2_get_ringparam,
5012         .set_ringparam          = bnx2_set_ringparam,
5013         .get_pauseparam         = bnx2_get_pauseparam,
5014         .set_pauseparam         = bnx2_set_pauseparam,
5015         .get_rx_csum            = bnx2_get_rx_csum,
5016         .set_rx_csum            = bnx2_set_rx_csum,
5017         .get_tx_csum            = ethtool_op_get_tx_csum,
5018         .set_tx_csum            = ethtool_op_set_tx_csum,
5019         .get_sg                 = ethtool_op_get_sg,
5020         .set_sg                 = ethtool_op_set_sg,
5021 #ifdef BCM_TSO
5022         .get_tso                = ethtool_op_get_tso,
5023         .set_tso                = ethtool_op_set_tso,
5024 #endif
5025         .self_test_count        = bnx2_self_test_count,
5026         .self_test              = bnx2_self_test,
5027         .get_strings            = bnx2_get_strings,
5028         .phys_id                = bnx2_phys_id,
5029         .get_stats_count        = bnx2_get_stats_count,
5030         .get_ethtool_stats      = bnx2_get_ethtool_stats,
5031 };
5032
5033 /* Called with rtnl_lock */
5034 static int
5035 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5036 {
5037         struct mii_ioctl_data *data = if_mii(ifr);
5038         struct bnx2 *bp = dev->priv;
5039         int err;
5040
5041         switch(cmd) {
5042         case SIOCGMIIPHY:
5043                 data->phy_id = bp->phy_addr;
5044
5045                 /* fallthru */
5046         case SIOCGMIIREG: {
5047                 u32 mii_regval;
5048
5049                 spin_lock_irq(&bp->phy_lock);
5050                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5051                 spin_unlock_irq(&bp->phy_lock);
5052
5053                 data->val_out = mii_regval;
5054
5055                 return err;
5056         }
5057
5058         case SIOCSMIIREG:
5059                 if (!capable(CAP_NET_ADMIN))
5060                         return -EPERM;
5061
5062                 spin_lock_irq(&bp->phy_lock);
5063                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5064                 spin_unlock_irq(&bp->phy_lock);
5065
5066                 return err;
5067
5068         default:
5069                 /* do nothing */
5070                 break;
5071         }
5072         return -EOPNOTSUPP;
5073 }
5074
5075 /* Called with rtnl_lock */
5076 static int
5077 bnx2_change_mac_addr(struct net_device *dev, void *p)
5078 {
5079         struct sockaddr *addr = p;
5080         struct bnx2 *bp = dev->priv;
5081
5082         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5083         if (netif_running(dev))
5084                 bnx2_set_mac_addr(bp);
5085
5086         return 0;
5087 }
5088
5089 /* Called with rtnl_lock */
5090 static int
5091 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5092 {
5093         struct bnx2 *bp = dev->priv;
5094
5095         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5096                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5097                 return -EINVAL;
5098
5099         dev->mtu = new_mtu;
5100         if (netif_running(dev)) {
5101                 bnx2_netif_stop(bp);
5102
5103                 bnx2_init_nic(bp);
5104
5105                 bnx2_netif_start(bp);
5106         }
5107         return 0;
5108 }
5109
5110 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5111 static void
5112 poll_bnx2(struct net_device *dev)
5113 {
5114         struct bnx2 *bp = dev->priv;
5115
5116         disable_irq(bp->pdev->irq);
5117         bnx2_interrupt(bp->pdev->irq, dev, NULL);
5118         enable_irq(bp->pdev->irq);
5119 }
5120 #endif
5121
5122 static int __devinit
5123 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5124 {
5125         struct bnx2 *bp;
5126         unsigned long mem_len;
5127         int rc;
5128         u32 reg;
5129
5130         SET_MODULE_OWNER(dev);
5131         SET_NETDEV_DEV(dev, &pdev->dev);
5132         bp = dev->priv;
5133
5134         bp->flags = 0;
5135         bp->phy_flags = 0;
5136
5137         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5138         rc = pci_enable_device(pdev);
5139         if (rc) {
5140                 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5141                 goto err_out;
5142         }
5143
5144         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5145                 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5146                        "aborting.\n");
5147                 rc = -ENODEV;
5148                 goto err_out_disable;
5149         }
5150
5151         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5152         if (rc) {
5153                 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5154                 goto err_out_disable;
5155         }
5156
5157         pci_set_master(pdev);
5158
5159         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5160         if (bp->pm_cap == 0) {
5161                 printk(KERN_ERR PFX "Cannot find power management capability, "
5162                                "aborting.\n");
5163                 rc = -EIO;
5164                 goto err_out_release;
5165         }
5166
5167         bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5168         if (bp->pcix_cap == 0) {
5169                 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5170                 rc = -EIO;
5171                 goto err_out_release;
5172         }
5173
5174         if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5175                 bp->flags |= USING_DAC_FLAG;
5176                 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5177                         printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5178                                "failed, aborting.\n");
5179                         rc = -EIO;
5180                         goto err_out_release;
5181                 }
5182         }
5183         else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5184                 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5185                 rc = -EIO;
5186                 goto err_out_release;
5187         }
5188
5189         bp->dev = dev;
5190         bp->pdev = pdev;
5191
5192         spin_lock_init(&bp->phy_lock);
5193         spin_lock_init(&bp->tx_lock);
5194         INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5195
5196         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5197         mem_len = MB_GET_CID_ADDR(17);
5198         dev->mem_end = dev->mem_start + mem_len;
5199         dev->irq = pdev->irq;
5200
5201         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5202
5203         if (!bp->regview) {
5204                 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5205                 rc = -ENOMEM;
5206                 goto err_out_release;
5207         }
5208
5209         /* Configure byte swap and enable write to the reg_window registers.
5210          * Rely on CPU to do target byte swapping on big endian systems
5211          * The chip's target access swapping will not swap all accesses
5212          */
5213         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5214                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5215                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5216
5217         bnx2_set_power_state(bp, 0);
5218
5219         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5220
5221         bp->phy_addr = 1;
5222
5223         /* Get bus information. */
5224         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5225         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5226                 u32 clkreg;
5227
5228                 bp->flags |= PCIX_FLAG;
5229
5230                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5231                 
5232                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5233                 switch (clkreg) {
5234                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5235                         bp->bus_speed_mhz = 133;
5236                         break;
5237
5238                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5239                         bp->bus_speed_mhz = 100;
5240                         break;
5241
5242                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5243                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5244                         bp->bus_speed_mhz = 66;
5245                         break;
5246
5247                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5248                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5249                         bp->bus_speed_mhz = 50;
5250                         break;
5251
5252                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5253                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5254                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5255                         bp->bus_speed_mhz = 33;
5256                         break;
5257                 }
5258         }
5259         else {
5260                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5261                         bp->bus_speed_mhz = 66;
5262                 else
5263                         bp->bus_speed_mhz = 33;
5264         }
5265
5266         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5267                 bp->flags |= PCI_32BIT_FLAG;
5268
5269         /* 5706A0 may falsely detect SERR and PERR. */
5270         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5271                 reg = REG_RD(bp, PCI_COMMAND);
5272                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5273                 REG_WR(bp, PCI_COMMAND, reg);
5274         }
5275         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5276                 !(bp->flags & PCIX_FLAG)) {
5277
5278                 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5279                        "aborting.\n");
5280                 goto err_out_unmap;
5281         }
5282
5283         bnx2_init_nvram(bp);
5284
5285         /* Get the permanent MAC address.  First we need to make sure the
5286          * firmware is actually running.
5287          */
5288         reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5289
5290         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5291             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5292                 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5293                 rc = -ENODEV;
5294                 goto err_out_unmap;
5295         }
5296
5297         bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5298                                 BNX2_DEV_INFO_BC_REV);
5299
5300         reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5301         bp->mac_addr[0] = (u8) (reg >> 8);
5302         bp->mac_addr[1] = (u8) reg;
5303
5304         reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5305         bp->mac_addr[2] = (u8) (reg >> 24);
5306         bp->mac_addr[3] = (u8) (reg >> 16);
5307         bp->mac_addr[4] = (u8) (reg >> 8);
5308         bp->mac_addr[5] = (u8) reg;
5309
5310         bp->tx_ring_size = MAX_TX_DESC_CNT;
5311         bp->rx_ring_size = 100;
5312
5313         bp->rx_csum = 1;
5314
5315         bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5316
5317         bp->tx_quick_cons_trip_int = 20;
5318         bp->tx_quick_cons_trip = 20;
5319         bp->tx_ticks_int = 80;
5320         bp->tx_ticks = 80;
5321                 
5322         bp->rx_quick_cons_trip_int = 6;
5323         bp->rx_quick_cons_trip = 6;
5324         bp->rx_ticks_int = 18;
5325         bp->rx_ticks = 18;
5326
5327         bp->stats_ticks = 1000000 & 0xffff00;
5328
5329         bp->timer_interval =  HZ;
5330         bp->current_interval =  HZ;
5331
5332         /* Disable WOL support if we are running on a SERDES chip. */
5333         if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5334                 bp->phy_flags |= PHY_SERDES_FLAG;
5335                 bp->flags |= NO_WOL_FLAG;
5336         }
5337
5338         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5339                 bp->tx_quick_cons_trip_int =
5340                         bp->tx_quick_cons_trip;
5341                 bp->tx_ticks_int = bp->tx_ticks;
5342                 bp->rx_quick_cons_trip_int =
5343                         bp->rx_quick_cons_trip;
5344                 bp->rx_ticks_int = bp->rx_ticks;
5345                 bp->comp_prod_trip_int = bp->comp_prod_trip;
5346                 bp->com_ticks_int = bp->com_ticks;
5347                 bp->cmd_ticks_int = bp->cmd_ticks;
5348         }
5349
5350         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5351         bp->req_line_speed = 0;
5352         if (bp->phy_flags & PHY_SERDES_FLAG) {
5353                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5354
5355                 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5356                                  BNX2_PORT_HW_CFG_CONFIG);
5357                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5358                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5359                         bp->autoneg = 0;
5360                         bp->req_line_speed = bp->line_speed = SPEED_1000;
5361                         bp->req_duplex = DUPLEX_FULL;
5362                 }
5363         }
5364         else {
5365                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5366         }
5367
5368         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5369
5370         init_timer(&bp->timer);
5371         bp->timer.expires = RUN_AT(bp->timer_interval);
5372         bp->timer.data = (unsigned long) bp;
5373         bp->timer.function = bnx2_timer;
5374
5375         return 0;
5376
5377 err_out_unmap:
5378         if (bp->regview) {
5379                 iounmap(bp->regview);
5380         }
5381
5382 err_out_release:
5383         pci_release_regions(pdev);
5384
5385 err_out_disable:
5386         pci_disable_device(pdev);
5387         pci_set_drvdata(pdev, NULL);
5388
5389 err_out:
5390         return rc;
5391 }
5392
5393 static int __devinit
5394 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5395 {
5396         static int version_printed = 0;
5397         struct net_device *dev = NULL;
5398         struct bnx2 *bp;
5399         int rc, i;
5400
5401         if (version_printed++ == 0)
5402                 printk(KERN_INFO "%s", version);
5403
5404         /* dev zeroed in init_etherdev */
5405         dev = alloc_etherdev(sizeof(*bp));
5406
5407         if (!dev)
5408                 return -ENOMEM;
5409
5410         rc = bnx2_init_board(pdev, dev);
5411         if (rc < 0) {
5412                 free_netdev(dev);
5413                 return rc;
5414         }
5415
5416         dev->open = bnx2_open;
5417         dev->hard_start_xmit = bnx2_start_xmit;
5418         dev->stop = bnx2_close;
5419         dev->get_stats = bnx2_get_stats;
5420         dev->set_multicast_list = bnx2_set_rx_mode;
5421         dev->do_ioctl = bnx2_ioctl;
5422         dev->set_mac_address = bnx2_change_mac_addr;
5423         dev->change_mtu = bnx2_change_mtu;
5424         dev->tx_timeout = bnx2_tx_timeout;
5425         dev->watchdog_timeo = TX_TIMEOUT;
5426 #ifdef BCM_VLAN
5427         dev->vlan_rx_register = bnx2_vlan_rx_register;
5428         dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5429 #endif
5430         dev->poll = bnx2_poll;
5431         dev->ethtool_ops = &bnx2_ethtool_ops;
5432         dev->weight = 64;
5433
5434         bp = dev->priv;
5435
5436 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5437         dev->poll_controller = poll_bnx2;
5438 #endif
5439
5440         if ((rc = register_netdev(dev))) {
5441                 printk(KERN_ERR PFX "Cannot register net device\n");
5442                 if (bp->regview)
5443                         iounmap(bp->regview);
5444                 pci_release_regions(pdev);
5445                 pci_disable_device(pdev);
5446                 pci_set_drvdata(pdev, NULL);
5447                 free_netdev(dev);
5448                 return rc;
5449         }
5450
5451         pci_set_drvdata(pdev, dev);
5452
5453         memcpy(dev->dev_addr, bp->mac_addr, 6);
5454         bp->name = board_info[ent->driver_data].name,
5455         printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5456                 "IRQ %d, ",
5457                 dev->name,
5458                 bp->name,
5459                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5460                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5461                 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5462                 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5463                 bp->bus_speed_mhz,
5464                 dev->base_addr,
5465                 bp->pdev->irq);
5466
5467         printk("node addr ");
5468         for (i = 0; i < 6; i++)
5469                 printk("%2.2x", dev->dev_addr[i]);
5470         printk("\n");
5471
5472         dev->features |= NETIF_F_SG;
5473         if (bp->flags & USING_DAC_FLAG)
5474                 dev->features |= NETIF_F_HIGHDMA;
5475         dev->features |= NETIF_F_IP_CSUM;
5476 #ifdef BCM_VLAN
5477         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5478 #endif
5479 #ifdef BCM_TSO
5480         dev->features |= NETIF_F_TSO;
5481 #endif
5482
5483         netif_carrier_off(bp->dev);
5484
5485         return 0;
5486 }
5487
5488 static void __devexit
5489 bnx2_remove_one(struct pci_dev *pdev)
5490 {
5491         struct net_device *dev = pci_get_drvdata(pdev);
5492         struct bnx2 *bp = dev->priv;
5493
5494         flush_scheduled_work();
5495
5496         unregister_netdev(dev);
5497
5498         if (bp->regview)
5499                 iounmap(bp->regview);
5500
5501         free_netdev(dev);
5502         pci_release_regions(pdev);
5503         pci_disable_device(pdev);
5504         pci_set_drvdata(pdev, NULL);
5505 }
5506
5507 static int
5508 bnx2_suspend(struct pci_dev *pdev, u32 state)
5509 {
5510         struct net_device *dev = pci_get_drvdata(pdev);
5511         struct bnx2 *bp = dev->priv;
5512         u32 reset_code;
5513
5514         if (!netif_running(dev))
5515                 return 0;
5516
5517         bnx2_netif_stop(bp);
5518         netif_device_detach(dev);
5519         del_timer_sync(&bp->timer);
5520         if (bp->wol)
5521                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5522         else
5523                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5524         bnx2_reset_chip(bp, reset_code);
5525         bnx2_free_skbs(bp);
5526         bnx2_set_power_state(bp, state);
5527         return 0;
5528 }
5529
5530 static int
5531 bnx2_resume(struct pci_dev *pdev)
5532 {
5533         struct net_device *dev = pci_get_drvdata(pdev);
5534         struct bnx2 *bp = dev->priv;
5535
5536         if (!netif_running(dev))
5537                 return 0;
5538
5539         bnx2_set_power_state(bp, 0);
5540         netif_device_attach(dev);
5541         bnx2_init_nic(bp);
5542         bnx2_netif_start(bp);
5543         return 0;
5544 }
5545
5546 static struct pci_driver bnx2_pci_driver = {
5547         .name           = DRV_MODULE_NAME,
5548         .id_table       = bnx2_pci_tbl,
5549         .probe          = bnx2_init_one,
5550         .remove         = __devexit_p(bnx2_remove_one),
5551         .suspend        = bnx2_suspend,
5552         .resume         = bnx2_resume,
5553 };
5554
5555 static int __init bnx2_init(void)
5556 {
5557         return pci_module_init(&bnx2_pci_driver);
5558 }
5559
5560 static void __exit bnx2_cleanup(void)
5561 {
5562         pci_unregister_driver(&bnx2_pci_driver);
5563 }
5564
5565 module_init(bnx2_init);
5566 module_exit(bnx2_cleanup);
5567
5568
5569