[BNX2]: Improve handshake with firmware
[linux-2.6.git] / drivers / net / bnx2.c
1 /* bnx2.c: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004, 2005 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12 #include "bnx2.h"
13 #include "bnx2_fw.h"
14
15 #define DRV_MODULE_NAME         "bnx2"
16 #define PFX DRV_MODULE_NAME     ": "
17 #define DRV_MODULE_VERSION      "1.4.30"
18 #define DRV_MODULE_RELDATE      "October 11, 2005"
19
20 #define RUN_AT(x) (jiffies + (x))
21
22 /* Time in jiffies before concluding the transmitter is hung. */
23 #define TX_TIMEOUT  (5*HZ)
24
25 static char version[] __devinitdata =
26         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
30 MODULE_LICENSE("GPL");
31 MODULE_VERSION(DRV_MODULE_VERSION);
32
33 static int disable_msi = 0;
34
35 module_param(disable_msi, int, 0);
36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38 typedef enum {
39         BCM5706 = 0,
40         NC370T,
41         NC370I,
42         BCM5706S,
43         NC370F,
44         BCM5708,
45         BCM5708S,
46 } board_t;
47
48 /* indexed by board_t, above */
49 static struct {
50         char *name;
51 } board_info[] __devinitdata = {
52         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
53         { "HP NC370T Multifunction Gigabit Server Adapter" },
54         { "HP NC370i Multifunction Gigabit Server Adapter" },
55         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
56         { "HP NC370F Multifunction Gigabit Server Adapter" },
57         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
58         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
59         };
60
61 static struct pci_device_id bnx2_pci_tbl[] = {
62         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
64         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
65           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
66         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
67           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
68         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
69           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
70         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
71           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
72         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
73           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
74         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
75           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
76         { 0, }
77 };
78
79 static struct flash_spec flash_table[] =
80 {
81         /* Slow EEPROM */
82         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
83          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
84          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
85          "EEPROM - slow"},
86         /* Expansion entry 0001 */
87         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
88          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
89          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
90          "Entry 0001"},
91         /* Saifun SA25F010 (non-buffered flash) */
92         /* strap, cfg1, & write1 need updates */
93         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
94          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
95          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
96          "Non-buffered flash (128kB)"},
97         /* Saifun SA25F020 (non-buffered flash) */
98         /* strap, cfg1, & write1 need updates */
99         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
100          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
101          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
102          "Non-buffered flash (256kB)"},
103         /* Expansion entry 0100 */
104         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
105          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
106          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
107          "Entry 0100"},
108         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
109         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,        
110          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
111          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
112          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
113         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
114         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
115          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
116          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
117          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
118         /* Saifun SA25F005 (non-buffered flash) */
119         /* strap, cfg1, & write1 need updates */
120         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
121          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
122          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
123          "Non-buffered flash (64kB)"},
124         /* Fast EEPROM */
125         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
126          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
127          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
128          "EEPROM - fast"},
129         /* Expansion entry 1001 */
130         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
131          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
132          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
133          "Entry 1001"},
134         /* Expansion entry 1010 */
135         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
136          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
138          "Entry 1010"},
139         /* ATMEL AT45DB011B (buffered flash) */
140         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
141          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
142          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
143          "Buffered flash (128kB)"},
144         /* Expansion entry 1100 */
145         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
146          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
148          "Entry 1100"},
149         /* Expansion entry 1101 */
150         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
151          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
152          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
153          "Entry 1101"},
154         /* Ateml Expansion entry 1110 */
155         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
156          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
157          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
158          "Entry 1110 (Atmel)"},
159         /* ATMEL AT45DB021B (buffered flash) */
160         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
161          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
162          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
163          "Buffered flash (256kB)"},
164 };
165
166 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
167
168 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
169 {
170         u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
171
172         if (diff > MAX_TX_DESC_CNT)
173                 diff = (diff & MAX_TX_DESC_CNT) - 1;
174         return (bp->tx_ring_size - diff);
175 }
176
177 static u32
178 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
179 {
180         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
181         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
182 }
183
184 static void
185 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
186 {
187         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
188         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
189 }
190
191 static void
192 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
193 {
194         offset += cid_addr;
195         REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
196         REG_WR(bp, BNX2_CTX_DATA, val);
197 }
198
199 static int
200 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
201 {
202         u32 val1;
203         int i, ret;
204
205         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
206                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
207                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
208
209                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
210                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
211
212                 udelay(40);
213         }
214
215         val1 = (bp->phy_addr << 21) | (reg << 16) |
216                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
217                 BNX2_EMAC_MDIO_COMM_START_BUSY;
218         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
219
220         for (i = 0; i < 50; i++) {
221                 udelay(10);
222
223                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
224                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
225                         udelay(5);
226
227                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
228                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
229
230                         break;
231                 }
232         }
233
234         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
235                 *val = 0x0;
236                 ret = -EBUSY;
237         }
238         else {
239                 *val = val1;
240                 ret = 0;
241         }
242
243         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
244                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
245                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
246
247                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
248                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
249
250                 udelay(40);
251         }
252
253         return ret;
254 }
255
256 static int
257 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
258 {
259         u32 val1;
260         int i, ret;
261
262         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
263                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
264                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
265
266                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
267                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
268
269                 udelay(40);
270         }
271
272         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
273                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
274                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
275         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
276     
277         for (i = 0; i < 50; i++) {
278                 udelay(10);
279
280                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
281                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
282                         udelay(5);
283                         break;
284                 }
285         }
286
287         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
288                 ret = -EBUSY;
289         else
290                 ret = 0;
291
292         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
293                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
294                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
295
296                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
297                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
298
299                 udelay(40);
300         }
301
302         return ret;
303 }
304
305 static void
306 bnx2_disable_int(struct bnx2 *bp)
307 {
308         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
309                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
310         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
311 }
312
313 static void
314 bnx2_enable_int(struct bnx2 *bp)
315 {
316         u32 val;
317
318         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
319                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
320
321         val = REG_RD(bp, BNX2_HC_COMMAND);
322         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
323 }
324
325 static void
326 bnx2_disable_int_sync(struct bnx2 *bp)
327 {
328         atomic_inc(&bp->intr_sem);
329         bnx2_disable_int(bp);
330         synchronize_irq(bp->pdev->irq);
331 }
332
333 static void
334 bnx2_netif_stop(struct bnx2 *bp)
335 {
336         bnx2_disable_int_sync(bp);
337         if (netif_running(bp->dev)) {
338                 netif_poll_disable(bp->dev);
339                 netif_tx_disable(bp->dev);
340                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
341         }
342 }
343
344 static void
345 bnx2_netif_start(struct bnx2 *bp)
346 {
347         if (atomic_dec_and_test(&bp->intr_sem)) {
348                 if (netif_running(bp->dev)) {
349                         netif_wake_queue(bp->dev);
350                         netif_poll_enable(bp->dev);
351                         bnx2_enable_int(bp);
352                 }
353         }
354 }
355
356 static void
357 bnx2_free_mem(struct bnx2 *bp)
358 {
359         if (bp->stats_blk) {
360                 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
361                                     bp->stats_blk, bp->stats_blk_mapping);
362                 bp->stats_blk = NULL;
363         }
364         if (bp->status_blk) {
365                 pci_free_consistent(bp->pdev, sizeof(struct status_block),
366                                     bp->status_blk, bp->status_blk_mapping);
367                 bp->status_blk = NULL;
368         }
369         if (bp->tx_desc_ring) {
370                 pci_free_consistent(bp->pdev,
371                                     sizeof(struct tx_bd) * TX_DESC_CNT,
372                                     bp->tx_desc_ring, bp->tx_desc_mapping);
373                 bp->tx_desc_ring = NULL;
374         }
375         kfree(bp->tx_buf_ring);
376         bp->tx_buf_ring = NULL;
377         if (bp->rx_desc_ring) {
378                 pci_free_consistent(bp->pdev,
379                                     sizeof(struct rx_bd) * RX_DESC_CNT,
380                                     bp->rx_desc_ring, bp->rx_desc_mapping);
381                 bp->rx_desc_ring = NULL;
382         }
383         kfree(bp->rx_buf_ring);
384         bp->rx_buf_ring = NULL;
385 }
386
387 static int
388 bnx2_alloc_mem(struct bnx2 *bp)
389 {
390         bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
391                                      GFP_KERNEL);
392         if (bp->tx_buf_ring == NULL)
393                 return -ENOMEM;
394
395         memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
396         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
397                                                 sizeof(struct tx_bd) *
398                                                 TX_DESC_CNT,
399                                                 &bp->tx_desc_mapping);
400         if (bp->tx_desc_ring == NULL)
401                 goto alloc_mem_err;
402
403         bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
404                                      GFP_KERNEL);
405         if (bp->rx_buf_ring == NULL)
406                 goto alloc_mem_err;
407
408         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
409         bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
410                                                 sizeof(struct rx_bd) *
411                                                 RX_DESC_CNT,
412                                                 &bp->rx_desc_mapping);
413         if (bp->rx_desc_ring == NULL)
414                 goto alloc_mem_err;
415
416         bp->status_blk = pci_alloc_consistent(bp->pdev,
417                                               sizeof(struct status_block),
418                                               &bp->status_blk_mapping);
419         if (bp->status_blk == NULL)
420                 goto alloc_mem_err;
421
422         memset(bp->status_blk, 0, sizeof(struct status_block));
423
424         bp->stats_blk = pci_alloc_consistent(bp->pdev,
425                                              sizeof(struct statistics_block),
426                                              &bp->stats_blk_mapping);
427         if (bp->stats_blk == NULL)
428                 goto alloc_mem_err;
429
430         memset(bp->stats_blk, 0, sizeof(struct statistics_block));
431
432         return 0;
433
434 alloc_mem_err:
435         bnx2_free_mem(bp);
436         return -ENOMEM;
437 }
438
439 static void
440 bnx2_report_fw_link(struct bnx2 *bp)
441 {
442         u32 fw_link_status = 0;
443
444         if (bp->link_up) {
445                 u32 bmsr;
446
447                 switch (bp->line_speed) {
448                 case SPEED_10:
449                         if (bp->duplex == DUPLEX_HALF)
450                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
451                         else
452                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
453                         break;
454                 case SPEED_100:
455                         if (bp->duplex == DUPLEX_HALF)
456                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
457                         else
458                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
459                         break;
460                 case SPEED_1000:
461                         if (bp->duplex == DUPLEX_HALF)
462                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
463                         else
464                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
465                         break;
466                 case SPEED_2500:
467                         if (bp->duplex == DUPLEX_HALF)
468                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
469                         else
470                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
471                         break;
472                 }
473
474                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
475
476                 if (bp->autoneg) {
477                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
478
479                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
480                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
481
482                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
483                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
484                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
485                         else
486                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
487                 }
488         }
489         else
490                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
491
492         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
493 }
494
495 static void
496 bnx2_report_link(struct bnx2 *bp)
497 {
498         if (bp->link_up) {
499                 netif_carrier_on(bp->dev);
500                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
501
502                 printk("%d Mbps ", bp->line_speed);
503
504                 if (bp->duplex == DUPLEX_FULL)
505                         printk("full duplex");
506                 else
507                         printk("half duplex");
508
509                 if (bp->flow_ctrl) {
510                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
511                                 printk(", receive ");
512                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
513                                         printk("& transmit ");
514                         }
515                         else {
516                                 printk(", transmit ");
517                         }
518                         printk("flow control ON");
519                 }
520                 printk("\n");
521         }
522         else {
523                 netif_carrier_off(bp->dev);
524                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
525         }
526
527         bnx2_report_fw_link(bp);
528 }
529
530 static void
531 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
532 {
533         u32 local_adv, remote_adv;
534
535         bp->flow_ctrl = 0;
536         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 
537                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
538
539                 if (bp->duplex == DUPLEX_FULL) {
540                         bp->flow_ctrl = bp->req_flow_ctrl;
541                 }
542                 return;
543         }
544
545         if (bp->duplex != DUPLEX_FULL) {
546                 return;
547         }
548
549         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
550             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
551                 u32 val;
552
553                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
554                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
555                         bp->flow_ctrl |= FLOW_CTRL_TX;
556                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
557                         bp->flow_ctrl |= FLOW_CTRL_RX;
558                 return;
559         }
560
561         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
562         bnx2_read_phy(bp, MII_LPA, &remote_adv);
563
564         if (bp->phy_flags & PHY_SERDES_FLAG) {
565                 u32 new_local_adv = 0;
566                 u32 new_remote_adv = 0;
567
568                 if (local_adv & ADVERTISE_1000XPAUSE)
569                         new_local_adv |= ADVERTISE_PAUSE_CAP;
570                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
571                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
572                 if (remote_adv & ADVERTISE_1000XPAUSE)
573                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
574                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
575                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
576
577                 local_adv = new_local_adv;
578                 remote_adv = new_remote_adv;
579         }
580
581         /* See Table 28B-3 of 802.3ab-1999 spec. */
582         if (local_adv & ADVERTISE_PAUSE_CAP) {
583                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
584                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
585                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
586                         }
587                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
588                                 bp->flow_ctrl = FLOW_CTRL_RX;
589                         }
590                 }
591                 else {
592                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
593                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
594                         }
595                 }
596         }
597         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
598                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
599                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
600
601                         bp->flow_ctrl = FLOW_CTRL_TX;
602                 }
603         }
604 }
605
606 static int
607 bnx2_5708s_linkup(struct bnx2 *bp)
608 {
609         u32 val;
610
611         bp->link_up = 1;
612         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
613         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
614                 case BCM5708S_1000X_STAT1_SPEED_10:
615                         bp->line_speed = SPEED_10;
616                         break;
617                 case BCM5708S_1000X_STAT1_SPEED_100:
618                         bp->line_speed = SPEED_100;
619                         break;
620                 case BCM5708S_1000X_STAT1_SPEED_1G:
621                         bp->line_speed = SPEED_1000;
622                         break;
623                 case BCM5708S_1000X_STAT1_SPEED_2G5:
624                         bp->line_speed = SPEED_2500;
625                         break;
626         }
627         if (val & BCM5708S_1000X_STAT1_FD)
628                 bp->duplex = DUPLEX_FULL;
629         else
630                 bp->duplex = DUPLEX_HALF;
631
632         return 0;
633 }
634
635 static int
636 bnx2_5706s_linkup(struct bnx2 *bp)
637 {
638         u32 bmcr, local_adv, remote_adv, common;
639
640         bp->link_up = 1;
641         bp->line_speed = SPEED_1000;
642
643         bnx2_read_phy(bp, MII_BMCR, &bmcr);
644         if (bmcr & BMCR_FULLDPLX) {
645                 bp->duplex = DUPLEX_FULL;
646         }
647         else {
648                 bp->duplex = DUPLEX_HALF;
649         }
650
651         if (!(bmcr & BMCR_ANENABLE)) {
652                 return 0;
653         }
654
655         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
656         bnx2_read_phy(bp, MII_LPA, &remote_adv);
657
658         common = local_adv & remote_adv;
659         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
660
661                 if (common & ADVERTISE_1000XFULL) {
662                         bp->duplex = DUPLEX_FULL;
663                 }
664                 else {
665                         bp->duplex = DUPLEX_HALF;
666                 }
667         }
668
669         return 0;
670 }
671
672 static int
673 bnx2_copper_linkup(struct bnx2 *bp)
674 {
675         u32 bmcr;
676
677         bnx2_read_phy(bp, MII_BMCR, &bmcr);
678         if (bmcr & BMCR_ANENABLE) {
679                 u32 local_adv, remote_adv, common;
680
681                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
682                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
683
684                 common = local_adv & (remote_adv >> 2);
685                 if (common & ADVERTISE_1000FULL) {
686                         bp->line_speed = SPEED_1000;
687                         bp->duplex = DUPLEX_FULL;
688                 }
689                 else if (common & ADVERTISE_1000HALF) {
690                         bp->line_speed = SPEED_1000;
691                         bp->duplex = DUPLEX_HALF;
692                 }
693                 else {
694                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
695                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
696
697                         common = local_adv & remote_adv;
698                         if (common & ADVERTISE_100FULL) {
699                                 bp->line_speed = SPEED_100;
700                                 bp->duplex = DUPLEX_FULL;
701                         }
702                         else if (common & ADVERTISE_100HALF) {
703                                 bp->line_speed = SPEED_100;
704                                 bp->duplex = DUPLEX_HALF;
705                         }
706                         else if (common & ADVERTISE_10FULL) {
707                                 bp->line_speed = SPEED_10;
708                                 bp->duplex = DUPLEX_FULL;
709                         }
710                         else if (common & ADVERTISE_10HALF) {
711                                 bp->line_speed = SPEED_10;
712                                 bp->duplex = DUPLEX_HALF;
713                         }
714                         else {
715                                 bp->line_speed = 0;
716                                 bp->link_up = 0;
717                         }
718                 }
719         }
720         else {
721                 if (bmcr & BMCR_SPEED100) {
722                         bp->line_speed = SPEED_100;
723                 }
724                 else {
725                         bp->line_speed = SPEED_10;
726                 }
727                 if (bmcr & BMCR_FULLDPLX) {
728                         bp->duplex = DUPLEX_FULL;
729                 }
730                 else {
731                         bp->duplex = DUPLEX_HALF;
732                 }
733         }
734
735         return 0;
736 }
737
738 static int
739 bnx2_set_mac_link(struct bnx2 *bp)
740 {
741         u32 val;
742
743         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
744         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
745                 (bp->duplex == DUPLEX_HALF)) {
746                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
747         }
748
749         /* Configure the EMAC mode register. */
750         val = REG_RD(bp, BNX2_EMAC_MODE);
751
752         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
753                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
754                 BNX2_EMAC_MODE_25G);
755
756         if (bp->link_up) {
757                 switch (bp->line_speed) {
758                         case SPEED_10:
759                                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
760                                         val |= BNX2_EMAC_MODE_PORT_MII_10;
761                                         break;
762                                 }
763                                 /* fall through */
764                         case SPEED_100:
765                                 val |= BNX2_EMAC_MODE_PORT_MII;
766                                 break;
767                         case SPEED_2500:
768                                 val |= BNX2_EMAC_MODE_25G;
769                                 /* fall through */
770                         case SPEED_1000:
771                                 val |= BNX2_EMAC_MODE_PORT_GMII;
772                                 break;
773                 }
774         }
775         else {
776                 val |= BNX2_EMAC_MODE_PORT_GMII;
777         }
778
779         /* Set the MAC to operate in the appropriate duplex mode. */
780         if (bp->duplex == DUPLEX_HALF)
781                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
782         REG_WR(bp, BNX2_EMAC_MODE, val);
783
784         /* Enable/disable rx PAUSE. */
785         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
786
787         if (bp->flow_ctrl & FLOW_CTRL_RX)
788                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
789         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
790
791         /* Enable/disable tx PAUSE. */
792         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
793         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
794
795         if (bp->flow_ctrl & FLOW_CTRL_TX)
796                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
797         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
798
799         /* Acknowledge the interrupt. */
800         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
801
802         return 0;
803 }
804
805 static int
806 bnx2_set_link(struct bnx2 *bp)
807 {
808         u32 bmsr;
809         u8 link_up;
810
811         if (bp->loopback == MAC_LOOPBACK) {
812                 bp->link_up = 1;
813                 return 0;
814         }
815
816         link_up = bp->link_up;
817
818         bnx2_read_phy(bp, MII_BMSR, &bmsr);
819         bnx2_read_phy(bp, MII_BMSR, &bmsr);
820
821         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
822             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
823                 u32 val;
824
825                 val = REG_RD(bp, BNX2_EMAC_STATUS);
826                 if (val & BNX2_EMAC_STATUS_LINK)
827                         bmsr |= BMSR_LSTATUS;
828                 else
829                         bmsr &= ~BMSR_LSTATUS;
830         }
831
832         if (bmsr & BMSR_LSTATUS) {
833                 bp->link_up = 1;
834
835                 if (bp->phy_flags & PHY_SERDES_FLAG) {
836                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
837                                 bnx2_5706s_linkup(bp);
838                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
839                                 bnx2_5708s_linkup(bp);
840                 }
841                 else {
842                         bnx2_copper_linkup(bp);
843                 }
844                 bnx2_resolve_flow_ctrl(bp);
845         }
846         else {
847                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
848                         (bp->autoneg & AUTONEG_SPEED)) {
849
850                         u32 bmcr;
851
852                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
853                         if (!(bmcr & BMCR_ANENABLE)) {
854                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
855                                         BMCR_ANENABLE);
856                         }
857                 }
858                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
859                 bp->link_up = 0;
860         }
861
862         if (bp->link_up != link_up) {
863                 bnx2_report_link(bp);
864         }
865
866         bnx2_set_mac_link(bp);
867
868         return 0;
869 }
870
871 static int
872 bnx2_reset_phy(struct bnx2 *bp)
873 {
874         int i;
875         u32 reg;
876
877         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
878
879 #define PHY_RESET_MAX_WAIT 100
880         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
881                 udelay(10);
882
883                 bnx2_read_phy(bp, MII_BMCR, &reg);
884                 if (!(reg & BMCR_RESET)) {
885                         udelay(20);
886                         break;
887                 }
888         }
889         if (i == PHY_RESET_MAX_WAIT) {
890                 return -EBUSY;
891         }
892         return 0;
893 }
894
895 static u32
896 bnx2_phy_get_pause_adv(struct bnx2 *bp)
897 {
898         u32 adv = 0;
899
900         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
901                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
902
903                 if (bp->phy_flags & PHY_SERDES_FLAG) {
904                         adv = ADVERTISE_1000XPAUSE;
905                 }
906                 else {
907                         adv = ADVERTISE_PAUSE_CAP;
908                 }
909         }
910         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
911                 if (bp->phy_flags & PHY_SERDES_FLAG) {
912                         adv = ADVERTISE_1000XPSE_ASYM;
913                 }
914                 else {
915                         adv = ADVERTISE_PAUSE_ASYM;
916                 }
917         }
918         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
919                 if (bp->phy_flags & PHY_SERDES_FLAG) {
920                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
921                 }
922                 else {
923                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
924                 }
925         }
926         return adv;
927 }
928
929 static int
930 bnx2_setup_serdes_phy(struct bnx2 *bp)
931 {
932         u32 adv, bmcr, up1;
933         u32 new_adv = 0;
934
935         if (!(bp->autoneg & AUTONEG_SPEED)) {
936                 u32 new_bmcr;
937                 int force_link_down = 0;
938
939                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
940                         bnx2_read_phy(bp, BCM5708S_UP1, &up1);
941                         if (up1 & BCM5708S_UP1_2G5) {
942                                 up1 &= ~BCM5708S_UP1_2G5;
943                                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
944                                 force_link_down = 1;
945                         }
946                 }
947
948                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
949                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
950
951                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
952                 new_bmcr = bmcr & ~BMCR_ANENABLE;
953                 new_bmcr |= BMCR_SPEED1000;
954                 if (bp->req_duplex == DUPLEX_FULL) {
955                         adv |= ADVERTISE_1000XFULL;
956                         new_bmcr |= BMCR_FULLDPLX;
957                 }
958                 else {
959                         adv |= ADVERTISE_1000XHALF;
960                         new_bmcr &= ~BMCR_FULLDPLX;
961                 }
962                 if ((new_bmcr != bmcr) || (force_link_down)) {
963                         /* Force a link down visible on the other side */
964                         if (bp->link_up) {
965                                 bnx2_write_phy(bp, MII_ADVERTISE, adv &
966                                                ~(ADVERTISE_1000XFULL |
967                                                  ADVERTISE_1000XHALF));
968                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
969                                         BMCR_ANRESTART | BMCR_ANENABLE);
970
971                                 bp->link_up = 0;
972                                 netif_carrier_off(bp->dev);
973                                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
974                         }
975                         bnx2_write_phy(bp, MII_ADVERTISE, adv);
976                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
977                 }
978                 return 0;
979         }
980
981         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
982                 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
983                 up1 |= BCM5708S_UP1_2G5;
984                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
985         }
986
987         if (bp->advertising & ADVERTISED_1000baseT_Full)
988                 new_adv |= ADVERTISE_1000XFULL;
989
990         new_adv |= bnx2_phy_get_pause_adv(bp);
991
992         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
993         bnx2_read_phy(bp, MII_BMCR, &bmcr);
994
995         bp->serdes_an_pending = 0;
996         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
997                 /* Force a link down visible on the other side */
998                 if (bp->link_up) {
999                         int i;
1000
1001                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1002                         for (i = 0; i < 110; i++) {
1003                                 udelay(100);
1004                         }
1005                 }
1006
1007                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1008                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1009                         BMCR_ANENABLE);
1010                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1011                         /* Speed up link-up time when the link partner
1012                          * does not autonegotiate which is very common
1013                          * in blade servers. Some blade servers use
1014                          * IPMI for kerboard input and it's important
1015                          * to minimize link disruptions. Autoneg. involves
1016                          * exchanging base pages plus 3 next pages and
1017                          * normally completes in about 120 msec.
1018                          */
1019                         bp->current_interval = SERDES_AN_TIMEOUT;
1020                         bp->serdes_an_pending = 1;
1021                         mod_timer(&bp->timer, jiffies + bp->current_interval);
1022                 }
1023         }
1024
1025         return 0;
1026 }
1027
1028 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1029         (ADVERTISED_1000baseT_Full)
1030
1031 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1032         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1033         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1034         ADVERTISED_1000baseT_Full)
1035
1036 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1037         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1038         
1039 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1040
1041 static int
1042 bnx2_setup_copper_phy(struct bnx2 *bp)
1043 {
1044         u32 bmcr;
1045         u32 new_bmcr;
1046
1047         bnx2_read_phy(bp, MII_BMCR, &bmcr);
1048
1049         if (bp->autoneg & AUTONEG_SPEED) {
1050                 u32 adv_reg, adv1000_reg;
1051                 u32 new_adv_reg = 0;
1052                 u32 new_adv1000_reg = 0;
1053
1054                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1055                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1056                         ADVERTISE_PAUSE_ASYM);
1057
1058                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1059                 adv1000_reg &= PHY_ALL_1000_SPEED;
1060
1061                 if (bp->advertising & ADVERTISED_10baseT_Half)
1062                         new_adv_reg |= ADVERTISE_10HALF;
1063                 if (bp->advertising & ADVERTISED_10baseT_Full)
1064                         new_adv_reg |= ADVERTISE_10FULL;
1065                 if (bp->advertising & ADVERTISED_100baseT_Half)
1066                         new_adv_reg |= ADVERTISE_100HALF;
1067                 if (bp->advertising & ADVERTISED_100baseT_Full)
1068                         new_adv_reg |= ADVERTISE_100FULL;
1069                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1070                         new_adv1000_reg |= ADVERTISE_1000FULL;
1071                 
1072                 new_adv_reg |= ADVERTISE_CSMA;
1073
1074                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1075
1076                 if ((adv1000_reg != new_adv1000_reg) ||
1077                         (adv_reg != new_adv_reg) ||
1078                         ((bmcr & BMCR_ANENABLE) == 0)) {
1079
1080                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1081                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1082                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1083                                 BMCR_ANENABLE);
1084                 }
1085                 else if (bp->link_up) {
1086                         /* Flow ctrl may have changed from auto to forced */
1087                         /* or vice-versa. */
1088
1089                         bnx2_resolve_flow_ctrl(bp);
1090                         bnx2_set_mac_link(bp);
1091                 }
1092                 return 0;
1093         }
1094
1095         new_bmcr = 0;
1096         if (bp->req_line_speed == SPEED_100) {
1097                 new_bmcr |= BMCR_SPEED100;
1098         }
1099         if (bp->req_duplex == DUPLEX_FULL) {
1100                 new_bmcr |= BMCR_FULLDPLX;
1101         }
1102         if (new_bmcr != bmcr) {
1103                 u32 bmsr;
1104                 int i = 0;
1105
1106                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1107                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1108                 
1109                 if (bmsr & BMSR_LSTATUS) {
1110                         /* Force link down */
1111                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1112                         do {
1113                                 udelay(100);
1114                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1115                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1116                                 i++;
1117                         } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1118                 }
1119
1120                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1121
1122                 /* Normally, the new speed is setup after the link has
1123                  * gone down and up again. In some cases, link will not go
1124                  * down so we need to set up the new speed here.
1125                  */
1126                 if (bmsr & BMSR_LSTATUS) {
1127                         bp->line_speed = bp->req_line_speed;
1128                         bp->duplex = bp->req_duplex;
1129                         bnx2_resolve_flow_ctrl(bp);
1130                         bnx2_set_mac_link(bp);
1131                 }
1132         }
1133         return 0;
1134 }
1135
1136 static int
1137 bnx2_setup_phy(struct bnx2 *bp)
1138 {
1139         if (bp->loopback == MAC_LOOPBACK)
1140                 return 0;
1141
1142         if (bp->phy_flags & PHY_SERDES_FLAG) {
1143                 return (bnx2_setup_serdes_phy(bp));
1144         }
1145         else {
1146                 return (bnx2_setup_copper_phy(bp));
1147         }
1148 }
1149
1150 static int
1151 bnx2_init_5708s_phy(struct bnx2 *bp)
1152 {
1153         u32 val;
1154
1155         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1156         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1157         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1158
1159         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1160         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1161         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1162
1163         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1164         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1165         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1166
1167         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1168                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1169                 val |= BCM5708S_UP1_2G5;
1170                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1171         }
1172
1173         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1174             (CHIP_ID(bp) == CHIP_ID_5708_B0)) {
1175                 /* increase tx signal amplitude */
1176                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1177                                BCM5708S_BLK_ADDR_TX_MISC);
1178                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1179                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1180                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1181                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1182         }
1183
1184         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1185               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1186
1187         if (val) {
1188                 u32 is_backplane;
1189
1190                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1191                                           BNX2_SHARED_HW_CFG_CONFIG);
1192                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1193                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1194                                        BCM5708S_BLK_ADDR_TX_MISC);
1195                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1196                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1197                                        BCM5708S_BLK_ADDR_DIG);
1198                 }
1199         }
1200         return 0;
1201 }
1202
1203 static int
1204 bnx2_init_5706s_phy(struct bnx2 *bp)
1205 {
1206         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1207
1208         if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1209                 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1210         }
1211
1212         if (bp->dev->mtu > 1500) {
1213                 u32 val;
1214
1215                 /* Set extended packet length bit */
1216                 bnx2_write_phy(bp, 0x18, 0x7);
1217                 bnx2_read_phy(bp, 0x18, &val);
1218                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1219
1220                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1221                 bnx2_read_phy(bp, 0x1c, &val);
1222                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1223         }
1224         else {
1225                 u32 val;
1226
1227                 bnx2_write_phy(bp, 0x18, 0x7);
1228                 bnx2_read_phy(bp, 0x18, &val);
1229                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1230
1231                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1232                 bnx2_read_phy(bp, 0x1c, &val);
1233                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1234         }
1235
1236         return 0;
1237 }
1238
1239 static int
1240 bnx2_init_copper_phy(struct bnx2 *bp)
1241 {
1242         u32 val;
1243
1244         bp->phy_flags |= PHY_CRC_FIX_FLAG;
1245
1246         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1247                 bnx2_write_phy(bp, 0x18, 0x0c00);
1248                 bnx2_write_phy(bp, 0x17, 0x000a);
1249                 bnx2_write_phy(bp, 0x15, 0x310b);
1250                 bnx2_write_phy(bp, 0x17, 0x201f);
1251                 bnx2_write_phy(bp, 0x15, 0x9506);
1252                 bnx2_write_phy(bp, 0x17, 0x401f);
1253                 bnx2_write_phy(bp, 0x15, 0x14e2);
1254                 bnx2_write_phy(bp, 0x18, 0x0400);
1255         }
1256
1257         if (bp->dev->mtu > 1500) {
1258                 /* Set extended packet length bit */
1259                 bnx2_write_phy(bp, 0x18, 0x7);
1260                 bnx2_read_phy(bp, 0x18, &val);
1261                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1262
1263                 bnx2_read_phy(bp, 0x10, &val);
1264                 bnx2_write_phy(bp, 0x10, val | 0x1);
1265         }
1266         else {
1267                 bnx2_write_phy(bp, 0x18, 0x7);
1268                 bnx2_read_phy(bp, 0x18, &val);
1269                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1270
1271                 bnx2_read_phy(bp, 0x10, &val);
1272                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1273         }
1274
1275         /* ethernet@wirespeed */
1276         bnx2_write_phy(bp, 0x18, 0x7007);
1277         bnx2_read_phy(bp, 0x18, &val);
1278         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1279         return 0;
1280 }
1281
1282
1283 static int
1284 bnx2_init_phy(struct bnx2 *bp)
1285 {
1286         u32 val;
1287         int rc = 0;
1288
1289         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1290         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1291
1292         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1293
1294         bnx2_reset_phy(bp);
1295
1296         bnx2_read_phy(bp, MII_PHYSID1, &val);
1297         bp->phy_id = val << 16;
1298         bnx2_read_phy(bp, MII_PHYSID2, &val);
1299         bp->phy_id |= val & 0xffff;
1300
1301         if (bp->phy_flags & PHY_SERDES_FLAG) {
1302                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1303                         rc = bnx2_init_5706s_phy(bp);
1304                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1305                         rc = bnx2_init_5708s_phy(bp);
1306         }
1307         else {
1308                 rc = bnx2_init_copper_phy(bp);
1309         }
1310
1311         bnx2_setup_phy(bp);
1312
1313         return rc;
1314 }
1315
1316 static int
1317 bnx2_set_mac_loopback(struct bnx2 *bp)
1318 {
1319         u32 mac_mode;
1320
1321         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1322         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1323         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1324         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1325         bp->link_up = 1;
1326         return 0;
1327 }
1328
1329 static int
1330 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1331 {
1332         int i;
1333         u32 val;
1334
1335         bp->fw_wr_seq++;
1336         msg_data |= bp->fw_wr_seq;
1337
1338         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1339
1340         /* wait for an acknowledgement. */
1341         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1342                 msleep(10);
1343
1344                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1345
1346                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1347                         break;
1348         }
1349         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1350                 return 0;
1351
1352         /* If we timed out, inform the firmware that this is the case. */
1353         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1354                 if (!silent)
1355                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
1356                                             "%x\n", msg_data);
1357
1358                 msg_data &= ~BNX2_DRV_MSG_CODE;
1359                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1360
1361                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1362
1363                 return -EBUSY;
1364         }
1365
1366         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1367                 return -EIO;
1368
1369         return 0;
1370 }
1371
1372 static void
1373 bnx2_init_context(struct bnx2 *bp)
1374 {
1375         u32 vcid;
1376
1377         vcid = 96;
1378         while (vcid) {
1379                 u32 vcid_addr, pcid_addr, offset;
1380
1381                 vcid--;
1382
1383                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1384                         u32 new_vcid;
1385
1386                         vcid_addr = GET_PCID_ADDR(vcid);
1387                         if (vcid & 0x8) {
1388                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1389                         }
1390                         else {
1391                                 new_vcid = vcid;
1392                         }
1393                         pcid_addr = GET_PCID_ADDR(new_vcid);
1394                 }
1395                 else {
1396                         vcid_addr = GET_CID_ADDR(vcid);
1397                         pcid_addr = vcid_addr;
1398                 }
1399
1400                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1401                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1402
1403                 /* Zero out the context. */
1404                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1405                         CTX_WR(bp, 0x00, offset, 0);
1406                 }
1407
1408                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1409                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1410         }
1411 }
1412
1413 static int
1414 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1415 {
1416         u16 *good_mbuf;
1417         u32 good_mbuf_cnt;
1418         u32 val;
1419
1420         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1421         if (good_mbuf == NULL) {
1422                 printk(KERN_ERR PFX "Failed to allocate memory in "
1423                                     "bnx2_alloc_bad_rbuf\n");
1424                 return -ENOMEM;
1425         }
1426
1427         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1428                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1429
1430         good_mbuf_cnt = 0;
1431
1432         /* Allocate a bunch of mbufs and save the good ones in an array. */
1433         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1434         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1435                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1436
1437                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1438
1439                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1440
1441                 /* The addresses with Bit 9 set are bad memory blocks. */
1442                 if (!(val & (1 << 9))) {
1443                         good_mbuf[good_mbuf_cnt] = (u16) val;
1444                         good_mbuf_cnt++;
1445                 }
1446
1447                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1448         }
1449
1450         /* Free the good ones back to the mbuf pool thus discarding
1451          * all the bad ones. */
1452         while (good_mbuf_cnt) {
1453                 good_mbuf_cnt--;
1454
1455                 val = good_mbuf[good_mbuf_cnt];
1456                 val = (val << 9) | val | 1;
1457
1458                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1459         }
1460         kfree(good_mbuf);
1461         return 0;
1462 }
1463
1464 static void
1465 bnx2_set_mac_addr(struct bnx2 *bp) 
1466 {
1467         u32 val;
1468         u8 *mac_addr = bp->dev->dev_addr;
1469
1470         val = (mac_addr[0] << 8) | mac_addr[1];
1471
1472         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1473
1474         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 
1475                 (mac_addr[4] << 8) | mac_addr[5];
1476
1477         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1478 }
1479
1480 static inline int
1481 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1482 {
1483         struct sk_buff *skb;
1484         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1485         dma_addr_t mapping;
1486         struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1487         unsigned long align;
1488
1489         skb = dev_alloc_skb(bp->rx_buf_size);
1490         if (skb == NULL) {
1491                 return -ENOMEM;
1492         }
1493
1494         if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1495                 skb_reserve(skb, 8 - align);
1496         }
1497
1498         skb->dev = bp->dev;
1499         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1500                 PCI_DMA_FROMDEVICE);
1501
1502         rx_buf->skb = skb;
1503         pci_unmap_addr_set(rx_buf, mapping, mapping);
1504
1505         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1506         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1507
1508         bp->rx_prod_bseq += bp->rx_buf_use_size;
1509
1510         return 0;
1511 }
1512
1513 static void
1514 bnx2_phy_int(struct bnx2 *bp)
1515 {
1516         u32 new_link_state, old_link_state;
1517
1518         new_link_state = bp->status_blk->status_attn_bits &
1519                 STATUS_ATTN_BITS_LINK_STATE;
1520         old_link_state = bp->status_blk->status_attn_bits_ack &
1521                 STATUS_ATTN_BITS_LINK_STATE;
1522         if (new_link_state != old_link_state) {
1523                 if (new_link_state) {
1524                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1525                                 STATUS_ATTN_BITS_LINK_STATE);
1526                 }
1527                 else {
1528                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1529                                 STATUS_ATTN_BITS_LINK_STATE);
1530                 }
1531                 bnx2_set_link(bp);
1532         }
1533 }
1534
1535 static void
1536 bnx2_tx_int(struct bnx2 *bp)
1537 {
1538         struct status_block *sblk = bp->status_blk;
1539         u16 hw_cons, sw_cons, sw_ring_cons;
1540         int tx_free_bd = 0;
1541
1542         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1543         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1544                 hw_cons++;
1545         }
1546         sw_cons = bp->tx_cons;
1547
1548         while (sw_cons != hw_cons) {
1549                 struct sw_bd *tx_buf;
1550                 struct sk_buff *skb;
1551                 int i, last;
1552
1553                 sw_ring_cons = TX_RING_IDX(sw_cons);
1554
1555                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1556                 skb = tx_buf->skb;
1557 #ifdef BCM_TSO 
1558                 /* partial BD completions possible with TSO packets */
1559                 if (skb_shinfo(skb)->tso_size) {
1560                         u16 last_idx, last_ring_idx;
1561
1562                         last_idx = sw_cons +
1563                                 skb_shinfo(skb)->nr_frags + 1;
1564                         last_ring_idx = sw_ring_cons +
1565                                 skb_shinfo(skb)->nr_frags + 1;
1566                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1567                                 last_idx++;
1568                         }
1569                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1570                                 break;
1571                         }
1572                 }
1573 #endif
1574                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1575                         skb_headlen(skb), PCI_DMA_TODEVICE);
1576
1577                 tx_buf->skb = NULL;
1578                 last = skb_shinfo(skb)->nr_frags;
1579
1580                 for (i = 0; i < last; i++) {
1581                         sw_cons = NEXT_TX_BD(sw_cons);
1582
1583                         pci_unmap_page(bp->pdev,
1584                                 pci_unmap_addr(
1585                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1586                                         mapping),
1587                                 skb_shinfo(skb)->frags[i].size,
1588                                 PCI_DMA_TODEVICE);
1589                 }
1590
1591                 sw_cons = NEXT_TX_BD(sw_cons);
1592
1593                 tx_free_bd += last + 1;
1594
1595                 dev_kfree_skb_irq(skb);
1596
1597                 hw_cons = bp->hw_tx_cons =
1598                         sblk->status_tx_quick_consumer_index0;
1599
1600                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1601                         hw_cons++;
1602                 }
1603         }
1604
1605         bp->tx_cons = sw_cons;
1606
1607         if (unlikely(netif_queue_stopped(bp->dev))) {
1608                 spin_lock(&bp->tx_lock);
1609                 if ((netif_queue_stopped(bp->dev)) &&
1610                     (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1611
1612                         netif_wake_queue(bp->dev);
1613                 }
1614                 spin_unlock(&bp->tx_lock);
1615         }
1616 }
1617
1618 static inline void
1619 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1620         u16 cons, u16 prod)
1621 {
1622         struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1623         struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1624         struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1625         struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1626
1627         pci_dma_sync_single_for_device(bp->pdev,
1628                 pci_unmap_addr(cons_rx_buf, mapping),
1629                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1630
1631         prod_rx_buf->skb = cons_rx_buf->skb;
1632         pci_unmap_addr_set(prod_rx_buf, mapping,
1633                         pci_unmap_addr(cons_rx_buf, mapping));
1634
1635         memcpy(prod_bd, cons_bd, 8);
1636
1637         bp->rx_prod_bseq += bp->rx_buf_use_size;
1638
1639 }
1640
1641 static int
1642 bnx2_rx_int(struct bnx2 *bp, int budget)
1643 {
1644         struct status_block *sblk = bp->status_blk;
1645         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1646         struct l2_fhdr *rx_hdr;
1647         int rx_pkt = 0;
1648
1649         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1650         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1651                 hw_cons++;
1652         }
1653         sw_cons = bp->rx_cons;
1654         sw_prod = bp->rx_prod;
1655
1656         /* Memory barrier necessary as speculative reads of the rx
1657          * buffer can be ahead of the index in the status block
1658          */
1659         rmb();
1660         while (sw_cons != hw_cons) {
1661                 unsigned int len;
1662                 u16 status;
1663                 struct sw_bd *rx_buf;
1664                 struct sk_buff *skb;
1665
1666                 sw_ring_cons = RX_RING_IDX(sw_cons);
1667                 sw_ring_prod = RX_RING_IDX(sw_prod);
1668
1669                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1670                 skb = rx_buf->skb;
1671                 pci_dma_sync_single_for_cpu(bp->pdev,
1672                         pci_unmap_addr(rx_buf, mapping),
1673                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1674
1675                 rx_hdr = (struct l2_fhdr *) skb->data;
1676                 len = rx_hdr->l2_fhdr_pkt_len - 4;
1677
1678                 if (rx_hdr->l2_fhdr_errors &
1679                         (L2_FHDR_ERRORS_BAD_CRC |
1680                         L2_FHDR_ERRORS_PHY_DECODE |
1681                         L2_FHDR_ERRORS_ALIGNMENT |
1682                         L2_FHDR_ERRORS_TOO_SHORT |
1683                         L2_FHDR_ERRORS_GIANT_FRAME)) {
1684
1685                         goto reuse_rx;
1686                 }
1687
1688                 /* Since we don't have a jumbo ring, copy small packets
1689                  * if mtu > 1500
1690                  */
1691                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1692                         struct sk_buff *new_skb;
1693
1694                         new_skb = dev_alloc_skb(len + 2);
1695                         if (new_skb == NULL)
1696                                 goto reuse_rx;
1697
1698                         /* aligned copy */
1699                         memcpy(new_skb->data,
1700                                 skb->data + bp->rx_offset - 2,
1701                                 len + 2);
1702
1703                         skb_reserve(new_skb, 2);
1704                         skb_put(new_skb, len);
1705                         new_skb->dev = bp->dev;
1706
1707                         bnx2_reuse_rx_skb(bp, skb,
1708                                 sw_ring_cons, sw_ring_prod);
1709
1710                         skb = new_skb;
1711                 }
1712                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1713                         pci_unmap_single(bp->pdev,
1714                                 pci_unmap_addr(rx_buf, mapping),
1715                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1716
1717                         skb_reserve(skb, bp->rx_offset);
1718                         skb_put(skb, len);
1719                 }
1720                 else {
1721 reuse_rx:
1722                         bnx2_reuse_rx_skb(bp, skb,
1723                                 sw_ring_cons, sw_ring_prod);
1724                         goto next_rx;
1725                 }
1726
1727                 skb->protocol = eth_type_trans(skb, bp->dev);
1728
1729                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1730                         (htons(skb->protocol) != 0x8100)) {
1731
1732                         dev_kfree_skb_irq(skb);
1733                         goto next_rx;
1734
1735                 }
1736
1737                 status = rx_hdr->l2_fhdr_status;
1738                 skb->ip_summed = CHECKSUM_NONE;
1739                 if (bp->rx_csum &&
1740                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1741                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
1742
1743                         u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1744
1745                         if (cksum == 0xffff)
1746                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1747                 }
1748
1749 #ifdef BCM_VLAN
1750                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1751                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1752                                 rx_hdr->l2_fhdr_vlan_tag);
1753                 }
1754                 else
1755 #endif
1756                         netif_receive_skb(skb);
1757
1758                 bp->dev->last_rx = jiffies;
1759                 rx_pkt++;
1760
1761 next_rx:
1762                 rx_buf->skb = NULL;
1763
1764                 sw_cons = NEXT_RX_BD(sw_cons);
1765                 sw_prod = NEXT_RX_BD(sw_prod);
1766
1767                 if ((rx_pkt == budget))
1768                         break;
1769
1770                 /* Refresh hw_cons to see if there is new work */
1771                 if (sw_cons == hw_cons) {
1772                         hw_cons = bp->hw_rx_cons =
1773                                 sblk->status_rx_quick_consumer_index0;
1774                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1775                                 hw_cons++;
1776                         rmb();
1777                 }
1778         }
1779         bp->rx_cons = sw_cons;
1780         bp->rx_prod = sw_prod;
1781
1782         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1783
1784         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1785
1786         mmiowb();
1787
1788         return rx_pkt;
1789
1790 }
1791
1792 /* MSI ISR - The only difference between this and the INTx ISR
1793  * is that the MSI interrupt is always serviced.
1794  */
1795 static irqreturn_t
1796 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1797 {
1798         struct net_device *dev = dev_instance;
1799         struct bnx2 *bp = dev->priv;
1800
1801         prefetch(bp->status_blk);
1802         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1803                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1804                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1805
1806         /* Return here if interrupt is disabled. */
1807         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1808                 return IRQ_HANDLED;
1809
1810         netif_rx_schedule(dev);
1811
1812         return IRQ_HANDLED;
1813 }
1814
1815 static irqreturn_t
1816 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1817 {
1818         struct net_device *dev = dev_instance;
1819         struct bnx2 *bp = dev->priv;
1820
1821         /* When using INTx, it is possible for the interrupt to arrive
1822          * at the CPU before the status block posted prior to the
1823          * interrupt. Reading a register will flush the status block.
1824          * When using MSI, the MSI message will always complete after
1825          * the status block write.
1826          */
1827         if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1828             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1829              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1830                 return IRQ_NONE;
1831
1832         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1833                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1834                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1835
1836         /* Return here if interrupt is shared and is disabled. */
1837         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1838                 return IRQ_HANDLED;
1839
1840         netif_rx_schedule(dev);
1841
1842         return IRQ_HANDLED;
1843 }
1844
1845 static inline int
1846 bnx2_has_work(struct bnx2 *bp)
1847 {
1848         struct status_block *sblk = bp->status_blk;
1849
1850         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1851             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1852                 return 1;
1853
1854         if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1855             bp->link_up)
1856                 return 1;
1857
1858         return 0;
1859 }
1860
1861 static int
1862 bnx2_poll(struct net_device *dev, int *budget)
1863 {
1864         struct bnx2 *bp = dev->priv;
1865
1866         if ((bp->status_blk->status_attn_bits &
1867                 STATUS_ATTN_BITS_LINK_STATE) !=
1868                 (bp->status_blk->status_attn_bits_ack &
1869                 STATUS_ATTN_BITS_LINK_STATE)) {
1870
1871                 spin_lock(&bp->phy_lock);
1872                 bnx2_phy_int(bp);
1873                 spin_unlock(&bp->phy_lock);
1874         }
1875
1876         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
1877                 bnx2_tx_int(bp);
1878
1879         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
1880                 int orig_budget = *budget;
1881                 int work_done;
1882
1883                 if (orig_budget > dev->quota)
1884                         orig_budget = dev->quota;
1885                 
1886                 work_done = bnx2_rx_int(bp, orig_budget);
1887                 *budget -= work_done;
1888                 dev->quota -= work_done;
1889         }
1890         
1891         bp->last_status_idx = bp->status_blk->status_idx;
1892         rmb();
1893
1894         if (!bnx2_has_work(bp)) {
1895                 netif_rx_complete(dev);
1896                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1897                         BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1898                         bp->last_status_idx);
1899                 return 0;
1900         }
1901
1902         return 1;
1903 }
1904
1905 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1906  * from set_multicast.
1907  */
1908 static void
1909 bnx2_set_rx_mode(struct net_device *dev)
1910 {
1911         struct bnx2 *bp = dev->priv;
1912         u32 rx_mode, sort_mode;
1913         int i;
1914
1915         spin_lock_bh(&bp->phy_lock);
1916
1917         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1918                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1919         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1920 #ifdef BCM_VLAN
1921         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
1922                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1923 #else
1924         if (!(bp->flags & ASF_ENABLE_FLAG))
1925                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1926 #endif
1927         if (dev->flags & IFF_PROMISC) {
1928                 /* Promiscuous mode. */
1929                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1930                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1931         }
1932         else if (dev->flags & IFF_ALLMULTI) {
1933                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1934                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1935                                0xffffffff);
1936                 }
1937                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1938         }
1939         else {
1940                 /* Accept one or more multicast(s). */
1941                 struct dev_mc_list *mclist;
1942                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1943                 u32 regidx;
1944                 u32 bit;
1945                 u32 crc;
1946
1947                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1948
1949                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1950                      i++, mclist = mclist->next) {
1951
1952                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1953                         bit = crc & 0xff;
1954                         regidx = (bit & 0xe0) >> 5;
1955                         bit &= 0x1f;
1956                         mc_filter[regidx] |= (1 << bit);
1957                 }
1958
1959                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1960                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1961                                mc_filter[i]);
1962                 }
1963
1964                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1965         }
1966
1967         if (rx_mode != bp->rx_mode) {
1968                 bp->rx_mode = rx_mode;
1969                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1970         }
1971
1972         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1973         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1974         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1975
1976         spin_unlock_bh(&bp->phy_lock);
1977 }
1978
1979 static void
1980 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1981         u32 rv2p_proc)
1982 {
1983         int i;
1984         u32 val;
1985
1986
1987         for (i = 0; i < rv2p_code_len; i += 8) {
1988                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1989                 rv2p_code++;
1990                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1991                 rv2p_code++;
1992
1993                 if (rv2p_proc == RV2P_PROC1) {
1994                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1995                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1996                 }
1997                 else {
1998                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1999                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2000                 }
2001         }
2002
2003         /* Reset the processor, un-stall is done later. */
2004         if (rv2p_proc == RV2P_PROC1) {
2005                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2006         }
2007         else {
2008                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2009         }
2010 }
2011
2012 static void
2013 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2014 {
2015         u32 offset;
2016         u32 val;
2017
2018         /* Halt the CPU. */
2019         val = REG_RD_IND(bp, cpu_reg->mode);
2020         val |= cpu_reg->mode_value_halt;
2021         REG_WR_IND(bp, cpu_reg->mode, val);
2022         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2023
2024         /* Load the Text area. */
2025         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2026         if (fw->text) {
2027                 int j;
2028
2029                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2030                         REG_WR_IND(bp, offset, fw->text[j]);
2031                 }
2032         }
2033
2034         /* Load the Data area. */
2035         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2036         if (fw->data) {
2037                 int j;
2038
2039                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2040                         REG_WR_IND(bp, offset, fw->data[j]);
2041                 }
2042         }
2043
2044         /* Load the SBSS area. */
2045         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2046         if (fw->sbss) {
2047                 int j;
2048
2049                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2050                         REG_WR_IND(bp, offset, fw->sbss[j]);
2051                 }
2052         }
2053
2054         /* Load the BSS area. */
2055         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2056         if (fw->bss) {
2057                 int j;
2058
2059                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2060                         REG_WR_IND(bp, offset, fw->bss[j]);
2061                 }
2062         }
2063
2064         /* Load the Read-Only area. */
2065         offset = cpu_reg->spad_base +
2066                 (fw->rodata_addr - cpu_reg->mips_view_base);
2067         if (fw->rodata) {
2068                 int j;
2069
2070                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2071                         REG_WR_IND(bp, offset, fw->rodata[j]);
2072                 }
2073         }
2074
2075         /* Clear the pre-fetch instruction. */
2076         REG_WR_IND(bp, cpu_reg->inst, 0);
2077         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2078
2079         /* Start the CPU. */
2080         val = REG_RD_IND(bp, cpu_reg->mode);
2081         val &= ~cpu_reg->mode_value_halt;
2082         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2083         REG_WR_IND(bp, cpu_reg->mode, val);
2084 }
2085
2086 static void
2087 bnx2_init_cpus(struct bnx2 *bp)
2088 {
2089         struct cpu_reg cpu_reg;
2090         struct fw_info fw;
2091
2092         /* Initialize the RV2P processor. */
2093         load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2094         load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2095
2096         /* Initialize the RX Processor. */
2097         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2098         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2099         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2100         cpu_reg.state = BNX2_RXP_CPU_STATE;
2101         cpu_reg.state_value_clear = 0xffffff;
2102         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2103         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2104         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2105         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2106         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2107         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2108         cpu_reg.mips_view_base = 0x8000000;
2109     
2110         fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2111         fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2112         fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2113         fw.start_addr = bnx2_RXP_b06FwStartAddr;
2114
2115         fw.text_addr = bnx2_RXP_b06FwTextAddr;
2116         fw.text_len = bnx2_RXP_b06FwTextLen;
2117         fw.text_index = 0;
2118         fw.text = bnx2_RXP_b06FwText;
2119
2120         fw.data_addr = bnx2_RXP_b06FwDataAddr;
2121         fw.data_len = bnx2_RXP_b06FwDataLen;
2122         fw.data_index = 0;
2123         fw.data = bnx2_RXP_b06FwData;
2124
2125         fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2126         fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2127         fw.sbss_index = 0;
2128         fw.sbss = bnx2_RXP_b06FwSbss;
2129
2130         fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2131         fw.bss_len = bnx2_RXP_b06FwBssLen;
2132         fw.bss_index = 0;
2133         fw.bss = bnx2_RXP_b06FwBss;
2134
2135         fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2136         fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2137         fw.rodata_index = 0;
2138         fw.rodata = bnx2_RXP_b06FwRodata;
2139
2140         load_cpu_fw(bp, &cpu_reg, &fw);
2141
2142         /* Initialize the TX Processor. */
2143         cpu_reg.mode = BNX2_TXP_CPU_MODE;
2144         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2145         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2146         cpu_reg.state = BNX2_TXP_CPU_STATE;
2147         cpu_reg.state_value_clear = 0xffffff;
2148         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2149         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2150         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2151         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2152         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2153         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2154         cpu_reg.mips_view_base = 0x8000000;
2155     
2156         fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2157         fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2158         fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2159         fw.start_addr = bnx2_TXP_b06FwStartAddr;
2160
2161         fw.text_addr = bnx2_TXP_b06FwTextAddr;
2162         fw.text_len = bnx2_TXP_b06FwTextLen;
2163         fw.text_index = 0;
2164         fw.text = bnx2_TXP_b06FwText;
2165
2166         fw.data_addr = bnx2_TXP_b06FwDataAddr;
2167         fw.data_len = bnx2_TXP_b06FwDataLen;
2168         fw.data_index = 0;
2169         fw.data = bnx2_TXP_b06FwData;
2170
2171         fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2172         fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2173         fw.sbss_index = 0;
2174         fw.sbss = bnx2_TXP_b06FwSbss;
2175
2176         fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2177         fw.bss_len = bnx2_TXP_b06FwBssLen;
2178         fw.bss_index = 0;
2179         fw.bss = bnx2_TXP_b06FwBss;
2180
2181         fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2182         fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2183         fw.rodata_index = 0;
2184         fw.rodata = bnx2_TXP_b06FwRodata;
2185
2186         load_cpu_fw(bp, &cpu_reg, &fw);
2187
2188         /* Initialize the TX Patch-up Processor. */
2189         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2190         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2191         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2192         cpu_reg.state = BNX2_TPAT_CPU_STATE;
2193         cpu_reg.state_value_clear = 0xffffff;
2194         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2195         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2196         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2197         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2198         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2199         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2200         cpu_reg.mips_view_base = 0x8000000;
2201     
2202         fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2203         fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2204         fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2205         fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2206
2207         fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2208         fw.text_len = bnx2_TPAT_b06FwTextLen;
2209         fw.text_index = 0;
2210         fw.text = bnx2_TPAT_b06FwText;
2211
2212         fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2213         fw.data_len = bnx2_TPAT_b06FwDataLen;
2214         fw.data_index = 0;
2215         fw.data = bnx2_TPAT_b06FwData;
2216
2217         fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2218         fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2219         fw.sbss_index = 0;
2220         fw.sbss = bnx2_TPAT_b06FwSbss;
2221
2222         fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2223         fw.bss_len = bnx2_TPAT_b06FwBssLen;
2224         fw.bss_index = 0;
2225         fw.bss = bnx2_TPAT_b06FwBss;
2226
2227         fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2228         fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2229         fw.rodata_index = 0;
2230         fw.rodata = bnx2_TPAT_b06FwRodata;
2231
2232         load_cpu_fw(bp, &cpu_reg, &fw);
2233
2234         /* Initialize the Completion Processor. */
2235         cpu_reg.mode = BNX2_COM_CPU_MODE;
2236         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2237         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2238         cpu_reg.state = BNX2_COM_CPU_STATE;
2239         cpu_reg.state_value_clear = 0xffffff;
2240         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2241         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2242         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2243         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2244         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2245         cpu_reg.spad_base = BNX2_COM_SCRATCH;
2246         cpu_reg.mips_view_base = 0x8000000;
2247     
2248         fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2249         fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2250         fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2251         fw.start_addr = bnx2_COM_b06FwStartAddr;
2252
2253         fw.text_addr = bnx2_COM_b06FwTextAddr;
2254         fw.text_len = bnx2_COM_b06FwTextLen;
2255         fw.text_index = 0;
2256         fw.text = bnx2_COM_b06FwText;
2257
2258         fw.data_addr = bnx2_COM_b06FwDataAddr;
2259         fw.data_len = bnx2_COM_b06FwDataLen;
2260         fw.data_index = 0;
2261         fw.data = bnx2_COM_b06FwData;
2262
2263         fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2264         fw.sbss_len = bnx2_COM_b06FwSbssLen;
2265         fw.sbss_index = 0;
2266         fw.sbss = bnx2_COM_b06FwSbss;
2267
2268         fw.bss_addr = bnx2_COM_b06FwBssAddr;
2269         fw.bss_len = bnx2_COM_b06FwBssLen;
2270         fw.bss_index = 0;
2271         fw.bss = bnx2_COM_b06FwBss;
2272
2273         fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2274         fw.rodata_len = bnx2_COM_b06FwRodataLen;
2275         fw.rodata_index = 0;
2276         fw.rodata = bnx2_COM_b06FwRodata;
2277
2278         load_cpu_fw(bp, &cpu_reg, &fw);
2279
2280 }
2281
2282 static int
2283 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2284 {
2285         u16 pmcsr;
2286
2287         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2288
2289         switch (state) {
2290         case PCI_D0: {
2291                 u32 val;
2292
2293                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2294                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2295                         PCI_PM_CTRL_PME_STATUS);
2296
2297                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2298                         /* delay required during transition out of D3hot */
2299                         msleep(20);
2300
2301                 val = REG_RD(bp, BNX2_EMAC_MODE);
2302                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2303                 val &= ~BNX2_EMAC_MODE_MPKT;
2304                 REG_WR(bp, BNX2_EMAC_MODE, val);
2305
2306                 val = REG_RD(bp, BNX2_RPM_CONFIG);
2307                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2308                 REG_WR(bp, BNX2_RPM_CONFIG, val);
2309                 break;
2310         }
2311         case PCI_D3hot: {
2312                 int i;
2313                 u32 val, wol_msg;
2314
2315                 if (bp->wol) {
2316                         u32 advertising;
2317                         u8 autoneg;
2318
2319                         autoneg = bp->autoneg;
2320                         advertising = bp->advertising;
2321
2322                         bp->autoneg = AUTONEG_SPEED;
2323                         bp->advertising = ADVERTISED_10baseT_Half |
2324                                 ADVERTISED_10baseT_Full |
2325                                 ADVERTISED_100baseT_Half |
2326                                 ADVERTISED_100baseT_Full |
2327                                 ADVERTISED_Autoneg;
2328
2329                         bnx2_setup_copper_phy(bp);
2330
2331                         bp->autoneg = autoneg;
2332                         bp->advertising = advertising;
2333
2334                         bnx2_set_mac_addr(bp);
2335
2336                         val = REG_RD(bp, BNX2_EMAC_MODE);
2337
2338                         /* Enable port mode. */
2339                         val &= ~BNX2_EMAC_MODE_PORT;
2340                         val |= BNX2_EMAC_MODE_PORT_MII |
2341                                BNX2_EMAC_MODE_MPKT_RCVD |
2342                                BNX2_EMAC_MODE_ACPI_RCVD |
2343                                BNX2_EMAC_MODE_FORCE_LINK |
2344                                BNX2_EMAC_MODE_MPKT;
2345
2346                         REG_WR(bp, BNX2_EMAC_MODE, val);
2347
2348                         /* receive all multicast */
2349                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2350                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2351                                        0xffffffff);
2352                         }
2353                         REG_WR(bp, BNX2_EMAC_RX_MODE,
2354                                BNX2_EMAC_RX_MODE_SORT_MODE);
2355
2356                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2357                               BNX2_RPM_SORT_USER0_MC_EN;
2358                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2359                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2360                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2361                                BNX2_RPM_SORT_USER0_ENA);
2362
2363                         /* Need to enable EMAC and RPM for WOL. */
2364                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2365                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2366                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2367                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2368
2369                         val = REG_RD(bp, BNX2_RPM_CONFIG);
2370                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2371                         REG_WR(bp, BNX2_RPM_CONFIG, val);
2372
2373                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2374                 }
2375                 else {
2376                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2377                 }
2378
2379                 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2380
2381                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2382                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2383                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2384
2385                         if (bp->wol)
2386                                 pmcsr |= 3;
2387                 }
2388                 else {
2389                         pmcsr |= 3;
2390                 }
2391                 if (bp->wol) {
2392                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2393                 }
2394                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2395                                       pmcsr);
2396
2397                 /* No more memory access after this point until
2398                  * device is brought back to D0.
2399                  */
2400                 udelay(50);
2401                 break;
2402         }
2403         default:
2404                 return -EINVAL;
2405         }
2406         return 0;
2407 }
2408
2409 static int
2410 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2411 {
2412         u32 val;
2413         int j;
2414
2415         /* Request access to the flash interface. */
2416         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2417         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2418                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2419                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2420                         break;
2421
2422                 udelay(5);
2423         }
2424
2425         if (j >= NVRAM_TIMEOUT_COUNT)
2426                 return -EBUSY;
2427
2428         return 0;
2429 }
2430
2431 static int
2432 bnx2_release_nvram_lock(struct bnx2 *bp)
2433 {
2434         int j;
2435         u32 val;
2436
2437         /* Relinquish nvram interface. */
2438         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2439
2440         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2441                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2442                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2443                         break;
2444
2445                 udelay(5);
2446         }
2447
2448         if (j >= NVRAM_TIMEOUT_COUNT)
2449                 return -EBUSY;
2450
2451         return 0;
2452 }
2453
2454
2455 static int
2456 bnx2_enable_nvram_write(struct bnx2 *bp)
2457 {
2458         u32 val;
2459
2460         val = REG_RD(bp, BNX2_MISC_CFG);
2461         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2462
2463         if (!bp->flash_info->buffered) {
2464                 int j;
2465
2466                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2467                 REG_WR(bp, BNX2_NVM_COMMAND,
2468                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2469
2470                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2471                         udelay(5);
2472
2473                         val = REG_RD(bp, BNX2_NVM_COMMAND);
2474                         if (val & BNX2_NVM_COMMAND_DONE)
2475                                 break;
2476                 }
2477
2478                 if (j >= NVRAM_TIMEOUT_COUNT)
2479                         return -EBUSY;
2480         }
2481         return 0;
2482 }
2483
2484 static void
2485 bnx2_disable_nvram_write(struct bnx2 *bp)
2486 {
2487         u32 val;
2488
2489         val = REG_RD(bp, BNX2_MISC_CFG);
2490         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2491 }
2492
2493
2494 static void
2495 bnx2_enable_nvram_access(struct bnx2 *bp)
2496 {
2497         u32 val;
2498
2499         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2500         /* Enable both bits, even on read. */
2501         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
2502                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2503 }
2504
2505 static void
2506 bnx2_disable_nvram_access(struct bnx2 *bp)
2507 {
2508         u32 val;
2509
2510         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2511         /* Disable both bits, even after read. */
2512         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
2513                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2514                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
2515 }
2516
2517 static int
2518 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2519 {
2520         u32 cmd;
2521         int j;
2522
2523         if (bp->flash_info->buffered)
2524                 /* Buffered flash, no erase needed */
2525                 return 0;
2526
2527         /* Build an erase command */
2528         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2529               BNX2_NVM_COMMAND_DOIT;
2530
2531         /* Need to clear DONE bit separately. */
2532         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2533
2534         /* Address of the NVRAM to read from. */
2535         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2536
2537         /* Issue an erase command. */
2538         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2539
2540         /* Wait for completion. */
2541         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2542                 u32 val;
2543
2544                 udelay(5);
2545
2546                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2547                 if (val & BNX2_NVM_COMMAND_DONE)
2548                         break;
2549         }
2550
2551         if (j >= NVRAM_TIMEOUT_COUNT)
2552                 return -EBUSY;
2553
2554         return 0;
2555 }
2556
2557 static int
2558 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2559 {
2560         u32 cmd;
2561         int j;
2562
2563         /* Build the command word. */
2564         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2565
2566         /* Calculate an offset of a buffered flash. */
2567         if (bp->flash_info->buffered) {
2568                 offset = ((offset / bp->flash_info->page_size) <<
2569                            bp->flash_info->page_bits) +
2570                           (offset % bp->flash_info->page_size);
2571         }
2572
2573         /* Need to clear DONE bit separately. */
2574         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2575
2576         /* Address of the NVRAM to read from. */
2577         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2578
2579         /* Issue a read command. */
2580         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2581
2582         /* Wait for completion. */
2583         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2584                 u32 val;
2585
2586                 udelay(5);
2587
2588                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2589                 if (val & BNX2_NVM_COMMAND_DONE) {
2590                         val = REG_RD(bp, BNX2_NVM_READ);
2591
2592                         val = be32_to_cpu(val);
2593                         memcpy(ret_val, &val, 4);
2594                         break;
2595                 }
2596         }
2597         if (j >= NVRAM_TIMEOUT_COUNT)
2598                 return -EBUSY;
2599
2600         return 0;
2601 }
2602
2603
2604 static int
2605 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2606 {
2607         u32 cmd, val32;
2608         int j;
2609
2610         /* Build the command word. */
2611         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2612
2613         /* Calculate an offset of a buffered flash. */
2614         if (bp->flash_info->buffered) {
2615                 offset = ((offset / bp->flash_info->page_size) <<
2616                           bp->flash_info->page_bits) +
2617                          (offset % bp->flash_info->page_size);
2618         }
2619
2620         /* Need to clear DONE bit separately. */
2621         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2622
2623         memcpy(&val32, val, 4);
2624         val32 = cpu_to_be32(val32);
2625
2626         /* Write the data. */
2627         REG_WR(bp, BNX2_NVM_WRITE, val32);
2628
2629         /* Address of the NVRAM to write to. */
2630         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2631
2632         /* Issue the write command. */
2633         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2634
2635         /* Wait for completion. */
2636         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2637                 udelay(5);
2638
2639                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2640                         break;
2641         }
2642         if (j >= NVRAM_TIMEOUT_COUNT)
2643                 return -EBUSY;
2644
2645         return 0;
2646 }
2647
2648 static int
2649 bnx2_init_nvram(struct bnx2 *bp)
2650 {
2651         u32 val;
2652         int j, entry_count, rc;
2653         struct flash_spec *flash;
2654
2655         /* Determine the selected interface. */
2656         val = REG_RD(bp, BNX2_NVM_CFG1);
2657
2658         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2659
2660         rc = 0;
2661         if (val & 0x40000000) {
2662
2663                 /* Flash interface has been reconfigured */
2664                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2665                      j++, flash++) {
2666                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2667                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2668                                 bp->flash_info = flash;
2669                                 break;
2670                         }
2671                 }
2672         }
2673         else {
2674                 u32 mask;
2675                 /* Not yet been reconfigured */
2676
2677                 if (val & (1 << 23))
2678                         mask = FLASH_BACKUP_STRAP_MASK;
2679                 else
2680                         mask = FLASH_STRAP_MASK;
2681
2682                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2683                         j++, flash++) {
2684
2685                         if ((val & mask) == (flash->strapping & mask)) {
2686                                 bp->flash_info = flash;
2687
2688                                 /* Request access to the flash interface. */
2689                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2690                                         return rc;
2691
2692                                 /* Enable access to flash interface */
2693                                 bnx2_enable_nvram_access(bp);
2694
2695                                 /* Reconfigure the flash interface */
2696                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2697                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2698                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2699                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2700
2701                                 /* Disable access to flash interface */
2702                                 bnx2_disable_nvram_access(bp);
2703                                 bnx2_release_nvram_lock(bp);
2704
2705                                 break;
2706                         }
2707                 }
2708         } /* if (val & 0x40000000) */
2709
2710         if (j == entry_count) {
2711                 bp->flash_info = NULL;
2712                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2713                 rc = -ENODEV;
2714         }
2715
2716         return rc;
2717 }
2718
2719 static int
2720 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2721                 int buf_size)
2722 {
2723         int rc = 0;
2724         u32 cmd_flags, offset32, len32, extra;
2725
2726         if (buf_size == 0)
2727                 return 0;
2728
2729         /* Request access to the flash interface. */
2730         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2731                 return rc;
2732
2733         /* Enable access to flash interface */
2734         bnx2_enable_nvram_access(bp);
2735
2736         len32 = buf_size;
2737         offset32 = offset;
2738         extra = 0;
2739
2740         cmd_flags = 0;
2741
2742         if (offset32 & 3) {
2743                 u8 buf[4];
2744                 u32 pre_len;
2745
2746                 offset32 &= ~3;
2747                 pre_len = 4 - (offset & 3);
2748
2749                 if (pre_len >= len32) {
2750                         pre_len = len32;
2751                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2752                                     BNX2_NVM_COMMAND_LAST;
2753                 }
2754                 else {
2755                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2756                 }
2757
2758                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2759
2760                 if (rc)
2761                         return rc;
2762
2763                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2764
2765                 offset32 += 4;
2766                 ret_buf += pre_len;
2767                 len32 -= pre_len;
2768         }
2769         if (len32 & 3) {
2770                 extra = 4 - (len32 & 3);
2771                 len32 = (len32 + 4) & ~3;
2772         }
2773
2774         if (len32 == 4) {
2775                 u8 buf[4];
2776
2777                 if (cmd_flags)
2778                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2779                 else
2780                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2781                                     BNX2_NVM_COMMAND_LAST;
2782
2783                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2784
2785                 memcpy(ret_buf, buf, 4 - extra);
2786         }
2787         else if (len32 > 0) {
2788                 u8 buf[4];
2789
2790                 /* Read the first word. */
2791                 if (cmd_flags)
2792                         cmd_flags = 0;
2793                 else
2794                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2795
2796                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2797
2798                 /* Advance to the next dword. */
2799                 offset32 += 4;
2800                 ret_buf += 4;
2801                 len32 -= 4;
2802
2803                 while (len32 > 4 && rc == 0) {
2804                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2805
2806                         /* Advance to the next dword. */
2807                         offset32 += 4;
2808                         ret_buf += 4;
2809                         len32 -= 4;
2810                 }
2811
2812                 if (rc)
2813                         return rc;
2814
2815                 cmd_flags = BNX2_NVM_COMMAND_LAST;
2816                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2817
2818                 memcpy(ret_buf, buf, 4 - extra);
2819         }
2820
2821         /* Disable access to flash interface */
2822         bnx2_disable_nvram_access(bp);
2823
2824         bnx2_release_nvram_lock(bp);
2825
2826         return rc;
2827 }
2828
2829 static int
2830 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2831                 int buf_size)
2832 {
2833         u32 written, offset32, len32;
2834         u8 *buf, start[4], end[4];
2835         int rc = 0;
2836         int align_start, align_end;
2837
2838         buf = data_buf;
2839         offset32 = offset;
2840         len32 = buf_size;
2841         align_start = align_end = 0;
2842
2843         if ((align_start = (offset32 & 3))) {
2844                 offset32 &= ~3;
2845                 len32 += align_start;
2846                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2847                         return rc;
2848         }
2849
2850         if (len32 & 3) {
2851                 if ((len32 > 4) || !align_start) {
2852                         align_end = 4 - (len32 & 3);
2853                         len32 += align_end;
2854                         if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2855                                 end, 4))) {
2856                                 return rc;
2857                         }
2858                 }
2859         }
2860
2861         if (align_start || align_end) {
2862                 buf = kmalloc(len32, GFP_KERNEL);
2863                 if (buf == 0)
2864                         return -ENOMEM;
2865                 if (align_start) {
2866                         memcpy(buf, start, 4);
2867                 }
2868                 if (align_end) {
2869                         memcpy(buf + len32 - 4, end, 4);
2870                 }
2871                 memcpy(buf + align_start, data_buf, buf_size);
2872         }
2873
2874         written = 0;
2875         while ((written < len32) && (rc == 0)) {
2876                 u32 page_start, page_end, data_start, data_end;
2877                 u32 addr, cmd_flags;
2878                 int i;
2879                 u8 flash_buffer[264];
2880
2881                 /* Find the page_start addr */
2882                 page_start = offset32 + written;
2883                 page_start -= (page_start % bp->flash_info->page_size);
2884                 /* Find the page_end addr */
2885                 page_end = page_start + bp->flash_info->page_size;
2886                 /* Find the data_start addr */
2887                 data_start = (written == 0) ? offset32 : page_start;
2888                 /* Find the data_end addr */
2889                 data_end = (page_end > offset32 + len32) ? 
2890                         (offset32 + len32) : page_end;
2891
2892                 /* Request access to the flash interface. */
2893                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2894                         goto nvram_write_end;
2895
2896                 /* Enable access to flash interface */
2897                 bnx2_enable_nvram_access(bp);
2898
2899                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2900                 if (bp->flash_info->buffered == 0) {
2901                         int j;
2902
2903                         /* Read the whole page into the buffer
2904                          * (non-buffer flash only) */
2905                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
2906                                 if (j == (bp->flash_info->page_size - 4)) {
2907                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
2908                                 }
2909                                 rc = bnx2_nvram_read_dword(bp,
2910                                         page_start + j, 
2911                                         &flash_buffer[j], 
2912                                         cmd_flags);
2913
2914                                 if (rc)
2915                                         goto nvram_write_end;
2916
2917                                 cmd_flags = 0;
2918                         }
2919                 }
2920
2921                 /* Enable writes to flash interface (unlock write-protect) */
2922                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2923                         goto nvram_write_end;
2924
2925                 /* Erase the page */
2926                 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2927                         goto nvram_write_end;
2928
2929                 /* Re-enable the write again for the actual write */
2930                 bnx2_enable_nvram_write(bp);
2931
2932                 /* Loop to write back the buffer data from page_start to
2933                  * data_start */
2934                 i = 0;
2935                 if (bp->flash_info->buffered == 0) {
2936                         for (addr = page_start; addr < data_start;
2937                                 addr += 4, i += 4) {
2938                                 
2939                                 rc = bnx2_nvram_write_dword(bp, addr,
2940                                         &flash_buffer[i], cmd_flags);
2941
2942                                 if (rc != 0)
2943                                         goto nvram_write_end;
2944
2945                                 cmd_flags = 0;
2946                         }
2947                 }
2948
2949                 /* Loop to write the new data from data_start to data_end */
2950                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2951                         if ((addr == page_end - 4) ||
2952                                 ((bp->flash_info->buffered) &&
2953                                  (addr == data_end - 4))) {
2954
2955                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2956                         }
2957                         rc = bnx2_nvram_write_dword(bp, addr, buf,
2958                                 cmd_flags);
2959
2960                         if (rc != 0)
2961                                 goto nvram_write_end;
2962
2963                         cmd_flags = 0;
2964                         buf += 4;
2965                 }
2966
2967                 /* Loop to write back the buffer data from data_end
2968                  * to page_end */
2969                 if (bp->flash_info->buffered == 0) {
2970                         for (addr = data_end; addr < page_end;
2971                                 addr += 4, i += 4) {
2972                         
2973                                 if (addr == page_end-4) {
2974                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2975                                 }
2976                                 rc = bnx2_nvram_write_dword(bp, addr,
2977                                         &flash_buffer[i], cmd_flags);
2978
2979                                 if (rc != 0)
2980                                         goto nvram_write_end;
2981
2982                                 cmd_flags = 0;
2983                         }
2984                 }
2985
2986                 /* Disable writes to flash interface (lock write-protect) */
2987                 bnx2_disable_nvram_write(bp);
2988
2989                 /* Disable access to flash interface */
2990                 bnx2_disable_nvram_access(bp);
2991                 bnx2_release_nvram_lock(bp);
2992
2993                 /* Increment written */
2994                 written += data_end - data_start;
2995         }
2996
2997 nvram_write_end:
2998         if (align_start || align_end)
2999                 kfree(buf);
3000         return rc;
3001 }
3002
3003 static int
3004 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3005 {
3006         u32 val;
3007         int i, rc = 0;
3008
3009         /* Wait for the current PCI transaction to complete before
3010          * issuing a reset. */
3011         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3012                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3013                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3014                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3015                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3016         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3017         udelay(5);
3018
3019         /* Wait for the firmware to tell us it is ok to issue a reset. */
3020         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3021
3022         /* Deposit a driver reset signature so the firmware knows that
3023          * this is a soft reset. */
3024         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3025                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
3026
3027         /* Do a dummy read to force the chip to complete all current transaction
3028          * before we issue a reset. */
3029         val = REG_RD(bp, BNX2_MISC_ID);
3030
3031         val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3032               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3033               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3034
3035         /* Chip reset. */
3036         REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3037
3038         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3039             (CHIP_ID(bp) == CHIP_ID_5706_A1))
3040                 msleep(15);
3041
3042         /* Reset takes approximate 30 usec */
3043         for (i = 0; i < 10; i++) {
3044                 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3045                 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3046                             BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3047                         break;
3048                 }
3049                 udelay(10);
3050         }
3051
3052         if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3053                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3054                 printk(KERN_ERR PFX "Chip reset did not complete\n");
3055                 return -EBUSY;
3056         }
3057
3058         /* Make sure byte swapping is properly configured. */
3059         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3060         if (val != 0x01020304) {
3061                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3062                 return -ENODEV;
3063         }
3064
3065         /* Wait for the firmware to finish its initialization. */
3066         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3067         if (rc)
3068                 return rc;
3069
3070         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3071                 /* Adjust the voltage regular to two steps lower.  The default
3072                  * of this register is 0x0000000e. */
3073                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3074
3075                 /* Remove bad rbuf memory from the free pool. */
3076                 rc = bnx2_alloc_bad_rbuf(bp);
3077         }
3078
3079         return rc;
3080 }
3081
3082 static int
3083 bnx2_init_chip(struct bnx2 *bp)
3084 {
3085         u32 val;
3086         int rc;
3087
3088         /* Make sure the interrupt is not active. */
3089         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3090
3091         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3092               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3093 #ifdef __BIG_ENDIAN
3094               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | 
3095 #endif
3096               BNX2_DMA_CONFIG_CNTL_WORD_SWAP | 
3097               DMA_READ_CHANS << 12 |
3098               DMA_WRITE_CHANS << 16;
3099
3100         val |= (0x2 << 20) | (1 << 11);
3101
3102         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
3103                 val |= (1 << 23);
3104
3105         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3106             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3107                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3108
3109         REG_WR(bp, BNX2_DMA_CONFIG, val);
3110
3111         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3112                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3113                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3114                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3115         }
3116
3117         if (bp->flags & PCIX_FLAG) {
3118                 u16 val16;
3119
3120                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3121                                      &val16);
3122                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3123                                       val16 & ~PCI_X_CMD_ERO);
3124         }
3125
3126         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3127                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3128                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3129                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3130
3131         /* Initialize context mapping and zero out the quick contexts.  The
3132          * context block must have already been enabled. */
3133         bnx2_init_context(bp);
3134
3135         bnx2_init_cpus(bp);
3136         bnx2_init_nvram(bp);
3137
3138         bnx2_set_mac_addr(bp);
3139
3140         val = REG_RD(bp, BNX2_MQ_CONFIG);
3141         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3142         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3143         REG_WR(bp, BNX2_MQ_CONFIG, val);
3144
3145         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3146         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3147         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3148
3149         val = (BCM_PAGE_BITS - 8) << 24;
3150         REG_WR(bp, BNX2_RV2P_CONFIG, val);
3151
3152         /* Configure page size. */
3153         val = REG_RD(bp, BNX2_TBDR_CONFIG);
3154         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3155         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3156         REG_WR(bp, BNX2_TBDR_CONFIG, val);
3157
3158         val = bp->mac_addr[0] +
3159               (bp->mac_addr[1] << 8) +
3160               (bp->mac_addr[2] << 16) +
3161               bp->mac_addr[3] +
3162               (bp->mac_addr[4] << 8) +
3163               (bp->mac_addr[5] << 16);
3164         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3165
3166         /* Program the MTU.  Also include 4 bytes for CRC32. */
3167         val = bp->dev->mtu + ETH_HLEN + 4;
3168         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3169                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3170         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3171
3172         bp->last_status_idx = 0;
3173         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3174
3175         /* Set up how to generate a link change interrupt. */
3176         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3177
3178         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3179                (u64) bp->status_blk_mapping & 0xffffffff);
3180         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3181
3182         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3183                (u64) bp->stats_blk_mapping & 0xffffffff);
3184         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3185                (u64) bp->stats_blk_mapping >> 32);
3186
3187         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, 
3188                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3189
3190         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3191                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3192
3193         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3194                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3195
3196         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3197
3198         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3199
3200         REG_WR(bp, BNX2_HC_COM_TICKS,
3201                (bp->com_ticks_int << 16) | bp->com_ticks);
3202
3203         REG_WR(bp, BNX2_HC_CMD_TICKS,
3204                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3205
3206         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3207         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
3208
3209         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3210                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3211         else {
3212                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3213                        BNX2_HC_CONFIG_TX_TMR_MODE |
3214                        BNX2_HC_CONFIG_COLLECT_STATS);
3215         }
3216
3217         /* Clear internal stats counters. */
3218         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3219
3220         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3221
3222         if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3223             BNX2_PORT_FEATURE_ASF_ENABLED)
3224                 bp->flags |= ASF_ENABLE_FLAG;
3225
3226         /* Initialize the receive filter. */
3227         bnx2_set_rx_mode(bp->dev);
3228
3229         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3230                           0);
3231
3232         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3233         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3234
3235         udelay(20);
3236
3237         return rc;
3238 }
3239
3240
3241 static void
3242 bnx2_init_tx_ring(struct bnx2 *bp)
3243 {
3244         struct tx_bd *txbd;
3245         u32 val;
3246
3247         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3248                 
3249         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3250         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3251
3252         bp->tx_prod = 0;
3253         bp->tx_cons = 0;
3254         bp->hw_tx_cons = 0;
3255         bp->tx_prod_bseq = 0;
3256         
3257         val = BNX2_L2CTX_TYPE_TYPE_L2;
3258         val |= BNX2_L2CTX_TYPE_SIZE_L2;
3259         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3260
3261         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3262         val |= 8 << 16;
3263         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3264
3265         val = (u64) bp->tx_desc_mapping >> 32;
3266         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3267
3268         val = (u64) bp->tx_desc_mapping & 0xffffffff;
3269         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3270 }
3271
3272 static void
3273 bnx2_init_rx_ring(struct bnx2 *bp)
3274 {
3275         struct rx_bd *rxbd;
3276         int i;
3277         u16 prod, ring_prod; 
3278         u32 val;
3279
3280         /* 8 for CRC and VLAN */
3281         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3282         /* 8 for alignment */
3283         bp->rx_buf_size = bp->rx_buf_use_size + 8;
3284
3285         ring_prod = prod = bp->rx_prod = 0;
3286         bp->rx_cons = 0;
3287         bp->hw_rx_cons = 0;
3288         bp->rx_prod_bseq = 0;
3289                 
3290         rxbd = &bp->rx_desc_ring[0];
3291         for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3292                 rxbd->rx_bd_len = bp->rx_buf_use_size;
3293                 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3294         }
3295
3296         rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3297         rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3298
3299         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3300         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3301         val |= 0x02 << 8;
3302         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3303
3304         val = (u64) bp->rx_desc_mapping >> 32;
3305         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3306
3307         val = (u64) bp->rx_desc_mapping & 0xffffffff;
3308         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3309
3310         for ( ;ring_prod < bp->rx_ring_size; ) {
3311                 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3312                         break;
3313                 }
3314                 prod = NEXT_RX_BD(prod);
3315                 ring_prod = RX_RING_IDX(prod);
3316         }
3317         bp->rx_prod = prod;
3318
3319         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3320
3321         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3322 }
3323
3324 static void
3325 bnx2_free_tx_skbs(struct bnx2 *bp)
3326 {
3327         int i;
3328
3329         if (bp->tx_buf_ring == NULL)
3330                 return;
3331
3332         for (i = 0; i < TX_DESC_CNT; ) {
3333                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3334                 struct sk_buff *skb = tx_buf->skb;
3335                 int j, last;
3336
3337                 if (skb == NULL) {
3338                         i++;
3339                         continue;
3340                 }
3341
3342                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3343                         skb_headlen(skb), PCI_DMA_TODEVICE);
3344
3345                 tx_buf->skb = NULL;
3346
3347                 last = skb_shinfo(skb)->nr_frags;
3348                 for (j = 0; j < last; j++) {
3349                         tx_buf = &bp->tx_buf_ring[i + j + 1];
3350                         pci_unmap_page(bp->pdev,
3351                                 pci_unmap_addr(tx_buf, mapping),
3352                                 skb_shinfo(skb)->frags[j].size,
3353                                 PCI_DMA_TODEVICE);
3354                 }
3355                 dev_kfree_skb_any(skb);
3356                 i += j + 1;
3357         }
3358
3359 }
3360
3361 static void
3362 bnx2_free_rx_skbs(struct bnx2 *bp)
3363 {
3364         int i;
3365
3366         if (bp->rx_buf_ring == NULL)
3367                 return;
3368
3369         for (i = 0; i < RX_DESC_CNT; i++) {
3370                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3371                 struct sk_buff *skb = rx_buf->skb;
3372
3373                 if (skb == NULL)
3374                         continue;
3375
3376                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3377                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3378
3379                 rx_buf->skb = NULL;
3380
3381                 dev_kfree_skb_any(skb);
3382         }
3383 }
3384
3385 static void
3386 bnx2_free_skbs(struct bnx2 *bp)
3387 {
3388         bnx2_free_tx_skbs(bp);
3389         bnx2_free_rx_skbs(bp);
3390 }
3391
3392 static int
3393 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3394 {
3395         int rc;
3396
3397         rc = bnx2_reset_chip(bp, reset_code);
3398         bnx2_free_skbs(bp);
3399         if (rc)
3400                 return rc;
3401
3402         bnx2_init_chip(bp);
3403         bnx2_init_tx_ring(bp);
3404         bnx2_init_rx_ring(bp);
3405         return 0;
3406 }
3407
3408 static int
3409 bnx2_init_nic(struct bnx2 *bp)
3410 {
3411         int rc;
3412
3413         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3414                 return rc;
3415
3416         bnx2_init_phy(bp);
3417         bnx2_set_link(bp);
3418         return 0;
3419 }
3420
3421 static int
3422 bnx2_test_registers(struct bnx2 *bp)
3423 {
3424         int ret;
3425         int i;
3426         static struct {
3427                 u16   offset;
3428                 u16   flags;
3429                 u32   rw_mask;
3430                 u32   ro_mask;
3431         } reg_tbl[] = {
3432                 { 0x006c, 0, 0x00000000, 0x0000003f },
3433                 { 0x0090, 0, 0xffffffff, 0x00000000 },
3434                 { 0x0094, 0, 0x00000000, 0x00000000 },
3435
3436                 { 0x0404, 0, 0x00003f00, 0x00000000 },
3437                 { 0x0418, 0, 0x00000000, 0xffffffff },
3438                 { 0x041c, 0, 0x00000000, 0xffffffff },
3439                 { 0x0420, 0, 0x00000000, 0x80ffffff },
3440                 { 0x0424, 0, 0x00000000, 0x00000000 },
3441                 { 0x0428, 0, 0x00000000, 0x00000001 },
3442                 { 0x0450, 0, 0x00000000, 0x0000ffff },
3443                 { 0x0454, 0, 0x00000000, 0xffffffff },
3444                 { 0x0458, 0, 0x00000000, 0xffffffff },
3445
3446                 { 0x0808, 0, 0x00000000, 0xffffffff },
3447                 { 0x0854, 0, 0x00000000, 0xffffffff },
3448                 { 0x0868, 0, 0x00000000, 0x77777777 },
3449                 { 0x086c, 0, 0x00000000, 0x77777777 },
3450                 { 0x0870, 0, 0x00000000, 0x77777777 },
3451                 { 0x0874, 0, 0x00000000, 0x77777777 },
3452
3453                 { 0x0c00, 0, 0x00000000, 0x00000001 },
3454                 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3455                 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3456                 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3457                 { 0x0c30, 0, 0x00000000, 0xffffffff },
3458                 { 0x0c34, 0, 0x00000000, 0xffffffff },
3459                 { 0x0c38, 0, 0x00000000, 0xffffffff },
3460                 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3461                 { 0x0c40, 0, 0x00000000, 0xffffffff },
3462                 { 0x0c44, 0, 0x00000000, 0xffffffff },
3463                 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3464                 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3465                 { 0x0c50, 0, 0x00000000, 0xffffffff },
3466                 { 0x0c54, 0, 0x00000000, 0xffffffff },
3467                 { 0x0c58, 0, 0x00000000, 0xffffffff },
3468                 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3469                 { 0x0c60, 0, 0x00000000, 0xffffffff },
3470                 { 0x0c64, 0, 0x00000000, 0xffffffff },
3471                 { 0x0c68, 0, 0x00000000, 0xffffffff },
3472                 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3473                 { 0x0c70, 0, 0x00000000, 0xffffffff },
3474                 { 0x0c74, 0, 0x00000000, 0xffffffff },
3475                 { 0x0c78, 0, 0x00000000, 0xffffffff },
3476                 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3477                 { 0x0c80, 0, 0x00000000, 0xffffffff },
3478                 { 0x0c84, 0, 0x00000000, 0xffffffff },
3479                 { 0x0c88, 0, 0x00000000, 0xffffffff },
3480                 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3481                 { 0x0c90, 0, 0x00000000, 0xffffffff },
3482                 { 0x0c94, 0, 0x00000000, 0xffffffff },
3483                 { 0x0c98, 0, 0x00000000, 0xffffffff },
3484                 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3485                 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3486                 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3487                 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3488                 { 0x0cac, 0, 0x00000000, 0xffffffff },
3489                 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3490                 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3491                 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3492                 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3493                 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3494                 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3495                 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3496                 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3497                 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3498                 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3499                 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3500                 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3501                 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3502                 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3503                 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3504                 { 0x0cec, 0, 0x00000000, 0xffffffff },
3505                 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3506                 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3507                 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3508                 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3509                 { 0x0d00, 0, 0x00000000, 0xffffffff },
3510                 { 0x0d04, 0, 0x00000000, 0xffffffff },
3511
3512                 { 0x1000, 0, 0x00000000, 0x00000001 },
3513                 { 0x1004, 0, 0x00000000, 0x000f0001 },
3514                 { 0x1044, 0, 0x00000000, 0xffc003ff },
3515                 { 0x1080, 0, 0x00000000, 0x0001ffff },
3516                 { 0x1084, 0, 0x00000000, 0xffffffff },
3517                 { 0x1088, 0, 0x00000000, 0xffffffff },
3518                 { 0x108c, 0, 0x00000000, 0xffffffff },
3519                 { 0x1090, 0, 0x00000000, 0xffffffff },
3520                 { 0x1094, 0, 0x00000000, 0xffffffff },
3521                 { 0x1098, 0, 0x00000000, 0xffffffff },
3522                 { 0x109c, 0, 0x00000000, 0xffffffff },
3523                 { 0x10a0, 0, 0x00000000, 0xffffffff },
3524
3525                 { 0x1408, 0, 0x01c00800, 0x00000000 },
3526                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3527                 { 0x14a8, 0, 0x00000000, 0x000001ff },
3528                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3529                 { 0x14b0, 0, 0x00000002, 0x00000001 },
3530                 { 0x14b8, 0, 0x00000000, 0x00000000 },
3531                 { 0x14c0, 0, 0x00000000, 0x00000009 },
3532                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3533                 { 0x14cc, 0, 0x00000000, 0x00000001 },
3534                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3535                 { 0x1500, 0, 0x00000000, 0xffffffff },
3536                 { 0x1504, 0, 0x00000000, 0xffffffff },
3537                 { 0x1508, 0, 0x00000000, 0xffffffff },
3538                 { 0x150c, 0, 0x00000000, 0xffffffff },
3539                 { 0x1510, 0, 0x00000000, 0xffffffff },
3540                 { 0x1514, 0, 0x00000000, 0xffffffff },
3541                 { 0x1518, 0, 0x00000000, 0xffffffff },
3542                 { 0x151c, 0, 0x00000000, 0xffffffff },
3543                 { 0x1520, 0, 0x00000000, 0xffffffff },
3544                 { 0x1524, 0, 0x00000000, 0xffffffff },
3545                 { 0x1528, 0, 0x00000000, 0xffffffff },
3546                 { 0x152c, 0, 0x00000000, 0xffffffff },
3547                 { 0x1530, 0, 0x00000000, 0xffffffff },
3548                 { 0x1534, 0, 0x00000000, 0xffffffff },
3549                 { 0x1538, 0, 0x00000000, 0xffffffff },
3550                 { 0x153c, 0, 0x00000000, 0xffffffff },
3551                 { 0x1540, 0, 0x00000000, 0xffffffff },
3552                 { 0x1544, 0, 0x00000000, 0xffffffff },
3553                 { 0x1548, 0, 0x00000000, 0xffffffff },
3554                 { 0x154c, 0, 0x00000000, 0xffffffff },
3555                 { 0x1550, 0, 0x00000000, 0xffffffff },
3556                 { 0x1554, 0, 0x00000000, 0xffffffff },
3557                 { 0x1558, 0, 0x00000000, 0xffffffff },
3558                 { 0x1600, 0, 0x00000000, 0xffffffff },
3559                 { 0x1604, 0, 0x00000000, 0xffffffff },
3560                 { 0x1608, 0, 0x00000000, 0xffffffff },
3561                 { 0x160c, 0, 0x00000000, 0xffffffff },
3562                 { 0x1610, 0, 0x00000000, 0xffffffff },
3563                 { 0x1614, 0, 0x00000000, 0xffffffff },
3564                 { 0x1618, 0, 0x00000000, 0xffffffff },
3565                 { 0x161c, 0, 0x00000000, 0xffffffff },
3566                 { 0x1620, 0, 0x00000000, 0xffffffff },
3567                 { 0x1624, 0, 0x00000000, 0xffffffff },
3568                 { 0x1628, 0, 0x00000000, 0xffffffff },
3569                 { 0x162c, 0, 0x00000000, 0xffffffff },
3570                 { 0x1630, 0, 0x00000000, 0xffffffff },
3571                 { 0x1634, 0, 0x00000000, 0xffffffff },
3572                 { 0x1638, 0, 0x00000000, 0xffffffff },
3573                 { 0x163c, 0, 0x00000000, 0xffffffff },
3574                 { 0x1640, 0, 0x00000000, 0xffffffff },
3575                 { 0x1644, 0, 0x00000000, 0xffffffff },
3576                 { 0x1648, 0, 0x00000000, 0xffffffff },
3577                 { 0x164c, 0, 0x00000000, 0xffffffff },
3578                 { 0x1650, 0, 0x00000000, 0xffffffff },
3579                 { 0x1654, 0, 0x00000000, 0xffffffff },
3580
3581                 { 0x1800, 0, 0x00000000, 0x00000001 },
3582                 { 0x1804, 0, 0x00000000, 0x00000003 },
3583                 { 0x1840, 0, 0x00000000, 0xffffffff },
3584                 { 0x1844, 0, 0x00000000, 0xffffffff },
3585                 { 0x1848, 0, 0x00000000, 0xffffffff },
3586                 { 0x184c, 0, 0x00000000, 0xffffffff },
3587                 { 0x1850, 0, 0x00000000, 0xffffffff },
3588                 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3589                 { 0x1904, 0, 0xffffffff, 0x00000000 },
3590                 { 0x190c, 0, 0xffffffff, 0x00000000 },
3591                 { 0x1914, 0, 0xffffffff, 0x00000000 },
3592                 { 0x191c, 0, 0xffffffff, 0x00000000 },
3593                 { 0x1924, 0, 0xffffffff, 0x00000000 },
3594                 { 0x192c, 0, 0xffffffff, 0x00000000 },
3595                 { 0x1934, 0, 0xffffffff, 0x00000000 },
3596                 { 0x193c, 0, 0xffffffff, 0x00000000 },
3597                 { 0x1944, 0, 0xffffffff, 0x00000000 },
3598                 { 0x194c, 0, 0xffffffff, 0x00000000 },
3599                 { 0x1954, 0, 0xffffffff, 0x00000000 },
3600                 { 0x195c, 0, 0xffffffff, 0x00000000 },
3601                 { 0x1964, 0, 0xffffffff, 0x00000000 },
3602                 { 0x196c, 0, 0xffffffff, 0x00000000 },
3603                 { 0x1974, 0, 0xffffffff, 0x00000000 },
3604                 { 0x197c, 0, 0xffffffff, 0x00000000 },
3605                 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3606
3607                 { 0x1c00, 0, 0x00000000, 0x00000001 },
3608                 { 0x1c04, 0, 0x00000000, 0x00000003 },
3609                 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3610                 { 0x1c40, 0, 0x00000000, 0xffffffff },
3611                 { 0x1c44, 0, 0x00000000, 0xffffffff },
3612                 { 0x1c48, 0, 0x00000000, 0xffffffff },
3613                 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3614                 { 0x1c50, 0, 0x00000000, 0xffffffff },
3615                 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3616                 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3617                 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3618                 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3619                 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3620                 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3621                 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3622                 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3623                 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3624                 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3625                 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3626                 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3627                 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3628                 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3629                 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3630                 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3631                 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3632                 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3633
3634                 { 0x2004, 0, 0x00000000, 0x0337000f },
3635                 { 0x2008, 0, 0xffffffff, 0x00000000 },
3636                 { 0x200c, 0, 0xffffffff, 0x00000000 },
3637                 { 0x2010, 0, 0xffffffff, 0x00000000 },
3638                 { 0x2014, 0, 0x801fff80, 0x00000000 },
3639                 { 0x2018, 0, 0x000003ff, 0x00000000 },
3640
3641                 { 0x2800, 0, 0x00000000, 0x00000001 },
3642                 { 0x2804, 0, 0x00000000, 0x00003f01 },
3643                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3644                 { 0x2810, 0, 0xffff0000, 0x00000000 },
3645                 { 0x2814, 0, 0xffff0000, 0x00000000 },
3646                 { 0x2818, 0, 0xffff0000, 0x00000000 },
3647                 { 0x281c, 0, 0xffff0000, 0x00000000 },
3648                 { 0x2834, 0, 0xffffffff, 0x00000000 },
3649                 { 0x2840, 0, 0x00000000, 0xffffffff },
3650                 { 0x2844, 0, 0x00000000, 0xffffffff },
3651                 { 0x2848, 0, 0xffffffff, 0x00000000 },
3652                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3653
3654                 { 0x2c00, 0, 0x00000000, 0x00000011 },
3655                 { 0x2c04, 0, 0x00000000, 0x00030007 },
3656
3657                 { 0x3000, 0, 0x00000000, 0x00000001 },
3658                 { 0x3004, 0, 0x00000000, 0x007007ff },
3659                 { 0x3008, 0, 0x00000003, 0x00000000 },
3660                 { 0x300c, 0, 0xffffffff, 0x00000000 },
3661                 { 0x3010, 0, 0xffffffff, 0x00000000 },
3662                 { 0x3014, 0, 0xffffffff, 0x00000000 },
3663                 { 0x3034, 0, 0xffffffff, 0x00000000 },
3664                 { 0x3038, 0, 0xffffffff, 0x00000000 },
3665                 { 0x3050, 0, 0x00000001, 0x00000000 },
3666
3667                 { 0x3c00, 0, 0x00000000, 0x00000001 },
3668                 { 0x3c04, 0, 0x00000000, 0x00070000 },
3669                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3670                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3671                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3672                 { 0x3c14, 0, 0x00000000, 0xffffffff },
3673                 { 0x3c18, 0, 0x00000000, 0xffffffff },
3674                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3675                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3676                 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3677                 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3678                 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3679                 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3680                 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3681                 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3682                 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3683                 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3684                 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3685                 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3686                 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3687                 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3688                 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3689                 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3690                 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3691                 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3692                 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3693                 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3694                 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3695                 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3696                 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3697                 { 0x3c78, 0, 0x00000000, 0x00000000 },
3698                 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3699                 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3700                 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3701                 { 0x3c88, 0, 0x00000000, 0xffffffff },
3702                 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3703
3704                 { 0x4000, 0, 0x00000000, 0x00000001 },
3705                 { 0x4004, 0, 0x00000000, 0x00030000 },
3706                 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3707                 { 0x400c, 0, 0xffffffff, 0x00000000 },
3708                 { 0x4088, 0, 0x00000000, 0x00070303 },
3709
3710                 { 0x4400, 0, 0x00000000, 0x00000001 },
3711                 { 0x4404, 0, 0x00000000, 0x00003f01 },
3712                 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3713                 { 0x440c, 0, 0xffffffff, 0x00000000 },
3714                 { 0x4410, 0, 0xffff,     0x0000 },
3715                 { 0x4414, 0, 0xffff,     0x0000 },
3716                 { 0x4418, 0, 0xffff,     0x0000 },
3717                 { 0x441c, 0, 0xffff,     0x0000 },
3718                 { 0x4428, 0, 0xffffffff, 0x00000000 },
3719                 { 0x442c, 0, 0xffffffff, 0x00000000 },
3720                 { 0x4430, 0, 0xffffffff, 0x00000000 },
3721                 { 0x4434, 0, 0xffffffff, 0x00000000 },
3722                 { 0x4438, 0, 0xffffffff, 0x00000000 },
3723                 { 0x443c, 0, 0xffffffff, 0x00000000 },
3724                 { 0x4440, 0, 0xffffffff, 0x00000000 },
3725                 { 0x4444, 0, 0xffffffff, 0x00000000 },
3726
3727                 { 0x4c00, 0, 0x00000000, 0x00000001 },
3728                 { 0x4c04, 0, 0x00000000, 0x0000003f },
3729                 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3730                 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3731                 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3732                 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3733                 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3734                 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3735                 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3736                 { 0x4c50, 0, 0x00000000, 0xffffffff },
3737
3738                 { 0x5004, 0, 0x00000000, 0x0000007f },
3739                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3740                 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3741
3742                 { 0x5400, 0, 0x00000008, 0x00000001 },
3743                 { 0x5404, 0, 0x00000000, 0x0000003f },
3744                 { 0x5408, 0, 0x0000001f, 0x00000000 },
3745                 { 0x540c, 0, 0xffffffff, 0x00000000 },
3746                 { 0x5410, 0, 0xffffffff, 0x00000000 },
3747                 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3748                 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3749                 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3750                 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3751                 { 0x5428, 0, 0x000000ff, 0x00000000 },
3752                 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3753                 { 0x5430, 0, 0x001fff80, 0x00000000 },
3754                 { 0x5438, 0, 0xffffffff, 0x00000000 },
3755                 { 0x543c, 0, 0xffffffff, 0x00000000 },
3756                 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3757
3758                 { 0x5c00, 0, 0x00000000, 0x00000001 },
3759                 { 0x5c04, 0, 0x00000000, 0x0003000f },
3760                 { 0x5c08, 0, 0x00000003, 0x00000000 },
3761                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3762                 { 0x5c10, 0, 0x00000000, 0xffffffff },
3763                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3764                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3765                 { 0x5c88, 0, 0x00000000, 0x00077373 },
3766                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3767
3768                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3769                 { 0x680c, 0, 0xffffffff, 0x00000000 },
3770                 { 0x6810, 0, 0xffffffff, 0x00000000 },
3771                 { 0x6814, 0, 0xffffffff, 0x00000000 },
3772                 { 0x6818, 0, 0xffffffff, 0x00000000 },
3773                 { 0x681c, 0, 0xffffffff, 0x00000000 },
3774                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3775                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3776                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3777                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3778                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3779                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3780                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3781                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3782                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3783                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3784                 { 0x684c, 0, 0xffffffff, 0x00000000 },
3785                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3786                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3787                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3788                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3789                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3790                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3791
3792                 { 0xffff, 0, 0x00000000, 0x00000000 },
3793         };
3794
3795         ret = 0;
3796         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3797                 u32 offset, rw_mask, ro_mask, save_val, val;
3798
3799                 offset = (u32) reg_tbl[i].offset;
3800                 rw_mask = reg_tbl[i].rw_mask;
3801                 ro_mask = reg_tbl[i].ro_mask;
3802
3803                 save_val = readl(bp->regview + offset);
3804
3805                 writel(0, bp->regview + offset);
3806
3807                 val = readl(bp->regview + offset);
3808                 if ((val & rw_mask) != 0) {
3809                         goto reg_test_err;
3810                 }
3811
3812                 if ((val & ro_mask) != (save_val & ro_mask)) {
3813                         goto reg_test_err;
3814                 }
3815
3816                 writel(0xffffffff, bp->regview + offset);
3817
3818                 val = readl(bp->regview + offset);
3819                 if ((val & rw_mask) != rw_mask) {
3820                         goto reg_test_err;
3821                 }
3822
3823                 if ((val & ro_mask) != (save_val & ro_mask)) {
3824                         goto reg_test_err;
3825                 }
3826
3827                 writel(save_val, bp->regview + offset);
3828                 continue;
3829
3830 reg_test_err:
3831                 writel(save_val, bp->regview + offset);
3832                 ret = -ENODEV;
3833                 break;
3834         }
3835         return ret;
3836 }
3837
3838 static int
3839 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3840 {
3841         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3842                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3843         int i;
3844
3845         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3846                 u32 offset;
3847
3848                 for (offset = 0; offset < size; offset += 4) {
3849
3850                         REG_WR_IND(bp, start + offset, test_pattern[i]);
3851
3852                         if (REG_RD_IND(bp, start + offset) !=
3853                                 test_pattern[i]) {
3854                                 return -ENODEV;
3855                         }
3856                 }
3857         }
3858         return 0;
3859 }
3860
3861 static int
3862 bnx2_test_memory(struct bnx2 *bp)
3863 {
3864         int ret = 0;
3865         int i;
3866         static struct {
3867                 u32   offset;
3868                 u32   len;
3869         } mem_tbl[] = {
3870                 { 0x60000,  0x4000 },
3871                 { 0xa0000,  0x3000 },
3872                 { 0xe0000,  0x4000 },
3873                 { 0x120000, 0x4000 },
3874                 { 0x1a0000, 0x4000 },
3875                 { 0x160000, 0x4000 },
3876                 { 0xffffffff, 0    },
3877         };
3878
3879         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3880                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3881                         mem_tbl[i].len)) != 0) {
3882                         return ret;
3883                 }
3884         }
3885         
3886         return ret;
3887 }
3888
3889 static int
3890 bnx2_test_loopback(struct bnx2 *bp)
3891 {
3892         unsigned int pkt_size, num_pkts, i;
3893         struct sk_buff *skb, *rx_skb;
3894         unsigned char *packet;
3895         u16 rx_start_idx, rx_idx, send_idx;
3896         u32 send_bseq, val;
3897         dma_addr_t map;
3898         struct tx_bd *txbd;
3899         struct sw_bd *rx_buf;
3900         struct l2_fhdr *rx_hdr;
3901         int ret = -ENODEV;
3902
3903         if (!netif_running(bp->dev))
3904                 return -ENODEV;
3905
3906         bp->loopback = MAC_LOOPBACK;
3907         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3908         bnx2_set_mac_loopback(bp);
3909
3910         pkt_size = 1514;
3911         skb = dev_alloc_skb(pkt_size);
3912         if (!skb)
3913                 return -ENOMEM;
3914         packet = skb_put(skb, pkt_size);
3915         memcpy(packet, bp->mac_addr, 6);
3916         memset(packet + 6, 0x0, 8);
3917         for (i = 14; i < pkt_size; i++)
3918                 packet[i] = (unsigned char) (i & 0xff);
3919
3920         map = pci_map_single(bp->pdev, skb->data, pkt_size,
3921                 PCI_DMA_TODEVICE);
3922
3923         val = REG_RD(bp, BNX2_HC_COMMAND);
3924         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3925         REG_RD(bp, BNX2_HC_COMMAND);
3926
3927         udelay(5);
3928         rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3929
3930         send_idx = 0;
3931         send_bseq = 0;
3932         num_pkts = 0;
3933
3934         txbd = &bp->tx_desc_ring[send_idx];
3935
3936         txbd->tx_bd_haddr_hi = (u64) map >> 32;
3937         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3938         txbd->tx_bd_mss_nbytes = pkt_size;
3939         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3940
3941         num_pkts++;
3942         send_idx = NEXT_TX_BD(send_idx);
3943
3944         send_bseq += pkt_size;
3945
3946         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3947         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3948
3949
3950         udelay(100);
3951
3952         val = REG_RD(bp, BNX2_HC_COMMAND);
3953         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3954         REG_RD(bp, BNX2_HC_COMMAND);
3955
3956         udelay(5);
3957
3958         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3959         dev_kfree_skb_irq(skb);
3960
3961         if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3962                 goto loopback_test_done;
3963         }
3964
3965         rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3966         if (rx_idx != rx_start_idx + num_pkts) {
3967                 goto loopback_test_done;
3968         }
3969
3970         rx_buf = &bp->rx_buf_ring[rx_start_idx];
3971         rx_skb = rx_buf->skb;
3972
3973         rx_hdr = (struct l2_fhdr *) rx_skb->data;
3974         skb_reserve(rx_skb, bp->rx_offset);
3975
3976         pci_dma_sync_single_for_cpu(bp->pdev,
3977                 pci_unmap_addr(rx_buf, mapping),
3978                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3979
3980         if (rx_hdr->l2_fhdr_errors &
3981                 (L2_FHDR_ERRORS_BAD_CRC |
3982                 L2_FHDR_ERRORS_PHY_DECODE |
3983                 L2_FHDR_ERRORS_ALIGNMENT |
3984                 L2_FHDR_ERRORS_TOO_SHORT |
3985                 L2_FHDR_ERRORS_GIANT_FRAME)) {
3986
3987                 goto loopback_test_done;
3988         }
3989
3990         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3991                 goto loopback_test_done;
3992         }
3993
3994         for (i = 14; i < pkt_size; i++) {
3995                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3996                         goto loopback_test_done;
3997                 }
3998         }
3999
4000         ret = 0;
4001
4002 loopback_test_done:
4003         bp->loopback = 0;
4004         return ret;
4005 }
4006
4007 #define NVRAM_SIZE 0x200
4008 #define CRC32_RESIDUAL 0xdebb20e3
4009
4010 static int
4011 bnx2_test_nvram(struct bnx2 *bp)
4012 {
4013         u32 buf[NVRAM_SIZE / 4];
4014         u8 *data = (u8 *) buf;
4015         int rc = 0;
4016         u32 magic, csum;
4017
4018         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4019                 goto test_nvram_done;
4020
4021         magic = be32_to_cpu(buf[0]);
4022         if (magic != 0x669955aa) {
4023                 rc = -ENODEV;
4024                 goto test_nvram_done;
4025         }
4026
4027         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4028                 goto test_nvram_done;
4029
4030         csum = ether_crc_le(0x100, data);
4031         if (csum != CRC32_RESIDUAL) {
4032                 rc = -ENODEV;
4033                 goto test_nvram_done;
4034         }
4035
4036         csum = ether_crc_le(0x100, data + 0x100);
4037         if (csum != CRC32_RESIDUAL) {
4038                 rc = -ENODEV;
4039         }
4040
4041 test_nvram_done:
4042         return rc;
4043 }
4044
4045 static int
4046 bnx2_test_link(struct bnx2 *bp)
4047 {
4048         u32 bmsr;
4049
4050         spin_lock_bh(&bp->phy_lock);
4051         bnx2_read_phy(bp, MII_BMSR, &bmsr);
4052         bnx2_read_phy(bp, MII_BMSR, &bmsr);
4053         spin_unlock_bh(&bp->phy_lock);
4054                 
4055         if (bmsr & BMSR_LSTATUS) {
4056                 return 0;
4057         }
4058         return -ENODEV;
4059 }
4060
4061 static int
4062 bnx2_test_intr(struct bnx2 *bp)
4063 {
4064         int i;
4065         u32 val;
4066         u16 status_idx;
4067
4068         if (!netif_running(bp->dev))
4069                 return -ENODEV;
4070
4071         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4072
4073         /* This register is not touched during run-time. */
4074         val = REG_RD(bp, BNX2_HC_COMMAND);
4075         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
4076         REG_RD(bp, BNX2_HC_COMMAND);
4077
4078         for (i = 0; i < 10; i++) {
4079                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4080                         status_idx) {
4081
4082                         break;
4083                 }
4084
4085                 msleep_interruptible(10);
4086         }
4087         if (i < 10)
4088                 return 0;
4089
4090         return -ENODEV;
4091 }
4092
4093 static void
4094 bnx2_timer(unsigned long data)
4095 {
4096         struct bnx2 *bp = (struct bnx2 *) data;
4097         u32 msg;
4098
4099         if (!netif_running(bp->dev))
4100                 return;
4101
4102         if (atomic_read(&bp->intr_sem) != 0)
4103                 goto bnx2_restart_timer;
4104
4105         msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4106         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4107
4108         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4109             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
4110
4111                 spin_lock(&bp->phy_lock);
4112                 if (bp->serdes_an_pending) {
4113                         bp->serdes_an_pending--;
4114                 }
4115                 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4116                         u32 bmcr;
4117
4118                         bp->current_interval = bp->timer_interval;
4119
4120                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4121
4122                         if (bmcr & BMCR_ANENABLE) {
4123                                 u32 phy1, phy2;
4124
4125                                 bnx2_write_phy(bp, 0x1c, 0x7c00);
4126                                 bnx2_read_phy(bp, 0x1c, &phy1);
4127
4128                                 bnx2_write_phy(bp, 0x17, 0x0f01);
4129                                 bnx2_read_phy(bp, 0x15, &phy2);
4130                                 bnx2_write_phy(bp, 0x17, 0x0f01);
4131                                 bnx2_read_phy(bp, 0x15, &phy2);
4132
4133                                 if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
4134                                         !(phy2 & 0x20)) {       /* no CONFIG */
4135
4136                                         bmcr &= ~BMCR_ANENABLE;
4137                                         bmcr |= BMCR_SPEED1000 |
4138                                                 BMCR_FULLDPLX;
4139                                         bnx2_write_phy(bp, MII_BMCR, bmcr);
4140                                         bp->phy_flags |=
4141                                                 PHY_PARALLEL_DETECT_FLAG;
4142                                 }
4143                         }
4144                 }
4145                 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4146                         (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4147                         u32 phy2;
4148
4149                         bnx2_write_phy(bp, 0x17, 0x0f01);
4150                         bnx2_read_phy(bp, 0x15, &phy2);
4151                         if (phy2 & 0x20) {
4152                                 u32 bmcr;
4153
4154                                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4155                                 bmcr |= BMCR_ANENABLE;
4156                                 bnx2_write_phy(bp, MII_BMCR, bmcr);
4157
4158                                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4159
4160                         }
4161                 }
4162                 else
4163                         bp->current_interval = bp->timer_interval;
4164
4165                 spin_unlock(&bp->phy_lock);
4166         }
4167
4168 bnx2_restart_timer:
4169         mod_timer(&bp->timer, jiffies + bp->current_interval);
4170 }
4171
4172 /* Called with rtnl_lock */
4173 static int
4174 bnx2_open(struct net_device *dev)
4175 {
4176         struct bnx2 *bp = dev->priv;
4177         int rc;
4178
4179         bnx2_set_power_state(bp, PCI_D0);
4180         bnx2_disable_int(bp);
4181
4182         rc = bnx2_alloc_mem(bp);
4183         if (rc)
4184                 return rc;
4185
4186         if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4187                 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4188                 !disable_msi) {
4189
4190                 if (pci_enable_msi(bp->pdev) == 0) {
4191                         bp->flags |= USING_MSI_FLAG;
4192                         rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4193                                         dev);
4194                 }
4195                 else {
4196                         rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4197                                         SA_SHIRQ, dev->name, dev);
4198                 }
4199         }
4200         else {
4201                 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4202                                 dev->name, dev);
4203         }
4204         if (rc) {
4205                 bnx2_free_mem(bp);
4206                 return rc;
4207         }
4208
4209         rc = bnx2_init_nic(bp);
4210
4211         if (rc) {
4212                 free_irq(bp->pdev->irq, dev);
4213                 if (bp->flags & USING_MSI_FLAG) {
4214                         pci_disable_msi(bp->pdev);
4215                         bp->flags &= ~USING_MSI_FLAG;
4216                 }
4217                 bnx2_free_skbs(bp);
4218                 bnx2_free_mem(bp);
4219                 return rc;
4220         }
4221         
4222         mod_timer(&bp->timer, jiffies + bp->current_interval);
4223
4224         atomic_set(&bp->intr_sem, 0);
4225
4226         bnx2_enable_int(bp);
4227
4228         if (bp->flags & USING_MSI_FLAG) {
4229                 /* Test MSI to make sure it is working
4230                  * If MSI test fails, go back to INTx mode
4231                  */
4232                 if (bnx2_test_intr(bp) != 0) {
4233                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
4234                                " using MSI, switching to INTx mode. Please"
4235                                " report this failure to the PCI maintainer"
4236                                " and include system chipset information.\n",
4237                                bp->dev->name);
4238
4239                         bnx2_disable_int(bp);
4240                         free_irq(bp->pdev->irq, dev);
4241                         pci_disable_msi(bp->pdev);
4242                         bp->flags &= ~USING_MSI_FLAG;
4243
4244                         rc = bnx2_init_nic(bp);
4245
4246                         if (!rc) {
4247                                 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4248                                         SA_SHIRQ, dev->name, dev);
4249                         }
4250                         if (rc) {
4251                                 bnx2_free_skbs(bp);
4252                                 bnx2_free_mem(bp);
4253                                 del_timer_sync(&bp->timer);
4254                                 return rc;
4255                         }
4256                         bnx2_enable_int(bp);
4257                 }
4258         }
4259         if (bp->flags & USING_MSI_FLAG) {
4260                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4261         }
4262
4263         netif_start_queue(dev);
4264
4265         return 0;
4266 }
4267
4268 static void
4269 bnx2_reset_task(void *data)
4270 {
4271         struct bnx2 *bp = data;
4272
4273         if (!netif_running(bp->dev))
4274                 return;
4275
4276         bp->in_reset_task = 1;
4277         bnx2_netif_stop(bp);
4278
4279         bnx2_init_nic(bp);
4280
4281         atomic_set(&bp->intr_sem, 1);
4282         bnx2_netif_start(bp);
4283         bp->in_reset_task = 0;
4284 }
4285
4286 static void
4287 bnx2_tx_timeout(struct net_device *dev)
4288 {
4289         struct bnx2 *bp = dev->priv;
4290
4291         /* This allows the netif to be shutdown gracefully before resetting */
4292         schedule_work(&bp->reset_task);
4293 }
4294
4295 #ifdef BCM_VLAN
4296 /* Called with rtnl_lock */
4297 static void
4298 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4299 {
4300         struct bnx2 *bp = dev->priv;
4301
4302         bnx2_netif_stop(bp);
4303
4304         bp->vlgrp = vlgrp;
4305         bnx2_set_rx_mode(dev);
4306
4307         bnx2_netif_start(bp);
4308 }
4309
4310 /* Called with rtnl_lock */
4311 static void
4312 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4313 {
4314         struct bnx2 *bp = dev->priv;
4315
4316         bnx2_netif_stop(bp);
4317
4318         if (bp->vlgrp)
4319                 bp->vlgrp->vlan_devices[vid] = NULL;
4320         bnx2_set_rx_mode(dev);
4321
4322         bnx2_netif_start(bp);
4323 }
4324 #endif
4325
4326 /* Called with dev->xmit_lock.
4327  * hard_start_xmit is pseudo-lockless - a lock is only required when
4328  * the tx queue is full. This way, we get the benefit of lockless
4329  * operations most of the time without the complexities to handle
4330  * netif_stop_queue/wake_queue race conditions.
4331  */
4332 static int
4333 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4334 {
4335         struct bnx2 *bp = dev->priv;
4336         dma_addr_t mapping;
4337         struct tx_bd *txbd;
4338         struct sw_bd *tx_buf;
4339         u32 len, vlan_tag_flags, last_frag, mss;
4340         u16 prod, ring_prod;
4341         int i;
4342
4343         if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4344                 netif_stop_queue(dev);
4345                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4346                         dev->name);
4347
4348                 return NETDEV_TX_BUSY;
4349         }
4350         len = skb_headlen(skb);
4351         prod = bp->tx_prod;
4352         ring_prod = TX_RING_IDX(prod);
4353
4354         vlan_tag_flags = 0;
4355         if (skb->ip_summed == CHECKSUM_HW) {
4356                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4357         }
4358
4359         if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4360                 vlan_tag_flags |=
4361                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4362         }
4363 #ifdef BCM_TSO 
4364         if ((mss = skb_shinfo(skb)->tso_size) &&
4365                 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4366                 u32 tcp_opt_len, ip_tcp_len;
4367
4368                 if (skb_header_cloned(skb) &&
4369                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4370                         dev_kfree_skb(skb);
4371                         return NETDEV_TX_OK;
4372                 }
4373
4374                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4375                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4376
4377                 tcp_opt_len = 0;
4378                 if (skb->h.th->doff > 5) {
4379                         tcp_opt_len = (skb->h.th->doff - 5) << 2;
4380                 }
4381                 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4382
4383                 skb->nh.iph->check = 0;
4384                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4385                 skb->h.th->check =
4386                         ~csum_tcpudp_magic(skb->nh.iph->saddr,
4387                                             skb->nh.iph->daddr,
4388                                             0, IPPROTO_TCP, 0);
4389
4390                 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4391                         vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4392                                 (tcp_opt_len >> 2)) << 8;
4393                 }
4394         }
4395         else
4396 #endif
4397         {
4398                 mss = 0;
4399         }
4400
4401         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4402         
4403         tx_buf = &bp->tx_buf_ring[ring_prod];
4404         tx_buf->skb = skb;
4405         pci_unmap_addr_set(tx_buf, mapping, mapping);
4406
4407         txbd = &bp->tx_desc_ring[ring_prod];
4408
4409         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4410         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4411         txbd->tx_bd_mss_nbytes = len | (mss << 16);
4412         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4413
4414         last_frag = skb_shinfo(skb)->nr_frags;
4415
4416         for (i = 0; i < last_frag; i++) {
4417                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4418
4419                 prod = NEXT_TX_BD(prod);
4420                 ring_prod = TX_RING_IDX(prod);
4421                 txbd = &bp->tx_desc_ring[ring_prod];
4422
4423                 len = frag->size;
4424                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4425                         len, PCI_DMA_TODEVICE);
4426                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4427                                 mapping, mapping);
4428
4429                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4430                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4431                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4432                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4433
4434         }
4435         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4436
4437         prod = NEXT_TX_BD(prod);
4438         bp->tx_prod_bseq += skb->len;
4439
4440         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4441         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4442
4443         mmiowb();
4444
4445         bp->tx_prod = prod;
4446         dev->trans_start = jiffies;
4447
4448         if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4449                 spin_lock(&bp->tx_lock);
4450                 netif_stop_queue(dev);
4451                 
4452                 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4453                         netif_wake_queue(dev);
4454                 spin_unlock(&bp->tx_lock);
4455         }
4456
4457         return NETDEV_TX_OK;
4458 }
4459
4460 /* Called with rtnl_lock */
4461 static int
4462 bnx2_close(struct net_device *dev)
4463 {
4464         struct bnx2 *bp = dev->priv;
4465         u32 reset_code;
4466
4467         /* Calling flush_scheduled_work() may deadlock because
4468          * linkwatch_event() may be on the workqueue and it will try to get
4469          * the rtnl_lock which we are holding.
4470          */
4471         while (bp->in_reset_task)
4472                 msleep(1);
4473
4474         bnx2_netif_stop(bp);
4475         del_timer_sync(&bp->timer);
4476         if (bp->wol)
4477                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4478         else
4479                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4480         bnx2_reset_chip(bp, reset_code);
4481         free_irq(bp->pdev->irq, dev);
4482         if (bp->flags & USING_MSI_FLAG) {
4483                 pci_disable_msi(bp->pdev);
4484                 bp->flags &= ~USING_MSI_FLAG;
4485         }
4486         bnx2_free_skbs(bp);
4487         bnx2_free_mem(bp);
4488         bp->link_up = 0;
4489         netif_carrier_off(bp->dev);
4490         bnx2_set_power_state(bp, PCI_D3hot);
4491         return 0;
4492 }
4493
4494 #define GET_NET_STATS64(ctr)                                    \
4495         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
4496         (unsigned long) (ctr##_lo)
4497
4498 #define GET_NET_STATS32(ctr)            \
4499         (ctr##_lo)
4500
4501 #if (BITS_PER_LONG == 64)
4502 #define GET_NET_STATS   GET_NET_STATS64
4503 #else
4504 #define GET_NET_STATS   GET_NET_STATS32
4505 #endif
4506
4507 static struct net_device_stats *
4508 bnx2_get_stats(struct net_device *dev)
4509 {
4510         struct bnx2 *bp = dev->priv;
4511         struct statistics_block *stats_blk = bp->stats_blk;
4512         struct net_device_stats *net_stats = &bp->net_stats;
4513
4514         if (bp->stats_blk == NULL) {
4515                 return net_stats;
4516         }
4517         net_stats->rx_packets =
4518                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4519                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4520                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4521
4522         net_stats->tx_packets =
4523                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4524                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4525                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4526
4527         net_stats->rx_bytes =
4528                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4529
4530         net_stats->tx_bytes =
4531                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4532
4533         net_stats->multicast = 
4534                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4535
4536         net_stats->collisions = 
4537                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4538
4539         net_stats->rx_length_errors = 
4540                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4541                 stats_blk->stat_EtherStatsOverrsizePkts);
4542
4543         net_stats->rx_over_errors = 
4544                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4545
4546         net_stats->rx_frame_errors = 
4547                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4548
4549         net_stats->rx_crc_errors = 
4550                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4551
4552         net_stats->rx_errors = net_stats->rx_length_errors +
4553                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4554                 net_stats->rx_crc_errors;
4555
4556         net_stats->tx_aborted_errors =
4557                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4558                 stats_blk->stat_Dot3StatsLateCollisions);
4559
4560         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4561             (CHIP_ID(bp) == CHIP_ID_5708_A0))
4562                 net_stats->tx_carrier_errors = 0;
4563         else {
4564                 net_stats->tx_carrier_errors =
4565                         (unsigned long)
4566                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
4567         }
4568
4569         net_stats->tx_errors =
4570                 (unsigned long) 
4571                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4572                 +
4573                 net_stats->tx_aborted_errors +
4574                 net_stats->tx_carrier_errors;
4575
4576         return net_stats;
4577 }
4578
4579 /* All ethtool functions called with rtnl_lock */
4580
4581 static int
4582 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4583 {
4584         struct bnx2 *bp = dev->priv;
4585
4586         cmd->supported = SUPPORTED_Autoneg;
4587         if (bp->phy_flags & PHY_SERDES_FLAG) {
4588                 cmd->supported |= SUPPORTED_1000baseT_Full |
4589                         SUPPORTED_FIBRE;
4590
4591                 cmd->port = PORT_FIBRE;
4592         }
4593         else {
4594                 cmd->supported |= SUPPORTED_10baseT_Half |
4595                         SUPPORTED_10baseT_Full |
4596                         SUPPORTED_100baseT_Half |
4597                         SUPPORTED_100baseT_Full |
4598                         SUPPORTED_1000baseT_Full |
4599                         SUPPORTED_TP;
4600
4601                 cmd->port = PORT_TP;
4602         }
4603
4604         cmd->advertising = bp->advertising;
4605
4606         if (bp->autoneg & AUTONEG_SPEED) {
4607                 cmd->autoneg = AUTONEG_ENABLE;
4608         }
4609         else {
4610                 cmd->autoneg = AUTONEG_DISABLE;
4611         }
4612
4613         if (netif_carrier_ok(dev)) {
4614                 cmd->speed = bp->line_speed;
4615                 cmd->duplex = bp->duplex;
4616         }
4617         else {
4618                 cmd->speed = -1;
4619                 cmd->duplex = -1;
4620         }
4621
4622         cmd->transceiver = XCVR_INTERNAL;
4623         cmd->phy_address = bp->phy_addr;
4624
4625         return 0;
4626 }
4627   
4628 static int
4629 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4630 {
4631         struct bnx2 *bp = dev->priv;
4632         u8 autoneg = bp->autoneg;
4633         u8 req_duplex = bp->req_duplex;
4634         u16 req_line_speed = bp->req_line_speed;
4635         u32 advertising = bp->advertising;
4636
4637         if (cmd->autoneg == AUTONEG_ENABLE) {
4638                 autoneg |= AUTONEG_SPEED;
4639
4640                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; 
4641
4642                 /* allow advertising 1 speed */
4643                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4644                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
4645                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
4646                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
4647
4648                         if (bp->phy_flags & PHY_SERDES_FLAG)
4649                                 return -EINVAL;
4650
4651                         advertising = cmd->advertising;
4652
4653                 }
4654                 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4655                         advertising = cmd->advertising;
4656                 }
4657                 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4658                         return -EINVAL;
4659                 }
4660                 else {
4661                         if (bp->phy_flags & PHY_SERDES_FLAG) {
4662                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4663                         }
4664                         else {
4665                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
4666                         }
4667                 }
4668                 advertising |= ADVERTISED_Autoneg;
4669         }
4670         else {
4671                 if (bp->phy_flags & PHY_SERDES_FLAG) {
4672                         if ((cmd->speed != SPEED_1000) ||
4673                                 (cmd->duplex != DUPLEX_FULL)) {
4674                                 return -EINVAL;
4675                         }
4676                 }
4677                 else if (cmd->speed == SPEED_1000) {
4678                         return -EINVAL;
4679                 }
4680                 autoneg &= ~AUTONEG_SPEED;
4681                 req_line_speed = cmd->speed;
4682                 req_duplex = cmd->duplex;
4683                 advertising = 0;
4684         }
4685
4686         bp->autoneg = autoneg;
4687         bp->advertising = advertising;
4688         bp->req_line_speed = req_line_speed;
4689         bp->req_duplex = req_duplex;
4690
4691         spin_lock_bh(&bp->phy_lock);
4692
4693         bnx2_setup_phy(bp);
4694
4695         spin_unlock_bh(&bp->phy_lock);
4696
4697         return 0;
4698 }
4699
4700 static void
4701 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4702 {
4703         struct bnx2 *bp = dev->priv;
4704
4705         strcpy(info->driver, DRV_MODULE_NAME);
4706         strcpy(info->version, DRV_MODULE_VERSION);
4707         strcpy(info->bus_info, pci_name(bp->pdev));
4708         info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4709         info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4710         info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4711         info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4712         info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4713         info->fw_version[7] = 0;
4714 }
4715
4716 static void
4717 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4718 {
4719         struct bnx2 *bp = dev->priv;
4720
4721         if (bp->flags & NO_WOL_FLAG) {
4722                 wol->supported = 0;
4723                 wol->wolopts = 0;
4724         }
4725         else {
4726                 wol->supported = WAKE_MAGIC;
4727                 if (bp->wol)
4728                         wol->wolopts = WAKE_MAGIC;
4729                 else
4730                         wol->wolopts = 0;
4731         }
4732         memset(&wol->sopass, 0, sizeof(wol->sopass));
4733 }
4734
4735 static int
4736 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4737 {
4738         struct bnx2 *bp = dev->priv;
4739
4740         if (wol->wolopts & ~WAKE_MAGIC)
4741                 return -EINVAL;
4742
4743         if (wol->wolopts & WAKE_MAGIC) {
4744                 if (bp->flags & NO_WOL_FLAG)
4745                         return -EINVAL;
4746
4747                 bp->wol = 1;
4748         }
4749         else {
4750                 bp->wol = 0;
4751         }
4752         return 0;
4753 }
4754
4755 static int
4756 bnx2_nway_reset(struct net_device *dev)
4757 {
4758         struct bnx2 *bp = dev->priv;
4759         u32 bmcr;
4760
4761         if (!(bp->autoneg & AUTONEG_SPEED)) {
4762                 return -EINVAL;
4763         }
4764
4765         spin_lock_bh(&bp->phy_lock);
4766
4767         /* Force a link down visible on the other side */
4768         if (bp->phy_flags & PHY_SERDES_FLAG) {
4769                 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4770                 spin_unlock_bh(&bp->phy_lock);
4771
4772                 msleep(20);
4773
4774                 spin_lock_bh(&bp->phy_lock);
4775                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4776                         bp->current_interval = SERDES_AN_TIMEOUT;
4777                         bp->serdes_an_pending = 1;
4778                         mod_timer(&bp->timer, jiffies + bp->current_interval);
4779                 }
4780         }
4781
4782         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4783         bmcr &= ~BMCR_LOOPBACK;
4784         bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4785
4786         spin_unlock_bh(&bp->phy_lock);
4787
4788         return 0;
4789 }
4790
4791 static int
4792 bnx2_get_eeprom_len(struct net_device *dev)
4793 {
4794         struct bnx2 *bp = dev->priv;
4795
4796         if (bp->flash_info == 0)
4797                 return 0;
4798
4799         return (int) bp->flash_info->total_size;
4800 }
4801
4802 static int
4803 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4804                 u8 *eebuf)
4805 {
4806         struct bnx2 *bp = dev->priv;
4807         int rc;
4808
4809         /* parameters already validated in ethtool_get_eeprom */
4810
4811         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4812
4813         return rc;
4814 }
4815
4816 static int
4817 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4818                 u8 *eebuf)
4819 {
4820         struct bnx2 *bp = dev->priv;
4821         int rc;
4822
4823         /* parameters already validated in ethtool_set_eeprom */
4824
4825         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4826
4827         return rc;
4828 }
4829
4830 static int
4831 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4832 {
4833         struct bnx2 *bp = dev->priv;
4834
4835         memset(coal, 0, sizeof(struct ethtool_coalesce));
4836
4837         coal->rx_coalesce_usecs = bp->rx_ticks;
4838         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4839         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4840         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4841
4842         coal->tx_coalesce_usecs = bp->tx_ticks;
4843         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4844         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4845         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4846
4847         coal->stats_block_coalesce_usecs = bp->stats_ticks;
4848
4849         return 0;
4850 }
4851
4852 static int
4853 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4854 {
4855         struct bnx2 *bp = dev->priv;
4856
4857         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4858         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4859
4860         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; 
4861         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4862
4863         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4864         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4865
4866         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4867         if (bp->rx_quick_cons_trip_int > 0xff)
4868                 bp->rx_quick_cons_trip_int = 0xff;
4869
4870         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4871         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4872
4873         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4874         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4875
4876         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4877         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4878
4879         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4880         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4881                 0xff;
4882
4883         bp->stats_ticks = coal->stats_block_coalesce_usecs;
4884         if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4885         bp->stats_ticks &= 0xffff00;
4886
4887         if (netif_running(bp->dev)) {
4888                 bnx2_netif_stop(bp);
4889                 bnx2_init_nic(bp);
4890                 bnx2_netif_start(bp);
4891         }
4892
4893         return 0;
4894 }
4895
4896 static void
4897 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4898 {
4899         struct bnx2 *bp = dev->priv;
4900
4901         ering->rx_max_pending = MAX_RX_DESC_CNT;
4902         ering->rx_mini_max_pending = 0;
4903         ering->rx_jumbo_max_pending = 0;
4904
4905         ering->rx_pending = bp->rx_ring_size;
4906         ering->rx_mini_pending = 0;
4907         ering->rx_jumbo_pending = 0;
4908
4909         ering->tx_max_pending = MAX_TX_DESC_CNT;
4910         ering->tx_pending = bp->tx_ring_size;
4911 }
4912
4913 static int
4914 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4915 {
4916         struct bnx2 *bp = dev->priv;
4917
4918         if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4919                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4920                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4921
4922                 return -EINVAL;
4923         }
4924         bp->rx_ring_size = ering->rx_pending;
4925         bp->tx_ring_size = ering->tx_pending;
4926
4927         if (netif_running(bp->dev)) {
4928                 bnx2_netif_stop(bp);
4929                 bnx2_init_nic(bp);
4930                 bnx2_netif_start(bp);
4931         }
4932
4933         return 0;
4934 }
4935
4936 static void
4937 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4938 {
4939         struct bnx2 *bp = dev->priv;
4940
4941         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4942         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4943         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4944 }
4945
4946 static int
4947 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4948 {
4949         struct bnx2 *bp = dev->priv;
4950
4951         bp->req_flow_ctrl = 0;
4952         if (epause->rx_pause)
4953                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4954         if (epause->tx_pause)
4955                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4956
4957         if (epause->autoneg) {
4958                 bp->autoneg |= AUTONEG_FLOW_CTRL;
4959         }
4960         else {
4961                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4962         }
4963
4964         spin_lock_bh(&bp->phy_lock);
4965
4966         bnx2_setup_phy(bp);
4967
4968         spin_unlock_bh(&bp->phy_lock);
4969
4970         return 0;
4971 }
4972
4973 static u32
4974 bnx2_get_rx_csum(struct net_device *dev)
4975 {
4976         struct bnx2 *bp = dev->priv;
4977
4978         return bp->rx_csum;
4979 }
4980
4981 static int
4982 bnx2_set_rx_csum(struct net_device *dev, u32 data)
4983 {
4984         struct bnx2 *bp = dev->priv;
4985
4986         bp->rx_csum = data;
4987         return 0;
4988 }
4989
4990 #define BNX2_NUM_STATS 45
4991
4992 static struct {
4993         char string[ETH_GSTRING_LEN];
4994 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4995         { "rx_bytes" },
4996         { "rx_error_bytes" },
4997         { "tx_bytes" },
4998         { "tx_error_bytes" },
4999         { "rx_ucast_packets" },
5000         { "rx_mcast_packets" },
5001         { "rx_bcast_packets" },
5002         { "tx_ucast_packets" },
5003         { "tx_mcast_packets" },
5004         { "tx_bcast_packets" },
5005         { "tx_mac_errors" },
5006         { "tx_carrier_errors" },
5007         { "rx_crc_errors" },
5008         { "rx_align_errors" },
5009         { "tx_single_collisions" },
5010         { "tx_multi_collisions" },
5011         { "tx_deferred" },
5012         { "tx_excess_collisions" },
5013         { "tx_late_collisions" },
5014         { "tx_total_collisions" },
5015         { "rx_fragments" },
5016         { "rx_jabbers" },
5017         { "rx_undersize_packets" },
5018         { "rx_oversize_packets" },
5019         { "rx_64_byte_packets" },
5020         { "rx_65_to_127_byte_packets" },
5021         { "rx_128_to_255_byte_packets" },
5022         { "rx_256_to_511_byte_packets" },
5023         { "rx_512_to_1023_byte_packets" },
5024         { "rx_1024_to_1522_byte_packets" },
5025         { "rx_1523_to_9022_byte_packets" },
5026         { "tx_64_byte_packets" },
5027         { "tx_65_to_127_byte_packets" },
5028         { "tx_128_to_255_byte_packets" },
5029         { "tx_256_to_511_byte_packets" },
5030         { "tx_512_to_1023_byte_packets" },
5031         { "tx_1024_to_1522_byte_packets" },
5032         { "tx_1523_to_9022_byte_packets" },
5033         { "rx_xon_frames" },
5034         { "rx_xoff_frames" },
5035         { "tx_xon_frames" },
5036         { "tx_xoff_frames" },
5037         { "rx_mac_ctrl_frames" },
5038         { "rx_filtered_packets" },
5039         { "rx_discards" },
5040 };
5041
5042 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5043
5044 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5045     STATS_OFFSET32(stat_IfHCInOctets_hi),
5046     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5047     STATS_OFFSET32(stat_IfHCOutOctets_hi),
5048     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5049     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5050     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5051     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5052     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5053     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5054     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5055     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5056     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),                 
5057     STATS_OFFSET32(stat_Dot3StatsFCSErrors),                          
5058     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),                    
5059     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),              
5060     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),            
5061     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),              
5062     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),                
5063     STATS_OFFSET32(stat_Dot3StatsLateCollisions),                     
5064     STATS_OFFSET32(stat_EtherStatsCollisions),                        
5065     STATS_OFFSET32(stat_EtherStatsFragments),                         
5066     STATS_OFFSET32(stat_EtherStatsJabbers),                           
5067     STATS_OFFSET32(stat_EtherStatsUndersizePkts),                     
5068     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),                     
5069     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),                    
5070     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),         
5071     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),        
5072     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),        
5073     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),       
5074     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),      
5075     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),      
5076     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),                    
5077     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),         
5078     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),        
5079     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),        
5080     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),       
5081     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),      
5082     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),      
5083     STATS_OFFSET32(stat_XonPauseFramesReceived),                      
5084     STATS_OFFSET32(stat_XoffPauseFramesReceived),                     
5085     STATS_OFFSET32(stat_OutXonSent),                                  
5086     STATS_OFFSET32(stat_OutXoffSent),                                 
5087     STATS_OFFSET32(stat_MacControlFramesReceived),                    
5088     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),                  
5089     STATS_OFFSET32(stat_IfInMBUFDiscards),                            
5090 };
5091
5092 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5093  * skipped because of errata.
5094  */               
5095 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5096         8,0,8,8,8,8,8,8,8,8,
5097         4,0,4,4,4,4,4,4,4,4,
5098         4,4,4,4,4,4,4,4,4,4,
5099         4,4,4,4,4,4,4,4,4,4,
5100         4,4,4,4,4,
5101 };
5102
5103 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5104         8,0,8,8,8,8,8,8,8,8,
5105         4,4,4,4,4,4,4,4,4,4,
5106         4,4,4,4,4,4,4,4,4,4,
5107         4,4,4,4,4,4,4,4,4,4,
5108         4,4,4,4,4,
5109 };
5110
5111 #define BNX2_NUM_TESTS 6
5112
5113 static struct {
5114         char string[ETH_GSTRING_LEN];
5115 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5116         { "register_test (offline)" },
5117         { "memory_test (offline)" },
5118         { "loopback_test (offline)" },
5119         { "nvram_test (online)" },
5120         { "interrupt_test (online)" },
5121         { "link_test (online)" },
5122 };
5123
5124 static int
5125 bnx2_self_test_count(struct net_device *dev)
5126 {
5127         return BNX2_NUM_TESTS;
5128 }
5129
5130 static void
5131 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5132 {
5133         struct bnx2 *bp = dev->priv;
5134
5135         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5136         if (etest->flags & ETH_TEST_FL_OFFLINE) {
5137                 bnx2_netif_stop(bp);
5138                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5139                 bnx2_free_skbs(bp);
5140
5141                 if (bnx2_test_registers(bp) != 0) {
5142                         buf[0] = 1;
5143                         etest->flags |= ETH_TEST_FL_FAILED;
5144                 }
5145                 if (bnx2_test_memory(bp) != 0) {
5146                         buf[1] = 1;
5147                         etest->flags |= ETH_TEST_FL_FAILED;
5148                 }
5149                 if (bnx2_test_loopback(bp) != 0) {
5150                         buf[2] = 1;
5151                         etest->flags |= ETH_TEST_FL_FAILED;
5152                 }
5153
5154                 if (!netif_running(bp->dev)) {
5155                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5156                 }
5157                 else {
5158                         bnx2_init_nic(bp);
5159                         bnx2_netif_start(bp);
5160                 }
5161
5162                 /* wait for link up */
5163                 msleep_interruptible(3000);
5164                 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5165                         msleep_interruptible(4000);
5166         }
5167
5168         if (bnx2_test_nvram(bp) != 0) {
5169                 buf[3] = 1;
5170                 etest->flags |= ETH_TEST_FL_FAILED;
5171         }
5172         if (bnx2_test_intr(bp) != 0) {
5173                 buf[4] = 1;
5174                 etest->flags |= ETH_TEST_FL_FAILED;
5175         }
5176
5177         if (bnx2_test_link(bp) != 0) {
5178                 buf[5] = 1;
5179                 etest->flags |= ETH_TEST_FL_FAILED;
5180
5181         }
5182 }
5183
5184 static void
5185 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5186 {
5187         switch (stringset) {
5188         case ETH_SS_STATS:
5189                 memcpy(buf, bnx2_stats_str_arr,
5190                         sizeof(bnx2_stats_str_arr));
5191                 break;
5192         case ETH_SS_TEST:
5193                 memcpy(buf, bnx2_tests_str_arr,
5194                         sizeof(bnx2_tests_str_arr));
5195                 break;
5196         }
5197 }
5198
5199 static int
5200 bnx2_get_stats_count(struct net_device *dev)
5201 {
5202         return BNX2_NUM_STATS;
5203 }
5204
5205 static void
5206 bnx2_get_ethtool_stats(struct net_device *dev,
5207                 struct ethtool_stats *stats, u64 *buf)
5208 {
5209         struct bnx2 *bp = dev->priv;
5210         int i;
5211         u32 *hw_stats = (u32 *) bp->stats_blk;
5212         u8 *stats_len_arr = NULL;
5213
5214         if (hw_stats == NULL) {
5215                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5216                 return;
5217         }
5218
5219         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5220             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5221             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5222             (CHIP_ID(bp) == CHIP_ID_5708_A0))
5223                 stats_len_arr = bnx2_5706_stats_len_arr;
5224         else
5225                 stats_len_arr = bnx2_5708_stats_len_arr;
5226
5227         for (i = 0; i < BNX2_NUM_STATS; i++) {
5228                 if (stats_len_arr[i] == 0) {
5229                         /* skip this counter */
5230                         buf[i] = 0;
5231                         continue;
5232                 }
5233                 if (stats_len_arr[i] == 4) {
5234                         /* 4-byte counter */
5235                         buf[i] = (u64)
5236                                 *(hw_stats + bnx2_stats_offset_arr[i]);
5237                         continue;
5238                 }
5239                 /* 8-byte counter */
5240                 buf[i] = (((u64) *(hw_stats +
5241                                         bnx2_stats_offset_arr[i])) << 32) +
5242                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5243         }
5244 }
5245
5246 static int
5247 bnx2_phys_id(struct net_device *dev, u32 data)
5248 {
5249         struct bnx2 *bp = dev->priv;
5250         int i;
5251         u32 save;
5252
5253         if (data == 0)
5254                 data = 2;
5255
5256         save = REG_RD(bp, BNX2_MISC_CFG);
5257         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5258
5259         for (i = 0; i < (data * 2); i++) {
5260                 if ((i % 2) == 0) {
5261                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5262                 }
5263                 else {
5264                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5265                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
5266                                 BNX2_EMAC_LED_100MB_OVERRIDE |
5267                                 BNX2_EMAC_LED_10MB_OVERRIDE |
5268                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5269                                 BNX2_EMAC_LED_TRAFFIC);
5270                 }
5271                 msleep_interruptible(500);
5272                 if (signal_pending(current))
5273                         break;
5274         }
5275         REG_WR(bp, BNX2_EMAC_LED, 0);
5276         REG_WR(bp, BNX2_MISC_CFG, save);
5277         return 0;
5278 }
5279
5280 static struct ethtool_ops bnx2_ethtool_ops = {
5281         .get_settings           = bnx2_get_settings,
5282         .set_settings           = bnx2_set_settings,
5283         .get_drvinfo            = bnx2_get_drvinfo,
5284         .get_wol                = bnx2_get_wol,
5285         .set_wol                = bnx2_set_wol,
5286         .nway_reset             = bnx2_nway_reset,
5287         .get_link               = ethtool_op_get_link,
5288         .get_eeprom_len         = bnx2_get_eeprom_len,
5289         .get_eeprom             = bnx2_get_eeprom,
5290         .set_eeprom             = bnx2_set_eeprom,
5291         .get_coalesce           = bnx2_get_coalesce,
5292         .set_coalesce           = bnx2_set_coalesce,
5293         .get_ringparam          = bnx2_get_ringparam,
5294         .set_ringparam          = bnx2_set_ringparam,
5295         .get_pauseparam         = bnx2_get_pauseparam,
5296         .set_pauseparam         = bnx2_set_pauseparam,
5297         .get_rx_csum            = bnx2_get_rx_csum,
5298         .set_rx_csum            = bnx2_set_rx_csum,
5299         .get_tx_csum            = ethtool_op_get_tx_csum,
5300         .set_tx_csum            = ethtool_op_set_tx_csum,
5301         .get_sg                 = ethtool_op_get_sg,
5302         .set_sg                 = ethtool_op_set_sg,
5303 #ifdef BCM_TSO
5304         .get_tso                = ethtool_op_get_tso,
5305         .set_tso                = ethtool_op_set_tso,
5306 #endif
5307         .self_test_count        = bnx2_self_test_count,
5308         .self_test              = bnx2_self_test,
5309         .get_strings            = bnx2_get_strings,
5310         .phys_id                = bnx2_phys_id,
5311         .get_stats_count        = bnx2_get_stats_count,
5312         .get_ethtool_stats      = bnx2_get_ethtool_stats,
5313         .get_perm_addr          = ethtool_op_get_perm_addr,
5314 };
5315
5316 /* Called with rtnl_lock */
5317 static int
5318 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5319 {
5320         struct mii_ioctl_data *data = if_mii(ifr);
5321         struct bnx2 *bp = dev->priv;
5322         int err;
5323
5324         switch(cmd) {
5325         case SIOCGMIIPHY:
5326                 data->phy_id = bp->phy_addr;
5327
5328                 /* fallthru */
5329         case SIOCGMIIREG: {
5330                 u32 mii_regval;
5331
5332                 spin_lock_bh(&bp->phy_lock);
5333                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5334                 spin_unlock_bh(&bp->phy_lock);
5335
5336                 data->val_out = mii_regval;
5337
5338                 return err;
5339         }
5340
5341         case SIOCSMIIREG:
5342                 if (!capable(CAP_NET_ADMIN))
5343                         return -EPERM;
5344
5345                 spin_lock_bh(&bp->phy_lock);
5346                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5347                 spin_unlock_bh(&bp->phy_lock);
5348
5349                 return err;
5350
5351         default:
5352                 /* do nothing */
5353                 break;
5354         }
5355         return -EOPNOTSUPP;
5356 }
5357
5358 /* Called with rtnl_lock */
5359 static int
5360 bnx2_change_mac_addr(struct net_device *dev, void *p)
5361 {
5362         struct sockaddr *addr = p;
5363         struct bnx2 *bp = dev->priv;
5364
5365         if (!is_valid_ether_addr(addr->sa_data))
5366                 return -EINVAL;
5367
5368         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5369         if (netif_running(dev))
5370                 bnx2_set_mac_addr(bp);
5371
5372         return 0;
5373 }
5374
5375 /* Called with rtnl_lock */
5376 static int
5377 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5378 {
5379         struct bnx2 *bp = dev->priv;
5380
5381         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5382                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5383                 return -EINVAL;
5384
5385         dev->mtu = new_mtu;
5386         if (netif_running(dev)) {
5387                 bnx2_netif_stop(bp);
5388
5389                 bnx2_init_nic(bp);
5390
5391                 bnx2_netif_start(bp);
5392         }
5393         return 0;
5394 }
5395
5396 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5397 static void
5398 poll_bnx2(struct net_device *dev)
5399 {
5400         struct bnx2 *bp = dev->priv;
5401
5402         disable_irq(bp->pdev->irq);
5403         bnx2_interrupt(bp->pdev->irq, dev, NULL);
5404         enable_irq(bp->pdev->irq);
5405 }
5406 #endif
5407
5408 static int __devinit
5409 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5410 {
5411         struct bnx2 *bp;
5412         unsigned long mem_len;
5413         int rc;
5414         u32 reg;
5415
5416         SET_MODULE_OWNER(dev);
5417         SET_NETDEV_DEV(dev, &pdev->dev);
5418         bp = dev->priv;
5419
5420         bp->flags = 0;
5421         bp->phy_flags = 0;
5422
5423         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5424         rc = pci_enable_device(pdev);
5425         if (rc) {
5426                 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5427                 goto err_out;
5428         }
5429
5430         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5431                 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5432                        "aborting.\n");
5433                 rc = -ENODEV;
5434                 goto err_out_disable;
5435         }
5436
5437         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5438         if (rc) {
5439                 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5440                 goto err_out_disable;
5441         }
5442
5443         pci_set_master(pdev);
5444
5445         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5446         if (bp->pm_cap == 0) {
5447                 printk(KERN_ERR PFX "Cannot find power management capability, "
5448                                "aborting.\n");
5449                 rc = -EIO;
5450                 goto err_out_release;
5451         }
5452
5453         bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5454         if (bp->pcix_cap == 0) {
5455                 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5456                 rc = -EIO;
5457                 goto err_out_release;
5458         }
5459
5460         if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5461                 bp->flags |= USING_DAC_FLAG;
5462                 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5463                         printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5464                                "failed, aborting.\n");
5465                         rc = -EIO;
5466                         goto err_out_release;
5467                 }
5468         }
5469         else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5470                 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5471                 rc = -EIO;
5472                 goto err_out_release;
5473         }
5474
5475         bp->dev = dev;
5476         bp->pdev = pdev;
5477
5478         spin_lock_init(&bp->phy_lock);
5479         spin_lock_init(&bp->tx_lock);
5480         INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5481
5482         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5483         mem_len = MB_GET_CID_ADDR(17);
5484         dev->mem_end = dev->mem_start + mem_len;
5485         dev->irq = pdev->irq;
5486
5487         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5488
5489         if (!bp->regview) {
5490                 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5491                 rc = -ENOMEM;
5492                 goto err_out_release;
5493         }
5494
5495         /* Configure byte swap and enable write to the reg_window registers.
5496          * Rely on CPU to do target byte swapping on big endian systems
5497          * The chip's target access swapping will not swap all accesses
5498          */
5499         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5500                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5501                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5502
5503         bnx2_set_power_state(bp, PCI_D0);
5504
5505         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5506
5507         /* Get bus information. */
5508         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5509         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5510                 u32 clkreg;
5511
5512                 bp->flags |= PCIX_FLAG;
5513
5514                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5515                 
5516                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5517                 switch (clkreg) {
5518                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5519                         bp->bus_speed_mhz = 133;
5520                         break;
5521
5522                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5523                         bp->bus_speed_mhz = 100;
5524                         break;
5525
5526                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5527                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5528                         bp->bus_speed_mhz = 66;
5529                         break;
5530
5531                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5532                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5533                         bp->bus_speed_mhz = 50;
5534                         break;
5535
5536                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5537                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5538                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5539                         bp->bus_speed_mhz = 33;
5540                         break;
5541                 }
5542         }
5543         else {
5544                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5545                         bp->bus_speed_mhz = 66;
5546                 else
5547                         bp->bus_speed_mhz = 33;
5548         }
5549
5550         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5551                 bp->flags |= PCI_32BIT_FLAG;
5552
5553         /* 5706A0 may falsely detect SERR and PERR. */
5554         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5555                 reg = REG_RD(bp, PCI_COMMAND);
5556                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5557                 REG_WR(bp, PCI_COMMAND, reg);
5558         }
5559         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5560                 !(bp->flags & PCIX_FLAG)) {
5561
5562                 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5563                        "aborting.\n");
5564                 goto err_out_unmap;
5565         }
5566
5567         bnx2_init_nvram(bp);
5568
5569         reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5570
5571         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5572             BNX2_SHM_HDR_SIGNATURE_SIG)
5573                 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5574         else
5575                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5576
5577         /* Get the permanent MAC address.  First we need to make sure the
5578          * firmware is actually running.
5579          */
5580         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
5581
5582         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5583             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5584                 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5585                 rc = -ENODEV;
5586                 goto err_out_unmap;
5587         }
5588
5589         bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
5590
5591         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
5592         bp->mac_addr[0] = (u8) (reg >> 8);
5593         bp->mac_addr[1] = (u8) reg;
5594
5595         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
5596         bp->mac_addr[2] = (u8) (reg >> 24);
5597         bp->mac_addr[3] = (u8) (reg >> 16);
5598         bp->mac_addr[4] = (u8) (reg >> 8);
5599         bp->mac_addr[5] = (u8) reg;
5600
5601         bp->tx_ring_size = MAX_TX_DESC_CNT;
5602         bp->rx_ring_size = 100;
5603
5604         bp->rx_csum = 1;
5605
5606         bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5607
5608         bp->tx_quick_cons_trip_int = 20;
5609         bp->tx_quick_cons_trip = 20;
5610         bp->tx_ticks_int = 80;
5611         bp->tx_ticks = 80;
5612                 
5613         bp->rx_quick_cons_trip_int = 6;
5614         bp->rx_quick_cons_trip = 6;
5615         bp->rx_ticks_int = 18;
5616         bp->rx_ticks = 18;
5617
5618         bp->stats_ticks = 1000000 & 0xffff00;
5619
5620         bp->timer_interval =  HZ;
5621         bp->current_interval =  HZ;
5622
5623         bp->phy_addr = 1;
5624
5625         /* Disable WOL support if we are running on a SERDES chip. */
5626         if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5627                 bp->phy_flags |= PHY_SERDES_FLAG;
5628                 bp->flags |= NO_WOL_FLAG;
5629                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5630                         bp->phy_addr = 2;
5631                         reg = REG_RD_IND(bp, bp->shmem_base +
5632                                          BNX2_SHARED_HW_CFG_CONFIG);
5633                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5634                                 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5635                 }
5636         }
5637
5638         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5639                 bp->tx_quick_cons_trip_int =
5640                         bp->tx_quick_cons_trip;
5641                 bp->tx_ticks_int = bp->tx_ticks;
5642                 bp->rx_quick_cons_trip_int =
5643                         bp->rx_quick_cons_trip;
5644                 bp->rx_ticks_int = bp->rx_ticks;
5645                 bp->comp_prod_trip_int = bp->comp_prod_trip;
5646                 bp->com_ticks_int = bp->com_ticks;
5647                 bp->cmd_ticks_int = bp->cmd_ticks;
5648         }
5649
5650         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5651         bp->req_line_speed = 0;
5652         if (bp->phy_flags & PHY_SERDES_FLAG) {
5653                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5654
5655                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
5656                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5657                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5658                         bp->autoneg = 0;
5659                         bp->req_line_speed = bp->line_speed = SPEED_1000;
5660                         bp->req_duplex = DUPLEX_FULL;
5661                 }
5662         }
5663         else {
5664                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5665         }
5666
5667         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5668
5669         init_timer(&bp->timer);
5670         bp->timer.expires = RUN_AT(bp->timer_interval);
5671         bp->timer.data = (unsigned long) bp;
5672         bp->timer.function = bnx2_timer;
5673
5674         return 0;
5675
5676 err_out_unmap:
5677         if (bp->regview) {
5678                 iounmap(bp->regview);
5679                 bp->regview = NULL;
5680         }
5681
5682 err_out_release:
5683         pci_release_regions(pdev);
5684
5685 err_out_disable:
5686         pci_disable_device(pdev);
5687         pci_set_drvdata(pdev, NULL);
5688
5689 err_out:
5690         return rc;
5691 }
5692
5693 static int __devinit
5694 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5695 {
5696         static int version_printed = 0;
5697         struct net_device *dev = NULL;
5698         struct bnx2 *bp;
5699         int rc, i;
5700
5701         if (version_printed++ == 0)
5702                 printk(KERN_INFO "%s", version);
5703
5704         /* dev zeroed in init_etherdev */
5705         dev = alloc_etherdev(sizeof(*bp));
5706
5707         if (!dev)
5708                 return -ENOMEM;
5709
5710         rc = bnx2_init_board(pdev, dev);
5711         if (rc < 0) {
5712                 free_netdev(dev);
5713                 return rc;
5714         }
5715
5716         dev->open = bnx2_open;
5717         dev->hard_start_xmit = bnx2_start_xmit;
5718         dev->stop = bnx2_close;
5719         dev->get_stats = bnx2_get_stats;
5720         dev->set_multicast_list = bnx2_set_rx_mode;
5721         dev->do_ioctl = bnx2_ioctl;
5722         dev->set_mac_address = bnx2_change_mac_addr;
5723         dev->change_mtu = bnx2_change_mtu;
5724         dev->tx_timeout = bnx2_tx_timeout;
5725         dev->watchdog_timeo = TX_TIMEOUT;
5726 #ifdef BCM_VLAN
5727         dev->vlan_rx_register = bnx2_vlan_rx_register;
5728         dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5729 #endif
5730         dev->poll = bnx2_poll;
5731         dev->ethtool_ops = &bnx2_ethtool_ops;
5732         dev->weight = 64;
5733
5734         bp = dev->priv;
5735
5736 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5737         dev->poll_controller = poll_bnx2;
5738 #endif
5739
5740         if ((rc = register_netdev(dev))) {
5741                 printk(KERN_ERR PFX "Cannot register net device\n");
5742                 if (bp->regview)
5743                         iounmap(bp->regview);
5744                 pci_release_regions(pdev);
5745                 pci_disable_device(pdev);
5746                 pci_set_drvdata(pdev, NULL);
5747                 free_netdev(dev);
5748                 return rc;
5749         }
5750
5751         pci_set_drvdata(pdev, dev);
5752
5753         memcpy(dev->dev_addr, bp->mac_addr, 6);
5754         memcpy(dev->perm_addr, bp->mac_addr, 6);
5755         bp->name = board_info[ent->driver_data].name,
5756         printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5757                 "IRQ %d, ",
5758                 dev->name,
5759                 bp->name,
5760                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5761                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5762                 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5763                 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5764                 bp->bus_speed_mhz,
5765                 dev->base_addr,
5766                 bp->pdev->irq);
5767
5768         printk("node addr ");
5769         for (i = 0; i < 6; i++)
5770                 printk("%2.2x", dev->dev_addr[i]);
5771         printk("\n");
5772
5773         dev->features |= NETIF_F_SG;
5774         if (bp->flags & USING_DAC_FLAG)
5775                 dev->features |= NETIF_F_HIGHDMA;
5776         dev->features |= NETIF_F_IP_CSUM;
5777 #ifdef BCM_VLAN
5778         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5779 #endif
5780 #ifdef BCM_TSO
5781         dev->features |= NETIF_F_TSO;
5782 #endif
5783
5784         netif_carrier_off(bp->dev);
5785
5786         return 0;
5787 }
5788
5789 static void __devexit
5790 bnx2_remove_one(struct pci_dev *pdev)
5791 {
5792         struct net_device *dev = pci_get_drvdata(pdev);
5793         struct bnx2 *bp = dev->priv;
5794
5795         flush_scheduled_work();
5796
5797         unregister_netdev(dev);
5798
5799         if (bp->regview)
5800                 iounmap(bp->regview);
5801
5802         free_netdev(dev);
5803         pci_release_regions(pdev);
5804         pci_disable_device(pdev);
5805         pci_set_drvdata(pdev, NULL);
5806 }
5807
5808 static int
5809 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5810 {
5811         struct net_device *dev = pci_get_drvdata(pdev);
5812         struct bnx2 *bp = dev->priv;
5813         u32 reset_code;
5814
5815         if (!netif_running(dev))
5816                 return 0;
5817
5818         bnx2_netif_stop(bp);
5819         netif_device_detach(dev);
5820         del_timer_sync(&bp->timer);
5821         if (bp->wol)
5822                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5823         else
5824                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5825         bnx2_reset_chip(bp, reset_code);
5826         bnx2_free_skbs(bp);
5827         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5828         return 0;
5829 }
5830
5831 static int
5832 bnx2_resume(struct pci_dev *pdev)
5833 {
5834         struct net_device *dev = pci_get_drvdata(pdev);
5835         struct bnx2 *bp = dev->priv;
5836
5837         if (!netif_running(dev))
5838                 return 0;
5839
5840         bnx2_set_power_state(bp, PCI_D0);
5841         netif_device_attach(dev);
5842         bnx2_init_nic(bp);
5843         bnx2_netif_start(bp);
5844         return 0;
5845 }
5846
5847 static struct pci_driver bnx2_pci_driver = {
5848         .name           = DRV_MODULE_NAME,
5849         .id_table       = bnx2_pci_tbl,
5850         .probe          = bnx2_init_one,
5851         .remove         = __devexit_p(bnx2_remove_one),
5852         .suspend        = bnx2_suspend,
5853         .resume         = bnx2_resume,
5854 };
5855
5856 static int __init bnx2_init(void)
5857 {
5858         return pci_module_init(&bnx2_pci_driver);
5859 }
5860
5861 static void __exit bnx2_cleanup(void)
5862 {
5863         pci_unregister_driver(&bnx2_pci_driver);
5864 }
5865
5866 module_init(bnx2_init);
5867 module_exit(bnx2_cleanup);
5868
5869
5870