[NET]: Fix NAPI completion handling in some drivers.
[linux-2.6.git] / drivers / net / bnx2.c
1 /* bnx2.c: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004-2007 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <asm/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
40 #define BCM_VLAN 1
41 #endif
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
50
51 #include "bnx2.h"
52 #include "bnx2_fw.h"
53 #include "bnx2_fw2.h"
54
55 #define FW_BUF_SIZE             0x8000
56
57 #define DRV_MODULE_NAME         "bnx2"
58 #define PFX DRV_MODULE_NAME     ": "
59 #define DRV_MODULE_VERSION      "1.6.7"
60 #define DRV_MODULE_RELDATE      "October 10, 2007"
61
62 #define RUN_AT(x) (jiffies + (x))
63
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT  (5*HZ)
66
67 static const char version[] __devinitdata =
68         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
74
75 static int disable_msi = 0;
76
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80 typedef enum {
81         BCM5706 = 0,
82         NC370T,
83         NC370I,
84         BCM5706S,
85         NC370F,
86         BCM5708,
87         BCM5708S,
88         BCM5709,
89         BCM5709S,
90 } board_t;
91
92 /* indexed by board_t, above */
93 static const struct {
94         char *name;
95 } board_info[] __devinitdata = {
96         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97         { "HP NC370T Multifunction Gigabit Server Adapter" },
98         { "HP NC370i Multifunction Gigabit Server Adapter" },
99         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100         { "HP NC370F Multifunction Gigabit Server Adapter" },
101         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
104         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
105         };
106
107 static struct pci_device_id bnx2_pci_tbl[] = {
108         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
114         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
116         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
120         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
122         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
124         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
126         { 0, }
127 };
128
129 static struct flash_spec flash_table[] =
130 {
131 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
133         /* Slow EEPROM */
134         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
135          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
136          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137          "EEPROM - slow"},
138         /* Expansion entry 0001 */
139         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
140          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
141          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142          "Entry 0001"},
143         /* Saifun SA25F010 (non-buffered flash) */
144         /* strap, cfg1, & write1 need updates */
145         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
146          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148          "Non-buffered flash (128kB)"},
149         /* Saifun SA25F020 (non-buffered flash) */
150         /* strap, cfg1, & write1 need updates */
151         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
152          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
153          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154          "Non-buffered flash (256kB)"},
155         /* Expansion entry 0100 */
156         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
157          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159          "Entry 0100"},
160         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
161         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
162          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
163          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
167          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
168          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170         /* Saifun SA25F005 (non-buffered flash) */
171         /* strap, cfg1, & write1 need updates */
172         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
173          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175          "Non-buffered flash (64kB)"},
176         /* Fast EEPROM */
177         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
178          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
179          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180          "EEPROM - fast"},
181         /* Expansion entry 1001 */
182         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
183          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
184          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185          "Entry 1001"},
186         /* Expansion entry 1010 */
187         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190          "Entry 1010"},
191         /* ATMEL AT45DB011B (buffered flash) */
192         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
193          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
194          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195          "Buffered flash (128kB)"},
196         /* Expansion entry 1100 */
197         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
198          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
199          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200          "Entry 1100"},
201         /* Expansion entry 1101 */
202         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
203          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205          "Entry 1101"},
206         /* Ateml Expansion entry 1110 */
207         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
208          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
209          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210          "Entry 1110 (Atmel)"},
211         /* ATMEL AT45DB021B (buffered flash) */
212         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
213          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215          "Buffered flash (256kB)"},
216 };
217
218 static struct flash_spec flash_5709 = {
219         .flags          = BNX2_NV_BUFFERED,
220         .page_bits      = BCM5709_FLASH_PAGE_BITS,
221         .page_size      = BCM5709_FLASH_PAGE_SIZE,
222         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
223         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
224         .name           = "5709 Buffered flash (256kB)",
225 };
226
227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
229 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
230 {
231         u32 diff;
232
233         smp_mb();
234
235         /* The ring uses 256 indices for 255 entries, one of them
236          * needs to be skipped.
237          */
238         diff = bp->tx_prod - bp->tx_cons;
239         if (unlikely(diff >= TX_DESC_CNT)) {
240                 diff &= 0xffff;
241                 if (diff == TX_DESC_CNT)
242                         diff = MAX_TX_DESC_CNT;
243         }
244         return (bp->tx_ring_size - diff);
245 }
246
247 static u32
248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249 {
250         u32 val;
251
252         spin_lock_bh(&bp->indirect_lock);
253         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
254         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255         spin_unlock_bh(&bp->indirect_lock);
256         return val;
257 }
258
259 static void
260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261 {
262         spin_lock_bh(&bp->indirect_lock);
263         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
265         spin_unlock_bh(&bp->indirect_lock);
266 }
267
268 static void
269 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
270 {
271         offset += cid_addr;
272         spin_lock_bh(&bp->indirect_lock);
273         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
274                 int i;
275
276                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
277                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
278                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
279                 for (i = 0; i < 5; i++) {
280                         u32 val;
281                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
282                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
283                                 break;
284                         udelay(5);
285                 }
286         } else {
287                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
288                 REG_WR(bp, BNX2_CTX_DATA, val);
289         }
290         spin_unlock_bh(&bp->indirect_lock);
291 }
292
293 static int
294 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
295 {
296         u32 val1;
297         int i, ret;
298
299         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
300                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
301                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
302
303                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
304                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
305
306                 udelay(40);
307         }
308
309         val1 = (bp->phy_addr << 21) | (reg << 16) |
310                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
311                 BNX2_EMAC_MDIO_COMM_START_BUSY;
312         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
313
314         for (i = 0; i < 50; i++) {
315                 udelay(10);
316
317                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
318                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
319                         udelay(5);
320
321                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
322                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
323
324                         break;
325                 }
326         }
327
328         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
329                 *val = 0x0;
330                 ret = -EBUSY;
331         }
332         else {
333                 *val = val1;
334                 ret = 0;
335         }
336
337         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
338                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
339                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
340
341                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
342                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
343
344                 udelay(40);
345         }
346
347         return ret;
348 }
349
350 static int
351 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
352 {
353         u32 val1;
354         int i, ret;
355
356         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
357                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
358                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
359
360                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
361                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
362
363                 udelay(40);
364         }
365
366         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
367                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
368                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
369         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
370
371         for (i = 0; i < 50; i++) {
372                 udelay(10);
373
374                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
375                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
376                         udelay(5);
377                         break;
378                 }
379         }
380
381         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
382                 ret = -EBUSY;
383         else
384                 ret = 0;
385
386         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
387                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
388                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
389
390                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
391                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
392
393                 udelay(40);
394         }
395
396         return ret;
397 }
398
399 static void
400 bnx2_disable_int(struct bnx2 *bp)
401 {
402         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
403                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
404         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
405 }
406
407 static void
408 bnx2_enable_int(struct bnx2 *bp)
409 {
410         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
411                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
412                BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
413
414         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
415                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
416
417         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
418 }
419
420 static void
421 bnx2_disable_int_sync(struct bnx2 *bp)
422 {
423         atomic_inc(&bp->intr_sem);
424         bnx2_disable_int(bp);
425         synchronize_irq(bp->pdev->irq);
426 }
427
428 static void
429 bnx2_netif_stop(struct bnx2 *bp)
430 {
431         bnx2_disable_int_sync(bp);
432         if (netif_running(bp->dev)) {
433                 napi_disable(&bp->napi);
434                 netif_tx_disable(bp->dev);
435                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
436         }
437 }
438
439 static void
440 bnx2_netif_start(struct bnx2 *bp)
441 {
442         if (atomic_dec_and_test(&bp->intr_sem)) {
443                 if (netif_running(bp->dev)) {
444                         netif_wake_queue(bp->dev);
445                         napi_enable(&bp->napi);
446                         bnx2_enable_int(bp);
447                 }
448         }
449 }
450
451 static void
452 bnx2_free_mem(struct bnx2 *bp)
453 {
454         int i;
455
456         for (i = 0; i < bp->ctx_pages; i++) {
457                 if (bp->ctx_blk[i]) {
458                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
459                                             bp->ctx_blk[i],
460                                             bp->ctx_blk_mapping[i]);
461                         bp->ctx_blk[i] = NULL;
462                 }
463         }
464         if (bp->status_blk) {
465                 pci_free_consistent(bp->pdev, bp->status_stats_size,
466                                     bp->status_blk, bp->status_blk_mapping);
467                 bp->status_blk = NULL;
468                 bp->stats_blk = NULL;
469         }
470         if (bp->tx_desc_ring) {
471                 pci_free_consistent(bp->pdev,
472                                     sizeof(struct tx_bd) * TX_DESC_CNT,
473                                     bp->tx_desc_ring, bp->tx_desc_mapping);
474                 bp->tx_desc_ring = NULL;
475         }
476         kfree(bp->tx_buf_ring);
477         bp->tx_buf_ring = NULL;
478         for (i = 0; i < bp->rx_max_ring; i++) {
479                 if (bp->rx_desc_ring[i])
480                         pci_free_consistent(bp->pdev,
481                                             sizeof(struct rx_bd) * RX_DESC_CNT,
482                                             bp->rx_desc_ring[i],
483                                             bp->rx_desc_mapping[i]);
484                 bp->rx_desc_ring[i] = NULL;
485         }
486         vfree(bp->rx_buf_ring);
487         bp->rx_buf_ring = NULL;
488 }
489
490 static int
491 bnx2_alloc_mem(struct bnx2 *bp)
492 {
493         int i, status_blk_size;
494
495         bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
496                                   GFP_KERNEL);
497         if (bp->tx_buf_ring == NULL)
498                 return -ENOMEM;
499
500         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
501                                                 sizeof(struct tx_bd) *
502                                                 TX_DESC_CNT,
503                                                 &bp->tx_desc_mapping);
504         if (bp->tx_desc_ring == NULL)
505                 goto alloc_mem_err;
506
507         bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
508                                   bp->rx_max_ring);
509         if (bp->rx_buf_ring == NULL)
510                 goto alloc_mem_err;
511
512         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
513                                    bp->rx_max_ring);
514
515         for (i = 0; i < bp->rx_max_ring; i++) {
516                 bp->rx_desc_ring[i] =
517                         pci_alloc_consistent(bp->pdev,
518                                              sizeof(struct rx_bd) * RX_DESC_CNT,
519                                              &bp->rx_desc_mapping[i]);
520                 if (bp->rx_desc_ring[i] == NULL)
521                         goto alloc_mem_err;
522
523         }
524
525         /* Combine status and statistics blocks into one allocation. */
526         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
527         bp->status_stats_size = status_blk_size +
528                                 sizeof(struct statistics_block);
529
530         bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
531                                               &bp->status_blk_mapping);
532         if (bp->status_blk == NULL)
533                 goto alloc_mem_err;
534
535         memset(bp->status_blk, 0, bp->status_stats_size);
536
537         bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
538                                   status_blk_size);
539
540         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
541
542         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
543                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
544                 if (bp->ctx_pages == 0)
545                         bp->ctx_pages = 1;
546                 for (i = 0; i < bp->ctx_pages; i++) {
547                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
548                                                 BCM_PAGE_SIZE,
549                                                 &bp->ctx_blk_mapping[i]);
550                         if (bp->ctx_blk[i] == NULL)
551                                 goto alloc_mem_err;
552                 }
553         }
554         return 0;
555
556 alloc_mem_err:
557         bnx2_free_mem(bp);
558         return -ENOMEM;
559 }
560
561 static void
562 bnx2_report_fw_link(struct bnx2 *bp)
563 {
564         u32 fw_link_status = 0;
565
566         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
567                 return;
568
569         if (bp->link_up) {
570                 u32 bmsr;
571
572                 switch (bp->line_speed) {
573                 case SPEED_10:
574                         if (bp->duplex == DUPLEX_HALF)
575                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
576                         else
577                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
578                         break;
579                 case SPEED_100:
580                         if (bp->duplex == DUPLEX_HALF)
581                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
582                         else
583                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
584                         break;
585                 case SPEED_1000:
586                         if (bp->duplex == DUPLEX_HALF)
587                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
588                         else
589                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
590                         break;
591                 case SPEED_2500:
592                         if (bp->duplex == DUPLEX_HALF)
593                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
594                         else
595                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
596                         break;
597                 }
598
599                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
600
601                 if (bp->autoneg) {
602                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
603
604                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
605                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
606
607                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
608                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
609                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
610                         else
611                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
612                 }
613         }
614         else
615                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
616
617         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
618 }
619
620 static char *
621 bnx2_xceiver_str(struct bnx2 *bp)
622 {
623         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
624                 ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" :
625                  "Copper"));
626 }
627
628 static void
629 bnx2_report_link(struct bnx2 *bp)
630 {
631         if (bp->link_up) {
632                 netif_carrier_on(bp->dev);
633                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
634                        bnx2_xceiver_str(bp));
635
636                 printk("%d Mbps ", bp->line_speed);
637
638                 if (bp->duplex == DUPLEX_FULL)
639                         printk("full duplex");
640                 else
641                         printk("half duplex");
642
643                 if (bp->flow_ctrl) {
644                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
645                                 printk(", receive ");
646                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
647                                         printk("& transmit ");
648                         }
649                         else {
650                                 printk(", transmit ");
651                         }
652                         printk("flow control ON");
653                 }
654                 printk("\n");
655         }
656         else {
657                 netif_carrier_off(bp->dev);
658                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
659                        bnx2_xceiver_str(bp));
660         }
661
662         bnx2_report_fw_link(bp);
663 }
664
665 static void
666 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
667 {
668         u32 local_adv, remote_adv;
669
670         bp->flow_ctrl = 0;
671         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
672                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
673
674                 if (bp->duplex == DUPLEX_FULL) {
675                         bp->flow_ctrl = bp->req_flow_ctrl;
676                 }
677                 return;
678         }
679
680         if (bp->duplex != DUPLEX_FULL) {
681                 return;
682         }
683
684         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
685             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
686                 u32 val;
687
688                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
689                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
690                         bp->flow_ctrl |= FLOW_CTRL_TX;
691                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
692                         bp->flow_ctrl |= FLOW_CTRL_RX;
693                 return;
694         }
695
696         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
697         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
698
699         if (bp->phy_flags & PHY_SERDES_FLAG) {
700                 u32 new_local_adv = 0;
701                 u32 new_remote_adv = 0;
702
703                 if (local_adv & ADVERTISE_1000XPAUSE)
704                         new_local_adv |= ADVERTISE_PAUSE_CAP;
705                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
706                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
707                 if (remote_adv & ADVERTISE_1000XPAUSE)
708                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
709                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
710                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
711
712                 local_adv = new_local_adv;
713                 remote_adv = new_remote_adv;
714         }
715
716         /* See Table 28B-3 of 802.3ab-1999 spec. */
717         if (local_adv & ADVERTISE_PAUSE_CAP) {
718                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
719                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
720                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
721                         }
722                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
723                                 bp->flow_ctrl = FLOW_CTRL_RX;
724                         }
725                 }
726                 else {
727                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
728                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
729                         }
730                 }
731         }
732         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
733                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
734                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
735
736                         bp->flow_ctrl = FLOW_CTRL_TX;
737                 }
738         }
739 }
740
741 static int
742 bnx2_5709s_linkup(struct bnx2 *bp)
743 {
744         u32 val, speed;
745
746         bp->link_up = 1;
747
748         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
749         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
750         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
751
752         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
753                 bp->line_speed = bp->req_line_speed;
754                 bp->duplex = bp->req_duplex;
755                 return 0;
756         }
757         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
758         switch (speed) {
759                 case MII_BNX2_GP_TOP_AN_SPEED_10:
760                         bp->line_speed = SPEED_10;
761                         break;
762                 case MII_BNX2_GP_TOP_AN_SPEED_100:
763                         bp->line_speed = SPEED_100;
764                         break;
765                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
766                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
767                         bp->line_speed = SPEED_1000;
768                         break;
769                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
770                         bp->line_speed = SPEED_2500;
771                         break;
772         }
773         if (val & MII_BNX2_GP_TOP_AN_FD)
774                 bp->duplex = DUPLEX_FULL;
775         else
776                 bp->duplex = DUPLEX_HALF;
777         return 0;
778 }
779
780 static int
781 bnx2_5708s_linkup(struct bnx2 *bp)
782 {
783         u32 val;
784
785         bp->link_up = 1;
786         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
787         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
788                 case BCM5708S_1000X_STAT1_SPEED_10:
789                         bp->line_speed = SPEED_10;
790                         break;
791                 case BCM5708S_1000X_STAT1_SPEED_100:
792                         bp->line_speed = SPEED_100;
793                         break;
794                 case BCM5708S_1000X_STAT1_SPEED_1G:
795                         bp->line_speed = SPEED_1000;
796                         break;
797                 case BCM5708S_1000X_STAT1_SPEED_2G5:
798                         bp->line_speed = SPEED_2500;
799                         break;
800         }
801         if (val & BCM5708S_1000X_STAT1_FD)
802                 bp->duplex = DUPLEX_FULL;
803         else
804                 bp->duplex = DUPLEX_HALF;
805
806         return 0;
807 }
808
809 static int
810 bnx2_5706s_linkup(struct bnx2 *bp)
811 {
812         u32 bmcr, local_adv, remote_adv, common;
813
814         bp->link_up = 1;
815         bp->line_speed = SPEED_1000;
816
817         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
818         if (bmcr & BMCR_FULLDPLX) {
819                 bp->duplex = DUPLEX_FULL;
820         }
821         else {
822                 bp->duplex = DUPLEX_HALF;
823         }
824
825         if (!(bmcr & BMCR_ANENABLE)) {
826                 return 0;
827         }
828
829         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
830         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
831
832         common = local_adv & remote_adv;
833         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
834
835                 if (common & ADVERTISE_1000XFULL) {
836                         bp->duplex = DUPLEX_FULL;
837                 }
838                 else {
839                         bp->duplex = DUPLEX_HALF;
840                 }
841         }
842
843         return 0;
844 }
845
846 static int
847 bnx2_copper_linkup(struct bnx2 *bp)
848 {
849         u32 bmcr;
850
851         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
852         if (bmcr & BMCR_ANENABLE) {
853                 u32 local_adv, remote_adv, common;
854
855                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
856                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
857
858                 common = local_adv & (remote_adv >> 2);
859                 if (common & ADVERTISE_1000FULL) {
860                         bp->line_speed = SPEED_1000;
861                         bp->duplex = DUPLEX_FULL;
862                 }
863                 else if (common & ADVERTISE_1000HALF) {
864                         bp->line_speed = SPEED_1000;
865                         bp->duplex = DUPLEX_HALF;
866                 }
867                 else {
868                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
869                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
870
871                         common = local_adv & remote_adv;
872                         if (common & ADVERTISE_100FULL) {
873                                 bp->line_speed = SPEED_100;
874                                 bp->duplex = DUPLEX_FULL;
875                         }
876                         else if (common & ADVERTISE_100HALF) {
877                                 bp->line_speed = SPEED_100;
878                                 bp->duplex = DUPLEX_HALF;
879                         }
880                         else if (common & ADVERTISE_10FULL) {
881                                 bp->line_speed = SPEED_10;
882                                 bp->duplex = DUPLEX_FULL;
883                         }
884                         else if (common & ADVERTISE_10HALF) {
885                                 bp->line_speed = SPEED_10;
886                                 bp->duplex = DUPLEX_HALF;
887                         }
888                         else {
889                                 bp->line_speed = 0;
890                                 bp->link_up = 0;
891                         }
892                 }
893         }
894         else {
895                 if (bmcr & BMCR_SPEED100) {
896                         bp->line_speed = SPEED_100;
897                 }
898                 else {
899                         bp->line_speed = SPEED_10;
900                 }
901                 if (bmcr & BMCR_FULLDPLX) {
902                         bp->duplex = DUPLEX_FULL;
903                 }
904                 else {
905                         bp->duplex = DUPLEX_HALF;
906                 }
907         }
908
909         return 0;
910 }
911
912 static int
913 bnx2_set_mac_link(struct bnx2 *bp)
914 {
915         u32 val;
916
917         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
918         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
919                 (bp->duplex == DUPLEX_HALF)) {
920                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
921         }
922
923         /* Configure the EMAC mode register. */
924         val = REG_RD(bp, BNX2_EMAC_MODE);
925
926         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
927                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
928                 BNX2_EMAC_MODE_25G_MODE);
929
930         if (bp->link_up) {
931                 switch (bp->line_speed) {
932                         case SPEED_10:
933                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
934                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
935                                         break;
936                                 }
937                                 /* fall through */
938                         case SPEED_100:
939                                 val |= BNX2_EMAC_MODE_PORT_MII;
940                                 break;
941                         case SPEED_2500:
942                                 val |= BNX2_EMAC_MODE_25G_MODE;
943                                 /* fall through */
944                         case SPEED_1000:
945                                 val |= BNX2_EMAC_MODE_PORT_GMII;
946                                 break;
947                 }
948         }
949         else {
950                 val |= BNX2_EMAC_MODE_PORT_GMII;
951         }
952
953         /* Set the MAC to operate in the appropriate duplex mode. */
954         if (bp->duplex == DUPLEX_HALF)
955                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
956         REG_WR(bp, BNX2_EMAC_MODE, val);
957
958         /* Enable/disable rx PAUSE. */
959         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
960
961         if (bp->flow_ctrl & FLOW_CTRL_RX)
962                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
963         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
964
965         /* Enable/disable tx PAUSE. */
966         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
967         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
968
969         if (bp->flow_ctrl & FLOW_CTRL_TX)
970                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
971         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
972
973         /* Acknowledge the interrupt. */
974         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
975
976         return 0;
977 }
978
979 static void
980 bnx2_enable_bmsr1(struct bnx2 *bp)
981 {
982         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
983             (CHIP_NUM(bp) == CHIP_NUM_5709))
984                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
985                                MII_BNX2_BLK_ADDR_GP_STATUS);
986 }
987
988 static void
989 bnx2_disable_bmsr1(struct bnx2 *bp)
990 {
991         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
992             (CHIP_NUM(bp) == CHIP_NUM_5709))
993                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
994                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
995 }
996
997 static int
998 bnx2_test_and_enable_2g5(struct bnx2 *bp)
999 {
1000         u32 up1;
1001         int ret = 1;
1002
1003         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1004                 return 0;
1005
1006         if (bp->autoneg & AUTONEG_SPEED)
1007                 bp->advertising |= ADVERTISED_2500baseX_Full;
1008
1009         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1010                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1011
1012         bnx2_read_phy(bp, bp->mii_up1, &up1);
1013         if (!(up1 & BCM5708S_UP1_2G5)) {
1014                 up1 |= BCM5708S_UP1_2G5;
1015                 bnx2_write_phy(bp, bp->mii_up1, up1);
1016                 ret = 0;
1017         }
1018
1019         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1020                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1021                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1022
1023         return ret;
1024 }
1025
1026 static int
1027 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1028 {
1029         u32 up1;
1030         int ret = 0;
1031
1032         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1033                 return 0;
1034
1035         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1036                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1037
1038         bnx2_read_phy(bp, bp->mii_up1, &up1);
1039         if (up1 & BCM5708S_UP1_2G5) {
1040                 up1 &= ~BCM5708S_UP1_2G5;
1041                 bnx2_write_phy(bp, bp->mii_up1, up1);
1042                 ret = 1;
1043         }
1044
1045         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1046                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1047                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1048
1049         return ret;
1050 }
1051
1052 static void
1053 bnx2_enable_forced_2g5(struct bnx2 *bp)
1054 {
1055         u32 bmcr;
1056
1057         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1058                 return;
1059
1060         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1061                 u32 val;
1062
1063                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1064                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1065                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1066                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1067                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1068                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1069
1070                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1071                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1072                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1073
1074         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1075                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1076                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1077         }
1078
1079         if (bp->autoneg & AUTONEG_SPEED) {
1080                 bmcr &= ~BMCR_ANENABLE;
1081                 if (bp->req_duplex == DUPLEX_FULL)
1082                         bmcr |= BMCR_FULLDPLX;
1083         }
1084         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1085 }
1086
1087 static void
1088 bnx2_disable_forced_2g5(struct bnx2 *bp)
1089 {
1090         u32 bmcr;
1091
1092         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1093                 return;
1094
1095         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1096                 u32 val;
1097
1098                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1099                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1100                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1101                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1102                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1103
1104                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1105                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1106                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1107
1108         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1109                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1110                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1111         }
1112
1113         if (bp->autoneg & AUTONEG_SPEED)
1114                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1115         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1116 }
1117
1118 static int
1119 bnx2_set_link(struct bnx2 *bp)
1120 {
1121         u32 bmsr;
1122         u8 link_up;
1123
1124         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1125                 bp->link_up = 1;
1126                 return 0;
1127         }
1128
1129         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1130                 return 0;
1131
1132         link_up = bp->link_up;
1133
1134         bnx2_enable_bmsr1(bp);
1135         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1136         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1137         bnx2_disable_bmsr1(bp);
1138
1139         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1140             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1141                 u32 val;
1142
1143                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1144                 if (val & BNX2_EMAC_STATUS_LINK)
1145                         bmsr |= BMSR_LSTATUS;
1146                 else
1147                         bmsr &= ~BMSR_LSTATUS;
1148         }
1149
1150         if (bmsr & BMSR_LSTATUS) {
1151                 bp->link_up = 1;
1152
1153                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1154                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1155                                 bnx2_5706s_linkup(bp);
1156                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1157                                 bnx2_5708s_linkup(bp);
1158                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1159                                 bnx2_5709s_linkup(bp);
1160                 }
1161                 else {
1162                         bnx2_copper_linkup(bp);
1163                 }
1164                 bnx2_resolve_flow_ctrl(bp);
1165         }
1166         else {
1167                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1168                     (bp->autoneg & AUTONEG_SPEED))
1169                         bnx2_disable_forced_2g5(bp);
1170
1171                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1172                 bp->link_up = 0;
1173         }
1174
1175         if (bp->link_up != link_up) {
1176                 bnx2_report_link(bp);
1177         }
1178
1179         bnx2_set_mac_link(bp);
1180
1181         return 0;
1182 }
1183
1184 static int
1185 bnx2_reset_phy(struct bnx2 *bp)
1186 {
1187         int i;
1188         u32 reg;
1189
1190         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1191
1192 #define PHY_RESET_MAX_WAIT 100
1193         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1194                 udelay(10);
1195
1196                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1197                 if (!(reg & BMCR_RESET)) {
1198                         udelay(20);
1199                         break;
1200                 }
1201         }
1202         if (i == PHY_RESET_MAX_WAIT) {
1203                 return -EBUSY;
1204         }
1205         return 0;
1206 }
1207
1208 static u32
1209 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1210 {
1211         u32 adv = 0;
1212
1213         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1214                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1215
1216                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1217                         adv = ADVERTISE_1000XPAUSE;
1218                 }
1219                 else {
1220                         adv = ADVERTISE_PAUSE_CAP;
1221                 }
1222         }
1223         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1224                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1225                         adv = ADVERTISE_1000XPSE_ASYM;
1226                 }
1227                 else {
1228                         adv = ADVERTISE_PAUSE_ASYM;
1229                 }
1230         }
1231         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1232                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1233                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1234                 }
1235                 else {
1236                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1237                 }
1238         }
1239         return adv;
1240 }
1241
1242 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1243
1244 static int
1245 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1246 {
1247         u32 speed_arg = 0, pause_adv;
1248
1249         pause_adv = bnx2_phy_get_pause_adv(bp);
1250
1251         if (bp->autoneg & AUTONEG_SPEED) {
1252                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1253                 if (bp->advertising & ADVERTISED_10baseT_Half)
1254                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1255                 if (bp->advertising & ADVERTISED_10baseT_Full)
1256                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1257                 if (bp->advertising & ADVERTISED_100baseT_Half)
1258                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1259                 if (bp->advertising & ADVERTISED_100baseT_Full)
1260                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1261                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1262                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1263                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1264                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1265         } else {
1266                 if (bp->req_line_speed == SPEED_2500)
1267                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1268                 else if (bp->req_line_speed == SPEED_1000)
1269                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1270                 else if (bp->req_line_speed == SPEED_100) {
1271                         if (bp->req_duplex == DUPLEX_FULL)
1272                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1273                         else
1274                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1275                 } else if (bp->req_line_speed == SPEED_10) {
1276                         if (bp->req_duplex == DUPLEX_FULL)
1277                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1278                         else
1279                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1280                 }
1281         }
1282
1283         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1284                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1285         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
1286                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1287
1288         if (port == PORT_TP)
1289                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1290                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1291
1292         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
1293
1294         spin_unlock_bh(&bp->phy_lock);
1295         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1296         spin_lock_bh(&bp->phy_lock);
1297
1298         return 0;
1299 }
1300
1301 static int
1302 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1303 {
1304         u32 adv, bmcr;
1305         u32 new_adv = 0;
1306
1307         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1308                 return (bnx2_setup_remote_phy(bp, port));
1309
1310         if (!(bp->autoneg & AUTONEG_SPEED)) {
1311                 u32 new_bmcr;
1312                 int force_link_down = 0;
1313
1314                 if (bp->req_line_speed == SPEED_2500) {
1315                         if (!bnx2_test_and_enable_2g5(bp))
1316                                 force_link_down = 1;
1317                 } else if (bp->req_line_speed == SPEED_1000) {
1318                         if (bnx2_test_and_disable_2g5(bp))
1319                                 force_link_down = 1;
1320                 }
1321                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1322                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1323
1324                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1325                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1326                 new_bmcr |= BMCR_SPEED1000;
1327
1328                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1329                         if (bp->req_line_speed == SPEED_2500)
1330                                 bnx2_enable_forced_2g5(bp);
1331                         else if (bp->req_line_speed == SPEED_1000) {
1332                                 bnx2_disable_forced_2g5(bp);
1333                                 new_bmcr &= ~0x2000;
1334                         }
1335
1336                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1337                         if (bp->req_line_speed == SPEED_2500)
1338                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1339                         else
1340                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1341                 }
1342
1343                 if (bp->req_duplex == DUPLEX_FULL) {
1344                         adv |= ADVERTISE_1000XFULL;
1345                         new_bmcr |= BMCR_FULLDPLX;
1346                 }
1347                 else {
1348                         adv |= ADVERTISE_1000XHALF;
1349                         new_bmcr &= ~BMCR_FULLDPLX;
1350                 }
1351                 if ((new_bmcr != bmcr) || (force_link_down)) {
1352                         /* Force a link down visible on the other side */
1353                         if (bp->link_up) {
1354                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1355                                                ~(ADVERTISE_1000XFULL |
1356                                                  ADVERTISE_1000XHALF));
1357                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1358                                         BMCR_ANRESTART | BMCR_ANENABLE);
1359
1360                                 bp->link_up = 0;
1361                                 netif_carrier_off(bp->dev);
1362                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1363                                 bnx2_report_link(bp);
1364                         }
1365                         bnx2_write_phy(bp, bp->mii_adv, adv);
1366                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1367                 } else {
1368                         bnx2_resolve_flow_ctrl(bp);
1369                         bnx2_set_mac_link(bp);
1370                 }
1371                 return 0;
1372         }
1373
1374         bnx2_test_and_enable_2g5(bp);
1375
1376         if (bp->advertising & ADVERTISED_1000baseT_Full)
1377                 new_adv |= ADVERTISE_1000XFULL;
1378
1379         new_adv |= bnx2_phy_get_pause_adv(bp);
1380
1381         bnx2_read_phy(bp, bp->mii_adv, &adv);
1382         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1383
1384         bp->serdes_an_pending = 0;
1385         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1386                 /* Force a link down visible on the other side */
1387                 if (bp->link_up) {
1388                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1389                         spin_unlock_bh(&bp->phy_lock);
1390                         msleep(20);
1391                         spin_lock_bh(&bp->phy_lock);
1392                 }
1393
1394                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1395                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1396                         BMCR_ANENABLE);
1397                 /* Speed up link-up time when the link partner
1398                  * does not autonegotiate which is very common
1399                  * in blade servers. Some blade servers use
1400                  * IPMI for kerboard input and it's important
1401                  * to minimize link disruptions. Autoneg. involves
1402                  * exchanging base pages plus 3 next pages and
1403                  * normally completes in about 120 msec.
1404                  */
1405                 bp->current_interval = SERDES_AN_TIMEOUT;
1406                 bp->serdes_an_pending = 1;
1407                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1408         } else {
1409                 bnx2_resolve_flow_ctrl(bp);
1410                 bnx2_set_mac_link(bp);
1411         }
1412
1413         return 0;
1414 }
1415
1416 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1417         (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ?                       \
1418                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1419                 (ADVERTISED_1000baseT_Full)
1420
1421 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1422         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1423         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1424         ADVERTISED_1000baseT_Full)
1425
1426 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1427         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1428
1429 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1430
1431 static void
1432 bnx2_set_default_remote_link(struct bnx2 *bp)
1433 {
1434         u32 link;
1435
1436         if (bp->phy_port == PORT_TP)
1437                 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
1438         else
1439                 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
1440
1441         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1442                 bp->req_line_speed = 0;
1443                 bp->autoneg |= AUTONEG_SPEED;
1444                 bp->advertising = ADVERTISED_Autoneg;
1445                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1446                         bp->advertising |= ADVERTISED_10baseT_Half;
1447                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1448                         bp->advertising |= ADVERTISED_10baseT_Full;
1449                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1450                         bp->advertising |= ADVERTISED_100baseT_Half;
1451                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1452                         bp->advertising |= ADVERTISED_100baseT_Full;
1453                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1454                         bp->advertising |= ADVERTISED_1000baseT_Full;
1455                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1456                         bp->advertising |= ADVERTISED_2500baseX_Full;
1457         } else {
1458                 bp->autoneg = 0;
1459                 bp->advertising = 0;
1460                 bp->req_duplex = DUPLEX_FULL;
1461                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1462                         bp->req_line_speed = SPEED_10;
1463                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1464                                 bp->req_duplex = DUPLEX_HALF;
1465                 }
1466                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1467                         bp->req_line_speed = SPEED_100;
1468                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1469                                 bp->req_duplex = DUPLEX_HALF;
1470                 }
1471                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1472                         bp->req_line_speed = SPEED_1000;
1473                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1474                         bp->req_line_speed = SPEED_2500;
1475         }
1476 }
1477
1478 static void
1479 bnx2_set_default_link(struct bnx2 *bp)
1480 {
1481         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1482                 return bnx2_set_default_remote_link(bp);
1483
1484         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1485         bp->req_line_speed = 0;
1486         if (bp->phy_flags & PHY_SERDES_FLAG) {
1487                 u32 reg;
1488
1489                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1490
1491                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
1492                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1493                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1494                         bp->autoneg = 0;
1495                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1496                         bp->req_duplex = DUPLEX_FULL;
1497                 }
1498         } else
1499                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1500 }
1501
1502 static void
1503 bnx2_send_heart_beat(struct bnx2 *bp)
1504 {
1505         u32 msg;
1506         u32 addr;
1507
1508         spin_lock(&bp->indirect_lock);
1509         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1510         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1511         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1512         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1513         spin_unlock(&bp->indirect_lock);
1514 }
1515
1516 static void
1517 bnx2_remote_phy_event(struct bnx2 *bp)
1518 {
1519         u32 msg;
1520         u8 link_up = bp->link_up;
1521         u8 old_port;
1522
1523         msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1524
1525         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1526                 bnx2_send_heart_beat(bp);
1527
1528         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1529
1530         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1531                 bp->link_up = 0;
1532         else {
1533                 u32 speed;
1534
1535                 bp->link_up = 1;
1536                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1537                 bp->duplex = DUPLEX_FULL;
1538                 switch (speed) {
1539                         case BNX2_LINK_STATUS_10HALF:
1540                                 bp->duplex = DUPLEX_HALF;
1541                         case BNX2_LINK_STATUS_10FULL:
1542                                 bp->line_speed = SPEED_10;
1543                                 break;
1544                         case BNX2_LINK_STATUS_100HALF:
1545                                 bp->duplex = DUPLEX_HALF;
1546                         case BNX2_LINK_STATUS_100BASE_T4:
1547                         case BNX2_LINK_STATUS_100FULL:
1548                                 bp->line_speed = SPEED_100;
1549                                 break;
1550                         case BNX2_LINK_STATUS_1000HALF:
1551                                 bp->duplex = DUPLEX_HALF;
1552                         case BNX2_LINK_STATUS_1000FULL:
1553                                 bp->line_speed = SPEED_1000;
1554                                 break;
1555                         case BNX2_LINK_STATUS_2500HALF:
1556                                 bp->duplex = DUPLEX_HALF;
1557                         case BNX2_LINK_STATUS_2500FULL:
1558                                 bp->line_speed = SPEED_2500;
1559                                 break;
1560                         default:
1561                                 bp->line_speed = 0;
1562                                 break;
1563                 }
1564
1565                 spin_lock(&bp->phy_lock);
1566                 bp->flow_ctrl = 0;
1567                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1568                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1569                         if (bp->duplex == DUPLEX_FULL)
1570                                 bp->flow_ctrl = bp->req_flow_ctrl;
1571                 } else {
1572                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1573                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1574                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1575                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1576                 }
1577
1578                 old_port = bp->phy_port;
1579                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1580                         bp->phy_port = PORT_FIBRE;
1581                 else
1582                         bp->phy_port = PORT_TP;
1583
1584                 if (old_port != bp->phy_port)
1585                         bnx2_set_default_link(bp);
1586
1587                 spin_unlock(&bp->phy_lock);
1588         }
1589         if (bp->link_up != link_up)
1590                 bnx2_report_link(bp);
1591
1592         bnx2_set_mac_link(bp);
1593 }
1594
1595 static int
1596 bnx2_set_remote_link(struct bnx2 *bp)
1597 {
1598         u32 evt_code;
1599
1600         evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
1601         switch (evt_code) {
1602                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1603                         bnx2_remote_phy_event(bp);
1604                         break;
1605                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1606                 default:
1607                         bnx2_send_heart_beat(bp);
1608                         break;
1609         }
1610         return 0;
1611 }
1612
1613 static int
1614 bnx2_setup_copper_phy(struct bnx2 *bp)
1615 {
1616         u32 bmcr;
1617         u32 new_bmcr;
1618
1619         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1620
1621         if (bp->autoneg & AUTONEG_SPEED) {
1622                 u32 adv_reg, adv1000_reg;
1623                 u32 new_adv_reg = 0;
1624                 u32 new_adv1000_reg = 0;
1625
1626                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1627                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1628                         ADVERTISE_PAUSE_ASYM);
1629
1630                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1631                 adv1000_reg &= PHY_ALL_1000_SPEED;
1632
1633                 if (bp->advertising & ADVERTISED_10baseT_Half)
1634                         new_adv_reg |= ADVERTISE_10HALF;
1635                 if (bp->advertising & ADVERTISED_10baseT_Full)
1636                         new_adv_reg |= ADVERTISE_10FULL;
1637                 if (bp->advertising & ADVERTISED_100baseT_Half)
1638                         new_adv_reg |= ADVERTISE_100HALF;
1639                 if (bp->advertising & ADVERTISED_100baseT_Full)
1640                         new_adv_reg |= ADVERTISE_100FULL;
1641                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1642                         new_adv1000_reg |= ADVERTISE_1000FULL;
1643
1644                 new_adv_reg |= ADVERTISE_CSMA;
1645
1646                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1647
1648                 if ((adv1000_reg != new_adv1000_reg) ||
1649                         (adv_reg != new_adv_reg) ||
1650                         ((bmcr & BMCR_ANENABLE) == 0)) {
1651
1652                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1653                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1654                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1655                                 BMCR_ANENABLE);
1656                 }
1657                 else if (bp->link_up) {
1658                         /* Flow ctrl may have changed from auto to forced */
1659                         /* or vice-versa. */
1660
1661                         bnx2_resolve_flow_ctrl(bp);
1662                         bnx2_set_mac_link(bp);
1663                 }
1664                 return 0;
1665         }
1666
1667         new_bmcr = 0;
1668         if (bp->req_line_speed == SPEED_100) {
1669                 new_bmcr |= BMCR_SPEED100;
1670         }
1671         if (bp->req_duplex == DUPLEX_FULL) {
1672                 new_bmcr |= BMCR_FULLDPLX;
1673         }
1674         if (new_bmcr != bmcr) {
1675                 u32 bmsr;
1676
1677                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1678                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1679
1680                 if (bmsr & BMSR_LSTATUS) {
1681                         /* Force link down */
1682                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1683                         spin_unlock_bh(&bp->phy_lock);
1684                         msleep(50);
1685                         spin_lock_bh(&bp->phy_lock);
1686
1687                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1688                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1689                 }
1690
1691                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1692
1693                 /* Normally, the new speed is setup after the link has
1694                  * gone down and up again. In some cases, link will not go
1695                  * down so we need to set up the new speed here.
1696                  */
1697                 if (bmsr & BMSR_LSTATUS) {
1698                         bp->line_speed = bp->req_line_speed;
1699                         bp->duplex = bp->req_duplex;
1700                         bnx2_resolve_flow_ctrl(bp);
1701                         bnx2_set_mac_link(bp);
1702                 }
1703         } else {
1704                 bnx2_resolve_flow_ctrl(bp);
1705                 bnx2_set_mac_link(bp);
1706         }
1707         return 0;
1708 }
1709
1710 static int
1711 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1712 {
1713         if (bp->loopback == MAC_LOOPBACK)
1714                 return 0;
1715
1716         if (bp->phy_flags & PHY_SERDES_FLAG) {
1717                 return (bnx2_setup_serdes_phy(bp, port));
1718         }
1719         else {
1720                 return (bnx2_setup_copper_phy(bp));
1721         }
1722 }
1723
1724 static int
1725 bnx2_init_5709s_phy(struct bnx2 *bp)
1726 {
1727         u32 val;
1728
1729         bp->mii_bmcr = MII_BMCR + 0x10;
1730         bp->mii_bmsr = MII_BMSR + 0x10;
1731         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1732         bp->mii_adv = MII_ADVERTISE + 0x10;
1733         bp->mii_lpa = MII_LPA + 0x10;
1734         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1735
1736         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1737         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1738
1739         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1740         bnx2_reset_phy(bp);
1741
1742         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1743
1744         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1745         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1746         val |= MII_BNX2_SD_1000XCTL1_FIBER;
1747         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1748
1749         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1750         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1751         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1752                 val |= BCM5708S_UP1_2G5;
1753         else
1754                 val &= ~BCM5708S_UP1_2G5;
1755         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1756
1757         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1758         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1759         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1760         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1761
1762         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1763
1764         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1765               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1766         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1767
1768         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1769
1770         return 0;
1771 }
1772
1773 static int
1774 bnx2_init_5708s_phy(struct bnx2 *bp)
1775 {
1776         u32 val;
1777
1778         bnx2_reset_phy(bp);
1779
1780         bp->mii_up1 = BCM5708S_UP1;
1781
1782         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1783         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1784         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1785
1786         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1787         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1788         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1789
1790         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1791         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1792         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1793
1794         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1795                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1796                 val |= BCM5708S_UP1_2G5;
1797                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1798         }
1799
1800         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1801             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1802             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1803                 /* increase tx signal amplitude */
1804                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1805                                BCM5708S_BLK_ADDR_TX_MISC);
1806                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1807                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1808                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1809                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1810         }
1811
1812         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1813               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1814
1815         if (val) {
1816                 u32 is_backplane;
1817
1818                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1819                                           BNX2_SHARED_HW_CFG_CONFIG);
1820                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1821                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1822                                        BCM5708S_BLK_ADDR_TX_MISC);
1823                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1824                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1825                                        BCM5708S_BLK_ADDR_DIG);
1826                 }
1827         }
1828         return 0;
1829 }
1830
1831 static int
1832 bnx2_init_5706s_phy(struct bnx2 *bp)
1833 {
1834         bnx2_reset_phy(bp);
1835
1836         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1837
1838         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1839                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1840
1841         if (bp->dev->mtu > 1500) {
1842                 u32 val;
1843
1844                 /* Set extended packet length bit */
1845                 bnx2_write_phy(bp, 0x18, 0x7);
1846                 bnx2_read_phy(bp, 0x18, &val);
1847                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1848
1849                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1850                 bnx2_read_phy(bp, 0x1c, &val);
1851                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1852         }
1853         else {
1854                 u32 val;
1855
1856                 bnx2_write_phy(bp, 0x18, 0x7);
1857                 bnx2_read_phy(bp, 0x18, &val);
1858                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1859
1860                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1861                 bnx2_read_phy(bp, 0x1c, &val);
1862                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1863         }
1864
1865         return 0;
1866 }
1867
1868 static int
1869 bnx2_init_copper_phy(struct bnx2 *bp)
1870 {
1871         u32 val;
1872
1873         bnx2_reset_phy(bp);
1874
1875         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1876                 bnx2_write_phy(bp, 0x18, 0x0c00);
1877                 bnx2_write_phy(bp, 0x17, 0x000a);
1878                 bnx2_write_phy(bp, 0x15, 0x310b);
1879                 bnx2_write_phy(bp, 0x17, 0x201f);
1880                 bnx2_write_phy(bp, 0x15, 0x9506);
1881                 bnx2_write_phy(bp, 0x17, 0x401f);
1882                 bnx2_write_phy(bp, 0x15, 0x14e2);
1883                 bnx2_write_phy(bp, 0x18, 0x0400);
1884         }
1885
1886         if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1887                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1888                                MII_BNX2_DSP_EXPAND_REG | 0x8);
1889                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1890                 val &= ~(1 << 8);
1891                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1892         }
1893
1894         if (bp->dev->mtu > 1500) {
1895                 /* Set extended packet length bit */
1896                 bnx2_write_phy(bp, 0x18, 0x7);
1897                 bnx2_read_phy(bp, 0x18, &val);
1898                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1899
1900                 bnx2_read_phy(bp, 0x10, &val);
1901                 bnx2_write_phy(bp, 0x10, val | 0x1);
1902         }
1903         else {
1904                 bnx2_write_phy(bp, 0x18, 0x7);
1905                 bnx2_read_phy(bp, 0x18, &val);
1906                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1907
1908                 bnx2_read_phy(bp, 0x10, &val);
1909                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1910         }
1911
1912         /* ethernet@wirespeed */
1913         bnx2_write_phy(bp, 0x18, 0x7007);
1914         bnx2_read_phy(bp, 0x18, &val);
1915         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1916         return 0;
1917 }
1918
1919
1920 static int
1921 bnx2_init_phy(struct bnx2 *bp)
1922 {
1923         u32 val;
1924         int rc = 0;
1925
1926         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1927         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1928
1929         bp->mii_bmcr = MII_BMCR;
1930         bp->mii_bmsr = MII_BMSR;
1931         bp->mii_bmsr1 = MII_BMSR;
1932         bp->mii_adv = MII_ADVERTISE;
1933         bp->mii_lpa = MII_LPA;
1934
1935         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1936
1937         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1938                 goto setup_phy;
1939
1940         bnx2_read_phy(bp, MII_PHYSID1, &val);
1941         bp->phy_id = val << 16;
1942         bnx2_read_phy(bp, MII_PHYSID2, &val);
1943         bp->phy_id |= val & 0xffff;
1944
1945         if (bp->phy_flags & PHY_SERDES_FLAG) {
1946                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1947                         rc = bnx2_init_5706s_phy(bp);
1948                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1949                         rc = bnx2_init_5708s_phy(bp);
1950                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1951                         rc = bnx2_init_5709s_phy(bp);
1952         }
1953         else {
1954                 rc = bnx2_init_copper_phy(bp);
1955         }
1956
1957 setup_phy:
1958         if (!rc)
1959                 rc = bnx2_setup_phy(bp, bp->phy_port);
1960
1961         return rc;
1962 }
1963
1964 static int
1965 bnx2_set_mac_loopback(struct bnx2 *bp)
1966 {
1967         u32 mac_mode;
1968
1969         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1970         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1971         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1972         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1973         bp->link_up = 1;
1974         return 0;
1975 }
1976
1977 static int bnx2_test_link(struct bnx2 *);
1978
1979 static int
1980 bnx2_set_phy_loopback(struct bnx2 *bp)
1981 {
1982         u32 mac_mode;
1983         int rc, i;
1984
1985         spin_lock_bh(&bp->phy_lock);
1986         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
1987                             BMCR_SPEED1000);
1988         spin_unlock_bh(&bp->phy_lock);
1989         if (rc)
1990                 return rc;
1991
1992         for (i = 0; i < 10; i++) {
1993                 if (bnx2_test_link(bp) == 0)
1994                         break;
1995                 msleep(100);
1996         }
1997
1998         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1999         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2000                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2001                       BNX2_EMAC_MODE_25G_MODE);
2002
2003         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2004         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2005         bp->link_up = 1;
2006         return 0;
2007 }
2008
2009 static int
2010 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2011 {
2012         int i;
2013         u32 val;
2014
2015         bp->fw_wr_seq++;
2016         msg_data |= bp->fw_wr_seq;
2017
2018         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2019
2020         /* wait for an acknowledgement. */
2021         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2022                 msleep(10);
2023
2024                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
2025
2026                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2027                         break;
2028         }
2029         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2030                 return 0;
2031
2032         /* If we timed out, inform the firmware that this is the case. */
2033         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2034                 if (!silent)
2035                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2036                                             "%x\n", msg_data);
2037
2038                 msg_data &= ~BNX2_DRV_MSG_CODE;
2039                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2040
2041                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2042
2043                 return -EBUSY;
2044         }
2045
2046         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2047                 return -EIO;
2048
2049         return 0;
2050 }
2051
2052 static int
2053 bnx2_init_5709_context(struct bnx2 *bp)
2054 {
2055         int i, ret = 0;
2056         u32 val;
2057
2058         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2059         val |= (BCM_PAGE_BITS - 8) << 16;
2060         REG_WR(bp, BNX2_CTX_COMMAND, val);
2061         for (i = 0; i < 10; i++) {
2062                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2063                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2064                         break;
2065                 udelay(2);
2066         }
2067         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2068                 return -EBUSY;
2069
2070         for (i = 0; i < bp->ctx_pages; i++) {
2071                 int j;
2072
2073                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2074                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2075                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2076                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2077                        (u64) bp->ctx_blk_mapping[i] >> 32);
2078                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2079                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2080                 for (j = 0; j < 10; j++) {
2081
2082                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2083                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2084                                 break;
2085                         udelay(5);
2086                 }
2087                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2088                         ret = -EBUSY;
2089                         break;
2090                 }
2091         }
2092         return ret;
2093 }
2094
2095 static void
2096 bnx2_init_context(struct bnx2 *bp)
2097 {
2098         u32 vcid;
2099
2100         vcid = 96;
2101         while (vcid) {
2102                 u32 vcid_addr, pcid_addr, offset;
2103                 int i;
2104
2105                 vcid--;
2106
2107                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2108                         u32 new_vcid;
2109
2110                         vcid_addr = GET_PCID_ADDR(vcid);
2111                         if (vcid & 0x8) {
2112                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2113                         }
2114                         else {
2115                                 new_vcid = vcid;
2116                         }
2117                         pcid_addr = GET_PCID_ADDR(new_vcid);
2118                 }
2119                 else {
2120                         vcid_addr = GET_CID_ADDR(vcid);
2121                         pcid_addr = vcid_addr;
2122                 }
2123
2124                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2125                         vcid_addr += (i << PHY_CTX_SHIFT);
2126                         pcid_addr += (i << PHY_CTX_SHIFT);
2127
2128                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
2129                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2130
2131                         /* Zero out the context. */
2132                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2133                                 CTX_WR(bp, 0x00, offset, 0);
2134
2135                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2136                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2137                 }
2138         }
2139 }
2140
2141 static int
2142 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2143 {
2144         u16 *good_mbuf;
2145         u32 good_mbuf_cnt;
2146         u32 val;
2147
2148         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2149         if (good_mbuf == NULL) {
2150                 printk(KERN_ERR PFX "Failed to allocate memory in "
2151                                     "bnx2_alloc_bad_rbuf\n");
2152                 return -ENOMEM;
2153         }
2154
2155         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2156                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2157
2158         good_mbuf_cnt = 0;
2159
2160         /* Allocate a bunch of mbufs and save the good ones in an array. */
2161         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2162         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2163                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
2164
2165                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
2166
2167                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2168
2169                 /* The addresses with Bit 9 set are bad memory blocks. */
2170                 if (!(val & (1 << 9))) {
2171                         good_mbuf[good_mbuf_cnt] = (u16) val;
2172                         good_mbuf_cnt++;
2173                 }
2174
2175                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2176         }
2177
2178         /* Free the good ones back to the mbuf pool thus discarding
2179          * all the bad ones. */
2180         while (good_mbuf_cnt) {
2181                 good_mbuf_cnt--;
2182
2183                 val = good_mbuf[good_mbuf_cnt];
2184                 val = (val << 9) | val | 1;
2185
2186                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
2187         }
2188         kfree(good_mbuf);
2189         return 0;
2190 }
2191
2192 static void
2193 bnx2_set_mac_addr(struct bnx2 *bp)
2194 {
2195         u32 val;
2196         u8 *mac_addr = bp->dev->dev_addr;
2197
2198         val = (mac_addr[0] << 8) | mac_addr[1];
2199
2200         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2201
2202         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2203                 (mac_addr[4] << 8) | mac_addr[5];
2204
2205         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2206 }
2207
2208 static inline int
2209 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
2210 {
2211         struct sk_buff *skb;
2212         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2213         dma_addr_t mapping;
2214         struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2215         unsigned long align;
2216
2217         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2218         if (skb == NULL) {
2219                 return -ENOMEM;
2220         }
2221
2222         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2223                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2224
2225         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2226                 PCI_DMA_FROMDEVICE);
2227
2228         rx_buf->skb = skb;
2229         pci_unmap_addr_set(rx_buf, mapping, mapping);
2230
2231         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2232         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2233
2234         bp->rx_prod_bseq += bp->rx_buf_use_size;
2235
2236         return 0;
2237 }
2238
2239 static int
2240 bnx2_phy_event_is_set(struct bnx2 *bp, u32 event)
2241 {
2242         struct status_block *sblk = bp->status_blk;
2243         u32 new_link_state, old_link_state;
2244         int is_set = 1;
2245
2246         new_link_state = sblk->status_attn_bits & event;
2247         old_link_state = sblk->status_attn_bits_ack & event;
2248         if (new_link_state != old_link_state) {
2249                 if (new_link_state)
2250                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2251                 else
2252                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2253         } else
2254                 is_set = 0;
2255
2256         return is_set;
2257 }
2258
2259 static void
2260 bnx2_phy_int(struct bnx2 *bp)
2261 {
2262         if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) {
2263                 spin_lock(&bp->phy_lock);
2264                 bnx2_set_link(bp);
2265                 spin_unlock(&bp->phy_lock);
2266         }
2267         if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_TIMER_ABORT))
2268                 bnx2_set_remote_link(bp);
2269
2270 }
2271
2272 static void
2273 bnx2_tx_int(struct bnx2 *bp)
2274 {
2275         struct status_block *sblk = bp->status_blk;
2276         u16 hw_cons, sw_cons, sw_ring_cons;
2277         int tx_free_bd = 0;
2278
2279         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
2280         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2281                 hw_cons++;
2282         }
2283         sw_cons = bp->tx_cons;
2284
2285         while (sw_cons != hw_cons) {
2286                 struct sw_bd *tx_buf;
2287                 struct sk_buff *skb;
2288                 int i, last;
2289
2290                 sw_ring_cons = TX_RING_IDX(sw_cons);
2291
2292                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2293                 skb = tx_buf->skb;
2294
2295                 /* partial BD completions possible with TSO packets */
2296                 if (skb_is_gso(skb)) {
2297                         u16 last_idx, last_ring_idx;
2298
2299                         last_idx = sw_cons +
2300                                 skb_shinfo(skb)->nr_frags + 1;
2301                         last_ring_idx = sw_ring_cons +
2302                                 skb_shinfo(skb)->nr_frags + 1;
2303                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2304                                 last_idx++;
2305                         }
2306                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2307                                 break;
2308                         }
2309                 }
2310
2311                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2312                         skb_headlen(skb), PCI_DMA_TODEVICE);
2313
2314                 tx_buf->skb = NULL;
2315                 last = skb_shinfo(skb)->nr_frags;
2316
2317                 for (i = 0; i < last; i++) {
2318                         sw_cons = NEXT_TX_BD(sw_cons);
2319
2320                         pci_unmap_page(bp->pdev,
2321                                 pci_unmap_addr(
2322                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2323                                         mapping),
2324                                 skb_shinfo(skb)->frags[i].size,
2325                                 PCI_DMA_TODEVICE);
2326                 }
2327
2328                 sw_cons = NEXT_TX_BD(sw_cons);
2329
2330                 tx_free_bd += last + 1;
2331
2332                 dev_kfree_skb(skb);
2333
2334                 hw_cons = bp->hw_tx_cons =
2335                         sblk->status_tx_quick_consumer_index0;
2336
2337                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2338                         hw_cons++;
2339                 }
2340         }
2341
2342         bp->tx_cons = sw_cons;
2343         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2344          * before checking for netif_queue_stopped().  Without the
2345          * memory barrier, there is a small possibility that bnx2_start_xmit()
2346          * will miss it and cause the queue to be stopped forever.
2347          */
2348         smp_mb();
2349
2350         if (unlikely(netif_queue_stopped(bp->dev)) &&
2351                      (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
2352                 netif_tx_lock(bp->dev);
2353                 if ((netif_queue_stopped(bp->dev)) &&
2354                     (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
2355                         netif_wake_queue(bp->dev);
2356                 netif_tx_unlock(bp->dev);
2357         }
2358 }
2359
2360 static inline void
2361 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
2362         u16 cons, u16 prod)
2363 {
2364         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2365         struct rx_bd *cons_bd, *prod_bd;
2366
2367         cons_rx_buf = &bp->rx_buf_ring[cons];
2368         prod_rx_buf = &bp->rx_buf_ring[prod];
2369
2370         pci_dma_sync_single_for_device(bp->pdev,
2371                 pci_unmap_addr(cons_rx_buf, mapping),
2372                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2373
2374         bp->rx_prod_bseq += bp->rx_buf_use_size;
2375
2376         prod_rx_buf->skb = skb;
2377
2378         if (cons == prod)
2379                 return;
2380
2381         pci_unmap_addr_set(prod_rx_buf, mapping,
2382                         pci_unmap_addr(cons_rx_buf, mapping));
2383
2384         cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2385         prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2386         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2387         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2388 }
2389
2390 static int
2391 bnx2_rx_int(struct bnx2 *bp, int budget)
2392 {
2393         struct status_block *sblk = bp->status_blk;
2394         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2395         struct l2_fhdr *rx_hdr;
2396         int rx_pkt = 0;
2397
2398         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
2399         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2400                 hw_cons++;
2401         }
2402         sw_cons = bp->rx_cons;
2403         sw_prod = bp->rx_prod;
2404
2405         /* Memory barrier necessary as speculative reads of the rx
2406          * buffer can be ahead of the index in the status block
2407          */
2408         rmb();
2409         while (sw_cons != hw_cons) {
2410                 unsigned int len;
2411                 u32 status;
2412                 struct sw_bd *rx_buf;
2413                 struct sk_buff *skb;
2414                 dma_addr_t dma_addr;
2415
2416                 sw_ring_cons = RX_RING_IDX(sw_cons);
2417                 sw_ring_prod = RX_RING_IDX(sw_prod);
2418
2419                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2420                 skb = rx_buf->skb;
2421
2422                 rx_buf->skb = NULL;
2423
2424                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2425
2426                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2427                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2428
2429                 rx_hdr = (struct l2_fhdr *) skb->data;
2430                 len = rx_hdr->l2_fhdr_pkt_len - 4;
2431
2432                 if ((status = rx_hdr->l2_fhdr_status) &
2433                         (L2_FHDR_ERRORS_BAD_CRC |
2434                         L2_FHDR_ERRORS_PHY_DECODE |
2435                         L2_FHDR_ERRORS_ALIGNMENT |
2436                         L2_FHDR_ERRORS_TOO_SHORT |
2437                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2438
2439                         goto reuse_rx;
2440                 }
2441
2442                 /* Since we don't have a jumbo ring, copy small packets
2443                  * if mtu > 1500
2444                  */
2445                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
2446                         struct sk_buff *new_skb;
2447
2448                         new_skb = netdev_alloc_skb(bp->dev, len + 2);
2449                         if (new_skb == NULL)
2450                                 goto reuse_rx;
2451
2452                         /* aligned copy */
2453                         skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2454                                       new_skb->data, len + 2);
2455                         skb_reserve(new_skb, 2);
2456                         skb_put(new_skb, len);
2457
2458                         bnx2_reuse_rx_skb(bp, skb,
2459                                 sw_ring_cons, sw_ring_prod);
2460
2461                         skb = new_skb;
2462                 }
2463                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
2464                         pci_unmap_single(bp->pdev, dma_addr,
2465                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
2466
2467                         skb_reserve(skb, bp->rx_offset);
2468                         skb_put(skb, len);
2469                 }
2470                 else {
2471 reuse_rx:
2472                         bnx2_reuse_rx_skb(bp, skb,
2473                                 sw_ring_cons, sw_ring_prod);
2474                         goto next_rx;
2475                 }
2476
2477                 skb->protocol = eth_type_trans(skb, bp->dev);
2478
2479                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2480                         (ntohs(skb->protocol) != 0x8100)) {
2481
2482                         dev_kfree_skb(skb);
2483                         goto next_rx;
2484
2485                 }
2486
2487                 skb->ip_summed = CHECKSUM_NONE;
2488                 if (bp->rx_csum &&
2489                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2490                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2491
2492                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2493                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2494                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2495                 }
2496
2497 #ifdef BCM_VLAN
2498                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
2499                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2500                                 rx_hdr->l2_fhdr_vlan_tag);
2501                 }
2502                 else
2503 #endif
2504                         netif_receive_skb(skb);
2505
2506                 bp->dev->last_rx = jiffies;
2507                 rx_pkt++;
2508
2509 next_rx:
2510                 sw_cons = NEXT_RX_BD(sw_cons);
2511                 sw_prod = NEXT_RX_BD(sw_prod);
2512
2513                 if ((rx_pkt == budget))
2514                         break;
2515
2516                 /* Refresh hw_cons to see if there is new work */
2517                 if (sw_cons == hw_cons) {
2518                         hw_cons = bp->hw_rx_cons =
2519                                 sblk->status_rx_quick_consumer_index0;
2520                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
2521                                 hw_cons++;
2522                         rmb();
2523                 }
2524         }
2525         bp->rx_cons = sw_cons;
2526         bp->rx_prod = sw_prod;
2527
2528         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2529
2530         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2531
2532         mmiowb();
2533
2534         return rx_pkt;
2535
2536 }
2537
2538 /* MSI ISR - The only difference between this and the INTx ISR
2539  * is that the MSI interrupt is always serviced.
2540  */
2541 static irqreturn_t
2542 bnx2_msi(int irq, void *dev_instance)
2543 {
2544         struct net_device *dev = dev_instance;
2545         struct bnx2 *bp = netdev_priv(dev);
2546
2547         prefetch(bp->status_blk);
2548         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2549                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2550                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2551
2552         /* Return here if interrupt is disabled. */
2553         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2554                 return IRQ_HANDLED;
2555
2556         netif_rx_schedule(dev, &bp->napi);
2557
2558         return IRQ_HANDLED;
2559 }
2560
2561 static irqreturn_t
2562 bnx2_msi_1shot(int irq, void *dev_instance)
2563 {
2564         struct net_device *dev = dev_instance;
2565         struct bnx2 *bp = netdev_priv(dev);
2566
2567         prefetch(bp->status_blk);
2568
2569         /* Return here if interrupt is disabled. */
2570         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2571                 return IRQ_HANDLED;
2572
2573         netif_rx_schedule(dev, &bp->napi);
2574
2575         return IRQ_HANDLED;
2576 }
2577
2578 static irqreturn_t
2579 bnx2_interrupt(int irq, void *dev_instance)
2580 {
2581         struct net_device *dev = dev_instance;
2582         struct bnx2 *bp = netdev_priv(dev);
2583         struct status_block *sblk = bp->status_blk;
2584
2585         /* When using INTx, it is possible for the interrupt to arrive
2586          * at the CPU before the status block posted prior to the
2587          * interrupt. Reading a register will flush the status block.
2588          * When using MSI, the MSI message will always complete after
2589          * the status block write.
2590          */
2591         if ((sblk->status_idx == bp->last_status_idx) &&
2592             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2593              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2594                 return IRQ_NONE;
2595
2596         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2597                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2598                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2599
2600         /* Read back to deassert IRQ immediately to avoid too many
2601          * spurious interrupts.
2602          */
2603         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2604
2605         /* Return here if interrupt is shared and is disabled. */
2606         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2607                 return IRQ_HANDLED;
2608
2609         if (netif_rx_schedule_prep(dev, &bp->napi)) {
2610                 bp->last_status_idx = sblk->status_idx;
2611                 __netif_rx_schedule(dev, &bp->napi);
2612         }
2613
2614         return IRQ_HANDLED;
2615 }
2616
2617 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
2618                                  STATUS_ATTN_BITS_TIMER_ABORT)
2619
2620 static inline int
2621 bnx2_has_work(struct bnx2 *bp)
2622 {
2623         struct status_block *sblk = bp->status_blk;
2624
2625         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
2626             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
2627                 return 1;
2628
2629         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2630             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2631                 return 1;
2632
2633         return 0;
2634 }
2635
2636 static int bnx2_poll_work(struct bnx2 *bp, int work_done, int budget)
2637 {
2638         struct status_block *sblk = bp->status_blk;
2639         u32 status_attn_bits = sblk->status_attn_bits;
2640         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2641
2642         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2643             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2644
2645                 bnx2_phy_int(bp);
2646
2647                 /* This is needed to take care of transient status
2648                  * during link changes.
2649                  */
2650                 REG_WR(bp, BNX2_HC_COMMAND,
2651                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2652                 REG_RD(bp, BNX2_HC_COMMAND);
2653         }
2654
2655         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
2656                 bnx2_tx_int(bp);
2657
2658         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons)
2659                 work_done += bnx2_rx_int(bp, budget - work_done);
2660
2661         return work_done;
2662 }
2663
2664 static int bnx2_poll(struct napi_struct *napi, int budget)
2665 {
2666         struct bnx2 *bp = container_of(napi, struct bnx2, napi);
2667         int work_done = 0;
2668
2669         while (1) {
2670                 work_done = bnx2_poll_work(bp, work_done, budget);
2671
2672                 if (unlikely(work_done >= budget))
2673                         break;
2674
2675                 if (likely(!bnx2_has_work(bp))) {
2676                         bp->last_status_idx = bp->status_blk->status_idx;
2677                         rmb();
2678
2679                         netif_rx_complete(bp->dev, napi);
2680                         if (likely(bp->flags & USING_MSI_FLAG)) {
2681                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2682                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2683                                        bp->last_status_idx);
2684                                 return 0;
2685                         }
2686                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2687                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2688                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2689                                bp->last_status_idx);
2690
2691                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2692                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2693                                bp->last_status_idx);
2694                         break;
2695                 }
2696         }
2697
2698         return work_done;
2699 }
2700
2701 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2702  * from set_multicast.
2703  */
2704 static void
2705 bnx2_set_rx_mode(struct net_device *dev)
2706 {
2707         struct bnx2 *bp = netdev_priv(dev);
2708         u32 rx_mode, sort_mode;
2709         int i;
2710
2711         spin_lock_bh(&bp->phy_lock);
2712
2713         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2714                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2715         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2716 #ifdef BCM_VLAN
2717         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2718                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2719 #else
2720         if (!(bp->flags & ASF_ENABLE_FLAG))
2721                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2722 #endif
2723         if (dev->flags & IFF_PROMISC) {
2724                 /* Promiscuous mode. */
2725                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2726                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2727                              BNX2_RPM_SORT_USER0_PROM_VLAN;
2728         }
2729         else if (dev->flags & IFF_ALLMULTI) {
2730                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2731                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2732                                0xffffffff);
2733                 }
2734                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2735         }
2736         else {
2737                 /* Accept one or more multicast(s). */
2738                 struct dev_mc_list *mclist;
2739                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2740                 u32 regidx;
2741                 u32 bit;
2742                 u32 crc;
2743
2744                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2745
2746                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2747                      i++, mclist = mclist->next) {
2748
2749                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2750                         bit = crc & 0xff;
2751                         regidx = (bit & 0xe0) >> 5;
2752                         bit &= 0x1f;
2753                         mc_filter[regidx] |= (1 << bit);
2754                 }
2755
2756                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2757                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2758                                mc_filter[i]);
2759                 }
2760
2761                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2762         }
2763
2764         if (rx_mode != bp->rx_mode) {
2765                 bp->rx_mode = rx_mode;
2766                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2767         }
2768
2769         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2770         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2771         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2772
2773         spin_unlock_bh(&bp->phy_lock);
2774 }
2775
2776 static void
2777 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2778         u32 rv2p_proc)
2779 {
2780         int i;
2781         u32 val;
2782
2783
2784         for (i = 0; i < rv2p_code_len; i += 8) {
2785                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2786                 rv2p_code++;
2787                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2788                 rv2p_code++;
2789
2790                 if (rv2p_proc == RV2P_PROC1) {
2791                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2792                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2793                 }
2794                 else {
2795                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2796                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2797                 }
2798         }
2799
2800         /* Reset the processor, un-stall is done later. */
2801         if (rv2p_proc == RV2P_PROC1) {
2802                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2803         }
2804         else {
2805                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2806         }
2807 }
2808
2809 static int
2810 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2811 {
2812         u32 offset;
2813         u32 val;
2814         int rc;
2815
2816         /* Halt the CPU. */
2817         val = REG_RD_IND(bp, cpu_reg->mode);
2818         val |= cpu_reg->mode_value_halt;
2819         REG_WR_IND(bp, cpu_reg->mode, val);
2820         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2821
2822         /* Load the Text area. */
2823         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2824         if (fw->gz_text) {
2825                 int j;
2826
2827                 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
2828                                        fw->gz_text_len);
2829                 if (rc < 0)
2830                         return rc;
2831
2832                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2833                         REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2834                 }
2835         }
2836
2837         /* Load the Data area. */
2838         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2839         if (fw->data) {
2840                 int j;
2841
2842                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2843                         REG_WR_IND(bp, offset, fw->data[j]);
2844                 }
2845         }
2846
2847         /* Load the SBSS area. */
2848         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2849         if (fw->sbss_len) {
2850                 int j;
2851
2852                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2853                         REG_WR_IND(bp, offset, 0);
2854                 }
2855         }
2856
2857         /* Load the BSS area. */
2858         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2859         if (fw->bss_len) {
2860                 int j;
2861
2862                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2863                         REG_WR_IND(bp, offset, 0);
2864                 }
2865         }
2866
2867         /* Load the Read-Only area. */
2868         offset = cpu_reg->spad_base +
2869                 (fw->rodata_addr - cpu_reg->mips_view_base);
2870         if (fw->rodata) {
2871                 int j;
2872
2873                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2874                         REG_WR_IND(bp, offset, fw->rodata[j]);
2875                 }
2876         }
2877
2878         /* Clear the pre-fetch instruction. */
2879         REG_WR_IND(bp, cpu_reg->inst, 0);
2880         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2881
2882         /* Start the CPU. */
2883         val = REG_RD_IND(bp, cpu_reg->mode);
2884         val &= ~cpu_reg->mode_value_halt;
2885         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2886         REG_WR_IND(bp, cpu_reg->mode, val);
2887
2888         return 0;
2889 }
2890
2891 static int
2892 bnx2_init_cpus(struct bnx2 *bp)
2893 {
2894         struct cpu_reg cpu_reg;
2895         struct fw_info *fw;
2896         int rc;
2897         void *text;
2898
2899         /* Initialize the RV2P processor. */
2900         text = vmalloc(FW_BUF_SIZE);
2901         if (!text)
2902                 return -ENOMEM;
2903         rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1));
2904         if (rc < 0)
2905                 goto init_cpu_err;
2906
2907         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
2908
2909         rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2));
2910         if (rc < 0)
2911                 goto init_cpu_err;
2912
2913         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
2914
2915         /* Initialize the RX Processor. */
2916         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2917         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2918         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2919         cpu_reg.state = BNX2_RXP_CPU_STATE;
2920         cpu_reg.state_value_clear = 0xffffff;
2921         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2922         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2923         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2924         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2925         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2926         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2927         cpu_reg.mips_view_base = 0x8000000;
2928
2929         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2930                 fw = &bnx2_rxp_fw_09;
2931         else
2932                 fw = &bnx2_rxp_fw_06;
2933
2934         fw->text = text;
2935         rc = load_cpu_fw(bp, &cpu_reg, fw);
2936         if (rc)
2937                 goto init_cpu_err;
2938
2939         /* Initialize the TX Processor. */
2940         cpu_reg.mode = BNX2_TXP_CPU_MODE;
2941         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2942         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2943         cpu_reg.state = BNX2_TXP_CPU_STATE;
2944         cpu_reg.state_value_clear = 0xffffff;
2945         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2946         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2947         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2948         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2949         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2950         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2951         cpu_reg.mips_view_base = 0x8000000;
2952
2953         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2954                 fw = &bnx2_txp_fw_09;
2955         else
2956                 fw = &bnx2_txp_fw_06;
2957
2958         fw->text = text;
2959         rc = load_cpu_fw(bp, &cpu_reg, fw);
2960         if (rc)
2961                 goto init_cpu_err;
2962
2963         /* Initialize the TX Patch-up Processor. */
2964         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2965         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2966         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2967         cpu_reg.state = BNX2_TPAT_CPU_STATE;
2968         cpu_reg.state_value_clear = 0xffffff;
2969         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2970         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2971         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2972         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2973         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2974         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2975         cpu_reg.mips_view_base = 0x8000000;
2976
2977         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2978                 fw = &bnx2_tpat_fw_09;
2979         else
2980                 fw = &bnx2_tpat_fw_06;
2981
2982         fw->text = text;
2983         rc = load_cpu_fw(bp, &cpu_reg, fw);
2984         if (rc)
2985                 goto init_cpu_err;
2986
2987         /* Initialize the Completion Processor. */
2988         cpu_reg.mode = BNX2_COM_CPU_MODE;
2989         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2990         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2991         cpu_reg.state = BNX2_COM_CPU_STATE;
2992         cpu_reg.state_value_clear = 0xffffff;
2993         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2994         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2995         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2996         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2997         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2998         cpu_reg.spad_base = BNX2_COM_SCRATCH;
2999         cpu_reg.mips_view_base = 0x8000000;
3000
3001         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3002                 fw = &bnx2_com_fw_09;
3003         else
3004                 fw = &bnx2_com_fw_06;
3005
3006         fw->text = text;
3007         rc = load_cpu_fw(bp, &cpu_reg, fw);
3008         if (rc)
3009                 goto init_cpu_err;
3010
3011         /* Initialize the Command Processor. */
3012         cpu_reg.mode = BNX2_CP_CPU_MODE;
3013         cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3014         cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3015         cpu_reg.state = BNX2_CP_CPU_STATE;
3016         cpu_reg.state_value_clear = 0xffffff;
3017         cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3018         cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3019         cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3020         cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3021         cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3022         cpu_reg.spad_base = BNX2_CP_SCRATCH;
3023         cpu_reg.mips_view_base = 0x8000000;
3024
3025         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3026                 fw = &bnx2_cp_fw_09;
3027
3028                 fw->text = text;
3029                 rc = load_cpu_fw(bp, &cpu_reg, fw);
3030                 if (rc)
3031                         goto init_cpu_err;
3032         }
3033 init_cpu_err:
3034         vfree(text);
3035         return rc;
3036 }
3037
3038 static int
3039 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3040 {
3041         u16 pmcsr;
3042
3043         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3044
3045         switch (state) {
3046         case PCI_D0: {
3047                 u32 val;
3048
3049                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3050                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3051                         PCI_PM_CTRL_PME_STATUS);
3052
3053                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3054                         /* delay required during transition out of D3hot */
3055                         msleep(20);
3056
3057                 val = REG_RD(bp, BNX2_EMAC_MODE);
3058                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3059                 val &= ~BNX2_EMAC_MODE_MPKT;
3060                 REG_WR(bp, BNX2_EMAC_MODE, val);
3061
3062                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3063                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3064                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3065                 break;
3066         }
3067         case PCI_D3hot: {
3068                 int i;
3069                 u32 val, wol_msg;
3070
3071                 if (bp->wol) {
3072                         u32 advertising;
3073                         u8 autoneg;
3074
3075                         autoneg = bp->autoneg;
3076                         advertising = bp->advertising;
3077
3078                         bp->autoneg = AUTONEG_SPEED;
3079                         bp->advertising = ADVERTISED_10baseT_Half |
3080                                 ADVERTISED_10baseT_Full |
3081                                 ADVERTISED_100baseT_Half |
3082                                 ADVERTISED_100baseT_Full |
3083                                 ADVERTISED_Autoneg;
3084
3085                         bnx2_setup_copper_phy(bp);
3086
3087                         bp->autoneg = autoneg;
3088                         bp->advertising = advertising;
3089
3090                         bnx2_set_mac_addr(bp);
3091
3092                         val = REG_RD(bp, BNX2_EMAC_MODE);
3093
3094                         /* Enable port mode. */
3095                         val &= ~BNX2_EMAC_MODE_PORT;
3096                         val |= BNX2_EMAC_MODE_PORT_MII |
3097                                BNX2_EMAC_MODE_MPKT_RCVD |
3098                                BNX2_EMAC_MODE_ACPI_RCVD |
3099                                BNX2_EMAC_MODE_MPKT;
3100
3101                         REG_WR(bp, BNX2_EMAC_MODE, val);
3102
3103                         /* receive all multicast */
3104                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3105                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3106                                        0xffffffff);
3107                         }
3108                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3109                                BNX2_EMAC_RX_MODE_SORT_MODE);
3110
3111                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3112                               BNX2_RPM_SORT_USER0_MC_EN;
3113                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3114                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3115                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3116                                BNX2_RPM_SORT_USER0_ENA);
3117
3118                         /* Need to enable EMAC and RPM for WOL. */
3119                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3120                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3121                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3122                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3123
3124                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3125                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3126                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3127
3128                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3129                 }
3130                 else {
3131                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3132                 }
3133
3134                 if (!(bp->flags & NO_WOL_FLAG))
3135                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3136
3137                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3138                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3139                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3140
3141                         if (bp->wol)
3142                                 pmcsr |= 3;
3143                 }
3144                 else {
3145                         pmcsr |= 3;
3146                 }
3147                 if (bp->wol) {
3148                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3149                 }
3150                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3151                                       pmcsr);
3152
3153                 /* No more memory access after this point until
3154                  * device is brought back to D0.
3155                  */
3156                 udelay(50);
3157                 break;
3158         }
3159         default:
3160                 return -EINVAL;
3161         }
3162         return 0;
3163 }
3164
3165 static int
3166 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3167 {
3168         u32 val;
3169         int j;
3170
3171         /* Request access to the flash interface. */
3172         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3173         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3174                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3175                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3176                         break;
3177
3178                 udelay(5);
3179         }
3180
3181         if (j >= NVRAM_TIMEOUT_COUNT)
3182                 return -EBUSY;
3183
3184         return 0;
3185 }
3186
3187 static int
3188 bnx2_release_nvram_lock(struct bnx2 *bp)
3189 {
3190         int j;
3191         u32 val;
3192
3193         /* Relinquish nvram interface. */
3194         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3195
3196         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3197                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3198                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3199                         break;
3200
3201                 udelay(5);
3202         }
3203
3204         if (j >= NVRAM_TIMEOUT_COUNT)
3205                 return -EBUSY;
3206
3207         return 0;
3208 }
3209
3210
3211 static int
3212 bnx2_enable_nvram_write(struct bnx2 *bp)
3213 {
3214         u32 val;
3215
3216         val = REG_RD(bp, BNX2_MISC_CFG);
3217         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3218
3219         if (bp->flash_info->flags & BNX2_NV_WREN) {
3220                 int j;
3221
3222                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3223                 REG_WR(bp, BNX2_NVM_COMMAND,
3224                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3225
3226                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3227                         udelay(5);
3228
3229                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3230                         if (val & BNX2_NVM_COMMAND_DONE)
3231                                 break;
3232                 }
3233
3234                 if (j >= NVRAM_TIMEOUT_COUNT)
3235                         return -EBUSY;
3236         }
3237         return 0;
3238 }
3239
3240 static void
3241 bnx2_disable_nvram_write(struct bnx2 *bp)
3242 {
3243         u32 val;
3244
3245         val = REG_RD(bp, BNX2_MISC_CFG);
3246         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3247 }
3248
3249
3250 static void
3251 bnx2_enable_nvram_access(struct bnx2 *bp)
3252 {
3253         u32 val;
3254
3255         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3256         /* Enable both bits, even on read. */
3257         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3258                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3259 }
3260
3261 static void
3262 bnx2_disable_nvram_access(struct bnx2 *bp)
3263 {
3264         u32 val;
3265
3266         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3267         /* Disable both bits, even after read. */
3268         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3269                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3270                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3271 }
3272
3273 static int
3274 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3275 {
3276         u32 cmd;
3277         int j;
3278
3279         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3280                 /* Buffered flash, no erase needed */
3281                 return 0;
3282
3283         /* Build an erase command */
3284         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3285               BNX2_NVM_COMMAND_DOIT;
3286
3287         /* Need to clear DONE bit separately. */
3288         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3289
3290         /* Address of the NVRAM to read from. */
3291         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3292
3293         /* Issue an erase command. */
3294         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3295
3296         /* Wait for completion. */
3297         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3298                 u32 val;
3299
3300                 udelay(5);
3301
3302                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3303                 if (val & BNX2_NVM_COMMAND_DONE)
3304                         break;
3305         }
3306
3307         if (j >= NVRAM_TIMEOUT_COUNT)
3308                 return -EBUSY;
3309
3310         return 0;
3311 }
3312
3313 static int
3314 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3315 {
3316         u32 cmd;
3317         int j;
3318
3319         /* Build the command word. */
3320         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3321
3322         /* Calculate an offset of a buffered flash, not needed for 5709. */
3323         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3324                 offset = ((offset / bp->flash_info->page_size) <<
3325                            bp->flash_info->page_bits) +
3326                           (offset % bp->flash_info->page_size);
3327         }
3328
3329         /* Need to clear DONE bit separately. */
3330         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3331
3332         /* Address of the NVRAM to read from. */
3333         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3334
3335         /* Issue a read command. */
3336         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3337
3338         /* Wait for completion. */
3339         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3340                 u32 val;
3341
3342                 udelay(5);
3343
3344                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3345                 if (val & BNX2_NVM_COMMAND_DONE) {
3346                         val = REG_RD(bp, BNX2_NVM_READ);
3347
3348                         val = be32_to_cpu(val);
3349                         memcpy(ret_val, &val, 4);
3350                         break;
3351                 }
3352         }
3353         if (j >= NVRAM_TIMEOUT_COUNT)
3354                 return -EBUSY;
3355
3356         return 0;
3357 }
3358
3359
3360 static int
3361 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3362 {
3363         u32 cmd, val32;
3364         int j;
3365
3366         /* Build the command word. */
3367         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3368
3369         /* Calculate an offset of a buffered flash, not needed for 5709. */
3370         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3371                 offset = ((offset / bp->flash_info->page_size) <<
3372                           bp->flash_info->page_bits) +
3373                          (offset % bp->flash_info->page_size);
3374         }
3375
3376         /* Need to clear DONE bit separately. */
3377         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3378
3379         memcpy(&val32, val, 4);
3380         val32 = cpu_to_be32(val32);
3381
3382         /* Write the data. */
3383         REG_WR(bp, BNX2_NVM_WRITE, val32);
3384
3385         /* Address of the NVRAM to write to. */
3386         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3387
3388         /* Issue the write command. */
3389         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3390
3391         /* Wait for completion. */
3392         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3393                 udelay(5);
3394
3395                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3396                         break;
3397         }
3398         if (j >= NVRAM_TIMEOUT_COUNT)
3399                 return -EBUSY;
3400
3401         return 0;
3402 }
3403
3404 static int
3405 bnx2_init_nvram(struct bnx2 *bp)
3406 {
3407         u32 val;
3408         int j, entry_count, rc = 0;
3409         struct flash_spec *flash;
3410
3411         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3412                 bp->flash_info = &flash_5709;
3413                 goto get_flash_size;
3414         }
3415
3416         /* Determine the selected interface. */
3417         val = REG_RD(bp, BNX2_NVM_CFG1);
3418
3419         entry_count = ARRAY_SIZE(flash_table);
3420
3421         if (val & 0x40000000) {
3422
3423                 /* Flash interface has been reconfigured */
3424                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3425                      j++, flash++) {
3426                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3427                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3428                                 bp->flash_info = flash;
3429                                 break;
3430                         }
3431                 }
3432         }
3433         else {
3434                 u32 mask;
3435                 /* Not yet been reconfigured */
3436
3437                 if (val & (1 << 23))
3438                         mask = FLASH_BACKUP_STRAP_MASK;
3439                 else
3440                         mask = FLASH_STRAP_MASK;
3441
3442                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3443                         j++, flash++) {
3444
3445                         if ((val & mask) == (flash->strapping & mask)) {
3446                                 bp->flash_info = flash;
3447
3448                                 /* Request access to the flash interface. */
3449                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3450                                         return rc;
3451
3452                                 /* Enable access to flash interface */
3453                                 bnx2_enable_nvram_access(bp);
3454
3455                                 /* Reconfigure the flash interface */
3456                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3457                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3458                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3459                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3460
3461                                 /* Disable access to flash interface */
3462                                 bnx2_disable_nvram_access(bp);
3463                                 bnx2_release_nvram_lock(bp);
3464
3465                                 break;
3466                         }
3467                 }
3468         } /* if (val & 0x40000000) */
3469
3470         if (j == entry_count) {
3471                 bp->flash_info = NULL;
3472                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3473                 return -ENODEV;
3474         }
3475
3476 get_flash_size:
3477         val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
3478         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3479         if (val)
3480                 bp->flash_size = val;
3481         else
3482                 bp->flash_size = bp->flash_info->total_size;
3483
3484         return rc;
3485 }
3486
3487 static int
3488 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3489                 int buf_size)
3490 {
3491         int rc = 0;
3492         u32 cmd_flags, offset32, len32, extra;
3493
3494         if (buf_size == 0)
3495                 return 0;
3496
3497         /* Request access to the flash interface. */
3498         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3499                 return rc;
3500
3501         /* Enable access to flash interface */
3502         bnx2_enable_nvram_access(bp);
3503
3504         len32 = buf_size;
3505         offset32 = offset;
3506         extra = 0;
3507
3508         cmd_flags = 0;
3509
3510         if (offset32 & 3) {
3511                 u8 buf[4];
3512                 u32 pre_len;
3513
3514                 offset32 &= ~3;
3515                 pre_len = 4 - (offset & 3);
3516
3517                 if (pre_len >= len32) {
3518                         pre_len = len32;
3519                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3520                                     BNX2_NVM_COMMAND_LAST;
3521                 }
3522                 else {
3523                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3524                 }
3525
3526                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3527
3528                 if (rc)
3529                         return rc;
3530
3531                 memcpy(ret_buf, buf + (offset & 3), pre_len);
3532
3533                 offset32 += 4;
3534                 ret_buf += pre_len;
3535                 len32 -= pre_len;
3536         }
3537         if (len32 & 3) {
3538                 extra = 4 - (len32 & 3);
3539                 len32 = (len32 + 4) & ~3;
3540         }
3541
3542         if (len32 == 4) {
3543                 u8 buf[4];
3544
3545                 if (cmd_flags)
3546                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3547                 else
3548                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3549                                     BNX2_NVM_COMMAND_LAST;
3550
3551                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3552
3553                 memcpy(ret_buf, buf, 4 - extra);
3554         }
3555         else if (len32 > 0) {
3556                 u8 buf[4];
3557
3558                 /* Read the first word. */
3559                 if (cmd_flags)
3560                         cmd_flags = 0;
3561                 else
3562                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3563
3564                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3565
3566                 /* Advance to the next dword. */
3567                 offset32 += 4;
3568                 ret_buf += 4;
3569                 len32 -= 4;
3570
3571                 while (len32 > 4 && rc == 0) {
3572                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3573
3574                         /* Advance to the next dword. */
3575                         offset32 += 4;
3576                         ret_buf += 4;
3577                         len32 -= 4;
3578                 }
3579
3580                 if (rc)
3581                         return rc;
3582
3583                 cmd_flags = BNX2_NVM_COMMAND_LAST;
3584                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3585
3586                 memcpy(ret_buf, buf, 4 - extra);
3587         }
3588
3589         /* Disable access to flash interface */
3590         bnx2_disable_nvram_access(bp);
3591
3592         bnx2_release_nvram_lock(bp);
3593
3594         return rc;
3595 }
3596
3597 static int
3598 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3599                 int buf_size)
3600 {
3601         u32 written, offset32, len32;
3602         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
3603         int rc = 0;
3604         int align_start, align_end;
3605
3606         buf = data_buf;
3607         offset32 = offset;
3608         len32 = buf_size;
3609         align_start = align_end = 0;
3610
3611         if ((align_start = (offset32 & 3))) {
3612                 offset32 &= ~3;
3613                 len32 += align_start;
3614                 if (len32 < 4)
3615                         len32 = 4;
3616                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3617                         return rc;
3618         }
3619
3620         if (len32 & 3) {
3621                 align_end = 4 - (len32 & 3);
3622                 len32 += align_end;
3623                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3624                         return rc;
3625         }
3626
3627         if (align_start || align_end) {
3628                 align_buf = kmalloc(len32, GFP_KERNEL);
3629                 if (align_buf == NULL)
3630                         return -ENOMEM;
3631                 if (align_start) {
3632                         memcpy(align_buf, start, 4);
3633                 }
3634                 if (align_end) {
3635                         memcpy(align_buf + len32 - 4, end, 4);
3636                 }
3637                 memcpy(align_buf + align_start, data_buf, buf_size);
3638                 buf = align_buf;
3639         }
3640
3641         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3642                 flash_buffer = kmalloc(264, GFP_KERNEL);
3643                 if (flash_buffer == NULL) {
3644                         rc = -ENOMEM;
3645                         goto nvram_write_end;
3646                 }
3647         }
3648
3649         written = 0;
3650         while ((written < len32) && (rc == 0)) {
3651                 u32 page_start, page_end, data_start, data_end;
3652                 u32 addr, cmd_flags;
3653                 int i;
3654
3655                 /* Find the page_start addr */
3656                 page_start = offset32 + written;
3657                 page_start -= (page_start % bp->flash_info->page_size);
3658                 /* Find the page_end addr */
3659                 page_end = page_start + bp->flash_info->page_size;
3660                 /* Find the data_start addr */
3661                 data_start = (written == 0) ? offset32 : page_start;
3662                 /* Find the data_end addr */
3663                 data_end = (page_end > offset32 + len32) ?
3664                         (offset32 + len32) : page_end;
3665
3666                 /* Request access to the flash interface. */
3667                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3668                         goto nvram_write_end;
3669
3670                 /* Enable access to flash interface */
3671                 bnx2_enable_nvram_access(bp);
3672
3673                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3674                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3675                         int j;
3676
3677                         /* Read the whole page into the buffer
3678                          * (non-buffer flash only) */
3679                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
3680                                 if (j == (bp->flash_info->page_size - 4)) {
3681                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
3682                                 }
3683                                 rc = bnx2_nvram_read_dword(bp,
3684                                         page_start + j,
3685                                         &flash_buffer[j],
3686                                         cmd_flags);
3687
3688                                 if (rc)
3689                                         goto nvram_write_end;
3690
3691                                 cmd_flags = 0;
3692                         }
3693                 }
3694
3695                 /* Enable writes to flash interface (unlock write-protect) */
3696                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3697                         goto nvram_write_end;
3698
3699                 /* Loop to write back the buffer data from page_start to
3700                  * data_start */
3701                 i = 0;
3702                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3703                         /* Erase the page */
3704                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3705                                 goto nvram_write_end;
3706
3707                         /* Re-enable the write again for the actual write */
3708                         bnx2_enable_nvram_write(bp);
3709
3710                         for (addr = page_start; addr < data_start;
3711                                 addr += 4, i += 4) {
3712
3713                                 rc = bnx2_nvram_write_dword(bp, addr,
3714                                         &flash_buffer[i], cmd_flags);
3715
3716                                 if (rc != 0)
3717                                         goto nvram_write_end;
3718
3719                                 cmd_flags = 0;
3720                         }
3721                 }
3722
3723                 /* Loop to write the new data from data_start to data_end */
3724                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3725                         if ((addr == page_end - 4) ||
3726                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
3727                                  (addr == data_end - 4))) {
3728
3729                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3730                         }
3731                         rc = bnx2_nvram_write_dword(bp, addr, buf,
3732                                 cmd_flags);
3733
3734                         if (rc != 0)
3735                                 goto nvram_write_end;
3736
3737                         cmd_flags = 0;
3738                         buf += 4;
3739                 }
3740
3741                 /* Loop to write back the buffer data from data_end
3742                  * to page_end */
3743                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3744                         for (addr = data_end; addr < page_end;
3745                                 addr += 4, i += 4) {
3746
3747                                 if (addr == page_end-4) {
3748                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3749                                 }
3750                                 rc = bnx2_nvram_write_dword(bp, addr,
3751                                         &flash_buffer[i], cmd_flags);
3752
3753                                 if (rc != 0)
3754                                         goto nvram_write_end;
3755
3756                                 cmd_flags = 0;
3757                         }
3758                 }
3759
3760                 /* Disable writes to flash interface (lock write-protect) */
3761                 bnx2_disable_nvram_write(bp);
3762
3763                 /* Disable access to flash interface */
3764                 bnx2_disable_nvram_access(bp);
3765                 bnx2_release_nvram_lock(bp);
3766
3767                 /* Increment written */
3768                 written += data_end - data_start;
3769         }
3770
3771 nvram_write_end:
3772         kfree(flash_buffer);
3773         kfree(align_buf);
3774         return rc;
3775 }
3776
3777 static void
3778 bnx2_init_remote_phy(struct bnx2 *bp)
3779 {
3780         u32 val;
3781
3782         bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG;
3783         if (!(bp->phy_flags & PHY_SERDES_FLAG))
3784                 return;
3785
3786         val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
3787         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
3788                 return;
3789
3790         if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
3791                 bp->phy_flags |= REMOTE_PHY_CAP_FLAG;
3792
3793                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
3794                 if (val & BNX2_LINK_STATUS_SERDES_LINK)
3795                         bp->phy_port = PORT_FIBRE;
3796                 else
3797                         bp->phy_port = PORT_TP;
3798
3799                 if (netif_running(bp->dev)) {
3800                         u32 sig;
3801
3802                         if (val & BNX2_LINK_STATUS_LINK_UP) {
3803                                 bp->link_up = 1;
3804                                 netif_carrier_on(bp->dev);
3805                         } else {
3806                                 bp->link_up = 0;
3807                                 netif_carrier_off(bp->dev);
3808                         }
3809                         sig = BNX2_DRV_ACK_CAP_SIGNATURE |
3810                               BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
3811                         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
3812                                    sig);
3813                 }
3814         }
3815 }
3816
3817 static int
3818 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3819 {
3820         u32 val;
3821         int i, rc = 0;
3822         u8 old_port;
3823
3824         /* Wait for the current PCI transaction to complete before
3825          * issuing a reset. */
3826         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3827                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3828                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3829                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3830                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3831         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3832         udelay(5);
3833
3834         /* Wait for the firmware to tell us it is ok to issue a reset. */
3835         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3836
3837         /* Deposit a driver reset signature so the firmware knows that
3838          * this is a soft reset. */
3839         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3840                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
3841
3842         /* Do a dummy read to force the chip to complete all current transaction
3843          * before we issue a reset. */
3844         val = REG_RD(bp, BNX2_MISC_ID);
3845
3846         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3847                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
3848                 REG_RD(bp, BNX2_MISC_COMMAND);
3849                 udelay(5);
3850
3851                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3852                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3853
3854                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
3855
3856         } else {
3857                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3858                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3859                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3860
3861                 /* Chip reset. */
3862                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3863
3864                 /* Reading back any register after chip reset will hang the
3865                  * bus on 5706 A0 and A1.  The msleep below provides plenty
3866                  * of margin for write posting.
3867                  */
3868                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3869                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
3870                         msleep(20);
3871
3872                 /* Reset takes approximate 30 usec */
3873                 for (i = 0; i < 10; i++) {
3874                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3875                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3876                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3877                                 break;
3878                         udelay(10);
3879                 }
3880
3881                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3882                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3883                         printk(KERN_ERR PFX "Chip reset did not complete\n");
3884                         return -EBUSY;
3885                 }
3886         }
3887
3888         /* Make sure byte swapping is properly configured. */
3889         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3890         if (val != 0x01020304) {
3891                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3892                 return -ENODEV;
3893         }
3894
3895         /* Wait for the firmware to finish its initialization. */
3896         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3897         if (rc)
3898                 return rc;
3899
3900         spin_lock_bh(&bp->phy_lock);
3901         old_port = bp->phy_port;
3902         bnx2_init_remote_phy(bp);
3903         if ((bp->phy_flags & REMOTE_PHY_CAP_FLAG) && old_port != bp->phy_port)
3904                 bnx2_set_default_remote_link(bp);
3905         spin_unlock_bh(&bp->phy_lock);
3906
3907         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3908                 /* Adjust the voltage regular to two steps lower.  The default
3909                  * of this register is 0x0000000e. */
3910                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3911
3912                 /* Remove bad rbuf memory from the free pool. */
3913                 rc = bnx2_alloc_bad_rbuf(bp);
3914         }
3915
3916         return rc;
3917 }
3918
3919 static int
3920 bnx2_init_chip(struct bnx2 *bp)
3921 {
3922         u32 val;
3923         int rc;
3924
3925         /* Make sure the interrupt is not active. */
3926         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3927
3928         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3929               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3930 #ifdef __BIG_ENDIAN
3931               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3932 #endif
3933               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3934               DMA_READ_CHANS << 12 |
3935               DMA_WRITE_CHANS << 16;
3936
3937         val |= (0x2 << 20) | (1 << 11);
3938
3939         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3940                 val |= (1 << 23);
3941
3942         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3943             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3944                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3945
3946         REG_WR(bp, BNX2_DMA_CONFIG, val);
3947
3948         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3949                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3950                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3951                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3952         }
3953
3954         if (bp->flags & PCIX_FLAG) {
3955                 u16 val16;
3956
3957                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3958                                      &val16);
3959                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3960                                       val16 & ~PCI_X_CMD_ERO);
3961         }
3962
3963         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3964                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3965                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3966                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3967
3968         /* Initialize context mapping and zero out the quick contexts.  The
3969          * context block must have already been enabled. */
3970         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3971                 rc = bnx2_init_5709_context(bp);
3972                 if (rc)
3973                         return rc;
3974         } else
3975                 bnx2_init_context(bp);
3976
3977         if ((rc = bnx2_init_cpus(bp)) != 0)
3978                 return rc;
3979
3980         bnx2_init_nvram(bp);
3981
3982         bnx2_set_mac_addr(bp);
3983
3984         val = REG_RD(bp, BNX2_MQ_CONFIG);
3985         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3986         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3987         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
3988                 val |= BNX2_MQ_CONFIG_HALT_DIS;
3989
3990         REG_WR(bp, BNX2_MQ_CONFIG, val);
3991
3992         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3993         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3994         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3995
3996         val = (BCM_PAGE_BITS - 8) << 24;
3997         REG_WR(bp, BNX2_RV2P_CONFIG, val);
3998
3999         /* Configure page size. */
4000         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4001         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4002         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4003         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4004
4005         val = bp->mac_addr[0] +
4006               (bp->mac_addr[1] << 8) +
4007               (bp->mac_addr[2] << 16) +
4008               bp->mac_addr[3] +
4009               (bp->mac_addr[4] << 8) +
4010               (bp->mac_addr[5] << 16);
4011         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4012
4013         /* Program the MTU.  Also include 4 bytes for CRC32. */
4014         val = bp->dev->mtu + ETH_HLEN + 4;
4015         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4016                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4017         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4018
4019         bp->last_status_idx = 0;
4020         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4021
4022         /* Set up how to generate a link change interrupt. */
4023         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4024
4025         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4026                (u64) bp->status_blk_mapping & 0xffffffff);
4027         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4028
4029         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4030                (u64) bp->stats_blk_mapping & 0xffffffff);
4031         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4032                (u64) bp->stats_blk_mapping >> 32);
4033
4034         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4035                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4036
4037         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4038                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4039
4040         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4041                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4042
4043         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4044
4045         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4046
4047         REG_WR(bp, BNX2_HC_COM_TICKS,
4048                (bp->com_ticks_int << 16) | bp->com_ticks);
4049
4050         REG_WR(bp, BNX2_HC_CMD_TICKS,
4051                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4052
4053         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4054                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4055         else
4056                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4057         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4058
4059         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4060                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4061         else {
4062                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4063                       BNX2_HC_CONFIG_COLLECT_STATS;
4064         }
4065
4066         if (bp->flags & ONE_SHOT_MSI_FLAG)
4067                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4068
4069         REG_WR(bp, BNX2_HC_CONFIG, val);
4070
4071         /* Clear internal stats counters. */
4072         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4073
4074         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4075
4076         /* Initialize the receive filter. */
4077         bnx2_set_rx_mode(bp->dev);
4078
4079         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4080                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4081                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4082                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4083         }
4084         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4085                           0);
4086
4087         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4088         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4089
4090         udelay(20);
4091
4092         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4093
4094         return rc;
4095 }
4096
4097 static void
4098 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4099 {
4100         u32 val, offset0, offset1, offset2, offset3;
4101
4102         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4103                 offset0 = BNX2_L2CTX_TYPE_XI;
4104                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4105                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4106                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4107         } else {
4108                 offset0 = BNX2_L2CTX_TYPE;
4109                 offset1 = BNX2_L2CTX_CMD_TYPE;
4110                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4111                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4112         }
4113         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4114         CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
4115
4116         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4117         CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
4118
4119         val = (u64) bp->tx_desc_mapping >> 32;
4120         CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
4121
4122         val = (u64) bp->tx_desc_mapping & 0xffffffff;
4123         CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
4124 }
4125
4126 static void
4127 bnx2_init_tx_ring(struct bnx2 *bp)
4128 {
4129         struct tx_bd *txbd;
4130         u32 cid;
4131
4132         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4133
4134         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4135
4136         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4137         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4138
4139         bp->tx_prod = 0;
4140         bp->tx_cons = 0;
4141         bp->hw_tx_cons = 0;
4142         bp->tx_prod_bseq = 0;
4143
4144         cid = TX_CID;
4145         bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4146         bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4147
4148         bnx2_init_tx_context(bp, cid);
4149 }
4150
4151 static void
4152 bnx2_init_rx_ring(struct bnx2 *bp)
4153 {
4154         struct rx_bd *rxbd;
4155         int i;
4156         u16 prod, ring_prod;
4157         u32 val;
4158
4159         /* 8 for CRC and VLAN */
4160         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4161         /* hw alignment */
4162         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4163
4164         ring_prod = prod = bp->rx_prod = 0;
4165         bp->rx_cons = 0;
4166         bp->hw_rx_cons = 0;
4167         bp->rx_prod_bseq = 0;
4168
4169         for (i = 0; i < bp->rx_max_ring; i++) {
4170                 int j;
4171
4172                 rxbd = &bp->rx_desc_ring[i][0];
4173                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4174                         rxbd->rx_bd_len = bp->rx_buf_use_size;
4175                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4176                 }
4177                 if (i == (bp->rx_max_ring - 1))
4178                         j = 0;
4179                 else
4180                         j = i + 1;
4181                 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
4182                 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
4183                                        0xffffffff;
4184         }
4185
4186         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
4187         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
4188         val |= 0x02 << 8;
4189         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
4190
4191         val = (u64) bp->rx_desc_mapping[0] >> 32;
4192         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
4193
4194         val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4195         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
4196
4197         for (i = 0; i < bp->rx_ring_size; i++) {
4198                 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
4199                         break;
4200                 }
4201                 prod = NEXT_RX_BD(prod);
4202                 ring_prod = RX_RING_IDX(prod);
4203         }
4204         bp->rx_prod = prod;
4205
4206         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4207
4208         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
4209 }
4210
4211 static void
4212 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4213 {
4214         u32 num_rings, max;
4215
4216         bp->rx_ring_size = size;
4217         num_rings = 1;
4218         while (size > MAX_RX_DESC_CNT) {
4219                 size -= MAX_RX_DESC_CNT;
4220                 num_rings++;
4221         }
4222         /* round to next power of 2 */
4223         max = MAX_RX_RINGS;
4224         while ((max & num_rings) == 0)
4225                 max >>= 1;
4226
4227         if (num_rings != max)
4228                 max <<= 1;
4229
4230         bp->rx_max_ring = max;
4231         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4232 }
4233
4234 static void
4235 bnx2_free_tx_skbs(struct bnx2 *bp)
4236 {
4237         int i;
4238
4239         if (bp->tx_buf_ring == NULL)
4240                 return;
4241
4242         for (i = 0; i < TX_DESC_CNT; ) {
4243                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4244                 struct sk_buff *skb = tx_buf->skb;
4245                 int j, last;
4246
4247                 if (skb == NULL) {
4248                         i++;
4249                         continue;
4250                 }
4251
4252                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4253                         skb_headlen(skb), PCI_DMA_TODEVICE);
4254
4255                 tx_buf->skb = NULL;
4256
4257                 last = skb_shinfo(skb)->nr_frags;
4258                 for (j = 0; j < last; j++) {
4259                         tx_buf = &bp->tx_buf_ring[i + j + 1];
4260                         pci_unmap_page(bp->pdev,
4261                                 pci_unmap_addr(tx_buf, mapping),
4262                                 skb_shinfo(skb)->frags[j].size,
4263                                 PCI_DMA_TODEVICE);
4264                 }
4265                 dev_kfree_skb(skb);
4266                 i += j + 1;
4267         }
4268
4269 }
4270
4271 static void
4272 bnx2_free_rx_skbs(struct bnx2 *bp)
4273 {
4274         int i;
4275
4276         if (bp->rx_buf_ring == NULL)
4277                 return;
4278
4279         for (i = 0; i < bp->rx_max_ring_idx; i++) {
4280                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4281                 struct sk_buff *skb = rx_buf->skb;
4282
4283                 if (skb == NULL)
4284                         continue;
4285
4286                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4287                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4288
4289                 rx_buf->skb = NULL;
4290
4291                 dev_kfree_skb(skb);
4292         }
4293 }
4294
4295 static void
4296 bnx2_free_skbs(struct bnx2 *bp)
4297 {
4298         bnx2_free_tx_skbs(bp);
4299         bnx2_free_rx_skbs(bp);
4300 }
4301
4302 static int
4303 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4304 {
4305         int rc;
4306
4307         rc = bnx2_reset_chip(bp, reset_code);
4308         bnx2_free_skbs(bp);
4309         if (rc)
4310                 return rc;
4311
4312         if ((rc = bnx2_init_chip(bp)) != 0)
4313                 return rc;
4314
4315         bnx2_init_tx_ring(bp);
4316         bnx2_init_rx_ring(bp);
4317         return 0;
4318 }
4319
4320 static int
4321 bnx2_init_nic(struct bnx2 *bp)
4322 {
4323         int rc;
4324
4325         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4326                 return rc;
4327
4328         spin_lock_bh(&bp->phy_lock);
4329         bnx2_init_phy(bp);
4330         bnx2_set_link(bp);
4331         spin_unlock_bh(&bp->phy_lock);
4332         return 0;
4333 }
4334
4335 static int
4336 bnx2_test_registers(struct bnx2 *bp)
4337 {
4338         int ret;
4339         int i, is_5709;
4340         static const struct {
4341                 u16   offset;
4342                 u16   flags;
4343 #define BNX2_FL_NOT_5709        1
4344                 u32   rw_mask;
4345                 u32   ro_mask;
4346         } reg_tbl[] = {
4347                 { 0x006c, 0, 0x00000000, 0x0000003f },
4348                 { 0x0090, 0, 0xffffffff, 0x00000000 },
4349                 { 0x0094, 0, 0x00000000, 0x00000000 },
4350
4351                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4352                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4353                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4354                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4355                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4356                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4357                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4358                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4359                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4360
4361                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4362                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4363                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4364                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4365                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4366                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4367
4368                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4369                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4370                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
4371
4372                 { 0x1000, 0, 0x00000000, 0x00000001 },
4373                 { 0x1004, 0, 0x00000000, 0x000f0001 },
4374
4375                 { 0x1408, 0, 0x01c00800, 0x00000000 },
4376                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4377                 { 0x14a8, 0, 0x00000000, 0x000001ff },
4378                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4379                 { 0x14b0, 0, 0x00000002, 0x00000001 },
4380                 { 0x14b8, 0, 0x00000000, 0x00000000 },
4381                 { 0x14c0, 0, 0x00000000, 0x00000009 },
4382                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4383                 { 0x14cc, 0, 0x00000000, 0x00000001 },
4384                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4385
4386                 { 0x1800, 0, 0x00000000, 0x00000001 },
4387                 { 0x1804, 0, 0x00000000, 0x00000003 },
4388
4389                 { 0x2800, 0, 0x00000000, 0x00000001 },
4390                 { 0x2804, 0, 0x00000000, 0x00003f01 },
4391                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4392                 { 0x2810, 0, 0xffff0000, 0x00000000 },
4393                 { 0x2814, 0, 0xffff0000, 0x00000000 },
4394                 { 0x2818, 0, 0xffff0000, 0x00000000 },
4395                 { 0x281c, 0, 0xffff0000, 0x00000000 },
4396                 { 0x2834, 0, 0xffffffff, 0x00000000 },
4397                 { 0x2840, 0, 0x00000000, 0xffffffff },
4398                 { 0x2844, 0, 0x00000000, 0xffffffff },
4399                 { 0x2848, 0, 0xffffffff, 0x00000000 },
4400                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4401
4402                 { 0x2c00, 0, 0x00000000, 0x00000011 },
4403                 { 0x2c04, 0, 0x00000000, 0x00030007 },
4404
4405                 { 0x3c00, 0, 0x00000000, 0x00000001 },
4406                 { 0x3c04, 0, 0x00000000, 0x00070000 },
4407                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4408                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4409                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4410                 { 0x3c14, 0, 0x00000000, 0xffffffff },
4411                 { 0x3c18, 0, 0x00000000, 0xffffffff },
4412                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4413                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4414
4415                 { 0x5004, 0, 0x00000000, 0x0000007f },
4416                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4417
4418                 { 0x5c00, 0, 0x00000000, 0x00000001 },
4419                 { 0x5c04, 0, 0x00000000, 0x0003000f },
4420                 { 0x5c08, 0, 0x00000003, 0x00000000 },
4421                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4422                 { 0x5c10, 0, 0x00000000, 0xffffffff },
4423                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4424                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4425                 { 0x5c88, 0, 0x00000000, 0x00077373 },
4426                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4427
4428                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4429                 { 0x680c, 0, 0xffffffff, 0x00000000 },
4430                 { 0x6810, 0, 0xffffffff, 0x00000000 },
4431                 { 0x6814, 0, 0xffffffff, 0x00000000 },
4432                 { 0x6818, 0, 0xffffffff, 0x00000000 },
4433                 { 0x681c, 0, 0xffffffff, 0x00000000 },
4434                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4435                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4436                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4437                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4438                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4439                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4440                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4441                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4442                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4443                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4444                 { 0x684c, 0, 0xffffffff, 0x00000000 },
4445                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4446                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4447                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4448                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4449                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4450                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4451
4452                 { 0xffff, 0, 0x00000000, 0x00000000 },
4453         };
4454
4455         ret = 0;
4456         is_5709 = 0;
4457         if (CHIP_NUM(bp) == CHIP_NUM_5709)
4458                 is_5709 = 1;
4459
4460         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
4461                 u32 offset, rw_mask, ro_mask, save_val, val;
4462                 u16 flags = reg_tbl[i].flags;
4463
4464                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
4465                         continue;
4466
4467                 offset = (u32) reg_tbl[i].offset;
4468                 rw_mask = reg_tbl[i].rw_mask;
4469                 ro_mask = reg_tbl[i].ro_mask;
4470
4471                 save_val = readl(bp->regview + offset);
4472
4473                 writel(0, bp->regview + offset);
4474
4475                 val = readl(bp->regview + offset);
4476                 if ((val & rw_mask) != 0) {
4477                         goto reg_test_err;
4478                 }
4479
4480                 if ((val & ro_mask) != (save_val & ro_mask)) {
4481                         goto reg_test_err;
4482                 }
4483
4484                 writel(0xffffffff, bp->regview + offset);
4485
4486                 val = readl(bp->regview + offset);
4487                 if ((val & rw_mask) != rw_mask) {
4488                         goto reg_test_err;
4489                 }
4490
4491                 if ((val & ro_mask) != (save_val & ro_mask)) {
4492                         goto reg_test_err;
4493                 }
4494
4495                 writel(save_val, bp->regview + offset);
4496                 continue;
4497
4498 reg_test_err:
4499                 writel(save_val, bp->regview + offset);
4500                 ret = -ENODEV;
4501                 break;
4502         }
4503         return ret;
4504 }
4505
4506 static int
4507 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
4508 {
4509         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
4510                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
4511         int i;
4512
4513         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
4514                 u32 offset;
4515
4516                 for (offset = 0; offset < size; offset += 4) {
4517
4518                         REG_WR_IND(bp, start + offset, test_pattern[i]);
4519
4520                         if (REG_RD_IND(bp, start + offset) !=
4521                                 test_pattern[i]) {
4522                                 return -ENODEV;
4523                         }
4524                 }
4525         }
4526         return 0;
4527 }
4528
4529 static int
4530 bnx2_test_memory(struct bnx2 *bp)
4531 {
4532         int ret = 0;
4533         int i;
4534         static struct mem_entry {
4535                 u32   offset;
4536                 u32   len;
4537         } mem_tbl_5706[] = {
4538                 { 0x60000,  0x4000 },
4539                 { 0xa0000,  0x3000 },
4540                 { 0xe0000,  0x4000 },
4541                 { 0x120000, 0x4000 },
4542                 { 0x1a0000, 0x4000 },
4543                 { 0x160000, 0x4000 },
4544                 { 0xffffffff, 0    },
4545         },
4546         mem_tbl_5709[] = {
4547                 { 0x60000,  0x4000 },
4548                 { 0xa0000,  0x3000 },
4549                 { 0xe0000,  0x4000 },
4550                 { 0x120000, 0x4000 },
4551                 { 0x1a0000, 0x4000 },
4552                 { 0xffffffff, 0    },
4553         };
4554         struct mem_entry *mem_tbl;
4555
4556         if (CHIP_NUM(bp) == CHIP_NUM_5709)
4557                 mem_tbl = mem_tbl_5709;
4558         else
4559                 mem_tbl = mem_tbl_5706;
4560
4561         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
4562                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
4563                         mem_tbl[i].len)) != 0) {
4564                         return ret;
4565                 }
4566         }
4567
4568         return ret;
4569 }
4570
4571 #define BNX2_MAC_LOOPBACK       0
4572 #define BNX2_PHY_LOOPBACK       1
4573
4574 static int
4575 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
4576 {
4577         unsigned int pkt_size, num_pkts, i;
4578         struct sk_buff *skb, *rx_skb;
4579         unsigned char *packet;
4580         u16 rx_start_idx, rx_idx;
4581         dma_addr_t map;
4582         struct tx_bd *txbd;
4583         struct sw_bd *rx_buf;
4584         struct l2_fhdr *rx_hdr;
4585         int ret = -ENODEV;
4586
4587         if (loopback_mode == BNX2_MAC_LOOPBACK) {
4588                 bp->loopback = MAC_LOOPBACK;
4589                 bnx2_set_mac_loopback(bp);
4590         }
4591         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
4592                 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4593                         return 0;
4594
4595                 bp->loopback = PHY_LOOPBACK;
4596                 bnx2_set_phy_loopback(bp);
4597         }
4598         else
4599                 return -EINVAL;
4600
4601         pkt_size = 1514;
4602         skb = netdev_alloc_skb(bp->dev, pkt_size);
4603         if (!skb)
4604                 return -ENOMEM;
4605         packet = skb_put(skb, pkt_size);
4606         memcpy(packet, bp->dev->dev_addr, 6);
4607         memset(packet + 6, 0x0, 8);
4608         for (i = 14; i < pkt_size; i++)
4609                 packet[i] = (unsigned char) (i & 0xff);
4610
4611         map = pci_map_single(bp->pdev, skb->data, pkt_size,
4612                 PCI_DMA_TODEVICE);
4613
4614         REG_WR(bp, BNX2_HC_COMMAND,
4615                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4616
4617         REG_RD(bp, BNX2_HC_COMMAND);
4618
4619         udelay(5);
4620         rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
4621
4622         num_pkts = 0;
4623
4624         txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
4625
4626         txbd->tx_bd_haddr_hi = (u64) map >> 32;
4627         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
4628         txbd->tx_bd_mss_nbytes = pkt_size;
4629         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
4630
4631         num_pkts++;
4632         bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
4633         bp->tx_prod_bseq += pkt_size;
4634
4635         REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
4636         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4637
4638         udelay(100);
4639
4640         REG_WR(bp, BNX2_HC_COMMAND,
4641                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4642
4643         REG_RD(bp, BNX2_HC_COMMAND);
4644
4645         udelay(5);
4646
4647         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4648         dev_kfree_skb(skb);
4649
4650         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4651                 goto loopback_test_done;
4652         }
4653
4654         rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4655         if (rx_idx != rx_start_idx + num_pkts) {
4656                 goto loopback_test_done;
4657         }
4658
4659         rx_buf = &bp->rx_buf_ring[rx_start_idx];
4660         rx_skb = rx_buf->skb;
4661
4662         rx_hdr = (struct l2_fhdr *) rx_skb->data;
4663         skb_reserve(rx_skb, bp->rx_offset);
4664
4665         pci_dma_sync_single_for_cpu(bp->pdev,
4666                 pci_unmap_addr(rx_buf, mapping),
4667                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4668
4669         if (rx_hdr->l2_fhdr_status &
4670                 (L2_FHDR_ERRORS_BAD_CRC |
4671                 L2_FHDR_ERRORS_PHY_DECODE |
4672                 L2_FHDR_ERRORS_ALIGNMENT |
4673                 L2_FHDR_ERRORS_TOO_SHORT |
4674                 L2_FHDR_ERRORS_GIANT_FRAME)) {
4675
4676                 goto loopback_test_done;
4677         }
4678
4679         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4680                 goto loopback_test_done;
4681         }
4682
4683         for (i = 14; i < pkt_size; i++) {
4684                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4685                         goto loopback_test_done;
4686                 }
4687         }
4688
4689         ret = 0;
4690
4691 loopback_test_done:
4692         bp->loopback = 0;
4693         return ret;
4694 }
4695
4696 #define BNX2_MAC_LOOPBACK_FAILED        1
4697 #define BNX2_PHY_LOOPBACK_FAILED        2
4698 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
4699                                          BNX2_PHY_LOOPBACK_FAILED)
4700
4701 static int
4702 bnx2_test_loopback(struct bnx2 *bp)
4703 {
4704         int rc = 0;
4705
4706         if (!netif_running(bp->dev))
4707                 return BNX2_LOOPBACK_FAILED;
4708
4709         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4710         spin_lock_bh(&bp->phy_lock);
4711         bnx2_init_phy(bp);
4712         spin_unlock_bh(&bp->phy_lock);
4713         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4714                 rc |= BNX2_MAC_LOOPBACK_FAILED;
4715         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4716                 rc |= BNX2_PHY_LOOPBACK_FAILED;
4717         return rc;
4718 }
4719
4720 #define NVRAM_SIZE 0x200
4721 #define CRC32_RESIDUAL 0xdebb20e3
4722
4723 static int
4724 bnx2_test_nvram(struct bnx2 *bp)
4725 {
4726         u32 buf[NVRAM_SIZE / 4];
4727         u8 *data = (u8 *) buf;
4728         int rc = 0;
4729         u32 magic, csum;
4730
4731         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4732                 goto test_nvram_done;
4733
4734         magic = be32_to_cpu(buf[0]);
4735         if (magic != 0x669955aa) {
4736                 rc = -ENODEV;
4737                 goto test_nvram_done;
4738         }
4739
4740         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4741                 goto test_nvram_done;
4742
4743         csum = ether_crc_le(0x100, data);
4744         if (csum != CRC32_RESIDUAL) {
4745                 rc = -ENODEV;
4746                 goto test_nvram_done;
4747         }
4748
4749         csum = ether_crc_le(0x100, data + 0x100);
4750         if (csum != CRC32_RESIDUAL) {
4751                 rc = -ENODEV;
4752         }
4753
4754 test_nvram_done:
4755         return rc;
4756 }
4757
4758 static int
4759 bnx2_test_link(struct bnx2 *bp)
4760 {
4761         u32 bmsr;
4762
4763         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
4764                 if (bp->link_up)
4765                         return 0;
4766                 return -ENODEV;
4767         }
4768         spin_lock_bh(&bp->phy_lock);
4769         bnx2_enable_bmsr1(bp);
4770         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4771         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4772         bnx2_disable_bmsr1(bp);
4773         spin_unlock_bh(&bp->phy_lock);
4774
4775         if (bmsr & BMSR_LSTATUS) {
4776                 return 0;
4777         }
4778         return -ENODEV;
4779 }
4780
4781 static int
4782 bnx2_test_intr(struct bnx2 *bp)
4783 {
4784         int i;
4785         u16 status_idx;
4786
4787         if (!netif_running(bp->dev))
4788                 return -ENODEV;
4789
4790         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4791
4792         /* This register is not touched during run-time. */
4793         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
4794         REG_RD(bp, BNX2_HC_COMMAND);
4795
4796         for (i = 0; i < 10; i++) {
4797                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4798                         status_idx) {
4799
4800                         break;
4801                 }
4802
4803                 msleep_interruptible(10);
4804         }
4805         if (i < 10)
4806                 return 0;
4807
4808         return -ENODEV;
4809 }
4810
4811 static void
4812 bnx2_5706_serdes_timer(struct bnx2 *bp)
4813 {
4814         spin_lock(&bp->phy_lock);
4815         if (bp->serdes_an_pending)
4816                 bp->serdes_an_pending--;
4817         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4818                 u32 bmcr;
4819
4820                 bp->current_interval = bp->timer_interval;
4821
4822                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4823
4824                 if (bmcr & BMCR_ANENABLE) {
4825                         u32 phy1, phy2;
4826
4827                         bnx2_write_phy(bp, 0x1c, 0x7c00);
4828                         bnx2_read_phy(bp, 0x1c, &phy1);
4829
4830                         bnx2_write_phy(bp, 0x17, 0x0f01);
4831                         bnx2_read_phy(bp, 0x15, &phy2);
4832                         bnx2_write_phy(bp, 0x17, 0x0f01);
4833                         bnx2_read_phy(bp, 0x15, &phy2);
4834
4835                         if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
4836                                 !(phy2 & 0x20)) {       /* no CONFIG */
4837
4838                                 bmcr &= ~BMCR_ANENABLE;
4839                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4840                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4841                                 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
4842                         }
4843                 }
4844         }
4845         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4846                  (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4847                 u32 phy2;
4848
4849                 bnx2_write_phy(bp, 0x17, 0x0f01);
4850                 bnx2_read_phy(bp, 0x15, &phy2);
4851                 if (phy2 & 0x20) {
4852                         u32 bmcr;
4853
4854                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4855                         bmcr |= BMCR_ANENABLE;
4856                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4857
4858                         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4859                 }
4860         } else
4861                 bp->current_interval = bp->timer_interval;
4862
4863         spin_unlock(&bp->phy_lock);
4864 }
4865
4866 static void
4867 bnx2_5708_serdes_timer(struct bnx2 *bp)
4868 {
4869         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4870                 return;
4871
4872         if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
4873                 bp->serdes_an_pending = 0;
4874                 return;
4875         }
4876
4877         spin_lock(&bp->phy_lock);
4878         if (bp->serdes_an_pending)
4879                 bp->serdes_an_pending--;
4880         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4881                 u32 bmcr;
4882
4883                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4884                 if (bmcr & BMCR_ANENABLE) {
4885                         bnx2_enable_forced_2g5(bp);
4886                         bp->current_interval = SERDES_FORCED_TIMEOUT;
4887                 } else {
4888                         bnx2_disable_forced_2g5(bp);
4889                         bp->serdes_an_pending = 2;
4890                         bp->current_interval = bp->timer_interval;
4891                 }
4892
4893         } else
4894                 bp->current_interval = bp->timer_interval;
4895
4896         spin_unlock(&bp->phy_lock);
4897 }
4898
4899 static void
4900 bnx2_timer(unsigned long data)
4901 {
4902         struct bnx2 *bp = (struct bnx2 *) data;
4903
4904         if (!netif_running(bp->dev))
4905                 return;
4906
4907         if (atomic_read(&bp->intr_sem) != 0)
4908                 goto bnx2_restart_timer;
4909
4910         bnx2_send_heart_beat(bp);
4911
4912         bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4913
4914         /* workaround occasional corrupted counters */
4915         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
4916                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
4917                                             BNX2_HC_COMMAND_STATS_NOW);
4918
4919         if (bp->phy_flags & PHY_SERDES_FLAG) {
4920                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4921                         bnx2_5706_serdes_timer(bp);
4922                 else
4923                         bnx2_5708_serdes_timer(bp);
4924         }
4925
4926 bnx2_restart_timer:
4927         mod_timer(&bp->timer, jiffies + bp->current_interval);
4928 }
4929
4930 static int
4931 bnx2_request_irq(struct bnx2 *bp)
4932 {
4933         struct net_device *dev = bp->dev;
4934         int rc = 0;
4935
4936         if (bp->flags & USING_MSI_FLAG) {
4937                 irq_handler_t   fn = bnx2_msi;
4938
4939                 if (bp->flags & ONE_SHOT_MSI_FLAG)
4940                         fn = bnx2_msi_1shot;
4941
4942                 rc = request_irq(bp->pdev->irq, fn, 0, dev->name, dev);
4943         } else
4944                 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4945                                  IRQF_SHARED, dev->name, dev);
4946         return rc;
4947 }
4948
4949 static void
4950 bnx2_free_irq(struct bnx2 *bp)
4951 {
4952         struct net_device *dev = bp->dev;
4953
4954         if (bp->flags & USING_MSI_FLAG) {
4955                 free_irq(bp->pdev->irq, dev);
4956                 pci_disable_msi(bp->pdev);
4957                 bp->flags &= ~(USING_MSI_FLAG | ONE_SHOT_MSI_FLAG);
4958         } else
4959                 free_irq(bp->pdev->irq, dev);
4960 }
4961
4962 /* Called with rtnl_lock */
4963 static int
4964 bnx2_open(struct net_device *dev)
4965 {
4966         struct bnx2 *bp = netdev_priv(dev);
4967         int rc;
4968
4969         netif_carrier_off(dev);
4970
4971         bnx2_set_power_state(bp, PCI_D0);
4972         bnx2_disable_int(bp);
4973
4974         rc = bnx2_alloc_mem(bp);
4975         if (rc)
4976                 return rc;
4977
4978         napi_enable(&bp->napi);
4979
4980         if ((bp->flags & MSI_CAP_FLAG) && !disable_msi) {
4981                 if (pci_enable_msi(bp->pdev) == 0) {
4982                         bp->flags |= USING_MSI_FLAG;
4983                         if (CHIP_NUM(bp) == CHIP_NUM_5709)
4984                                 bp->flags |= ONE_SHOT_MSI_FLAG;
4985                 }
4986         }
4987         rc = bnx2_request_irq(bp);
4988
4989         if (rc) {
4990                 napi_disable(&bp->napi);
4991                 bnx2_free_mem(bp);
4992                 return rc;
4993         }
4994
4995         rc = bnx2_init_nic(bp);
4996
4997         if (rc) {
4998                 napi_disable(&bp->napi);
4999                 bnx2_free_irq(bp);
5000                 bnx2_free_skbs(bp);
5001                 bnx2_free_mem(bp);
5002                 return rc;
5003         }
5004
5005         mod_timer(&bp->timer, jiffies + bp->current_interval);
5006
5007         atomic_set(&bp->intr_sem, 0);
5008
5009         bnx2_enable_int(bp);
5010
5011         if (bp->flags & USING_MSI_FLAG) {
5012                 /* Test MSI to make sure it is working
5013                  * If MSI test fails, go back to INTx mode
5014                  */
5015                 if (bnx2_test_intr(bp) != 0) {
5016                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5017                                " using MSI, switching to INTx mode. Please"
5018                                " report this failure to the PCI maintainer"
5019                                " and include system chipset information.\n",
5020                                bp->dev->name);
5021
5022                         bnx2_disable_int(bp);
5023                         bnx2_free_irq(bp);
5024
5025                         rc = bnx2_init_nic(bp);
5026
5027                         if (!rc)
5028                                 rc = bnx2_request_irq(bp);
5029
5030                         if (rc) {
5031                                 napi_disable(&bp->napi);
5032                                 bnx2_free_skbs(bp);
5033                                 bnx2_free_mem(bp);
5034                                 del_timer_sync(&bp->timer);
5035                                 return rc;
5036                         }
5037                         bnx2_enable_int(bp);
5038                 }
5039         }
5040         if (bp->flags & USING_MSI_FLAG) {
5041                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5042         }
5043
5044         netif_start_queue(dev);
5045
5046         return 0;
5047 }
5048
5049 static void
5050 bnx2_reset_task(struct work_struct *work)
5051 {
5052         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5053
5054         if (!netif_running(bp->dev))
5055                 return;
5056
5057         bp->in_reset_task = 1;
5058         bnx2_netif_stop(bp);
5059
5060         bnx2_init_nic(bp);
5061
5062         atomic_set(&bp->intr_sem, 1);
5063         bnx2_netif_start(bp);
5064         bp->in_reset_task = 0;
5065 }
5066
5067 static void
5068 bnx2_tx_timeout(struct net_device *dev)
5069 {
5070         struct bnx2 *bp = netdev_priv(dev);
5071
5072         /* This allows the netif to be shutdown gracefully before resetting */
5073         schedule_work(&bp->reset_task);
5074 }
5075
5076 #ifdef BCM_VLAN
5077 /* Called with rtnl_lock */
5078 static void
5079 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5080 {
5081         struct bnx2 *bp = netdev_priv(dev);
5082
5083         bnx2_netif_stop(bp);
5084
5085         bp->vlgrp = vlgrp;
5086         bnx2_set_rx_mode(dev);
5087
5088         bnx2_netif_start(bp);
5089 }
5090 #endif
5091
5092 /* Called with netif_tx_lock.
5093  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5094  * netif_wake_queue().
5095  */
5096 static int
5097 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5098 {
5099         struct bnx2 *bp = netdev_priv(dev);
5100         dma_addr_t mapping;
5101         struct tx_bd *txbd;
5102         struct sw_bd *tx_buf;
5103         u32 len, vlan_tag_flags, last_frag, mss;
5104         u16 prod, ring_prod;
5105         int i;
5106
5107         if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
5108                 netif_stop_queue(dev);
5109                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5110                         dev->name);
5111
5112                 return NETDEV_TX_BUSY;
5113         }
5114         len = skb_headlen(skb);
5115         prod = bp->tx_prod;
5116         ring_prod = TX_RING_IDX(prod);
5117
5118         vlan_tag_flags = 0;
5119         if (skb->ip_summed == CHECKSUM_PARTIAL) {
5120                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5121         }
5122
5123         if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
5124                 vlan_tag_flags |=
5125                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5126         }
5127         if ((mss = skb_shinfo(skb)->gso_size)) {
5128                 u32 tcp_opt_len, ip_tcp_len;
5129                 struct iphdr *iph;
5130
5131                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5132
5133                 tcp_opt_len = tcp_optlen(skb);
5134
5135                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5136                         u32 tcp_off = skb_transport_offset(skb) -
5137                                       sizeof(struct ipv6hdr) - ETH_HLEN;
5138
5139                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5140                                           TX_BD_FLAGS_SW_FLAGS;
5141                         if (likely(tcp_off == 0))
5142                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5143                         else {
5144                                 tcp_off >>= 3;
5145                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
5146                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
5147                                                   ((tcp_off & 0x10) <<
5148                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
5149                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5150                         }
5151                 } else {
5152                         if (skb_header_cloned(skb) &&
5153                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5154                                 dev_kfree_skb(skb);
5155                                 return NETDEV_TX_OK;
5156                         }
5157
5158                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5159
5160                         iph = ip_hdr(skb);
5161                         iph->check = 0;
5162                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5163                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5164                                                                  iph->daddr, 0,
5165                                                                  IPPROTO_TCP,
5166                                                                  0);
5167                         if (tcp_opt_len || (iph->ihl > 5)) {
5168                                 vlan_tag_flags |= ((iph->ihl - 5) +
5169                                                    (tcp_opt_len >> 2)) << 8;
5170                         }
5171                 }
5172         } else
5173                 mss = 0;
5174
5175         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5176
5177         tx_buf = &bp->tx_buf_ring[ring_prod];
5178         tx_buf->skb = skb;
5179         pci_unmap_addr_set(tx_buf, mapping, mapping);
5180
5181         txbd = &bp->tx_desc_ring[ring_prod];
5182
5183         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5184         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5185         txbd->tx_bd_mss_nbytes = len | (mss << 16);
5186         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5187
5188         last_frag = skb_shinfo(skb)->nr_frags;
5189
5190         for (i = 0; i < last_frag; i++) {
5191                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5192
5193                 prod = NEXT_TX_BD(prod);
5194                 ring_prod = TX_RING_IDX(prod);
5195                 txbd = &bp->tx_desc_ring[ring_prod];
5196
5197                 len = frag->size;
5198                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5199                         len, PCI_DMA_TODEVICE);
5200                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5201                                 mapping, mapping);
5202
5203                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5204                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5205                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5206                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5207
5208         }
5209         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5210
5211         prod = NEXT_TX_BD(prod);
5212         bp->tx_prod_bseq += skb->len;
5213
5214         REG_WR16(bp, bp->tx_bidx_addr, prod);
5215         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5216
5217         mmiowb();
5218
5219         bp->tx_prod = prod;
5220         dev->trans_start = jiffies;
5221
5222         if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
5223                 netif_stop_queue(dev);
5224                 if (bnx2_tx_avail(bp) > bp->tx_wake_thresh)
5225                         netif_wake_queue(dev);
5226         }
5227
5228         return NETDEV_TX_OK;
5229 }
5230
5231 /* Called with rtnl_lock */
5232 static int
5233 bnx2_close(struct net_device *dev)
5234 {
5235         struct bnx2 *bp = netdev_priv(dev);
5236         u32 reset_code;
5237
5238         /* Calling flush_scheduled_work() may deadlock because
5239          * linkwatch_event() may be on the workqueue and it will try to get
5240          * the rtnl_lock which we are holding.
5241          */
5242         while (bp->in_reset_task)
5243                 msleep(1);
5244
5245         bnx2_disable_int_sync(bp);
5246         napi_disable(&bp->napi);
5247         del_timer_sync(&bp->timer);
5248         if (bp->flags & NO_WOL_FLAG)
5249                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5250         else if (bp->wol)
5251                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5252         else
5253                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5254         bnx2_reset_chip(bp, reset_code);
5255         bnx2_free_irq(bp);
5256         bnx2_free_skbs(bp);
5257         bnx2_free_mem(bp);
5258         bp->link_up = 0;
5259         netif_carrier_off(bp->dev);
5260         bnx2_set_power_state(bp, PCI_D3hot);
5261         return 0;
5262 }
5263
5264 #define GET_NET_STATS64(ctr)                                    \
5265         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
5266         (unsigned long) (ctr##_lo)
5267
5268 #define GET_NET_STATS32(ctr)            \
5269         (ctr##_lo)
5270
5271 #if (BITS_PER_LONG == 64)
5272 #define GET_NET_STATS   GET_NET_STATS64
5273 #else
5274 #define GET_NET_STATS   GET_NET_STATS32
5275 #endif
5276
5277 static struct net_device_stats *
5278 bnx2_get_stats(struct net_device *dev)
5279 {
5280         struct bnx2 *bp = netdev_priv(dev);
5281         struct statistics_block *stats_blk = bp->stats_blk;
5282         struct net_device_stats *net_stats = &bp->net_stats;
5283
5284         if (bp->stats_blk == NULL) {
5285                 return net_stats;
5286         }
5287         net_stats->rx_packets =
5288                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5289                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5290                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5291
5292         net_stats->tx_packets =
5293                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5294                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5295                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5296
5297         net_stats->rx_bytes =
5298                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5299
5300         net_stats->tx_bytes =
5301                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5302
5303         net_stats->multicast =
5304                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5305
5306         net_stats->collisions =
5307                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5308
5309         net_stats->rx_length_errors =
5310                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5311                 stats_blk->stat_EtherStatsOverrsizePkts);
5312
5313         net_stats->rx_over_errors =
5314                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5315
5316         net_stats->rx_frame_errors =
5317                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5318
5319         net_stats->rx_crc_errors =
5320                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5321
5322         net_stats->rx_errors = net_stats->rx_length_errors +
5323                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5324                 net_stats->rx_crc_errors;
5325
5326         net_stats->tx_aborted_errors =
5327                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5328                 stats_blk->stat_Dot3StatsLateCollisions);
5329
5330         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5331             (CHIP_ID(bp) == CHIP_ID_5708_A0))
5332                 net_stats->tx_carrier_errors = 0;
5333         else {
5334                 net_stats->tx_carrier_errors =
5335                         (unsigned long)
5336                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
5337         }
5338
5339         net_stats->tx_errors =
5340                 (unsigned long)
5341                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
5342                 +
5343                 net_stats->tx_aborted_errors +
5344                 net_stats->tx_carrier_errors;
5345
5346         net_stats->rx_missed_errors =
5347                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
5348                 stats_blk->stat_FwRxDrop);
5349
5350         return net_stats;
5351 }
5352
5353 /* All ethtool functions called with rtnl_lock */
5354
5355 static int
5356 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5357 {
5358         struct bnx2 *bp = netdev_priv(dev);
5359         int support_serdes = 0, support_copper = 0;
5360
5361         cmd->supported = SUPPORTED_Autoneg;
5362         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5363                 support_serdes = 1;
5364                 support_copper = 1;
5365         } else if (bp->phy_port == PORT_FIBRE)
5366                 support_serdes = 1;
5367         else
5368                 support_copper = 1;
5369
5370         if (support_serdes) {
5371                 cmd->supported |= SUPPORTED_1000baseT_Full |
5372                         SUPPORTED_FIBRE;
5373                 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
5374                         cmd->supported |= SUPPORTED_2500baseX_Full;
5375
5376         }
5377         if (support_copper) {
5378                 cmd->supported |= SUPPORTED_10baseT_Half |
5379                         SUPPORTED_10baseT_Full |
5380                         SUPPORTED_100baseT_Half |
5381                         SUPPORTED_100baseT_Full |
5382                         SUPPORTED_1000baseT_Full |
5383                         SUPPORTED_TP;
5384
5385         }
5386
5387         spin_lock_bh(&bp->phy_lock);
5388         cmd->port = bp->phy_port;
5389         cmd->advertising = bp->advertising;
5390
5391         if (bp->autoneg & AUTONEG_SPEED) {
5392                 cmd->autoneg = AUTONEG_ENABLE;
5393         }
5394         else {
5395                 cmd->autoneg = AUTONEG_DISABLE;
5396         }
5397
5398         if (netif_carrier_ok(dev)) {
5399                 cmd->speed = bp->line_speed;
5400                 cmd->duplex = bp->duplex;
5401         }
5402         else {
5403                 cmd->speed = -1;
5404                 cmd->duplex = -1;
5405         }
5406         spin_unlock_bh(&bp->phy_lock);
5407
5408         cmd->transceiver = XCVR_INTERNAL;
5409         cmd->phy_address = bp->phy_addr;
5410
5411         return 0;
5412 }
5413
5414 static int
5415 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5416 {
5417         struct bnx2 *bp = netdev_priv(dev);
5418         u8 autoneg = bp->autoneg;
5419         u8 req_duplex = bp->req_duplex;
5420         u16 req_line_speed = bp->req_line_speed;
5421         u32 advertising = bp->advertising;
5422         int err = -EINVAL;
5423
5424         spin_lock_bh(&bp->phy_lock);
5425
5426         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
5427                 goto err_out_unlock;
5428
5429         if (cmd->port != bp->phy_port && !(bp->phy_flags & REMOTE_PHY_CAP_FLAG))
5430                 goto err_out_unlock;
5431
5432         if (cmd->autoneg == AUTONEG_ENABLE) {
5433                 autoneg |= AUTONEG_SPEED;
5434
5435                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
5436
5437                 /* allow advertising 1 speed */
5438                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
5439                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
5440                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
5441                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
5442
5443                         if (cmd->port == PORT_FIBRE)
5444                                 goto err_out_unlock;
5445
5446                         advertising = cmd->advertising;
5447
5448                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
5449                         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ||
5450                             (cmd->port == PORT_TP))
5451                                 goto err_out_unlock;
5452                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
5453                         advertising = cmd->advertising;
5454                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
5455                         goto err_out_unlock;
5456                 else {
5457                         if (cmd->port == PORT_FIBRE)
5458                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
5459                         else
5460                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
5461                 }
5462                 advertising |= ADVERTISED_Autoneg;
5463         }
5464         else {
5465                 if (cmd->port == PORT_FIBRE) {
5466                         if ((cmd->speed != SPEED_1000 &&
5467                              cmd->speed != SPEED_2500) ||
5468                             (cmd->duplex != DUPLEX_FULL))
5469                                 goto err_out_unlock;
5470
5471                         if (cmd->speed == SPEED_2500 &&
5472                             !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
5473                                 goto err_out_unlock;
5474                 }
5475                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
5476                         goto err_out_unlock;
5477
5478                 autoneg &= ~AUTONEG_SPEED;
5479                 req_line_speed = cmd->speed;
5480                 req_duplex = cmd->duplex;
5481                 advertising = 0;
5482         }
5483
5484         bp->autoneg = autoneg;
5485         bp->advertising = advertising;
5486         bp->req_line_speed = req_line_speed;
5487         bp->req_duplex = req_duplex;
5488
5489         err = bnx2_setup_phy(bp, cmd->port);
5490
5491 err_out_unlock:
5492         spin_unlock_bh(&bp->phy_lock);
5493
5494         return err;
5495 }
5496
5497 static void
5498 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
5499 {
5500         struct bnx2 *bp = netdev_priv(dev);
5501
5502         strcpy(info->driver, DRV_MODULE_NAME);
5503         strcpy(info->version, DRV_MODULE_VERSION);
5504         strcpy(info->bus_info, pci_name(bp->pdev));
5505         strcpy(info->fw_version, bp->fw_version);
5506 }
5507
5508 #define BNX2_REGDUMP_LEN                (32 * 1024)
5509
5510 static int
5511 bnx2_get_regs_len(struct net_device *dev)
5512 {
5513         return BNX2_REGDUMP_LEN;
5514 }
5515
5516 static void
5517 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
5518 {
5519         u32 *p = _p, i, offset;
5520         u8 *orig_p = _p;
5521         struct bnx2 *bp = netdev_priv(dev);
5522         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
5523                                  0x0800, 0x0880, 0x0c00, 0x0c10,
5524                                  0x0c30, 0x0d08, 0x1000, 0x101c,
5525                                  0x1040, 0x1048, 0x1080, 0x10a4,
5526                                  0x1400, 0x1490, 0x1498, 0x14f0,
5527                                  0x1500, 0x155c, 0x1580, 0x15dc,
5528                                  0x1600, 0x1658, 0x1680, 0x16d8,
5529                                  0x1800, 0x1820, 0x1840, 0x1854,
5530                                  0x1880, 0x1894, 0x1900, 0x1984,
5531                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
5532                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
5533                                  0x2000, 0x2030, 0x23c0, 0x2400,
5534                                  0x2800, 0x2820, 0x2830, 0x2850,
5535                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
5536                                  0x3c00, 0x3c94, 0x4000, 0x4010,
5537                                  0x4080, 0x4090, 0x43c0, 0x4458,
5538                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
5539                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
5540                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
5541                                  0x5fc0, 0x6000, 0x6400, 0x6428,
5542                                  0x6800, 0x6848, 0x684c, 0x6860,
5543                                  0x6888, 0x6910, 0x8000 };
5544
5545         regs->version = 0;
5546
5547         memset(p, 0, BNX2_REGDUMP_LEN);
5548
5549         if (!netif_running(bp->dev))
5550                 return;
5551
5552         i = 0;
5553         offset = reg_boundaries[0];
5554         p += offset;
5555         while (offset < BNX2_REGDUMP_LEN) {
5556                 *p++ = REG_RD(bp, offset);
5557                 offset += 4;
5558                 if (offset == reg_boundaries[i + 1]) {
5559                         offset = reg_boundaries[i + 2];
5560                         p = (u32 *) (orig_p + offset);
5561                         i += 2;
5562                 }
5563         }
5564 }
5565
5566 static void
5567 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5568 {
5569         struct bnx2 *bp = netdev_priv(dev);
5570
5571         if (bp->flags & NO_WOL_FLAG) {
5572                 wol->supported = 0;
5573                 wol->wolopts = 0;
5574         }
5575         else {
5576                 wol->supported = WAKE_MAGIC;
5577                 if (bp->wol)
5578                         wol->wolopts = WAKE_MAGIC;
5579                 else
5580                         wol->wolopts = 0;
5581         }
5582         memset(&wol->sopass, 0, sizeof(wol->sopass));
5583 }
5584
5585 static int
5586 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5587 {
5588         struct bnx2 *bp = netdev_priv(dev);
5589
5590         if (wol->wolopts & ~WAKE_MAGIC)
5591                 return -EINVAL;
5592
5593         if (wol->wolopts & WAKE_MAGIC) {
5594                 if (bp->flags & NO_WOL_FLAG)
5595                         return -EINVAL;
5596
5597                 bp->wol = 1;
5598         }
5599         else {
5600                 bp->wol = 0;
5601         }
5602         return 0;
5603 }
5604
5605 static int
5606 bnx2_nway_reset(struct net_device *dev)
5607 {
5608         struct bnx2 *bp = netdev_priv(dev);
5609         u32 bmcr;
5610
5611         if (!(bp->autoneg & AUTONEG_SPEED)) {
5612                 return -EINVAL;
5613         }
5614
5615         spin_lock_bh(&bp->phy_lock);
5616
5617         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5618                 int rc;
5619
5620                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
5621                 spin_unlock_bh(&bp->phy_lock);
5622                 return rc;
5623         }
5624
5625         /* Force a link down visible on the other side */
5626         if (bp->phy_flags & PHY_SERDES_FLAG) {
5627                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
5628                 spin_unlock_bh(&bp->phy_lock);
5629
5630                 msleep(20);
5631
5632                 spin_lock_bh(&bp->phy_lock);
5633
5634                 bp->current_interval = SERDES_AN_TIMEOUT;
5635                 bp->serdes_an_pending = 1;
5636                 mod_timer(&bp->timer, jiffies + bp->current_interval);
5637         }
5638
5639         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5640         bmcr &= ~BMCR_LOOPBACK;
5641         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
5642
5643         spin_unlock_bh(&bp->phy_lock);
5644
5645         return 0;
5646 }
5647
5648 static int
5649 bnx2_get_eeprom_len(struct net_device *dev)
5650 {
5651         struct bnx2 *bp = netdev_priv(dev);
5652
5653         if (bp->flash_info == NULL)
5654                 return 0;
5655
5656         return (int) bp->flash_size;
5657 }
5658
5659 static int
5660 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5661                 u8 *eebuf)
5662 {
5663         struct bnx2 *bp = netdev_priv(dev);
5664         int rc;
5665
5666         /* parameters already validated in ethtool_get_eeprom */
5667
5668         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
5669
5670         return rc;
5671 }
5672
5673 static int
5674 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5675                 u8 *eebuf)
5676 {
5677         struct bnx2 *bp = netdev_priv(dev);
5678         int rc;
5679
5680         /* parameters already validated in ethtool_set_eeprom */
5681
5682         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
5683
5684         return rc;
5685 }
5686
5687 static int
5688 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5689 {
5690         struct bnx2 *bp = netdev_priv(dev);
5691
5692         memset(coal, 0, sizeof(struct ethtool_coalesce));
5693
5694         coal->rx_coalesce_usecs = bp->rx_ticks;
5695         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
5696         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
5697         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
5698
5699         coal->tx_coalesce_usecs = bp->tx_ticks;
5700         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
5701         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
5702         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
5703
5704         coal->stats_block_coalesce_usecs = bp->stats_ticks;
5705
5706         return 0;
5707 }
5708
5709 static int
5710 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5711 {
5712         struct bnx2 *bp = netdev_priv(dev);
5713
5714         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
5715         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
5716
5717         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
5718         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
5719
5720         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
5721         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
5722
5723         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
5724         if (bp->rx_quick_cons_trip_int > 0xff)
5725                 bp->rx_quick_cons_trip_int = 0xff;
5726
5727         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
5728         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
5729
5730         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
5731         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
5732
5733         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
5734         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
5735
5736         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
5737         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
5738                 0xff;
5739
5740         bp->stats_ticks = coal->stats_block_coalesce_usecs;
5741         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5742                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
5743                         bp->stats_ticks = USEC_PER_SEC;
5744         }
5745         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
5746                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
5747         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
5748
5749         if (netif_running(bp->dev)) {
5750                 bnx2_netif_stop(bp);
5751                 bnx2_init_nic(bp);
5752                 bnx2_netif_start(bp);
5753         }
5754
5755         return 0;
5756 }
5757
5758 static void
5759 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5760 {
5761         struct bnx2 *bp = netdev_priv(dev);
5762
5763         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
5764         ering->rx_mini_max_pending = 0;
5765         ering->rx_jumbo_max_pending = 0;
5766
5767         ering->rx_pending = bp->rx_ring_size;
5768         ering->rx_mini_pending = 0;
5769         ering->rx_jumbo_pending = 0;
5770
5771         ering->tx_max_pending = MAX_TX_DESC_CNT;
5772         ering->tx_pending = bp->tx_ring_size;
5773 }
5774
5775 static int
5776 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5777 {
5778         struct bnx2 *bp = netdev_priv(dev);
5779
5780         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5781                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5782                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5783
5784                 return -EINVAL;
5785         }
5786         if (netif_running(bp->dev)) {
5787                 bnx2_netif_stop(bp);
5788                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5789                 bnx2_free_skbs(bp);
5790                 bnx2_free_mem(bp);
5791         }
5792
5793         bnx2_set_rx_ring_size(bp, ering->rx_pending);
5794         bp->tx_ring_size = ering->tx_pending;
5795
5796         if (netif_running(bp->dev)) {
5797                 int rc;
5798
5799                 rc = bnx2_alloc_mem(bp);
5800                 if (rc)
5801                         return rc;
5802                 bnx2_init_nic(bp);
5803                 bnx2_netif_start(bp);
5804         }
5805
5806         return 0;
5807 }
5808
5809 static void
5810 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5811 {
5812         struct bnx2 *bp = netdev_priv(dev);
5813
5814         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5815         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5816         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5817 }
5818
5819 static int
5820 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5821 {
5822         struct bnx2 *bp = netdev_priv(dev);
5823
5824         bp->req_flow_ctrl = 0;
5825         if (epause->rx_pause)
5826                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5827         if (epause->tx_pause)
5828                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5829
5830         if (epause->autoneg) {
5831                 bp->autoneg |= AUTONEG_FLOW_CTRL;
5832         }
5833         else {
5834                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5835         }
5836
5837         spin_lock_bh(&bp->phy_lock);
5838
5839         bnx2_setup_phy(bp, bp->phy_port);
5840
5841         spin_unlock_bh(&bp->phy_lock);
5842
5843         return 0;
5844 }
5845
5846 static u32
5847 bnx2_get_rx_csum(struct net_device *dev)
5848 {
5849         struct bnx2 *bp = netdev_priv(dev);
5850
5851         return bp->rx_csum;
5852 }
5853
5854 static int
5855 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5856 {
5857         struct bnx2 *bp = netdev_priv(dev);
5858
5859         bp->rx_csum = data;
5860         return 0;
5861 }
5862
5863 static int
5864 bnx2_set_tso(struct net_device *dev, u32 data)
5865 {
5866         struct bnx2 *bp = netdev_priv(dev);
5867
5868         if (data) {
5869                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5870                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5871                         dev->features |= NETIF_F_TSO6;
5872         } else
5873                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
5874                                    NETIF_F_TSO_ECN);
5875         return 0;
5876 }
5877
5878 #define BNX2_NUM_STATS 46
5879
5880 static struct {
5881         char string[ETH_GSTRING_LEN];
5882 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5883         { "rx_bytes" },
5884         { "rx_error_bytes" },
5885         { "tx_bytes" },
5886         { "tx_error_bytes" },
5887         { "rx_ucast_packets" },
5888         { "rx_mcast_packets" },
5889         { "rx_bcast_packets" },
5890         { "tx_ucast_packets" },
5891         { "tx_mcast_packets" },
5892         { "tx_bcast_packets" },
5893         { "tx_mac_errors" },
5894         { "tx_carrier_errors" },
5895         { "rx_crc_errors" },
5896         { "rx_align_errors" },
5897         { "tx_single_collisions" },
5898         { "tx_multi_collisions" },
5899         { "tx_deferred" },
5900         { "tx_excess_collisions" },
5901         { "tx_late_collisions" },
5902         { "tx_total_collisions" },
5903         { "rx_fragments" },
5904         { "rx_jabbers" },
5905         { "rx_undersize_packets" },
5906         { "rx_oversize_packets" },
5907         { "rx_64_byte_packets" },
5908         { "rx_65_to_127_byte_packets" },
5909         { "rx_128_to_255_byte_packets" },
5910         { "rx_256_to_511_byte_packets" },
5911         { "rx_512_to_1023_byte_packets" },
5912         { "rx_1024_to_1522_byte_packets" },
5913         { "rx_1523_to_9022_byte_packets" },
5914         { "tx_64_byte_packets" },
5915         { "tx_65_to_127_byte_packets" },
5916         { "tx_128_to_255_byte_packets" },
5917         { "tx_256_to_511_byte_packets" },
5918         { "tx_512_to_1023_byte_packets" },
5919         { "tx_1024_to_1522_byte_packets" },
5920         { "tx_1523_to_9022_byte_packets" },
5921         { "rx_xon_frames" },
5922         { "rx_xoff_frames" },
5923         { "tx_xon_frames" },
5924         { "tx_xoff_frames" },
5925         { "rx_mac_ctrl_frames" },
5926         { "rx_filtered_packets" },
5927         { "rx_discards" },
5928         { "rx_fw_discards" },
5929 };
5930
5931 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5932
5933 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5934     STATS_OFFSET32(stat_IfHCInOctets_hi),
5935     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5936     STATS_OFFSET32(stat_IfHCOutOctets_hi),
5937     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5938     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5939     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5940     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5941     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5942     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5943     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5944     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5945     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5946     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5947     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5948     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5949     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5950     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5951     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5952     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5953     STATS_OFFSET32(stat_EtherStatsCollisions),
5954     STATS_OFFSET32(stat_EtherStatsFragments),
5955     STATS_OFFSET32(stat_EtherStatsJabbers),
5956     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5957     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5958     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5959     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5960     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5961     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5962     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5963     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5964     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5965     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5966     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5967     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5968     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5969     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5970     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5971     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5972     STATS_OFFSET32(stat_XonPauseFramesReceived),
5973     STATS_OFFSET32(stat_XoffPauseFramesReceived),
5974     STATS_OFFSET32(stat_OutXonSent),
5975     STATS_OFFSET32(stat_OutXoffSent),
5976     STATS_OFFSET32(stat_MacControlFramesReceived),
5977     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5978     STATS_OFFSET32(stat_IfInMBUFDiscards),
5979     STATS_OFFSET32(stat_FwRxDrop),
5980 };
5981
5982 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5983  * skipped because of errata.
5984  */
5985 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5986         8,0,8,8,8,8,8,8,8,8,
5987         4,0,4,4,4,4,4,4,4,4,
5988         4,4,4,4,4,4,4,4,4,4,
5989         4,4,4,4,4,4,4,4,4,4,
5990         4,4,4,4,4,4,
5991 };
5992
5993 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5994         8,0,8,8,8,8,8,8,8,8,
5995         4,4,4,4,4,4,4,4,4,4,
5996         4,4,4,4,4,4,4,4,4,4,
5997         4,4,4,4,4,4,4,4,4,4,
5998         4,4,4,4,4,4,
5999 };
6000
6001 #define BNX2_NUM_TESTS 6
6002
6003 static struct {
6004         char string[ETH_GSTRING_LEN];
6005 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6006         { "register_test (offline)" },
6007         { "memory_test (offline)" },
6008         { "loopback_test (offline)" },
6009         { "nvram_test (online)" },
6010         { "interrupt_test (online)" },
6011         { "link_test (online)" },
6012 };
6013
6014 static int
6015 bnx2_get_sset_count(struct net_device *dev, int sset)
6016 {
6017         switch (sset) {
6018         case ETH_SS_TEST:
6019                 return BNX2_NUM_TESTS;
6020         case ETH_SS_STATS:
6021                 return BNX2_NUM_STATS;
6022         default:
6023                 return -EOPNOTSUPP;
6024         }
6025 }
6026
6027 static void
6028 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6029 {
6030         struct bnx2 *bp = netdev_priv(dev);
6031
6032         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6033         if (etest->flags & ETH_TEST_FL_OFFLINE) {
6034                 int i;
6035
6036                 bnx2_netif_stop(bp);
6037                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6038                 bnx2_free_skbs(bp);
6039
6040                 if (bnx2_test_registers(bp) != 0) {
6041                         buf[0] = 1;
6042                         etest->flags |= ETH_TEST_FL_FAILED;
6043                 }
6044                 if (bnx2_test_memory(bp) != 0) {
6045                         buf[1] = 1;
6046                         etest->flags |= ETH_TEST_FL_FAILED;
6047                 }
6048                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6049                         etest->flags |= ETH_TEST_FL_FAILED;
6050
6051                 if (!netif_running(bp->dev)) {
6052                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6053                 }
6054                 else {
6055                         bnx2_init_nic(bp);
6056                         bnx2_netif_start(bp);
6057                 }
6058
6059                 /* wait for link up */
6060                 for (i = 0; i < 7; i++) {
6061                         if (bp->link_up)
6062                                 break;
6063                         msleep_interruptible(1000);
6064                 }
6065         }
6066
6067         if (bnx2_test_nvram(bp) != 0) {
6068                 buf[3] = 1;
6069                 etest->flags |= ETH_TEST_FL_FAILED;
6070         }
6071         if (bnx2_test_intr(bp) != 0) {
6072                 buf[4] = 1;
6073                 etest->flags |= ETH_TEST_FL_FAILED;
6074         }
6075
6076         if (bnx2_test_link(bp) != 0) {
6077                 buf[5] = 1;
6078                 etest->flags |= ETH_TEST_FL_FAILED;
6079
6080         }
6081 }
6082
6083 static void
6084 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6085 {
6086         switch (stringset) {
6087         case ETH_SS_STATS:
6088                 memcpy(buf, bnx2_stats_str_arr,
6089                         sizeof(bnx2_stats_str_arr));
6090                 break;
6091         case ETH_SS_TEST:
6092                 memcpy(buf, bnx2_tests_str_arr,
6093                         sizeof(bnx2_tests_str_arr));
6094                 break;
6095         }
6096 }
6097
6098 static void
6099 bnx2_get_ethtool_stats(struct net_device *dev,
6100                 struct ethtool_stats *stats, u64 *buf)
6101 {
6102         struct bnx2 *bp = netdev_priv(dev);
6103         int i;
6104         u32 *hw_stats = (u32 *) bp->stats_blk;
6105         u8 *stats_len_arr = NULL;
6106
6107         if (hw_stats == NULL) {
6108                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6109                 return;
6110         }
6111
6112         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6113             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6114             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6115             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6116                 stats_len_arr = bnx2_5706_stats_len_arr;
6117         else
6118                 stats_len_arr = bnx2_5708_stats_len_arr;
6119
6120         for (i = 0; i < BNX2_NUM_STATS; i++) {
6121                 if (stats_len_arr[i] == 0) {
6122                         /* skip this counter */
6123                         buf[i] = 0;
6124                         continue;
6125                 }
6126                 if (stats_len_arr[i] == 4) {
6127                         /* 4-byte counter */
6128                         buf[i] = (u64)
6129