dma-mapping: replace all DMA_64BIT_MASK macro with DMA_BIT_MASK(64)
[linux-2.6.git] / drivers / net / bnx2.c
1 /* bnx2.c: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004-2009 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
40 #define BCM_VLAN 1
41 #endif
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/firmware.h>
50 #include <linux/log2.h>
51
52 #include "bnx2.h"
53 #include "bnx2_fw.h"
54
55 #define DRV_MODULE_NAME         "bnx2"
56 #define PFX DRV_MODULE_NAME     ": "
57 #define DRV_MODULE_VERSION      "2.0.0"
58 #define DRV_MODULE_RELDATE      "April 2, 2009"
59 #define FW_MIPS_FILE_06         "bnx2/bnx2-mips-06-4.6.16.fw"
60 #define FW_RV2P_FILE_06         "bnx2/bnx2-rv2p-06-4.6.16.fw"
61 #define FW_MIPS_FILE_09         "bnx2/bnx2-mips-09-4.6.17.fw"
62 #define FW_RV2P_FILE_09         "bnx2/bnx2-rv2p-09-4.6.15.fw"
63
64 #define RUN_AT(x) (jiffies + (x))
65
66 /* Time in jiffies before concluding the transmitter is hung. */
67 #define TX_TIMEOUT  (5*HZ)
68
69 static char version[] __devinitdata =
70         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
71
72 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
73 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
74 MODULE_LICENSE("GPL");
75 MODULE_VERSION(DRV_MODULE_VERSION);
76 MODULE_FIRMWARE(FW_MIPS_FILE_06);
77 MODULE_FIRMWARE(FW_RV2P_FILE_06);
78 MODULE_FIRMWARE(FW_MIPS_FILE_09);
79 MODULE_FIRMWARE(FW_RV2P_FILE_09);
80
81 static int disable_msi = 0;
82
83 module_param(disable_msi, int, 0);
84 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
85
86 typedef enum {
87         BCM5706 = 0,
88         NC370T,
89         NC370I,
90         BCM5706S,
91         NC370F,
92         BCM5708,
93         BCM5708S,
94         BCM5709,
95         BCM5709S,
96         BCM5716,
97         BCM5716S,
98 } board_t;
99
100 /* indexed by board_t, above */
101 static struct {
102         char *name;
103 } board_info[] __devinitdata = {
104         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
105         { "HP NC370T Multifunction Gigabit Server Adapter" },
106         { "HP NC370i Multifunction Gigabit Server Adapter" },
107         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
108         { "HP NC370F Multifunction Gigabit Server Adapter" },
109         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
110         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
111         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
112         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
113         { "Broadcom NetXtreme II BCM5716 1000Base-T" },
114         { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
115         };
116
117 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
118         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
119           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
120         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
121           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
122         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
123           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
124         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
125           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
126         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
127           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
128         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
129           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
130         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
131           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
132         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
133           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
134         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
135           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
136         { PCI_VENDOR_ID_BROADCOM, 0x163b,
137           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
138         { PCI_VENDOR_ID_BROADCOM, 0x163c,
139           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
140         { 0, }
141 };
142
143 static struct flash_spec flash_table[] =
144 {
145 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
146 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
147         /* Slow EEPROM */
148         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
149          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
150          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
151          "EEPROM - slow"},
152         /* Expansion entry 0001 */
153         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
154          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
155          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
156          "Entry 0001"},
157         /* Saifun SA25F010 (non-buffered flash) */
158         /* strap, cfg1, & write1 need updates */
159         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
160          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
161          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
162          "Non-buffered flash (128kB)"},
163         /* Saifun SA25F020 (non-buffered flash) */
164         /* strap, cfg1, & write1 need updates */
165         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
166          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
167          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
168          "Non-buffered flash (256kB)"},
169         /* Expansion entry 0100 */
170         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
171          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
172          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
173          "Entry 0100"},
174         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
175         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
176          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
177          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
178          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
179         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
180         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
181          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
182          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
183          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
184         /* Saifun SA25F005 (non-buffered flash) */
185         /* strap, cfg1, & write1 need updates */
186         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
187          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
188          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
189          "Non-buffered flash (64kB)"},
190         /* Fast EEPROM */
191         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
192          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
193          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
194          "EEPROM - fast"},
195         /* Expansion entry 1001 */
196         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
197          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
198          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
199          "Entry 1001"},
200         /* Expansion entry 1010 */
201         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
202          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
203          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
204          "Entry 1010"},
205         /* ATMEL AT45DB011B (buffered flash) */
206         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
207          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
208          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
209          "Buffered flash (128kB)"},
210         /* Expansion entry 1100 */
211         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
212          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
213          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
214          "Entry 1100"},
215         /* Expansion entry 1101 */
216         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
217          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
218          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
219          "Entry 1101"},
220         /* Ateml Expansion entry 1110 */
221         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
222          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
223          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
224          "Entry 1110 (Atmel)"},
225         /* ATMEL AT45DB021B (buffered flash) */
226         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
227          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
228          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
229          "Buffered flash (256kB)"},
230 };
231
232 static struct flash_spec flash_5709 = {
233         .flags          = BNX2_NV_BUFFERED,
234         .page_bits      = BCM5709_FLASH_PAGE_BITS,
235         .page_size      = BCM5709_FLASH_PAGE_SIZE,
236         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
237         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
238         .name           = "5709 Buffered flash (256kB)",
239 };
240
241 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
242
243 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
244 {
245         u32 diff;
246
247         smp_mb();
248
249         /* The ring uses 256 indices for 255 entries, one of them
250          * needs to be skipped.
251          */
252         diff = txr->tx_prod - txr->tx_cons;
253         if (unlikely(diff >= TX_DESC_CNT)) {
254                 diff &= 0xffff;
255                 if (diff == TX_DESC_CNT)
256                         diff = MAX_TX_DESC_CNT;
257         }
258         return (bp->tx_ring_size - diff);
259 }
260
261 static u32
262 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
263 {
264         u32 val;
265
266         spin_lock_bh(&bp->indirect_lock);
267         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
268         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
269         spin_unlock_bh(&bp->indirect_lock);
270         return val;
271 }
272
273 static void
274 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
275 {
276         spin_lock_bh(&bp->indirect_lock);
277         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
278         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
279         spin_unlock_bh(&bp->indirect_lock);
280 }
281
282 static void
283 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
284 {
285         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
286 }
287
288 static u32
289 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
290 {
291         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
292 }
293
294 static void
295 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
296 {
297         offset += cid_addr;
298         spin_lock_bh(&bp->indirect_lock);
299         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
300                 int i;
301
302                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
303                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
304                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
305                 for (i = 0; i < 5; i++) {
306                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
307                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
308                                 break;
309                         udelay(5);
310                 }
311         } else {
312                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
313                 REG_WR(bp, BNX2_CTX_DATA, val);
314         }
315         spin_unlock_bh(&bp->indirect_lock);
316 }
317
318 static int
319 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
320 {
321         u32 val1;
322         int i, ret;
323
324         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
325                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
326                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
327
328                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
329                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
330
331                 udelay(40);
332         }
333
334         val1 = (bp->phy_addr << 21) | (reg << 16) |
335                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
336                 BNX2_EMAC_MDIO_COMM_START_BUSY;
337         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
338
339         for (i = 0; i < 50; i++) {
340                 udelay(10);
341
342                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
343                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
344                         udelay(5);
345
346                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
347                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
348
349                         break;
350                 }
351         }
352
353         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
354                 *val = 0x0;
355                 ret = -EBUSY;
356         }
357         else {
358                 *val = val1;
359                 ret = 0;
360         }
361
362         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
363                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
364                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
365
366                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
367                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
368
369                 udelay(40);
370         }
371
372         return ret;
373 }
374
375 static int
376 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
377 {
378         u32 val1;
379         int i, ret;
380
381         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
382                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
383                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
384
385                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
386                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
387
388                 udelay(40);
389         }
390
391         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
392                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
393                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
394         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
395
396         for (i = 0; i < 50; i++) {
397                 udelay(10);
398
399                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
400                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
401                         udelay(5);
402                         break;
403                 }
404         }
405
406         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
407                 ret = -EBUSY;
408         else
409                 ret = 0;
410
411         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
412                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
413                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
414
415                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
416                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
417
418                 udelay(40);
419         }
420
421         return ret;
422 }
423
424 static void
425 bnx2_disable_int(struct bnx2 *bp)
426 {
427         int i;
428         struct bnx2_napi *bnapi;
429
430         for (i = 0; i < bp->irq_nvecs; i++) {
431                 bnapi = &bp->bnx2_napi[i];
432                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
433                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
434         }
435         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
436 }
437
438 static void
439 bnx2_enable_int(struct bnx2 *bp)
440 {
441         int i;
442         struct bnx2_napi *bnapi;
443
444         for (i = 0; i < bp->irq_nvecs; i++) {
445                 bnapi = &bp->bnx2_napi[i];
446
447                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
448                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
449                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
450                        bnapi->last_status_idx);
451
452                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
453                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
454                        bnapi->last_status_idx);
455         }
456         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
457 }
458
459 static void
460 bnx2_disable_int_sync(struct bnx2 *bp)
461 {
462         int i;
463
464         atomic_inc(&bp->intr_sem);
465         bnx2_disable_int(bp);
466         for (i = 0; i < bp->irq_nvecs; i++)
467                 synchronize_irq(bp->irq_tbl[i].vector);
468 }
469
470 static void
471 bnx2_napi_disable(struct bnx2 *bp)
472 {
473         int i;
474
475         for (i = 0; i < bp->irq_nvecs; i++)
476                 napi_disable(&bp->bnx2_napi[i].napi);
477 }
478
479 static void
480 bnx2_napi_enable(struct bnx2 *bp)
481 {
482         int i;
483
484         for (i = 0; i < bp->irq_nvecs; i++)
485                 napi_enable(&bp->bnx2_napi[i].napi);
486 }
487
488 static void
489 bnx2_netif_stop(struct bnx2 *bp)
490 {
491         bnx2_disable_int_sync(bp);
492         if (netif_running(bp->dev)) {
493                 bnx2_napi_disable(bp);
494                 netif_tx_disable(bp->dev);
495                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
496         }
497 }
498
499 static void
500 bnx2_netif_start(struct bnx2 *bp)
501 {
502         if (atomic_dec_and_test(&bp->intr_sem)) {
503                 if (netif_running(bp->dev)) {
504                         netif_tx_wake_all_queues(bp->dev);
505                         bnx2_napi_enable(bp);
506                         bnx2_enable_int(bp);
507                 }
508         }
509 }
510
511 static void
512 bnx2_free_tx_mem(struct bnx2 *bp)
513 {
514         int i;
515
516         for (i = 0; i < bp->num_tx_rings; i++) {
517                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
518                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
519
520                 if (txr->tx_desc_ring) {
521                         pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
522                                             txr->tx_desc_ring,
523                                             txr->tx_desc_mapping);
524                         txr->tx_desc_ring = NULL;
525                 }
526                 kfree(txr->tx_buf_ring);
527                 txr->tx_buf_ring = NULL;
528         }
529 }
530
531 static void
532 bnx2_free_rx_mem(struct bnx2 *bp)
533 {
534         int i;
535
536         for (i = 0; i < bp->num_rx_rings; i++) {
537                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
538                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
539                 int j;
540
541                 for (j = 0; j < bp->rx_max_ring; j++) {
542                         if (rxr->rx_desc_ring[j])
543                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
544                                                     rxr->rx_desc_ring[j],
545                                                     rxr->rx_desc_mapping[j]);
546                         rxr->rx_desc_ring[j] = NULL;
547                 }
548                 if (rxr->rx_buf_ring)
549                         vfree(rxr->rx_buf_ring);
550                 rxr->rx_buf_ring = NULL;
551
552                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
553                         if (rxr->rx_pg_desc_ring[j])
554                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
555                                                     rxr->rx_pg_desc_ring[j],
556                                                     rxr->rx_pg_desc_mapping[j]);
557                         rxr->rx_pg_desc_ring[j] = NULL;
558                 }
559                 if (rxr->rx_pg_ring)
560                         vfree(rxr->rx_pg_ring);
561                 rxr->rx_pg_ring = NULL;
562         }
563 }
564
565 static int
566 bnx2_alloc_tx_mem(struct bnx2 *bp)
567 {
568         int i;
569
570         for (i = 0; i < bp->num_tx_rings; i++) {
571                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
572                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
573
574                 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
575                 if (txr->tx_buf_ring == NULL)
576                         return -ENOMEM;
577
578                 txr->tx_desc_ring =
579                         pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
580                                              &txr->tx_desc_mapping);
581                 if (txr->tx_desc_ring == NULL)
582                         return -ENOMEM;
583         }
584         return 0;
585 }
586
587 static int
588 bnx2_alloc_rx_mem(struct bnx2 *bp)
589 {
590         int i;
591
592         for (i = 0; i < bp->num_rx_rings; i++) {
593                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
594                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
595                 int j;
596
597                 rxr->rx_buf_ring =
598                         vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
599                 if (rxr->rx_buf_ring == NULL)
600                         return -ENOMEM;
601
602                 memset(rxr->rx_buf_ring, 0,
603                        SW_RXBD_RING_SIZE * bp->rx_max_ring);
604
605                 for (j = 0; j < bp->rx_max_ring; j++) {
606                         rxr->rx_desc_ring[j] =
607                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
608                                                      &rxr->rx_desc_mapping[j]);
609                         if (rxr->rx_desc_ring[j] == NULL)
610                                 return -ENOMEM;
611
612                 }
613
614                 if (bp->rx_pg_ring_size) {
615                         rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
616                                                   bp->rx_max_pg_ring);
617                         if (rxr->rx_pg_ring == NULL)
618                                 return -ENOMEM;
619
620                         memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
621                                bp->rx_max_pg_ring);
622                 }
623
624                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
625                         rxr->rx_pg_desc_ring[j] =
626                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
627                                                 &rxr->rx_pg_desc_mapping[j]);
628                         if (rxr->rx_pg_desc_ring[j] == NULL)
629                                 return -ENOMEM;
630
631                 }
632         }
633         return 0;
634 }
635
636 static void
637 bnx2_free_mem(struct bnx2 *bp)
638 {
639         int i;
640         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
641
642         bnx2_free_tx_mem(bp);
643         bnx2_free_rx_mem(bp);
644
645         for (i = 0; i < bp->ctx_pages; i++) {
646                 if (bp->ctx_blk[i]) {
647                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
648                                             bp->ctx_blk[i],
649                                             bp->ctx_blk_mapping[i]);
650                         bp->ctx_blk[i] = NULL;
651                 }
652         }
653         if (bnapi->status_blk.msi) {
654                 pci_free_consistent(bp->pdev, bp->status_stats_size,
655                                     bnapi->status_blk.msi,
656                                     bp->status_blk_mapping);
657                 bnapi->status_blk.msi = NULL;
658                 bp->stats_blk = NULL;
659         }
660 }
661
662 static int
663 bnx2_alloc_mem(struct bnx2 *bp)
664 {
665         int i, status_blk_size, err;
666         struct bnx2_napi *bnapi;
667         void *status_blk;
668
669         /* Combine status and statistics blocks into one allocation. */
670         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
671         if (bp->flags & BNX2_FLAG_MSIX_CAP)
672                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
673                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
674         bp->status_stats_size = status_blk_size +
675                                 sizeof(struct statistics_block);
676
677         status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
678                                           &bp->status_blk_mapping);
679         if (status_blk == NULL)
680                 goto alloc_mem_err;
681
682         memset(status_blk, 0, bp->status_stats_size);
683
684         bnapi = &bp->bnx2_napi[0];
685         bnapi->status_blk.msi = status_blk;
686         bnapi->hw_tx_cons_ptr =
687                 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
688         bnapi->hw_rx_cons_ptr =
689                 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
690         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
691                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
692                         struct status_block_msix *sblk;
693
694                         bnapi = &bp->bnx2_napi[i];
695
696                         sblk = (void *) (status_blk +
697                                          BNX2_SBLK_MSIX_ALIGN_SIZE * i);
698                         bnapi->status_blk.msix = sblk;
699                         bnapi->hw_tx_cons_ptr =
700                                 &sblk->status_tx_quick_consumer_index;
701                         bnapi->hw_rx_cons_ptr =
702                                 &sblk->status_rx_quick_consumer_index;
703                         bnapi->int_num = i << 24;
704                 }
705         }
706
707         bp->stats_blk = status_blk + status_blk_size;
708
709         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
710
711         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
712                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
713                 if (bp->ctx_pages == 0)
714                         bp->ctx_pages = 1;
715                 for (i = 0; i < bp->ctx_pages; i++) {
716                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
717                                                 BCM_PAGE_SIZE,
718                                                 &bp->ctx_blk_mapping[i]);
719                         if (bp->ctx_blk[i] == NULL)
720                                 goto alloc_mem_err;
721                 }
722         }
723
724         err = bnx2_alloc_rx_mem(bp);
725         if (err)
726                 goto alloc_mem_err;
727
728         err = bnx2_alloc_tx_mem(bp);
729         if (err)
730                 goto alloc_mem_err;
731
732         return 0;
733
734 alloc_mem_err:
735         bnx2_free_mem(bp);
736         return -ENOMEM;
737 }
738
739 static void
740 bnx2_report_fw_link(struct bnx2 *bp)
741 {
742         u32 fw_link_status = 0;
743
744         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
745                 return;
746
747         if (bp->link_up) {
748                 u32 bmsr;
749
750                 switch (bp->line_speed) {
751                 case SPEED_10:
752                         if (bp->duplex == DUPLEX_HALF)
753                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
754                         else
755                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
756                         break;
757                 case SPEED_100:
758                         if (bp->duplex == DUPLEX_HALF)
759                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
760                         else
761                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
762                         break;
763                 case SPEED_1000:
764                         if (bp->duplex == DUPLEX_HALF)
765                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
766                         else
767                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
768                         break;
769                 case SPEED_2500:
770                         if (bp->duplex == DUPLEX_HALF)
771                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
772                         else
773                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
774                         break;
775                 }
776
777                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
778
779                 if (bp->autoneg) {
780                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
781
782                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
783                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
784
785                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
786                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
787                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
788                         else
789                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
790                 }
791         }
792         else
793                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
794
795         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
796 }
797
798 static char *
799 bnx2_xceiver_str(struct bnx2 *bp)
800 {
801         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
802                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
803                  "Copper"));
804 }
805
806 static void
807 bnx2_report_link(struct bnx2 *bp)
808 {
809         if (bp->link_up) {
810                 netif_carrier_on(bp->dev);
811                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
812                        bnx2_xceiver_str(bp));
813
814                 printk("%d Mbps ", bp->line_speed);
815
816                 if (bp->duplex == DUPLEX_FULL)
817                         printk("full duplex");
818                 else
819                         printk("half duplex");
820
821                 if (bp->flow_ctrl) {
822                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
823                                 printk(", receive ");
824                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
825                                         printk("& transmit ");
826                         }
827                         else {
828                                 printk(", transmit ");
829                         }
830                         printk("flow control ON");
831                 }
832                 printk("\n");
833         }
834         else {
835                 netif_carrier_off(bp->dev);
836                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
837                        bnx2_xceiver_str(bp));
838         }
839
840         bnx2_report_fw_link(bp);
841 }
842
843 static void
844 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
845 {
846         u32 local_adv, remote_adv;
847
848         bp->flow_ctrl = 0;
849         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
850                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
851
852                 if (bp->duplex == DUPLEX_FULL) {
853                         bp->flow_ctrl = bp->req_flow_ctrl;
854                 }
855                 return;
856         }
857
858         if (bp->duplex != DUPLEX_FULL) {
859                 return;
860         }
861
862         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
863             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
864                 u32 val;
865
866                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
867                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
868                         bp->flow_ctrl |= FLOW_CTRL_TX;
869                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
870                         bp->flow_ctrl |= FLOW_CTRL_RX;
871                 return;
872         }
873
874         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
875         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
876
877         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
878                 u32 new_local_adv = 0;
879                 u32 new_remote_adv = 0;
880
881                 if (local_adv & ADVERTISE_1000XPAUSE)
882                         new_local_adv |= ADVERTISE_PAUSE_CAP;
883                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
884                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
885                 if (remote_adv & ADVERTISE_1000XPAUSE)
886                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
887                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
888                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
889
890                 local_adv = new_local_adv;
891                 remote_adv = new_remote_adv;
892         }
893
894         /* See Table 28B-3 of 802.3ab-1999 spec. */
895         if (local_adv & ADVERTISE_PAUSE_CAP) {
896                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
897                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
898                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
899                         }
900                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
901                                 bp->flow_ctrl = FLOW_CTRL_RX;
902                         }
903                 }
904                 else {
905                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
906                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
907                         }
908                 }
909         }
910         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
911                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
912                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
913
914                         bp->flow_ctrl = FLOW_CTRL_TX;
915                 }
916         }
917 }
918
919 static int
920 bnx2_5709s_linkup(struct bnx2 *bp)
921 {
922         u32 val, speed;
923
924         bp->link_up = 1;
925
926         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
927         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
928         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
929
930         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
931                 bp->line_speed = bp->req_line_speed;
932                 bp->duplex = bp->req_duplex;
933                 return 0;
934         }
935         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
936         switch (speed) {
937                 case MII_BNX2_GP_TOP_AN_SPEED_10:
938                         bp->line_speed = SPEED_10;
939                         break;
940                 case MII_BNX2_GP_TOP_AN_SPEED_100:
941                         bp->line_speed = SPEED_100;
942                         break;
943                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
944                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
945                         bp->line_speed = SPEED_1000;
946                         break;
947                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
948                         bp->line_speed = SPEED_2500;
949                         break;
950         }
951         if (val & MII_BNX2_GP_TOP_AN_FD)
952                 bp->duplex = DUPLEX_FULL;
953         else
954                 bp->duplex = DUPLEX_HALF;
955         return 0;
956 }
957
958 static int
959 bnx2_5708s_linkup(struct bnx2 *bp)
960 {
961         u32 val;
962
963         bp->link_up = 1;
964         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
965         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
966                 case BCM5708S_1000X_STAT1_SPEED_10:
967                         bp->line_speed = SPEED_10;
968                         break;
969                 case BCM5708S_1000X_STAT1_SPEED_100:
970                         bp->line_speed = SPEED_100;
971                         break;
972                 case BCM5708S_1000X_STAT1_SPEED_1G:
973                         bp->line_speed = SPEED_1000;
974                         break;
975                 case BCM5708S_1000X_STAT1_SPEED_2G5:
976                         bp->line_speed = SPEED_2500;
977                         break;
978         }
979         if (val & BCM5708S_1000X_STAT1_FD)
980                 bp->duplex = DUPLEX_FULL;
981         else
982                 bp->duplex = DUPLEX_HALF;
983
984         return 0;
985 }
986
987 static int
988 bnx2_5706s_linkup(struct bnx2 *bp)
989 {
990         u32 bmcr, local_adv, remote_adv, common;
991
992         bp->link_up = 1;
993         bp->line_speed = SPEED_1000;
994
995         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
996         if (bmcr & BMCR_FULLDPLX) {
997                 bp->duplex = DUPLEX_FULL;
998         }
999         else {
1000                 bp->duplex = DUPLEX_HALF;
1001         }
1002
1003         if (!(bmcr & BMCR_ANENABLE)) {
1004                 return 0;
1005         }
1006
1007         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1008         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1009
1010         common = local_adv & remote_adv;
1011         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1012
1013                 if (common & ADVERTISE_1000XFULL) {
1014                         bp->duplex = DUPLEX_FULL;
1015                 }
1016                 else {
1017                         bp->duplex = DUPLEX_HALF;
1018                 }
1019         }
1020
1021         return 0;
1022 }
1023
1024 static int
1025 bnx2_copper_linkup(struct bnx2 *bp)
1026 {
1027         u32 bmcr;
1028
1029         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1030         if (bmcr & BMCR_ANENABLE) {
1031                 u32 local_adv, remote_adv, common;
1032
1033                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1034                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1035
1036                 common = local_adv & (remote_adv >> 2);
1037                 if (common & ADVERTISE_1000FULL) {
1038                         bp->line_speed = SPEED_1000;
1039                         bp->duplex = DUPLEX_FULL;
1040                 }
1041                 else if (common & ADVERTISE_1000HALF) {
1042                         bp->line_speed = SPEED_1000;
1043                         bp->duplex = DUPLEX_HALF;
1044                 }
1045                 else {
1046                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1047                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1048
1049                         common = local_adv & remote_adv;
1050                         if (common & ADVERTISE_100FULL) {
1051                                 bp->line_speed = SPEED_100;
1052                                 bp->duplex = DUPLEX_FULL;
1053                         }
1054                         else if (common & ADVERTISE_100HALF) {
1055                                 bp->line_speed = SPEED_100;
1056                                 bp->duplex = DUPLEX_HALF;
1057                         }
1058                         else if (common & ADVERTISE_10FULL) {
1059                                 bp->line_speed = SPEED_10;
1060                                 bp->duplex = DUPLEX_FULL;
1061                         }
1062                         else if (common & ADVERTISE_10HALF) {
1063                                 bp->line_speed = SPEED_10;
1064                                 bp->duplex = DUPLEX_HALF;
1065                         }
1066                         else {
1067                                 bp->line_speed = 0;
1068                                 bp->link_up = 0;
1069                         }
1070                 }
1071         }
1072         else {
1073                 if (bmcr & BMCR_SPEED100) {
1074                         bp->line_speed = SPEED_100;
1075                 }
1076                 else {
1077                         bp->line_speed = SPEED_10;
1078                 }
1079                 if (bmcr & BMCR_FULLDPLX) {
1080                         bp->duplex = DUPLEX_FULL;
1081                 }
1082                 else {
1083                         bp->duplex = DUPLEX_HALF;
1084                 }
1085         }
1086
1087         return 0;
1088 }
1089
1090 static void
1091 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1092 {
1093         u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1094
1095         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1096         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1097         val |= 0x02 << 8;
1098
1099         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1100                 u32 lo_water, hi_water;
1101
1102                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1103                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1104                 else
1105                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1106                 if (lo_water >= bp->rx_ring_size)
1107                         lo_water = 0;
1108
1109                 hi_water = bp->rx_ring_size / 4;
1110
1111                 if (hi_water <= lo_water)
1112                         lo_water = 0;
1113
1114                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1115                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1116
1117                 if (hi_water > 0xf)
1118                         hi_water = 0xf;
1119                 else if (hi_water == 0)
1120                         lo_water = 0;
1121                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1122         }
1123         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1124 }
1125
1126 static void
1127 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1128 {
1129         int i;
1130         u32 cid;
1131
1132         for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1133                 if (i == 1)
1134                         cid = RX_RSS_CID;
1135                 bnx2_init_rx_context(bp, cid);
1136         }
1137 }
1138
1139 static void
1140 bnx2_set_mac_link(struct bnx2 *bp)
1141 {
1142         u32 val;
1143
1144         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1145         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1146                 (bp->duplex == DUPLEX_HALF)) {
1147                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1148         }
1149
1150         /* Configure the EMAC mode register. */
1151         val = REG_RD(bp, BNX2_EMAC_MODE);
1152
1153         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1154                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1155                 BNX2_EMAC_MODE_25G_MODE);
1156
1157         if (bp->link_up) {
1158                 switch (bp->line_speed) {
1159                         case SPEED_10:
1160                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1161                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1162                                         break;
1163                                 }
1164                                 /* fall through */
1165                         case SPEED_100:
1166                                 val |= BNX2_EMAC_MODE_PORT_MII;
1167                                 break;
1168                         case SPEED_2500:
1169                                 val |= BNX2_EMAC_MODE_25G_MODE;
1170                                 /* fall through */
1171                         case SPEED_1000:
1172                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1173                                 break;
1174                 }
1175         }
1176         else {
1177                 val |= BNX2_EMAC_MODE_PORT_GMII;
1178         }
1179
1180         /* Set the MAC to operate in the appropriate duplex mode. */
1181         if (bp->duplex == DUPLEX_HALF)
1182                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1183         REG_WR(bp, BNX2_EMAC_MODE, val);
1184
1185         /* Enable/disable rx PAUSE. */
1186         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1187
1188         if (bp->flow_ctrl & FLOW_CTRL_RX)
1189                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1190         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1191
1192         /* Enable/disable tx PAUSE. */
1193         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1194         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1195
1196         if (bp->flow_ctrl & FLOW_CTRL_TX)
1197                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1198         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1199
1200         /* Acknowledge the interrupt. */
1201         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1202
1203         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1204                 bnx2_init_all_rx_contexts(bp);
1205 }
1206
1207 static void
1208 bnx2_enable_bmsr1(struct bnx2 *bp)
1209 {
1210         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1211             (CHIP_NUM(bp) == CHIP_NUM_5709))
1212                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213                                MII_BNX2_BLK_ADDR_GP_STATUS);
1214 }
1215
1216 static void
1217 bnx2_disable_bmsr1(struct bnx2 *bp)
1218 {
1219         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1220             (CHIP_NUM(bp) == CHIP_NUM_5709))
1221                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1222                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1223 }
1224
1225 static int
1226 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1227 {
1228         u32 up1;
1229         int ret = 1;
1230
1231         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1232                 return 0;
1233
1234         if (bp->autoneg & AUTONEG_SPEED)
1235                 bp->advertising |= ADVERTISED_2500baseX_Full;
1236
1237         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1238                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1239
1240         bnx2_read_phy(bp, bp->mii_up1, &up1);
1241         if (!(up1 & BCM5708S_UP1_2G5)) {
1242                 up1 |= BCM5708S_UP1_2G5;
1243                 bnx2_write_phy(bp, bp->mii_up1, up1);
1244                 ret = 0;
1245         }
1246
1247         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1248                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1249                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1250
1251         return ret;
1252 }
1253
1254 static int
1255 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1256 {
1257         u32 up1;
1258         int ret = 0;
1259
1260         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1261                 return 0;
1262
1263         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1264                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1265
1266         bnx2_read_phy(bp, bp->mii_up1, &up1);
1267         if (up1 & BCM5708S_UP1_2G5) {
1268                 up1 &= ~BCM5708S_UP1_2G5;
1269                 bnx2_write_phy(bp, bp->mii_up1, up1);
1270                 ret = 1;
1271         }
1272
1273         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1274                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1275                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1276
1277         return ret;
1278 }
1279
1280 static void
1281 bnx2_enable_forced_2g5(struct bnx2 *bp)
1282 {
1283         u32 bmcr;
1284
1285         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1286                 return;
1287
1288         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1289                 u32 val;
1290
1291                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1292                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1293                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1294                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1295                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1296                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1297
1298                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1299                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1300                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1301
1302         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1303                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1304                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1305         }
1306
1307         if (bp->autoneg & AUTONEG_SPEED) {
1308                 bmcr &= ~BMCR_ANENABLE;
1309                 if (bp->req_duplex == DUPLEX_FULL)
1310                         bmcr |= BMCR_FULLDPLX;
1311         }
1312         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1313 }
1314
1315 static void
1316 bnx2_disable_forced_2g5(struct bnx2 *bp)
1317 {
1318         u32 bmcr;
1319
1320         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1321                 return;
1322
1323         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1324                 u32 val;
1325
1326                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1327                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1328                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1329                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1330                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1331
1332                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1333                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1334                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1335
1336         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1337                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1338                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1339         }
1340
1341         if (bp->autoneg & AUTONEG_SPEED)
1342                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1343         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1344 }
1345
1346 static void
1347 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1348 {
1349         u32 val;
1350
1351         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1352         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1353         if (start)
1354                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1355         else
1356                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1357 }
1358
1359 static int
1360 bnx2_set_link(struct bnx2 *bp)
1361 {
1362         u32 bmsr;
1363         u8 link_up;
1364
1365         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1366                 bp->link_up = 1;
1367                 return 0;
1368         }
1369
1370         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1371                 return 0;
1372
1373         link_up = bp->link_up;
1374
1375         bnx2_enable_bmsr1(bp);
1376         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1377         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1378         bnx2_disable_bmsr1(bp);
1379
1380         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1381             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1382                 u32 val, an_dbg;
1383
1384                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1385                         bnx2_5706s_force_link_dn(bp, 0);
1386                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1387                 }
1388                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1389
1390                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1391                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1392                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1393
1394                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1395                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1396                         bmsr |= BMSR_LSTATUS;
1397                 else
1398                         bmsr &= ~BMSR_LSTATUS;
1399         }
1400
1401         if (bmsr & BMSR_LSTATUS) {
1402                 bp->link_up = 1;
1403
1404                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1405                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1406                                 bnx2_5706s_linkup(bp);
1407                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1408                                 bnx2_5708s_linkup(bp);
1409                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1410                                 bnx2_5709s_linkup(bp);
1411                 }
1412                 else {
1413                         bnx2_copper_linkup(bp);
1414                 }
1415                 bnx2_resolve_flow_ctrl(bp);
1416         }
1417         else {
1418                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1419                     (bp->autoneg & AUTONEG_SPEED))
1420                         bnx2_disable_forced_2g5(bp);
1421
1422                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1423                         u32 bmcr;
1424
1425                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1426                         bmcr |= BMCR_ANENABLE;
1427                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1428
1429                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1430                 }
1431                 bp->link_up = 0;
1432         }
1433
1434         if (bp->link_up != link_up) {
1435                 bnx2_report_link(bp);
1436         }
1437
1438         bnx2_set_mac_link(bp);
1439
1440         return 0;
1441 }
1442
1443 static int
1444 bnx2_reset_phy(struct bnx2 *bp)
1445 {
1446         int i;
1447         u32 reg;
1448
1449         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1450
1451 #define PHY_RESET_MAX_WAIT 100
1452         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1453                 udelay(10);
1454
1455                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1456                 if (!(reg & BMCR_RESET)) {
1457                         udelay(20);
1458                         break;
1459                 }
1460         }
1461         if (i == PHY_RESET_MAX_WAIT) {
1462                 return -EBUSY;
1463         }
1464         return 0;
1465 }
1466
1467 static u32
1468 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1469 {
1470         u32 adv = 0;
1471
1472         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1473                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1474
1475                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1476                         adv = ADVERTISE_1000XPAUSE;
1477                 }
1478                 else {
1479                         adv = ADVERTISE_PAUSE_CAP;
1480                 }
1481         }
1482         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1483                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1484                         adv = ADVERTISE_1000XPSE_ASYM;
1485                 }
1486                 else {
1487                         adv = ADVERTISE_PAUSE_ASYM;
1488                 }
1489         }
1490         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1491                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1492                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1493                 }
1494                 else {
1495                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1496                 }
1497         }
1498         return adv;
1499 }
1500
1501 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1502
1503 static int
1504 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1505 __releases(&bp->phy_lock)
1506 __acquires(&bp->phy_lock)
1507 {
1508         u32 speed_arg = 0, pause_adv;
1509
1510         pause_adv = bnx2_phy_get_pause_adv(bp);
1511
1512         if (bp->autoneg & AUTONEG_SPEED) {
1513                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1514                 if (bp->advertising & ADVERTISED_10baseT_Half)
1515                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1516                 if (bp->advertising & ADVERTISED_10baseT_Full)
1517                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1518                 if (bp->advertising & ADVERTISED_100baseT_Half)
1519                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1520                 if (bp->advertising & ADVERTISED_100baseT_Full)
1521                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1522                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1523                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1524                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1525                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1526         } else {
1527                 if (bp->req_line_speed == SPEED_2500)
1528                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1529                 else if (bp->req_line_speed == SPEED_1000)
1530                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1531                 else if (bp->req_line_speed == SPEED_100) {
1532                         if (bp->req_duplex == DUPLEX_FULL)
1533                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1534                         else
1535                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1536                 } else if (bp->req_line_speed == SPEED_10) {
1537                         if (bp->req_duplex == DUPLEX_FULL)
1538                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1539                         else
1540                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1541                 }
1542         }
1543
1544         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1545                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1546         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1547                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1548
1549         if (port == PORT_TP)
1550                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1551                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1552
1553         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1554
1555         spin_unlock_bh(&bp->phy_lock);
1556         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1557         spin_lock_bh(&bp->phy_lock);
1558
1559         return 0;
1560 }
1561
1562 static int
1563 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1564 __releases(&bp->phy_lock)
1565 __acquires(&bp->phy_lock)
1566 {
1567         u32 adv, bmcr;
1568         u32 new_adv = 0;
1569
1570         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1571                 return (bnx2_setup_remote_phy(bp, port));
1572
1573         if (!(bp->autoneg & AUTONEG_SPEED)) {
1574                 u32 new_bmcr;
1575                 int force_link_down = 0;
1576
1577                 if (bp->req_line_speed == SPEED_2500) {
1578                         if (!bnx2_test_and_enable_2g5(bp))
1579                                 force_link_down = 1;
1580                 } else if (bp->req_line_speed == SPEED_1000) {
1581                         if (bnx2_test_and_disable_2g5(bp))
1582                                 force_link_down = 1;
1583                 }
1584                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1585                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1586
1587                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1588                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1589                 new_bmcr |= BMCR_SPEED1000;
1590
1591                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1592                         if (bp->req_line_speed == SPEED_2500)
1593                                 bnx2_enable_forced_2g5(bp);
1594                         else if (bp->req_line_speed == SPEED_1000) {
1595                                 bnx2_disable_forced_2g5(bp);
1596                                 new_bmcr &= ~0x2000;
1597                         }
1598
1599                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1600                         if (bp->req_line_speed == SPEED_2500)
1601                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1602                         else
1603                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1604                 }
1605
1606                 if (bp->req_duplex == DUPLEX_FULL) {
1607                         adv |= ADVERTISE_1000XFULL;
1608                         new_bmcr |= BMCR_FULLDPLX;
1609                 }
1610                 else {
1611                         adv |= ADVERTISE_1000XHALF;
1612                         new_bmcr &= ~BMCR_FULLDPLX;
1613                 }
1614                 if ((new_bmcr != bmcr) || (force_link_down)) {
1615                         /* Force a link down visible on the other side */
1616                         if (bp->link_up) {
1617                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1618                                                ~(ADVERTISE_1000XFULL |
1619                                                  ADVERTISE_1000XHALF));
1620                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1621                                         BMCR_ANRESTART | BMCR_ANENABLE);
1622
1623                                 bp->link_up = 0;
1624                                 netif_carrier_off(bp->dev);
1625                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1626                                 bnx2_report_link(bp);
1627                         }
1628                         bnx2_write_phy(bp, bp->mii_adv, adv);
1629                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1630                 } else {
1631                         bnx2_resolve_flow_ctrl(bp);
1632                         bnx2_set_mac_link(bp);
1633                 }
1634                 return 0;
1635         }
1636
1637         bnx2_test_and_enable_2g5(bp);
1638
1639         if (bp->advertising & ADVERTISED_1000baseT_Full)
1640                 new_adv |= ADVERTISE_1000XFULL;
1641
1642         new_adv |= bnx2_phy_get_pause_adv(bp);
1643
1644         bnx2_read_phy(bp, bp->mii_adv, &adv);
1645         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1646
1647         bp->serdes_an_pending = 0;
1648         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1649                 /* Force a link down visible on the other side */
1650                 if (bp->link_up) {
1651                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1652                         spin_unlock_bh(&bp->phy_lock);
1653                         msleep(20);
1654                         spin_lock_bh(&bp->phy_lock);
1655                 }
1656
1657                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1658                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1659                         BMCR_ANENABLE);
1660                 /* Speed up link-up time when the link partner
1661                  * does not autonegotiate which is very common
1662                  * in blade servers. Some blade servers use
1663                  * IPMI for kerboard input and it's important
1664                  * to minimize link disruptions. Autoneg. involves
1665                  * exchanging base pages plus 3 next pages and
1666                  * normally completes in about 120 msec.
1667                  */
1668                 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1669                 bp->serdes_an_pending = 1;
1670                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1671         } else {
1672                 bnx2_resolve_flow_ctrl(bp);
1673                 bnx2_set_mac_link(bp);
1674         }
1675
1676         return 0;
1677 }
1678
1679 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1680         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1681                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1682                 (ADVERTISED_1000baseT_Full)
1683
1684 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1685         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1686         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1687         ADVERTISED_1000baseT_Full)
1688
1689 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1690         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1691
1692 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1693
1694 static void
1695 bnx2_set_default_remote_link(struct bnx2 *bp)
1696 {
1697         u32 link;
1698
1699         if (bp->phy_port == PORT_TP)
1700                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1701         else
1702                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1703
1704         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1705                 bp->req_line_speed = 0;
1706                 bp->autoneg |= AUTONEG_SPEED;
1707                 bp->advertising = ADVERTISED_Autoneg;
1708                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1709                         bp->advertising |= ADVERTISED_10baseT_Half;
1710                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1711                         bp->advertising |= ADVERTISED_10baseT_Full;
1712                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1713                         bp->advertising |= ADVERTISED_100baseT_Half;
1714                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1715                         bp->advertising |= ADVERTISED_100baseT_Full;
1716                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1717                         bp->advertising |= ADVERTISED_1000baseT_Full;
1718                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1719                         bp->advertising |= ADVERTISED_2500baseX_Full;
1720         } else {
1721                 bp->autoneg = 0;
1722                 bp->advertising = 0;
1723                 bp->req_duplex = DUPLEX_FULL;
1724                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1725                         bp->req_line_speed = SPEED_10;
1726                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1727                                 bp->req_duplex = DUPLEX_HALF;
1728                 }
1729                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1730                         bp->req_line_speed = SPEED_100;
1731                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1732                                 bp->req_duplex = DUPLEX_HALF;
1733                 }
1734                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1735                         bp->req_line_speed = SPEED_1000;
1736                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1737                         bp->req_line_speed = SPEED_2500;
1738         }
1739 }
1740
1741 static void
1742 bnx2_set_default_link(struct bnx2 *bp)
1743 {
1744         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1745                 bnx2_set_default_remote_link(bp);
1746                 return;
1747         }
1748
1749         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1750         bp->req_line_speed = 0;
1751         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1752                 u32 reg;
1753
1754                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1755
1756                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1757                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1758                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1759                         bp->autoneg = 0;
1760                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1761                         bp->req_duplex = DUPLEX_FULL;
1762                 }
1763         } else
1764                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1765 }
1766
1767 static void
1768 bnx2_send_heart_beat(struct bnx2 *bp)
1769 {
1770         u32 msg;
1771         u32 addr;
1772
1773         spin_lock(&bp->indirect_lock);
1774         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1775         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1776         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1777         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1778         spin_unlock(&bp->indirect_lock);
1779 }
1780
1781 static void
1782 bnx2_remote_phy_event(struct bnx2 *bp)
1783 {
1784         u32 msg;
1785         u8 link_up = bp->link_up;
1786         u8 old_port;
1787
1788         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1789
1790         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1791                 bnx2_send_heart_beat(bp);
1792
1793         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1794
1795         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1796                 bp->link_up = 0;
1797         else {
1798                 u32 speed;
1799
1800                 bp->link_up = 1;
1801                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1802                 bp->duplex = DUPLEX_FULL;
1803                 switch (speed) {
1804                         case BNX2_LINK_STATUS_10HALF:
1805                                 bp->duplex = DUPLEX_HALF;
1806                         case BNX2_LINK_STATUS_10FULL:
1807                                 bp->line_speed = SPEED_10;
1808                                 break;
1809                         case BNX2_LINK_STATUS_100HALF:
1810                                 bp->duplex = DUPLEX_HALF;
1811                         case BNX2_LINK_STATUS_100BASE_T4:
1812                         case BNX2_LINK_STATUS_100FULL:
1813                                 bp->line_speed = SPEED_100;
1814                                 break;
1815                         case BNX2_LINK_STATUS_1000HALF:
1816                                 bp->duplex = DUPLEX_HALF;
1817                         case BNX2_LINK_STATUS_1000FULL:
1818                                 bp->line_speed = SPEED_1000;
1819                                 break;
1820                         case BNX2_LINK_STATUS_2500HALF:
1821                                 bp->duplex = DUPLEX_HALF;
1822                         case BNX2_LINK_STATUS_2500FULL:
1823                                 bp->line_speed = SPEED_2500;
1824                                 break;
1825                         default:
1826                                 bp->line_speed = 0;
1827                                 break;
1828                 }
1829
1830                 bp->flow_ctrl = 0;
1831                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1832                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1833                         if (bp->duplex == DUPLEX_FULL)
1834                                 bp->flow_ctrl = bp->req_flow_ctrl;
1835                 } else {
1836                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1837                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1838                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1839                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1840                 }
1841
1842                 old_port = bp->phy_port;
1843                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1844                         bp->phy_port = PORT_FIBRE;
1845                 else
1846                         bp->phy_port = PORT_TP;
1847
1848                 if (old_port != bp->phy_port)
1849                         bnx2_set_default_link(bp);
1850
1851         }
1852         if (bp->link_up != link_up)
1853                 bnx2_report_link(bp);
1854
1855         bnx2_set_mac_link(bp);
1856 }
1857
1858 static int
1859 bnx2_set_remote_link(struct bnx2 *bp)
1860 {
1861         u32 evt_code;
1862
1863         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1864         switch (evt_code) {
1865                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1866                         bnx2_remote_phy_event(bp);
1867                         break;
1868                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1869                 default:
1870                         bnx2_send_heart_beat(bp);
1871                         break;
1872         }
1873         return 0;
1874 }
1875
1876 static int
1877 bnx2_setup_copper_phy(struct bnx2 *bp)
1878 __releases(&bp->phy_lock)
1879 __acquires(&bp->phy_lock)
1880 {
1881         u32 bmcr;
1882         u32 new_bmcr;
1883
1884         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1885
1886         if (bp->autoneg & AUTONEG_SPEED) {
1887                 u32 adv_reg, adv1000_reg;
1888                 u32 new_adv_reg = 0;
1889                 u32 new_adv1000_reg = 0;
1890
1891                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1892                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1893                         ADVERTISE_PAUSE_ASYM);
1894
1895                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1896                 adv1000_reg &= PHY_ALL_1000_SPEED;
1897
1898                 if (bp->advertising & ADVERTISED_10baseT_Half)
1899                         new_adv_reg |= ADVERTISE_10HALF;
1900                 if (bp->advertising & ADVERTISED_10baseT_Full)
1901                         new_adv_reg |= ADVERTISE_10FULL;
1902                 if (bp->advertising & ADVERTISED_100baseT_Half)
1903                         new_adv_reg |= ADVERTISE_100HALF;
1904                 if (bp->advertising & ADVERTISED_100baseT_Full)
1905                         new_adv_reg |= ADVERTISE_100FULL;
1906                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1907                         new_adv1000_reg |= ADVERTISE_1000FULL;
1908
1909                 new_adv_reg |= ADVERTISE_CSMA;
1910
1911                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1912
1913                 if ((adv1000_reg != new_adv1000_reg) ||
1914                         (adv_reg != new_adv_reg) ||
1915                         ((bmcr & BMCR_ANENABLE) == 0)) {
1916
1917                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1918                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1919                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1920                                 BMCR_ANENABLE);
1921                 }
1922                 else if (bp->link_up) {
1923                         /* Flow ctrl may have changed from auto to forced */
1924                         /* or vice-versa. */
1925
1926                         bnx2_resolve_flow_ctrl(bp);
1927                         bnx2_set_mac_link(bp);
1928                 }
1929                 return 0;
1930         }
1931
1932         new_bmcr = 0;
1933         if (bp->req_line_speed == SPEED_100) {
1934                 new_bmcr |= BMCR_SPEED100;
1935         }
1936         if (bp->req_duplex == DUPLEX_FULL) {
1937                 new_bmcr |= BMCR_FULLDPLX;
1938         }
1939         if (new_bmcr != bmcr) {
1940                 u32 bmsr;
1941
1942                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1943                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1944
1945                 if (bmsr & BMSR_LSTATUS) {
1946                         /* Force link down */
1947                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1948                         spin_unlock_bh(&bp->phy_lock);
1949                         msleep(50);
1950                         spin_lock_bh(&bp->phy_lock);
1951
1952                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1953                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1954                 }
1955
1956                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1957
1958                 /* Normally, the new speed is setup after the link has
1959                  * gone down and up again. In some cases, link will not go
1960                  * down so we need to set up the new speed here.
1961                  */
1962                 if (bmsr & BMSR_LSTATUS) {
1963                         bp->line_speed = bp->req_line_speed;
1964                         bp->duplex = bp->req_duplex;
1965                         bnx2_resolve_flow_ctrl(bp);
1966                         bnx2_set_mac_link(bp);
1967                 }
1968         } else {
1969                 bnx2_resolve_flow_ctrl(bp);
1970                 bnx2_set_mac_link(bp);
1971         }
1972         return 0;
1973 }
1974
1975 static int
1976 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1977 __releases(&bp->phy_lock)
1978 __acquires(&bp->phy_lock)
1979 {
1980         if (bp->loopback == MAC_LOOPBACK)
1981                 return 0;
1982
1983         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1984                 return (bnx2_setup_serdes_phy(bp, port));
1985         }
1986         else {
1987                 return (bnx2_setup_copper_phy(bp));
1988         }
1989 }
1990
1991 static int
1992 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1993 {
1994         u32 val;
1995
1996         bp->mii_bmcr = MII_BMCR + 0x10;
1997         bp->mii_bmsr = MII_BMSR + 0x10;
1998         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1999         bp->mii_adv = MII_ADVERTISE + 0x10;
2000         bp->mii_lpa = MII_LPA + 0x10;
2001         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2002
2003         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2004         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2005
2006         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2007         if (reset_phy)
2008                 bnx2_reset_phy(bp);
2009
2010         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2011
2012         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2013         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2014         val |= MII_BNX2_SD_1000XCTL1_FIBER;
2015         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2016
2017         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2018         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2019         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2020                 val |= BCM5708S_UP1_2G5;
2021         else
2022                 val &= ~BCM5708S_UP1_2G5;
2023         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2024
2025         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2026         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2027         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2028         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2029
2030         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2031
2032         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2033               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2034         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2035
2036         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2037
2038         return 0;
2039 }
2040
2041 static int
2042 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2043 {
2044         u32 val;
2045
2046         if (reset_phy)
2047                 bnx2_reset_phy(bp);
2048
2049         bp->mii_up1 = BCM5708S_UP1;
2050
2051         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2052         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2053         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2054
2055         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2056         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2057         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2058
2059         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2060         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2061         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2062
2063         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2064                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2065                 val |= BCM5708S_UP1_2G5;
2066                 bnx2_write_phy(bp, BCM5708S_UP1, val);
2067         }
2068
2069         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2070             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2071             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2072                 /* increase tx signal amplitude */
2073                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2074                                BCM5708S_BLK_ADDR_TX_MISC);
2075                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2076                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2077                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2078                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2079         }
2080
2081         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2082               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2083
2084         if (val) {
2085                 u32 is_backplane;
2086
2087                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2088                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2089                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2090                                        BCM5708S_BLK_ADDR_TX_MISC);
2091                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2092                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2093                                        BCM5708S_BLK_ADDR_DIG);
2094                 }
2095         }
2096         return 0;
2097 }
2098
2099 static int
2100 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2101 {
2102         if (reset_phy)
2103                 bnx2_reset_phy(bp);
2104
2105         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2106
2107         if (CHIP_NUM(bp) == CHIP_NUM_5706)
2108                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2109
2110         if (bp->dev->mtu > 1500) {
2111                 u32 val;
2112
2113                 /* Set extended packet length bit */
2114                 bnx2_write_phy(bp, 0x18, 0x7);
2115                 bnx2_read_phy(bp, 0x18, &val);
2116                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2117
2118                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2119                 bnx2_read_phy(bp, 0x1c, &val);
2120                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2121         }
2122         else {
2123                 u32 val;
2124
2125                 bnx2_write_phy(bp, 0x18, 0x7);
2126                 bnx2_read_phy(bp, 0x18, &val);
2127                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2128
2129                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2130                 bnx2_read_phy(bp, 0x1c, &val);
2131                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2132         }
2133
2134         return 0;
2135 }
2136
2137 static int
2138 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2139 {
2140         u32 val;
2141
2142         if (reset_phy)
2143                 bnx2_reset_phy(bp);
2144
2145         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2146                 bnx2_write_phy(bp, 0x18, 0x0c00);
2147                 bnx2_write_phy(bp, 0x17, 0x000a);
2148                 bnx2_write_phy(bp, 0x15, 0x310b);
2149                 bnx2_write_phy(bp, 0x17, 0x201f);
2150                 bnx2_write_phy(bp, 0x15, 0x9506);
2151                 bnx2_write_phy(bp, 0x17, 0x401f);
2152                 bnx2_write_phy(bp, 0x15, 0x14e2);
2153                 bnx2_write_phy(bp, 0x18, 0x0400);
2154         }
2155
2156         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2157                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2158                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2159                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2160                 val &= ~(1 << 8);
2161                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2162         }
2163
2164         if (bp->dev->mtu > 1500) {
2165                 /* Set extended packet length bit */
2166                 bnx2_write_phy(bp, 0x18, 0x7);
2167                 bnx2_read_phy(bp, 0x18, &val);
2168                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2169
2170                 bnx2_read_phy(bp, 0x10, &val);
2171                 bnx2_write_phy(bp, 0x10, val | 0x1);
2172         }
2173         else {
2174                 bnx2_write_phy(bp, 0x18, 0x7);
2175                 bnx2_read_phy(bp, 0x18, &val);
2176                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2177
2178                 bnx2_read_phy(bp, 0x10, &val);
2179                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2180         }
2181
2182         /* ethernet@wirespeed */
2183         bnx2_write_phy(bp, 0x18, 0x7007);
2184         bnx2_read_phy(bp, 0x18, &val);
2185         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2186         return 0;
2187 }
2188
2189
2190 static int
2191 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2192 __releases(&bp->phy_lock)
2193 __acquires(&bp->phy_lock)
2194 {
2195         u32 val;
2196         int rc = 0;
2197
2198         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2199         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2200
2201         bp->mii_bmcr = MII_BMCR;
2202         bp->mii_bmsr = MII_BMSR;
2203         bp->mii_bmsr1 = MII_BMSR;
2204         bp->mii_adv = MII_ADVERTISE;
2205         bp->mii_lpa = MII_LPA;
2206
2207         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2208
2209         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2210                 goto setup_phy;
2211
2212         bnx2_read_phy(bp, MII_PHYSID1, &val);
2213         bp->phy_id = val << 16;
2214         bnx2_read_phy(bp, MII_PHYSID2, &val);
2215         bp->phy_id |= val & 0xffff;
2216
2217         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2218                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2219                         rc = bnx2_init_5706s_phy(bp, reset_phy);
2220                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2221                         rc = bnx2_init_5708s_phy(bp, reset_phy);
2222                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2223                         rc = bnx2_init_5709s_phy(bp, reset_phy);
2224         }
2225         else {
2226                 rc = bnx2_init_copper_phy(bp, reset_phy);
2227         }
2228
2229 setup_phy:
2230         if (!rc)
2231                 rc = bnx2_setup_phy(bp, bp->phy_port);
2232
2233         return rc;
2234 }
2235
2236 static int
2237 bnx2_set_mac_loopback(struct bnx2 *bp)
2238 {
2239         u32 mac_mode;
2240
2241         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2242         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2243         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2244         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2245         bp->link_up = 1;
2246         return 0;
2247 }
2248
2249 static int bnx2_test_link(struct bnx2 *);
2250
2251 static int
2252 bnx2_set_phy_loopback(struct bnx2 *bp)
2253 {
2254         u32 mac_mode;
2255         int rc, i;
2256
2257         spin_lock_bh(&bp->phy_lock);
2258         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2259                             BMCR_SPEED1000);
2260         spin_unlock_bh(&bp->phy_lock);
2261         if (rc)
2262                 return rc;
2263
2264         for (i = 0; i < 10; i++) {
2265                 if (bnx2_test_link(bp) == 0)
2266                         break;
2267                 msleep(100);
2268         }
2269
2270         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2271         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2272                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2273                       BNX2_EMAC_MODE_25G_MODE);
2274
2275         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2276         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2277         bp->link_up = 1;
2278         return 0;
2279 }
2280
2281 static int
2282 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2283 {
2284         int i;
2285         u32 val;
2286
2287         bp->fw_wr_seq++;
2288         msg_data |= bp->fw_wr_seq;
2289
2290         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2291
2292         if (!ack)
2293                 return 0;
2294
2295         /* wait for an acknowledgement. */
2296         for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2297                 msleep(10);
2298
2299                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2300
2301                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2302                         break;
2303         }
2304         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2305                 return 0;
2306
2307         /* If we timed out, inform the firmware that this is the case. */
2308         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2309                 if (!silent)
2310                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2311                                             "%x\n", msg_data);
2312
2313                 msg_data &= ~BNX2_DRV_MSG_CODE;
2314                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2315
2316                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2317
2318                 return -EBUSY;
2319         }
2320
2321         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2322                 return -EIO;
2323
2324         return 0;
2325 }
2326
2327 static int
2328 bnx2_init_5709_context(struct bnx2 *bp)
2329 {
2330         int i, ret = 0;
2331         u32 val;
2332
2333         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2334         val |= (BCM_PAGE_BITS - 8) << 16;
2335         REG_WR(bp, BNX2_CTX_COMMAND, val);
2336         for (i = 0; i < 10; i++) {
2337                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2338                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2339                         break;
2340                 udelay(2);
2341         }
2342         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2343                 return -EBUSY;
2344
2345         for (i = 0; i < bp->ctx_pages; i++) {
2346                 int j;
2347
2348                 if (bp->ctx_blk[i])
2349                         memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2350                 else
2351                         return -ENOMEM;
2352
2353                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2354                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2355                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2356                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2357                        (u64) bp->ctx_blk_mapping[i] >> 32);
2358                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2359                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2360                 for (j = 0; j < 10; j++) {
2361
2362                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2363                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2364                                 break;
2365                         udelay(5);
2366                 }
2367                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2368                         ret = -EBUSY;
2369                         break;
2370                 }
2371         }
2372         return ret;
2373 }
2374
2375 static void
2376 bnx2_init_context(struct bnx2 *bp)
2377 {
2378         u32 vcid;
2379
2380         vcid = 96;
2381         while (vcid) {
2382                 u32 vcid_addr, pcid_addr, offset;
2383                 int i;
2384
2385                 vcid--;
2386
2387                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2388                         u32 new_vcid;
2389
2390                         vcid_addr = GET_PCID_ADDR(vcid);
2391                         if (vcid & 0x8) {
2392                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2393                         }
2394                         else {
2395                                 new_vcid = vcid;
2396                         }
2397                         pcid_addr = GET_PCID_ADDR(new_vcid);
2398                 }
2399                 else {
2400                         vcid_addr = GET_CID_ADDR(vcid);
2401                         pcid_addr = vcid_addr;
2402                 }
2403
2404                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2405                         vcid_addr += (i << PHY_CTX_SHIFT);
2406                         pcid_addr += (i << PHY_CTX_SHIFT);
2407
2408                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2409                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2410
2411                         /* Zero out the context. */
2412                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2413                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2414                 }
2415         }
2416 }
2417
2418 static int
2419 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2420 {
2421         u16 *good_mbuf;
2422         u32 good_mbuf_cnt;
2423         u32 val;
2424
2425         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2426         if (good_mbuf == NULL) {
2427                 printk(KERN_ERR PFX "Failed to allocate memory in "
2428                                     "bnx2_alloc_bad_rbuf\n");
2429                 return -ENOMEM;
2430         }
2431
2432         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2433                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2434
2435         good_mbuf_cnt = 0;
2436
2437         /* Allocate a bunch of mbufs and save the good ones in an array. */
2438         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2439         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2440                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2441                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2442
2443                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2444
2445                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2446
2447                 /* The addresses with Bit 9 set are bad memory blocks. */
2448                 if (!(val & (1 << 9))) {
2449                         good_mbuf[good_mbuf_cnt] = (u16) val;
2450                         good_mbuf_cnt++;
2451                 }
2452
2453                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2454         }
2455
2456         /* Free the good ones back to the mbuf pool thus discarding
2457          * all the bad ones. */
2458         while (good_mbuf_cnt) {
2459                 good_mbuf_cnt--;
2460
2461                 val = good_mbuf[good_mbuf_cnt];
2462                 val = (val << 9) | val | 1;
2463
2464                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2465         }
2466         kfree(good_mbuf);
2467         return 0;
2468 }
2469
2470 static void
2471 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2472 {
2473         u32 val;
2474
2475         val = (mac_addr[0] << 8) | mac_addr[1];
2476
2477         REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2478
2479         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2480                 (mac_addr[4] << 8) | mac_addr[5];
2481
2482         REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2483 }
2484
2485 static inline int
2486 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2487 {
2488         dma_addr_t mapping;
2489         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2490         struct rx_bd *rxbd =
2491                 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2492         struct page *page = alloc_page(GFP_ATOMIC);
2493
2494         if (!page)
2495                 return -ENOMEM;
2496         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2497                                PCI_DMA_FROMDEVICE);
2498         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2499                 __free_page(page);
2500                 return -EIO;
2501         }
2502
2503         rx_pg->page = page;
2504         pci_unmap_addr_set(rx_pg, mapping, mapping);
2505         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2506         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2507         return 0;
2508 }
2509
2510 static void
2511 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2512 {
2513         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2514         struct page *page = rx_pg->page;
2515
2516         if (!page)
2517                 return;
2518
2519         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2520                        PCI_DMA_FROMDEVICE);
2521
2522         __free_page(page);
2523         rx_pg->page = NULL;
2524 }
2525
2526 static inline int
2527 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2528 {
2529         struct sk_buff *skb;
2530         struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2531         dma_addr_t mapping;
2532         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2533         unsigned long align;
2534
2535         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2536         if (skb == NULL) {
2537                 return -ENOMEM;
2538         }
2539
2540         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2541                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2542
2543         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2544                 PCI_DMA_FROMDEVICE);
2545         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2546                 dev_kfree_skb(skb);
2547                 return -EIO;
2548         }
2549
2550         rx_buf->skb = skb;
2551         pci_unmap_addr_set(rx_buf, mapping, mapping);
2552
2553         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2554         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2555
2556         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2557
2558         return 0;
2559 }
2560
2561 static int
2562 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2563 {
2564         struct status_block *sblk = bnapi->status_blk.msi;
2565         u32 new_link_state, old_link_state;
2566         int is_set = 1;
2567
2568         new_link_state = sblk->status_attn_bits & event;
2569         old_link_state = sblk->status_attn_bits_ack & event;
2570         if (new_link_state != old_link_state) {
2571                 if (new_link_state)
2572                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2573                 else
2574                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2575         } else
2576                 is_set = 0;
2577
2578         return is_set;
2579 }
2580
2581 static void
2582 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2583 {
2584         spin_lock(&bp->phy_lock);
2585
2586         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2587                 bnx2_set_link(bp);
2588         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2589                 bnx2_set_remote_link(bp);
2590
2591         spin_unlock(&bp->phy_lock);
2592
2593 }
2594
2595 static inline u16
2596 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2597 {
2598         u16 cons;
2599
2600         /* Tell compiler that status block fields can change. */
2601         barrier();
2602         cons = *bnapi->hw_tx_cons_ptr;
2603         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2604                 cons++;
2605         return cons;
2606 }
2607
2608 static int
2609 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2610 {
2611         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2612         u16 hw_cons, sw_cons, sw_ring_cons;
2613         int tx_pkt = 0, index;
2614         struct netdev_queue *txq;
2615
2616         index = (bnapi - bp->bnx2_napi);
2617         txq = netdev_get_tx_queue(bp->dev, index);
2618
2619         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2620         sw_cons = txr->tx_cons;
2621
2622         while (sw_cons != hw_cons) {
2623                 struct sw_tx_bd *tx_buf;
2624                 struct sk_buff *skb;
2625                 int i, last;
2626
2627                 sw_ring_cons = TX_RING_IDX(sw_cons);
2628
2629                 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2630                 skb = tx_buf->skb;
2631
2632                 /* partial BD completions possible with TSO packets */
2633                 if (skb_is_gso(skb)) {
2634                         u16 last_idx, last_ring_idx;
2635
2636                         last_idx = sw_cons +
2637                                 skb_shinfo(skb)->nr_frags + 1;
2638                         last_ring_idx = sw_ring_cons +
2639                                 skb_shinfo(skb)->nr_frags + 1;
2640                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2641                                 last_idx++;
2642                         }
2643                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2644                                 break;
2645                         }
2646                 }
2647
2648                 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2649
2650                 tx_buf->skb = NULL;
2651                 last = skb_shinfo(skb)->nr_frags;
2652
2653                 for (i = 0; i < last; i++) {
2654                         sw_cons = NEXT_TX_BD(sw_cons);
2655                 }
2656
2657                 sw_cons = NEXT_TX_BD(sw_cons);
2658
2659                 dev_kfree_skb(skb);
2660                 tx_pkt++;
2661                 if (tx_pkt == budget)
2662                         break;
2663
2664                 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2665         }
2666
2667         txr->hw_tx_cons = hw_cons;
2668         txr->tx_cons = sw_cons;
2669
2670         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2671          * before checking for netif_tx_queue_stopped().  Without the
2672          * memory barrier, there is a small possibility that bnx2_start_xmit()
2673          * will miss it and cause the queue to be stopped forever.
2674          */
2675         smp_mb();
2676
2677         if (unlikely(netif_tx_queue_stopped(txq)) &&
2678                      (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2679                 __netif_tx_lock(txq, smp_processor_id());
2680                 if ((netif_tx_queue_stopped(txq)) &&
2681                     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2682                         netif_tx_wake_queue(txq);
2683                 __netif_tx_unlock(txq);
2684         }
2685
2686         return tx_pkt;
2687 }
2688
2689 static void
2690 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2691                         struct sk_buff *skb, int count)
2692 {
2693         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2694         struct rx_bd *cons_bd, *prod_bd;
2695         int i;
2696         u16 hw_prod, prod;
2697         u16 cons = rxr->rx_pg_cons;
2698
2699         cons_rx_pg = &rxr->rx_pg_ring[cons];
2700
2701         /* The caller was unable to allocate a new page to replace the
2702          * last one in the frags array, so we need to recycle that page
2703          * and then free the skb.
2704          */
2705         if (skb) {
2706                 struct page *page;
2707                 struct skb_shared_info *shinfo;
2708
2709                 shinfo = skb_shinfo(skb);
2710                 shinfo->nr_frags--;
2711                 page = shinfo->frags[shinfo->nr_frags].page;
2712                 shinfo->frags[shinfo->nr_frags].page = NULL;
2713
2714                 cons_rx_pg->page = page;
2715                 dev_kfree_skb(skb);
2716         }
2717
2718         hw_prod = rxr->rx_pg_prod;
2719
2720         for (i = 0; i < count; i++) {
2721                 prod = RX_PG_RING_IDX(hw_prod);
2722
2723                 prod_rx_pg = &rxr->rx_pg_ring[prod];
2724                 cons_rx_pg = &rxr->rx_pg_ring[cons];
2725                 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2726                 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2727
2728                 if (prod != cons) {
2729                         prod_rx_pg->page = cons_rx_pg->page;
2730                         cons_rx_pg->page = NULL;
2731                         pci_unmap_addr_set(prod_rx_pg, mapping,
2732                                 pci_unmap_addr(cons_rx_pg, mapping));
2733
2734                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2735                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2736
2737                 }
2738                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2739                 hw_prod = NEXT_RX_BD(hw_prod);
2740         }
2741         rxr->rx_pg_prod = hw_prod;
2742         rxr->rx_pg_cons = cons;
2743 }
2744
2745 static inline void
2746 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2747                   struct sk_buff *skb, u16 cons, u16 prod)
2748 {
2749         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2750         struct rx_bd *cons_bd, *prod_bd;
2751
2752         cons_rx_buf = &rxr->rx_buf_ring[cons];
2753         prod_rx_buf = &rxr->rx_buf_ring[prod];
2754
2755         pci_dma_sync_single_for_device(bp->pdev,
2756                 pci_unmap_addr(cons_rx_buf, mapping),
2757                 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2758
2759         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2760
2761         prod_rx_buf->skb = skb;
2762
2763         if (cons == prod)
2764                 return;
2765
2766         pci_unmap_addr_set(prod_rx_buf, mapping,
2767                         pci_unmap_addr(cons_rx_buf, mapping));
2768
2769         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2770         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2771         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2772         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2773 }
2774
2775 static int
2776 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2777             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2778             u32 ring_idx)
2779 {
2780         int err;
2781         u16 prod = ring_idx & 0xffff;
2782
2783         err = bnx2_alloc_rx_skb(bp, rxr, prod);
2784         if (unlikely(err)) {
2785                 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2786                 if (hdr_len) {
2787                         unsigned int raw_len = len + 4;
2788                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2789
2790                         bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2791                 }
2792                 return err;
2793         }
2794
2795         skb_reserve(skb, BNX2_RX_OFFSET);
2796         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2797                          PCI_DMA_FROMDEVICE);
2798
2799         if (hdr_len == 0) {
2800                 skb_put(skb, len);
2801                 return 0;
2802         } else {
2803                 unsigned int i, frag_len, frag_size, pages;
2804                 struct sw_pg *rx_pg;
2805                 u16 pg_cons = rxr->rx_pg_cons;
2806                 u16 pg_prod = rxr->rx_pg_prod;
2807
2808                 frag_size = len + 4 - hdr_len;
2809                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2810                 skb_put(skb, hdr_len);
2811
2812                 for (i = 0; i < pages; i++) {
2813                         dma_addr_t mapping_old;
2814
2815                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2816                         if (unlikely(frag_len <= 4)) {
2817                                 unsigned int tail = 4 - frag_len;
2818
2819                                 rxr->rx_pg_cons = pg_cons;
2820                                 rxr->rx_pg_prod = pg_prod;
2821                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2822                                                         pages - i);
2823                                 skb->len -= tail;
2824                                 if (i == 0) {
2825                                         skb->tail -= tail;
2826                                 } else {
2827                                         skb_frag_t *frag =
2828                                                 &skb_shinfo(skb)->frags[i - 1];
2829                                         frag->size -= tail;
2830                                         skb->data_len -= tail;
2831                                         skb->truesize -= tail;
2832                                 }
2833                                 return 0;
2834                         }
2835                         rx_pg = &rxr->rx_pg_ring[pg_cons];
2836
2837                         /* Don't unmap yet.  If we're unable to allocate a new
2838                          * page, we need to recycle the page and the DMA addr.
2839                          */
2840                         mapping_old = pci_unmap_addr(rx_pg, mapping);
2841                         if (i == pages - 1)
2842                                 frag_len -= 4;
2843
2844                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2845                         rx_pg->page = NULL;
2846
2847                         err = bnx2_alloc_rx_page(bp, rxr,
2848                                                  RX_PG_RING_IDX(pg_prod));
2849                         if (unlikely(err)) {
2850                                 rxr->rx_pg_cons = pg_cons;
2851                                 rxr->rx_pg_prod = pg_prod;
2852                                 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2853                                                         pages - i);
2854                                 return err;
2855                         }
2856
2857                         pci_unmap_page(bp->pdev, mapping_old,
2858                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
2859
2860                         frag_size -= frag_len;
2861                         skb->data_len += frag_len;
2862                         skb->truesize += frag_len;
2863                         skb->len += frag_len;
2864
2865                         pg_prod = NEXT_RX_BD(pg_prod);
2866                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2867                 }
2868                 rxr->rx_pg_prod = pg_prod;
2869                 rxr->rx_pg_cons = pg_cons;
2870         }
2871         return 0;
2872 }
2873
2874 static inline u16
2875 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2876 {
2877         u16 cons;
2878
2879         /* Tell compiler that status block fields can change. */
2880         barrier();
2881         cons = *bnapi->hw_rx_cons_ptr;
2882         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2883                 cons++;
2884         return cons;
2885 }
2886
2887 static int
2888 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2889 {
2890         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2891         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2892         struct l2_fhdr *rx_hdr;
2893         int rx_pkt = 0, pg_ring_used = 0;
2894
2895         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2896         sw_cons = rxr->rx_cons;
2897         sw_prod = rxr->rx_prod;
2898
2899         /* Memory barrier necessary as speculative reads of the rx
2900          * buffer can be ahead of the index in the status block
2901          */
2902         rmb();
2903         while (sw_cons != hw_cons) {
2904                 unsigned int len, hdr_len;
2905                 u32 status;
2906                 struct sw_bd *rx_buf;
2907                 struct sk_buff *skb;
2908                 dma_addr_t dma_addr;
2909                 u16 vtag = 0;
2910                 int hw_vlan __maybe_unused = 0;
2911
2912                 sw_ring_cons = RX_RING_IDX(sw_cons);
2913                 sw_ring_prod = RX_RING_IDX(sw_prod);
2914
2915                 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2916                 skb = rx_buf->skb;
2917
2918                 rx_buf->skb = NULL;
2919
2920                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2921
2922                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2923                         BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2924                         PCI_DMA_FROMDEVICE);
2925
2926                 rx_hdr = (struct l2_fhdr *) skb->data;
2927                 len = rx_hdr->l2_fhdr_pkt_len;
2928                 status = rx_hdr->l2_fhdr_status;
2929
2930                 hdr_len = 0;
2931                 if (status & L2_FHDR_STATUS_SPLIT) {
2932                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2933                         pg_ring_used = 1;
2934                 } else if (len > bp->rx_jumbo_thresh) {
2935                         hdr_len = bp->rx_jumbo_thresh;
2936                         pg_ring_used = 1;
2937                 }
2938
2939                 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
2940                                        L2_FHDR_ERRORS_PHY_DECODE |
2941                                        L2_FHDR_ERRORS_ALIGNMENT |
2942                                        L2_FHDR_ERRORS_TOO_SHORT |
2943                                        L2_FHDR_ERRORS_GIANT_FRAME))) {
2944
2945                         bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2946                                           sw_ring_prod);
2947                         if (pg_ring_used) {
2948                                 int pages;
2949
2950                                 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
2951
2952                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2953                         }
2954                         goto next_rx;
2955                 }
2956
2957                 len -= 4;
2958
2959                 if (len <= bp->rx_copy_thresh) {
2960                         struct sk_buff *new_skb;
2961
2962                         new_skb = netdev_alloc_skb(bp->dev, len + 6);
2963                         if (new_skb == NULL) {
2964                                 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2965                                                   sw_ring_prod);
2966                                 goto next_rx;
2967                         }
2968
2969                         /* aligned copy */
2970                         skb_copy_from_linear_data_offset(skb,
2971                                                          BNX2_RX_OFFSET - 6,
2972                                       new_skb->data, len + 6);
2973                         skb_reserve(new_skb, 6);
2974                         skb_put(new_skb, len);
2975
2976                         bnx2_reuse_rx_skb(bp, rxr, skb,
2977                                 sw_ring_cons, sw_ring_prod);
2978
2979                         skb = new_skb;
2980                 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2981                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2982                         goto next_rx;
2983
2984                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2985                     !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2986                         vtag = rx_hdr->l2_fhdr_vlan_tag;
2987 #ifdef BCM_VLAN
2988                         if (bp->vlgrp)
2989                                 hw_vlan = 1;
2990                         else
2991 #endif
2992                         {
2993                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2994                                         __skb_push(skb, 4);
2995
2996                                 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2997                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
2998                                 ve->h_vlan_TCI = htons(vtag);
2999                                 len += 4;
3000                         }
3001                 }
3002
3003                 skb->protocol = eth_type_trans(skb, bp->dev);
3004
3005                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3006                         (ntohs(skb->protocol) != 0x8100)) {
3007
3008                         dev_kfree_skb(skb);
3009                         goto next_rx;
3010
3011                 }
3012
3013                 skb->ip_summed = CHECKSUM_NONE;
3014                 if (bp->rx_csum &&
3015                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3016                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
3017
3018                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3019                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3020                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3021                 }
3022
3023                 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3024
3025 #ifdef BCM_VLAN
3026                 if (hw_vlan)
3027                         vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3028                 else
3029 #endif
3030                         netif_receive_skb(skb);
3031
3032                 rx_pkt++;
3033
3034 next_rx:
3035                 sw_cons = NEXT_RX_BD(sw_cons);
3036                 sw_prod = NEXT_RX_BD(sw_prod);
3037
3038                 if ((rx_pkt == budget))
3039                         break;
3040
3041                 /* Refresh hw_cons to see if there is new work */
3042                 if (sw_cons == hw_cons) {
3043                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3044                         rmb();
3045                 }
3046         }
3047         rxr->rx_cons = sw_cons;
3048         rxr->rx_prod = sw_prod;
3049
3050         if (pg_ring_used)
3051                 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3052
3053         REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3054
3055         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3056
3057         mmiowb();
3058
3059         return rx_pkt;
3060
3061 }
3062
3063 /* MSI ISR - The only difference between this and the INTx ISR
3064  * is that the MSI interrupt is always serviced.
3065  */
3066 static irqreturn_t
3067 bnx2_msi(int irq, void *dev_instance)
3068 {
3069         struct bnx2_napi *bnapi = dev_instance;
3070         struct bnx2 *bp = bnapi->bp;
3071
3072         prefetch(bnapi->status_blk.msi);
3073         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3074                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3075                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3076
3077         /* Return here if interrupt is disabled. */
3078         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3079                 return IRQ_HANDLED;
3080
3081         napi_schedule(&bnapi->napi);
3082
3083         return IRQ_HANDLED;
3084 }
3085
3086 static irqreturn_t
3087 bnx2_msi_1shot(int irq, void *dev_instance)
3088 {
3089         struct bnx2_napi *bnapi = dev_instance;
3090         struct bnx2 *bp = bnapi->bp;
3091
3092         prefetch(bnapi->status_blk.msi);
3093
3094         /* Return here if interrupt is disabled. */
3095         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3096                 return IRQ_HANDLED;
3097
3098         napi_schedule(&bnapi->napi);
3099
3100         return IRQ_HANDLED;
3101 }
3102
3103 static irqreturn_t
3104 bnx2_interrupt(int irq, void *dev_instance)
3105 {
3106         struct bnx2_napi *bnapi = dev_instance;
3107         struct bnx2 *bp = bnapi->bp;
3108         struct status_block *sblk = bnapi->status_blk.msi;
3109
3110         /* When using INTx, it is possible for the interrupt to arrive
3111          * at the CPU before the status block posted prior to the
3112          * interrupt. Reading a register will flush the status block.
3113          * When using MSI, the MSI message will always complete after
3114          * the status block write.
3115          */
3116         if ((sblk->status_idx == bnapi->last_status_idx) &&
3117             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3118              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3119                 return IRQ_NONE;
3120
3121         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3122                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3123                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3124
3125         /* Read back to deassert IRQ immediately to avoid too many
3126          * spurious interrupts.
3127          */
3128         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3129
3130         /* Return here if interrupt is shared and is disabled. */
3131         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3132                 return IRQ_HANDLED;
3133
3134         if (napi_schedule_prep(&bnapi->napi)) {
3135                 bnapi->last_status_idx = sblk->status_idx;
3136                 __napi_schedule(&bnapi->napi);
3137         }
3138
3139         return IRQ_HANDLED;
3140 }
3141
3142 static inline int
3143 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3144 {
3145         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3146         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3147
3148         if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3149             (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3150                 return 1;
3151         return 0;
3152 }
3153
3154 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
3155                                  STATUS_ATTN_BITS_TIMER_ABORT)
3156
3157 static inline int
3158 bnx2_has_work(struct bnx2_napi *bnapi)
3159 {
3160         struct status_block *sblk = bnapi->status_blk.msi;
3161
3162         if (bnx2_has_fast_work(bnapi))
3163                 return 1;
3164
3165         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3166             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3167                 return 1;
3168
3169         return 0;
3170 }
3171
3172 static void
3173 bnx2_chk_missed_msi(struct bnx2 *bp)
3174 {
3175         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3176         u32 msi_ctrl;
3177
3178         if (bnx2_has_work(bnapi)) {
3179                 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3180                 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3181                         return;
3182
3183                 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3184                         REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3185                                ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3186                         REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3187                         bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3188                 }
3189         }
3190
3191         bp->idle_chk_status_idx = bnapi->last_status_idx;
3192 }
3193
3194 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3195 {
3196         struct status_block *sblk = bnapi->status_blk.msi;
3197         u32 status_attn_bits = sblk->status_attn_bits;
3198         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3199
3200         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3201             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3202
3203                 bnx2_phy_int(bp, bnapi);
3204
3205                 /* This is needed to take care of transient status
3206                  * during link changes.
3207                  */
3208                 REG_WR(bp, BNX2_HC_COMMAND,
3209                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3210                 REG_RD(bp, BNX2_HC_COMMAND);
3211         }
3212 }
3213
3214 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3215                           int work_done, int budget)
3216 {
3217         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3218         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3219
3220         if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3221                 bnx2_tx_int(bp, bnapi, 0);
3222
3223         if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3224                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3225
3226         return work_done;
3227 }
3228
3229 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3230 {
3231         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3232         struct bnx2 *bp = bnapi->bp;
3233         int work_done = 0;
3234         struct status_block_msix *sblk = bnapi->status_blk.msix;
3235
3236         while (1) {
3237                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3238                 if (unlikely(work_done >= budget))
3239                         break;
3240
3241                 bnapi->last_status_idx = sblk->status_idx;
3242                 /* status idx must be read before checking for more work. */
3243                 rmb();
3244                 if (likely(!bnx2_has_fast_work(bnapi))) {
3245
3246                         napi_complete(napi);
3247                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3248                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3249                                bnapi->last_status_idx);
3250                         break;
3251                 }
3252         }
3253         return work_done;
3254 }
3255
3256 static int bnx2_poll(struct napi_struct *napi, int budget)
3257 {
3258         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3259         struct bnx2 *bp = bnapi->bp;
3260         int work_done = 0;
3261         struct status_block *sblk = bnapi->status_blk.msi;
3262
3263         while (1) {
3264                 bnx2_poll_link(bp, bnapi);
3265
3266                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3267
3268                 /* bnapi->last_status_idx is used below to tell the hw how
3269                  * much work has been processed, so we must read it before
3270                  * checking for more work.
3271                  */
3272                 bnapi->last_status_idx = sblk->status_idx;
3273
3274                 if (unlikely(work_done >= budget))
3275                         break;
3276
3277                 rmb();
3278                 if (likely(!bnx2_has_work(bnapi))) {
3279                         napi_complete(napi);
3280                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3281                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3282                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3283                                        bnapi->last_status_idx);
3284                                 break;
3285                         }
3286                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3287                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3288                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3289                                bnapi->last_status_idx);
3290
3291                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3292                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3293                                bnapi->last_status_idx);
3294                         break;
3295                 }
3296         }
3297
3298         return work_done;
3299 }
3300
3301 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3302  * from set_multicast.
3303  */
3304 static void
3305 bnx2_set_rx_mode(struct net_device *dev)
3306 {
3307         struct bnx2 *bp = netdev_priv(dev);
3308         u32 rx_mode, sort_mode;
3309         struct dev_addr_list *uc_ptr;
3310         int i;
3311
3312         if (!netif_running(dev))
3313                 return;
3314
3315         spin_lock_bh(&bp->phy_lock);
3316
3317         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3318                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3319         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3320 #ifdef BCM_VLAN
3321         if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3322                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3323 #else
3324         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3325                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3326 #endif
3327         if (dev->flags & IFF_PROMISC) {
3328                 /* Promiscuous mode. */
3329                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3330                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3331                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3332         }
3333         else if (dev->flags & IFF_ALLMULTI) {
3334                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3335                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3336                                0xffffffff);
3337                 }
3338                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3339         }
3340         else {
3341                 /* Accept one or more multicast(s). */
3342                 struct dev_mc_list *mclist;
3343                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3344                 u32 regidx;
3345                 u32 bit;
3346                 u32 crc;
3347
3348                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3349
3350                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3351                      i++, mclist = mclist->next) {
3352
3353                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3354                         bit = crc & 0xff;
3355                         regidx = (bit & 0xe0) >> 5;
3356                         bit &= 0x1f;
3357                         mc_filter[regidx] |= (1 << bit);
3358                 }
3359
3360                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3361                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3362                                mc_filter[i]);
3363                 }
3364
3365                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3366         }
3367
3368         uc_ptr = NULL;
3369         if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3370                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3371                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3372                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3373         } else if (!(dev->flags & IFF_PROMISC)) {
3374                 uc_ptr = dev->uc_list;
3375
3376                 /* Add all entries into to the match filter list */
3377                 for (i = 0; i < dev->uc_count; i++) {
3378                         bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3379                                           i + BNX2_START_UNICAST_ADDRESS_INDEX);
3380                         sort_mode |= (1 <<
3381                                       (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3382                         uc_ptr = uc_ptr->next;
3383                 }
3384
3385         }
3386
3387         if (rx_mode != bp->rx_mode) {
3388                 bp->rx_mode = rx_mode;
3389                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3390         }
3391
3392         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3393         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3394         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3395
3396         spin_unlock_bh(&bp->phy_lock);
3397 }
3398
3399 static int __devinit
3400 check_fw_section(const struct firmware *fw,
3401                  const struct bnx2_fw_file_section *section,
3402                  u32 alignment, bool non_empty)
3403 {
3404         u32 offset = be32_to_cpu(section->offset);
3405         u32 len = be32_to_cpu(section->len);
3406
3407         if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3408                 return -EINVAL;
3409         if ((non_empty && len == 0) || len > fw->size - offset ||
3410             len & (alignment - 1))
3411                 return -EINVAL;
3412         return 0;
3413 }
3414
3415 static int __devinit
3416 check_mips_fw_entry(const struct firmware *fw,
3417                     const struct bnx2_mips_fw_file_entry *entry)
3418 {
3419         if (check_fw_section(fw, &entry->text, 4, true) ||
3420             check_fw_section(fw, &entry->data, 4, false) ||
3421             check_fw_section(fw, &entry->rodata, 4, false))
3422                 return -EINVAL;
3423         return 0;
3424 }
3425
3426 static int __devinit
3427 bnx2_request_firmware(struct bnx2 *bp)
3428 {
3429         const char *mips_fw_file, *rv2p_fw_file;
3430         const struct bnx2_mips_fw_file *mips;
3431         const struct bnx2_rv2p_fw_file *rv2p;
3432         int rc;
3433
3434         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3435                 mips_fw_file = FW_MIPS_FILE_09;
3436                 rv2p_fw_file = FW_RV2P_FILE_09;
3437         } else {
3438                 mips_fw_file = FW_MIPS_FILE_06;
3439                 rv2p_fw_file = FW_RV2P_FILE_06;
3440         }
3441
3442         rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3443         if (rc) {
3444                 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3445                        mips_fw_file);
3446                 return rc;
3447         }
3448
3449         rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3450         if (rc) {
3451                 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3452                        rv2p_fw_file);
3453                 return rc;
3454         }
3455         mips = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3456         rv2p = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3457         if (bp->mips_firmware->size < sizeof(*mips) ||
3458             check_mips_fw_entry(bp->mips_firmware, &mips->com) ||
3459             check_mips_fw_entry(bp->mips_firmware, &mips->cp) ||
3460             check_mips_fw_entry(bp->mips_firmware, &mips->rxp) ||
3461             check_mips_fw_entry(bp->mips_firmware, &mips->tpat) ||
3462             check_mips_fw_entry(bp->mips_firmware, &mips->txp)) {
3463                 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3464                        mips_fw_file);
3465                 return -EINVAL;
3466         }
3467         if (bp->rv2p_firmware->size < sizeof(*rv2p) ||
3468             check_fw_section(bp->rv2p_firmware, &rv2p->proc1.rv2p, 8, true) ||
3469             check_fw_section(bp->rv2p_firmware, &rv2p->proc2.rv2p, 8, true)) {
3470                 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3471                        rv2p_fw_file);
3472                 return -EINVAL;
3473         }
3474
3475         return 0;
3476 }
3477
3478 static u32
3479 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3480 {
3481         switch (idx) {
3482         case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3483                 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3484                 rv2p_code |= RV2P_BD_PAGE_SIZE;
3485                 break;
3486         }
3487         return rv2p_code;
3488 }
3489
3490 static int
3491 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3492              const struct bnx2_rv2p_fw_file_entry *fw_entry)
3493 {
3494         u32 rv2p_code_len, file_offset;
3495         __be32 *rv2p_code;
3496         int i;
3497         u32 val, cmd, addr;
3498
3499         rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3500         file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3501
3502         rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3503
3504         if (rv2p_proc == RV2P_PROC1) {
3505                 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3506                 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3507         } else {
3508                 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3509                 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3510         }
3511
3512         for (i = 0; i < rv2p_code_len; i += 8) {
3513                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3514                 rv2p_code++;
3515                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3516                 rv2p_code++;
3517
3518                 val = (i / 8) | cmd;
3519                 REG_WR(bp, addr, val);
3520         }
3521
3522         rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3523         for (i = 0; i < 8; i++) {
3524                 u32 loc, code;
3525
3526                 loc = be32_to_cpu(fw_entry->fixup[i]);
3527                 if (loc && ((loc * 4) < rv2p_code_len)) {
3528                         code = be32_to_cpu(*(rv2p_code + loc - 1));
3529                         REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3530                         code = be32_to_cpu(*(rv2p_code + loc));
3531                         code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3532                         REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3533
3534                         val = (loc / 2) | cmd;
3535                         REG_WR(bp, addr, val);
3536                 }
3537         }
3538
3539         /* Reset the processor, un-stall is done later. */
3540         if (rv2p_proc == RV2P_PROC1) {
3541                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3542         }
3543         else {
3544                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3545         }
3546
3547         return 0;
3548 }
3549
3550 static int
3551 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3552             const struct bnx2_mips_fw_file_entry *fw_entry)
3553 {
3554         u32 addr, len, file_offset;
3555         __be32 *data;
3556         u32 offset;
3557         u32 val;
3558
3559         /* Halt the CPU. */
3560         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3561         val |= cpu_reg->mode_value_halt;
3562         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3563         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3564
3565         /* Load the Text area. */
3566         addr = be32_to_cpu(fw_entry->text.addr);
3567         len = be32_to_cpu(fw_entry->text.len);
3568         file_offset = be32_to_cpu(fw_entry->text.offset);
3569         data = (__be32 *)(bp->mips_firmware->data + file_offset);
3570
3571         offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3572         if (len) {
3573                 int j;
3574
3575                 for (j = 0; j < (len / 4); j++, offset += 4)
3576                         bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3577         }
3578
3579         /* Load the Data area. */
3580         addr = be32_to_cpu(fw_entry->data.addr);
3581         len = be32_to_cpu(fw_entry->data.len);
3582         file_offset = be32_to_cpu(fw_entry->data.offset);
3583         data = (__be32 *)(bp->mips_firmware->data + file_offset);
3584
3585         offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3586         if (len) {
3587                 int j;
3588
3589                 for (j = 0; j < (len / 4); j++, offset += 4)
3590                         bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3591         }
3592
3593         /* Load the Read-Only area. */
3594         addr = be32_to_cpu(fw_entry->rodata.addr);
3595         len = be32_to_cpu(fw_entry->rodata.len);
3596         file_offset = be32_to_cpu(fw_entry->rodata.offset);
3597         data = (__be32 *)(bp->mips_firmware->data + file_offset);
3598
3599         offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3600         if (len) {
3601                 int j;
3602
3603                 for (j = 0; j < (len / 4); j++, offset += 4)
3604                         bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3605         }
3606
3607         /* Clear the pre-fetch instruction. */
3608         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3609
3610         val = be32_to_cpu(fw_entry->start_addr);
3611         bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3612
3613         /* Start the CPU. */
3614         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3615         val &= ~cpu_reg->mode_value_halt;
3616         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3617         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3618
3619         return 0;
3620 }
3621
3622 static int
3623 bnx2_init_cpus(struct bnx2 *bp)
3624 {
3625         const struct bnx2_mips_fw_file *mips_fw =
3626                 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3627         const struct bnx2_rv2p_fw_file *rv2p_fw =
3628                 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3629         int rc;
3630
3631         /* Initialize the RV2P processor. */
3632         load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3633         load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3634
3635         /* Initialize the RX Processor. */
3636         rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3637         if (rc)
3638                 goto init_cpu_err;
3639
3640         /* Initialize the TX Processor. */
3641         rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3642         if (rc)
3643                 goto init_cpu_err;
3644
3645         /* Initialize the TX Patch-up Processor. */
3646         rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3647         if (rc)
3648                 goto init_cpu_err;
3649
3650         /* Initialize the Completion Processor. */
3651         rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3652         if (rc)
3653                 goto init_cpu_err;
3654
3655         /* Initialize the Command Processor. */
3656         rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3657
3658 init_cpu_err:
3659         return rc;
3660 }
3661
3662 static int
3663 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3664 {
3665         u16 pmcsr;
3666
3667         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3668
3669         switch (state) {
3670         case PCI_D0: {
3671                 u32 val;
3672
3673                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3674                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3675                         PCI_PM_CTRL_PME_STATUS);
3676
3677                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3678                         /* delay required during transition out of D3hot */
3679                         msleep(20);
3680
3681                 val = REG_RD(bp, BNX2_EMAC_MODE);
3682                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3683                 val &= ~BNX2_EMAC_MODE_MPKT;
3684                 REG_WR(bp, BNX2_EMAC_MODE, val);
3685
3686                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3687                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3688                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3689                 break;
3690         }
3691         case PCI_D3hot: {
3692                 int i;
3693                 u32 val, wol_msg;
3694
3695                 if (bp->wol) {
3696                         u32 advertising;
3697                         u8 autoneg;
3698
3699                         autoneg = bp->autoneg;
3700                         advertising = bp->advertising;
3701
3702                         if (bp->phy_port == PORT_TP) {
3703                                 bp->autoneg = AUTONEG_SPEED;
3704                                 bp->advertising = ADVERTISED_10baseT_Half |
3705                                         ADVERTISED_10baseT_Full |
3706                                         ADVERTISED_100baseT_Half |
3707                                         ADVERTISED_100baseT_Full |
3708                                         ADVERTISED_Autoneg;
3709                         }
3710
3711                         spin_lock_bh(&bp->phy_lock);
3712                         bnx2_setup_phy(bp, bp->phy_port);
3713                         spin_unlock_bh(&bp->phy_lock);
3714
3715                         bp->autoneg = autoneg;
3716                         bp->advertising = advertising;
3717
3718                         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3719
3720                         val = REG_RD(bp, BNX2_EMAC_MODE);
3721
3722                         /* Enable port mode. */
3723                         val &= ~BNX2_EMAC_MODE_PORT;
3724                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3725                                BNX2_EMAC_MODE_ACPI_RCVD |
3726                                BNX2_EMAC_MODE_MPKT;
3727                         if (bp->phy_port == PORT_TP)
3728                                 val |= BNX2_EMAC_MODE_PORT_MII;
3729                         else {
3730                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3731                                 if (bp->line_speed == SPEED_2500)
3732                                         val |= BNX2_EMAC_MODE_25G_MODE;
3733                         }
3734
3735                         REG_WR(bp, BNX2_EMAC_MODE, val);
3736
3737                         /* receive all multicast */
3738                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3739                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3740                                        0xffffffff);
3741                         }
3742                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3743                                BNX2_EMAC_RX_MODE_SORT_MODE);
3744
3745                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3746                               BNX2_RPM_SORT_USER0_MC_EN;
3747                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3748                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3749                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3750                                BNX2_RPM_SORT_USER0_ENA);
3751
3752                         /* Need to enable EMAC and RPM for WOL. */
3753                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3754                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3755                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3756                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3757
3758                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3759                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3760                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3761
3762                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3763                 }
3764                 else {
3765                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3766                 }
3767
3768                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3769                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3770                                      1, 0);
3771
3772                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3773                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3774                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3775
3776                         if (bp->wol)
3777                                 pmcsr |= 3;
3778                 }
3779                 else {
3780                         pmcsr |= 3;
3781                 }
3782                 if (bp->wol) {
3783                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3784                 }
3785                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3786                                       pmcsr);
3787
3788                 /* No more memory access after this point until
3789                  * device is brought back to D0.
3790                  */
3791                 udelay(50);
3792                 break;
3793         }
3794         default:
3795                 return -EINVAL;
3796         }
3797         return 0;
3798 }
3799
3800 static int
3801 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3802 {
3803         u32 val;
3804         int j;
3805
3806         /* Request access to the flash interface. */
3807         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3808         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3809                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3810                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3811                         break;
3812
3813                 udelay(5);
3814         }
3815
3816         if (j >= NVRAM_TIMEOUT_COUNT)
3817                 return -EBUSY;
3818
3819         return 0;
3820 }
3821
3822 static int
3823 bnx2_release_nvram_lock(struct bnx2 *bp)
3824 {
3825         int j;
3826         u32 val;
3827
3828         /* Relinquish nvram interface. */
3829         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3830
3831         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3832                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3833                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3834                         break;
3835
3836                 udelay(5);
3837         }
3838
3839         if (j >= NVRAM_TIMEOUT_COUNT)
3840                 return -EBUSY;
3841
3842         return 0;
3843 }
3844
3845
3846 static int
3847 bnx2_enable_nvram_write(struct bnx2 *bp)
3848 {
3849         u32 val;
3850
3851         val = REG_RD(bp, BNX2_MISC_CFG);
3852         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3853
3854         if (bp->flash_info->flags & BNX2_NV_WREN) {
3855                 int j;
3856
3857                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3858                 REG_WR(bp, BNX2_NVM_COMMAND,
3859                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3860
3861                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3862                         udelay(5);
3863
3864                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3865                         if (val & BNX2_NVM_COMMAND_DONE)
3866                                 break;
3867                 }
3868
3869                 if (j >= NVRAM_TIMEOUT_COUNT)
3870                         return -EBUSY;
3871         }
3872         return 0;
3873 }
3874
3875 static void
3876 bnx2_disable_nvram_write(struct bnx2 *bp)
3877 {
3878         u32 val;
3879
3880         val = REG_RD(bp, BNX2_MISC_CFG);
3881         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3882 }
3883
3884
3885 static void
3886 bnx2_enable_nvram_access(struct bnx2 *bp)
3887 {
3888         u32 val;
3889
3890         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3891         /* Enable both bits, even on read. */
3892         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3893                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3894 }
3895
3896 static void
3897 bnx2_disable_nvram_access(struct bnx2 *bp)
3898 {
3899         u32 val;
3900
3901         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3902         /* Disable both bits, even after read. */
3903         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3904                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3905                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3906 }
3907
3908 static int
3909 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3910 {
3911         u32 cmd;
3912         int j;
3913
3914         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3915                 /* Buffered flash, no erase needed */
3916                 return 0;
3917
3918         /* Build an erase command */
3919         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3920               BNX2_NVM_COMMAND_DOIT;
3921
3922         /* Need to clear DONE bit separately. */
3923         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3924
3925         /* Address of the NVRAM to read from. */
3926         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3927
3928         /* Issue an erase command. */
3929         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3930
3931         /* Wait for completion. */
3932         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3933                 u32 val;
3934
3935                 udelay(5);
3936
3937                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3938                 if (val & BNX2_NVM_COMMAND_DONE)
3939                         break;
3940         }
3941
3942         if (j >= NVRAM_TIMEOUT_COUNT)
3943                 return -EBUSY;
3944
3945         return 0;
3946 }
3947
3948 static int
3949 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3950 {
3951         u32 cmd;
3952         int j;
3953
3954         /* Build the command word. */
3955         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3956
3957         /* Calculate an offset of a buffered flash, not needed for 5709. */
3958         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3959                 offset = ((offset / bp->flash_info->page_size) <<
3960                            bp->flash_info->page_bits) +
3961                           (offset % bp->flash_info->page_size);
3962         }
3963
3964         /* Need to clear DONE bit separately. */
3965         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3966
3967         /* Address of the NVRAM to read from. */
3968         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3969
3970         /* Issue a read command. */
3971         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3972
3973         /* Wait for completion. */
3974         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3975                 u32 val;
3976
3977                 udelay(5);
3978
3979                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3980                 if (val & BNX2_NVM_COMMAND_DONE) {
3981                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3982                         memcpy(ret_val, &v, 4);
3983                         break;
3984                 }
3985         }
3986         if (j >= NVRAM_TIMEOUT_COUNT)
3987                 return -EBUSY;
3988
3989         return 0;
3990 }
3991
3992
3993 static int
3994 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3995 {
3996         u32 cmd;
3997         __be32 val32;
3998         int j;
3999
4000         /* Build the command word. */
4001         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4002
4003         /* Calculate an offset of a buffered flash, not needed for 5709. */
4004         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4005                 offset = ((offset / bp->flash_info->page_size) <<
4006                           bp->flash_info->page_bits) +
4007                          (offset % bp->flash_info->page_size);
4008         }
4009
4010         /* Need to clear DONE bit separately. */
4011         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4012
4013         memcpy(&val32, val, 4);
4014
4015         /* Write the data. */
4016         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4017
4018         /* Address of the NVRAM to write to. */
4019         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4020
4021         /* Issue the write command. */
4022         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4023
4024         /* Wait for completion. */
4025         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4026                 udelay(5);
4027
4028                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4029                         break;
4030         }
4031         if (j >= NVRAM_TIMEOUT_COUNT)
4032                 return -EBUSY;
4033
4034         return 0;
4035 }
4036
4037 static int
4038 bnx2_init_nvram(struct bnx2 *bp)
4039 {
4040         u32 val;
4041         int j, entry_count, rc = 0;
4042         struct flash_spec *flash;
4043
4044         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4045                 bp->flash_info = &flash_5709;
4046                 goto get_flash_size;
4047         }
4048
4049         /* Determine the selected interface. */
4050         val = REG_RD(bp, BNX2_NVM_CFG1);
4051
4052         entry_count = ARRAY_SIZE(flash_table);
4053
4054         if (val & 0x40000000) {
4055
4056                 /* Flash interface has been reconfigured */
4057                 for (j = 0, flash = &flash_table[0]; j < entry_count;
4058                      j++, flash++) {
4059                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
4060                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4061                                 bp->flash_info = flash;
4062                                 break;
4063                         }
4064                 }
4065         }
4066         else {
4067                 u32 mask;
4068                 /* Not yet been reconfigured */
4069
4070                 if (val & (1 << 23))
4071                         mask = FLASH_BACKUP_STRAP_MASK;
4072                 else
4073                         mask = FLASH_STRAP_MASK;
4074
4075                 for (j = 0, flash = &flash_table[0]; j < entry_count;
4076                         j++, flash++) {
4077
4078                         if ((val & mask) == (flash->strapping & mask)) {
4079                                 bp->flash_info = flash;
4080
4081                                 /* Request access to the flash interface. */
4082                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4083                                         return rc;
4084
4085                                 /* Enable access to flash interface */
4086                                 bnx2_enable_nvram_access(bp);
4087
4088                                 /* Reconfigure the flash interface */
4089                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4090                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4091                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4092                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4093
4094                                 /* Disable access to flash interface */
4095                                 bnx2_disable_nvram_access(bp);
4096                                 bnx2_release_nvram_lock(bp);
4097
4098                                 break;
4099                         }
4100                 }
4101         } /* if (val & 0x40000000) */
4102
4103         if (j == entry_count) {
4104                 bp->flash_info = NULL;
4105                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4106                 return -ENODEV;
4107         }
4108
4109 get_flash_size:
4110         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4111         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4112         if (val)
4113                 bp->flash_size = val;
4114         else
4115                 bp->flash_size = bp->flash_info->total_size;
4116
4117         return rc;
4118 }
4119
4120 static int
4121 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4122                 int buf_size)
4123 {
4124         int rc = 0;
4125         u32 cmd_flags, offset32, len32, extra;
4126
4127         if (buf_size == 0)
4128                 return 0;
4129
4130         /* Request access to the flash interface. */
4131         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4132                 return rc;
4133
4134         /* Enable access to flash interface */
4135         bnx2_enable_nvram_access(bp);
4136
4137         len32 = buf_size;
4138         offset32 = offset;
4139         extra = 0;
4140
4141         cmd_flags = 0;
4142
4143         if (offset32 & 3) {
4144                 u8 buf[4];
4145                 u32 pre_len;
4146
4147                 offset32 &= ~3;
4148                 pre_len = 4 - (offset & 3);
4149
4150                 if (pre_len >= len32) {
4151                         pre_len = len32;
4152                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4153                                     BNX2_NVM_COMMAND_LAST;
4154                 }
4155                 else {
4156                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4157                 }
4158
4159                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4160
4161                 if (rc)
4162                         return rc;
4163
4164                 memcpy(ret_buf, buf + (offset & 3), pre_len);
4165
4166                 offset32 += 4;
4167                 ret_buf += pre_len;
4168                 len32 -= pre_len;
4169         }
4170         if (len32 & 3) {
4171                 extra = 4 - (len32 & 3);
4172                 len32 = (len32 + 4) & ~3;
4173         }
4174
4175         if (len32 == 4) {
4176                 u8 buf[4];
4177
4178                 if (cmd_flags)
4179                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4180                 else
4181                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4182                                     BNX2_NVM_COMMAND_LAST;
4183
4184                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4185
4186                 memcpy(ret_buf, buf, 4 - extra);
4187         }
4188         else if (len32 > 0) {
4189                 u8 buf[4];
4190
4191                 /* Read the first word. */
4192                 if (cmd_flags)
4193                         cmd_flags = 0;
4194                 else
4195                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4196
4197                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4198
4199                 /* Advance to the next dword. */
4200                 offset32 += 4;
4201                 ret_buf += 4;
4202                 len32 -= 4;
4203
4204                 while (len32 > 4 && rc == 0) {
4205                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4206
4207                         /* Advance to the next dword. */
4208                         offset32 += 4;
4209                         ret_buf += 4;
4210                         len32 -= 4;
4211                 }
4212
4213                 if (rc)
4214                         return rc;
4215
4216                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4217                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4218
4219                 memcpy(ret_buf, buf, 4 - extra);
4220         }
4221
4222         /* Disable access to flash interface */
4223         bnx2_disable_nvram_access(bp);
4224
4225         bnx2_release_nvram_lock(bp);
4226
4227         return rc;
4228 }
4229
4230 static int
4231 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4232                 int buf_size)
4233 {
4234         u32 written, offset32, len32;
4235         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4236         int rc = 0;
4237         int align_start, align_end;
4238
4239         buf = data_buf;
4240         offset32 = offset;
4241         len32 = buf_size;
4242         align_start = align_end = 0;
4243
4244         if ((align_start = (offset32 & 3))) {
4245                 offset32 &= ~3;
4246                 len32 += align_start;
4247                 if (len32 < 4)
4248                         len32 = 4;
4249                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4250                         return rc;
4251         }
4252
4253         if (len32 & 3) {
4254                 align_end = 4 - (len32 & 3);
4255                 len32 += align_end;
4256                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4257                         return rc;
4258         }
4259
4260         if (align_start || align_end) {
4261                 align_buf = kmalloc(len32, GFP_KERNEL);
4262                 if (align_buf == NULL)
4263                         return -ENOMEM;
4264                 if (align_start) {
4265                         memcpy(align_buf, start, 4);
4266                 }
4267                 if (align_end) {
4268                         memcpy(align_buf + len32 - 4, end, 4);
4269                 }
4270                 memcpy(align_buf + align_start, data_buf, buf_size);
4271                 buf = align_buf;
4272         }
4273
4274         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4275                 flash_buffer = kmalloc(264, GFP_KERNEL);
4276                 if (flash_buffer == NULL) {
4277                         rc = -ENOMEM;
4278                         goto nvram_write_end;
4279                 }
4280         }
4281
4282         written = 0;
4283         while ((written < len32) && (rc == 0)) {
4284                 u32 page_start, page_end, data_start, data_end;
4285                 u32 addr, cmd_flags;
4286                 int i;
4287
4288                 /* Find the page_start addr */
4289                 page_start = offset32 + written;
4290                 page_start -= (page_start % bp->flash_info->page_size);
4291                 /* Find the page_end addr */
4292                 page_end = page_start + bp->flash_info->page_size;
4293                 /* Find the data_start addr */
4294                 data_start = (written == 0) ? offset32 : page_start;
4295                 /* Find the data_end addr */
4296                 data_end = (page_end > offset32 + len32) ?
4297                         (offset32 + len32) : page_end;
4298
4299                 /* Request access to the flash interface. */
4300                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4301                         goto nvram_write_end;
4302
4303                 /* Enable access to flash interface */
4304                 bnx2_enable_nvram_access(bp);
4305
4306                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4307                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4308                         int j;
4309
4310                         /* Read the whole page into the buffer
4311                          * (non-buffer flash only) */
4312                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4313                                 if (j == (bp->flash_info->page_size - 4)) {
4314                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4315                                 }
4316                                 rc = bnx2_nvram_read_dword(bp,
4317                                         page_start + j,
4318                                         &flash_buffer[j],
4319                                         cmd_flags);
4320
4321                                 if (rc)
4322                                         goto nvram_write_end;
4323
4324                                 cmd_flags = 0;
4325                         }
4326                 }
4327
4328                 /* Enable writes to flash interface (unlock write-protect) */
4329                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4330                         goto nvram_write_end;
4331
4332                 /* Loop to write back the buffer data from page_start to
4333                  * data_start */
4334                 i = 0;
4335                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4336                         /* Erase the page */
4337                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4338                                 goto nvram_write_end;
4339
4340                         /* Re-enable the write again for the actual write */
4341                         bnx2_enable_nvram_write(bp);
4342
4343                         for (addr = page_start; addr < data_start;
4344                                 addr += 4, i += 4) {
4345
4346                                 rc = bnx2_nvram_write_dword(bp, addr,
4347                                         &flash_buffer[i], cmd_flags);
4348
4349                                 if (rc != 0)
4350                                         goto nvram_write_end;
4351
4352                                 cmd_flags = 0;
4353                         }
4354                 }
4355
4356                 /* Loop to write the new data from data_start to data_end */
4357                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4358                         if ((addr == page_end - 4) ||
4359                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4360                                  (addr == data_end - 4))) {
4361
4362                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4363                         }
4364                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4365                                 cmd_flags);
4366
4367                         if (rc != 0)
4368                                 goto nvram_write_end;
4369
4370                         cmd_flags = 0;
4371                         buf += 4;
4372                 }
4373
4374                 /* Loop to write back the buffer data from data_end
4375                  * to page_end */
4376                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4377                         for (addr = data_end; addr < page_end;
4378                                 addr += 4, i += 4) {
4379
4380                                 if (addr == page_end-4) {
4381                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4382                                 }
4383                                 rc = bnx2_nvram_write_dword(bp, addr,
4384                                         &flash_buffer[i], cmd_flags);
4385
4386                                 if (rc != 0)
4387                                         goto nvram_write_end;
4388
4389                                 cmd_flags = 0;
4390                         }
4391                 }
4392
4393                 /* Disable writes to flash interface (lock write-protect) */
4394                 bnx2_disable_nvram_write(bp);
4395
4396                 /* Disable access to flash interface */
4397                 bnx2_disable_nvram_access(bp);
4398                 bnx2_release_nvram_lock(bp);
4399
4400                 /* Increment written */
4401                 written += data_end - data_start;
4402         }
4403
4404 nvram_write_end:
4405         kfree(flash_buffer);
4406         kfree(align_buf);
4407         return rc;
4408 }
4409
4410 static void
4411 bnx2_init_fw_cap(struct bnx2 *bp)
4412 {
4413         u32 val, sig = 0;
4414
4415         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4416         bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4417
4418         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4419                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4420
4421         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4422         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4423                 return;
4424
4425         if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4426                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4427                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4428         }
4429
4430         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4431             (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4432                 u32 link;
4433
4434                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4435
4436                 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4437                 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4438                         bp->phy_port = PORT_FIBRE;
4439                 else
4440                         bp->phy_port = PORT_TP;
4441
4442                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4443                        BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4444         }
4445
4446         if (netif_running(bp->dev) && sig)
4447                 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4448 }
4449
4450 static void
4451 bnx2_setup_msix_tbl(struct bnx2 *bp)
4452 {
4453         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4454
4455         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4456         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4457 }
4458
4459 static int
4460 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4461 {
4462         u32 val;
4463         int i, rc = 0;
4464         u8 old_port;
4465
4466         /* Wait for the current PCI transaction to complete before
4467          * issuing a reset. */
4468         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4469                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4470                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4471                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4472                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4473         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4474         udelay(5);
4475
4476         /* Wait for the firmware to tell us it is ok to issue a reset. */
4477         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4478
4479         /* Deposit a driver reset signature so the firmware knows that
4480          * this is a soft reset. */
4481         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4482                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4483
4484         /* Do a dummy read to force the chip to complete all current transaction
4485          * before we issue a reset. */
4486         val = REG_RD(bp, BNX2_MISC_ID);
4487
4488         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4489                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4490                 REG_RD(bp, BNX2_MISC_COMMAND);
4491                 udelay(5);
4492
4493                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4494                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4495
4496                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4497
4498         } else {
4499                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4500                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4501                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4502
4503                 /* Chip reset. */
4504                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4505
4506                 /* Reading back any register after chip reset will hang the
4507                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4508                  * of margin for write posting.
4509                  */
4510                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4511                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4512                         msleep(20);
4513
4514                 /* Reset takes approximate 30 usec */
4515                 for (i = 0; i < 10; i++) {
4516                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4517                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4518                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4519                                 break;
4520                         udelay(10);
4521                 }
4522
4523                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4524                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4525                         printk(KERN_ERR PFX "Chip reset did not complete\n");
4526                         return -EBUSY;
4527                 }
4528         }
4529
4530         /* Make sure byte swapping is properly configured. */
4531         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4532         if (val != 0x01020304) {
4533                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4534                 return -ENODEV;
4535         }
4536
4537         /* Wait for the firmware to finish its initialization. */
4538         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4539         if (rc)
4540                 return rc;
4541
4542         spin_lock_bh(&bp->phy_lock);
4543         old_port = bp->phy_port;
4544         bnx2_init_fw_cap(bp);
4545         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4546             old_port != bp->phy_port)
4547                 bnx2_set_default_remote_link(bp);
4548         spin_unlock_bh(&bp->phy_lock);
4549
4550         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4551                 /* Adjust the voltage regular to two steps lower.  The default
4552                  * of this register is 0x0000000e. */
4553                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4554
4555                 /* Remove bad rbuf memory from the free pool. */
4556                 rc = bnx2_alloc_bad_rbuf(bp);
4557         }
4558
4559         if (bp->flags & BNX2_FLAG_USING_MSIX)
4560                 bnx2_setup_msix_tbl(bp);
4561
4562         return rc;
4563 }
4564
4565 static int
4566 bnx2_init_chip(struct bnx2 *bp)
4567 {
4568         u32 val, mtu;
4569         int rc, i;
4570
4571         /* Make sure the interrupt is not active. */
4572         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4573
4574         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4575               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4576 #ifdef __BIG_ENDIAN
4577               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4578 #endif
4579               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4580               DMA_READ_CHANS << 12 |
4581               DMA_WRITE_CHANS << 16;
4582
4583         val |= (0x2 << 20) | (1 << 11);
4584
4585         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4586                 val |= (1 << 23);
4587
4588         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4589             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4590                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4591
4592         REG_WR(bp, BNX2_DMA_CONFIG, val);
4593
4594         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4595                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4596                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4597                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4598         }
4599
4600         if (bp->flags & BNX2_FLAG_PCIX) {
4601                 u16 val16;
4602
4603                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4604                                      &val16);
4605                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4606                                       val16 & ~PCI_X_CMD_ERO);
4607         }
4608
4609         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4610                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4611                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4612                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4613
4614         /* Initialize context mapping and zero out the quick contexts.  The
4615          * context block must have already been enabled. */
4616         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4617                 rc = bnx2_init_5709_context(bp);
4618                 if (rc)
4619                         return rc;
4620         } else
4621                 bnx2_init_context(bp);
4622
4623         if ((rc = bnx2_init_cpus(bp)) != 0)
4624                 return rc;
4625
4626         bnx2_init_nvram(bp);
4627
4628         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4629
4630         val = REG_RD(bp, BNX2_MQ_CONFIG);
4631         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4632         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4633         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4634                 val |= BNX2_MQ_CONFIG_HALT_DIS;
4635
4636         REG_WR(bp, BNX2_MQ_CONFIG, val);
4637
4638         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4639         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4640         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4641
4642         val = (BCM_PAGE_BITS - 8) << 24;
4643         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4644
4645         /* Configure page size. */
4646         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4647         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4648         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4649         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4650
4651         val = bp->mac_addr[0] +
4652               (bp->mac_addr[1] << 8) +
4653               (bp->mac_addr[2] << 16) +
4654               bp->mac_addr[3] +
4655               (bp->mac_addr[4] << 8) +
4656               (bp->mac_addr[5] << 16);
4657         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4658
4659         /* Program the MTU.  Also include 4 bytes for CRC32. */
4660         mtu = bp->dev->mtu;
4661         val = mtu + ETH_HLEN + ETH_FCS_LEN;
4662         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4663                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4664         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4665
4666         if (mtu < 1500)
4667                 mtu = 1500;
4668
4669         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4670         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4671         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4672
4673         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4674                 bp->bnx2_napi[i].last_status_idx = 0;
4675
4676         bp->idle_chk_status_idx = 0xffff;
4677
4678         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4679
4680         /* Set up how to generate a link change interrupt. */
4681         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4682
4683         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4684                (u64) bp->status_blk_mapping & 0xffffffff);
4685         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4686
4687         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4688                (u64) bp->stats_blk_mapping & 0xffffffff);
4689         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4690                (u64) bp->stats_blk_mapping >> 32);
4691
4692         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4693                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4694
4695         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4696                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4697
4698         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4699                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4700
4701         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4702
4703         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4704
4705         REG_WR(bp, BNX2_HC_COM_TICKS,
4706                (bp->com_ticks_int << 16) | bp->com_ticks);
4707
4708         REG_WR(bp, BNX2_HC_CMD_TICKS,
4709                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4710
4711         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4712                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4713         else
4714                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4715         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4716
4717         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4718                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4719         else {
4720                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4721                       BNX2_HC_CONFIG_COLLECT_STATS;
4722         }
4723
4724         if (bp->irq_nvecs > 1) {
4725                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4726                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4727
4728                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4729         }
4730
4731         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4732                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4733
4734         REG_WR(bp, BNX2_HC_CONFIG, val);
4735
4736         for (i = 1; i < bp->irq_nvecs; i++) {
4737                 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4738                            BNX2_HC_SB_CONFIG_1;
4739
4740                 REG_WR(bp, base,
4741                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4742                         BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4743                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4744
4745                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4746                         (bp->tx_quick_cons_trip_int << 16) |
4747                          bp->tx_quick_cons_trip);
4748
4749                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4750                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4751
4752                 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4753                        (bp->rx_quick_cons_trip_int << 16) |
4754                         bp->rx_quick_cons_trip);
4755
4756                 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4757                         (bp->rx_ticks_int << 16) | bp->rx_ticks);
4758         }
4759
4760         /* Clear internal stats counters. */
4761         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4762
4763         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4764
4765         /* Initialize the receive filter. */
4766         bnx2_set_rx_mode(bp->dev);
4767
4768         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4769                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4770                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4771                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4772         }
4773         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4774                           1, 0);
4775
4776         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4777         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4778
4779         udelay(20);
4780
4781         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4782
4783         return rc;
4784 }
4785
4786 static void
4787 bnx2_clear_ring_states(struct bnx2 *bp)
4788 {
4789         struct bnx2_napi *bnapi;
4790         struct bnx2_tx_ring_info *txr;
4791         struct bnx2_rx_ring_info *rxr;
4792         int i;
4793
4794         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4795                 bnapi = &bp->bnx2_napi[i];
4796                 txr = &bnapi->tx_ring;
4797                 rxr = &bnapi->rx_ring;
4798
4799                 txr->tx_cons = 0;
4800                 txr->hw_tx_cons = 0;
4801                 rxr->rx_prod_bseq = 0;
4802                 rxr->rx_prod = 0;
4803                 rxr->rx_cons = 0;
4804                 rxr->rx_pg_prod = 0;
4805                 rxr->rx_pg_cons = 0;
4806         }
4807 }
4808
4809 static void
4810 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4811 {
4812         u32 val, offset0, offset1, offset2, offset3;
4813         u32 cid_addr = GET_CID_ADDR(cid);
4814
4815         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4816                 offset0 = BNX2_L2CTX_TYPE_XI;
4817                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4818                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4819                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4820         } else {
4821                 offset0 = BNX2_L2CTX_TYPE;
4822                 offset1 = BNX2_L2CTX_CMD_TYPE;
4823                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4824                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4825         }
4826         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4827         bnx2_ctx_wr(bp, cid_addr, offset0, val);
4828
4829         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4830         bnx2_ctx_wr(bp, cid_addr, offset1, val);
4831
4832         val = (u64) txr->tx_desc_mapping >> 32;
4833         bnx2_ctx_wr(bp, cid_addr, offset2, val);
4834
4835         val = (u64) txr->tx_desc_mapping & 0xffffffff;
4836         bnx2_ctx_wr(bp, cid_addr, offset3, val);
4837 }
4838
4839 static void
4840 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4841 {
4842         struct tx_bd *txbd;
4843         u32 cid = TX_CID;
4844         struct bnx2_napi *bnapi;
4845         struct bnx2_tx_ring_info *txr;
4846
4847         bnapi = &bp->bnx2_napi[ring_num];
4848         txr = &bnapi->tx_ring;
4849
4850         if (ring_num == 0)
4851                 cid = TX_CID;
4852         else
4853                 cid = TX_TSS_CID + ring_num - 1;
4854
4855         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4856
4857         txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4858
4859         txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4860         txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4861
4862         txr->tx_prod = 0;
4863         txr->tx_prod_bseq = 0;
4864
4865         txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4866         txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4867
4868         bnx2_init_tx_context(bp, cid, txr);
4869 }
4870
4871 static void
4872 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4873                      int num_rings)
4874 {
4875         int i;
4876         struct rx_bd *rxbd;
4877
4878         for (i = 0; i < num_rings; i++) {
4879                 int j;
4880
4881                 rxbd = &rx_ring[i][0];
4882                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4883                         rxbd->rx_bd_len = buf_size;
4884                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4885                 }
4886                 if (i == (num_rings - 1))
4887                         j = 0;
4888                 else
4889                         j = i + 1;
4890                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4891                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4892         }
4893 }
4894
4895 static void
4896 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4897 {
4898         int i;
4899         u16 prod, ring_prod;
4900         u32 cid, rx_cid_addr, val;
4901         struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4902         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4903
4904         if (ring_num == 0)
4905                 cid = RX_CID;
4906         else
4907                 cid = RX_RSS_CID + ring_num - 1;
4908
4909         rx_cid_addr = GET_CID_ADDR(cid);
4910
4911         bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4912                              bp->rx_buf_use_size, bp->rx_max_ring);
4913
4914         bnx2_init_rx_context(bp, cid);
4915
4916         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4917                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4918                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4919         }
4920
4921         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4922         if (bp->rx_pg_ring_size) {
4923                 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4924                                      rxr->rx_pg_desc_mapping,
4925                                      PAGE_SIZE, bp->rx_max_pg_ring);
4926                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4927                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4928                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4929                        BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4930
4931                 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4932                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4933
4934                 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4935                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4936
4937                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4938                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4939         }
4940
4941         val = (u64) rxr->rx_desc_mapping[0] >> 32;
4942         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4943
4944         val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4945         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4946
4947         ring_prod = prod = rxr->rx_pg_prod;
4948         for (i = 0; i < bp->rx_pg_ring_size; i++) {
4949                 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4950                         break;
4951                 prod = NEXT_RX_BD(prod);
4952                 ring_prod = RX_PG_RING_IDX(prod);
4953         }
4954         rxr->rx_pg_prod = prod;
4955
4956         ring_prod = prod = rxr->rx_prod;
4957         for (i = 0; i < bp->rx_ring_size; i++) {
4958                 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4959                         break;
4960                 prod = NEXT_RX_BD(prod);
4961                 ring_prod = RX_RING_IDX(prod);
4962         }
4963         rxr->rx_prod = prod;
4964
4965         rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4966         rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4967         rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4968
4969         REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4970         REG_WR16(bp, rxr->rx_bidx_addr, prod);
4971
4972         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4973 }
4974
4975 static void
4976 bnx2_init_all_rings(struct bnx2 *bp)
4977 {
4978         int i;
4979         u32 val;
4980
4981         bnx2_clear_ring_states(bp);
4982
4983         REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4984         for (i = 0; i < bp->num_tx_rings; i++)
4985                 bnx2_init_tx_ring(bp, i);
4986
4987         if (bp->num_tx_rings > 1)
4988                 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4989                        (TX_TSS_CID << 7));
4990
4991         REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4992         bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4993
4994         for (i = 0; i < bp->num_rx_rings; i++)
4995                 bnx2_init_rx_ring(bp, i);
4996
4997         if (bp->num_rx_rings > 1) {
4998                 u32 tbl_32;
4999                 u8 *tbl = (u8 *) &tbl_32;
5000
5001                 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5002                                 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5003
5004                 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5005                         tbl[i % 4] = i % (bp->num_rx_rings - 1);
5006                         if ((i % 4) == 3)
5007                                 bnx2_reg_wr_ind(bp,
5008                                                 BNX2_RXP_SCRATCH_RSS_TBL + i,
5009                                                 cpu_to_be32(tbl_32));
5010                 }
5011
5012                 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5013                       BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5014
5015                 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5016
5017         }
5018 }
5019
5020 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5021 {
5022         u32 max, num_rings = 1;
5023
5024         while (ring_size > MAX_RX_DESC_CNT) {
5025                 ring_size -= MAX_RX_DESC_CNT;
5026                 num_rings++;
5027         }
5028         /* round to next power of 2 */
5029         max = max_size;
5030         while ((max & num_rings) == 0)
5031                 max >>= 1;
5032
5033         if (num_rings != max)
5034                 max <<= 1;
5035
5036         return max;
5037 }
5038
5039 static void
5040 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5041 {
5042         u32 rx_size, rx_space, jumbo_size;
5043
5044         /* 8 for CRC and VLAN */
5045         rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5046
5047         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5048                 sizeof(struct skb_shared_info);
5049
5050         bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5051         bp->rx_pg_ring_size = 0;
5052         bp->rx_max_pg_ring = 0;
5053         bp->rx_max_pg_ring_idx = 0;
5054         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5055                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5056
5057                 jumbo_size = size * pages;
5058                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5059                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5060
5061                 bp->rx_pg_ring_size = jumbo_size;
5062                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5063                                                         MAX_RX_PG_RINGS);
5064                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5065                 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5066                 bp->rx_copy_thresh = 0;
5067         }
5068
5069         bp->rx_buf_use_size = rx_size;
5070         /* hw alignment */
5071         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5072         bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5073         bp->rx_ring_size = size;
5074         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5075         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5076 }
5077
5078 static void
5079 bnx2_free_tx_skbs(struct bnx2 *bp)
5080 {
5081         int i;
5082
5083         for (i = 0; i < bp->num_tx_rings; i++) {
5084                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5085                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5086                 int j;
5087
5088                 if (txr->tx_buf_ring == NULL)
5089                         continue;
5090
5091                 for (j = 0; j < TX_DESC_CNT; ) {
5092                         struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5093                         struct sk_buff *skb = tx_buf->skb;
5094
5095                         if (skb == NULL) {
5096                                 j++;
5097                                 continue;
5098                         }
5099
5100                         skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5101
5102                         tx_buf->skb = NULL;
5103
5104                         j += skb_shinfo(skb)->nr_frags + 1;
5105                         dev_kfree_skb(skb);
5106                 }
5107         }
5108 }
5109
5110 static void
5111 bnx2_free_rx_skbs(struct bnx2 *bp)
5112 {
5113         int i;
5114
5115         for (i = 0; i < bp->num_rx_rings; i++) {
5116                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5117                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5118                 int j;
5119
5120                 if (rxr->rx_buf_ring == NULL)
5121                         return;
5122
5123                 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5124                         struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5125                         struct sk_buff *skb = rx_buf->skb;
5126
5127                         if (skb == NULL)
5128                                 continue;
5129
5130                         pci_unmap_single(bp->pdev,
5131                                          pci_unmap_addr(rx_buf, mapping),
5132                                          bp->rx_buf_use_size,
5133                                          PCI_DMA_FROMDEVICE);
5134
5135                         rx_buf->skb = NULL;
5136
5137                         dev_kfree_skb(skb);
5138                 }
5139                 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5140                         bnx2_free_rx_page(bp, rxr, j);
5141         }
5142 }
5143
5144 static void
5145 bnx2_free_skbs(struct bnx2 *bp)
5146 {
5147         bnx2_free_tx_skbs(bp);
5148         bnx2_free_rx_skbs(bp);
5149 }
5150
5151 static int
5152 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5153 {
5154         int rc;
5155
5156         rc = bnx2_reset_chip(bp, reset_code);
5157         bnx2_free_skbs(bp);
5158         if (rc)
5159                 return rc;
5160
5161         if ((rc = bnx2_init_chip(bp)) != 0)
5162                 return rc;
5163
5164         bnx2_init_all_rings(bp);
5165         return 0;
5166 }
5167
5168 static int
5169 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5170 {
5171         int rc;
5172
5173         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5174                 return rc;
5175
5176         spin_lock_bh(&bp->phy_lock);
5177         bnx2_init_phy(bp, reset_phy);
5178         bnx2_set_link(bp);
5179         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5180                 bnx2_remote_phy_event(bp);
5181         spin_unlock_bh(&bp->phy_lock);
5182         return 0;
5183 }
5184
5185 static int
5186 bnx2_shutdown_chip(struct bnx2 *bp)
5187 {
5188         u32 reset_code;
5189
5190         if (bp->flags & BNX2_FLAG_NO_WOL)
5191                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5192         else if (bp->wol)
5193                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5194         else
5195                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5196
5197         return bnx2_reset_chip(bp, reset_code);
5198 }
5199
5200 static int
5201 bnx2_test_registers(struct bnx2 *bp)
5202 {
5203         int ret;
5204         int i, is_5709;
5205         static const struct {
5206                 u16   offset;
5207                 u16   flags;
5208 #define BNX2_FL_NOT_5709        1
5209                 u32   rw_mask;
5210                 u32   ro_mask;
5211         } reg_tbl[] = {
5212                 { 0x006c, 0, 0x00000000, 0x0000003f },
5213                 { 0x0090, 0, 0xffffffff, 0x00000000 },
5214                 { 0x0094, 0, 0x00000000, 0x00000000 },
5215
5216                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5217                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5218                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5219                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5220                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5221                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5222                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5223                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5224                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5225
5226                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5227                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5228                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5229                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5230                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5231                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5232
5233                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5234                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5235                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5236
5237                 { 0x1000, 0, 0x00000000, 0x00000001 },
5238                 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5239
5240                 { 0x1408, 0, 0x01c00800, 0x00000000 },
5241                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5242                 { 0x14a8, 0, 0x00000000, 0x000001ff },
5243                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5244                 { 0x14b0, 0, 0x00000002, 0x00000001 },
5245                 { 0x14b8, 0, 0x00000000, 0x00000000 },
5246                 { 0x14c0, 0, 0x00000000, 0x00000009 },
5247                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5248                 { 0x14cc, 0, 0x00000000, 0x00000001 },
5249                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5250
5251                 { 0x1800, 0, 0x00000000, 0x00000001 },
5252                 { 0x1804, 0, 0x00000000, 0x00000003 },
5253
5254                 { 0x2800, 0, 0x00000000, 0x00000001 },
5255                 { 0x2804, 0, 0x00000000, 0x00003f01 },
5256                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5257                 { 0x2810, 0, 0xffff0000, 0x00000000 },
5258                 { 0x2814, 0, 0xffff0000, 0x00000000 },
5259                 { 0x2818, 0, 0xffff0000, 0x00000000 },
5260                 { 0x281c, 0, 0xffff0000, 0x00000000 },
5261                 { 0x2834, 0, 0xffffffff, 0x00000000 },
5262                 { 0x2840, 0, 0x00000000, 0xffffffff },
5263                 { 0x2844, 0, 0x00000000, 0xffffffff },
5264                 { 0x2848, 0, 0xffffffff, 0x00000000 },
5265                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5266
5267                 { 0x2c00, 0, 0x00000000, 0x00000011 },
5268                 { 0x2c04, 0, 0x00000000, 0x00030007 },
5269
5270                 { 0x3c00, 0, 0x00000000, 0x00000001 },
5271                 { 0x3c04, 0, 0x00000000, 0x00070000 },
5272                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5273                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5274                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5275                 { 0x3c14, 0, 0x00000000, 0xffffffff },
5276                 { 0x3c18, 0, 0x00000000, 0xffffffff },
5277                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5278                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5279
5280                 { 0x5004, 0, 0x00000000, 0x0000007f },
5281                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5282
5283                 { 0x5c00, 0, 0x00000000, 0x00000001 },
5284                 { 0x5c04, 0, 0x00000000, 0x0003000f },
5285                 { 0x5c08, 0, 0x00000003, 0x00000000 },
5286                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5287                 { 0x5c10, 0, 0x00000000, 0xffffffff },
5288                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5289                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5290                 { 0x5c88, 0, 0x00000000, 0x00077373 },
5291                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5292
5293                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5294                 { 0x680c, 0, 0xffffffff, 0x00000000 },
5295                 { 0x6810, 0, 0xffffffff, 0x00000000 },
5296                 { 0x6814, 0, 0xffffffff, 0x00000000 },
5297                 { 0x6818, 0, 0xffffffff, 0x00000000 },
5298                 { 0x681c, 0, 0xffffffff, 0x00000000 },
5299                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5300                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5301                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5302                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5303                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5304                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5305                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5306                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5307                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5308                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5309                 { 0x684c, 0, 0xffffffff, 0x00000000 },
5310                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5311                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5312                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5313                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5314                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5315                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5316
5317                 { 0xffff, 0, 0x00000000, 0x00000000 },
5318         };
5319
5320         ret = 0;
5321         is_5709 = 0;
5322         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5323                 is_5709 = 1;
5324
5325         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5326                 u32 offset, rw_mask, ro_mask, save_val, val;
5327                 u16 flags = reg_tbl[i].flags;
5328
5329                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5330                         continue;
5331
5332                 offset = (u32) reg_tbl[i].offset;
5333                 rw_mask = reg_tbl[i].rw_mask;
5334                 ro_mask = reg_tbl[i].ro_mask;
5335
5336                 save_val = readl(bp->regview + offset);
5337
5338                 writel(0, bp->regview + offset);
5339
5340                 val = readl(bp->regview + offset);
5341                 if ((val & rw_mask) != 0) {
5342                         goto reg_test_err;
5343                 }
5344
5345                 if ((val & ro_mask) != (save_val & ro_mask)) {
5346                         goto reg_test_err;
5347                 }
5348
5349                 writel(0xffffffff, bp->regview + offset);
5350
5351                 val = readl(bp->regview + offset);
5352                 if ((val & rw_mask) != rw_mask) {
5353                         goto reg_test_err;
5354                 }
5355
5356                 if ((val & ro_mask) != (save_val & ro_mask)) {
5357                         goto reg_test_err;
5358                 }
5359
5360                 writel(save_val, bp->regview + offset);
5361                 continue;
5362
5363 reg_test_err:
5364                 writel(save_val, bp->regview + offset);
5365                 ret = -ENODEV;
5366                 break;
5367         }
5368         return ret;
5369 }
5370
5371 static int
5372 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5373 {
5374         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5375                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5376         int i;
5377
5378         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5379                 u32 offset;
5380
5381                 for (offset = 0; offset < size; offset += 4) {
5382
5383                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5384
5385                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5386                                 test_pattern[i]) {
5387                                 return -ENODEV;
5388                         }
5389                 }
5390         }
5391         return 0;
5392 }
5393
5394 static int
5395 bnx2_test_memory(struct bnx2 *bp)
5396 {
5397         int ret = 0;
5398         int i;
5399         static struct mem_entry {
5400                 u32   offset;
5401                 u32   len;
5402         } mem_tbl_5706[] = {
5403                 { 0x60000,  0x4000 },
5404                 { 0xa0000,  0x3000 },
5405                 { 0xe0000,  0x4000 },
5406                 { 0x120000, 0x4000 },
5407                 { 0x1a0000, 0x4000 },
5408                 { 0x160000, 0x4000 },
5409                 { 0xffffffff, 0    },
5410         },
5411         mem_tbl_5709[] = {
5412                 { 0x60000,  0x4000 },
5413                 { 0xa0000,  0x3000 },
5414                 { 0xe0000,  0x4000 },
5415                 { 0x120000, 0x4000 },
5416                 { 0x1a0000, 0x4000 },
5417                 { 0xffffffff, 0    },
5418         };
5419         struct mem_entry *mem_tbl;
5420
5421         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5422                 mem_tbl = mem_tbl_5709;
5423         else
5424                 mem_tbl = mem_tbl_5706;
5425
5426         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5427                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5428                         mem_tbl[i].len)) != 0) {
5429                         return ret;
5430                 }
5431         }
5432
5433         return ret;
5434 }
5435
5436 #define BNX2_MAC_LOOPBACK       0
5437 #define BNX2_PHY_LOOPBACK       1
5438
5439 static int
5440 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5441 {
5442         unsigned int pkt_size, num_pkts, i;
5443         struct sk_buff *skb, *rx_skb;
5444         unsigned char *packet;
5445         u16 rx_start_idx, rx_idx;
5446         dma_addr_t map;
5447         struct tx_bd *txbd;
5448         struct sw_bd *rx_buf;
5449         struct l2_fhdr *rx_hdr;
5450         int ret = -ENODEV;
5451         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5452         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5453         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5454
5455         tx_napi = bnapi;
5456
5457         txr = &tx_napi->tx_ring;
5458         rxr = &bnapi->rx_ring;
5459         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5460                 bp->loopback = MAC_LOOPBACK;
5461                 bnx2_set_mac_loopback(bp);
5462         }
5463         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5464                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5465                         return 0;
5466
5467                 bp->loopback = PHY_LOOPBACK;
5468                 bnx2_set_phy_loopback(bp);
5469         }
5470         else
5471                 return -EINVAL;
5472
5473         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5474         skb = netdev_alloc_skb(bp->dev, pkt_size);
5475         if (!skb)
5476                 return -ENOMEM;
5477         packet = skb_put(skb, pkt_size);
5478         memcpy(packet, bp->dev->dev_addr, 6);
5479         memset(packet + 6, 0x0, 8);
5480         for (i = 14; i < pkt_size; i++)
5481                 packet[i] = (unsigned char) (i & 0xff);
5482
5483         if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5484                 dev_kfree_skb(skb);
5485                 return -EIO;
5486         }
5487         map = skb_shinfo(skb)->dma_maps[0];
5488
5489         REG_WR(bp, BNX2_HC_COMMAND,
5490                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5491
5492         REG_RD(bp, BNX2_HC_COMMAND);
5493
5494         udelay(5);
5495         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5496
5497         num_pkts = 0;
5498
5499         txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5500
5501         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5502         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5503         txbd->tx_bd_mss_nbytes = pkt_size;
5504         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5505
5506         num_pkts++;
5507         txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5508         txr->tx_prod_bseq += pkt_size;
5509
5510         REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5511         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5512
5513         udelay(100);
5514
5515         REG_WR(bp, BNX2_HC_COMMAND,
5516                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5517
5518         REG_RD(bp, BNX2_HC_COMMAND);
5519
5520         udelay(5);
5521
5522         skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5523         dev_kfree_skb(skb);
5524
5525         if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5526                 goto loopback_test_done;
5527
5528         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5529         if (rx_idx != rx_start_idx + num_pkts) {
5530                 goto loopback_test_done;
5531         }
5532
5533         rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5534         rx_skb = rx_buf->skb;
5535
5536         rx_hdr = (struct l2_fhdr *) rx_skb->data;
5537         skb_reserve(rx_skb, BNX2_RX_OFFSET);
5538
5539         pci_dma_sync_single_for_cpu(bp->pdev,
5540                 pci_unmap_addr(rx_buf, mapping),
5541                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5542
5543         if (rx_hdr->l2_fhdr_status &
5544                 (L2_FHDR_ERRORS_BAD_CRC |
5545                 L2_FHDR_ERRORS_PHY_DECODE |
5546                 L2_FHDR_ERRORS_ALIGNMENT |
5547                 L2_FHDR_ERRORS_TOO_SHORT |
5548                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5549
5550                 goto loopback_test_done;
5551         }
5552
5553         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5554                 goto loopback_test_done;
5555         }
5556
5557         for (i = 14; i < pkt_size; i++) {
5558                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5559                         goto loopback_test_done;
5560                 }
5561         }
5562
5563         ret = 0;
5564
5565 loopback_test_done:
5566         bp->loopback = 0;
5567         return ret;
5568 }
5569
5570 #define BNX2_MAC_LOOPBACK_FAILED        1
5571 #define BNX2_PHY_LOOPBACK_FAILED        2
5572 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5573                                          BNX2_PHY_LOOPBACK_FAILED)
5574
5575 static int
5576 bnx2_test_loopback(struct bnx2 *bp)
5577 {
5578         int rc = 0;
5579
5580         if (!netif_running(bp->dev))
5581                 return BNX2_LOOPBACK_FAILED;
5582
5583         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5584         spin_lock_bh(&bp->phy_lock);
5585         bnx2_init_phy(bp, 1);
5586         spin_unlock_bh(&bp->phy_lock);
5587         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5588                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5589         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5590                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5591         return rc;
5592 }
5593
5594 #define NVRAM_SIZE 0x200
5595 #define CRC32_RESIDUAL 0xdebb20e3
5596
5597 static int
5598 bnx2_test_nvram(struct bnx2 *bp)
5599 {
5600         __be32 buf[NVRAM_SIZE / 4];
5601         u8 *data = (u8 *) buf;
5602         int rc = 0;
5603         u32 magic, csum;
5604
5605         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5606                 goto test_nvram_done;
5607
5608         magic = be32_to_cpu(buf[0]);
5609         if (magic != 0x669955aa) {
5610                 rc = -ENODEV;
5611                 goto test_nvram_done;
5612         }
5613
5614         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5615                 goto test_nvram_done;
5616
5617         csum = ether_crc_le(0x100, data);
5618         if (csum != CRC32_RESIDUAL) {
5619                 rc = -ENODEV;
5620                 goto test_nvram_done;
5621         }
5622
5623         csum = ether_crc_le(0x100, data + 0x100);
5624         if (csum != CRC32_RESIDUAL) {
5625                 rc = -ENODEV;
5626         }
5627
5628 test_nvram_done:
5629         return rc;
5630 }
5631
5632 static int
5633 bnx2_test_link(struct bnx2 *bp)
5634 {
5635         u32 bmsr;
5636
5637         if (!netif_running(bp->dev))
5638                 return -ENODEV;
5639
5640         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5641                 if (bp->link_up)
5642                         return 0;
5643                 return -ENODEV;
5644         }
5645         spin_lock_bh(&bp->phy_lock);
5646         bnx2_enable_bmsr1(bp);
5647         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5648         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5649         bnx2_disable_bmsr1(bp);
5650         spin_unlock_bh(&bp->phy_lock);
5651
5652         if (bmsr & BMSR_LSTATUS) {
5653                 return 0;
5654         }
5655         return -ENODEV;
5656 }
5657
5658 static int
5659 bnx2_test_intr(struct bnx2 *bp)
5660 {
5661         int i;
5662         u16 status_idx;
5663
5664         if (!netif_running(bp->dev))
5665                 return -ENODEV;
5666
5667         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5668
5669         /* This register is not touched during run-time. */
5670         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5671         REG_RD(bp, BNX2_HC_COMMAND);
5672
5673         for (i = 0; i < 10; i++) {
5674                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5675                         status_idx) {
5676
5677                         break;
5678                 }
5679
5680                 msleep_interruptible(10);
5681         }
5682         if (i < 10)
5683                 return 0;
5684
5685         return -ENODEV;
5686 }
5687
5688 /* Determining link for parallel detection. */
5689 static int
5690 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5691 {
5692         u32 mode_ctl, an_dbg, exp;
5693
5694         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5695                 return 0;
5696
5697         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5698         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5699
5700         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5701                 return 0;
5702
5703         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5704         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5705         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5706
5707         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5708                 return 0;
5709
5710         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5711         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5712         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5713
5714         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5715                 return 0;
5716
5717         return 1;
5718 }
5719
5720 static void
5721 bnx2_5706_serdes_timer(struct bnx2 *bp)
5722 {
5723         int check_link = 1;
5724
5725         spin_lock(&bp->phy_lock);
5726         if (bp->serdes_an_pending) {
5727                 bp->serdes_an_pending--;
5728                 check_link = 0;
5729         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5730                 u32 bmcr;
5731
5732                 bp->current_interval = BNX2_TIMER_INTERVAL;
5733
5734                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5735
5736                 if (bmcr & BMCR_ANENABLE) {
5737                         if (bnx2_5706_serdes_has_link(bp)) {
5738                                 bmcr &= ~BMCR_ANENABLE;
5739                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5740                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5741                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5742                         }
5743                 }
5744         }
5745         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5746                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5747                 u32 phy2;
5748
5749                 bnx2_write_phy(bp, 0x17, 0x0f01);
5750                 bnx2_read_phy(bp, 0x15, &phy2);
5751                 if (phy2 & 0x20) {
5752                         u32 bmcr;
5753
5754                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5755                         bmcr |= BMCR_ANENABLE;
5756                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5757
5758                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5759                 }
5760         } else
5761                 bp->current_interval = BNX2_TIMER_INTERVAL;
5762
5763         if (check_link) {
5764                 u32 val;
5765
5766                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5767                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5768                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5769
5770                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5771                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5772                                 bnx2_5706s_force_link_dn(bp, 1);
5773                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5774                         } else
5775                                 bnx2_set_link(bp);
5776                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5777                         bnx2_set_link(bp);
5778         }
5779         spin_unlock(&bp->phy_lock);
5780 }
5781
5782 static void
5783 bnx2_5708_serdes_timer(struct bnx2 *bp)
5784 {
5785         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5786                 return;
5787
5788         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5789                 bp->serdes_an_pending = 0;
5790                 return;
5791         }
5792
5793         spin_lock(&bp->phy_lock);
5794         if (bp->serdes_an_pending)
5795                 bp->serdes_an_pending--;
5796         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5797                 u32 bmcr;
5798
5799                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5800                 if (bmcr & BMCR_ANENABLE) {
5801                         bnx2_enable_forced_2g5(bp);
5802                         bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
5803                 } else {
5804                         bnx2_disable_forced_2g5(bp);
5805                         bp->serdes_an_pending = 2;
5806                         bp->current_interval = BNX2_TIMER_INTERVAL;
5807                 }
5808
5809         } else
5810                 bp->current_interval = BNX2_TIMER_INTERVAL;
5811
5812         spin_unlock(&bp->phy_lock);
5813 }
5814
5815 static void
5816 bnx2_timer(unsigned long data)
5817 {
5818         struct bnx2 *bp = (struct bnx2 *) data;
5819
5820         if (!netif_running(bp->dev))
5821                 return;
5822
5823         if (atomic_read(&bp->intr_sem) != 0)
5824                 goto bnx2_restart_timer;
5825
5826         if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
5827              BNX2_FLAG_USING_MSI)
5828                 bnx2_chk_missed_msi(bp);
5829
5830         bnx2_send_heart_beat(bp);
5831
5832         bp->stats_blk->stat_FwRxDrop =
5833                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5834
5835         /* workaround occasional corrupted counters */
5836         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5837                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5838                                             BNX2_HC_COMMAND_STATS_NOW);
5839
5840         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5841                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5842                         bnx2_5706_serdes_timer(bp);
5843                 else
5844                         bnx2_5708_serdes_timer(bp);
5845         }
5846
5847 bnx2_restart_timer:
5848         mod_timer(&bp->timer, jiffies + bp->current_interval);
5849 }
5850
5851 static int
5852 bnx2_request_irq(struct bnx2 *bp)
5853 {
5854         unsigned long flags;
5855         struct bnx2_irq *irq;
5856         int rc = 0, i;
5857
5858         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5859                 flags = 0;
5860         else
5861                 flags = IRQF_SHARED;
5862
5863         for (i = 0; i < bp->irq_nvecs; i++) {
5864                 irq = &bp->irq_tbl[i];
5865                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5866                                  &bp->bnx2_napi[i]);
5867                 if (rc)
5868                         break;
5869                 irq->requested = 1;
5870         }
5871         return rc;
5872 }
5873
5874 static void
5875 bnx2_free_irq(struct bnx2 *bp)
5876 {
5877         struct bnx2_irq *irq;
5878         int i;
5879
5880         for (i = 0; i < bp->irq_nvecs; i++) {
5881                 irq = &bp->irq_tbl[i];
5882                 if (irq->requested)
5883                         free_irq(irq->vector, &bp->bnx2_napi[i]);
5884                 irq->requested = 0;
5885         }
5886         if (bp->flags & BNX2_FLAG_USING_MSI)
5887                 pci_disable_msi(bp->pdev);
5888         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5889                 pci_disable_msix(bp->pdev);
5890
5891         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5892 }
5893
5894 static void
5895 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5896 {
5897         int i, rc;
5898         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5899         struct net_device *dev = bp->dev;
5900         const int len = sizeof(bp->irq_tbl[0].name);
5901
5902         bnx2_setup_msix_tbl(bp);
5903         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5904         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5905         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5906
5907         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5908                 msix_ent[i].entry = i;
5909                 msix_ent[i].vector = 0;
5910         }
5911
5912         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5913         if (rc != 0)
5914                 return;
5915
5916         bp->irq_nvecs = msix_vecs;
5917         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5918         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5919                 bp->irq_tbl[i].vector = msix_ent[i].vector;
5920                 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
5921                 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5922         }
5923 }
5924
5925 static void
5926 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5927 {
5928         int cpus = num_online_cpus();
5929         int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5930
5931         bp->irq_tbl[0].handler = bnx2_interrupt;
5932         strcpy(bp->irq_tbl[0].name, bp->dev->name);
5933         bp->irq_nvecs = 1;
5934         bp->irq_tbl[0].vector = bp->pdev->irq;
5935
5936         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5937                 bnx2_enable_msix(bp, msix_vecs);
5938
5939         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5940             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5941                 if (pci_enable_msi(bp->pdev) == 0) {
5942                         bp->flags |= BNX2_FLAG_USING_MSI;
5943                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5944                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5945                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5946                         } else
5947                                 bp->irq_tbl[0].handler = bnx2_msi;
5948
5949                         bp->irq_tbl[0].vector = bp->pdev->irq;
5950                 }
5951         }
5952
5953         bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5954         bp->dev->real_num_tx_queues = bp->num_tx_rings;
5955
5956         bp->num_rx_rings = bp->irq_nvecs;
5957 }
5958
5959 /* Called with rtnl_lock */
5960 static int
5961 bnx2_open(struct net_device *dev)
5962 {
5963         struct bnx2 *bp = netdev_priv(dev);
5964         int rc;
5965
5966         netif_carrier_off(dev);
5967
5968         bnx2_set_power_state(bp, PCI_D0);
5969         bnx2_disable_int(bp);
5970
5971         bnx2_setup_int_mode(bp, disable_msi);
5972         bnx2_napi_enable(bp);
5973         rc = bnx2_alloc_mem(bp);
5974         if (rc)
5975                 goto open_err;
5976
5977         rc = bnx2_request_irq(bp);
5978         if (rc)
5979                 goto open_err;
5980
5981         rc = bnx2_init_nic(bp, 1);
5982         if (rc)
5983                 goto open_err;
5984
5985         mod_timer(&bp->timer, jiffies + bp->current_interval);
5986
5987         atomic_set(&bp->intr_sem, 0);
5988
5989         bnx2_enable_int(bp);
5990
5991         if (bp->flags & BNX2_FLAG_USING_MSI) {
5992                 /* Test MSI to make sure it is working
5993                  * If MSI test fails, go back to INTx mode
5994                  */
5995                 if (bnx2_test_intr(bp) != 0) {
5996                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5997                                " using MSI, switching to INTx mode. Please"
5998                                " report this failure to the PCI maintainer"
5999                                " and include system chipset information.\n",
6000                                bp->dev->name);
6001
6002                         bnx2_disable_int(bp);
6003                         bnx2_free_irq(bp);
6004
6005                         bnx2_setup_int_mode(bp, 1);
6006
6007                         rc = bnx2_init_nic(bp, 0);
6008
6009                         if (!rc)
6010                                 rc = bnx2_request_irq(bp);
6011
6012                         if (rc) {
6013                                 del_timer_sync(&bp->timer);
6014                                 goto open_err;
6015                         }
6016                         bnx2_enable_int(bp);
6017                 }
6018         }
6019         if (bp->flags & BNX2_FLAG_USING_MSI)
6020                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
6021         else if (bp->flags & BNX2_FLAG_USING_MSIX)
6022                 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
6023
6024         netif_tx_start_all_queues(dev);
6025
6026         return 0;
6027
6028 open_err:
6029         bnx2_napi_disable(bp);
6030         bnx2_free_skbs(bp);
6031         bnx2_free_irq(bp);
6032         bnx2_free_mem(bp);
6033         return rc;
6034 }
6035
6036 static void
6037 bnx2_reset_task(struct work_struct *work)
6038 {
6039         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6040
6041         if (!netif_running(bp->dev))
6042                 return;
6043
6044         bnx2_netif_stop(bp);
6045
6046         bnx2_init_nic(bp, 1);
6047