728b0d736929d484fa318f4b5e8e3a2dd4a74506
[linux-2.6.git] / drivers / net / benet / be_cmds.h
1 /*
2  * Copyright (C) 2005 - 2010 ServerEngines
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation.  The full GNU General
8  * Public License is included in this distribution in the file called COPYING.
9  *
10  * Contact Information:
11  * linux-drivers@serverengines.com
12  *
13  * ServerEngines
14  * 209 N. Fair Oaks Ave
15  * Sunnyvale, CA 94085
16  */
17
18 /*
19  * The driver sends configuration and managements command requests to the
20  * firmware in the BE. These requests are communicated to the processor
21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22  * WRB inside a MAILBOX.
23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24  */
25
26 struct be_sge {
27         u32 pa_lo;
28         u32 pa_hi;
29         u32 len;
30 };
31
32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
35 struct be_mcc_wrb {
36         u32 embedded;           /* dword 0 */
37         u32 payload_length;     /* dword 1 */
38         u32 tag0;               /* dword 2 */
39         u32 tag1;               /* dword 3 */
40         u32 rsvd;               /* dword 4 */
41         union {
42                 u8 embedded_payload[236]; /* used by embedded cmds */
43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
44         } payload;
45 };
46
47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
51
52 /* Completion Status */
53 enum {
54         MCC_STATUS_SUCCESS = 0x0,
55 /* The client does not have sufficient privileges to execute the command */
56         MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57 /* A parameter in the command was invalid. */
58         MCC_STATUS_INVALID_PARAMETER = 0x2,
59 /* There are insufficient chip resources to execute the command */
60         MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61 /* The command is completing because the queue was getting flushed */
62         MCC_STATUS_QUEUE_FLUSHING = 0x4,
63 /* The command is completing with a DMA error */
64         MCC_STATUS_DMA_FAILED = 0x5,
65         MCC_STATUS_NOT_SUPPORTED = 66
66 };
67
68 #define CQE_STATUS_COMPL_MASK           0xFFFF
69 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
70 #define CQE_STATUS_EXTD_MASK            0xFFFF
71 #define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
72
73 struct be_mcc_compl {
74         u32 status;             /* dword 0 */
75         u32 tag0;               /* dword 1 */
76         u32 tag1;               /* dword 2 */
77         u32 flags;              /* dword 3 */
78 };
79
80 /* When the async bit of mcc_compl is set, the last 4 bytes of
81  * mcc_compl is interpreted as follows:
82  */
83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
84 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
85 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
86 struct be_async_event_trailer {
87         u32 code;
88 };
89
90 enum {
91         ASYNC_EVENT_LINK_DOWN   = 0x0,
92         ASYNC_EVENT_LINK_UP     = 0x1
93 };
94
95 /* When the event code of an async trailer is link-state, the mcc_compl
96  * must be interpreted as follows
97  */
98 struct be_async_event_link_state {
99         u8 physical_port;
100         u8 port_link_status;
101         u8 port_duplex;
102         u8 port_speed;
103         u8 port_fault;
104         u8 rsvd0[7];
105         struct be_async_event_trailer trailer;
106 } __packed;
107
108 struct be_mcc_mailbox {
109         struct be_mcc_wrb wrb;
110         struct be_mcc_compl compl;
111 };
112
113 #define CMD_SUBSYSTEM_COMMON    0x1
114 #define CMD_SUBSYSTEM_ETH       0x3
115 #define CMD_SUBSYSTEM_LOWLEVEL  0xb
116
117 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
118 #define OPCODE_COMMON_NTWK_MAC_SET                      2
119 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
120 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
121 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
122 #define OPCODE_COMMON_READ_FLASHROM                     6
123 #define OPCODE_COMMON_WRITE_FLASHROM                    7
124 #define OPCODE_COMMON_CQ_CREATE                         12
125 #define OPCODE_COMMON_EQ_CREATE                         13
126 #define OPCODE_COMMON_MCC_CREATE                        21
127 #define OPCODE_COMMON_SEEPROM_READ                      30
128 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
129 #define OPCODE_COMMON_GET_FW_VERSION                    35
130 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
131 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
132 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
133 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
134 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
135 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
136 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
137 #define OPCODE_COMMON_MCC_DESTROY                       53
138 #define OPCODE_COMMON_CQ_DESTROY                        54
139 #define OPCODE_COMMON_EQ_DESTROY                        55
140 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
141 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
142 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
143 #define OPCODE_COMMON_FUNCTION_RESET                    61
144 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON             69
145 #define OPCODE_COMMON_GET_BEACON_STATE                  70
146 #define OPCODE_COMMON_READ_TRANSRECV_DATA               73
147
148 #define OPCODE_ETH_ACPI_CONFIG                          2
149 #define OPCODE_ETH_PROMISCUOUS                          3
150 #define OPCODE_ETH_GET_STATISTICS                       4
151 #define OPCODE_ETH_TX_CREATE                            7
152 #define OPCODE_ETH_RX_CREATE                            8
153 #define OPCODE_ETH_TX_DESTROY                           9
154 #define OPCODE_ETH_RX_DESTROY                           10
155 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG                12
156
157 #define OPCODE_LOWLEVEL_HOST_DDR_DMA                    17
158 #define OPCODE_LOWLEVEL_LOOPBACK_TEST                   18
159 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE               19
160
161 struct be_cmd_req_hdr {
162         u8 opcode;              /* dword 0 */
163         u8 subsystem;           /* dword 0 */
164         u8 port_number;         /* dword 0 */
165         u8 domain;              /* dword 0 */
166         u32 timeout;            /* dword 1 */
167         u32 request_length;     /* dword 2 */
168         u8 version;             /* dword 3 */
169         u8 rsvd[3];             /* dword 3 */
170 };
171
172 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
173 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
174 struct be_cmd_resp_hdr {
175         u32 info;               /* dword 0 */
176         u32 status;             /* dword 1 */
177         u32 response_length;    /* dword 2 */
178         u32 actual_resp_len;    /* dword 3 */
179 };
180
181 struct phys_addr {
182         u32 lo;
183         u32 hi;
184 };
185
186 /**************************
187  * BE Command definitions *
188  **************************/
189
190 /* Pseudo amap definition in which each bit of the actual structure is defined
191  * as a byte: used to calculate offset/shift/mask of each field */
192 struct amap_eq_context {
193         u8 cidx[13];            /* dword 0*/
194         u8 rsvd0[3];            /* dword 0*/
195         u8 epidx[13];           /* dword 0*/
196         u8 valid;               /* dword 0*/
197         u8 rsvd1;               /* dword 0*/
198         u8 size;                /* dword 0*/
199         u8 pidx[13];            /* dword 1*/
200         u8 rsvd2[3];            /* dword 1*/
201         u8 pd[10];              /* dword 1*/
202         u8 count[3];            /* dword 1*/
203         u8 solevent;            /* dword 1*/
204         u8 stalled;             /* dword 1*/
205         u8 armed;               /* dword 1*/
206         u8 rsvd3[4];            /* dword 2*/
207         u8 func[8];             /* dword 2*/
208         u8 rsvd4;               /* dword 2*/
209         u8 delaymult[10];       /* dword 2*/
210         u8 rsvd5[2];            /* dword 2*/
211         u8 phase[2];            /* dword 2*/
212         u8 nodelay;             /* dword 2*/
213         u8 rsvd6[4];            /* dword 2*/
214         u8 rsvd7[32];           /* dword 3*/
215 } __packed;
216
217 struct be_cmd_req_eq_create {
218         struct be_cmd_req_hdr hdr;
219         u16 num_pages;          /* sword */
220         u16 rsvd0;              /* sword */
221         u8 context[sizeof(struct amap_eq_context) / 8];
222         struct phys_addr pages[8];
223 } __packed;
224
225 struct be_cmd_resp_eq_create {
226         struct be_cmd_resp_hdr resp_hdr;
227         u16 eq_id;              /* sword */
228         u16 rsvd0;              /* sword */
229 } __packed;
230
231 /******************** Mac query ***************************/
232 enum {
233         MAC_ADDRESS_TYPE_STORAGE = 0x0,
234         MAC_ADDRESS_TYPE_NETWORK = 0x1,
235         MAC_ADDRESS_TYPE_PD = 0x2,
236         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
237 };
238
239 struct mac_addr {
240         u16 size_of_struct;
241         u8 addr[ETH_ALEN];
242 } __packed;
243
244 struct be_cmd_req_mac_query {
245         struct be_cmd_req_hdr hdr;
246         u8 type;
247         u8 permanent;
248         u16 if_id;
249 } __packed;
250
251 struct be_cmd_resp_mac_query {
252         struct be_cmd_resp_hdr hdr;
253         struct mac_addr mac;
254 };
255
256 /******************** PMac Add ***************************/
257 struct be_cmd_req_pmac_add {
258         struct be_cmd_req_hdr hdr;
259         u32 if_id;
260         u8 mac_address[ETH_ALEN];
261         u8 rsvd0[2];
262 } __packed;
263
264 struct be_cmd_resp_pmac_add {
265         struct be_cmd_resp_hdr hdr;
266         u32 pmac_id;
267 };
268
269 /******************** PMac Del ***************************/
270 struct be_cmd_req_pmac_del {
271         struct be_cmd_req_hdr hdr;
272         u32 if_id;
273         u32 pmac_id;
274 };
275
276 /******************** Create CQ ***************************/
277 /* Pseudo amap definition in which each bit of the actual structure is defined
278  * as a byte: used to calculate offset/shift/mask of each field */
279 struct amap_cq_context {
280         u8 cidx[11];            /* dword 0*/
281         u8 rsvd0;               /* dword 0*/
282         u8 coalescwm[2];        /* dword 0*/
283         u8 nodelay;             /* dword 0*/
284         u8 epidx[11];           /* dword 0*/
285         u8 rsvd1;               /* dword 0*/
286         u8 count[2];            /* dword 0*/
287         u8 valid;               /* dword 0*/
288         u8 solevent;            /* dword 0*/
289         u8 eventable;           /* dword 0*/
290         u8 pidx[11];            /* dword 1*/
291         u8 rsvd2;               /* dword 1*/
292         u8 pd[10];              /* dword 1*/
293         u8 eqid[8];             /* dword 1*/
294         u8 stalled;             /* dword 1*/
295         u8 armed;               /* dword 1*/
296         u8 rsvd3[4];            /* dword 2*/
297         u8 func[8];             /* dword 2*/
298         u8 rsvd4[20];           /* dword 2*/
299         u8 rsvd5[32];           /* dword 3*/
300 } __packed;
301
302 struct be_cmd_req_cq_create {
303         struct be_cmd_req_hdr hdr;
304         u16 num_pages;
305         u16 rsvd0;
306         u8 context[sizeof(struct amap_cq_context) / 8];
307         struct phys_addr pages[8];
308 } __packed;
309
310 struct be_cmd_resp_cq_create {
311         struct be_cmd_resp_hdr hdr;
312         u16 cq_id;
313         u16 rsvd0;
314 } __packed;
315
316 /******************** Create MCCQ ***************************/
317 /* Pseudo amap definition in which each bit of the actual structure is defined
318  * as a byte: used to calculate offset/shift/mask of each field */
319 struct amap_mcc_context {
320         u8 con_index[14];
321         u8 rsvd0[2];
322         u8 ring_size[4];
323         u8 fetch_wrb;
324         u8 fetch_r2t;
325         u8 cq_id[10];
326         u8 prod_index[14];
327         u8 fid[8];
328         u8 pdid[9];
329         u8 valid;
330         u8 rsvd1[32];
331         u8 rsvd2[32];
332 } __packed;
333
334 struct be_cmd_req_mcc_create {
335         struct be_cmd_req_hdr hdr;
336         u16 num_pages;
337         u16 rsvd0;
338         u8 context[sizeof(struct amap_mcc_context) / 8];
339         struct phys_addr pages[8];
340 } __packed;
341
342 struct be_cmd_resp_mcc_create {
343         struct be_cmd_resp_hdr hdr;
344         u16 id;
345         u16 rsvd0;
346 } __packed;
347
348 /******************** Create TxQ ***************************/
349 #define BE_ETH_TX_RING_TYPE_STANDARD            2
350 #define BE_ULP1_NUM                             1
351
352 /* Pseudo amap definition in which each bit of the actual structure is defined
353  * as a byte: used to calculate offset/shift/mask of each field */
354 struct amap_tx_context {
355         u8 rsvd0[16];           /* dword 0 */
356         u8 tx_ring_size[4];     /* dword 0 */
357         u8 rsvd1[26];           /* dword 0 */
358         u8 pci_func_id[8];      /* dword 1 */
359         u8 rsvd2[9];            /* dword 1 */
360         u8 ctx_valid;           /* dword 1 */
361         u8 cq_id_send[16];      /* dword 2 */
362         u8 rsvd3[16];           /* dword 2 */
363         u8 rsvd4[32];           /* dword 3 */
364         u8 rsvd5[32];           /* dword 4 */
365         u8 rsvd6[32];           /* dword 5 */
366         u8 rsvd7[32];           /* dword 6 */
367         u8 rsvd8[32];           /* dword 7 */
368         u8 rsvd9[32];           /* dword 8 */
369         u8 rsvd10[32];          /* dword 9 */
370         u8 rsvd11[32];          /* dword 10 */
371         u8 rsvd12[32];          /* dword 11 */
372         u8 rsvd13[32];          /* dword 12 */
373         u8 rsvd14[32];          /* dword 13 */
374         u8 rsvd15[32];          /* dword 14 */
375         u8 rsvd16[32];          /* dword 15 */
376 } __packed;
377
378 struct be_cmd_req_eth_tx_create {
379         struct be_cmd_req_hdr hdr;
380         u8 num_pages;
381         u8 ulp_num;
382         u8 type;
383         u8 bound_port;
384         u8 context[sizeof(struct amap_tx_context) / 8];
385         struct phys_addr pages[8];
386 } __packed;
387
388 struct be_cmd_resp_eth_tx_create {
389         struct be_cmd_resp_hdr hdr;
390         u16 cid;
391         u16 rsvd0;
392 } __packed;
393
394 /******************** Create RxQ ***************************/
395 struct be_cmd_req_eth_rx_create {
396         struct be_cmd_req_hdr hdr;
397         u16 cq_id;
398         u8 frag_size;
399         u8 num_pages;
400         struct phys_addr pages[2];
401         u32 interface_id;
402         u16 max_frame_size;
403         u16 rsvd0;
404         u32 rss_queue;
405 } __packed;
406
407 struct be_cmd_resp_eth_rx_create {
408         struct be_cmd_resp_hdr hdr;
409         u16 id;
410         u8 cpu_id;
411         u8 rsvd0;
412 } __packed;
413
414 /******************** Q Destroy  ***************************/
415 /* Type of Queue to be destroyed */
416 enum {
417         QTYPE_EQ = 1,
418         QTYPE_CQ,
419         QTYPE_TXQ,
420         QTYPE_RXQ,
421         QTYPE_MCCQ
422 };
423
424 struct be_cmd_req_q_destroy {
425         struct be_cmd_req_hdr hdr;
426         u16 id;
427         u16 bypass_flush;       /* valid only for rx q destroy */
428 } __packed;
429
430 /************ I/f Create (it's actually I/f Config Create)**********/
431
432 /* Capability flags for the i/f */
433 enum be_if_flags {
434         BE_IF_FLAGS_RSS = 0x4,
435         BE_IF_FLAGS_PROMISCUOUS = 0x8,
436         BE_IF_FLAGS_BROADCAST = 0x10,
437         BE_IF_FLAGS_UNTAGGED = 0x20,
438         BE_IF_FLAGS_ULP = 0x40,
439         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
440         BE_IF_FLAGS_VLAN = 0x100,
441         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
442         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
443         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
444 };
445
446 /* An RX interface is an object with one or more MAC addresses and
447  * filtering capabilities. */
448 struct be_cmd_req_if_create {
449         struct be_cmd_req_hdr hdr;
450         u32 version;            /* ignore currently */
451         u32 capability_flags;
452         u32 enable_flags;
453         u8 mac_addr[ETH_ALEN];
454         u8 rsvd0;
455         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
456         u32 vlan_tag;    /* not used currently */
457 } __packed;
458
459 struct be_cmd_resp_if_create {
460         struct be_cmd_resp_hdr hdr;
461         u32 interface_id;
462         u32 pmac_id;
463 };
464
465 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
466 struct be_cmd_req_if_destroy {
467         struct be_cmd_req_hdr hdr;
468         u32 interface_id;
469 };
470
471 /*************** HW Stats Get **********************************/
472 struct be_port_rxf_stats {
473         u32 rx_bytes_lsd;       /* dword 0*/
474         u32 rx_bytes_msd;       /* dword 1*/
475         u32 rx_total_frames;    /* dword 2*/
476         u32 rx_unicast_frames;  /* dword 3*/
477         u32 rx_multicast_frames;        /* dword 4*/
478         u32 rx_broadcast_frames;        /* dword 5*/
479         u32 rx_crc_errors;      /* dword 6*/
480         u32 rx_alignment_symbol_errors; /* dword 7*/
481         u32 rx_pause_frames;    /* dword 8*/
482         u32 rx_control_frames;  /* dword 9*/
483         u32 rx_in_range_errors; /* dword 10*/
484         u32 rx_out_range_errors;        /* dword 11*/
485         u32 rx_frame_too_long;  /* dword 12*/
486         u32 rx_address_match_errors;    /* dword 13*/
487         u32 rx_vlan_mismatch;   /* dword 14*/
488         u32 rx_dropped_too_small;       /* dword 15*/
489         u32 rx_dropped_too_short;       /* dword 16*/
490         u32 rx_dropped_header_too_small;        /* dword 17*/
491         u32 rx_dropped_tcp_length;      /* dword 18*/
492         u32 rx_dropped_runt;    /* dword 19*/
493         u32 rx_64_byte_packets; /* dword 20*/
494         u32 rx_65_127_byte_packets;     /* dword 21*/
495         u32 rx_128_256_byte_packets;    /* dword 22*/
496         u32 rx_256_511_byte_packets;    /* dword 23*/
497         u32 rx_512_1023_byte_packets;   /* dword 24*/
498         u32 rx_1024_1518_byte_packets;  /* dword 25*/
499         u32 rx_1519_2047_byte_packets;  /* dword 26*/
500         u32 rx_2048_4095_byte_packets;  /* dword 27*/
501         u32 rx_4096_8191_byte_packets;  /* dword 28*/
502         u32 rx_8192_9216_byte_packets;  /* dword 29*/
503         u32 rx_ip_checksum_errs;        /* dword 30*/
504         u32 rx_tcp_checksum_errs;       /* dword 31*/
505         u32 rx_udp_checksum_errs;       /* dword 32*/
506         u32 rx_non_rss_packets; /* dword 33*/
507         u32 rx_ipv4_packets;    /* dword 34*/
508         u32 rx_ipv6_packets;    /* dword 35*/
509         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
510         u32 rx_ipv4_bytes_msd;  /* dword 37*/
511         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
512         u32 rx_ipv6_bytes_msd;  /* dword 39*/
513         u32 rx_chute1_packets;  /* dword 40*/
514         u32 rx_chute2_packets;  /* dword 41*/
515         u32 rx_chute3_packets;  /* dword 42*/
516         u32 rx_management_packets;      /* dword 43*/
517         u32 rx_switched_unicast_packets;        /* dword 44*/
518         u32 rx_switched_multicast_packets;      /* dword 45*/
519         u32 rx_switched_broadcast_packets;      /* dword 46*/
520         u32 tx_bytes_lsd;       /* dword 47*/
521         u32 tx_bytes_msd;       /* dword 48*/
522         u32 tx_unicastframes;   /* dword 49*/
523         u32 tx_multicastframes; /* dword 50*/
524         u32 tx_broadcastframes; /* dword 51*/
525         u32 tx_pauseframes;     /* dword 52*/
526         u32 tx_controlframes;   /* dword 53*/
527         u32 tx_64_byte_packets; /* dword 54*/
528         u32 tx_65_127_byte_packets;     /* dword 55*/
529         u32 tx_128_256_byte_packets;    /* dword 56*/
530         u32 tx_256_511_byte_packets;    /* dword 57*/
531         u32 tx_512_1023_byte_packets;   /* dword 58*/
532         u32 tx_1024_1518_byte_packets;  /* dword 59*/
533         u32 tx_1519_2047_byte_packets;  /* dword 60*/
534         u32 tx_2048_4095_byte_packets;  /* dword 61*/
535         u32 tx_4096_8191_byte_packets;  /* dword 62*/
536         u32 tx_8192_9216_byte_packets;  /* dword 63*/
537         u32 rx_fifo_overflow;   /* dword 64*/
538         u32 rx_input_fifo_overflow;     /* dword 65*/
539 };
540
541 struct be_rxf_stats {
542         struct be_port_rxf_stats port[2];
543         u32 rx_drops_no_pbuf;   /* dword 132*/
544         u32 rx_drops_no_txpb;   /* dword 133*/
545         u32 rx_drops_no_erx_descr;      /* dword 134*/
546         u32 rx_drops_no_tpre_descr;     /* dword 135*/
547         u32 management_rx_port_packets; /* dword 136*/
548         u32 management_rx_port_bytes;   /* dword 137*/
549         u32 management_rx_port_pause_frames;    /* dword 138*/
550         u32 management_rx_port_errors;  /* dword 139*/
551         u32 management_tx_port_packets; /* dword 140*/
552         u32 management_tx_port_bytes;   /* dword 141*/
553         u32 management_tx_port_pause;   /* dword 142*/
554         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
555         u32 rx_drops_too_many_frags;    /* dword 144*/
556         u32 rx_drops_invalid_ring;      /* dword 145*/
557         u32 forwarded_packets;  /* dword 146*/
558         u32 rx_drops_mtu;       /* dword 147*/
559         u32 rsvd0[15];
560 };
561
562 struct be_erx_stats {
563         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
564         u32 debug_wdma_sent_hold;          /* dword 44*/
565         u32 debug_wdma_pbfree_sent_hold;   /* dword 45*/
566         u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
567         u32 debug_pmem_pbuf_dealloc;       /* dword 47*/
568 };
569
570 struct be_hw_stats {
571         struct be_rxf_stats rxf;
572         u32 rsvd[48];
573         struct be_erx_stats erx;
574 };
575
576 struct be_cmd_req_get_stats {
577         struct be_cmd_req_hdr hdr;
578         u8 rsvd[sizeof(struct be_hw_stats)];
579 };
580
581 struct be_cmd_resp_get_stats {
582         struct be_cmd_resp_hdr hdr;
583         struct be_hw_stats hw_stats;
584 };
585
586 struct be_cmd_req_vlan_config {
587         struct be_cmd_req_hdr hdr;
588         u8 interface_id;
589         u8 promiscuous;
590         u8 untagged;
591         u8 num_vlan;
592         u16 normal_vlan[64];
593 } __packed;
594
595 struct be_cmd_req_promiscuous_config {
596         struct be_cmd_req_hdr hdr;
597         u8 port0_promiscuous;
598         u8 port1_promiscuous;
599         u16 rsvd0;
600 } __packed;
601
602 /******************** Multicast MAC Config *******************/
603 #define BE_MAX_MC               64 /* set mcast promisc if > 64 */
604 struct macaddr {
605         u8 byte[ETH_ALEN];
606 };
607
608 struct be_cmd_req_mcast_mac_config {
609         struct be_cmd_req_hdr hdr;
610         u16 num_mac;
611         u8 promiscuous;
612         u8 interface_id;
613         struct macaddr mac[BE_MAX_MC];
614 } __packed;
615
616 static inline struct be_hw_stats *
617 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
618 {
619         return &cmd->hw_stats;
620 }
621
622 /******************** Link Status Query *******************/
623 struct be_cmd_req_link_status {
624         struct be_cmd_req_hdr hdr;
625         u32 rsvd;
626 };
627
628 enum {
629         PHY_LINK_DUPLEX_NONE = 0x0,
630         PHY_LINK_DUPLEX_HALF = 0x1,
631         PHY_LINK_DUPLEX_FULL = 0x2
632 };
633
634 enum {
635         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
636         PHY_LINK_SPEED_10MBPS = 0x1,
637         PHY_LINK_SPEED_100MBPS = 0x2,
638         PHY_LINK_SPEED_1GBPS = 0x3,
639         PHY_LINK_SPEED_10GBPS = 0x4
640 };
641
642 struct be_cmd_resp_link_status {
643         struct be_cmd_resp_hdr hdr;
644         u8 physical_port;
645         u8 mac_duplex;
646         u8 mac_speed;
647         u8 mac_fault;
648         u8 mgmt_mac_duplex;
649         u8 mgmt_mac_speed;
650         u16 link_speed;
651         u32 rsvd0;
652 } __packed;
653
654 /******************** Port Identification ***************************/
655 /*    Identifies the type of port attached to NIC     */
656 struct be_cmd_req_port_type {
657         struct be_cmd_req_hdr hdr;
658         u32 page_num;
659         u32 port;
660 };
661
662 enum {
663         TR_PAGE_A0 = 0xa0,
664         TR_PAGE_A2 = 0xa2
665 };
666
667 struct be_cmd_resp_port_type {
668         struct be_cmd_resp_hdr hdr;
669         u32 page_num;
670         u32 port;
671         struct data {
672                 u8 identifier;
673                 u8 identifier_ext;
674                 u8 connector;
675                 u8 transceiver[8];
676                 u8 rsvd0[3];
677                 u8 length_km;
678                 u8 length_hm;
679                 u8 length_om1;
680                 u8 length_om2;
681                 u8 length_cu;
682                 u8 length_cu_m;
683                 u8 vendor_name[16];
684                 u8 rsvd;
685                 u8 vendor_oui[3];
686                 u8 vendor_pn[16];
687                 u8 vendor_rev[4];
688         } data;
689 };
690
691 /******************** Get FW Version *******************/
692 struct be_cmd_req_get_fw_version {
693         struct be_cmd_req_hdr hdr;
694         u8 rsvd0[FW_VER_LEN];
695         u8 rsvd1[FW_VER_LEN];
696 } __packed;
697
698 struct be_cmd_resp_get_fw_version {
699         struct be_cmd_resp_hdr hdr;
700         u8 firmware_version_string[FW_VER_LEN];
701         u8 fw_on_flash_version_string[FW_VER_LEN];
702 } __packed;
703
704 /******************** Set Flow Contrl *******************/
705 struct be_cmd_req_set_flow_control {
706         struct be_cmd_req_hdr hdr;
707         u16 tx_flow_control;
708         u16 rx_flow_control;
709 } __packed;
710
711 /******************** Get Flow Contrl *******************/
712 struct be_cmd_req_get_flow_control {
713         struct be_cmd_req_hdr hdr;
714         u32 rsvd;
715 };
716
717 struct be_cmd_resp_get_flow_control {
718         struct be_cmd_resp_hdr hdr;
719         u16 tx_flow_control;
720         u16 rx_flow_control;
721 } __packed;
722
723 /******************** Modify EQ Delay *******************/
724 struct be_cmd_req_modify_eq_delay {
725         struct be_cmd_req_hdr hdr;
726         u32 num_eq;
727         struct {
728                 u32 eq_id;
729                 u32 phase;
730                 u32 delay_multiplier;
731         } delay[8];
732 } __packed;
733
734 struct be_cmd_resp_modify_eq_delay {
735         struct be_cmd_resp_hdr hdr;
736         u32 rsvd0;
737 } __packed;
738
739 /******************** Get FW Config *******************/
740 struct be_cmd_req_query_fw_cfg {
741         struct be_cmd_req_hdr hdr;
742         u32 rsvd[30];
743 };
744
745 struct be_cmd_resp_query_fw_cfg {
746         struct be_cmd_resp_hdr hdr;
747         u32 be_config_number;
748         u32 asic_revision;
749         u32 phys_port;
750         u32 function_cap;
751         u32 rsvd[26];
752 };
753
754 /******************** Port Beacon ***************************/
755
756 #define BEACON_STATE_ENABLED            0x1
757 #define BEACON_STATE_DISABLED           0x0
758
759 struct be_cmd_req_enable_disable_beacon {
760         struct be_cmd_req_hdr hdr;
761         u8  port_num;
762         u8  beacon_state;
763         u8  beacon_duration;
764         u8  status_duration;
765 } __packed;
766
767 struct be_cmd_resp_enable_disable_beacon {
768         struct be_cmd_resp_hdr resp_hdr;
769         u32 rsvd0;
770 } __packed;
771
772 struct be_cmd_req_get_beacon_state {
773         struct be_cmd_req_hdr hdr;
774         u8  port_num;
775         u8  rsvd0;
776         u16 rsvd1;
777 } __packed;
778
779 struct be_cmd_resp_get_beacon_state {
780         struct be_cmd_resp_hdr resp_hdr;
781         u8 beacon_state;
782         u8 rsvd0[3];
783 } __packed;
784
785 /****************** Firmware Flash ******************/
786 struct flashrom_params {
787         u32 op_code;
788         u32 op_type;
789         u32 data_buf_size;
790         u32 offset;
791         u8 data_buf[4];
792 };
793
794 struct be_cmd_write_flashrom {
795         struct be_cmd_req_hdr hdr;
796         struct flashrom_params params;
797 };
798
799 /************************ WOL *******************************/
800 struct be_cmd_req_acpi_wol_magic_config{
801         struct be_cmd_req_hdr hdr;
802         u32 rsvd0[145];
803         u8 magic_mac[6];
804         u8 rsvd2[2];
805 } __packed;
806
807 /********************** LoopBack test *********************/
808 struct be_cmd_req_loopback_test {
809         struct be_cmd_req_hdr hdr;
810         u32 loopback_type;
811         u32 num_pkts;
812         u64 pattern;
813         u32 src_port;
814         u32 dest_port;
815         u32 pkt_size;
816 };
817
818 struct be_cmd_resp_loopback_test {
819         struct be_cmd_resp_hdr resp_hdr;
820         u32    status;
821         u32    num_txfer;
822         u32    num_rx;
823         u32    miscomp_off;
824         u32    ticks_compl;
825 };
826
827 struct be_cmd_req_set_lmode {
828         struct be_cmd_req_hdr hdr;
829         u8 src_port;
830         u8 dest_port;
831         u8 loopback_type;
832         u8 loopback_state;
833 };
834
835 struct be_cmd_resp_set_lmode {
836         struct be_cmd_resp_hdr resp_hdr;
837         u8 rsvd0[4];
838 };
839
840 /********************** DDR DMA test *********************/
841 struct be_cmd_req_ddrdma_test {
842         struct be_cmd_req_hdr hdr;
843         u64 pattern;
844         u32 byte_count;
845         u32 rsvd0;
846         u8  snd_buff[4096];
847         u8  rsvd1[4096];
848 };
849
850 struct be_cmd_resp_ddrdma_test {
851         struct be_cmd_resp_hdr hdr;
852         u64 pattern;
853         u32 byte_cnt;
854         u32 snd_err;
855         u8  rsvd0[4096];
856         u8  rcv_buff[4096];
857 };
858
859 /*********************** SEEPROM Read ***********************/
860
861 #define BE_READ_SEEPROM_LEN 1024
862 struct be_cmd_req_seeprom_read {
863         struct be_cmd_req_hdr hdr;
864         u8 rsvd0[BE_READ_SEEPROM_LEN];
865 };
866
867 struct be_cmd_resp_seeprom_read {
868         struct be_cmd_req_hdr hdr;
869         u8 seeprom_data[BE_READ_SEEPROM_LEN];
870 };
871
872 extern int be_pci_fnum_get(struct be_adapter *adapter);
873 extern int be_cmd_POST(struct be_adapter *adapter);
874 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
875                         u8 type, bool permanent, u32 if_handle);
876 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
877                         u32 if_id, u32 *pmac_id);
878 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
879 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
880                         u32 en_flags, u8 *mac, bool pmac_invalid,
881                         u32 *if_handle, u32 *pmac_id);
882 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
883 extern int be_cmd_eq_create(struct be_adapter *adapter,
884                         struct be_queue_info *eq, int eq_delay);
885 extern int be_cmd_cq_create(struct be_adapter *adapter,
886                         struct be_queue_info *cq, struct be_queue_info *eq,
887                         bool sol_evts, bool no_delay,
888                         int num_cqe_dma_coalesce);
889 extern int be_cmd_mccq_create(struct be_adapter *adapter,
890                         struct be_queue_info *mccq,
891                         struct be_queue_info *cq);
892 extern int be_cmd_txq_create(struct be_adapter *adapter,
893                         struct be_queue_info *txq,
894                         struct be_queue_info *cq);
895 extern int be_cmd_rxq_create(struct be_adapter *adapter,
896                         struct be_queue_info *rxq, u16 cq_id,
897                         u16 frag_size, u16 max_frame_size, u32 if_id,
898                         u32 rss);
899 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
900                         int type);
901 extern int be_cmd_link_status_query(struct be_adapter *adapter,
902                         bool *link_up, u8 *mac_speed, u16 *link_speed);
903 extern int be_cmd_reset(struct be_adapter *adapter);
904 extern int be_cmd_get_stats(struct be_adapter *adapter,
905                         struct be_dma_mem *nonemb_cmd);
906 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
907
908 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
909 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
910                         u16 *vtag_array, u32 num, bool untagged,
911                         bool promiscuous);
912 extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
913                         u8 port_num, bool en);
914 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
915                         struct net_device *netdev, struct be_dma_mem *mem);
916 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
917                         u32 tx_fc, u32 rx_fc);
918 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
919                         u32 *tx_fc, u32 *rx_fc);
920 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
921                         u32 *port_num, u32 *cap);
922 extern int be_cmd_reset_function(struct be_adapter *adapter);
923 extern int be_process_mcc(struct be_adapter *adapter);
924 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
925                         u8 port_num, u8 beacon, u8 status, u8 state);
926 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
927                         u8 port_num, u32 *state);
928 extern int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
929                                         u8 *connector);
930 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
931                         struct be_dma_mem *cmd, u32 flash_oper,
932                         u32 flash_opcode, u32 buf_size);
933 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
934                                 int offset);
935 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
936                                 struct be_dma_mem *nonemb_cmd);
937 extern int be_cmd_fw_init(struct be_adapter *adapter);
938 extern int be_cmd_fw_clean(struct be_adapter *adapter);
939 extern void be_async_mcc_enable(struct be_adapter *adapter);
940 extern void be_async_mcc_disable(struct be_adapter *adapter);
941 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
942                                 u32 loopback_type, u32 pkt_size,
943                                 u32 num_pkts, u64 pattern);
944 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
945                         u32 byte_cnt, struct be_dma_mem *cmd);
946 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
947                                 struct be_dma_mem *nonemb_cmd);
948 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
949                                 u8 loopback_type, u8 enable);
950