net: convert multicast list to list_head
[linux-2.6.git] / drivers / net / benet / be_cmds.c
1 /*
2  * Copyright (C) 2005 - 2010 ServerEngines
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation.  The full GNU General
8  * Public License is included in this distribution in the file called COPYING.
9  *
10  * Contact Information:
11  * linux-drivers@serverengines.com
12  *
13  * ServerEngines
14  * 209 N. Fair Oaks Ave
15  * Sunnyvale, CA 94085
16  */
17
18 #include "be.h"
19 #include "be_cmds.h"
20
21 static void be_mcc_notify(struct be_adapter *adapter)
22 {
23         struct be_queue_info *mccq = &adapter->mcc_obj.q;
24         u32 val = 0;
25
26         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
28         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
29 }
30
31 /* To check if valid bit is set, check the entire word as we don't know
32  * the endianness of the data (old entry is host endian while a new entry is
33  * little endian) */
34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
35 {
36         if (compl->flags != 0) {
37                 compl->flags = le32_to_cpu(compl->flags);
38                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
39                 return true;
40         } else {
41                 return false;
42         }
43 }
44
45 /* Need to reset the entire word that houses the valid bit */
46 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
47 {
48         compl->flags = 0;
49 }
50
51 static int be_mcc_compl_process(struct be_adapter *adapter,
52         struct be_mcc_compl *compl)
53 {
54         u16 compl_status, extd_status;
55
56         /* Just swap the status to host endian; mcc tag is opaquely copied
57          * from mcc_wrb */
58         be_dws_le_to_cpu(compl, 4);
59
60         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
61                                 CQE_STATUS_COMPL_MASK;
62         if (compl_status == MCC_STATUS_SUCCESS) {
63                 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
64                         struct be_cmd_resp_get_stats *resp =
65                                                 adapter->stats.cmd.va;
66                         be_dws_le_to_cpu(&resp->hw_stats,
67                                                 sizeof(resp->hw_stats));
68                         netdev_stats_update(adapter);
69                 }
70         } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) {
71                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
72                                 CQE_STATUS_EXTD_MASK;
73                 dev_warn(&adapter->pdev->dev,
74                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
75                         compl->tag0, compl_status, extd_status);
76         }
77         return compl_status;
78 }
79
80 /* Link state evt is a string of bytes; no need for endian swapping */
81 static void be_async_link_state_process(struct be_adapter *adapter,
82                 struct be_async_event_link_state *evt)
83 {
84         be_link_status_update(adapter,
85                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
86 }
87
88 static inline bool is_link_state_evt(u32 trailer)
89 {
90         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
91                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
92                                 ASYNC_EVENT_CODE_LINK_STATE);
93 }
94
95 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
96 {
97         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
98         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
99
100         if (be_mcc_compl_is_new(compl)) {
101                 queue_tail_inc(mcc_cq);
102                 return compl;
103         }
104         return NULL;
105 }
106
107 void be_async_mcc_enable(struct be_adapter *adapter)
108 {
109         spin_lock_bh(&adapter->mcc_cq_lock);
110
111         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
112         adapter->mcc_obj.rearm_cq = true;
113
114         spin_unlock_bh(&adapter->mcc_cq_lock);
115 }
116
117 void be_async_mcc_disable(struct be_adapter *adapter)
118 {
119         adapter->mcc_obj.rearm_cq = false;
120 }
121
122 int be_process_mcc(struct be_adapter *adapter, int *status)
123 {
124         struct be_mcc_compl *compl;
125         int num = 0;
126         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
127
128         spin_lock_bh(&adapter->mcc_cq_lock);
129         while ((compl = be_mcc_compl_get(adapter))) {
130                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
131                         /* Interpret flags as an async trailer */
132                         BUG_ON(!is_link_state_evt(compl->flags));
133
134                         /* Interpret compl as a async link evt */
135                         be_async_link_state_process(adapter,
136                                 (struct be_async_event_link_state *) compl);
137                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
138                                 *status = be_mcc_compl_process(adapter, compl);
139                                 atomic_dec(&mcc_obj->q.used);
140                 }
141                 be_mcc_compl_use(compl);
142                 num++;
143         }
144
145         spin_unlock_bh(&adapter->mcc_cq_lock);
146         return num;
147 }
148
149 /* Wait till no more pending mcc requests are present */
150 static int be_mcc_wait_compl(struct be_adapter *adapter)
151 {
152 #define mcc_timeout             120000 /* 12s timeout */
153         int i, num, status = 0;
154         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
155
156         for (i = 0; i < mcc_timeout; i++) {
157                 num = be_process_mcc(adapter, &status);
158                 if (num)
159                         be_cq_notify(adapter, mcc_obj->cq.id,
160                                 mcc_obj->rearm_cq, num);
161
162                 if (atomic_read(&mcc_obj->q.used) == 0)
163                         break;
164                 udelay(100);
165         }
166         if (i == mcc_timeout) {
167                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
168                 return -1;
169         }
170         return status;
171 }
172
173 /* Notify MCC requests and wait for completion */
174 static int be_mcc_notify_wait(struct be_adapter *adapter)
175 {
176         be_mcc_notify(adapter);
177         return be_mcc_wait_compl(adapter);
178 }
179
180 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
181 {
182         int cnt = 0, wait = 5;
183         u32 ready;
184
185         do {
186                 ready = ioread32(db);
187                 if (ready == 0xffffffff) {
188                         dev_err(&adapter->pdev->dev,
189                                 "pci slot disconnected\n");
190                         return -1;
191                 }
192
193                 ready &= MPU_MAILBOX_DB_RDY_MASK;
194                 if (ready)
195                         break;
196
197                 if (cnt > 4000000) {
198                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
199                         return -1;
200                 }
201
202                 if (cnt > 50)
203                         wait = 200;
204                 cnt += wait;
205                 udelay(wait);
206         } while (true);
207
208         return 0;
209 }
210
211 /*
212  * Insert the mailbox address into the doorbell in two steps
213  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
214  */
215 static int be_mbox_notify_wait(struct be_adapter *adapter)
216 {
217         int status;
218         u32 val = 0;
219         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
220         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
221         struct be_mcc_mailbox *mbox = mbox_mem->va;
222         struct be_mcc_compl *compl = &mbox->compl;
223
224         /* wait for ready to be set */
225         status = be_mbox_db_ready_wait(adapter, db);
226         if (status != 0)
227                 return status;
228
229         val |= MPU_MAILBOX_DB_HI_MASK;
230         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
231         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
232         iowrite32(val, db);
233
234         /* wait for ready to be set */
235         status = be_mbox_db_ready_wait(adapter, db);
236         if (status != 0)
237                 return status;
238
239         val = 0;
240         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
241         val |= (u32)(mbox_mem->dma >> 4) << 2;
242         iowrite32(val, db);
243
244         status = be_mbox_db_ready_wait(adapter, db);
245         if (status != 0)
246                 return status;
247
248         /* A cq entry has been made now */
249         if (be_mcc_compl_is_new(compl)) {
250                 status = be_mcc_compl_process(adapter, &mbox->compl);
251                 be_mcc_compl_use(compl);
252                 if (status)
253                         return status;
254         } else {
255                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
256                 return -1;
257         }
258         return 0;
259 }
260
261 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
262 {
263         u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
264
265         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
266         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
267                 return -1;
268         else
269                 return 0;
270 }
271
272 int be_cmd_POST(struct be_adapter *adapter)
273 {
274         u16 stage;
275         int status, timeout = 0;
276
277         do {
278                 status = be_POST_stage_get(adapter, &stage);
279                 if (status) {
280                         dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
281                                 stage);
282                         return -1;
283                 } else if (stage != POST_STAGE_ARMFW_RDY) {
284                         set_current_state(TASK_INTERRUPTIBLE);
285                         schedule_timeout(2 * HZ);
286                         timeout += 2;
287                 } else {
288                         return 0;
289                 }
290         } while (timeout < 20);
291
292         dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
293         return -1;
294 }
295
296 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
297 {
298         return wrb->payload.embedded_payload;
299 }
300
301 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
302 {
303         return &wrb->payload.sgl[0];
304 }
305
306 /* Don't touch the hdr after it's prepared */
307 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
308                                 bool embedded, u8 sge_cnt, u32 opcode)
309 {
310         if (embedded)
311                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
312         else
313                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
314                                 MCC_WRB_SGE_CNT_SHIFT;
315         wrb->payload_length = payload_len;
316         wrb->tag0 = opcode;
317         be_dws_cpu_to_le(wrb, 8);
318 }
319
320 /* Don't touch the hdr after it's prepared */
321 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
322                                 u8 subsystem, u8 opcode, int cmd_len)
323 {
324         req_hdr->opcode = opcode;
325         req_hdr->subsystem = subsystem;
326         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
327         req_hdr->version = 0;
328 }
329
330 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
331                         struct be_dma_mem *mem)
332 {
333         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
334         u64 dma = (u64)mem->dma;
335
336         for (i = 0; i < buf_pages; i++) {
337                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
338                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
339                 dma += PAGE_SIZE_4K;
340         }
341 }
342
343 /* Converts interrupt delay in microseconds to multiplier value */
344 static u32 eq_delay_to_mult(u32 usec_delay)
345 {
346 #define MAX_INTR_RATE                   651042
347         const u32 round = 10;
348         u32 multiplier;
349
350         if (usec_delay == 0)
351                 multiplier = 0;
352         else {
353                 u32 interrupt_rate = 1000000 / usec_delay;
354                 /* Max delay, corresponding to the lowest interrupt rate */
355                 if (interrupt_rate == 0)
356                         multiplier = 1023;
357                 else {
358                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
359                         multiplier /= interrupt_rate;
360                         /* Round the multiplier to the closest value.*/
361                         multiplier = (multiplier + round/2) / round;
362                         multiplier = min(multiplier, (u32)1023);
363                 }
364         }
365         return multiplier;
366 }
367
368 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
369 {
370         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
371         struct be_mcc_wrb *wrb
372                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
373         memset(wrb, 0, sizeof(*wrb));
374         return wrb;
375 }
376
377 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
378 {
379         struct be_queue_info *mccq = &adapter->mcc_obj.q;
380         struct be_mcc_wrb *wrb;
381
382         if (atomic_read(&mccq->used) >= mccq->len) {
383                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
384                 return NULL;
385         }
386
387         wrb = queue_head_node(mccq);
388         queue_head_inc(mccq);
389         atomic_inc(&mccq->used);
390         memset(wrb, 0, sizeof(*wrb));
391         return wrb;
392 }
393
394 /* Tell fw we're about to start firing cmds by writing a
395  * special pattern across the wrb hdr; uses mbox
396  */
397 int be_cmd_fw_init(struct be_adapter *adapter)
398 {
399         u8 *wrb;
400         int status;
401
402         spin_lock(&adapter->mbox_lock);
403
404         wrb = (u8 *)wrb_from_mbox(adapter);
405         *wrb++ = 0xFF;
406         *wrb++ = 0x12;
407         *wrb++ = 0x34;
408         *wrb++ = 0xFF;
409         *wrb++ = 0xFF;
410         *wrb++ = 0x56;
411         *wrb++ = 0x78;
412         *wrb = 0xFF;
413
414         status = be_mbox_notify_wait(adapter);
415
416         spin_unlock(&adapter->mbox_lock);
417         return status;
418 }
419
420 /* Tell fw we're done with firing cmds by writing a
421  * special pattern across the wrb hdr; uses mbox
422  */
423 int be_cmd_fw_clean(struct be_adapter *adapter)
424 {
425         u8 *wrb;
426         int status;
427
428         if (adapter->eeh_err)
429                 return -EIO;
430
431         spin_lock(&adapter->mbox_lock);
432
433         wrb = (u8 *)wrb_from_mbox(adapter);
434         *wrb++ = 0xFF;
435         *wrb++ = 0xAA;
436         *wrb++ = 0xBB;
437         *wrb++ = 0xFF;
438         *wrb++ = 0xFF;
439         *wrb++ = 0xCC;
440         *wrb++ = 0xDD;
441         *wrb = 0xFF;
442
443         status = be_mbox_notify_wait(adapter);
444
445         spin_unlock(&adapter->mbox_lock);
446         return status;
447 }
448 int be_cmd_eq_create(struct be_adapter *adapter,
449                 struct be_queue_info *eq, int eq_delay)
450 {
451         struct be_mcc_wrb *wrb;
452         struct be_cmd_req_eq_create *req;
453         struct be_dma_mem *q_mem = &eq->dma_mem;
454         int status;
455
456         spin_lock(&adapter->mbox_lock);
457
458         wrb = wrb_from_mbox(adapter);
459         req = embedded_payload(wrb);
460
461         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
462
463         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
464                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
465
466         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
467
468         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
469         /* 4byte eqe*/
470         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
471         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
472                         __ilog2_u32(eq->len/256));
473         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
474                         eq_delay_to_mult(eq_delay));
475         be_dws_cpu_to_le(req->context, sizeof(req->context));
476
477         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
478
479         status = be_mbox_notify_wait(adapter);
480         if (!status) {
481                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
482                 eq->id = le16_to_cpu(resp->eq_id);
483                 eq->created = true;
484         }
485
486         spin_unlock(&adapter->mbox_lock);
487         return status;
488 }
489
490 /* Uses mbox */
491 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
492                         u8 type, bool permanent, u32 if_handle)
493 {
494         struct be_mcc_wrb *wrb;
495         struct be_cmd_req_mac_query *req;
496         int status;
497
498         spin_lock(&adapter->mbox_lock);
499
500         wrb = wrb_from_mbox(adapter);
501         req = embedded_payload(wrb);
502
503         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
504                         OPCODE_COMMON_NTWK_MAC_QUERY);
505
506         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
507                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
508
509         req->type = type;
510         if (permanent) {
511                 req->permanent = 1;
512         } else {
513                 req->if_id = cpu_to_le16((u16) if_handle);
514                 req->permanent = 0;
515         }
516
517         status = be_mbox_notify_wait(adapter);
518         if (!status) {
519                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
520                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
521         }
522
523         spin_unlock(&adapter->mbox_lock);
524         return status;
525 }
526
527 /* Uses synchronous MCCQ */
528 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
529                 u32 if_id, u32 *pmac_id)
530 {
531         struct be_mcc_wrb *wrb;
532         struct be_cmd_req_pmac_add *req;
533         int status;
534
535         spin_lock_bh(&adapter->mcc_lock);
536
537         wrb = wrb_from_mccq(adapter);
538         if (!wrb) {
539                 status = -EBUSY;
540                 goto err;
541         }
542         req = embedded_payload(wrb);
543
544         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
545                         OPCODE_COMMON_NTWK_PMAC_ADD);
546
547         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
548                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
549
550         req->if_id = cpu_to_le32(if_id);
551         memcpy(req->mac_address, mac_addr, ETH_ALEN);
552
553         status = be_mcc_notify_wait(adapter);
554         if (!status) {
555                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
556                 *pmac_id = le32_to_cpu(resp->pmac_id);
557         }
558
559 err:
560         spin_unlock_bh(&adapter->mcc_lock);
561         return status;
562 }
563
564 /* Uses synchronous MCCQ */
565 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
566 {
567         struct be_mcc_wrb *wrb;
568         struct be_cmd_req_pmac_del *req;
569         int status;
570
571         spin_lock_bh(&adapter->mcc_lock);
572
573         wrb = wrb_from_mccq(adapter);
574         if (!wrb) {
575                 status = -EBUSY;
576                 goto err;
577         }
578         req = embedded_payload(wrb);
579
580         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
581                         OPCODE_COMMON_NTWK_PMAC_DEL);
582
583         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
584                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
585
586         req->if_id = cpu_to_le32(if_id);
587         req->pmac_id = cpu_to_le32(pmac_id);
588
589         status = be_mcc_notify_wait(adapter);
590
591 err:
592         spin_unlock_bh(&adapter->mcc_lock);
593         return status;
594 }
595
596 /* Uses Mbox */
597 int be_cmd_cq_create(struct be_adapter *adapter,
598                 struct be_queue_info *cq, struct be_queue_info *eq,
599                 bool sol_evts, bool no_delay, int coalesce_wm)
600 {
601         struct be_mcc_wrb *wrb;
602         struct be_cmd_req_cq_create *req;
603         struct be_dma_mem *q_mem = &cq->dma_mem;
604         void *ctxt;
605         int status;
606
607         spin_lock(&adapter->mbox_lock);
608
609         wrb = wrb_from_mbox(adapter);
610         req = embedded_payload(wrb);
611         ctxt = &req->context;
612
613         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
614                         OPCODE_COMMON_CQ_CREATE);
615
616         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
617                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
618
619         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
620
621         AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
622         AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
623         AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
624                         __ilog2_u32(cq->len/256));
625         AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
626         AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
627         AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
628         AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
629         AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
630         be_dws_cpu_to_le(ctxt, sizeof(req->context));
631
632         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
633
634         status = be_mbox_notify_wait(adapter);
635         if (!status) {
636                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
637                 cq->id = le16_to_cpu(resp->cq_id);
638                 cq->created = true;
639         }
640
641         spin_unlock(&adapter->mbox_lock);
642
643         return status;
644 }
645
646 static u32 be_encoded_q_len(int q_len)
647 {
648         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
649         if (len_encoded == 16)
650                 len_encoded = 0;
651         return len_encoded;
652 }
653
654 int be_cmd_mccq_create(struct be_adapter *adapter,
655                         struct be_queue_info *mccq,
656                         struct be_queue_info *cq)
657 {
658         struct be_mcc_wrb *wrb;
659         struct be_cmd_req_mcc_create *req;
660         struct be_dma_mem *q_mem = &mccq->dma_mem;
661         void *ctxt;
662         int status;
663
664         spin_lock(&adapter->mbox_lock);
665
666         wrb = wrb_from_mbox(adapter);
667         req = embedded_payload(wrb);
668         ctxt = &req->context;
669
670         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
671                         OPCODE_COMMON_MCC_CREATE);
672
673         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
674                         OPCODE_COMMON_MCC_CREATE, sizeof(*req));
675
676         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
677
678         AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
679         AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
680                 be_encoded_q_len(mccq->len));
681         AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
682
683         be_dws_cpu_to_le(ctxt, sizeof(req->context));
684
685         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
686
687         status = be_mbox_notify_wait(adapter);
688         if (!status) {
689                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
690                 mccq->id = le16_to_cpu(resp->id);
691                 mccq->created = true;
692         }
693         spin_unlock(&adapter->mbox_lock);
694
695         return status;
696 }
697
698 int be_cmd_txq_create(struct be_adapter *adapter,
699                         struct be_queue_info *txq,
700                         struct be_queue_info *cq)
701 {
702         struct be_mcc_wrb *wrb;
703         struct be_cmd_req_eth_tx_create *req;
704         struct be_dma_mem *q_mem = &txq->dma_mem;
705         void *ctxt;
706         int status;
707
708         spin_lock(&adapter->mbox_lock);
709
710         wrb = wrb_from_mbox(adapter);
711         req = embedded_payload(wrb);
712         ctxt = &req->context;
713
714         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
715                         OPCODE_ETH_TX_CREATE);
716
717         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
718                 sizeof(*req));
719
720         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
721         req->ulp_num = BE_ULP1_NUM;
722         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
723
724         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
725                 be_encoded_q_len(txq->len));
726         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
727         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
728
729         be_dws_cpu_to_le(ctxt, sizeof(req->context));
730
731         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
732
733         status = be_mbox_notify_wait(adapter);
734         if (!status) {
735                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
736                 txq->id = le16_to_cpu(resp->cid);
737                 txq->created = true;
738         }
739
740         spin_unlock(&adapter->mbox_lock);
741
742         return status;
743 }
744
745 /* Uses mbox */
746 int be_cmd_rxq_create(struct be_adapter *adapter,
747                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
748                 u16 max_frame_size, u32 if_id, u32 rss)
749 {
750         struct be_mcc_wrb *wrb;
751         struct be_cmd_req_eth_rx_create *req;
752         struct be_dma_mem *q_mem = &rxq->dma_mem;
753         int status;
754
755         spin_lock(&adapter->mbox_lock);
756
757         wrb = wrb_from_mbox(adapter);
758         req = embedded_payload(wrb);
759
760         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
761                         OPCODE_ETH_RX_CREATE);
762
763         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
764                 sizeof(*req));
765
766         req->cq_id = cpu_to_le16(cq_id);
767         req->frag_size = fls(frag_size) - 1;
768         req->num_pages = 2;
769         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
770         req->interface_id = cpu_to_le32(if_id);
771         req->max_frame_size = cpu_to_le16(max_frame_size);
772         req->rss_queue = cpu_to_le32(rss);
773
774         status = be_mbox_notify_wait(adapter);
775         if (!status) {
776                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
777                 rxq->id = le16_to_cpu(resp->id);
778                 rxq->created = true;
779         }
780
781         spin_unlock(&adapter->mbox_lock);
782
783         return status;
784 }
785
786 /* Generic destroyer function for all types of queues
787  * Uses Mbox
788  */
789 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
790                 int queue_type)
791 {
792         struct be_mcc_wrb *wrb;
793         struct be_cmd_req_q_destroy *req;
794         u8 subsys = 0, opcode = 0;
795         int status;
796
797         if (adapter->eeh_err)
798                 return -EIO;
799
800         spin_lock(&adapter->mbox_lock);
801
802         wrb = wrb_from_mbox(adapter);
803         req = embedded_payload(wrb);
804
805         switch (queue_type) {
806         case QTYPE_EQ:
807                 subsys = CMD_SUBSYSTEM_COMMON;
808                 opcode = OPCODE_COMMON_EQ_DESTROY;
809                 break;
810         case QTYPE_CQ:
811                 subsys = CMD_SUBSYSTEM_COMMON;
812                 opcode = OPCODE_COMMON_CQ_DESTROY;
813                 break;
814         case QTYPE_TXQ:
815                 subsys = CMD_SUBSYSTEM_ETH;
816                 opcode = OPCODE_ETH_TX_DESTROY;
817                 break;
818         case QTYPE_RXQ:
819                 subsys = CMD_SUBSYSTEM_ETH;
820                 opcode = OPCODE_ETH_RX_DESTROY;
821                 break;
822         case QTYPE_MCCQ:
823                 subsys = CMD_SUBSYSTEM_COMMON;
824                 opcode = OPCODE_COMMON_MCC_DESTROY;
825                 break;
826         default:
827                 BUG();
828         }
829
830         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
831
832         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
833         req->id = cpu_to_le16(q->id);
834
835         status = be_mbox_notify_wait(adapter);
836
837         spin_unlock(&adapter->mbox_lock);
838
839         return status;
840 }
841
842 /* Create an rx filtering policy configuration on an i/f
843  * Uses mbox
844  */
845 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
846                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
847                 u32 domain)
848 {
849         struct be_mcc_wrb *wrb;
850         struct be_cmd_req_if_create *req;
851         int status;
852
853         spin_lock(&adapter->mbox_lock);
854
855         wrb = wrb_from_mbox(adapter);
856         req = embedded_payload(wrb);
857
858         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
859                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
860
861         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
862                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
863
864         req->hdr.domain = domain;
865         req->capability_flags = cpu_to_le32(cap_flags);
866         req->enable_flags = cpu_to_le32(en_flags);
867         req->pmac_invalid = pmac_invalid;
868         if (!pmac_invalid)
869                 memcpy(req->mac_addr, mac, ETH_ALEN);
870
871         status = be_mbox_notify_wait(adapter);
872         if (!status) {
873                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
874                 *if_handle = le32_to_cpu(resp->interface_id);
875                 if (!pmac_invalid)
876                         *pmac_id = le32_to_cpu(resp->pmac_id);
877         }
878
879         spin_unlock(&adapter->mbox_lock);
880         return status;
881 }
882
883 /* Uses mbox */
884 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
885 {
886         struct be_mcc_wrb *wrb;
887         struct be_cmd_req_if_destroy *req;
888         int status;
889
890         if (adapter->eeh_err)
891                 return -EIO;
892
893         spin_lock(&adapter->mbox_lock);
894
895         wrb = wrb_from_mbox(adapter);
896         req = embedded_payload(wrb);
897
898         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
899                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
900
901         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
902                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
903
904         req->interface_id = cpu_to_le32(interface_id);
905
906         status = be_mbox_notify_wait(adapter);
907
908         spin_unlock(&adapter->mbox_lock);
909
910         return status;
911 }
912
913 /* Get stats is a non embedded command: the request is not embedded inside
914  * WRB but is a separate dma memory block
915  * Uses asynchronous MCC
916  */
917 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
918 {
919         struct be_mcc_wrb *wrb;
920         struct be_cmd_req_get_stats *req;
921         struct be_sge *sge;
922         int status = 0;
923
924         spin_lock_bh(&adapter->mcc_lock);
925
926         wrb = wrb_from_mccq(adapter);
927         if (!wrb) {
928                 status = -EBUSY;
929                 goto err;
930         }
931         req = nonemb_cmd->va;
932         sge = nonembedded_sgl(wrb);
933
934         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
935                         OPCODE_ETH_GET_STATISTICS);
936
937         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
938                 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
939         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
940         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
941         sge->len = cpu_to_le32(nonemb_cmd->size);
942
943         be_mcc_notify(adapter);
944
945 err:
946         spin_unlock_bh(&adapter->mcc_lock);
947         return status;
948 }
949
950 /* Uses synchronous mcc */
951 int be_cmd_link_status_query(struct be_adapter *adapter,
952                         bool *link_up, u8 *mac_speed, u16 *link_speed)
953 {
954         struct be_mcc_wrb *wrb;
955         struct be_cmd_req_link_status *req;
956         int status;
957
958         spin_lock_bh(&adapter->mcc_lock);
959
960         wrb = wrb_from_mccq(adapter);
961         if (!wrb) {
962                 status = -EBUSY;
963                 goto err;
964         }
965         req = embedded_payload(wrb);
966
967         *link_up = false;
968
969         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
970                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
971
972         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
973                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
974
975         status = be_mcc_notify_wait(adapter);
976         if (!status) {
977                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
978                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
979                         *link_up = true;
980                         *link_speed = le16_to_cpu(resp->link_speed);
981                         *mac_speed = resp->mac_speed;
982                 }
983         }
984
985 err:
986         spin_unlock_bh(&adapter->mcc_lock);
987         return status;
988 }
989
990 /* Uses Mbox */
991 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
992 {
993         struct be_mcc_wrb *wrb;
994         struct be_cmd_req_get_fw_version *req;
995         int status;
996
997         spin_lock(&adapter->mbox_lock);
998
999         wrb = wrb_from_mbox(adapter);
1000         req = embedded_payload(wrb);
1001
1002         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1003                         OPCODE_COMMON_GET_FW_VERSION);
1004
1005         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1006                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1007
1008         status = be_mbox_notify_wait(adapter);
1009         if (!status) {
1010                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1011                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1012         }
1013
1014         spin_unlock(&adapter->mbox_lock);
1015         return status;
1016 }
1017
1018 /* set the EQ delay interval of an EQ to specified value
1019  * Uses async mcc
1020  */
1021 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1022 {
1023         struct be_mcc_wrb *wrb;
1024         struct be_cmd_req_modify_eq_delay *req;
1025         int status = 0;
1026
1027         spin_lock_bh(&adapter->mcc_lock);
1028
1029         wrb = wrb_from_mccq(adapter);
1030         if (!wrb) {
1031                 status = -EBUSY;
1032                 goto err;
1033         }
1034         req = embedded_payload(wrb);
1035
1036         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1037                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1038
1039         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1040                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1041
1042         req->num_eq = cpu_to_le32(1);
1043         req->delay[0].eq_id = cpu_to_le32(eq_id);
1044         req->delay[0].phase = 0;
1045         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1046
1047         be_mcc_notify(adapter);
1048
1049 err:
1050         spin_unlock_bh(&adapter->mcc_lock);
1051         return status;
1052 }
1053
1054 /* Uses sycnhronous mcc */
1055 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1056                         u32 num, bool untagged, bool promiscuous)
1057 {
1058         struct be_mcc_wrb *wrb;
1059         struct be_cmd_req_vlan_config *req;
1060         int status;
1061
1062         spin_lock_bh(&adapter->mcc_lock);
1063
1064         wrb = wrb_from_mccq(adapter);
1065         if (!wrb) {
1066                 status = -EBUSY;
1067                 goto err;
1068         }
1069         req = embedded_payload(wrb);
1070
1071         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1072                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1073
1074         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1075                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1076
1077         req->interface_id = if_id;
1078         req->promiscuous = promiscuous;
1079         req->untagged = untagged;
1080         req->num_vlan = num;
1081         if (!promiscuous) {
1082                 memcpy(req->normal_vlan, vtag_array,
1083                         req->num_vlan * sizeof(vtag_array[0]));
1084         }
1085
1086         status = be_mcc_notify_wait(adapter);
1087
1088 err:
1089         spin_unlock_bh(&adapter->mcc_lock);
1090         return status;
1091 }
1092
1093 /* Uses MCC for this command as it may be called in BH context
1094  * Uses synchronous mcc
1095  */
1096 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1097 {
1098         struct be_mcc_wrb *wrb;
1099         struct be_cmd_req_promiscuous_config *req;
1100         int status;
1101
1102         spin_lock_bh(&adapter->mcc_lock);
1103
1104         wrb = wrb_from_mccq(adapter);
1105         if (!wrb) {
1106                 status = -EBUSY;
1107                 goto err;
1108         }
1109         req = embedded_payload(wrb);
1110
1111         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1112
1113         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1114                 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1115
1116         if (port_num)
1117                 req->port1_promiscuous = en;
1118         else
1119                 req->port0_promiscuous = en;
1120
1121         status = be_mcc_notify_wait(adapter);
1122
1123 err:
1124         spin_unlock_bh(&adapter->mcc_lock);
1125         return status;
1126 }
1127
1128 /*
1129  * Uses MCC for this command as it may be called in BH context
1130  * (mc == NULL) => multicast promiscous
1131  */
1132 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1133                 struct net_device *netdev, struct be_dma_mem *mem)
1134 {
1135         struct be_mcc_wrb *wrb;
1136         struct be_cmd_req_mcast_mac_config *req = mem->va;
1137         struct be_sge *sge;
1138         int status;
1139
1140         spin_lock_bh(&adapter->mcc_lock);
1141
1142         wrb = wrb_from_mccq(adapter);
1143         if (!wrb) {
1144                 status = -EBUSY;
1145                 goto err;
1146         }
1147         sge = nonembedded_sgl(wrb);
1148         memset(req, 0, sizeof(*req));
1149
1150         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1151                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1152         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1153         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1154         sge->len = cpu_to_le32(mem->size);
1155
1156         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1157                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1158
1159         req->interface_id = if_id;
1160         if (netdev) {
1161                 int i;
1162                 struct netdev_hw_addr *ha;
1163
1164                 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1165
1166                 i = 0;
1167                 netdev_for_each_mc_addr(ha, netdev)
1168                         memcpy(req->mac[i].byte, ha->addr, ETH_ALEN);
1169         } else {
1170                 req->promiscuous = 1;
1171         }
1172
1173         status = be_mcc_notify_wait(adapter);
1174
1175 err:
1176         spin_unlock_bh(&adapter->mcc_lock);
1177         return status;
1178 }
1179
1180 /* Uses synchrounous mcc */
1181 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1182 {
1183         struct be_mcc_wrb *wrb;
1184         struct be_cmd_req_set_flow_control *req;
1185         int status;
1186
1187         spin_lock_bh(&adapter->mcc_lock);
1188
1189         wrb = wrb_from_mccq(adapter);
1190         if (!wrb) {
1191                 status = -EBUSY;
1192                 goto err;
1193         }
1194         req = embedded_payload(wrb);
1195
1196         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1197                         OPCODE_COMMON_SET_FLOW_CONTROL);
1198
1199         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1200                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1201
1202         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1203         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1204
1205         status = be_mcc_notify_wait(adapter);
1206
1207 err:
1208         spin_unlock_bh(&adapter->mcc_lock);
1209         return status;
1210 }
1211
1212 /* Uses sycn mcc */
1213 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1214 {
1215         struct be_mcc_wrb *wrb;
1216         struct be_cmd_req_get_flow_control *req;
1217         int status;
1218
1219         spin_lock_bh(&adapter->mcc_lock);
1220
1221         wrb = wrb_from_mccq(adapter);
1222         if (!wrb) {
1223                 status = -EBUSY;
1224                 goto err;
1225         }
1226         req = embedded_payload(wrb);
1227
1228         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1229                         OPCODE_COMMON_GET_FLOW_CONTROL);
1230
1231         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1232                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1233
1234         status = be_mcc_notify_wait(adapter);
1235         if (!status) {
1236                 struct be_cmd_resp_get_flow_control *resp =
1237                                                 embedded_payload(wrb);
1238                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1239                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1240         }
1241
1242 err:
1243         spin_unlock_bh(&adapter->mcc_lock);
1244         return status;
1245 }
1246
1247 /* Uses mbox */
1248 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
1249 {
1250         struct be_mcc_wrb *wrb;
1251         struct be_cmd_req_query_fw_cfg *req;
1252         int status;
1253
1254         spin_lock(&adapter->mbox_lock);
1255
1256         wrb = wrb_from_mbox(adapter);
1257         req = embedded_payload(wrb);
1258
1259         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1260                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1261
1262         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1263                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1264
1265         status = be_mbox_notify_wait(adapter);
1266         if (!status) {
1267                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1268                 *port_num = le32_to_cpu(resp->phys_port);
1269                 *cap = le32_to_cpu(resp->function_cap);
1270         }
1271
1272         spin_unlock(&adapter->mbox_lock);
1273         return status;
1274 }
1275
1276 /* Uses mbox */
1277 int be_cmd_reset_function(struct be_adapter *adapter)
1278 {
1279         struct be_mcc_wrb *wrb;
1280         struct be_cmd_req_hdr *req;
1281         int status;
1282
1283         spin_lock(&adapter->mbox_lock);
1284
1285         wrb = wrb_from_mbox(adapter);
1286         req = embedded_payload(wrb);
1287
1288         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1289                         OPCODE_COMMON_FUNCTION_RESET);
1290
1291         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1292                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1293
1294         status = be_mbox_notify_wait(adapter);
1295
1296         spin_unlock(&adapter->mbox_lock);
1297         return status;
1298 }
1299
1300 /* Uses sync mcc */
1301 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1302                         u8 bcn, u8 sts, u8 state)
1303 {
1304         struct be_mcc_wrb *wrb;
1305         struct be_cmd_req_enable_disable_beacon *req;
1306         int status;
1307
1308         spin_lock_bh(&adapter->mcc_lock);
1309
1310         wrb = wrb_from_mccq(adapter);
1311         if (!wrb) {
1312                 status = -EBUSY;
1313                 goto err;
1314         }
1315         req = embedded_payload(wrb);
1316
1317         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1318                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1319
1320         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1321                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1322
1323         req->port_num = port_num;
1324         req->beacon_state = state;
1325         req->beacon_duration = bcn;
1326         req->status_duration = sts;
1327
1328         status = be_mcc_notify_wait(adapter);
1329
1330 err:
1331         spin_unlock_bh(&adapter->mcc_lock);
1332         return status;
1333 }
1334
1335 /* Uses sync mcc */
1336 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1337 {
1338         struct be_mcc_wrb *wrb;
1339         struct be_cmd_req_get_beacon_state *req;
1340         int status;
1341
1342         spin_lock_bh(&adapter->mcc_lock);
1343
1344         wrb = wrb_from_mccq(adapter);
1345         if (!wrb) {
1346                 status = -EBUSY;
1347                 goto err;
1348         }
1349         req = embedded_payload(wrb);
1350
1351         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1352                         OPCODE_COMMON_GET_BEACON_STATE);
1353
1354         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1355                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1356
1357         req->port_num = port_num;
1358
1359         status = be_mcc_notify_wait(adapter);
1360         if (!status) {
1361                 struct be_cmd_resp_get_beacon_state *resp =
1362                                                 embedded_payload(wrb);
1363                 *state = resp->beacon_state;
1364         }
1365
1366 err:
1367         spin_unlock_bh(&adapter->mcc_lock);
1368         return status;
1369 }
1370
1371 /* Uses sync mcc */
1372 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1373                                 u8 *connector)
1374 {
1375         struct be_mcc_wrb *wrb;
1376         struct be_cmd_req_port_type *req;
1377         int status;
1378
1379         spin_lock_bh(&adapter->mcc_lock);
1380
1381         wrb = wrb_from_mccq(adapter);
1382         if (!wrb) {
1383                 status = -EBUSY;
1384                 goto err;
1385         }
1386         req = embedded_payload(wrb);
1387
1388         be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1389                         OPCODE_COMMON_READ_TRANSRECV_DATA);
1390
1391         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1392                 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1393
1394         req->port = cpu_to_le32(port);
1395         req->page_num = cpu_to_le32(TR_PAGE_A0);
1396         status = be_mcc_notify_wait(adapter);
1397         if (!status) {
1398                 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1399                         *connector = resp->data.connector;
1400         }
1401
1402 err:
1403         spin_unlock_bh(&adapter->mcc_lock);
1404         return status;
1405 }
1406
1407 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1408                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1409 {
1410         struct be_mcc_wrb *wrb;
1411         struct be_cmd_write_flashrom *req;
1412         struct be_sge *sge;
1413         int status;
1414
1415         spin_lock_bh(&adapter->mcc_lock);
1416
1417         wrb = wrb_from_mccq(adapter);
1418         if (!wrb) {
1419                 status = -EBUSY;
1420                 goto err;
1421         }
1422         req = cmd->va;
1423         sge = nonembedded_sgl(wrb);
1424
1425         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1426                         OPCODE_COMMON_WRITE_FLASHROM);
1427
1428         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1429                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1430         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1431         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1432         sge->len = cpu_to_le32(cmd->size);
1433
1434         req->params.op_type = cpu_to_le32(flash_type);
1435         req->params.op_code = cpu_to_le32(flash_opcode);
1436         req->params.data_buf_size = cpu_to_le32(buf_size);
1437
1438         status = be_mcc_notify_wait(adapter);
1439
1440 err:
1441         spin_unlock_bh(&adapter->mcc_lock);
1442         return status;
1443 }
1444
1445 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1446                          int offset)
1447 {
1448         struct be_mcc_wrb *wrb;
1449         struct be_cmd_write_flashrom *req;
1450         int status;
1451
1452         spin_lock_bh(&adapter->mcc_lock);
1453
1454         wrb = wrb_from_mccq(adapter);
1455         if (!wrb) {
1456                 status = -EBUSY;
1457                 goto err;
1458         }
1459         req = embedded_payload(wrb);
1460
1461         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1462                         OPCODE_COMMON_READ_FLASHROM);
1463
1464         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1465                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1466
1467         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1468         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1469         req->params.offset = offset;
1470         req->params.data_buf_size = 0x4;
1471
1472         status = be_mcc_notify_wait(adapter);
1473         if (!status)
1474                 memcpy(flashed_crc, req->params.data_buf, 4);
1475
1476 err:
1477         spin_unlock_bh(&adapter->mcc_lock);
1478         return status;
1479 }
1480
1481 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1482                                 struct be_dma_mem *nonemb_cmd)
1483 {
1484         struct be_mcc_wrb *wrb;
1485         struct be_cmd_req_acpi_wol_magic_config *req;
1486         struct be_sge *sge;
1487         int status;
1488
1489         spin_lock_bh(&adapter->mcc_lock);
1490
1491         wrb = wrb_from_mccq(adapter);
1492         if (!wrb) {
1493                 status = -EBUSY;
1494                 goto err;
1495         }
1496         req = nonemb_cmd->va;
1497         sge = nonembedded_sgl(wrb);
1498
1499         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1500                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1501
1502         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1503                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1504         memcpy(req->magic_mac, mac, ETH_ALEN);
1505
1506         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1507         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1508         sge->len = cpu_to_le32(nonemb_cmd->size);
1509
1510         status = be_mcc_notify_wait(adapter);
1511
1512 err:
1513         spin_unlock_bh(&adapter->mcc_lock);
1514         return status;
1515 }
1516
1517 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1518                         u8 loopback_type, u8 enable)
1519 {
1520         struct be_mcc_wrb *wrb;
1521         struct be_cmd_req_set_lmode *req;
1522         int status;
1523
1524         spin_lock_bh(&adapter->mcc_lock);
1525
1526         wrb = wrb_from_mccq(adapter);
1527         if (!wrb) {
1528                 status = -EBUSY;
1529                 goto err;
1530         }
1531
1532         req = embedded_payload(wrb);
1533
1534         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1535                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1536
1537         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1538                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1539                         sizeof(*req));
1540
1541         req->src_port = port_num;
1542         req->dest_port = port_num;
1543         req->loopback_type = loopback_type;
1544         req->loopback_state = enable;
1545
1546         status = be_mcc_notify_wait(adapter);
1547 err:
1548         spin_unlock_bh(&adapter->mcc_lock);
1549         return status;
1550 }
1551
1552 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1553                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1554 {
1555         struct be_mcc_wrb *wrb;
1556         struct be_cmd_req_loopback_test *req;
1557         int status;
1558
1559         spin_lock_bh(&adapter->mcc_lock);
1560
1561         wrb = wrb_from_mccq(adapter);
1562         if (!wrb) {
1563                 status = -EBUSY;
1564                 goto err;
1565         }
1566
1567         req = embedded_payload(wrb);
1568
1569         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1570                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1571
1572         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1573                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1574         req->hdr.timeout = 4;
1575
1576         req->pattern = cpu_to_le64(pattern);
1577         req->src_port = cpu_to_le32(port_num);
1578         req->dest_port = cpu_to_le32(port_num);
1579         req->pkt_size = cpu_to_le32(pkt_size);
1580         req->num_pkts = cpu_to_le32(num_pkts);
1581         req->loopback_type = cpu_to_le32(loopback_type);
1582
1583         status = be_mcc_notify_wait(adapter);
1584         if (!status) {
1585                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1586                 status = le32_to_cpu(resp->status);
1587         }
1588
1589 err:
1590         spin_unlock_bh(&adapter->mcc_lock);
1591         return status;
1592 }
1593
1594 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1595                                 u32 byte_cnt, struct be_dma_mem *cmd)
1596 {
1597         struct be_mcc_wrb *wrb;
1598         struct be_cmd_req_ddrdma_test *req;
1599         struct be_sge *sge;
1600         int status;
1601         int i, j = 0;
1602
1603         spin_lock_bh(&adapter->mcc_lock);
1604
1605         wrb = wrb_from_mccq(adapter);
1606         if (!wrb) {
1607                 status = -EBUSY;
1608                 goto err;
1609         }
1610         req = cmd->va;
1611         sge = nonembedded_sgl(wrb);
1612         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1613                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1614         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1615                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1616
1617         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1618         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1619         sge->len = cpu_to_le32(cmd->size);
1620
1621         req->pattern = cpu_to_le64(pattern);
1622         req->byte_count = cpu_to_le32(byte_cnt);
1623         for (i = 0; i < byte_cnt; i++) {
1624                 req->snd_buff[i] = (u8)(pattern >> (j*8));
1625                 j++;
1626                 if (j > 7)
1627                         j = 0;
1628         }
1629
1630         status = be_mcc_notify_wait(adapter);
1631
1632         if (!status) {
1633                 struct be_cmd_resp_ddrdma_test *resp;
1634                 resp = cmd->va;
1635                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1636                                 resp->snd_err) {
1637                         status = -1;
1638                 }
1639         }
1640
1641 err:
1642         spin_unlock_bh(&adapter->mcc_lock);
1643         return status;
1644 }
1645
1646 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1647                                 struct be_dma_mem *nonemb_cmd)
1648 {
1649         struct be_mcc_wrb *wrb;
1650         struct be_cmd_req_seeprom_read *req;
1651         struct be_sge *sge;
1652         int status;
1653
1654         spin_lock_bh(&adapter->mcc_lock);
1655
1656         wrb = wrb_from_mccq(adapter);
1657         req = nonemb_cmd->va;
1658         sge = nonembedded_sgl(wrb);
1659
1660         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1661                         OPCODE_COMMON_SEEPROM_READ);
1662
1663         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1664                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1665
1666         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1667         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1668         sge->len = cpu_to_le32(nonemb_cmd->size);
1669
1670         status = be_mcc_notify_wait(adapter);
1671
1672         spin_unlock_bh(&adapter->mcc_lock);
1673         return status;
1674 }