be2net: fix tx completion polling
[linux-2.6.git] / drivers / net / benet / be_cmds.c
1 /*
2  * Copyright (C) 2005 - 2010 ServerEngines
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation.  The full GNU General
8  * Public License is included in this distribution in the file called COPYING.
9  *
10  * Contact Information:
11  * linux-drivers@serverengines.com
12  *
13  * ServerEngines
14  * 209 N. Fair Oaks Ave
15  * Sunnyvale, CA 94085
16  */
17
18 #include "be.h"
19 #include "be_cmds.h"
20
21 static void be_mcc_notify(struct be_adapter *adapter)
22 {
23         struct be_queue_info *mccq = &adapter->mcc_obj.q;
24         u32 val = 0;
25
26         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
28         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
29 }
30
31 /* To check if valid bit is set, check the entire word as we don't know
32  * the endianness of the data (old entry is host endian while a new entry is
33  * little endian) */
34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
35 {
36         if (compl->flags != 0) {
37                 compl->flags = le32_to_cpu(compl->flags);
38                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
39                 return true;
40         } else {
41                 return false;
42         }
43 }
44
45 /* Need to reset the entire word that houses the valid bit */
46 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
47 {
48         compl->flags = 0;
49 }
50
51 static int be_mcc_compl_process(struct be_adapter *adapter,
52         struct be_mcc_compl *compl)
53 {
54         u16 compl_status, extd_status;
55
56         /* Just swap the status to host endian; mcc tag is opaquely copied
57          * from mcc_wrb */
58         be_dws_le_to_cpu(compl, 4);
59
60         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
61                                 CQE_STATUS_COMPL_MASK;
62         if (compl_status == MCC_STATUS_SUCCESS) {
63                 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
64                         struct be_cmd_resp_get_stats *resp =
65                                                 adapter->stats.cmd.va;
66                         be_dws_le_to_cpu(&resp->hw_stats,
67                                                 sizeof(resp->hw_stats));
68                         netdev_stats_update(adapter);
69                 }
70         } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) {
71                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
72                                 CQE_STATUS_EXTD_MASK;
73                 dev_warn(&adapter->pdev->dev,
74                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
75                         compl->tag0, compl_status, extd_status);
76         }
77         return compl_status;
78 }
79
80 /* Link state evt is a string of bytes; no need for endian swapping */
81 static void be_async_link_state_process(struct be_adapter *adapter,
82                 struct be_async_event_link_state *evt)
83 {
84         be_link_status_update(adapter,
85                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
86 }
87
88 static inline bool is_link_state_evt(u32 trailer)
89 {
90         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
91                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
92                                 ASYNC_EVENT_CODE_LINK_STATE);
93 }
94
95 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
96 {
97         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
98         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
99
100         if (be_mcc_compl_is_new(compl)) {
101                 queue_tail_inc(mcc_cq);
102                 return compl;
103         }
104         return NULL;
105 }
106
107 void be_async_mcc_enable(struct be_adapter *adapter)
108 {
109         spin_lock_bh(&adapter->mcc_cq_lock);
110
111         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
112         adapter->mcc_obj.rearm_cq = true;
113
114         spin_unlock_bh(&adapter->mcc_cq_lock);
115 }
116
117 void be_async_mcc_disable(struct be_adapter *adapter)
118 {
119         adapter->mcc_obj.rearm_cq = false;
120 }
121
122 int be_process_mcc(struct be_adapter *adapter, int *status)
123 {
124         struct be_mcc_compl *compl;
125         int num = 0;
126         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
127
128         spin_lock_bh(&adapter->mcc_cq_lock);
129         while ((compl = be_mcc_compl_get(adapter))) {
130                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
131                         /* Interpret flags as an async trailer */
132                         BUG_ON(!is_link_state_evt(compl->flags));
133
134                         /* Interpret compl as a async link evt */
135                         be_async_link_state_process(adapter,
136                                 (struct be_async_event_link_state *) compl);
137                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
138                                 *status = be_mcc_compl_process(adapter, compl);
139                                 atomic_dec(&mcc_obj->q.used);
140                 }
141                 be_mcc_compl_use(compl);
142                 num++;
143         }
144
145         spin_unlock_bh(&adapter->mcc_cq_lock);
146         return num;
147 }
148
149 /* Wait till no more pending mcc requests are present */
150 static int be_mcc_wait_compl(struct be_adapter *adapter)
151 {
152 #define mcc_timeout             120000 /* 12s timeout */
153         int i, num, status = 0;
154         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
155
156         for (i = 0; i < mcc_timeout; i++) {
157                 num = be_process_mcc(adapter, &status);
158                 if (num)
159                         be_cq_notify(adapter, mcc_obj->cq.id,
160                                 mcc_obj->rearm_cq, num);
161
162                 if (atomic_read(&mcc_obj->q.used) == 0)
163                         break;
164                 udelay(100);
165         }
166         if (i == mcc_timeout) {
167                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
168                 return -1;
169         }
170         return status;
171 }
172
173 /* Notify MCC requests and wait for completion */
174 static int be_mcc_notify_wait(struct be_adapter *adapter)
175 {
176         be_mcc_notify(adapter);
177         return be_mcc_wait_compl(adapter);
178 }
179
180 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
181 {
182         int cnt = 0, wait = 5;
183         u32 ready;
184
185         do {
186                 ready = ioread32(db);
187                 if (ready == 0xffffffff) {
188                         dev_err(&adapter->pdev->dev,
189                                 "pci slot disconnected\n");
190                         return -1;
191                 }
192
193                 ready &= MPU_MAILBOX_DB_RDY_MASK;
194                 if (ready)
195                         break;
196
197                 if (cnt > 4000000) {
198                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
199                         return -1;
200                 }
201
202                 if (cnt > 50)
203                         wait = 200;
204                 cnt += wait;
205                 udelay(wait);
206         } while (true);
207
208         return 0;
209 }
210
211 /*
212  * Insert the mailbox address into the doorbell in two steps
213  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
214  */
215 static int be_mbox_notify_wait(struct be_adapter *adapter)
216 {
217         int status;
218         u32 val = 0;
219         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
220         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
221         struct be_mcc_mailbox *mbox = mbox_mem->va;
222         struct be_mcc_compl *compl = &mbox->compl;
223
224         /* wait for ready to be set */
225         status = be_mbox_db_ready_wait(adapter, db);
226         if (status != 0)
227                 return status;
228
229         val |= MPU_MAILBOX_DB_HI_MASK;
230         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
231         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
232         iowrite32(val, db);
233
234         /* wait for ready to be set */
235         status = be_mbox_db_ready_wait(adapter, db);
236         if (status != 0)
237                 return status;
238
239         val = 0;
240         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
241         val |= (u32)(mbox_mem->dma >> 4) << 2;
242         iowrite32(val, db);
243
244         status = be_mbox_db_ready_wait(adapter, db);
245         if (status != 0)
246                 return status;
247
248         /* A cq entry has been made now */
249         if (be_mcc_compl_is_new(compl)) {
250                 status = be_mcc_compl_process(adapter, &mbox->compl);
251                 be_mcc_compl_use(compl);
252                 if (status)
253                         return status;
254         } else {
255                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
256                 return -1;
257         }
258         return 0;
259 }
260
261 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
262 {
263         u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
264
265         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
266         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
267                 return -1;
268         else
269                 return 0;
270 }
271
272 int be_cmd_POST(struct be_adapter *adapter)
273 {
274         u16 stage;
275         int status, timeout = 0;
276
277         do {
278                 status = be_POST_stage_get(adapter, &stage);
279                 if (status) {
280                         dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
281                                 stage);
282                         return -1;
283                 } else if (stage != POST_STAGE_ARMFW_RDY) {
284                         set_current_state(TASK_INTERRUPTIBLE);
285                         schedule_timeout(2 * HZ);
286                         timeout += 2;
287                 } else {
288                         return 0;
289                 }
290         } while (timeout < 20);
291
292         dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
293         return -1;
294 }
295
296 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
297 {
298         return wrb->payload.embedded_payload;
299 }
300
301 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
302 {
303         return &wrb->payload.sgl[0];
304 }
305
306 /* Don't touch the hdr after it's prepared */
307 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
308                                 bool embedded, u8 sge_cnt, u32 opcode)
309 {
310         if (embedded)
311                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
312         else
313                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
314                                 MCC_WRB_SGE_CNT_SHIFT;
315         wrb->payload_length = payload_len;
316         wrb->tag0 = opcode;
317         be_dws_cpu_to_le(wrb, 8);
318 }
319
320 /* Don't touch the hdr after it's prepared */
321 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
322                                 u8 subsystem, u8 opcode, int cmd_len)
323 {
324         req_hdr->opcode = opcode;
325         req_hdr->subsystem = subsystem;
326         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
327         req_hdr->version = 0;
328 }
329
330 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
331                         struct be_dma_mem *mem)
332 {
333         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
334         u64 dma = (u64)mem->dma;
335
336         for (i = 0; i < buf_pages; i++) {
337                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
338                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
339                 dma += PAGE_SIZE_4K;
340         }
341 }
342
343 /* Converts interrupt delay in microseconds to multiplier value */
344 static u32 eq_delay_to_mult(u32 usec_delay)
345 {
346 #define MAX_INTR_RATE                   651042
347         const u32 round = 10;
348         u32 multiplier;
349
350         if (usec_delay == 0)
351                 multiplier = 0;
352         else {
353                 u32 interrupt_rate = 1000000 / usec_delay;
354                 /* Max delay, corresponding to the lowest interrupt rate */
355                 if (interrupt_rate == 0)
356                         multiplier = 1023;
357                 else {
358                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
359                         multiplier /= interrupt_rate;
360                         /* Round the multiplier to the closest value.*/
361                         multiplier = (multiplier + round/2) / round;
362                         multiplier = min(multiplier, (u32)1023);
363                 }
364         }
365         return multiplier;
366 }
367
368 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
369 {
370         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
371         struct be_mcc_wrb *wrb
372                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
373         memset(wrb, 0, sizeof(*wrb));
374         return wrb;
375 }
376
377 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
378 {
379         struct be_queue_info *mccq = &adapter->mcc_obj.q;
380         struct be_mcc_wrb *wrb;
381
382         if (atomic_read(&mccq->used) >= mccq->len) {
383                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
384                 return NULL;
385         }
386
387         wrb = queue_head_node(mccq);
388         queue_head_inc(mccq);
389         atomic_inc(&mccq->used);
390         memset(wrb, 0, sizeof(*wrb));
391         return wrb;
392 }
393
394 /* Tell fw we're about to start firing cmds by writing a
395  * special pattern across the wrb hdr; uses mbox
396  */
397 int be_cmd_fw_init(struct be_adapter *adapter)
398 {
399         u8 *wrb;
400         int status;
401
402         spin_lock(&adapter->mbox_lock);
403
404         wrb = (u8 *)wrb_from_mbox(adapter);
405         *wrb++ = 0xFF;
406         *wrb++ = 0x12;
407         *wrb++ = 0x34;
408         *wrb++ = 0xFF;
409         *wrb++ = 0xFF;
410         *wrb++ = 0x56;
411         *wrb++ = 0x78;
412         *wrb = 0xFF;
413
414         status = be_mbox_notify_wait(adapter);
415
416         spin_unlock(&adapter->mbox_lock);
417         return status;
418 }
419
420 /* Tell fw we're done with firing cmds by writing a
421  * special pattern across the wrb hdr; uses mbox
422  */
423 int be_cmd_fw_clean(struct be_adapter *adapter)
424 {
425         u8 *wrb;
426         int status;
427
428         if (adapter->eeh_err)
429                 return -EIO;
430
431         spin_lock(&adapter->mbox_lock);
432
433         wrb = (u8 *)wrb_from_mbox(adapter);
434         *wrb++ = 0xFF;
435         *wrb++ = 0xAA;
436         *wrb++ = 0xBB;
437         *wrb++ = 0xFF;
438         *wrb++ = 0xFF;
439         *wrb++ = 0xCC;
440         *wrb++ = 0xDD;
441         *wrb = 0xFF;
442
443         status = be_mbox_notify_wait(adapter);
444
445         spin_unlock(&adapter->mbox_lock);
446         return status;
447 }
448 int be_cmd_eq_create(struct be_adapter *adapter,
449                 struct be_queue_info *eq, int eq_delay)
450 {
451         struct be_mcc_wrb *wrb;
452         struct be_cmd_req_eq_create *req;
453         struct be_dma_mem *q_mem = &eq->dma_mem;
454         int status;
455
456         spin_lock(&adapter->mbox_lock);
457
458         wrb = wrb_from_mbox(adapter);
459         req = embedded_payload(wrb);
460
461         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
462
463         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
464                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
465
466         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
467
468         AMAP_SET_BITS(struct amap_eq_context, func, req->context,
469                         be_pci_func(adapter));
470         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
471         /* 4byte eqe*/
472         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
473         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
474                         __ilog2_u32(eq->len/256));
475         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
476                         eq_delay_to_mult(eq_delay));
477         be_dws_cpu_to_le(req->context, sizeof(req->context));
478
479         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
480
481         status = be_mbox_notify_wait(adapter);
482         if (!status) {
483                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
484                 eq->id = le16_to_cpu(resp->eq_id);
485                 eq->created = true;
486         }
487
488         spin_unlock(&adapter->mbox_lock);
489         return status;
490 }
491
492 /* Uses mbox */
493 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
494                         u8 type, bool permanent, u32 if_handle)
495 {
496         struct be_mcc_wrb *wrb;
497         struct be_cmd_req_mac_query *req;
498         int status;
499
500         spin_lock(&adapter->mbox_lock);
501
502         wrb = wrb_from_mbox(adapter);
503         req = embedded_payload(wrb);
504
505         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
506                         OPCODE_COMMON_NTWK_MAC_QUERY);
507
508         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
509                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
510
511         req->type = type;
512         if (permanent) {
513                 req->permanent = 1;
514         } else {
515                 req->if_id = cpu_to_le16((u16) if_handle);
516                 req->permanent = 0;
517         }
518
519         status = be_mbox_notify_wait(adapter);
520         if (!status) {
521                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
522                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
523         }
524
525         spin_unlock(&adapter->mbox_lock);
526         return status;
527 }
528
529 /* Uses synchronous MCCQ */
530 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
531                 u32 if_id, u32 *pmac_id)
532 {
533         struct be_mcc_wrb *wrb;
534         struct be_cmd_req_pmac_add *req;
535         int status;
536
537         spin_lock_bh(&adapter->mcc_lock);
538
539         wrb = wrb_from_mccq(adapter);
540         if (!wrb) {
541                 status = -EBUSY;
542                 goto err;
543         }
544         req = embedded_payload(wrb);
545
546         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
547                         OPCODE_COMMON_NTWK_PMAC_ADD);
548
549         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
550                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
551
552         req->if_id = cpu_to_le32(if_id);
553         memcpy(req->mac_address, mac_addr, ETH_ALEN);
554
555         status = be_mcc_notify_wait(adapter);
556         if (!status) {
557                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
558                 *pmac_id = le32_to_cpu(resp->pmac_id);
559         }
560
561 err:
562         spin_unlock_bh(&adapter->mcc_lock);
563         return status;
564 }
565
566 /* Uses synchronous MCCQ */
567 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
568 {
569         struct be_mcc_wrb *wrb;
570         struct be_cmd_req_pmac_del *req;
571         int status;
572
573         spin_lock_bh(&adapter->mcc_lock);
574
575         wrb = wrb_from_mccq(adapter);
576         if (!wrb) {
577                 status = -EBUSY;
578                 goto err;
579         }
580         req = embedded_payload(wrb);
581
582         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
583                         OPCODE_COMMON_NTWK_PMAC_DEL);
584
585         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
586                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
587
588         req->if_id = cpu_to_le32(if_id);
589         req->pmac_id = cpu_to_le32(pmac_id);
590
591         status = be_mcc_notify_wait(adapter);
592
593 err:
594         spin_unlock_bh(&adapter->mcc_lock);
595         return status;
596 }
597
598 /* Uses Mbox */
599 int be_cmd_cq_create(struct be_adapter *adapter,
600                 struct be_queue_info *cq, struct be_queue_info *eq,
601                 bool sol_evts, bool no_delay, int coalesce_wm)
602 {
603         struct be_mcc_wrb *wrb;
604         struct be_cmd_req_cq_create *req;
605         struct be_dma_mem *q_mem = &cq->dma_mem;
606         void *ctxt;
607         int status;
608
609         spin_lock(&adapter->mbox_lock);
610
611         wrb = wrb_from_mbox(adapter);
612         req = embedded_payload(wrb);
613         ctxt = &req->context;
614
615         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
616                         OPCODE_COMMON_CQ_CREATE);
617
618         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
619                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
620
621         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
622
623         AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
624         AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
625         AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
626                         __ilog2_u32(cq->len/256));
627         AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
628         AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
629         AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
630         AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
631         AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
632         AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter));
633         be_dws_cpu_to_le(ctxt, sizeof(req->context));
634
635         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
636
637         status = be_mbox_notify_wait(adapter);
638         if (!status) {
639                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
640                 cq->id = le16_to_cpu(resp->cq_id);
641                 cq->created = true;
642         }
643
644         spin_unlock(&adapter->mbox_lock);
645
646         return status;
647 }
648
649 static u32 be_encoded_q_len(int q_len)
650 {
651         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
652         if (len_encoded == 16)
653                 len_encoded = 0;
654         return len_encoded;
655 }
656
657 int be_cmd_mccq_create(struct be_adapter *adapter,
658                         struct be_queue_info *mccq,
659                         struct be_queue_info *cq)
660 {
661         struct be_mcc_wrb *wrb;
662         struct be_cmd_req_mcc_create *req;
663         struct be_dma_mem *q_mem = &mccq->dma_mem;
664         void *ctxt;
665         int status;
666
667         spin_lock(&adapter->mbox_lock);
668
669         wrb = wrb_from_mbox(adapter);
670         req = embedded_payload(wrb);
671         ctxt = &req->context;
672
673         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
674                         OPCODE_COMMON_MCC_CREATE);
675
676         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
677                         OPCODE_COMMON_MCC_CREATE, sizeof(*req));
678
679         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
680
681         AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter));
682         AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
683         AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
684                 be_encoded_q_len(mccq->len));
685         AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
686
687         be_dws_cpu_to_le(ctxt, sizeof(req->context));
688
689         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
690
691         status = be_mbox_notify_wait(adapter);
692         if (!status) {
693                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
694                 mccq->id = le16_to_cpu(resp->id);
695                 mccq->created = true;
696         }
697         spin_unlock(&adapter->mbox_lock);
698
699         return status;
700 }
701
702 int be_cmd_txq_create(struct be_adapter *adapter,
703                         struct be_queue_info *txq,
704                         struct be_queue_info *cq)
705 {
706         struct be_mcc_wrb *wrb;
707         struct be_cmd_req_eth_tx_create *req;
708         struct be_dma_mem *q_mem = &txq->dma_mem;
709         void *ctxt;
710         int status;
711
712         spin_lock(&adapter->mbox_lock);
713
714         wrb = wrb_from_mbox(adapter);
715         req = embedded_payload(wrb);
716         ctxt = &req->context;
717
718         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
719                         OPCODE_ETH_TX_CREATE);
720
721         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
722                 sizeof(*req));
723
724         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
725         req->ulp_num = BE_ULP1_NUM;
726         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
727
728         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
729                 be_encoded_q_len(txq->len));
730         AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
731                         be_pci_func(adapter));
732         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
733         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
734
735         be_dws_cpu_to_le(ctxt, sizeof(req->context));
736
737         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
738
739         status = be_mbox_notify_wait(adapter);
740         if (!status) {
741                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
742                 txq->id = le16_to_cpu(resp->cid);
743                 txq->created = true;
744         }
745
746         spin_unlock(&adapter->mbox_lock);
747
748         return status;
749 }
750
751 /* Uses mbox */
752 int be_cmd_rxq_create(struct be_adapter *adapter,
753                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
754                 u16 max_frame_size, u32 if_id, u32 rss)
755 {
756         struct be_mcc_wrb *wrb;
757         struct be_cmd_req_eth_rx_create *req;
758         struct be_dma_mem *q_mem = &rxq->dma_mem;
759         int status;
760
761         spin_lock(&adapter->mbox_lock);
762
763         wrb = wrb_from_mbox(adapter);
764         req = embedded_payload(wrb);
765
766         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
767                         OPCODE_ETH_RX_CREATE);
768
769         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
770                 sizeof(*req));
771
772         req->cq_id = cpu_to_le16(cq_id);
773         req->frag_size = fls(frag_size) - 1;
774         req->num_pages = 2;
775         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
776         req->interface_id = cpu_to_le32(if_id);
777         req->max_frame_size = cpu_to_le16(max_frame_size);
778         req->rss_queue = cpu_to_le32(rss);
779
780         status = be_mbox_notify_wait(adapter);
781         if (!status) {
782                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
783                 rxq->id = le16_to_cpu(resp->id);
784                 rxq->created = true;
785         }
786
787         spin_unlock(&adapter->mbox_lock);
788
789         return status;
790 }
791
792 /* Generic destroyer function for all types of queues
793  * Uses Mbox
794  */
795 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
796                 int queue_type)
797 {
798         struct be_mcc_wrb *wrb;
799         struct be_cmd_req_q_destroy *req;
800         u8 subsys = 0, opcode = 0;
801         int status;
802
803         if (adapter->eeh_err)
804                 return -EIO;
805
806         spin_lock(&adapter->mbox_lock);
807
808         wrb = wrb_from_mbox(adapter);
809         req = embedded_payload(wrb);
810
811         switch (queue_type) {
812         case QTYPE_EQ:
813                 subsys = CMD_SUBSYSTEM_COMMON;
814                 opcode = OPCODE_COMMON_EQ_DESTROY;
815                 break;
816         case QTYPE_CQ:
817                 subsys = CMD_SUBSYSTEM_COMMON;
818                 opcode = OPCODE_COMMON_CQ_DESTROY;
819                 break;
820         case QTYPE_TXQ:
821                 subsys = CMD_SUBSYSTEM_ETH;
822                 opcode = OPCODE_ETH_TX_DESTROY;
823                 break;
824         case QTYPE_RXQ:
825                 subsys = CMD_SUBSYSTEM_ETH;
826                 opcode = OPCODE_ETH_RX_DESTROY;
827                 break;
828         case QTYPE_MCCQ:
829                 subsys = CMD_SUBSYSTEM_COMMON;
830                 opcode = OPCODE_COMMON_MCC_DESTROY;
831                 break;
832         default:
833                 BUG();
834         }
835
836         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
837
838         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
839         req->id = cpu_to_le16(q->id);
840
841         status = be_mbox_notify_wait(adapter);
842
843         spin_unlock(&adapter->mbox_lock);
844
845         return status;
846 }
847
848 /* Create an rx filtering policy configuration on an i/f
849  * Uses mbox
850  */
851 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
852                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
853 {
854         struct be_mcc_wrb *wrb;
855         struct be_cmd_req_if_create *req;
856         int status;
857
858         spin_lock(&adapter->mbox_lock);
859
860         wrb = wrb_from_mbox(adapter);
861         req = embedded_payload(wrb);
862
863         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
864                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
865
866         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
867                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
868
869         req->capability_flags = cpu_to_le32(cap_flags);
870         req->enable_flags = cpu_to_le32(en_flags);
871         req->pmac_invalid = pmac_invalid;
872         if (!pmac_invalid)
873                 memcpy(req->mac_addr, mac, ETH_ALEN);
874
875         status = be_mbox_notify_wait(adapter);
876         if (!status) {
877                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
878                 *if_handle = le32_to_cpu(resp->interface_id);
879                 if (!pmac_invalid)
880                         *pmac_id = le32_to_cpu(resp->pmac_id);
881         }
882
883         spin_unlock(&adapter->mbox_lock);
884         return status;
885 }
886
887 /* Uses mbox */
888 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
889 {
890         struct be_mcc_wrb *wrb;
891         struct be_cmd_req_if_destroy *req;
892         int status;
893
894         if (adapter->eeh_err)
895                 return -EIO;
896
897         spin_lock(&adapter->mbox_lock);
898
899         wrb = wrb_from_mbox(adapter);
900         req = embedded_payload(wrb);
901
902         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
903                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
904
905         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
906                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
907
908         req->interface_id = cpu_to_le32(interface_id);
909
910         status = be_mbox_notify_wait(adapter);
911
912         spin_unlock(&adapter->mbox_lock);
913
914         return status;
915 }
916
917 /* Get stats is a non embedded command: the request is not embedded inside
918  * WRB but is a separate dma memory block
919  * Uses asynchronous MCC
920  */
921 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
922 {
923         struct be_mcc_wrb *wrb;
924         struct be_cmd_req_get_stats *req;
925         struct be_sge *sge;
926         int status = 0;
927
928         spin_lock_bh(&adapter->mcc_lock);
929
930         wrb = wrb_from_mccq(adapter);
931         if (!wrb) {
932                 status = -EBUSY;
933                 goto err;
934         }
935         req = nonemb_cmd->va;
936         sge = nonembedded_sgl(wrb);
937
938         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
939                         OPCODE_ETH_GET_STATISTICS);
940
941         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
942                 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
943         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
944         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
945         sge->len = cpu_to_le32(nonemb_cmd->size);
946
947         be_mcc_notify(adapter);
948
949 err:
950         spin_unlock_bh(&adapter->mcc_lock);
951         return status;
952 }
953
954 /* Uses synchronous mcc */
955 int be_cmd_link_status_query(struct be_adapter *adapter,
956                         bool *link_up, u8 *mac_speed, u16 *link_speed)
957 {
958         struct be_mcc_wrb *wrb;
959         struct be_cmd_req_link_status *req;
960         int status;
961
962         spin_lock_bh(&adapter->mcc_lock);
963
964         wrb = wrb_from_mccq(adapter);
965         if (!wrb) {
966                 status = -EBUSY;
967                 goto err;
968         }
969         req = embedded_payload(wrb);
970
971         *link_up = false;
972
973         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
974                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
975
976         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
977                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
978
979         status = be_mcc_notify_wait(adapter);
980         if (!status) {
981                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
982                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
983                         *link_up = true;
984                         *link_speed = le16_to_cpu(resp->link_speed);
985                         *mac_speed = resp->mac_speed;
986                 }
987         }
988
989 err:
990         spin_unlock_bh(&adapter->mcc_lock);
991         return status;
992 }
993
994 /* Uses Mbox */
995 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
996 {
997         struct be_mcc_wrb *wrb;
998         struct be_cmd_req_get_fw_version *req;
999         int status;
1000
1001         spin_lock(&adapter->mbox_lock);
1002
1003         wrb = wrb_from_mbox(adapter);
1004         req = embedded_payload(wrb);
1005
1006         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1007                         OPCODE_COMMON_GET_FW_VERSION);
1008
1009         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1010                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1011
1012         status = be_mbox_notify_wait(adapter);
1013         if (!status) {
1014                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1015                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1016         }
1017
1018         spin_unlock(&adapter->mbox_lock);
1019         return status;
1020 }
1021
1022 /* set the EQ delay interval of an EQ to specified value
1023  * Uses async mcc
1024  */
1025 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1026 {
1027         struct be_mcc_wrb *wrb;
1028         struct be_cmd_req_modify_eq_delay *req;
1029         int status = 0;
1030
1031         spin_lock_bh(&adapter->mcc_lock);
1032
1033         wrb = wrb_from_mccq(adapter);
1034         if (!wrb) {
1035                 status = -EBUSY;
1036                 goto err;
1037         }
1038         req = embedded_payload(wrb);
1039
1040         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1041                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1042
1043         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1044                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1045
1046         req->num_eq = cpu_to_le32(1);
1047         req->delay[0].eq_id = cpu_to_le32(eq_id);
1048         req->delay[0].phase = 0;
1049         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1050
1051         be_mcc_notify(adapter);
1052
1053 err:
1054         spin_unlock_bh(&adapter->mcc_lock);
1055         return status;
1056 }
1057
1058 /* Uses sycnhronous mcc */
1059 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1060                         u32 num, bool untagged, bool promiscuous)
1061 {
1062         struct be_mcc_wrb *wrb;
1063         struct be_cmd_req_vlan_config *req;
1064         int status;
1065
1066         spin_lock_bh(&adapter->mcc_lock);
1067
1068         wrb = wrb_from_mccq(adapter);
1069         if (!wrb) {
1070                 status = -EBUSY;
1071                 goto err;
1072         }
1073         req = embedded_payload(wrb);
1074
1075         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1076                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1077
1078         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1079                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1080
1081         req->interface_id = if_id;
1082         req->promiscuous = promiscuous;
1083         req->untagged = untagged;
1084         req->num_vlan = num;
1085         if (!promiscuous) {
1086                 memcpy(req->normal_vlan, vtag_array,
1087                         req->num_vlan * sizeof(vtag_array[0]));
1088         }
1089
1090         status = be_mcc_notify_wait(adapter);
1091
1092 err:
1093         spin_unlock_bh(&adapter->mcc_lock);
1094         return status;
1095 }
1096
1097 /* Uses MCC for this command as it may be called in BH context
1098  * Uses synchronous mcc
1099  */
1100 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1101 {
1102         struct be_mcc_wrb *wrb;
1103         struct be_cmd_req_promiscuous_config *req;
1104         int status;
1105
1106         spin_lock_bh(&adapter->mcc_lock);
1107
1108         wrb = wrb_from_mccq(adapter);
1109         if (!wrb) {
1110                 status = -EBUSY;
1111                 goto err;
1112         }
1113         req = embedded_payload(wrb);
1114
1115         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1116
1117         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1118                 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1119
1120         if (port_num)
1121                 req->port1_promiscuous = en;
1122         else
1123                 req->port0_promiscuous = en;
1124
1125         status = be_mcc_notify_wait(adapter);
1126
1127 err:
1128         spin_unlock_bh(&adapter->mcc_lock);
1129         return status;
1130 }
1131
1132 /*
1133  * Uses MCC for this command as it may be called in BH context
1134  * (mc == NULL) => multicast promiscous
1135  */
1136 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1137                 struct net_device *netdev, struct be_dma_mem *mem)
1138 {
1139         struct be_mcc_wrb *wrb;
1140         struct be_cmd_req_mcast_mac_config *req = mem->va;
1141         struct be_sge *sge;
1142         int status;
1143
1144         spin_lock_bh(&adapter->mcc_lock);
1145
1146         wrb = wrb_from_mccq(adapter);
1147         if (!wrb) {
1148                 status = -EBUSY;
1149                 goto err;
1150         }
1151         sge = nonembedded_sgl(wrb);
1152         memset(req, 0, sizeof(*req));
1153
1154         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1155                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1156         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1157         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1158         sge->len = cpu_to_le32(mem->size);
1159
1160         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1161                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1162
1163         req->interface_id = if_id;
1164         if (netdev) {
1165                 int i;
1166                 struct dev_mc_list *mc;
1167
1168                 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1169
1170                 i = 0;
1171                 netdev_for_each_mc_addr(mc, netdev)
1172                         memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
1173         } else {
1174                 req->promiscuous = 1;
1175         }
1176
1177         status = be_mcc_notify_wait(adapter);
1178
1179 err:
1180         spin_unlock_bh(&adapter->mcc_lock);
1181         return status;
1182 }
1183
1184 /* Uses synchrounous mcc */
1185 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1186 {
1187         struct be_mcc_wrb *wrb;
1188         struct be_cmd_req_set_flow_control *req;
1189         int status;
1190
1191         spin_lock_bh(&adapter->mcc_lock);
1192
1193         wrb = wrb_from_mccq(adapter);
1194         if (!wrb) {
1195                 status = -EBUSY;
1196                 goto err;
1197         }
1198         req = embedded_payload(wrb);
1199
1200         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1201                         OPCODE_COMMON_SET_FLOW_CONTROL);
1202
1203         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1204                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1205
1206         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1207         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1208
1209         status = be_mcc_notify_wait(adapter);
1210
1211 err:
1212         spin_unlock_bh(&adapter->mcc_lock);
1213         return status;
1214 }
1215
1216 /* Uses sycn mcc */
1217 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1218 {
1219         struct be_mcc_wrb *wrb;
1220         struct be_cmd_req_get_flow_control *req;
1221         int status;
1222
1223         spin_lock_bh(&adapter->mcc_lock);
1224
1225         wrb = wrb_from_mccq(adapter);
1226         if (!wrb) {
1227                 status = -EBUSY;
1228                 goto err;
1229         }
1230         req = embedded_payload(wrb);
1231
1232         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1233                         OPCODE_COMMON_GET_FLOW_CONTROL);
1234
1235         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1236                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1237
1238         status = be_mcc_notify_wait(adapter);
1239         if (!status) {
1240                 struct be_cmd_resp_get_flow_control *resp =
1241                                                 embedded_payload(wrb);
1242                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1243                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1244         }
1245
1246 err:
1247         spin_unlock_bh(&adapter->mcc_lock);
1248         return status;
1249 }
1250
1251 /* Uses mbox */
1252 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
1253 {
1254         struct be_mcc_wrb *wrb;
1255         struct be_cmd_req_query_fw_cfg *req;
1256         int status;
1257
1258         spin_lock(&adapter->mbox_lock);
1259
1260         wrb = wrb_from_mbox(adapter);
1261         req = embedded_payload(wrb);
1262
1263         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1264                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1265
1266         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1267                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1268
1269         status = be_mbox_notify_wait(adapter);
1270         if (!status) {
1271                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1272                 *port_num = le32_to_cpu(resp->phys_port);
1273                 *cap = le32_to_cpu(resp->function_cap);
1274         }
1275
1276         spin_unlock(&adapter->mbox_lock);
1277         return status;
1278 }
1279
1280 /* Uses mbox */
1281 int be_cmd_reset_function(struct be_adapter *adapter)
1282 {
1283         struct be_mcc_wrb *wrb;
1284         struct be_cmd_req_hdr *req;
1285         int status;
1286
1287         spin_lock(&adapter->mbox_lock);
1288
1289         wrb = wrb_from_mbox(adapter);
1290         req = embedded_payload(wrb);
1291
1292         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1293                         OPCODE_COMMON_FUNCTION_RESET);
1294
1295         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1296                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1297
1298         status = be_mbox_notify_wait(adapter);
1299
1300         spin_unlock(&adapter->mbox_lock);
1301         return status;
1302 }
1303
1304 /* Uses sync mcc */
1305 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1306                         u8 bcn, u8 sts, u8 state)
1307 {
1308         struct be_mcc_wrb *wrb;
1309         struct be_cmd_req_enable_disable_beacon *req;
1310         int status;
1311
1312         spin_lock_bh(&adapter->mcc_lock);
1313
1314         wrb = wrb_from_mccq(adapter);
1315         if (!wrb) {
1316                 status = -EBUSY;
1317                 goto err;
1318         }
1319         req = embedded_payload(wrb);
1320
1321         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1322                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1323
1324         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1325                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1326
1327         req->port_num = port_num;
1328         req->beacon_state = state;
1329         req->beacon_duration = bcn;
1330         req->status_duration = sts;
1331
1332         status = be_mcc_notify_wait(adapter);
1333
1334 err:
1335         spin_unlock_bh(&adapter->mcc_lock);
1336         return status;
1337 }
1338
1339 /* Uses sync mcc */
1340 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1341 {
1342         struct be_mcc_wrb *wrb;
1343         struct be_cmd_req_get_beacon_state *req;
1344         int status;
1345
1346         spin_lock_bh(&adapter->mcc_lock);
1347
1348         wrb = wrb_from_mccq(adapter);
1349         if (!wrb) {
1350                 status = -EBUSY;
1351                 goto err;
1352         }
1353         req = embedded_payload(wrb);
1354
1355         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1356                         OPCODE_COMMON_GET_BEACON_STATE);
1357
1358         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1359                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1360
1361         req->port_num = port_num;
1362
1363         status = be_mcc_notify_wait(adapter);
1364         if (!status) {
1365                 struct be_cmd_resp_get_beacon_state *resp =
1366                                                 embedded_payload(wrb);
1367                 *state = resp->beacon_state;
1368         }
1369
1370 err:
1371         spin_unlock_bh(&adapter->mcc_lock);
1372         return status;
1373 }
1374
1375 /* Uses sync mcc */
1376 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1377                                 u8 *connector)
1378 {
1379         struct be_mcc_wrb *wrb;
1380         struct be_cmd_req_port_type *req;
1381         int status;
1382
1383         spin_lock_bh(&adapter->mcc_lock);
1384
1385         wrb = wrb_from_mccq(adapter);
1386         if (!wrb) {
1387                 status = -EBUSY;
1388                 goto err;
1389         }
1390         req = embedded_payload(wrb);
1391
1392         be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1393                         OPCODE_COMMON_READ_TRANSRECV_DATA);
1394
1395         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1396                 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1397
1398         req->port = cpu_to_le32(port);
1399         req->page_num = cpu_to_le32(TR_PAGE_A0);
1400         status = be_mcc_notify_wait(adapter);
1401         if (!status) {
1402                 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1403                         *connector = resp->data.connector;
1404         }
1405
1406 err:
1407         spin_unlock_bh(&adapter->mcc_lock);
1408         return status;
1409 }
1410
1411 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1412                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1413 {
1414         struct be_mcc_wrb *wrb;
1415         struct be_cmd_write_flashrom *req;
1416         struct be_sge *sge;
1417         int status;
1418
1419         spin_lock_bh(&adapter->mcc_lock);
1420
1421         wrb = wrb_from_mccq(adapter);
1422         if (!wrb) {
1423                 status = -EBUSY;
1424                 goto err;
1425         }
1426         req = cmd->va;
1427         sge = nonembedded_sgl(wrb);
1428
1429         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1430                         OPCODE_COMMON_WRITE_FLASHROM);
1431
1432         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1433                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1434         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1435         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1436         sge->len = cpu_to_le32(cmd->size);
1437
1438         req->params.op_type = cpu_to_le32(flash_type);
1439         req->params.op_code = cpu_to_le32(flash_opcode);
1440         req->params.data_buf_size = cpu_to_le32(buf_size);
1441
1442         status = be_mcc_notify_wait(adapter);
1443
1444 err:
1445         spin_unlock_bh(&adapter->mcc_lock);
1446         return status;
1447 }
1448
1449 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1450                          int offset)
1451 {
1452         struct be_mcc_wrb *wrb;
1453         struct be_cmd_write_flashrom *req;
1454         int status;
1455
1456         spin_lock_bh(&adapter->mcc_lock);
1457
1458         wrb = wrb_from_mccq(adapter);
1459         if (!wrb) {
1460                 status = -EBUSY;
1461                 goto err;
1462         }
1463         req = embedded_payload(wrb);
1464
1465         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1466                         OPCODE_COMMON_READ_FLASHROM);
1467
1468         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1469                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1470
1471         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1472         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1473         req->params.offset = offset;
1474         req->params.data_buf_size = 0x4;
1475
1476         status = be_mcc_notify_wait(adapter);
1477         if (!status)
1478                 memcpy(flashed_crc, req->params.data_buf, 4);
1479
1480 err:
1481         spin_unlock_bh(&adapter->mcc_lock);
1482         return status;
1483 }
1484
1485 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1486                                 struct be_dma_mem *nonemb_cmd)
1487 {
1488         struct be_mcc_wrb *wrb;
1489         struct be_cmd_req_acpi_wol_magic_config *req;
1490         struct be_sge *sge;
1491         int status;
1492
1493         spin_lock_bh(&adapter->mcc_lock);
1494
1495         wrb = wrb_from_mccq(adapter);
1496         if (!wrb) {
1497                 status = -EBUSY;
1498                 goto err;
1499         }
1500         req = nonemb_cmd->va;
1501         sge = nonembedded_sgl(wrb);
1502
1503         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1504                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1505
1506         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1507                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1508         memcpy(req->magic_mac, mac, ETH_ALEN);
1509
1510         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1511         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1512         sge->len = cpu_to_le32(nonemb_cmd->size);
1513
1514         status = be_mcc_notify_wait(adapter);
1515
1516 err:
1517         spin_unlock_bh(&adapter->mcc_lock);
1518         return status;
1519 }
1520
1521 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1522                         u8 loopback_type, u8 enable)
1523 {
1524         struct be_mcc_wrb *wrb;
1525         struct be_cmd_req_set_lmode *req;
1526         int status;
1527
1528         spin_lock_bh(&adapter->mcc_lock);
1529
1530         wrb = wrb_from_mccq(adapter);
1531         if (!wrb) {
1532                 status = -EBUSY;
1533                 goto err;
1534         }
1535
1536         req = embedded_payload(wrb);
1537
1538         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1539                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1540
1541         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1542                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1543                         sizeof(*req));
1544
1545         req->src_port = port_num;
1546         req->dest_port = port_num;
1547         req->loopback_type = loopback_type;
1548         req->loopback_state = enable;
1549
1550         status = be_mcc_notify_wait(adapter);
1551 err:
1552         spin_unlock_bh(&adapter->mcc_lock);
1553         return status;
1554 }
1555
1556 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1557                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1558 {
1559         struct be_mcc_wrb *wrb;
1560         struct be_cmd_req_loopback_test *req;
1561         int status;
1562
1563         spin_lock_bh(&adapter->mcc_lock);
1564
1565         wrb = wrb_from_mccq(adapter);
1566         if (!wrb) {
1567                 status = -EBUSY;
1568                 goto err;
1569         }
1570
1571         req = embedded_payload(wrb);
1572
1573         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1574                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1575
1576         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1577                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1578         req->hdr.timeout = 4;
1579
1580         req->pattern = cpu_to_le64(pattern);
1581         req->src_port = cpu_to_le32(port_num);
1582         req->dest_port = cpu_to_le32(port_num);
1583         req->pkt_size = cpu_to_le32(pkt_size);
1584         req->num_pkts = cpu_to_le32(num_pkts);
1585         req->loopback_type = cpu_to_le32(loopback_type);
1586
1587         status = be_mcc_notify_wait(adapter);
1588         if (!status) {
1589                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1590                 status = le32_to_cpu(resp->status);
1591         }
1592
1593 err:
1594         spin_unlock_bh(&adapter->mcc_lock);
1595         return status;
1596 }
1597
1598 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1599                                 u32 byte_cnt, struct be_dma_mem *cmd)
1600 {
1601         struct be_mcc_wrb *wrb;
1602         struct be_cmd_req_ddrdma_test *req;
1603         struct be_sge *sge;
1604         int status;
1605         int i, j = 0;
1606
1607         spin_lock_bh(&adapter->mcc_lock);
1608
1609         wrb = wrb_from_mccq(adapter);
1610         if (!wrb) {
1611                 status = -EBUSY;
1612                 goto err;
1613         }
1614         req = cmd->va;
1615         sge = nonembedded_sgl(wrb);
1616         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1617                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1618         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1619                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1620
1621         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1622         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1623         sge->len = cpu_to_le32(cmd->size);
1624
1625         req->pattern = cpu_to_le64(pattern);
1626         req->byte_count = cpu_to_le32(byte_cnt);
1627         for (i = 0; i < byte_cnt; i++) {
1628                 req->snd_buff[i] = (u8)(pattern >> (j*8));
1629                 j++;
1630                 if (j > 7)
1631                         j = 0;
1632         }
1633
1634         status = be_mcc_notify_wait(adapter);
1635
1636         if (!status) {
1637                 struct be_cmd_resp_ddrdma_test *resp;
1638                 resp = cmd->va;
1639                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1640                                 resp->snd_err) {
1641                         status = -1;
1642                 }
1643         }
1644
1645 err:
1646         spin_unlock_bh(&adapter->mcc_lock);
1647         return status;
1648 }
1649
1650 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1651                                 struct be_dma_mem *nonemb_cmd)
1652 {
1653         struct be_mcc_wrb *wrb;
1654         struct be_cmd_req_seeprom_read *req;
1655         struct be_sge *sge;
1656         int status;
1657
1658         spin_lock_bh(&adapter->mcc_lock);
1659
1660         wrb = wrb_from_mccq(adapter);
1661         req = nonemb_cmd->va;
1662         sge = nonembedded_sgl(wrb);
1663
1664         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1665                         OPCODE_COMMON_SEEPROM_READ);
1666
1667         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1668                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1669
1670         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1671         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1672         sge->len = cpu_to_le32(nonemb_cmd->size);
1673
1674         status = be_mcc_notify_wait(adapter);
1675
1676         spin_unlock_bh(&adapter->mcc_lock);
1677         return status;
1678 }