Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / benet / be_cmds.c
1 /*
2  * Copyright (C) 2005 - 2009 ServerEngines
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation.  The full GNU General
8  * Public License is included in this distribution in the file called COPYING.
9  *
10  * Contact Information:
11  * linux-drivers@serverengines.com
12  *
13  * ServerEngines
14  * 209 N. Fair Oaks Ave
15  * Sunnyvale, CA 94085
16  */
17
18 #include "be.h"
19 #include "be_cmds.h"
20
21 static void be_mcc_notify(struct be_adapter *adapter)
22 {
23         struct be_queue_info *mccq = &adapter->mcc_obj.q;
24         u32 val = 0;
25
26         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
28         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
29 }
30
31 /* To check if valid bit is set, check the entire word as we don't know
32  * the endianness of the data (old entry is host endian while a new entry is
33  * little endian) */
34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
35 {
36         if (compl->flags != 0) {
37                 compl->flags = le32_to_cpu(compl->flags);
38                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
39                 return true;
40         } else {
41                 return false;
42         }
43 }
44
45 /* Need to reset the entire word that houses the valid bit */
46 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
47 {
48         compl->flags = 0;
49 }
50
51 static int be_mcc_compl_process(struct be_adapter *adapter,
52         struct be_mcc_compl *compl)
53 {
54         u16 compl_status, extd_status;
55
56         /* Just swap the status to host endian; mcc tag is opaquely copied
57          * from mcc_wrb */
58         be_dws_le_to_cpu(compl, 4);
59
60         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
61                                 CQE_STATUS_COMPL_MASK;
62         if (compl_status == MCC_STATUS_SUCCESS) {
63                 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
64                         struct be_cmd_resp_get_stats *resp =
65                                                 adapter->stats.cmd.va;
66                         be_dws_le_to_cpu(&resp->hw_stats,
67                                                 sizeof(resp->hw_stats));
68                         netdev_stats_update(adapter);
69                 }
70         } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) {
71                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
72                                 CQE_STATUS_EXTD_MASK;
73                 dev_warn(&adapter->pdev->dev,
74                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
75                         compl->tag0, compl_status, extd_status);
76         }
77         return compl_status;
78 }
79
80 /* Link state evt is a string of bytes; no need for endian swapping */
81 static void be_async_link_state_process(struct be_adapter *adapter,
82                 struct be_async_event_link_state *evt)
83 {
84         be_link_status_update(adapter,
85                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
86 }
87
88 static inline bool is_link_state_evt(u32 trailer)
89 {
90         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
91                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
92                                 ASYNC_EVENT_CODE_LINK_STATE);
93 }
94
95 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
96 {
97         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
98         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
99
100         if (be_mcc_compl_is_new(compl)) {
101                 queue_tail_inc(mcc_cq);
102                 return compl;
103         }
104         return NULL;
105 }
106
107 int be_process_mcc(struct be_adapter *adapter)
108 {
109         struct be_mcc_compl *compl;
110         int num = 0, status = 0;
111
112         spin_lock_bh(&adapter->mcc_cq_lock);
113         while ((compl = be_mcc_compl_get(adapter))) {
114                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
115                         /* Interpret flags as an async trailer */
116                         BUG_ON(!is_link_state_evt(compl->flags));
117
118                         /* Interpret compl as a async link evt */
119                         be_async_link_state_process(adapter,
120                                 (struct be_async_event_link_state *) compl);
121                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
122                                 status = be_mcc_compl_process(adapter, compl);
123                                 atomic_dec(&adapter->mcc_obj.q.used);
124                 }
125                 be_mcc_compl_use(compl);
126                 num++;
127         }
128
129         if (num)
130                 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, num);
131
132         spin_unlock_bh(&adapter->mcc_cq_lock);
133         return status;
134 }
135
136 /* Wait till no more pending mcc requests are present */
137 static int be_mcc_wait_compl(struct be_adapter *adapter)
138 {
139 #define mcc_timeout             120000 /* 12s timeout */
140         int i, status;
141         for (i = 0; i < mcc_timeout; i++) {
142                 status = be_process_mcc(adapter);
143                 if (status)
144                         return status;
145
146                 if (atomic_read(&adapter->mcc_obj.q.used) == 0)
147                         break;
148                 udelay(100);
149         }
150         if (i == mcc_timeout) {
151                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
152                 return -1;
153         }
154         return 0;
155 }
156
157 /* Notify MCC requests and wait for completion */
158 static int be_mcc_notify_wait(struct be_adapter *adapter)
159 {
160         be_mcc_notify(adapter);
161         return be_mcc_wait_compl(adapter);
162 }
163
164 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
165 {
166         int cnt = 0, wait = 5;
167         u32 ready;
168
169         do {
170                 ready = ioread32(db);
171                 if (ready == 0xffffffff) {
172                         dev_err(&adapter->pdev->dev,
173                                 "pci slot disconnected\n");
174                         return -1;
175                 }
176
177                 ready &= MPU_MAILBOX_DB_RDY_MASK;
178                 if (ready)
179                         break;
180
181                 if (cnt > 4000000) {
182                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
183                         return -1;
184                 }
185
186                 if (cnt > 50)
187                         wait = 200;
188                 cnt += wait;
189                 udelay(wait);
190         } while (true);
191
192         return 0;
193 }
194
195 /*
196  * Insert the mailbox address into the doorbell in two steps
197  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
198  */
199 static int be_mbox_notify_wait(struct be_adapter *adapter)
200 {
201         int status;
202         u32 val = 0;
203         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
204         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
205         struct be_mcc_mailbox *mbox = mbox_mem->va;
206         struct be_mcc_compl *compl = &mbox->compl;
207
208         /* wait for ready to be set */
209         status = be_mbox_db_ready_wait(adapter, db);
210         if (status != 0)
211                 return status;
212
213         val |= MPU_MAILBOX_DB_HI_MASK;
214         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
215         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
216         iowrite32(val, db);
217
218         /* wait for ready to be set */
219         status = be_mbox_db_ready_wait(adapter, db);
220         if (status != 0)
221                 return status;
222
223         val = 0;
224         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
225         val |= (u32)(mbox_mem->dma >> 4) << 2;
226         iowrite32(val, db);
227
228         status = be_mbox_db_ready_wait(adapter, db);
229         if (status != 0)
230                 return status;
231
232         /* A cq entry has been made now */
233         if (be_mcc_compl_is_new(compl)) {
234                 status = be_mcc_compl_process(adapter, &mbox->compl);
235                 be_mcc_compl_use(compl);
236                 if (status)
237                         return status;
238         } else {
239                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
240                 return -1;
241         }
242         return 0;
243 }
244
245 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
246 {
247         u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
248
249         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
250         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
251                 return -1;
252         else
253                 return 0;
254 }
255
256 int be_cmd_POST(struct be_adapter *adapter)
257 {
258         u16 stage;
259         int status, timeout = 0;
260
261         do {
262                 status = be_POST_stage_get(adapter, &stage);
263                 if (status) {
264                         dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
265                                 stage);
266                         return -1;
267                 } else if (stage != POST_STAGE_ARMFW_RDY) {
268                         set_current_state(TASK_INTERRUPTIBLE);
269                         schedule_timeout(2 * HZ);
270                         timeout += 2;
271                 } else {
272                         return 0;
273                 }
274         } while (timeout < 20);
275
276         dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
277         return -1;
278 }
279
280 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
281 {
282         return wrb->payload.embedded_payload;
283 }
284
285 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
286 {
287         return &wrb->payload.sgl[0];
288 }
289
290 /* Don't touch the hdr after it's prepared */
291 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
292                                 bool embedded, u8 sge_cnt, u32 opcode)
293 {
294         if (embedded)
295                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
296         else
297                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
298                                 MCC_WRB_SGE_CNT_SHIFT;
299         wrb->payload_length = payload_len;
300         wrb->tag0 = opcode;
301         be_dws_cpu_to_le(wrb, 8);
302 }
303
304 /* Don't touch the hdr after it's prepared */
305 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
306                                 u8 subsystem, u8 opcode, int cmd_len)
307 {
308         req_hdr->opcode = opcode;
309         req_hdr->subsystem = subsystem;
310         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
311         req_hdr->version = 0;
312 }
313
314 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
315                         struct be_dma_mem *mem)
316 {
317         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
318         u64 dma = (u64)mem->dma;
319
320         for (i = 0; i < buf_pages; i++) {
321                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
322                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
323                 dma += PAGE_SIZE_4K;
324         }
325 }
326
327 /* Converts interrupt delay in microseconds to multiplier value */
328 static u32 eq_delay_to_mult(u32 usec_delay)
329 {
330 #define MAX_INTR_RATE                   651042
331         const u32 round = 10;
332         u32 multiplier;
333
334         if (usec_delay == 0)
335                 multiplier = 0;
336         else {
337                 u32 interrupt_rate = 1000000 / usec_delay;
338                 /* Max delay, corresponding to the lowest interrupt rate */
339                 if (interrupt_rate == 0)
340                         multiplier = 1023;
341                 else {
342                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
343                         multiplier /= interrupt_rate;
344                         /* Round the multiplier to the closest value.*/
345                         multiplier = (multiplier + round/2) / round;
346                         multiplier = min(multiplier, (u32)1023);
347                 }
348         }
349         return multiplier;
350 }
351
352 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
353 {
354         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
355         struct be_mcc_wrb *wrb
356                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
357         memset(wrb, 0, sizeof(*wrb));
358         return wrb;
359 }
360
361 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
362 {
363         struct be_queue_info *mccq = &adapter->mcc_obj.q;
364         struct be_mcc_wrb *wrb;
365
366         if (atomic_read(&mccq->used) >= mccq->len) {
367                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
368                 return NULL;
369         }
370
371         wrb = queue_head_node(mccq);
372         queue_head_inc(mccq);
373         atomic_inc(&mccq->used);
374         memset(wrb, 0, sizeof(*wrb));
375         return wrb;
376 }
377
378 /* Tell fw we're about to start firing cmds by writing a
379  * special pattern across the wrb hdr; uses mbox
380  */
381 int be_cmd_fw_init(struct be_adapter *adapter)
382 {
383         u8 *wrb;
384         int status;
385
386         spin_lock(&adapter->mbox_lock);
387
388         wrb = (u8 *)wrb_from_mbox(adapter);
389         *wrb++ = 0xFF;
390         *wrb++ = 0x12;
391         *wrb++ = 0x34;
392         *wrb++ = 0xFF;
393         *wrb++ = 0xFF;
394         *wrb++ = 0x56;
395         *wrb++ = 0x78;
396         *wrb = 0xFF;
397
398         status = be_mbox_notify_wait(adapter);
399
400         spin_unlock(&adapter->mbox_lock);
401         return status;
402 }
403
404 /* Tell fw we're done with firing cmds by writing a
405  * special pattern across the wrb hdr; uses mbox
406  */
407 int be_cmd_fw_clean(struct be_adapter *adapter)
408 {
409         u8 *wrb;
410         int status;
411
412         if (adapter->eeh_err)
413                 return -EIO;
414
415         spin_lock(&adapter->mbox_lock);
416
417         wrb = (u8 *)wrb_from_mbox(adapter);
418         *wrb++ = 0xFF;
419         *wrb++ = 0xAA;
420         *wrb++ = 0xBB;
421         *wrb++ = 0xFF;
422         *wrb++ = 0xFF;
423         *wrb++ = 0xCC;
424         *wrb++ = 0xDD;
425         *wrb = 0xFF;
426
427         status = be_mbox_notify_wait(adapter);
428
429         spin_unlock(&adapter->mbox_lock);
430         return status;
431 }
432 int be_cmd_eq_create(struct be_adapter *adapter,
433                 struct be_queue_info *eq, int eq_delay)
434 {
435         struct be_mcc_wrb *wrb;
436         struct be_cmd_req_eq_create *req;
437         struct be_dma_mem *q_mem = &eq->dma_mem;
438         int status;
439
440         spin_lock(&adapter->mbox_lock);
441
442         wrb = wrb_from_mbox(adapter);
443         req = embedded_payload(wrb);
444
445         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
446
447         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
448                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
449
450         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
451
452         AMAP_SET_BITS(struct amap_eq_context, func, req->context,
453                         be_pci_func(adapter));
454         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
455         /* 4byte eqe*/
456         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
457         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
458                         __ilog2_u32(eq->len/256));
459         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
460                         eq_delay_to_mult(eq_delay));
461         be_dws_cpu_to_le(req->context, sizeof(req->context));
462
463         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
464
465         status = be_mbox_notify_wait(adapter);
466         if (!status) {
467                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
468                 eq->id = le16_to_cpu(resp->eq_id);
469                 eq->created = true;
470         }
471
472         spin_unlock(&adapter->mbox_lock);
473         return status;
474 }
475
476 /* Uses mbox */
477 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
478                         u8 type, bool permanent, u32 if_handle)
479 {
480         struct be_mcc_wrb *wrb;
481         struct be_cmd_req_mac_query *req;
482         int status;
483
484         spin_lock(&adapter->mbox_lock);
485
486         wrb = wrb_from_mbox(adapter);
487         req = embedded_payload(wrb);
488
489         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
490                         OPCODE_COMMON_NTWK_MAC_QUERY);
491
492         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
493                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
494
495         req->type = type;
496         if (permanent) {
497                 req->permanent = 1;
498         } else {
499                 req->if_id = cpu_to_le16((u16) if_handle);
500                 req->permanent = 0;
501         }
502
503         status = be_mbox_notify_wait(adapter);
504         if (!status) {
505                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
506                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
507         }
508
509         spin_unlock(&adapter->mbox_lock);
510         return status;
511 }
512
513 /* Uses synchronous MCCQ */
514 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
515                 u32 if_id, u32 *pmac_id)
516 {
517         struct be_mcc_wrb *wrb;
518         struct be_cmd_req_pmac_add *req;
519         int status;
520
521         spin_lock_bh(&adapter->mcc_lock);
522
523         wrb = wrb_from_mccq(adapter);
524         if (!wrb) {
525                 status = -EBUSY;
526                 goto err;
527         }
528         req = embedded_payload(wrb);
529
530         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
531                         OPCODE_COMMON_NTWK_PMAC_ADD);
532
533         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
534                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
535
536         req->if_id = cpu_to_le32(if_id);
537         memcpy(req->mac_address, mac_addr, ETH_ALEN);
538
539         status = be_mcc_notify_wait(adapter);
540         if (!status) {
541                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
542                 *pmac_id = le32_to_cpu(resp->pmac_id);
543         }
544
545 err:
546         spin_unlock_bh(&adapter->mcc_lock);
547         return status;
548 }
549
550 /* Uses synchronous MCCQ */
551 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
552 {
553         struct be_mcc_wrb *wrb;
554         struct be_cmd_req_pmac_del *req;
555         int status;
556
557         spin_lock_bh(&adapter->mcc_lock);
558
559         wrb = wrb_from_mccq(adapter);
560         if (!wrb) {
561                 status = -EBUSY;
562                 goto err;
563         }
564         req = embedded_payload(wrb);
565
566         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
567                         OPCODE_COMMON_NTWK_PMAC_DEL);
568
569         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
570                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
571
572         req->if_id = cpu_to_le32(if_id);
573         req->pmac_id = cpu_to_le32(pmac_id);
574
575         status = be_mcc_notify_wait(adapter);
576
577 err:
578         spin_unlock_bh(&adapter->mcc_lock);
579         return status;
580 }
581
582 /* Uses Mbox */
583 int be_cmd_cq_create(struct be_adapter *adapter,
584                 struct be_queue_info *cq, struct be_queue_info *eq,
585                 bool sol_evts, bool no_delay, int coalesce_wm)
586 {
587         struct be_mcc_wrb *wrb;
588         struct be_cmd_req_cq_create *req;
589         struct be_dma_mem *q_mem = &cq->dma_mem;
590         void *ctxt;
591         int status;
592
593         spin_lock(&adapter->mbox_lock);
594
595         wrb = wrb_from_mbox(adapter);
596         req = embedded_payload(wrb);
597         ctxt = &req->context;
598
599         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
600                         OPCODE_COMMON_CQ_CREATE);
601
602         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
603                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
604
605         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
606
607         AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
608         AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
609         AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
610                         __ilog2_u32(cq->len/256));
611         AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
612         AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
613         AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
614         AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
615         AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
616         AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter));
617         be_dws_cpu_to_le(ctxt, sizeof(req->context));
618
619         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
620
621         status = be_mbox_notify_wait(adapter);
622         if (!status) {
623                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
624                 cq->id = le16_to_cpu(resp->cq_id);
625                 cq->created = true;
626         }
627
628         spin_unlock(&adapter->mbox_lock);
629
630         return status;
631 }
632
633 static u32 be_encoded_q_len(int q_len)
634 {
635         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
636         if (len_encoded == 16)
637                 len_encoded = 0;
638         return len_encoded;
639 }
640
641 int be_cmd_mccq_create(struct be_adapter *adapter,
642                         struct be_queue_info *mccq,
643                         struct be_queue_info *cq)
644 {
645         struct be_mcc_wrb *wrb;
646         struct be_cmd_req_mcc_create *req;
647         struct be_dma_mem *q_mem = &mccq->dma_mem;
648         void *ctxt;
649         int status;
650
651         spin_lock(&adapter->mbox_lock);
652
653         wrb = wrb_from_mbox(adapter);
654         req = embedded_payload(wrb);
655         ctxt = &req->context;
656
657         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
658                         OPCODE_COMMON_MCC_CREATE);
659
660         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
661                         OPCODE_COMMON_MCC_CREATE, sizeof(*req));
662
663         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
664
665         AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter));
666         AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
667         AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
668                 be_encoded_q_len(mccq->len));
669         AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
670
671         be_dws_cpu_to_le(ctxt, sizeof(req->context));
672
673         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
674
675         status = be_mbox_notify_wait(adapter);
676         if (!status) {
677                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
678                 mccq->id = le16_to_cpu(resp->id);
679                 mccq->created = true;
680         }
681         spin_unlock(&adapter->mbox_lock);
682
683         return status;
684 }
685
686 int be_cmd_txq_create(struct be_adapter *adapter,
687                         struct be_queue_info *txq,
688                         struct be_queue_info *cq)
689 {
690         struct be_mcc_wrb *wrb;
691         struct be_cmd_req_eth_tx_create *req;
692         struct be_dma_mem *q_mem = &txq->dma_mem;
693         void *ctxt;
694         int status;
695
696         spin_lock(&adapter->mbox_lock);
697
698         wrb = wrb_from_mbox(adapter);
699         req = embedded_payload(wrb);
700         ctxt = &req->context;
701
702         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
703                         OPCODE_ETH_TX_CREATE);
704
705         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
706                 sizeof(*req));
707
708         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
709         req->ulp_num = BE_ULP1_NUM;
710         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
711
712         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
713                 be_encoded_q_len(txq->len));
714         AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
715                         be_pci_func(adapter));
716         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
717         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
718
719         be_dws_cpu_to_le(ctxt, sizeof(req->context));
720
721         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
722
723         status = be_mbox_notify_wait(adapter);
724         if (!status) {
725                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
726                 txq->id = le16_to_cpu(resp->cid);
727                 txq->created = true;
728         }
729
730         spin_unlock(&adapter->mbox_lock);
731
732         return status;
733 }
734
735 /* Uses mbox */
736 int be_cmd_rxq_create(struct be_adapter *adapter,
737                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
738                 u16 max_frame_size, u32 if_id, u32 rss)
739 {
740         struct be_mcc_wrb *wrb;
741         struct be_cmd_req_eth_rx_create *req;
742         struct be_dma_mem *q_mem = &rxq->dma_mem;
743         int status;
744
745         spin_lock(&adapter->mbox_lock);
746
747         wrb = wrb_from_mbox(adapter);
748         req = embedded_payload(wrb);
749
750         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
751                         OPCODE_ETH_RX_CREATE);
752
753         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
754                 sizeof(*req));
755
756         req->cq_id = cpu_to_le16(cq_id);
757         req->frag_size = fls(frag_size) - 1;
758         req->num_pages = 2;
759         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
760         req->interface_id = cpu_to_le32(if_id);
761         req->max_frame_size = cpu_to_le16(max_frame_size);
762         req->rss_queue = cpu_to_le32(rss);
763
764         status = be_mbox_notify_wait(adapter);
765         if (!status) {
766                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
767                 rxq->id = le16_to_cpu(resp->id);
768                 rxq->created = true;
769         }
770
771         spin_unlock(&adapter->mbox_lock);
772
773         return status;
774 }
775
776 /* Generic destroyer function for all types of queues
777  * Uses Mbox
778  */
779 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
780                 int queue_type)
781 {
782         struct be_mcc_wrb *wrb;
783         struct be_cmd_req_q_destroy *req;
784         u8 subsys = 0, opcode = 0;
785         int status;
786
787         if (adapter->eeh_err)
788                 return -EIO;
789
790         spin_lock(&adapter->mbox_lock);
791
792         wrb = wrb_from_mbox(adapter);
793         req = embedded_payload(wrb);
794
795         switch (queue_type) {
796         case QTYPE_EQ:
797                 subsys = CMD_SUBSYSTEM_COMMON;
798                 opcode = OPCODE_COMMON_EQ_DESTROY;
799                 break;
800         case QTYPE_CQ:
801                 subsys = CMD_SUBSYSTEM_COMMON;
802                 opcode = OPCODE_COMMON_CQ_DESTROY;
803                 break;
804         case QTYPE_TXQ:
805                 subsys = CMD_SUBSYSTEM_ETH;
806                 opcode = OPCODE_ETH_TX_DESTROY;
807                 break;
808         case QTYPE_RXQ:
809                 subsys = CMD_SUBSYSTEM_ETH;
810                 opcode = OPCODE_ETH_RX_DESTROY;
811                 break;
812         case QTYPE_MCCQ:
813                 subsys = CMD_SUBSYSTEM_COMMON;
814                 opcode = OPCODE_COMMON_MCC_DESTROY;
815                 break;
816         default:
817                 BUG();
818         }
819
820         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
821
822         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
823         req->id = cpu_to_le16(q->id);
824
825         status = be_mbox_notify_wait(adapter);
826
827         spin_unlock(&adapter->mbox_lock);
828
829         return status;
830 }
831
832 /* Create an rx filtering policy configuration on an i/f
833  * Uses mbox
834  */
835 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
836                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
837 {
838         struct be_mcc_wrb *wrb;
839         struct be_cmd_req_if_create *req;
840         int status;
841
842         spin_lock(&adapter->mbox_lock);
843
844         wrb = wrb_from_mbox(adapter);
845         req = embedded_payload(wrb);
846
847         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
848                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
849
850         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
851                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
852
853         req->capability_flags = cpu_to_le32(cap_flags);
854         req->enable_flags = cpu_to_le32(en_flags);
855         req->pmac_invalid = pmac_invalid;
856         if (!pmac_invalid)
857                 memcpy(req->mac_addr, mac, ETH_ALEN);
858
859         status = be_mbox_notify_wait(adapter);
860         if (!status) {
861                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
862                 *if_handle = le32_to_cpu(resp->interface_id);
863                 if (!pmac_invalid)
864                         *pmac_id = le32_to_cpu(resp->pmac_id);
865         }
866
867         spin_unlock(&adapter->mbox_lock);
868         return status;
869 }
870
871 /* Uses mbox */
872 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
873 {
874         struct be_mcc_wrb *wrb;
875         struct be_cmd_req_if_destroy *req;
876         int status;
877
878         if (adapter->eeh_err)
879                 return -EIO;
880
881         spin_lock(&adapter->mbox_lock);
882
883         wrb = wrb_from_mbox(adapter);
884         req = embedded_payload(wrb);
885
886         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
887                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
888
889         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
890                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
891
892         req->interface_id = cpu_to_le32(interface_id);
893
894         status = be_mbox_notify_wait(adapter);
895
896         spin_unlock(&adapter->mbox_lock);
897
898         return status;
899 }
900
901 /* Get stats is a non embedded command: the request is not embedded inside
902  * WRB but is a separate dma memory block
903  * Uses asynchronous MCC
904  */
905 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
906 {
907         struct be_mcc_wrb *wrb;
908         struct be_cmd_req_get_stats *req;
909         struct be_sge *sge;
910         int status = 0;
911
912         spin_lock_bh(&adapter->mcc_lock);
913
914         wrb = wrb_from_mccq(adapter);
915         if (!wrb) {
916                 status = -EBUSY;
917                 goto err;
918         }
919         req = nonemb_cmd->va;
920         sge = nonembedded_sgl(wrb);
921
922         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
923                         OPCODE_ETH_GET_STATISTICS);
924
925         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
926                 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
927         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
928         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
929         sge->len = cpu_to_le32(nonemb_cmd->size);
930
931         be_mcc_notify(adapter);
932
933 err:
934         spin_unlock_bh(&adapter->mcc_lock);
935         return status;
936 }
937
938 /* Uses synchronous mcc */
939 int be_cmd_link_status_query(struct be_adapter *adapter,
940                         bool *link_up, u8 *mac_speed, u16 *link_speed)
941 {
942         struct be_mcc_wrb *wrb;
943         struct be_cmd_req_link_status *req;
944         int status;
945
946         spin_lock_bh(&adapter->mcc_lock);
947
948         wrb = wrb_from_mccq(adapter);
949         if (!wrb) {
950                 status = -EBUSY;
951                 goto err;
952         }
953         req = embedded_payload(wrb);
954
955         *link_up = false;
956
957         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
958                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
959
960         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
961                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
962
963         status = be_mcc_notify_wait(adapter);
964         if (!status) {
965                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
966                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
967                         *link_up = true;
968                         *link_speed = le16_to_cpu(resp->link_speed);
969                         *mac_speed = resp->mac_speed;
970                 }
971         }
972
973 err:
974         spin_unlock_bh(&adapter->mcc_lock);
975         return status;
976 }
977
978 /* Uses Mbox */
979 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
980 {
981         struct be_mcc_wrb *wrb;
982         struct be_cmd_req_get_fw_version *req;
983         int status;
984
985         spin_lock(&adapter->mbox_lock);
986
987         wrb = wrb_from_mbox(adapter);
988         req = embedded_payload(wrb);
989
990         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
991                         OPCODE_COMMON_GET_FW_VERSION);
992
993         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
994                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
995
996         status = be_mbox_notify_wait(adapter);
997         if (!status) {
998                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
999                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1000         }
1001
1002         spin_unlock(&adapter->mbox_lock);
1003         return status;
1004 }
1005
1006 /* set the EQ delay interval of an EQ to specified value
1007  * Uses async mcc
1008  */
1009 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1010 {
1011         struct be_mcc_wrb *wrb;
1012         struct be_cmd_req_modify_eq_delay *req;
1013         int status = 0;
1014
1015         spin_lock_bh(&adapter->mcc_lock);
1016
1017         wrb = wrb_from_mccq(adapter);
1018         if (!wrb) {
1019                 status = -EBUSY;
1020                 goto err;
1021         }
1022         req = embedded_payload(wrb);
1023
1024         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1025                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1026
1027         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1028                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1029
1030         req->num_eq = cpu_to_le32(1);
1031         req->delay[0].eq_id = cpu_to_le32(eq_id);
1032         req->delay[0].phase = 0;
1033         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1034
1035         be_mcc_notify(adapter);
1036
1037 err:
1038         spin_unlock_bh(&adapter->mcc_lock);
1039         return status;
1040 }
1041
1042 /* Uses sycnhronous mcc */
1043 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1044                         u32 num, bool untagged, bool promiscuous)
1045 {
1046         struct be_mcc_wrb *wrb;
1047         struct be_cmd_req_vlan_config *req;
1048         int status;
1049
1050         spin_lock_bh(&adapter->mcc_lock);
1051
1052         wrb = wrb_from_mccq(adapter);
1053         if (!wrb) {
1054                 status = -EBUSY;
1055                 goto err;
1056         }
1057         req = embedded_payload(wrb);
1058
1059         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1060                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1061
1062         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1063                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1064
1065         req->interface_id = if_id;
1066         req->promiscuous = promiscuous;
1067         req->untagged = untagged;
1068         req->num_vlan = num;
1069         if (!promiscuous) {
1070                 memcpy(req->normal_vlan, vtag_array,
1071                         req->num_vlan * sizeof(vtag_array[0]));
1072         }
1073
1074         status = be_mcc_notify_wait(adapter);
1075
1076 err:
1077         spin_unlock_bh(&adapter->mcc_lock);
1078         return status;
1079 }
1080
1081 /* Uses MCC for this command as it may be called in BH context
1082  * Uses synchronous mcc
1083  */
1084 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1085 {
1086         struct be_mcc_wrb *wrb;
1087         struct be_cmd_req_promiscuous_config *req;
1088         int status;
1089
1090         spin_lock_bh(&adapter->mcc_lock);
1091
1092         wrb = wrb_from_mccq(adapter);
1093         if (!wrb) {
1094                 status = -EBUSY;
1095                 goto err;
1096         }
1097         req = embedded_payload(wrb);
1098
1099         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1100
1101         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1102                 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1103
1104         if (port_num)
1105                 req->port1_promiscuous = en;
1106         else
1107                 req->port0_promiscuous = en;
1108
1109         status = be_mcc_notify_wait(adapter);
1110
1111 err:
1112         spin_unlock_bh(&adapter->mcc_lock);
1113         return status;
1114 }
1115
1116 /*
1117  * Uses MCC for this command as it may be called in BH context
1118  * (mc == NULL) => multicast promiscous
1119  */
1120 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1121                 struct dev_mc_list *mc_list, u32 mc_count,
1122                 struct be_dma_mem *mem)
1123 {
1124         struct be_mcc_wrb *wrb;
1125         struct be_cmd_req_mcast_mac_config *req = mem->va;
1126         struct be_sge *sge;
1127         int status;
1128
1129         spin_lock_bh(&adapter->mcc_lock);
1130
1131         wrb = wrb_from_mccq(adapter);
1132         if (!wrb) {
1133                 status = -EBUSY;
1134                 goto err;
1135         }
1136         sge = nonembedded_sgl(wrb);
1137         memset(req, 0, sizeof(*req));
1138
1139         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1140                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1141         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1142         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1143         sge->len = cpu_to_le32(mem->size);
1144
1145         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1146                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1147
1148         req->interface_id = if_id;
1149         if (mc_list) {
1150                 int i;
1151                 struct dev_mc_list *mc;
1152
1153                 req->num_mac = cpu_to_le16(mc_count);
1154
1155                 for (mc = mc_list, i = 0; mc; mc = mc->next, i++)
1156                         memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
1157         } else {
1158                 req->promiscuous = 1;
1159         }
1160
1161         status = be_mcc_notify_wait(adapter);
1162
1163 err:
1164         spin_unlock_bh(&adapter->mcc_lock);
1165         return status;
1166 }
1167
1168 /* Uses synchrounous mcc */
1169 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1170 {
1171         struct be_mcc_wrb *wrb;
1172         struct be_cmd_req_set_flow_control *req;
1173         int status;
1174
1175         spin_lock_bh(&adapter->mcc_lock);
1176
1177         wrb = wrb_from_mccq(adapter);
1178         if (!wrb) {
1179                 status = -EBUSY;
1180                 goto err;
1181         }
1182         req = embedded_payload(wrb);
1183
1184         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1185                         OPCODE_COMMON_SET_FLOW_CONTROL);
1186
1187         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1188                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1189
1190         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1191         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1192
1193         status = be_mcc_notify_wait(adapter);
1194
1195 err:
1196         spin_unlock_bh(&adapter->mcc_lock);
1197         return status;
1198 }
1199
1200 /* Uses sycn mcc */
1201 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1202 {
1203         struct be_mcc_wrb *wrb;
1204         struct be_cmd_req_get_flow_control *req;
1205         int status;
1206
1207         spin_lock_bh(&adapter->mcc_lock);
1208
1209         wrb = wrb_from_mccq(adapter);
1210         if (!wrb) {
1211                 status = -EBUSY;
1212                 goto err;
1213         }
1214         req = embedded_payload(wrb);
1215
1216         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1217                         OPCODE_COMMON_GET_FLOW_CONTROL);
1218
1219         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1220                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1221
1222         status = be_mcc_notify_wait(adapter);
1223         if (!status) {
1224                 struct be_cmd_resp_get_flow_control *resp =
1225                                                 embedded_payload(wrb);
1226                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1227                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1228         }
1229
1230 err:
1231         spin_unlock_bh(&adapter->mcc_lock);
1232         return status;
1233 }
1234
1235 /* Uses mbox */
1236 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
1237 {
1238         struct be_mcc_wrb *wrb;
1239         struct be_cmd_req_query_fw_cfg *req;
1240         int status;
1241
1242         spin_lock(&adapter->mbox_lock);
1243
1244         wrb = wrb_from_mbox(adapter);
1245         req = embedded_payload(wrb);
1246
1247         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1248                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1249
1250         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1251                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1252
1253         status = be_mbox_notify_wait(adapter);
1254         if (!status) {
1255                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1256                 *port_num = le32_to_cpu(resp->phys_port);
1257                 *cap = le32_to_cpu(resp->function_cap);
1258         }
1259
1260         spin_unlock(&adapter->mbox_lock);
1261         return status;
1262 }
1263
1264 /* Uses mbox */
1265 int be_cmd_reset_function(struct be_adapter *adapter)
1266 {
1267         struct be_mcc_wrb *wrb;
1268         struct be_cmd_req_hdr *req;
1269         int status;
1270
1271         spin_lock(&adapter->mbox_lock);
1272
1273         wrb = wrb_from_mbox(adapter);
1274         req = embedded_payload(wrb);
1275
1276         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1277                         OPCODE_COMMON_FUNCTION_RESET);
1278
1279         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1280                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1281
1282         status = be_mbox_notify_wait(adapter);
1283
1284         spin_unlock(&adapter->mbox_lock);
1285         return status;
1286 }
1287
1288 /* Uses sync mcc */
1289 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1290                         u8 bcn, u8 sts, u8 state)
1291 {
1292         struct be_mcc_wrb *wrb;
1293         struct be_cmd_req_enable_disable_beacon *req;
1294         int status;
1295
1296         spin_lock_bh(&adapter->mcc_lock);
1297
1298         wrb = wrb_from_mccq(adapter);
1299         if (!wrb) {
1300                 status = -EBUSY;
1301                 goto err;
1302         }
1303         req = embedded_payload(wrb);
1304
1305         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1306                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1307
1308         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1309                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1310
1311         req->port_num = port_num;
1312         req->beacon_state = state;
1313         req->beacon_duration = bcn;
1314         req->status_duration = sts;
1315
1316         status = be_mcc_notify_wait(adapter);
1317
1318 err:
1319         spin_unlock_bh(&adapter->mcc_lock);
1320         return status;
1321 }
1322
1323 /* Uses sync mcc */
1324 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1325 {
1326         struct be_mcc_wrb *wrb;
1327         struct be_cmd_req_get_beacon_state *req;
1328         int status;
1329
1330         spin_lock_bh(&adapter->mcc_lock);
1331
1332         wrb = wrb_from_mccq(adapter);
1333         if (!wrb) {
1334                 status = -EBUSY;
1335                 goto err;
1336         }
1337         req = embedded_payload(wrb);
1338
1339         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1340                         OPCODE_COMMON_GET_BEACON_STATE);
1341
1342         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1343                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1344
1345         req->port_num = port_num;
1346
1347         status = be_mcc_notify_wait(adapter);
1348         if (!status) {
1349                 struct be_cmd_resp_get_beacon_state *resp =
1350                                                 embedded_payload(wrb);
1351                 *state = resp->beacon_state;
1352         }
1353
1354 err:
1355         spin_unlock_bh(&adapter->mcc_lock);
1356         return status;
1357 }
1358
1359 /* Uses sync mcc */
1360 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1361                                 u8 *connector)
1362 {
1363         struct be_mcc_wrb *wrb;
1364         struct be_cmd_req_port_type *req;
1365         int status;
1366
1367         spin_lock_bh(&adapter->mcc_lock);
1368
1369         wrb = wrb_from_mccq(adapter);
1370         if (!wrb) {
1371                 status = -EBUSY;
1372                 goto err;
1373         }
1374         req = embedded_payload(wrb);
1375
1376         be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1377                         OPCODE_COMMON_READ_TRANSRECV_DATA);
1378
1379         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1380                 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1381
1382         req->port = cpu_to_le32(port);
1383         req->page_num = cpu_to_le32(TR_PAGE_A0);
1384         status = be_mcc_notify_wait(adapter);
1385         if (!status) {
1386                 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1387                         *connector = resp->data.connector;
1388         }
1389
1390 err:
1391         spin_unlock_bh(&adapter->mcc_lock);
1392         return status;
1393 }
1394
1395 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1396                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1397 {
1398         struct be_mcc_wrb *wrb;
1399         struct be_cmd_write_flashrom *req;
1400         struct be_sge *sge;
1401         int status;
1402
1403         spin_lock_bh(&adapter->mcc_lock);
1404
1405         wrb = wrb_from_mccq(adapter);
1406         if (!wrb) {
1407                 status = -EBUSY;
1408                 goto err;
1409         }
1410         req = cmd->va;
1411         sge = nonembedded_sgl(wrb);
1412
1413         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1414                         OPCODE_COMMON_WRITE_FLASHROM);
1415
1416         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1417                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1418         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1419         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1420         sge->len = cpu_to_le32(cmd->size);
1421
1422         req->params.op_type = cpu_to_le32(flash_type);
1423         req->params.op_code = cpu_to_le32(flash_opcode);
1424         req->params.data_buf_size = cpu_to_le32(buf_size);
1425
1426         status = be_mcc_notify_wait(adapter);
1427
1428 err:
1429         spin_unlock_bh(&adapter->mcc_lock);
1430         return status;
1431 }
1432
1433 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1434                          int offset)
1435 {
1436         struct be_mcc_wrb *wrb;
1437         struct be_cmd_write_flashrom *req;
1438         int status;
1439
1440         spin_lock_bh(&adapter->mcc_lock);
1441
1442         wrb = wrb_from_mccq(adapter);
1443         if (!wrb) {
1444                 status = -EBUSY;
1445                 goto err;
1446         }
1447         req = embedded_payload(wrb);
1448
1449         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1450                         OPCODE_COMMON_READ_FLASHROM);
1451
1452         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1453                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1454
1455         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1456         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1457         req->params.offset = offset;
1458         req->params.data_buf_size = 0x4;
1459
1460         status = be_mcc_notify_wait(adapter);
1461         if (!status)
1462                 memcpy(flashed_crc, req->params.data_buf, 4);
1463
1464 err:
1465         spin_unlock_bh(&adapter->mcc_lock);
1466         return status;
1467 }
1468
1469 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1470                                 struct be_dma_mem *nonemb_cmd)
1471 {
1472         struct be_mcc_wrb *wrb;
1473         struct be_cmd_req_acpi_wol_magic_config *req;
1474         struct be_sge *sge;
1475         int status;
1476
1477         spin_lock_bh(&adapter->mcc_lock);
1478
1479         wrb = wrb_from_mccq(adapter);
1480         if (!wrb) {
1481                 status = -EBUSY;
1482                 goto err;
1483         }
1484         req = nonemb_cmd->va;
1485         sge = nonembedded_sgl(wrb);
1486
1487         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1488                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1489
1490         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1491                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1492         memcpy(req->magic_mac, mac, ETH_ALEN);
1493
1494         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1495         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1496         sge->len = cpu_to_le32(nonemb_cmd->size);
1497
1498         status = be_mcc_notify_wait(adapter);
1499
1500 err:
1501         spin_unlock_bh(&adapter->mcc_lock);
1502         return status;
1503 }
1504
1505 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1506                         u8 loopback_type, u8 enable)
1507 {
1508         struct be_mcc_wrb *wrb;
1509         struct be_cmd_req_set_lmode *req;
1510         int status;
1511
1512         spin_lock_bh(&adapter->mcc_lock);
1513
1514         wrb = wrb_from_mccq(adapter);
1515         if (!wrb) {
1516                 status = -EBUSY;
1517                 goto err;
1518         }
1519
1520         req = embedded_payload(wrb);
1521
1522         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1523                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1524
1525         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1526                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1527                         sizeof(*req));
1528
1529         req->src_port = port_num;
1530         req->dest_port = port_num;
1531         req->loopback_type = loopback_type;
1532         req->loopback_state = enable;
1533
1534         status = be_mcc_notify_wait(adapter);
1535 err:
1536         spin_unlock_bh(&adapter->mcc_lock);
1537         return status;
1538 }
1539
1540 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1541                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1542 {
1543         struct be_mcc_wrb *wrb;
1544         struct be_cmd_req_loopback_test *req;
1545         int status;
1546
1547         spin_lock_bh(&adapter->mcc_lock);
1548
1549         wrb = wrb_from_mccq(adapter);
1550         if (!wrb) {
1551                 status = -EBUSY;
1552                 goto err;
1553         }
1554
1555         req = embedded_payload(wrb);
1556
1557         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1558                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1559
1560         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1561                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1562         req->hdr.timeout = 4;
1563
1564         req->pattern = cpu_to_le64(pattern);
1565         req->src_port = cpu_to_le32(port_num);
1566         req->dest_port = cpu_to_le32(port_num);
1567         req->pkt_size = cpu_to_le32(pkt_size);
1568         req->num_pkts = cpu_to_le32(num_pkts);
1569         req->loopback_type = cpu_to_le32(loopback_type);
1570
1571         status = be_mcc_notify_wait(adapter);
1572         if (!status) {
1573                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1574                 status = le32_to_cpu(resp->status);
1575         }
1576
1577 err:
1578         spin_unlock_bh(&adapter->mcc_lock);
1579         return status;
1580 }
1581
1582 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1583                                 u32 byte_cnt, struct be_dma_mem *cmd)
1584 {
1585         struct be_mcc_wrb *wrb;
1586         struct be_cmd_req_ddrdma_test *req;
1587         struct be_sge *sge;
1588         int status;
1589         int i, j = 0;
1590
1591         spin_lock_bh(&adapter->mcc_lock);
1592
1593         wrb = wrb_from_mccq(adapter);
1594         if (!wrb) {
1595                 status = -EBUSY;
1596                 goto err;
1597         }
1598         req = cmd->va;
1599         sge = nonembedded_sgl(wrb);
1600         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1601                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1602         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1603                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1604
1605         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1606         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1607         sge->len = cpu_to_le32(cmd->size);
1608
1609         req->pattern = cpu_to_le64(pattern);
1610         req->byte_count = cpu_to_le32(byte_cnt);
1611         for (i = 0; i < byte_cnt; i++) {
1612                 req->snd_buff[i] = (u8)(pattern >> (j*8));
1613                 j++;
1614                 if (j > 7)
1615                         j = 0;
1616         }
1617
1618         status = be_mcc_notify_wait(adapter);
1619
1620         if (!status) {
1621                 struct be_cmd_resp_ddrdma_test *resp;
1622                 resp = cmd->va;
1623                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1624                                 resp->snd_err) {
1625                         status = -1;
1626                 }
1627         }
1628
1629 err:
1630         spin_unlock_bh(&adapter->mcc_lock);
1631         return status;
1632 }
1633
1634 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1635                                 struct be_dma_mem *nonemb_cmd)
1636 {
1637         struct be_mcc_wrb *wrb;
1638         struct be_cmd_req_seeprom_read *req;
1639         struct be_sge *sge;
1640         int status;
1641
1642         spin_lock_bh(&adapter->mcc_lock);
1643
1644         wrb = wrb_from_mccq(adapter);
1645         req = nonemb_cmd->va;
1646         sge = nonembedded_sgl(wrb);
1647
1648         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1649                         OPCODE_COMMON_SEEPROM_READ);
1650
1651         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1652                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1653
1654         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1655         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1656         sge->len = cpu_to_le32(nonemb_cmd->size);
1657
1658         status = be_mcc_notify_wait(adapter);
1659
1660         spin_unlock_bh(&adapter->mcc_lock);
1661         return status;
1662 }