Create platform_device.h to contain all the platform device details.
[linux-2.6.git] / drivers / net / amd8111e.c
1
2 /* Advanced  Micro Devices Inc. AMD8111E Linux Network Driver 
3  * Copyright (C) 2004 Advanced Micro Devices 
4  *
5  * 
6  * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8  * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9  * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10  * Copyright 1993 United States Government as represented by the
11  *      Director, National Security Agency.[ pcnet32.c ]
12  * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
14  *
15  * 
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License as published by
18  * the Free Software Foundation; either version 2 of the License, or
19  * (at your option) any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; if not, write to the Free Software
28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
29  * USA
30   
31 Module Name:
32
33         amd8111e.c
34
35 Abstract:
36         
37          AMD8111 based 10/100 Ethernet Controller Driver. 
38
39 Environment:
40
41         Kernel Mode
42
43 Revision History:
44         3.0.0
45            Initial Revision.
46         3.0.1
47          1. Dynamic interrupt coalescing.
48          2. Removed prev_stats.
49          3. MII support.
50          4. Dynamic IPG support
51         3.0.2  05/29/2003
52          1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
53          2. Bug fix: Fixed VLAN support failure.
54          3. Bug fix: Fixed receive interrupt coalescing bug.
55          4. Dynamic IPG support is disabled by default.
56         3.0.3 06/05/2003
57          1. Bug fix: Fixed failure to close the interface if SMP is enabled.
58         3.0.4 12/09/2003
59          1. Added set_mac_address routine for bonding driver support.
60          2. Tested the driver for bonding support
61          3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth 
62             indicated to the h/w.
63          4. Modified amd8111e_rx() routine to receive all the received packets 
64             in the first interrupt.
65          5. Bug fix: Corrected  rx_errors  reported in get_stats() function.
66         3.0.5 03/22/2004
67          1. Added NAPI support  
68
69 */
70
71
72 #include <linux/config.h>
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/types.h>
76 #include <linux/compiler.h>
77 #include <linux/slab.h>
78 #include <linux/delay.h>
79 #include <linux/init.h>
80 #include <linux/ioport.h>
81 #include <linux/pci.h>
82 #include <linux/netdevice.h>
83 #include <linux/etherdevice.h>
84 #include <linux/skbuff.h>
85 #include <linux/ethtool.h>
86 #include <linux/mii.h>
87 #include <linux/if_vlan.h>
88 #include <linux/ctype.h>        
89 #include <linux/crc32.h>
90 #include <linux/dma-mapping.h>
91
92 #include <asm/system.h>
93 #include <asm/io.h>
94 #include <asm/byteorder.h>
95 #include <asm/uaccess.h>
96
97 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
98 #define AMD8111E_VLAN_TAG_USED 1
99 #else
100 #define AMD8111E_VLAN_TAG_USED 0
101 #endif
102
103 #include "amd8111e.h"
104 #define MODULE_NAME     "amd8111e"
105 #define MODULE_VERS     "3.0.5"
106 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
107 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.3");
108 MODULE_LICENSE("GPL");
109 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
110 module_param_array(speed_duplex, int, NULL, 0);
111 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
112 module_param_array(coalesce, bool, NULL, 0);
113 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
114 module_param_array(dynamic_ipg, bool, NULL, 0);
115 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
116
117 static struct pci_device_id amd8111e_pci_tbl[] = {
118                 
119         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
120          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
121         { 0, }
122
123 };
124 /* 
125 This function will read the PHY registers.
126 */
127 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
128 {
129         void __iomem *mmio = lp->mmio;
130         unsigned int reg_val;
131         unsigned int repeat= REPEAT_CNT;
132
133         reg_val = readl(mmio + PHY_ACCESS);
134         while (reg_val & PHY_CMD_ACTIVE)
135                 reg_val = readl( mmio + PHY_ACCESS );
136
137         writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
138                            ((reg & 0x1f) << 16),  mmio +PHY_ACCESS);
139         do{
140                 reg_val = readl(mmio + PHY_ACCESS);
141                 udelay(30);  /* It takes 30 us to read/write data */
142         } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
143         if(reg_val & PHY_RD_ERR)
144                 goto err_phy_read;
145         
146         *val = reg_val & 0xffff;
147         return 0;
148 err_phy_read:   
149         *val = 0;
150         return -EINVAL;
151         
152 }
153
154 /* 
155 This function will write into PHY registers. 
156 */
157 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
158 {
159         unsigned int repeat = REPEAT_CNT
160         void __iomem *mmio = lp->mmio;
161         unsigned int reg_val;
162
163         reg_val = readl(mmio + PHY_ACCESS);
164         while (reg_val & PHY_CMD_ACTIVE)
165                 reg_val = readl( mmio + PHY_ACCESS );
166
167         writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
168                            ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
169
170         do{
171                 reg_val = readl(mmio + PHY_ACCESS);
172                 udelay(30);  /* It takes 30 us to read/write the data */
173         } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
174         
175         if(reg_val & PHY_RD_ERR)
176                 goto err_phy_write;
177         
178         return 0;
179
180 err_phy_write:  
181         return -EINVAL;
182         
183 }
184 /* 
185 This is the mii register read function provided to the mii interface.
186 */ 
187 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
188 {
189         struct amd8111e_priv* lp = netdev_priv(dev);
190         unsigned int reg_val;
191
192         amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
193         return reg_val;
194         
195 }
196
197 /* 
198 This is the mii register write function provided to the mii interface.
199 */ 
200 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
201 {
202         struct amd8111e_priv* lp = netdev_priv(dev);
203
204         amd8111e_write_phy(lp, phy_id, reg_num, val);
205 }
206
207 /*
208 This function will set PHY speed. During initialization sets the original speed to 100 full.
209 */
210 static void amd8111e_set_ext_phy(struct net_device *dev)
211 {
212         struct amd8111e_priv *lp = netdev_priv(dev);
213         u32 bmcr,advert,tmp;
214         
215         /* Determine mii register values to set the speed */
216         advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
217         tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
218         switch (lp->ext_phy_option){
219
220                 default:
221                 case SPEED_AUTONEG: /* advertise all values */
222                         tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
223                                 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
224                         break;
225                 case SPEED10_HALF:
226                         tmp |= ADVERTISE_10HALF;
227                         break;
228                 case SPEED10_FULL:
229                         tmp |= ADVERTISE_10FULL;
230                         break;
231                 case SPEED100_HALF: 
232                         tmp |= ADVERTISE_100HALF;
233                         break;
234                 case SPEED100_FULL:
235                         tmp |= ADVERTISE_100FULL;
236                         break;
237         }
238
239         if(advert != tmp)
240                 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
241         /* Restart auto negotiation */
242         bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
243         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
244         amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
245
246 }
247
248 /* 
249 This function will unmap skb->data space and will free 
250 all transmit and receive skbuffs.
251 */
252 static int amd8111e_free_skbs(struct net_device *dev)
253 {
254         struct amd8111e_priv *lp = netdev_priv(dev);
255         struct sk_buff* rx_skbuff;
256         int i;
257
258         /* Freeing transmit skbs */
259         for(i = 0; i < NUM_TX_BUFFERS; i++){
260                 if(lp->tx_skbuff[i]){
261                         pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i],                                        lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
262                         dev_kfree_skb (lp->tx_skbuff[i]);
263                         lp->tx_skbuff[i] = NULL;
264                         lp->tx_dma_addr[i] = 0;
265                 }
266         }
267         /* Freeing previously allocated receive buffers */
268         for (i = 0; i < NUM_RX_BUFFERS; i++){
269                 rx_skbuff = lp->rx_skbuff[i];
270                 if(rx_skbuff != NULL){
271                         pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
272                                   lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
273                         dev_kfree_skb(lp->rx_skbuff[i]);
274                         lp->rx_skbuff[i] = NULL;
275                         lp->rx_dma_addr[i] = 0;
276                 }
277         }
278         
279         return 0;
280 }
281
282 /*
283 This will set the receive buffer length corresponding to the mtu size of networkinterface.
284 */
285 static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
286 {
287         struct amd8111e_priv* lp = netdev_priv(dev);
288         unsigned int mtu = dev->mtu;
289         
290         if (mtu > ETH_DATA_LEN){
291                 /* MTU + ethernet header + FCS
292                 + optional VLAN tag + skb reserve space 2 */
293
294                 lp->rx_buff_len = mtu + ETH_HLEN + 10;
295                 lp->options |= OPTION_JUMBO_ENABLE;
296         } else{
297                 lp->rx_buff_len = PKT_BUFF_SZ;
298                 lp->options &= ~OPTION_JUMBO_ENABLE;
299         }
300 }
301
302 /* 
303 This function will free all the previously allocated buffers, determine new receive buffer length  and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
304  */
305 static int amd8111e_init_ring(struct net_device *dev)
306 {
307         struct amd8111e_priv *lp = netdev_priv(dev);
308         int i;
309
310         lp->rx_idx = lp->tx_idx = 0;
311         lp->tx_complete_idx = 0;
312         lp->tx_ring_idx = 0;
313         
314
315         if(lp->opened)
316                 /* Free previously allocated transmit and receive skbs */
317                 amd8111e_free_skbs(dev);        
318
319         else{
320                  /* allocate the tx and rx descriptors */
321                 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev, 
322                         sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
323                         &lp->tx_ring_dma_addr)) == NULL)
324                 
325                         goto err_no_mem;
326         
327                 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev, 
328                         sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
329                         &lp->rx_ring_dma_addr)) == NULL)
330                 
331                         goto err_free_tx_ring;
332
333         }
334         /* Set new receive buff size */
335         amd8111e_set_rx_buff_len(dev);
336
337         /* Allocating receive  skbs */
338         for (i = 0; i < NUM_RX_BUFFERS; i++) {
339
340                 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
341                                 /* Release previos allocated skbs */
342                                 for(--i; i >= 0 ;i--)
343                                         dev_kfree_skb(lp->rx_skbuff[i]);
344                                 goto err_free_rx_ring;
345                 }
346                 skb_reserve(lp->rx_skbuff[i],2);
347         }
348         /* Initilaizing receive descriptors */
349         for (i = 0; i < NUM_RX_BUFFERS; i++) {
350                 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, 
351                         lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
352
353                 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
354                 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
355                 wmb();
356                 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
357         }
358
359         /* Initializing transmit descriptors */
360         for (i = 0; i < NUM_TX_RING_DR; i++) {
361                 lp->tx_ring[i].buff_phy_addr = 0;
362                 lp->tx_ring[i].tx_flags = 0;
363                 lp->tx_ring[i].buff_count = 0;
364         }
365
366         return 0;
367
368 err_free_rx_ring:
369         
370         pci_free_consistent(lp->pci_dev, 
371                 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
372                 lp->rx_ring_dma_addr);
373
374 err_free_tx_ring:
375         
376         pci_free_consistent(lp->pci_dev,
377                  sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring, 
378                  lp->tx_ring_dma_addr);
379
380 err_no_mem:
381         return -ENOMEM;
382 }
383 /* This function will set the interrupt coalescing according to the input arguments */
384 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
385 {
386         unsigned int timeout;
387         unsigned int event_count;
388
389         struct amd8111e_priv *lp = netdev_priv(dev);
390         void __iomem *mmio = lp->mmio;
391         struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
392
393
394         switch(cmod)
395         {
396                 case RX_INTR_COAL :
397                         timeout = coal_conf->rx_timeout;
398                         event_count = coal_conf->rx_event_count;
399                         if( timeout > MAX_TIMEOUT || 
400                                         event_count > MAX_EVENT_COUNT ) 
401                         return -EINVAL;
402
403                         timeout = timeout * DELAY_TIMER_CONV; 
404                         writel(VAL0|STINTEN, mmio+INTEN0);
405                         writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
406                                                         mmio+DLY_INT_A);
407                         break;
408
409                 case TX_INTR_COAL :
410                         timeout = coal_conf->tx_timeout;
411                         event_count = coal_conf->tx_event_count;
412                         if( timeout > MAX_TIMEOUT || 
413                                         event_count > MAX_EVENT_COUNT ) 
414                         return -EINVAL;
415
416                    
417                         timeout = timeout * DELAY_TIMER_CONV; 
418                         writel(VAL0|STINTEN,mmio+INTEN0);
419                         writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
420                                                          mmio+DLY_INT_B);
421                         break;
422
423                 case DISABLE_COAL:
424                         writel(0,mmio+STVAL);
425                         writel(STINTEN, mmio+INTEN0);
426                         writel(0, mmio +DLY_INT_B);
427                         writel(0, mmio+DLY_INT_A);
428                         break;
429                  case ENABLE_COAL: 
430                        /* Start the timer */
431                         writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /*  0.5 sec */
432                         writel(VAL0|STINTEN, mmio+INTEN0);
433                         break;
434                 default:
435                         break;
436
437    }
438         return 0;
439
440 }
441
442 /* 
443 This function initializes the device registers  and starts the device.  
444 */
445 static int amd8111e_restart(struct net_device *dev)
446 {
447         struct amd8111e_priv *lp = netdev_priv(dev);
448         void __iomem *mmio = lp->mmio;
449         int i,reg_val;
450
451         /* stop the chip */
452          writel(RUN, mmio + CMD0);
453
454         if(amd8111e_init_ring(dev))
455                 return -ENOMEM;
456
457         /* enable the port manager and set auto negotiation always */
458         writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
459         writel((u32)XPHYANE|XPHYRST , mmio + CTRL2); 
460         
461         amd8111e_set_ext_phy(dev);
462
463         /* set control registers */
464         reg_val = readl(mmio + CTRL1);
465         reg_val &= ~XMTSP_MASK;
466         writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
467
468         /* enable interrupt */
469         writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN | 
470                 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
471                 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
472
473         writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
474
475         /* initialize tx and rx ring base addresses */
476         writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
477         writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
478
479         writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
480         writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
481         
482         /* set default IPG to 96 */
483         writew((u32)DEFAULT_IPG,mmio+IPG);
484         writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1); 
485
486         if(lp->options & OPTION_JUMBO_ENABLE){
487                 writel((u32)VAL2|JUMBO, mmio + CMD3);
488                 /* Reset REX_UFLO */
489                 writel( REX_UFLO, mmio + CMD2);
490                 /* Should not set REX_UFLO for jumbo frames */
491                 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
492         }else{
493                 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
494                 writel((u32)JUMBO, mmio + CMD3);
495         }
496
497 #if AMD8111E_VLAN_TAG_USED
498         writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
499 #endif
500         writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
501         
502         /* Setting the MAC address to the device */
503         for(i = 0; i < ETH_ADDR_LEN; i++)
504                 writeb( dev->dev_addr[i], mmio + PADR + i ); 
505
506         /* Enable interrupt coalesce */
507         if(lp->options & OPTION_INTR_COAL_ENABLE){
508                 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
509                                                                 dev->name);
510                 amd8111e_set_coalesce(dev,ENABLE_COAL);
511         }
512         
513         /* set RUN bit to start the chip */
514         writel(VAL2 | RDMD0, mmio + CMD0);
515         writel(VAL0 | INTREN | RUN, mmio + CMD0);
516         
517         /* To avoid PCI posting bug */
518         readl(mmio+CMD0);
519         return 0;
520 }
521 /* 
522 This function clears necessary the device registers. 
523 */      
524 static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
525 {
526         unsigned int reg_val;
527         unsigned int logic_filter[2] ={0,};
528         void __iomem *mmio = lp->mmio;
529
530
531         /* stop the chip */
532         writel(RUN, mmio + CMD0);
533
534         /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
535         writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
536
537         /* Clear RCV_RING_BASE_ADDR */
538         writel(0, mmio + RCV_RING_BASE_ADDR0);
539
540         /* Clear XMT_RING_BASE_ADDR */
541         writel(0, mmio + XMT_RING_BASE_ADDR0);
542         writel(0, mmio + XMT_RING_BASE_ADDR1);
543         writel(0, mmio + XMT_RING_BASE_ADDR2);
544         writel(0, mmio + XMT_RING_BASE_ADDR3);
545
546         /* Clear CMD0  */
547         writel(CMD0_CLEAR,mmio + CMD0);
548         
549         /* Clear CMD2 */
550         writel(CMD2_CLEAR, mmio +CMD2);
551
552         /* Clear CMD7 */
553         writel(CMD7_CLEAR , mmio + CMD7);
554
555         /* Clear DLY_INT_A and DLY_INT_B */
556         writel(0x0, mmio + DLY_INT_A);
557         writel(0x0, mmio + DLY_INT_B);
558
559         /* Clear FLOW_CONTROL */
560         writel(0x0, mmio + FLOW_CONTROL);
561
562         /* Clear INT0  write 1 to clear register */
563         reg_val = readl(mmio + INT0);
564         writel(reg_val, mmio + INT0);
565
566         /* Clear STVAL */
567         writel(0x0, mmio + STVAL);
568
569         /* Clear INTEN0 */
570         writel( INTEN0_CLEAR, mmio + INTEN0);
571
572         /* Clear LADRF */
573         writel(0x0 , mmio + LADRF);
574
575         /* Set SRAM_SIZE & SRAM_BOUNDARY registers  */
576         writel( 0x80010,mmio + SRAM_SIZE);
577
578         /* Clear RCV_RING0_LEN */
579         writel(0x0, mmio +  RCV_RING_LEN0);
580
581         /* Clear XMT_RING0/1/2/3_LEN */
582         writel(0x0, mmio +  XMT_RING_LEN0);
583         writel(0x0, mmio +  XMT_RING_LEN1);
584         writel(0x0, mmio +  XMT_RING_LEN2);
585         writel(0x0, mmio +  XMT_RING_LEN3);
586
587         /* Clear XMT_RING_LIMIT */
588         writel(0x0, mmio + XMT_RING_LIMIT);
589
590         /* Clear MIB */
591         writew(MIB_CLEAR, mmio + MIB_ADDR);
592
593         /* Clear LARF */
594         amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
595
596         /* SRAM_SIZE register */
597         reg_val = readl(mmio + SRAM_SIZE);
598         
599         if(lp->options & OPTION_JUMBO_ENABLE)
600                 writel( VAL2|JUMBO, mmio + CMD3);
601 #if AMD8111E_VLAN_TAG_USED
602         writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
603 #endif
604         /* Set default value to CTRL1 Register */
605         writel(CTRL1_DEFAULT, mmio + CTRL1);
606
607         /* To avoid PCI posting bug */
608         readl(mmio + CMD2);
609
610 }
611
612 /* 
613 This function disables the interrupt and clears all the pending 
614 interrupts in INT0
615  */
616 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
617 {       
618         u32 intr0;
619
620         /* Disable interrupt */
621         writel(INTREN, lp->mmio + CMD0);
622         
623         /* Clear INT0 */
624         intr0 = readl(lp->mmio + INT0);
625         writel(intr0, lp->mmio + INT0);
626         
627         /* To avoid PCI posting bug */
628         readl(lp->mmio + INT0);
629
630 }
631
632 /*
633 This function stops the chip. 
634 */
635 static void amd8111e_stop_chip(struct amd8111e_priv* lp)
636 {
637         writel(RUN, lp->mmio + CMD0);
638         
639         /* To avoid PCI posting bug */
640         readl(lp->mmio + CMD0);
641 }
642
643 /* 
644 This function frees the  transmiter and receiver descriptor rings.
645 */
646 static void amd8111e_free_ring(struct amd8111e_priv* lp)
647 {       
648
649         /* Free transmit and receive skbs */
650         amd8111e_free_skbs(lp->amd8111e_net_dev);
651
652         /* Free transmit and receive descriptor rings */
653         if(lp->rx_ring){
654                 pci_free_consistent(lp->pci_dev, 
655                         sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
656                         lp->rx_ring, lp->rx_ring_dma_addr);
657                 lp->rx_ring = NULL;
658         }
659         
660         if(lp->tx_ring){
661                 pci_free_consistent(lp->pci_dev, 
662                         sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
663                         lp->tx_ring, lp->tx_ring_dma_addr);
664
665                 lp->tx_ring = NULL;
666         }
667
668 }
669 #if AMD8111E_VLAN_TAG_USED      
670 /* 
671 This is the receive indication function for packets with vlan tag.
672 */      
673 static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
674 {
675 #ifdef CONFIG_AMD8111E_NAPI
676         return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
677 #else
678         return vlan_hwaccel_rx(skb, lp->vlgrp, vlan_tag);
679 #endif /* CONFIG_AMD8111E_NAPI */
680 }
681 #endif
682
683 /*
684 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb. 
685 */
686 static int amd8111e_tx(struct net_device *dev)
687 {
688         struct amd8111e_priv* lp = netdev_priv(dev);
689         int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
690         int status;
691         /* Complete all the transmit packet */
692         while (lp->tx_complete_idx != lp->tx_idx){
693                 tx_index =  lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
694                 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
695
696                 if(status & OWN_BIT)
697                         break;  /* It still hasn't been Txed */
698
699                 lp->tx_ring[tx_index].buff_phy_addr = 0;
700
701                 /* We must free the original skb */
702                 if (lp->tx_skbuff[tx_index]) {
703                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
704                                         lp->tx_skbuff[tx_index]->len,
705                                         PCI_DMA_TODEVICE);
706                         dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
707                         lp->tx_skbuff[tx_index] = NULL;
708                         lp->tx_dma_addr[tx_index] = 0;
709                 }
710                 lp->tx_complete_idx++;
711                 /*COAL update tx coalescing parameters */
712                 lp->coal_conf.tx_packets++;
713                 lp->coal_conf.tx_bytes += lp->tx_ring[tx_index].buff_count;     
714
715                 if (netif_queue_stopped(dev) &&
716                         lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
717                         /* The ring is no longer full, clear tbusy. */
718                         /* lp->tx_full = 0; */
719                         netif_wake_queue (dev);
720                 }
721         }
722         return 0;
723 }
724
725 #ifdef CONFIG_AMD8111E_NAPI
726 /* This function handles the driver receive operation in polling mode */
727 static int amd8111e_rx_poll(struct net_device *dev, int * budget)
728 {
729         struct amd8111e_priv *lp = netdev_priv(dev);
730         int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
731         void __iomem *mmio = lp->mmio;
732         struct sk_buff *skb,*new_skb;
733         int min_pkt_len, status;
734         unsigned int intr0;
735         int num_rx_pkt = 0;
736         /*int max_rx_pkt = NUM_RX_BUFFERS;*/
737         short pkt_len;
738 #if AMD8111E_VLAN_TAG_USED              
739         short vtag;
740 #endif
741         int rx_pkt_limit = dev->quota;
742         unsigned long flags;
743         
744         do{   
745                 /* process receive packets until we use the quota*/
746                 /* If we own the next entry, it's a new packet. Send it up. */
747                 while(1) {
748                         status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
749                         if (status & OWN_BIT)
750                                 break;
751
752                         /* 
753                          * There is a tricky error noted by John Murphy,
754                          * <murf@perftech.com> to Russ Nelson: Even with
755                          * full-sized * buffers it's possible for a  
756                          * jabber packet to use two buffers, with only 
757                          * the last correctly noting the error.
758                          */
759
760                         if(status & ERR_BIT) {
761                                 /* reseting flags */
762                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
763                                 goto err_next_pkt;
764                         }
765                         /* check for STP and ENP */
766                         if(!((status & STP_BIT) && (status & ENP_BIT))){
767                                 /* reseting flags */
768                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
769                                 goto err_next_pkt;
770                         }
771                         pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
772
773 #if AMD8111E_VLAN_TAG_USED              
774                         vtag = status & TT_MASK;
775                         /*MAC will strip vlan tag*/ 
776                         if(lp->vlgrp != NULL && vtag !=0)
777                                 min_pkt_len =MIN_PKT_LEN - 4;
778                         else
779 #endif
780                                 min_pkt_len =MIN_PKT_LEN;
781
782                         if (pkt_len < min_pkt_len) {
783                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
784                                 lp->drv_rx_errors++;
785                                 goto err_next_pkt;
786                         }
787                         if(--rx_pkt_limit < 0)
788                                 goto rx_not_empty;
789                         if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
790                                 /* if allocation fail, 
791                                    ignore that pkt and go to next one */
792                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
793                                 lp->drv_rx_errors++;
794                                 goto err_next_pkt;
795                         }
796                 
797                         skb_reserve(new_skb, 2);
798                         skb = lp->rx_skbuff[rx_index];
799                         pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
800                                          lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
801                         skb_put(skb, pkt_len);
802                         skb->dev = dev;
803                         lp->rx_skbuff[rx_index] = new_skb;
804                         new_skb->dev = dev;
805                         lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
806                                                                    new_skb->data,
807                                                                    lp->rx_buff_len-2,
808                                                                    PCI_DMA_FROMDEVICE);
809         
810                         skb->protocol = eth_type_trans(skb, dev);
811
812 #if AMD8111E_VLAN_TAG_USED              
813                         if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
814                                 amd8111e_vlan_rx(lp, skb,
815                                          le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
816                         } else
817 #endif
818                                 netif_receive_skb(skb);
819                         /*COAL update rx coalescing parameters*/
820                         lp->coal_conf.rx_packets++;
821                         lp->coal_conf.rx_bytes += pkt_len;      
822                         num_rx_pkt++;
823                         dev->last_rx = jiffies;
824         
825                 err_next_pkt:   
826                         lp->rx_ring[rx_index].buff_phy_addr
827                                 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
828                         lp->rx_ring[rx_index].buff_count = 
829                                 cpu_to_le16(lp->rx_buff_len-2);
830                         wmb();
831                         lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
832                         rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
833                 }
834                 /* Check the interrupt status register for more packets in the 
835                    mean time. Process them since we have not used up our quota.*/
836
837                 intr0 = readl(mmio + INT0);
838                 /*Ack receive packets */
839                 writel(intr0 & RINT0,mmio + INT0);
840
841         } while(intr0 & RINT0);
842
843         /* Receive descriptor is empty now */
844         dev->quota -= num_rx_pkt;
845         *budget -= num_rx_pkt;
846
847         spin_lock_irqsave(&lp->lock, flags);
848         netif_rx_complete(dev);
849         writel(VAL0|RINTEN0, mmio + INTEN0);
850         writel(VAL2 | RDMD0, mmio + CMD0);
851         spin_unlock_irqrestore(&lp->lock, flags);
852         return 0;
853
854 rx_not_empty:
855         /* Do not call a netif_rx_complete */
856         dev->quota -= num_rx_pkt;       
857         *budget -= num_rx_pkt;
858         return 1;
859 }
860
861 #else
862 /* 
863 This function will check the ownership of receive buffers and descriptors. It will indicate to kernel up to half the number of maximum receive buffers in the descriptor ring, in a single receive interrupt. It will also replenish the descriptors with new skbs.
864 */
865 static int amd8111e_rx(struct net_device *dev)
866 {
867         struct amd8111e_priv *lp = netdev_priv(dev);
868         struct sk_buff *skb,*new_skb;
869         int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
870         int min_pkt_len, status;
871         int num_rx_pkt = 0;
872         int max_rx_pkt = NUM_RX_BUFFERS;
873         short pkt_len;
874 #if AMD8111E_VLAN_TAG_USED              
875         short vtag;
876 #endif
877         
878         /* If we own the next entry, it's a new packet. Send it up. */
879         while(++num_rx_pkt <= max_rx_pkt){
880                 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
881                 if(status & OWN_BIT)
882                         return 0;
883                
884                 /* check if err summary bit is set */ 
885                 if(status & ERR_BIT){
886                         /* 
887                          * There is a tricky error noted by John Murphy,
888                          * <murf@perftech.com> to Russ Nelson: Even with full-sized
889                          * buffers it's possible for a jabber packet to use two
890                          * buffers, with only the last correctly noting the error.                       */
891                         /* reseting flags */
892                         lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
893                         goto err_next_pkt;
894                 }
895                 /* check for STP and ENP */
896                 if(!((status & STP_BIT) && (status & ENP_BIT))){
897                         /* reseting flags */
898                         lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
899                         goto err_next_pkt;
900                 }
901                 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
902
903 #if AMD8111E_VLAN_TAG_USED              
904                 vtag = status & TT_MASK;
905                 /*MAC will strip vlan tag*/ 
906                 if(lp->vlgrp != NULL && vtag !=0)
907                         min_pkt_len =MIN_PKT_LEN - 4;
908                 else
909 #endif
910                         min_pkt_len =MIN_PKT_LEN;
911
912                 if (pkt_len < min_pkt_len) {
913                         lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
914                         lp->drv_rx_errors++;
915                         goto err_next_pkt;
916                 }
917                 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
918                         /* if allocation fail, 
919                                 ignore that pkt and go to next one */
920                         lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
921                         lp->drv_rx_errors++;
922                         goto err_next_pkt;
923                 }
924                 
925                 skb_reserve(new_skb, 2);
926                 skb = lp->rx_skbuff[rx_index];
927                 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
928                         lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
929                 skb_put(skb, pkt_len);
930                 skb->dev = dev;
931                 lp->rx_skbuff[rx_index] = new_skb;
932                 new_skb->dev = dev;
933                 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
934                         new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
935         
936                 skb->protocol = eth_type_trans(skb, dev);
937
938 #if AMD8111E_VLAN_TAG_USED                              
939                 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
940                         amd8111e_vlan_rx(lp, skb,
941                                  le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
942                 } else
943 #endif
944                         
945                         netif_rx (skb);
946                         /*COAL update rx coalescing parameters*/
947                         lp->coal_conf.rx_packets++;
948                         lp->coal_conf.rx_bytes += pkt_len;      
949
950                         dev->last_rx = jiffies;
951         
952 err_next_pkt:
953                 lp->rx_ring[rx_index].buff_phy_addr
954                          = cpu_to_le32(lp->rx_dma_addr[rx_index]);
955                 lp->rx_ring[rx_index].buff_count = 
956                                 cpu_to_le16(lp->rx_buff_len-2);
957                 wmb();
958                 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
959                 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
960         }
961
962         return 0;
963 }
964 #endif /* CONFIG_AMD8111E_NAPI */
965 /* 
966 This function will indicate the link status to the kernel.
967 */
968 static int amd8111e_link_change(struct net_device* dev)
969 {       
970         struct amd8111e_priv *lp = netdev_priv(dev);
971         int status0,speed;
972
973         /* read the link change */
974         status0 = readl(lp->mmio + STAT0);
975         
976         if(status0 & LINK_STATS){
977                 if(status0 & AUTONEG_COMPLETE)
978                         lp->link_config.autoneg = AUTONEG_ENABLE;
979                 else 
980                         lp->link_config.autoneg = AUTONEG_DISABLE;
981
982                 if(status0 & FULL_DPLX)
983                         lp->link_config.duplex = DUPLEX_FULL;
984                 else 
985                         lp->link_config.duplex = DUPLEX_HALF;
986                 speed = (status0 & SPEED_MASK) >> 7;
987                 if(speed == PHY_SPEED_10)
988                         lp->link_config.speed = SPEED_10;
989                 else if(speed == PHY_SPEED_100)
990                         lp->link_config.speed = SPEED_100;
991
992                 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n",                        dev->name,
993                        (lp->link_config.speed == SPEED_100) ? "100": "10", 
994                        (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half"); 
995                 netif_carrier_on(dev);
996         }
997         else{   
998                 lp->link_config.speed = SPEED_INVALID;
999                 lp->link_config.duplex = DUPLEX_INVALID;
1000                 lp->link_config.autoneg = AUTONEG_INVALID;
1001                 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
1002                 netif_carrier_off(dev);
1003         }
1004                 
1005         return 0;
1006 }
1007 /*
1008 This function reads the mib counters.    
1009 */
1010 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
1011 {
1012         unsigned int  status;
1013         unsigned  int data;
1014         unsigned int repeat = REPEAT_CNT;
1015
1016         writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
1017         do {
1018                 status = readw(mmio + MIB_ADDR);
1019                 udelay(2);      /* controller takes MAX 2 us to get mib data */
1020         }
1021         while (--repeat && (status & MIB_CMD_ACTIVE));
1022
1023         data = readl(mmio + MIB_DATA);
1024         return data;
1025 }
1026
1027 /*
1028 This function reads the mib registers and returns the hardware statistics. It  updates previous internal driver statistics with new values.
1029 */ 
1030 static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
1031 {
1032         struct amd8111e_priv *lp = netdev_priv(dev);
1033         void __iomem *mmio = lp->mmio;
1034         unsigned long flags;
1035         /* struct net_device_stats *prev_stats = &lp->prev_stats; */
1036         struct net_device_stats* new_stats = &lp->stats;
1037         
1038         if(!lp->opened)
1039                 return &lp->stats;      
1040         spin_lock_irqsave (&lp->lock, flags);
1041
1042         /* stats.rx_packets */
1043         new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
1044                                 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
1045                                 amd8111e_read_mib(mmio, rcv_unicast_pkts);
1046
1047         /* stats.tx_packets */
1048         new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
1049
1050         /*stats.rx_bytes */
1051         new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
1052
1053         /* stats.tx_bytes */
1054         new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
1055
1056         /* stats.rx_errors */
1057         /* hw errors + errors driver reported */
1058         new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1059                                 amd8111e_read_mib(mmio, rcv_fragments)+
1060                                 amd8111e_read_mib(mmio, rcv_jabbers)+
1061                                 amd8111e_read_mib(mmio, rcv_alignment_errors)+
1062                                 amd8111e_read_mib(mmio, rcv_fcs_errors)+
1063                                 amd8111e_read_mib(mmio, rcv_miss_pkts)+
1064                                 lp->drv_rx_errors;
1065
1066         /* stats.tx_errors */
1067         new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1068
1069         /* stats.rx_dropped*/
1070         new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
1071
1072         /* stats.tx_dropped*/
1073         new_stats->tx_dropped = amd8111e_read_mib(mmio,  xmt_underrun_pkts);
1074
1075         /* stats.multicast*/
1076         new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
1077
1078         /* stats.collisions*/
1079         new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
1080
1081         /* stats.rx_length_errors*/
1082         new_stats->rx_length_errors = 
1083                 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1084                 amd8111e_read_mib(mmio, rcv_oversize_pkts);
1085
1086         /* stats.rx_over_errors*/
1087         new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1088
1089         /* stats.rx_crc_errors*/
1090         new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
1091
1092         /* stats.rx_frame_errors*/
1093         new_stats->rx_frame_errors =
1094                 amd8111e_read_mib(mmio, rcv_alignment_errors);
1095
1096         /* stats.rx_fifo_errors */
1097         new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1098
1099         /* stats.rx_missed_errors */
1100         new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1101
1102         /* stats.tx_aborted_errors*/
1103         new_stats->tx_aborted_errors = 
1104                 amd8111e_read_mib(mmio, xmt_excessive_collision);
1105
1106         /* stats.tx_carrier_errors*/
1107         new_stats->tx_carrier_errors = 
1108                 amd8111e_read_mib(mmio, xmt_loss_carrier);
1109
1110         /* stats.tx_fifo_errors*/
1111         new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1112
1113         /* stats.tx_window_errors*/
1114         new_stats->tx_window_errors =
1115                 amd8111e_read_mib(mmio, xmt_late_collision);
1116
1117         /* Reset the mibs for collecting new statistics */
1118         /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
1119                 
1120         spin_unlock_irqrestore (&lp->lock, flags);
1121
1122         return new_stats;
1123 }
1124 /* This function recalculate the interupt coalescing  mode on every interrupt 
1125 according to the datarate and the packet rate.
1126 */
1127 static int amd8111e_calc_coalesce(struct net_device *dev)
1128 {
1129         struct amd8111e_priv *lp = netdev_priv(dev);
1130         struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1131         int tx_pkt_rate;
1132         int rx_pkt_rate;
1133         int tx_data_rate;
1134         int rx_data_rate;
1135         int rx_pkt_size;
1136         int tx_pkt_size;
1137
1138         tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1139         coal_conf->tx_prev_packets =  coal_conf->tx_packets;
1140         
1141         tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1142         coal_conf->tx_prev_bytes =  coal_conf->tx_bytes;
1143         
1144         rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1145         coal_conf->rx_prev_packets =  coal_conf->rx_packets;
1146         
1147         rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1148         coal_conf->rx_prev_bytes =  coal_conf->rx_bytes;
1149         
1150         if(rx_pkt_rate < 800){
1151                 if(coal_conf->rx_coal_type != NO_COALESCE){
1152                         
1153                         coal_conf->rx_timeout = 0x0;
1154                         coal_conf->rx_event_count = 0;
1155                         amd8111e_set_coalesce(dev,RX_INTR_COAL);
1156                         coal_conf->rx_coal_type = NO_COALESCE;
1157                 }
1158         }
1159         else{
1160         
1161                 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1162                 if (rx_pkt_size < 128){
1163                         if(coal_conf->rx_coal_type != NO_COALESCE){
1164                         
1165                                 coal_conf->rx_timeout = 0;
1166                                 coal_conf->rx_event_count = 0;
1167                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1168                                 coal_conf->rx_coal_type = NO_COALESCE;
1169                         }
1170
1171                 }
1172                 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1173         
1174                         if(coal_conf->rx_coal_type !=  LOW_COALESCE){
1175                                 coal_conf->rx_timeout = 1;
1176                                 coal_conf->rx_event_count = 4;
1177                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1178                                 coal_conf->rx_coal_type = LOW_COALESCE;
1179                         }
1180                 }
1181                 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1182                         
1183                         if(coal_conf->rx_coal_type !=  MEDIUM_COALESCE){
1184                                 coal_conf->rx_timeout = 1;
1185                                 coal_conf->rx_event_count = 4;
1186                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1187                                 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1188                         }               
1189                                 
1190                 }
1191                 else if(rx_pkt_size >= 1024){
1192                         if(coal_conf->rx_coal_type !=  HIGH_COALESCE){
1193                                 coal_conf->rx_timeout = 2;
1194                                 coal_conf->rx_event_count = 3;
1195                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1196                                 coal_conf->rx_coal_type = HIGH_COALESCE;
1197                         }               
1198                 }
1199         }
1200         /* NOW FOR TX INTR COALESC */
1201         if(tx_pkt_rate < 800){
1202                 if(coal_conf->tx_coal_type != NO_COALESCE){
1203                         
1204                         coal_conf->tx_timeout = 0x0;
1205                         coal_conf->tx_event_count = 0;
1206                         amd8111e_set_coalesce(dev,TX_INTR_COAL);
1207                         coal_conf->tx_coal_type = NO_COALESCE;
1208                 }
1209         }
1210         else{
1211         
1212                 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1213                 if (tx_pkt_size < 128){
1214                 
1215                         if(coal_conf->tx_coal_type != NO_COALESCE){
1216                         
1217                                 coal_conf->tx_timeout = 0;
1218                                 coal_conf->tx_event_count = 0;
1219                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1220                                 coal_conf->tx_coal_type = NO_COALESCE;
1221                         }
1222
1223                 }
1224                 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1225         
1226                         if(coal_conf->tx_coal_type !=  LOW_COALESCE){
1227                                 coal_conf->tx_timeout = 1;
1228                                 coal_conf->tx_event_count = 2;
1229                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1230                                 coal_conf->tx_coal_type = LOW_COALESCE;
1231
1232                         }
1233                 }
1234                 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1235                         
1236                         if(coal_conf->tx_coal_type !=  MEDIUM_COALESCE){
1237                                 coal_conf->tx_timeout = 2;
1238                                 coal_conf->tx_event_count = 5;
1239                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1240                                 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1241                         }               
1242                                 
1243                 }
1244                 else if(tx_pkt_size >= 1024){
1245                         if (tx_pkt_size >= 1024){
1246                                 if(coal_conf->tx_coal_type !=  HIGH_COALESCE){
1247                                         coal_conf->tx_timeout = 4;
1248                                         coal_conf->tx_event_count = 8;
1249                                         amd8111e_set_coalesce(dev,TX_INTR_COAL);
1250                                         coal_conf->tx_coal_type = HIGH_COALESCE;
1251                                 }               
1252                         }
1253                 }
1254         }
1255         return 0;
1256
1257 }
1258 /*
1259 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1260 */
1261 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1262 {
1263
1264         struct net_device * dev = (struct net_device *) dev_id;
1265         struct amd8111e_priv *lp = netdev_priv(dev);
1266         void __iomem *mmio = lp->mmio;
1267         unsigned int intr0, intren0;
1268         unsigned int handled = 1;
1269
1270         if(unlikely(dev == NULL))
1271                 return IRQ_NONE;
1272
1273         spin_lock(&lp->lock);
1274
1275         /* disabling interrupt */
1276         writel(INTREN, mmio + CMD0);
1277
1278         /* Read interrupt status */
1279         intr0 = readl(mmio + INT0);
1280         intren0 = readl(mmio + INTEN0);
1281
1282         /* Process all the INT event until INTR bit is clear. */
1283
1284         if (!(intr0 & INTR)){
1285                 handled = 0;
1286                 goto err_no_interrupt;
1287         }
1288                  
1289         /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1290         writel(intr0, mmio + INT0);
1291
1292         /* Check if Receive Interrupt has occurred. */
1293 #ifdef CONFIG_AMD8111E_NAPI
1294         if(intr0 & RINT0){
1295                 if(netif_rx_schedule_prep(dev)){
1296                         /* Disable receive interupts */
1297                         writel(RINTEN0, mmio + INTEN0);
1298                         /* Schedule a polling routine */
1299                         __netif_rx_schedule(dev);
1300                 }
1301                 else if (intren0 & RINTEN0) {
1302                         printk("************Driver bug! \
1303                                 interrupt while in poll\n");
1304                         /* Fix by disable receive interrupts */
1305                         writel(RINTEN0, mmio + INTEN0);
1306                 }
1307         }
1308 #else
1309         if(intr0 & RINT0){
1310                 amd8111e_rx(dev);
1311                 writel(VAL2 | RDMD0, mmio + CMD0);
1312         }
1313 #endif /* CONFIG_AMD8111E_NAPI */
1314         /* Check if  Transmit Interrupt has occurred. */
1315         if(intr0 & TINT0)
1316                 amd8111e_tx(dev);
1317                 
1318         /* Check if  Link Change Interrupt has occurred. */
1319         if (intr0 & LCINT)
1320                 amd8111e_link_change(dev);
1321
1322         /* Check if Hardware Timer Interrupt has occurred. */
1323         if (intr0 & STINT)
1324                 amd8111e_calc_coalesce(dev);
1325
1326 err_no_interrupt:
1327         writel( VAL0 | INTREN,mmio + CMD0);
1328         
1329         spin_unlock(&lp->lock);
1330         
1331         return IRQ_RETVAL(handled);
1332 }
1333
1334 #ifdef CONFIG_NET_POLL_CONTROLLER
1335 static void amd8111e_poll(struct net_device *dev)
1336
1337         unsigned long flags;
1338         local_save_flags(flags); 
1339         local_irq_disable();
1340         amd8111e_interrupt(0, dev, NULL);
1341         local_irq_restore(flags); 
1342
1343 #endif
1344
1345
1346 /*
1347 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1348 */
1349 static int amd8111e_close(struct net_device * dev)
1350 {
1351         struct amd8111e_priv *lp = netdev_priv(dev);
1352         netif_stop_queue(dev);
1353         
1354         spin_lock_irq(&lp->lock);
1355         
1356         amd8111e_disable_interrupt(lp);
1357         amd8111e_stop_chip(lp);
1358         amd8111e_free_ring(lp);
1359         
1360         netif_carrier_off(lp->amd8111e_net_dev);
1361
1362         /* Delete ipg timer */
1363         if(lp->options & OPTION_DYN_IPG_ENABLE)         
1364                 del_timer_sync(&lp->ipg_data.ipg_timer);
1365
1366         spin_unlock_irq(&lp->lock);
1367         free_irq(dev->irq, dev);
1368         
1369         /* Update the statistics before closing */
1370         amd8111e_get_stats(dev);
1371         lp->opened = 0;
1372         return 0;
1373 }
1374 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device. 
1375 */
1376 static int amd8111e_open(struct net_device * dev )
1377 {
1378         struct amd8111e_priv *lp = netdev_priv(dev);
1379
1380         if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, SA_SHIRQ,
1381                                          dev->name, dev)) 
1382                 return -EAGAIN;
1383
1384         spin_lock_irq(&lp->lock);
1385
1386         amd8111e_init_hw_default(lp);
1387
1388         if(amd8111e_restart(dev)){
1389                 spin_unlock_irq(&lp->lock);
1390                 if (dev->irq)
1391                         free_irq(dev->irq, dev);
1392                 return -ENOMEM;
1393         }
1394         /* Start ipg timer */
1395         if(lp->options & OPTION_DYN_IPG_ENABLE){                
1396                 add_timer(&lp->ipg_data.ipg_timer);
1397                 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1398         }
1399
1400         lp->opened = 1;
1401
1402         spin_unlock_irq(&lp->lock);
1403
1404         netif_start_queue(dev);
1405
1406         return 0;               
1407 }
1408 /* 
1409 This function checks if there is any transmit  descriptors available to queue more packet.
1410 */
1411 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
1412 {       
1413         int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1414         if(lp->tx_skbuff[tx_index] != 0)
1415                 return -1;
1416         else
1417                 return 0;
1418         
1419 }
1420 /* 
1421 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1422 */
1423
1424 static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
1425 {
1426         struct amd8111e_priv *lp = netdev_priv(dev);
1427         int tx_index;
1428         unsigned long flags;
1429
1430         spin_lock_irqsave(&lp->lock, flags);
1431
1432         tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1433
1434         lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1435
1436         lp->tx_skbuff[tx_index] = skb;
1437         lp->tx_ring[tx_index].tx_flags = 0;
1438
1439 #if AMD8111E_VLAN_TAG_USED
1440         if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
1441                 lp->tx_ring[tx_index].tag_ctrl_cmd |= 
1442                                 cpu_to_le16(TCC_VLAN_INSERT);   
1443                 lp->tx_ring[tx_index].tag_ctrl_info = 
1444                                 cpu_to_le16(vlan_tx_tag_get(skb));
1445
1446         }
1447 #endif
1448         lp->tx_dma_addr[tx_index] =
1449             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1450         lp->tx_ring[tx_index].buff_phy_addr =
1451             (u32) cpu_to_le32(lp->tx_dma_addr[tx_index]);
1452
1453         /*  Set FCS and LTINT bits */
1454         wmb();
1455         lp->tx_ring[tx_index].tx_flags |=
1456             cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1457
1458         lp->tx_idx++;
1459
1460         /* Trigger an immediate send poll. */
1461         writel( VAL1 | TDMD0, lp->mmio + CMD0);
1462         writel( VAL2 | RDMD0,lp->mmio + CMD0);
1463
1464         dev->trans_start = jiffies;
1465
1466         if(amd8111e_tx_queue_avail(lp) < 0){
1467                 netif_stop_queue(dev);
1468         }
1469         spin_unlock_irqrestore(&lp->lock, flags);
1470         return 0;
1471 }
1472 /*
1473 This function returns all the memory mapped registers of the device.
1474 */
1475 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1476 {
1477         void __iomem *mmio = lp->mmio;
1478         /* Read only necessary registers */
1479         buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1480         buf[1] = readl(mmio + XMT_RING_LEN0);
1481         buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1482         buf[3] = readl(mmio + RCV_RING_LEN0);
1483         buf[4] = readl(mmio + CMD0);
1484         buf[5] = readl(mmio + CMD2);
1485         buf[6] = readl(mmio + CMD3);
1486         buf[7] = readl(mmio + CMD7);
1487         buf[8] = readl(mmio + INT0);
1488         buf[9] = readl(mmio + INTEN0);
1489         buf[10] = readl(mmio + LADRF);
1490         buf[11] = readl(mmio + LADRF+4);
1491         buf[12] = readl(mmio + STAT0);
1492 }
1493
1494 /*
1495 amd8111e crc generator implementation is different from the kernel
1496 ether_crc() function.
1497 */
1498 static int amd8111e_ether_crc(int len, char* mac_addr)
1499 {
1500         int i,byte;
1501         unsigned char octet;
1502         u32 crc= INITCRC;
1503
1504         for(byte=0; byte < len; byte++){
1505                 octet = mac_addr[byte];
1506                 for( i=0;i < 8; i++){
1507                         /*If the next bit form the input stream is 1,subtract                            the divisor (CRC32) from the dividend(crc).*/
1508                         if( (octet & 0x1) ^ (crc & 0x1) ){
1509                                 crc >>= 1;
1510                                 crc ^= CRC32;
1511                         }
1512                         else
1513                                 crc >>= 1;
1514                         
1515                         octet >>= 1;
1516                 }
1517         }       
1518         return crc; 
1519 }
1520 /*
1521 This function sets promiscuos mode, all-multi mode or the multicast address 
1522 list to the device.
1523 */
1524 static void amd8111e_set_multicast_list(struct net_device *dev)
1525 {
1526         struct dev_mc_list* mc_ptr;
1527         struct amd8111e_priv *lp = netdev_priv(dev);
1528         u32 mc_filter[2] ;
1529         int i,bit_num;
1530         if(dev->flags & IFF_PROMISC){
1531                 printk(KERN_INFO "%s: Setting  promiscuous mode.\n",dev->name);
1532                 writel( VAL2 | PROM, lp->mmio + CMD2);
1533                 return;
1534         }
1535         else
1536                 writel( PROM, lp->mmio + CMD2);
1537         if(dev->flags & IFF_ALLMULTI || dev->mc_count > MAX_FILTER_SIZE){
1538                 /* get all multicast packet */
1539                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1540                 lp->mc_list = dev->mc_list;
1541                 lp->options |= OPTION_MULTICAST_ENABLE;
1542                 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1543                 return;
1544         }
1545         if( dev->mc_count == 0 ){
1546                 /* get only own packets */
1547                 mc_filter[1] = mc_filter[0] = 0;
1548                 lp->mc_list = NULL;
1549                 lp->options &= ~OPTION_MULTICAST_ENABLE;
1550                 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1551                 /* disable promiscous mode */
1552                 writel(PROM, lp->mmio + CMD2);
1553                 return;
1554         }
1555         /* load all the multicast addresses in the logic filter */
1556         lp->options |= OPTION_MULTICAST_ENABLE;
1557         lp->mc_list = dev->mc_list;
1558         mc_filter[1] = mc_filter[0] = 0;
1559         for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1560                      i++, mc_ptr = mc_ptr->next) {
1561                 bit_num = ( amd8111e_ether_crc(ETH_ALEN,mc_ptr->dmi_addr)                                                        >> 26 ) & 0x3f;
1562                 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1563         }       
1564         amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1565
1566         /* To eliminate PCI posting bug */
1567         readl(lp->mmio + CMD2);
1568
1569 }
1570
1571 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1572 {
1573         struct amd8111e_priv *lp = netdev_priv(dev);
1574         struct pci_dev *pci_dev = lp->pci_dev;
1575         strcpy (info->driver, MODULE_NAME);
1576         strcpy (info->version, MODULE_VERS);
1577         sprintf(info->fw_version,"%u",chip_version);
1578         strcpy (info->bus_info, pci_name(pci_dev));
1579 }
1580
1581 static int amd8111e_get_regs_len(struct net_device *dev)
1582 {
1583         return AMD8111E_REG_DUMP_LEN;
1584 }
1585
1586 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1587 {
1588         struct amd8111e_priv *lp = netdev_priv(dev);
1589         regs->version = 0;
1590         amd8111e_read_regs(lp, buf);
1591 }
1592
1593 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1594 {
1595         struct amd8111e_priv *lp = netdev_priv(dev);
1596         spin_lock_irq(&lp->lock);
1597         mii_ethtool_gset(&lp->mii_if, ecmd);
1598         spin_unlock_irq(&lp->lock);
1599         return 0;
1600 }
1601
1602 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1603 {
1604         struct amd8111e_priv *lp = netdev_priv(dev);
1605         int res;
1606         spin_lock_irq(&lp->lock);
1607         res = mii_ethtool_sset(&lp->mii_if, ecmd);
1608         spin_unlock_irq(&lp->lock);
1609         return res;
1610 }
1611
1612 static int amd8111e_nway_reset(struct net_device *dev)
1613 {
1614         struct amd8111e_priv *lp = netdev_priv(dev);
1615         return mii_nway_restart(&lp->mii_if);
1616 }
1617
1618 static u32 amd8111e_get_link(struct net_device *dev)
1619 {
1620         struct amd8111e_priv *lp = netdev_priv(dev);
1621         return mii_link_ok(&lp->mii_if);
1622 }
1623
1624 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1625 {
1626         struct amd8111e_priv *lp = netdev_priv(dev);
1627         wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1628         if (lp->options & OPTION_WOL_ENABLE)
1629                 wol_info->wolopts = WAKE_MAGIC;
1630 }
1631
1632 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1633 {
1634         struct amd8111e_priv *lp = netdev_priv(dev);
1635         if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1636                 return -EINVAL;
1637         spin_lock_irq(&lp->lock);
1638         if (wol_info->wolopts & WAKE_MAGIC)
1639                 lp->options |= 
1640                         (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1641         else if(wol_info->wolopts & WAKE_PHY)
1642                 lp->options |= 
1643                         (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1644         else
1645                 lp->options &= ~OPTION_WOL_ENABLE; 
1646         spin_unlock_irq(&lp->lock);
1647         return 0;
1648 }
1649
1650 static struct ethtool_ops ops = {
1651         .get_drvinfo = amd8111e_get_drvinfo,
1652         .get_regs_len = amd8111e_get_regs_len,
1653         .get_regs = amd8111e_get_regs,
1654         .get_settings = amd8111e_get_settings,
1655         .set_settings = amd8111e_set_settings,
1656         .nway_reset = amd8111e_nway_reset,
1657         .get_link = amd8111e_get_link,
1658         .get_wol = amd8111e_get_wol,
1659         .set_wol = amd8111e_set_wol,
1660 };
1661
1662 /*
1663 This function handles all the  ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application. 
1664 */
1665         
1666 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1667 {
1668         struct mii_ioctl_data *data = if_mii(ifr);
1669         struct amd8111e_priv *lp = netdev_priv(dev);
1670         int err;
1671         u32 mii_regval;
1672
1673         if (!capable(CAP_NET_ADMIN))
1674                 return -EPERM;
1675
1676         switch(cmd) {
1677         case SIOCGMIIPHY:
1678                 data->phy_id = lp->ext_phy_addr;
1679
1680         /* fallthru */
1681         case SIOCGMIIREG: 
1682
1683                 spin_lock_irq(&lp->lock);
1684                 err = amd8111e_read_phy(lp, data->phy_id,
1685                         data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1686                 spin_unlock_irq(&lp->lock);
1687
1688                 data->val_out = mii_regval;
1689                 return err;
1690
1691         case SIOCSMIIREG:
1692
1693                 spin_lock_irq(&lp->lock);
1694                 err = amd8111e_write_phy(lp, data->phy_id,
1695                         data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1696                 spin_unlock_irq(&lp->lock);
1697
1698                 return err;
1699
1700         default:
1701                 /* do nothing */
1702                 break;
1703         }
1704         return -EOPNOTSUPP;
1705 }
1706 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1707 {
1708         struct amd8111e_priv *lp = netdev_priv(dev);
1709         int i;
1710         struct sockaddr *addr = p;
1711
1712         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1713         spin_lock_irq(&lp->lock);
1714         /* Setting the MAC address to the device */
1715         for(i = 0; i < ETH_ADDR_LEN; i++)
1716                 writeb( dev->dev_addr[i], lp->mmio + PADR + i ); 
1717                 
1718         spin_unlock_irq(&lp->lock);
1719
1720         return 0;
1721 }
1722
1723 /* 
1724 This function changes the mtu of the device. It restarts the device  to initialize the descriptor with new receive buffers.
1725 */  
1726 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1727 {
1728         struct amd8111e_priv *lp = netdev_priv(dev);
1729         int err;
1730
1731         if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1732                 return -EINVAL;
1733
1734         if (!netif_running(dev)) {
1735                 /* new_mtu will be used
1736                    when device starts netxt time */ 
1737                 dev->mtu = new_mtu;
1738                 return 0;
1739         }
1740
1741         spin_lock_irq(&lp->lock);
1742
1743         /* stop the chip */
1744         writel(RUN, lp->mmio + CMD0);
1745
1746         dev->mtu = new_mtu;
1747
1748         err = amd8111e_restart(dev);
1749         spin_unlock_irq(&lp->lock);
1750         if(!err)
1751                 netif_start_queue(dev);
1752         return err;
1753 }
1754
1755 #if AMD8111E_VLAN_TAG_USED
1756 static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1757 {
1758         struct  amd8111e_priv *lp = netdev_priv(dev);
1759         spin_lock_irq(&lp->lock);
1760         lp->vlgrp = grp;
1761         spin_unlock_irq(&lp->lock);
1762 }
1763         
1764 static void amd8111e_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1765 {
1766         struct amd8111e_priv *lp = netdev_priv(dev);
1767         spin_lock_irq(&lp->lock);
1768         if (lp->vlgrp)
1769                 lp->vlgrp->vlan_devices[vid] = NULL;
1770         spin_unlock_irq(&lp->lock);
1771 }
1772 #endif
1773 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1774 {
1775         writel( VAL1|MPPLBA, lp->mmio + CMD3);
1776         writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1777
1778         /* To eliminate PCI posting bug */
1779         readl(lp->mmio + CMD7);
1780         return 0;
1781 }
1782
1783 static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1784 {
1785
1786         /* Adapter is already stoped/suspended/interrupt-disabled */
1787         writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1788         
1789         /* To eliminate PCI posting bug */
1790         readl(lp->mmio + CMD7);
1791         return 0;
1792 }       
1793 /* This function is called when a packet transmission fails to complete within a  resonable period, on the assumption that an interrupts have been failed or the  interface is locked up. This function will reinitialize the hardware */
1794
1795 static void amd8111e_tx_timeout(struct net_device *dev)
1796 {
1797         struct amd8111e_priv* lp = netdev_priv(dev);
1798         int err;
1799
1800         printk(KERN_ERR "%s: transmit timed out, resetting\n",
1801                                                       dev->name);
1802         spin_lock_irq(&lp->lock);
1803         err = amd8111e_restart(dev);
1804         spin_unlock_irq(&lp->lock);
1805         if(!err)
1806                 netif_wake_queue(dev);
1807 }
1808 static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1809 {       
1810         struct net_device *dev = pci_get_drvdata(pci_dev);
1811         struct amd8111e_priv *lp = netdev_priv(dev);
1812         
1813         if (!netif_running(dev))
1814                 return 0;
1815
1816         /* disable the interrupt */
1817         spin_lock_irq(&lp->lock);
1818         amd8111e_disable_interrupt(lp);
1819         spin_unlock_irq(&lp->lock);
1820
1821         netif_device_detach(dev);
1822         
1823         /* stop chip */
1824         spin_lock_irq(&lp->lock);
1825         if(lp->options & OPTION_DYN_IPG_ENABLE)         
1826                 del_timer_sync(&lp->ipg_data.ipg_timer);
1827         amd8111e_stop_chip(lp);
1828         spin_unlock_irq(&lp->lock);
1829
1830         if(lp->options & OPTION_WOL_ENABLE){
1831                  /* enable wol */
1832                 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1833                         amd8111e_enable_magicpkt(lp);   
1834                 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1835                         amd8111e_enable_link_change(lp);        
1836                 
1837                 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1838                 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1839
1840         }
1841         else{           
1842                 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1843                 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1844         }
1845         
1846         pci_save_state(pci_dev);
1847         pci_set_power_state(pci_dev, PCI_D3hot);
1848
1849         return 0;
1850 }
1851 static int amd8111e_resume(struct pci_dev *pci_dev)
1852 {
1853         struct net_device *dev = pci_get_drvdata(pci_dev);
1854         struct amd8111e_priv *lp = netdev_priv(dev);
1855         
1856         if (!netif_running(dev))
1857                 return 0;
1858
1859         pci_set_power_state(pci_dev, PCI_D0);
1860         pci_restore_state(pci_dev);
1861
1862         pci_enable_wake(pci_dev, PCI_D3hot, 0);
1863         pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1864
1865         netif_device_attach(dev);
1866
1867         spin_lock_irq(&lp->lock);
1868         amd8111e_restart(dev);
1869         /* Restart ipg timer */
1870         if(lp->options & OPTION_DYN_IPG_ENABLE)         
1871                 mod_timer(&lp->ipg_data.ipg_timer, 
1872                                 jiffies + IPG_CONVERGE_JIFFIES);
1873         spin_unlock_irq(&lp->lock);
1874
1875         return 0;
1876 }
1877
1878
1879 static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1880 {
1881         struct net_device *dev = pci_get_drvdata(pdev);
1882         if (dev) {
1883                 unregister_netdev(dev);
1884                 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1885                 free_netdev(dev);
1886                 pci_release_regions(pdev);
1887                 pci_disable_device(pdev);
1888                 pci_set_drvdata(pdev, NULL);
1889         }
1890 }
1891 static void amd8111e_config_ipg(struct net_device* dev)
1892 {
1893         struct amd8111e_priv *lp = netdev_priv(dev);
1894         struct ipg_info* ipg_data = &lp->ipg_data;
1895         void __iomem *mmio = lp->mmio;
1896         unsigned int prev_col_cnt = ipg_data->col_cnt;
1897         unsigned int total_col_cnt;
1898         unsigned int tmp_ipg;
1899         
1900         if(lp->link_config.duplex == DUPLEX_FULL){
1901                 ipg_data->ipg = DEFAULT_IPG;
1902                 return;
1903         }
1904
1905         if(ipg_data->ipg_state == SSTATE){
1906                 
1907                 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1908                         
1909                         ipg_data->timer_tick = 0;
1910                         ipg_data->ipg = MIN_IPG - IPG_STEP;
1911                         ipg_data->current_ipg = MIN_IPG;
1912                         ipg_data->diff_col_cnt = 0xFFFFFFFF;
1913                         ipg_data->ipg_state = CSTATE;
1914                 }
1915                 else
1916                         ipg_data->timer_tick++;
1917         }
1918
1919         if(ipg_data->ipg_state == CSTATE){
1920                 
1921                 /* Get the current collision count */
1922
1923                 total_col_cnt = ipg_data->col_cnt = 
1924                                 amd8111e_read_mib(mmio, xmt_collisions);
1925
1926                 if ((total_col_cnt - prev_col_cnt) < 
1927                                 (ipg_data->diff_col_cnt)){
1928                         
1929                         ipg_data->diff_col_cnt =
1930                                 total_col_cnt - prev_col_cnt ;
1931
1932                         ipg_data->ipg = ipg_data->current_ipg;
1933                 }
1934
1935                 ipg_data->current_ipg += IPG_STEP;
1936
1937                 if (ipg_data->current_ipg <= MAX_IPG)
1938                         tmp_ipg = ipg_data->current_ipg;
1939                 else{
1940                         tmp_ipg = ipg_data->ipg;
1941                         ipg_data->ipg_state = SSTATE;
1942                 }
1943                 writew((u32)tmp_ipg, mmio + IPG); 
1944                 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1); 
1945         }
1946          mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1947         return;
1948
1949 }
1950
1951 static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1952 {
1953         struct amd8111e_priv *lp = netdev_priv(dev);
1954         int i;
1955
1956         for (i = 0x1e; i >= 0; i--) {
1957                 u32 id1, id2;
1958
1959                 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1960                         continue;
1961                 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1962                         continue;
1963                 lp->ext_phy_id = (id1 << 16) | id2;
1964                 lp->ext_phy_addr = i;
1965                 return;
1966         }
1967         lp->ext_phy_id = 0;
1968         lp->ext_phy_addr = 1;
1969 }
1970
1971 static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1972                                   const struct pci_device_id *ent)
1973 {
1974         int err,i,pm_cap;
1975         unsigned long reg_addr,reg_len;
1976         struct amd8111e_priv* lp;
1977         struct net_device* dev;
1978
1979         err = pci_enable_device(pdev);
1980         if(err){
1981                 printk(KERN_ERR "amd8111e: Cannot enable new PCI device,"
1982                         "exiting.\n");
1983                 return err;
1984         }
1985
1986         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1987                 printk(KERN_ERR "amd8111e: Cannot find PCI base address"
1988                        "exiting.\n");
1989                 err = -ENODEV;
1990                 goto err_disable_pdev;
1991         }
1992
1993         err = pci_request_regions(pdev, MODULE_NAME);
1994         if(err){
1995                 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1996                        "exiting.\n");
1997                 goto err_disable_pdev;
1998         }
1999
2000         pci_set_master(pdev);
2001
2002         /* Find power-management capability. */
2003         if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
2004                 printk(KERN_ERR "amd8111e: No Power Management capability, "
2005                        "exiting.\n");
2006                 goto err_free_reg;
2007         }
2008
2009         /* Initialize DMA */
2010         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) < 0) {
2011                 printk(KERN_ERR "amd8111e: DMA not supported,"
2012                         "exiting.\n");
2013                 goto err_free_reg;
2014         }
2015         
2016         reg_addr = pci_resource_start(pdev, 0);
2017         reg_len = pci_resource_len(pdev, 0);
2018
2019         dev = alloc_etherdev(sizeof(struct amd8111e_priv));
2020         if (!dev) {
2021                 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
2022                 err = -ENOMEM;
2023                 goto err_free_reg;
2024         }
2025
2026         SET_MODULE_OWNER(dev);
2027         SET_NETDEV_DEV(dev, &pdev->dev);
2028
2029 #if AMD8111E_VLAN_TAG_USED
2030         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
2031         dev->vlan_rx_register =amd8111e_vlan_rx_register;
2032         dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
2033 #endif  
2034         
2035         lp = netdev_priv(dev);
2036         lp->pci_dev = pdev;
2037         lp->amd8111e_net_dev = dev;
2038         lp->pm_cap = pm_cap;
2039
2040         spin_lock_init(&lp->lock);
2041
2042         lp->mmio = ioremap(reg_addr, reg_len);
2043         if (lp->mmio == 0) {
2044                 printk(KERN_ERR "amd8111e: Cannot map device registers, "
2045                        "exiting\n");
2046                 err = -ENOMEM;
2047                 goto err_free_dev;
2048         }
2049         
2050         /* Initializing MAC address */
2051         for(i = 0; i < ETH_ADDR_LEN; i++)
2052                         dev->dev_addr[i] =readb(lp->mmio + PADR + i);
2053         
2054         /* Setting user defined parametrs */
2055         lp->ext_phy_option = speed_duplex[card_idx];
2056         if(coalesce[card_idx])
2057                 lp->options |= OPTION_INTR_COAL_ENABLE;         
2058         if(dynamic_ipg[card_idx++])
2059                 lp->options |= OPTION_DYN_IPG_ENABLE;                   
2060
2061         /* Initialize driver entry points */
2062         dev->open = amd8111e_open;
2063         dev->hard_start_xmit = amd8111e_start_xmit;
2064         dev->stop = amd8111e_close;
2065         dev->get_stats = amd8111e_get_stats;
2066         dev->set_multicast_list = amd8111e_set_multicast_list;
2067         dev->set_mac_address = amd8111e_set_mac_address;
2068         dev->do_ioctl = amd8111e_ioctl;
2069         dev->change_mtu = amd8111e_change_mtu;
2070         SET_ETHTOOL_OPS(dev, &ops);
2071         dev->irq =pdev->irq;
2072         dev->tx_timeout = amd8111e_tx_timeout; 
2073         dev->watchdog_timeo = AMD8111E_TX_TIMEOUT; 
2074 #ifdef CONFIG_AMD8111E_NAPI
2075         dev->poll = amd8111e_rx_poll;
2076         dev->weight = 32;
2077 #endif
2078 #ifdef CONFIG_NET_POLL_CONTROLLER
2079         dev->poll_controller = amd8111e_poll; 
2080 #endif
2081
2082 #if AMD8111E_VLAN_TAG_USED
2083         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2084         dev->vlan_rx_register =amd8111e_vlan_rx_register;
2085         dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
2086 #endif  
2087         /* Probe the external PHY */
2088         amd8111e_probe_ext_phy(dev);
2089
2090         /* setting mii default values */
2091         lp->mii_if.dev = dev;
2092         lp->mii_if.mdio_read = amd8111e_mdio_read;
2093         lp->mii_if.mdio_write = amd8111e_mdio_write;
2094         lp->mii_if.phy_id = lp->ext_phy_addr;
2095
2096         /* Set receive buffer length and set jumbo option*/
2097         amd8111e_set_rx_buff_len(dev);
2098
2099
2100         err = register_netdev(dev);
2101         if (err) {
2102                 printk(KERN_ERR "amd8111e: Cannot register net device, "
2103                        "exiting.\n");
2104                 goto err_iounmap;
2105         }
2106
2107         pci_set_drvdata(pdev, dev);
2108         
2109         /* Initialize software ipg timer */
2110         if(lp->options & OPTION_DYN_IPG_ENABLE){                
2111                 init_timer(&lp->ipg_data.ipg_timer);
2112                 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
2113                 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
2114                 lp->ipg_data.ipg_timer.expires = jiffies + 
2115                                                  IPG_CONVERGE_JIFFIES;
2116                 lp->ipg_data.ipg = DEFAULT_IPG;
2117                 lp->ipg_data.ipg_state = CSTATE;
2118         };
2119
2120         /*  display driver and device information */
2121
2122         chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
2123         printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n",                                                           dev->name,MODULE_VERS);
2124         printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet ",                                                    dev->name, chip_version);
2125         for (i = 0; i < 6; i++)
2126                 printk("%2.2x%c",dev->dev_addr[i],i == 5 ? ' ' : ':');
2127         printk( "\n");  
2128         if (lp->ext_phy_id)
2129                 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
2130                        dev->name, lp->ext_phy_id, lp->ext_phy_addr);
2131         else
2132                 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
2133                        dev->name);
2134         return 0;
2135 err_iounmap:
2136         iounmap(lp->mmio);
2137
2138 err_free_dev:
2139         free_netdev(dev);
2140
2141 err_free_reg:
2142         pci_release_regions(pdev);
2143
2144 err_disable_pdev:
2145         pci_disable_device(pdev);
2146         pci_set_drvdata(pdev, NULL);
2147         return err;
2148
2149 }
2150
2151 static struct pci_driver amd8111e_driver = {
2152         .name           = MODULE_NAME,
2153         .id_table       = amd8111e_pci_tbl,
2154         .probe          = amd8111e_probe_one,
2155         .remove         = __devexit_p(amd8111e_remove_one),
2156         .suspend        = amd8111e_suspend,
2157         .resume         = amd8111e_resume
2158 };
2159
2160 static int __init amd8111e_init(void)
2161 {
2162         return pci_module_init(&amd8111e_driver);
2163 }
2164
2165 static void __exit amd8111e_cleanup(void)
2166 {
2167         pci_unregister_driver(&amd8111e_driver);
2168 }
2169
2170 module_init(amd8111e_init);
2171 module_exit(amd8111e_cleanup);