drivers/net/amd8111e.c

   1
   2 /* Advanced  Micro Devices Inc. AMD8111E Linux Network Driver
   3  * Copyright (C) 2004 Advanced Micro Devices
   4  *
   5  *
   6  * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
   7  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
   8  * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
   9  * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
  10  * Copyright 1993 United States Government as represented by the
  11  *      Director, National Security Agency.[ pcnet32.c ]
  12  * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
  13  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  14  *
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
  29  * USA
  30
  31 Module Name:
  32
  33         amd8111e.c
  34
  35 Abstract:
  36
  37          AMD8111 based 10/100 Ethernet Controller Driver.
  38
  39 Environment:
  40
  41         Kernel Mode
  42
  43 Revision History:
  44         3.0.0
  45            Initial Revision.
  46         3.0.1
  47          1. Dynamic interrupt coalescing.
  48          2. Removed prev_stats.
  49          3. MII support.
  50          4. Dynamic IPG support
  51         3.0.2  05/29/2003
  52          1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
  53          2. Bug fix: Fixed VLAN support failure.
  54          3. Bug fix: Fixed receive interrupt coalescing bug.
  55          4. Dynamic IPG support is disabled by default.
  56         3.0.3 06/05/2003
  57          1. Bug fix: Fixed failure to close the interface if SMP is enabled.
  58         3.0.4 12/09/2003
  59          1. Added set_mac_address routine for bonding driver support.
  60          2. Tested the driver for bonding support
  61          3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
  62             indicated to the h/w.
  63          4. Modified amd8111e_rx() routine to receive all the received packets
  64             in the first interrupt.
  65          5. Bug fix: Corrected  rx_errors  reported in get_stats() function.
  66         3.0.5 03/22/2004
  67          1. Added NAPI support
  68
  69 */
  70
  71
  72 #include <linux/module.h>
  73 #include <linux/kernel.h>
  74 #include <linux/types.h>
  75 #include <linux/compiler.h>
  76 #include <linux/delay.h>
  77 #include <linux/init.h>
  78 #include <linux/ioport.h>
  79 #include <linux/pci.h>
  80 #include <linux/netdevice.h>
  81 #include <linux/etherdevice.h>
  82 #include <linux/skbuff.h>
  83 #include <linux/ethtool.h>
  84 #include <linux/mii.h>
  85 #include <linux/if_vlan.h>
  86 #include <linux/ctype.h>
  87 #include <linux/crc32.h>
  88 #include <linux/dma-mapping.h>
  89
  90 #include <asm/system.h>
  91 #include <asm/io.h>
  92 #include <asm/byteorder.h>
  93 #include <asm/uaccess.h>
  94
  95 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  96 #define AMD8111E_VLAN_TAG_USED 1
  97 #else
  98 #define AMD8111E_VLAN_TAG_USED 0
  99 #endif
 100
 101 #include "amd8111e.h"
 102 #define MODULE_NAME     "amd8111e"
 103 #define MODULE_VERS     "3.0.7"
 104 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
 105 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS);
 106 MODULE_LICENSE("GPL");
 107 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
 108 module_param_array(speed_duplex, int, NULL, 0);
 109 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
 110 module_param_array(coalesce, bool, NULL, 0);
 111 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
 112 module_param_array(dynamic_ipg, bool, NULL, 0);
 113 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
 114
 115 static DEFINE_PCI_DEVICE_TABLE(amd8111e_pci_tbl) = {
 116
 117         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
 118          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 119         { 0, }
 120
 121 };
 122 /*
 123 This function will read the PHY registers.
 124 */
 125 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
 126 {
 127         void __iomem *mmio = lp->mmio;
 128         unsigned int reg_val;
 129         unsigned int repeat= REPEAT_CNT;
 130
 131         reg_val = readl(mmio + PHY_ACCESS);
 132         while (reg_val & PHY_CMD_ACTIVE)
 133                 reg_val = readl( mmio + PHY_ACCESS );
 134
 135         writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
 136                            ((reg & 0x1f) << 16),  mmio +PHY_ACCESS);
 137         do{
 138                 reg_val = readl(mmio + PHY_ACCESS);
 139                 udelay(30);  /* It takes 30 us to read/write data */
 140         } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
 141         if(reg_val & PHY_RD_ERR)
 142                 goto err_phy_read;
 143
 144         *val = reg_val & 0xffff;
 145         return 0;
 146 err_phy_read:
 147         *val = 0;
 148         return -EINVAL;
 149
 150 }
 151
 152 /*
 153 This function will write into PHY registers.
 154 */
 155 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
 156 {
 157         unsigned int repeat = REPEAT_CNT;
 158         void __iomem *mmio = lp->mmio;
 159         unsigned int reg_val;
 160
 161         reg_val = readl(mmio + PHY_ACCESS);
 162         while (reg_val & PHY_CMD_ACTIVE)
 163                 reg_val = readl( mmio + PHY_ACCESS );
 164
 165         writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
 166                            ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
 167
 168         do{
 169                 reg_val = readl(mmio + PHY_ACCESS);
 170                 udelay(30);  /* It takes 30 us to read/write the data */
 171         } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
 172
 173         if(reg_val & PHY_RD_ERR)
 174                 goto err_phy_write;
 175
 176         return 0;
 177
 178 err_phy_write:
 179         return -EINVAL;
 180
 181 }
 182 /*
 183 This is the mii register read function provided to the mii interface.
 184 */
 185 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
 186 {
 187         struct amd8111e_priv* lp = netdev_priv(dev);
 188         unsigned int reg_val;
 189
 190         amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
 191         return reg_val;
 192
 193 }
 194
 195 /*
 196 This is the mii register write function provided to the mii interface.
 197 */
 198 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
 199 {
 200         struct amd8111e_priv* lp = netdev_priv(dev);
 201
 202         amd8111e_write_phy(lp, phy_id, reg_num, val);
 203 }
 204
 205 /*
 206 This function will set PHY speed. During initialization sets the original speed to 100 full.
 207 */
 208 static void amd8111e_set_ext_phy(struct net_device *dev)
 209 {
 210         struct amd8111e_priv *lp = netdev_priv(dev);
 211         u32 bmcr,advert,tmp;
 212
 213         /* Determine mii register values to set the speed */
 214         advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
 215         tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
 216         switch (lp->ext_phy_option){
 217
 218                 default:
 219                 case SPEED_AUTONEG: /* advertise all values */
 220                         tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
 221                                 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
 222                         break;
 223                 case SPEED10_HALF:
 224                         tmp |= ADVERTISE_10HALF;
 225                         break;
 226                 case SPEED10_FULL:
 227                         tmp |= ADVERTISE_10FULL;
 228                         break;
 229                 case SPEED100_HALF:
 230                         tmp |= ADVERTISE_100HALF;
 231                         break;
 232                 case SPEED100_FULL:
 233                         tmp |= ADVERTISE_100FULL;
 234                         break;
 235         }
 236
 237         if(advert != tmp)
 238                 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
 239         /* Restart auto negotiation */
 240         bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
 241         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
 242         amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
 243
 244 }
 245
 246 /*
 247 This function will unmap skb->data space and will free
 248 all transmit and receive skbuffs.
 249 */
 250 static int amd8111e_free_skbs(struct net_device *dev)
 251 {
 252         struct amd8111e_priv *lp = netdev_priv(dev);
 253         struct sk_buff* rx_skbuff;
 254         int i;
 255
 256         /* Freeing transmit skbs */
 257         for(i = 0; i < NUM_TX_BUFFERS; i++){
 258                 if(lp->tx_skbuff[i]){
 259                         pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i],                                        lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
 260                         dev_kfree_skb (lp->tx_skbuff[i]);
 261                         lp->tx_skbuff[i] = NULL;
 262                         lp->tx_dma_addr[i] = 0;
 263                 }
 264         }
 265         /* Freeing previously allocated receive buffers */
 266         for (i = 0; i < NUM_RX_BUFFERS; i++){
 267                 rx_skbuff = lp->rx_skbuff[i];
 268                 if(rx_skbuff != NULL){
 269                         pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
 270                                   lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
 271                         dev_kfree_skb(lp->rx_skbuff[i]);
 272                         lp->rx_skbuff[i] = NULL;
 273                         lp->rx_dma_addr[i] = 0;
 274                 }
 275         }
 276
 277         return 0;
 278 }
 279
 280 /*
 281 This will set the receive buffer length corresponding to the mtu size of networkinterface.
 282 */
 283 static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
 284 {
 285         struct amd8111e_priv* lp = netdev_priv(dev);
 286         unsigned int mtu = dev->mtu;
 287
 288         if (mtu > ETH_DATA_LEN){
 289                 /* MTU + ethernet header + FCS
 290                 + optional VLAN tag + skb reserve space 2 */
 291
 292                 lp->rx_buff_len = mtu + ETH_HLEN + 10;
 293                 lp->options |= OPTION_JUMBO_ENABLE;
 294         } else{
 295                 lp->rx_buff_len = PKT_BUFF_SZ;
 296                 lp->options &= ~OPTION_JUMBO_ENABLE;
 297         }
 298 }
 299
 300 /*
 301 This function will free all the previously allocated buffers, determine new receive buffer length  and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
 302  */
 303 static int amd8111e_init_ring(struct net_device *dev)
 304 {
 305         struct amd8111e_priv *lp = netdev_priv(dev);
 306         int i;
 307
 308         lp->rx_idx = lp->tx_idx = 0;
 309         lp->tx_complete_idx = 0;
 310         lp->tx_ring_idx = 0;
 311
 312
 313         if(lp->opened)
 314                 /* Free previously allocated transmit and receive skbs */
 315                 amd8111e_free_skbs(dev);
 316
 317         else{
 318                  /* allocate the tx and rx descriptors */
 319                 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
 320                         sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
 321                         &lp->tx_ring_dma_addr)) == NULL)
 322
 323                         goto err_no_mem;
 324
 325                 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
 326                         sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
 327                         &lp->rx_ring_dma_addr)) == NULL)
 328
 329                         goto err_free_tx_ring;
 330
 331         }
 332         /* Set new receive buff size */
 333         amd8111e_set_rx_buff_len(dev);
 334
 335         /* Allocating receive  skbs */
 336         for (i = 0; i < NUM_RX_BUFFERS; i++) {
 337
 338                 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
 339                                 /* Release previos allocated skbs */
 340                                 for(--i; i >= 0 ;i--)
 341                                         dev_kfree_skb(lp->rx_skbuff[i]);
 342                                 goto err_free_rx_ring;
 343                 }
 344                 skb_reserve(lp->rx_skbuff[i],2);
 345         }
 346         /* Initilaizing receive descriptors */
 347         for (i = 0; i < NUM_RX_BUFFERS; i++) {
 348                 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
 349                         lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
 350
 351                 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
 352                 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
 353                 wmb();
 354                 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
 355         }
 356
 357         /* Initializing transmit descriptors */
 358         for (i = 0; i < NUM_TX_RING_DR; i++) {
 359                 lp->tx_ring[i].buff_phy_addr = 0;
 360                 lp->tx_ring[i].tx_flags = 0;
 361                 lp->tx_ring[i].buff_count = 0;
 362         }
 363
 364         return 0;
 365
 366 err_free_rx_ring:
 367
 368         pci_free_consistent(lp->pci_dev,
 369                 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
 370                 lp->rx_ring_dma_addr);
 371
 372 err_free_tx_ring:
 373
 374         pci_free_consistent(lp->pci_dev,
 375                  sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
 376                  lp->tx_ring_dma_addr);
 377
 378 err_no_mem:
 379         return -ENOMEM;
 380 }
 381 /* This function will set the interrupt coalescing according to the input arguments */
 382 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
 383 {
 384         unsigned int timeout;
 385         unsigned int event_count;
 386
 387         struct amd8111e_priv *lp = netdev_priv(dev);
 388         void __iomem *mmio = lp->mmio;
 389         struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
 390
 391
 392         switch(cmod)
 393         {
 394                 case RX_INTR_COAL :
 395                         timeout = coal_conf->rx_timeout;
 396                         event_count = coal_conf->rx_event_count;
 397                         if( timeout > MAX_TIMEOUT ||
 398                                         event_count > MAX_EVENT_COUNT )
 399                                 return -EINVAL;
 400
 401                         timeout = timeout * DELAY_TIMER_CONV;
 402                         writel(VAL0|STINTEN, mmio+INTEN0);
 403                         writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
 404                                                         mmio+DLY_INT_A);
 405                         break;
 406
 407                 case TX_INTR_COAL :
 408                         timeout = coal_conf->tx_timeout;
 409                         event_count = coal_conf->tx_event_count;
 410                         if( timeout > MAX_TIMEOUT ||
 411                                         event_count > MAX_EVENT_COUNT )
 412                                 return -EINVAL;
 413
 414
 415                         timeout = timeout * DELAY_TIMER_CONV;
 416                         writel(VAL0|STINTEN,mmio+INTEN0);
 417                         writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
 418                                                          mmio+DLY_INT_B);
 419                         break;
 420
 421                 case DISABLE_COAL:
 422                         writel(0,mmio+STVAL);
 423                         writel(STINTEN, mmio+INTEN0);
 424                         writel(0, mmio +DLY_INT_B);
 425                         writel(0, mmio+DLY_INT_A);
 426                         break;
 427                  case ENABLE_COAL:
 428                        /* Start the timer */
 429                         writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /*  0.5 sec */
 430                         writel(VAL0|STINTEN, mmio+INTEN0);
 431                         break;
 432                 default:
 433                         break;
 434
 435    }
 436         return 0;
 437
 438 }
 439
 440 /*
 441 This function initializes the device registers  and starts the device.
 442 */
 443 static int amd8111e_restart(struct net_device *dev)
 444 {
 445         struct amd8111e_priv *lp = netdev_priv(dev);
 446         void __iomem *mmio = lp->mmio;
 447         int i,reg_val;
 448
 449         /* stop the chip */
 450          writel(RUN, mmio + CMD0);
 451
 452         if(amd8111e_init_ring(dev))
 453                 return -ENOMEM;
 454
 455         /* enable the port manager and set auto negotiation always */
 456         writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
 457         writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
 458
 459         amd8111e_set_ext_phy(dev);
 460
 461         /* set control registers */
 462         reg_val = readl(mmio + CTRL1);
 463         reg_val &= ~XMTSP_MASK;
 464         writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
 465
 466         /* enable interrupt */
 467         writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
 468                 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
 469                 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
 470
 471         writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
 472
 473         /* initialize tx and rx ring base addresses */
 474         writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
 475         writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
 476
 477         writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
 478         writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
 479
 480         /* set default IPG to 96 */
 481         writew((u32)DEFAULT_IPG,mmio+IPG);
 482         writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
 483
 484         if(lp->options & OPTION_JUMBO_ENABLE){
 485                 writel((u32)VAL2|JUMBO, mmio + CMD3);
 486                 /* Reset REX_UFLO */
 487                 writel( REX_UFLO, mmio + CMD2);
 488                 /* Should not set REX_UFLO for jumbo frames */
 489                 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
 490         }else{
 491                 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
 492                 writel((u32)JUMBO, mmio + CMD3);
 493         }
 494
 495 #if AMD8111E_VLAN_TAG_USED
 496         writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
 497 #endif
 498         writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
 499
 500         /* Setting the MAC address to the device */
 501         for(i = 0; i < ETH_ADDR_LEN; i++)
 502                 writeb( dev->dev_addr[i], mmio + PADR + i );
 503
 504         /* Enable interrupt coalesce */
 505         if(lp->options & OPTION_INTR_COAL_ENABLE){
 506                 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
 507                                                                 dev->name);
 508                 amd8111e_set_coalesce(dev,ENABLE_COAL);
 509         }
 510
 511         /* set RUN bit to start the chip */
 512         writel(VAL2 | RDMD0, mmio + CMD0);
 513         writel(VAL0 | INTREN | RUN, mmio + CMD0);
 514
 515         /* To avoid PCI posting bug */
 516         readl(mmio+CMD0);
 517         return 0;
 518 }
 519 /*
 520 This function clears necessary the device registers.
 521 */
 522 static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
 523 {
 524         unsigned int reg_val;
 525         unsigned int logic_filter[2] ={0,};
 526         void __iomem *mmio = lp->mmio;
 527
 528
 529         /* stop the chip */
 530         writel(RUN, mmio + CMD0);
 531
 532         /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
 533         writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
 534
 535         /* Clear RCV_RING_BASE_ADDR */
 536         writel(0, mmio + RCV_RING_BASE_ADDR0);
 537
 538         /* Clear XMT_RING_BASE_ADDR */
 539         writel(0, mmio + XMT_RING_BASE_ADDR0);
 540         writel(0, mmio + XMT_RING_BASE_ADDR1);
 541         writel(0, mmio + XMT_RING_BASE_ADDR2);
 542         writel(0, mmio + XMT_RING_BASE_ADDR3);
 543
 544         /* Clear CMD0  */
 545         writel(CMD0_CLEAR,mmio + CMD0);
 546
 547         /* Clear CMD2 */
 548         writel(CMD2_CLEAR, mmio +CMD2);
 549
 550         /* Clear CMD7 */
 551         writel(CMD7_CLEAR , mmio + CMD7);
 552
 553         /* Clear DLY_INT_A and DLY_INT_B */
 554         writel(0x0, mmio + DLY_INT_A);
 555         writel(0x0, mmio + DLY_INT_B);
 556
 557         /* Clear FLOW_CONTROL */
 558         writel(0x0, mmio + FLOW_CONTROL);
 559
 560         /* Clear INT0  write 1 to clear register */
 561         reg_val = readl(mmio + INT0);
 562         writel(reg_val, mmio + INT0);
 563
 564         /* Clear STVAL */
 565         writel(0x0, mmio + STVAL);
 566
 567         /* Clear INTEN0 */
 568         writel( INTEN0_CLEAR, mmio + INTEN0);
 569
 570         /* Clear LADRF */
 571         writel(0x0 , mmio + LADRF);
 572
 573         /* Set SRAM_SIZE & SRAM_BOUNDARY registers  */
 574         writel( 0x80010,mmio + SRAM_SIZE);
 575
 576         /* Clear RCV_RING0_LEN */
 577         writel(0x0, mmio +  RCV_RING_LEN0);
 578
 579         /* Clear XMT_RING0/1/2/3_LEN */
 580         writel(0x0, mmio +  XMT_RING_LEN0);
 581         writel(0x0, mmio +  XMT_RING_LEN1);
 582         writel(0x0, mmio +  XMT_RING_LEN2);
 583         writel(0x0, mmio +  XMT_RING_LEN3);
 584
 585         /* Clear XMT_RING_LIMIT */
 586         writel(0x0, mmio + XMT_RING_LIMIT);
 587
 588         /* Clear MIB */
 589         writew(MIB_CLEAR, mmio + MIB_ADDR);
 590
 591         /* Clear LARF */
 592         amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
 593
 594         /* SRAM_SIZE register */
 595         reg_val = readl(mmio + SRAM_SIZE);
 596
 597         if(lp->options & OPTION_JUMBO_ENABLE)
 598                 writel( VAL2|JUMBO, mmio + CMD3);
 599 #if AMD8111E_VLAN_TAG_USED
 600         writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
 601 #endif
 602         /* Set default value to CTRL1 Register */
 603         writel(CTRL1_DEFAULT, mmio + CTRL1);
 604
 605         /* To avoid PCI posting bug */
 606         readl(mmio + CMD2);
 607
 608 }
 609
 610 /*
 611 This function disables the interrupt and clears all the pending
 612 interrupts in INT0
 613  */
 614 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
 615 {
 616         u32 intr0;
 617
 618         /* Disable interrupt */
 619         writel(INTREN, lp->mmio + CMD0);
 620
 621         /* Clear INT0 */
 622         intr0 = readl(lp->mmio + INT0);
 623         writel(intr0, lp->mmio + INT0);
 624
 625         /* To avoid PCI posting bug */
 626         readl(lp->mmio + INT0);
 627
 628 }
 629
 630 /*
 631 This function stops the chip.
 632 */
 633 static void amd8111e_stop_chip(struct amd8111e_priv* lp)
 634 {
 635         writel(RUN, lp->mmio + CMD0);
 636
 637         /* To avoid PCI posting bug */
 638         readl(lp->mmio + CMD0);
 639 }
 640
 641 /*
 642 This function frees the  transmiter and receiver descriptor rings.
 643 */
 644 static void amd8111e_free_ring(struct amd8111e_priv* lp)
 645 {
 646         /* Free transmit and receive descriptor rings */
 647         if(lp->rx_ring){
 648                 pci_free_consistent(lp->pci_dev,
 649                         sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
 650                         lp->rx_ring, lp->rx_ring_dma_addr);
 651                 lp->rx_ring = NULL;
 652         }
 653
 654         if(lp->tx_ring){
 655                 pci_free_consistent(lp->pci_dev,
 656                         sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
 657                         lp->tx_ring, lp->tx_ring_dma_addr);
 658
 659                 lp->tx_ring = NULL;
 660         }
 661
 662 }
 663 #if AMD8111E_VLAN_TAG_USED
 664 /*
 665 This is the receive indication function for packets with vlan tag.
 666 */
 667 static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
 668 {
 669         return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
 670 }
 671 #endif
 672
 673 /*
 674 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
 675 */
 676 static int amd8111e_tx(struct net_device *dev)
 677 {
 678         struct amd8111e_priv* lp = netdev_priv(dev);
 679         int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
 680         int status;
 681         /* Complete all the transmit packet */
 682         while (lp->tx_complete_idx != lp->tx_idx){
 683                 tx_index =  lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
 684                 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
 685
 686                 if(status & OWN_BIT)
 687                         break;  /* It still hasn't been Txed */
 688
 689                 lp->tx_ring[tx_index].buff_phy_addr = 0;
 690
 691                 /* We must free the original skb */
 692                 if (lp->tx_skbuff[tx_index]) {
 693                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
 694                                         lp->tx_skbuff[tx_index]->len,
 695                                         PCI_DMA_TODEVICE);
 696                         dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
 697                         lp->tx_skbuff[tx_index] = NULL;
 698                         lp->tx_dma_addr[tx_index] = 0;
 699                 }
 700                 lp->tx_complete_idx++;
 701                 /*COAL update tx coalescing parameters */
 702                 lp->coal_conf.tx_packets++;
 703                 lp->coal_conf.tx_bytes +=
 704                         le16_to_cpu(lp->tx_ring[tx_index].buff_count);
 705
 706                 if (netif_queue_stopped(dev) &&
 707                         lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
 708                         /* The ring is no longer full, clear tbusy. */
 709                         /* lp->tx_full = 0; */
 710                         netif_wake_queue (dev);
 711                 }
 712         }
 713         return 0;
 714 }
 715
 716 /* This function handles the driver receive operation in polling mode */
 717 static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
 718 {
 719         struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
 720         struct net_device *dev = lp->amd8111e_net_dev;
 721         int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
 722         void __iomem *mmio = lp->mmio;
 723         struct sk_buff *skb,*new_skb;
 724         int min_pkt_len, status;
 725         unsigned int intr0;
 726         int num_rx_pkt = 0;
 727         short pkt_len;
 728 #if AMD8111E_VLAN_TAG_USED
 729         short vtag;
 730 #endif
 731         int rx_pkt_limit = budget;
 732         unsigned long flags;
 733
 734         do{
 735                 /* process receive packets until we use the quota*/
 736                 /* If we own the next entry, it's a new packet. Send it up. */
 737                 while(1) {
 738                         status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
 739                         if (status & OWN_BIT)
 740                                 break;
 741
 742                         /*
 743                          * There is a tricky error noted by John Murphy,
 744                          * <murf@perftech.com> to Russ Nelson: Even with
 745                          * full-sized * buffers it's possible for a
 746                          * jabber packet to use two buffers, with only
 747                          * the last correctly noting the error.
 748                          */
 749
 750                         if(status & ERR_BIT) {
 751                                 /* reseting flags */
 752                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 753                                 goto err_next_pkt;
 754                         }
 755                         /* check for STP and ENP */
 756                         if(!((status & STP_BIT) && (status & ENP_BIT))){
 757                                 /* reseting flags */
 758                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 759                                 goto err_next_pkt;
 760                         }
 761                         pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
 762
 763 #if AMD8111E_VLAN_TAG_USED
 764                         vtag = status & TT_MASK;
 765                         /*MAC will strip vlan tag*/
 766                         if(lp->vlgrp != NULL && vtag !=0)
 767                                 min_pkt_len =MIN_PKT_LEN - 4;
 768                         else
 769 #endif
 770                                 min_pkt_len =MIN_PKT_LEN;
 771
 772                         if (pkt_len < min_pkt_len) {
 773                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 774                                 lp->drv_rx_errors++;
 775                                 goto err_next_pkt;
 776                         }
 777                         if(--rx_pkt_limit < 0)
 778                                 goto rx_not_empty;
 779                         if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
 780                                 /* if allocation fail,
 781                                    ignore that pkt and go to next one */
 782                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 783                                 lp->drv_rx_errors++;
 784                                 goto err_next_pkt;
 785                         }
 786
 787                         skb_reserve(new_skb, 2);
 788                         skb = lp->rx_skbuff[rx_index];
 789                         pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
 790                                          lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
 791                         skb_put(skb, pkt_len);
 792                         lp->rx_skbuff[rx_index] = new_skb;
 793                         lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
 794                                                                    new_skb->data,
 795                                                                    lp->rx_buff_len-2,
 796                                                                    PCI_DMA_FROMDEVICE);
 797
 798                         skb->protocol = eth_type_trans(skb, dev);
 799
 800 #if AMD8111E_VLAN_TAG_USED
 801                         if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
 802                                 amd8111e_vlan_rx(lp, skb,
 803                                          le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
 804                         } else
 805 #endif
 806                                 netif_receive_skb(skb);
 807                         /*COAL update rx coalescing parameters*/
 808                         lp->coal_conf.rx_packets++;
 809                         lp->coal_conf.rx_bytes += pkt_len;
 810                         num_rx_pkt++;
 811
 812                 err_next_pkt:
 813                         lp->rx_ring[rx_index].buff_phy_addr
 814                                 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
 815                         lp->rx_ring[rx_index].buff_count =
 816                                 cpu_to_le16(lp->rx_buff_len-2);
 817                         wmb();
 818                         lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
 819                         rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
 820                 }
 821                 /* Check the interrupt status register for more packets in the
 822                    mean time. Process them since we have not used up our quota.*/
 823
 824                 intr0 = readl(mmio + INT0);
 825                 /*Ack receive packets */
 826                 writel(intr0 & RINT0,mmio + INT0);
 827
 828         } while(intr0 & RINT0);
 829
 830         if (rx_pkt_limit > 0) {
 831                 /* Receive descriptor is empty now */
 832                 spin_lock_irqsave(&lp->lock, flags);
 833                 __napi_complete(napi);
 834                 writel(VAL0|RINTEN0, mmio + INTEN0);
 835                 writel(VAL2 | RDMD0, mmio + CMD0);
 836                 spin_unlock_irqrestore(&lp->lock, flags);
 837         }
 838
 839 rx_not_empty:
 840         return num_rx_pkt;
 841 }
 842
 843 /*
 844 This function will indicate the link status to the kernel.
 845 */
 846 static int amd8111e_link_change(struct net_device* dev)
 847 {
 848         struct amd8111e_priv *lp = netdev_priv(dev);
 849         int status0,speed;
 850
 851         /* read the link change */
 852         status0 = readl(lp->mmio + STAT0);
 853
 854         if(status0 & LINK_STATS){
 855                 if(status0 & AUTONEG_COMPLETE)
 856                         lp->link_config.autoneg = AUTONEG_ENABLE;
 857                 else
 858                         lp->link_config.autoneg = AUTONEG_DISABLE;
 859
 860                 if(status0 & FULL_DPLX)
 861                         lp->link_config.duplex = DUPLEX_FULL;
 862                 else
 863                         lp->link_config.duplex = DUPLEX_HALF;
 864                 speed = (status0 & SPEED_MASK) >> 7;
 865                 if(speed == PHY_SPEED_10)
 866                         lp->link_config.speed = SPEED_10;
 867                 else if(speed == PHY_SPEED_100)
 868                         lp->link_config.speed = SPEED_100;
 869
 870                 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n",                        dev->name,
 871                        (lp->link_config.speed == SPEED_100) ? "100": "10",
 872                        (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
 873                 netif_carrier_on(dev);
 874         }
 875         else{
 876                 lp->link_config.speed = SPEED_INVALID;
 877                 lp->link_config.duplex = DUPLEX_INVALID;
 878                 lp->link_config.autoneg = AUTONEG_INVALID;
 879                 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
 880                 netif_carrier_off(dev);
 881         }
 882
 883         return 0;
 884 }
 885 /*
 886 This function reads the mib counters.
 887 */
 888 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
 889 {
 890         unsigned int  status;
 891         unsigned  int data;
 892         unsigned int repeat = REPEAT_CNT;
 893
 894         writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
 895         do {
 896                 status = readw(mmio + MIB_ADDR);
 897                 udelay(2);      /* controller takes MAX 2 us to get mib data */
 898         }
 899         while (--repeat && (status & MIB_CMD_ACTIVE));
 900
 901         data = readl(mmio + MIB_DATA);
 902         return data;
 903 }
 904
 905 /*
 906  * This function reads the mib registers and returns the hardware statistics.
 907  * It updates previous internal driver statistics with new values.
 908  */
 909 static struct net_device_stats *amd8111e_get_stats(struct net_device *dev)
 910 {
 911         struct amd8111e_priv *lp = netdev_priv(dev);
 912         void __iomem *mmio = lp->mmio;
 913         unsigned long flags;
 914         struct net_device_stats *new_stats = &dev->stats;
 915
 916         if (!lp->opened)
 917                 return new_stats;
 918         spin_lock_irqsave (&lp->lock, flags);
 919
 920         /* stats.rx_packets */
 921         new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
 922                                 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
 923                                 amd8111e_read_mib(mmio, rcv_unicast_pkts);
 924
 925         /* stats.tx_packets */
 926         new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
 927
 928         /*stats.rx_bytes */
 929         new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
 930
 931         /* stats.tx_bytes */
 932         new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
 933
 934         /* stats.rx_errors */
 935         /* hw errors + errors driver reported */
 936         new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
 937                                 amd8111e_read_mib(mmio, rcv_fragments)+
 938                                 amd8111e_read_mib(mmio, rcv_jabbers)+
 939                                 amd8111e_read_mib(mmio, rcv_alignment_errors)+
 940                                 amd8111e_read_mib(mmio, rcv_fcs_errors)+
 941                                 amd8111e_read_mib(mmio, rcv_miss_pkts)+
 942                                 lp->drv_rx_errors;
 943
 944         /* stats.tx_errors */
 945         new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
 946
 947         /* stats.rx_dropped*/
 948         new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
 949
 950         /* stats.tx_dropped*/
 951         new_stats->tx_dropped = amd8111e_read_mib(mmio,  xmt_underrun_pkts);
 952
 953         /* stats.multicast*/
 954         new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
 955
 956         /* stats.collisions*/
 957         new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
 958
 959         /* stats.rx_length_errors*/
 960         new_stats->rx_length_errors =
 961                 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
 962                 amd8111e_read_mib(mmio, rcv_oversize_pkts);
 963
 964         /* stats.rx_over_errors*/
 965         new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
 966
 967         /* stats.rx_crc_errors*/
 968         new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
 969
 970         /* stats.rx_frame_errors*/
 971         new_stats->rx_frame_errors =
 972                 amd8111e_read_mib(mmio, rcv_alignment_errors);
 973
 974         /* stats.rx_fifo_errors */
 975         new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
 976
 977         /* stats.rx_missed_errors */
 978         new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
 979
 980         /* stats.tx_aborted_errors*/
 981         new_stats->tx_aborted_errors =
 982                 amd8111e_read_mib(mmio, xmt_excessive_collision);
 983
 984         /* stats.tx_carrier_errors*/
 985         new_stats->tx_carrier_errors =
 986                 amd8111e_read_mib(mmio, xmt_loss_carrier);
 987
 988         /* stats.tx_fifo_errors*/
 989         new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
 990
 991         /* stats.tx_window_errors*/
 992         new_stats->tx_window_errors =
 993                 amd8111e_read_mib(mmio, xmt_late_collision);
 994
 995         /* Reset the mibs for collecting new statistics */
 996         /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
 997
 998         spin_unlock_irqrestore (&lp->lock, flags);
 999
1000         return new_stats;
1001 }
1002 /* This function recalculate the interrupt coalescing  mode on every interrupt
1003 according to the datarate and the packet rate.
1004 */
1005 static int amd8111e_calc_coalesce(struct net_device *dev)
1006 {
1007         struct amd8111e_priv *lp = netdev_priv(dev);
1008         struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1009         int tx_pkt_rate;
1010         int rx_pkt_rate;
1011         int tx_data_rate;
1012         int rx_data_rate;
1013         int rx_pkt_size;
1014         int tx_pkt_size;
1015
1016         tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1017         coal_conf->tx_prev_packets =  coal_conf->tx_packets;
1018
1019         tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1020         coal_conf->tx_prev_bytes =  coal_conf->tx_bytes;
1021
1022         rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1023         coal_conf->rx_prev_packets =  coal_conf->rx_packets;
1024
1025         rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1026         coal_conf->rx_prev_bytes =  coal_conf->rx_bytes;
1027
1028         if(rx_pkt_rate < 800){
1029                 if(coal_conf->rx_coal_type != NO_COALESCE){
1030
1031                         coal_conf->rx_timeout = 0x0;
1032                         coal_conf->rx_event_count = 0;
1033                         amd8111e_set_coalesce(dev,RX_INTR_COAL);
1034                         coal_conf->rx_coal_type = NO_COALESCE;
1035                 }
1036         }
1037         else{
1038
1039                 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1040                 if (rx_pkt_size < 128){
1041                         if(coal_conf->rx_coal_type != NO_COALESCE){
1042
1043                                 coal_conf->rx_timeout = 0;
1044                                 coal_conf->rx_event_count = 0;
1045                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1046                                 coal_conf->rx_coal_type = NO_COALESCE;
1047                         }
1048
1049                 }
1050                 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1051
1052                         if(coal_conf->rx_coal_type !=  LOW_COALESCE){
1053                                 coal_conf->rx_timeout = 1;
1054                                 coal_conf->rx_event_count = 4;
1055                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1056                                 coal_conf->rx_coal_type = LOW_COALESCE;
1057                         }
1058                 }
1059                 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1060
1061                         if(coal_conf->rx_coal_type !=  MEDIUM_COALESCE){
1062                                 coal_conf->rx_timeout = 1;
1063                                 coal_conf->rx_event_count = 4;
1064                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1065                                 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1066                         }
1067
1068                 }
1069                 else if(rx_pkt_size >= 1024){
1070                         if(coal_conf->rx_coal_type !=  HIGH_COALESCE){
1071                                 coal_conf->rx_timeout = 2;
1072                                 coal_conf->rx_event_count = 3;
1073                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1074                                 coal_conf->rx_coal_type = HIGH_COALESCE;
1075                         }
1076                 }
1077         }
1078         /* NOW FOR TX INTR COALESC */
1079         if(tx_pkt_rate < 800){
1080                 if(coal_conf->tx_coal_type != NO_COALESCE){
1081
1082                         coal_conf->tx_timeout = 0x0;
1083                         coal_conf->tx_event_count = 0;
1084                         amd8111e_set_coalesce(dev,TX_INTR_COAL);
1085                         coal_conf->tx_coal_type = NO_COALESCE;
1086                 }
1087         }
1088         else{
1089
1090                 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1091                 if (tx_pkt_size < 128){
1092
1093                         if(coal_conf->tx_coal_type != NO_COALESCE){
1094
1095                                 coal_conf->tx_timeout = 0;
1096                                 coal_conf->tx_event_count = 0;
1097                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1098                                 coal_conf->tx_coal_type = NO_COALESCE;
1099                         }
1100
1101                 }
1102                 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1103
1104                         if(coal_conf->tx_coal_type !=  LOW_COALESCE){
1105                                 coal_conf->tx_timeout = 1;
1106                                 coal_conf->tx_event_count = 2;
1107                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1108                                 coal_conf->tx_coal_type = LOW_COALESCE;
1109
1110                         }
1111                 }
1112                 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1113
1114                         if(coal_conf->tx_coal_type !=  MEDIUM_COALESCE){
1115                                 coal_conf->tx_timeout = 2;
1116                                 coal_conf->tx_event_count = 5;
1117                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1118                                 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1119                         }
1120
1121                 }
1122                 else if(tx_pkt_size >= 1024){
1123                         if (tx_pkt_size >= 1024){
1124                                 if(coal_conf->tx_coal_type !=  HIGH_COALESCE){
1125                                         coal_conf->tx_timeout = 4;
1126                                         coal_conf->tx_event_count = 8;
1127                                         amd8111e_set_coalesce(dev,TX_INTR_COAL);
1128                                         coal_conf->tx_coal_type = HIGH_COALESCE;
1129                                 }
1130                         }
1131                 }
1132         }
1133         return 0;
1134
1135 }
1136 /*
1137 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1138 */
1139 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1140 {
1141
1142         struct net_device * dev = (struct net_device *) dev_id;
1143         struct amd8111e_priv *lp = netdev_priv(dev);
1144         void __iomem *mmio = lp->mmio;
1145         unsigned int intr0, intren0;
1146         unsigned int handled = 1;
1147
1148         if(unlikely(dev == NULL))
1149                 return IRQ_NONE;
1150
1151         spin_lock(&lp->lock);
1152
1153         /* disabling interrupt */
1154         writel(INTREN, mmio + CMD0);
1155
1156         /* Read interrupt status */
1157         intr0 = readl(mmio + INT0);
1158         intren0 = readl(mmio + INTEN0);
1159
1160         /* Process all the INT event until INTR bit is clear. */
1161
1162         if (!(intr0 & INTR)){
1163                 handled = 0;
1164                 goto err_no_interrupt;
1165         }
1166
1167         /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1168         writel(intr0, mmio + INT0);
1169
1170         /* Check if Receive Interrupt has occurred. */
1171         if (intr0 & RINT0) {
1172                 if (napi_schedule_prep(&lp->napi)) {
1173                         /* Disable receive interupts */
1174                         writel(RINTEN0, mmio + INTEN0);
1175                         /* Schedule a polling routine */
1176                         __napi_schedule(&lp->napi);
1177                 } else if (intren0 & RINTEN0) {
1178                         printk("************Driver bug! interrupt while in poll\n");
1179                         /* Fix by disable receive interrupts */
1180                         writel(RINTEN0, mmio + INTEN0);
1181                 }
1182         }
1183
1184         /* Check if  Transmit Interrupt has occurred. */
1185         if (intr0 & TINT0)
1186                 amd8111e_tx(dev);
1187
1188         /* Check if  Link Change Interrupt has occurred. */
1189         if (intr0 & LCINT)
1190                 amd8111e_link_change(dev);
1191
1192         /* Check if Hardware Timer Interrupt has occurred. */
1193         if (intr0 & STINT)
1194                 amd8111e_calc_coalesce(dev);
1195
1196 err_no_interrupt:
1197         writel( VAL0 | INTREN,mmio + CMD0);
1198
1199         spin_unlock(&lp->lock);
1200
1201         return IRQ_RETVAL(handled);
1202 }
1203
1204 #ifdef CONFIG_NET_POLL_CONTROLLER
1205 static void amd8111e_poll(struct net_device *dev)
1206 {
1207         unsigned long flags;
1208         local_irq_save(flags);
1209         amd8111e_interrupt(0, dev);
1210         local_irq_restore(flags);
1211 }
1212 #endif
1213
1214
1215 /*
1216 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1217 */
1218 static int amd8111e_close(struct net_device * dev)
1219 {
1220         struct amd8111e_priv *lp = netdev_priv(dev);
1221         netif_stop_queue(dev);
1222
1223         napi_disable(&lp->napi);
1224
1225         spin_lock_irq(&lp->lock);
1226
1227         amd8111e_disable_interrupt(lp);
1228         amd8111e_stop_chip(lp);
1229
1230         /* Free transmit and receive skbs */
1231         amd8111e_free_skbs(lp->amd8111e_net_dev);
1232
1233         netif_carrier_off(lp->amd8111e_net_dev);
1234
1235         /* Delete ipg timer */
1236         if(lp->options & OPTION_DYN_IPG_ENABLE)
1237                 del_timer_sync(&lp->ipg_data.ipg_timer);
1238
1239         spin_unlock_irq(&lp->lock);
1240         free_irq(dev->irq, dev);
1241         amd8111e_free_ring(lp);
1242
1243         /* Update the statistics before closing */
1244         amd8111e_get_stats(dev);
1245         lp->opened = 0;
1246         return 0;
1247 }
1248 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1249 */
1250 static int amd8111e_open(struct net_device * dev )
1251 {
1252         struct amd8111e_priv *lp = netdev_priv(dev);
1253
1254         if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
1255                                          dev->name, dev))
1256                 return -EAGAIN;
1257
1258         napi_enable(&lp->napi);
1259
1260         spin_lock_irq(&lp->lock);
1261
1262         amd8111e_init_hw_default(lp);
1263
1264         if(amd8111e_restart(dev)){
1265                 spin_unlock_irq(&lp->lock);
1266                 napi_disable(&lp->napi);
1267                 if (dev->irq)
1268                         free_irq(dev->irq, dev);
1269                 return -ENOMEM;
1270         }
1271         /* Start ipg timer */
1272         if(lp->options & OPTION_DYN_IPG_ENABLE){
1273                 add_timer(&lp->ipg_data.ipg_timer);
1274                 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1275         }
1276
1277         lp->opened = 1;
1278
1279         spin_unlock_irq(&lp->lock);
1280
1281         netif_start_queue(dev);
1282
1283         return 0;
1284 }
1285 /*
1286 This function checks if there is any transmit  descriptors available to queue more packet.
1287 */
1288 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
1289 {
1290         int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1291         if (lp->tx_skbuff[tx_index])
1292                 return -1;
1293         else
1294                 return 0;
1295
1296 }
1297 /*
1298 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1299 */
1300
1301 static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb,
1302                                        struct net_device * dev)
1303 {
1304         struct amd8111e_priv *lp = netdev_priv(dev);
1305         int tx_index;
1306         unsigned long flags;
1307
1308         spin_lock_irqsave(&lp->lock, flags);
1309
1310         tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1311
1312         lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1313
1314         lp->tx_skbuff[tx_index] = skb;
1315         lp->tx_ring[tx_index].tx_flags = 0;
1316
1317 #if AMD8111E_VLAN_TAG_USED
1318         if (vlan_tx_tag_present(skb)) {
1319                 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1320                                 cpu_to_le16(TCC_VLAN_INSERT);
1321                 lp->tx_ring[tx_index].tag_ctrl_info =
1322                                 cpu_to_le16(vlan_tx_tag_get(skb));
1323
1324         }
1325 #endif
1326         lp->tx_dma_addr[tx_index] =
1327             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1328         lp->tx_ring[tx_index].buff_phy_addr =
1329             cpu_to_le32(lp->tx_dma_addr[tx_index]);
1330
1331         /*  Set FCS and LTINT bits */
1332         wmb();
1333         lp->tx_ring[tx_index].tx_flags |=
1334             cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1335
1336         lp->tx_idx++;
1337
1338         /* Trigger an immediate send poll. */
1339         writel( VAL1 | TDMD0, lp->mmio + CMD0);
1340         writel( VAL2 | RDMD0,lp->mmio + CMD0);
1341
1342         if(amd8111e_tx_queue_avail(lp) < 0){
1343                 netif_stop_queue(dev);
1344         }
1345         spin_unlock_irqrestore(&lp->lock, flags);
1346         return NETDEV_TX_OK;
1347 }
1348 /*
1349 This function returns all the memory mapped registers of the device.
1350 */
1351 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1352 {
1353         void __iomem *mmio = lp->mmio;
1354         /* Read only necessary registers */
1355         buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1356         buf[1] = readl(mmio + XMT_RING_LEN0);
1357         buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1358         buf[3] = readl(mmio + RCV_RING_LEN0);
1359         buf[4] = readl(mmio + CMD0);
1360         buf[5] = readl(mmio + CMD2);
1361         buf[6] = readl(mmio + CMD3);
1362         buf[7] = readl(mmio + CMD7);
1363         buf[8] = readl(mmio + INT0);
1364         buf[9] = readl(mmio + INTEN0);
1365         buf[10] = readl(mmio + LADRF);
1366         buf[11] = readl(mmio + LADRF+4);
1367         buf[12] = readl(mmio + STAT0);
1368 }
1369
1370
1371 /*
1372 This function sets promiscuos mode, all-multi mode or the multicast address
1373 list to the device.
1374 */
1375 static void amd8111e_set_multicast_list(struct net_device *dev)
1376 {
1377         struct netdev_hw_addr *ha;
1378         struct amd8111e_priv *lp = netdev_priv(dev);
1379         u32 mc_filter[2] ;
1380         int bit_num;
1381
1382         if(dev->flags & IFF_PROMISC){
1383                 writel( VAL2 | PROM, lp->mmio + CMD2);
1384                 return;
1385         }
1386         else
1387                 writel( PROM, lp->mmio + CMD2);
1388         if (dev->flags & IFF_ALLMULTI ||
1389             netdev_mc_count(dev) > MAX_FILTER_SIZE) {
1390                 /* get all multicast packet */
1391                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1392                 lp->options |= OPTION_MULTICAST_ENABLE;
1393                 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1394                 return;
1395         }
1396         if (netdev_mc_empty(dev)) {
1397                 /* get only own packets */
1398                 mc_filter[1] = mc_filter[0] = 0;
1399                 lp->options &= ~OPTION_MULTICAST_ENABLE;
1400                 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1401                 /* disable promiscous mode */
1402                 writel(PROM, lp->mmio + CMD2);
1403                 return;
1404         }
1405         /* load all the multicast addresses in the logic filter */
1406         lp->options |= OPTION_MULTICAST_ENABLE;
1407         mc_filter[1] = mc_filter[0] = 0;
1408         netdev_for_each_mc_addr(ha, dev) {
1409                 bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f;
1410                 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1411         }
1412         amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1413
1414         /* To eliminate PCI posting bug */
1415         readl(lp->mmio + CMD2);
1416
1417 }
1418
1419 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1420 {
1421         struct amd8111e_priv *lp = netdev_priv(dev);
1422         struct pci_dev *pci_dev = lp->pci_dev;
1423         strcpy (info->driver, MODULE_NAME);
1424         strcpy (info->version, MODULE_VERS);
1425         sprintf(info->fw_version,"%u",chip_version);
1426         strcpy (info->bus_info, pci_name(pci_dev));
1427 }
1428
1429 static int amd8111e_get_regs_len(struct net_device *dev)
1430 {
1431         return AMD8111E_REG_DUMP_LEN;
1432 }
1433
1434 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1435 {
1436         struct amd8111e_priv *lp = netdev_priv(dev);
1437         regs->version = 0;
1438         amd8111e_read_regs(lp, buf);
1439 }
1440
1441 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1442 {
1443         struct amd8111e_priv *lp = netdev_priv(dev);
1444         spin_lock_irq(&lp->lock);
1445         mii_ethtool_gset(&lp->mii_if, ecmd);
1446         spin_unlock_irq(&lp->lock);
1447         return 0;
1448 }
1449
1450 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1451 {
1452         struct amd8111e_priv *lp = netdev_priv(dev);
1453         int res;
1454         spin_lock_irq(&lp->lock);
1455         res = mii_ethtool_sset(&lp->mii_if, ecmd);
1456         spin_unlock_irq(&lp->lock);
1457         return res;
1458 }
1459
1460 static int amd8111e_nway_reset(struct net_device *dev)
1461 {
1462         struct amd8111e_priv *lp = netdev_priv(dev);
1463         return mii_nway_restart(&lp->mii_if);
1464 }
1465
1466 static u32 amd8111e_get_link(struct net_device *dev)
1467 {
1468         struct amd8111e_priv *lp = netdev_priv(dev);
1469         return mii_link_ok(&lp->mii_if);
1470 }
1471
1472 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1473 {
1474         struct amd8111e_priv *lp = netdev_priv(dev);
1475         wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1476         if (lp->options & OPTION_WOL_ENABLE)
1477                 wol_info->wolopts = WAKE_MAGIC;
1478 }
1479
1480 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1481 {
1482         struct amd8111e_priv *lp = netdev_priv(dev);
1483         if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1484                 return -EINVAL;
1485         spin_lock_irq(&lp->lock);
1486         if (wol_info->wolopts & WAKE_MAGIC)
1487                 lp->options |=
1488                         (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1489         else if(wol_info->wolopts & WAKE_PHY)
1490                 lp->options |=
1491                         (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1492         else
1493                 lp->options &= ~OPTION_WOL_ENABLE;
1494         spin_unlock_irq(&lp->lock);
1495         return 0;
1496 }
1497
1498 static const struct ethtool_ops ops = {
1499         .get_drvinfo = amd8111e_get_drvinfo,
1500         .get_regs_len = amd8111e_get_regs_len,
1501         .get_regs = amd8111e_get_regs,
1502         .get_settings = amd8111e_get_settings,
1503         .set_settings = amd8111e_set_settings,
1504         .nway_reset = amd8111e_nway_reset,
1505         .get_link = amd8111e_get_link,
1506         .get_wol = amd8111e_get_wol,
1507         .set_wol = amd8111e_set_wol,
1508 };
1509
1510 /*
1511 This function handles all the  ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1512 */
1513
1514 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1515 {
1516         struct mii_ioctl_data *data = if_mii(ifr);
1517         struct amd8111e_priv *lp = netdev_priv(dev);
1518         int err;
1519         u32 mii_regval;
1520
1521         switch(cmd) {
1522         case SIOCGMIIPHY:
1523                 data->phy_id = lp->ext_phy_addr;
1524
1525         /* fallthru */
1526         case SIOCGMIIREG:
1527
1528                 spin_lock_irq(&lp->lock);
1529                 err = amd8111e_read_phy(lp, data->phy_id,
1530                         data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1531                 spin_unlock_irq(&lp->lock);
1532
1533                 data->val_out = mii_regval;
1534                 return err;
1535
1536         case SIOCSMIIREG:
1537
1538                 spin_lock_irq(&lp->lock);
1539                 err = amd8111e_write_phy(lp, data->phy_id,
1540                         data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1541                 spin_unlock_irq(&lp->lock);
1542
1543                 return err;
1544
1545         default:
1546                 /* do nothing */
1547                 break;
1548         }
1549         return -EOPNOTSUPP;
1550 }
1551 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1552 {
1553         struct amd8111e_priv *lp = netdev_priv(dev);
1554         int i;
1555         struct sockaddr *addr = p;
1556
1557         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1558         spin_lock_irq(&lp->lock);
1559         /* Setting the MAC address to the device */
1560         for(i = 0; i < ETH_ADDR_LEN; i++)
1561                 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1562
1563         spin_unlock_irq(&lp->lock);
1564
1565         return 0;
1566 }
1567
1568 /*
1569 This function changes the mtu of the device. It restarts the device  to initialize the descriptor with new receive buffers.
1570 */
1571 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1572 {
1573         struct amd8111e_priv *lp = netdev_priv(dev);
1574         int err;
1575
1576         if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1577                 return -EINVAL;
1578
1579         if (!netif_running(dev)) {
1580                 /* new_mtu will be used
1581                    when device starts netxt time */
1582                 dev->mtu = new_mtu;
1583                 return 0;
1584         }
1585
1586         spin_lock_irq(&lp->lock);
1587
1588         /* stop the chip */
1589         writel(RUN, lp->mmio + CMD0);
1590
1591         dev->mtu = new_mtu;
1592
1593         err = amd8111e_restart(dev);
1594         spin_unlock_irq(&lp->lock);
1595         if(!err)
1596                 netif_start_queue(dev);
1597         return err;
1598 }
1599
1600 #if AMD8111E_VLAN_TAG_USED
1601 static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1602 {
1603         struct  amd8111e_priv *lp = netdev_priv(dev);
1604         spin_lock_irq(&lp->lock);
1605         lp->vlgrp = grp;
1606         spin_unlock_irq(&lp->lock);
1607 }
1608 #endif
1609
1610 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1611 {
1612         writel( VAL1|MPPLBA, lp->mmio + CMD3);
1613         writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1614
1615         /* To eliminate PCI posting bug */
1616         readl(lp->mmio + CMD7);
1617         return 0;
1618 }
1619
1620 static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1621 {
1622
1623         /* Adapter is already stoped/suspended/interrupt-disabled */
1624         writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1625
1626         /* To eliminate PCI posting bug */
1627         readl(lp->mmio + CMD7);
1628         return 0;
1629 }
1630
1631 /*
1632  * This function is called when a packet transmission fails to complete
1633  * within a reasonable period, on the assumption that an interrupt have
1634  * failed or the interface is locked up. This function will reinitialize
1635  * the hardware.
1636  */
1637 static void amd8111e_tx_timeout(struct net_device *dev)
1638 {
1639         struct amd8111e_priv* lp = netdev_priv(dev);
1640         int err;
1641
1642         printk(KERN_ERR "%s: transmit timed out, resetting\n",
1643                                                       dev->name);
1644         spin_lock_irq(&lp->lock);
1645         err = amd8111e_restart(dev);
1646         spin_unlock_irq(&lp->lock);
1647         if(!err)
1648                 netif_wake_queue(dev);
1649 }
1650 static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1651 {
1652         struct net_device *dev = pci_get_drvdata(pci_dev);
1653         struct amd8111e_priv *lp = netdev_priv(dev);
1654
1655         if (!netif_running(dev))
1656                 return 0;
1657
1658         /* disable the interrupt */
1659         spin_lock_irq(&lp->lock);
1660         amd8111e_disable_interrupt(lp);
1661         spin_unlock_irq(&lp->lock);
1662
1663         netif_device_detach(dev);
1664
1665         /* stop chip */
1666         spin_lock_irq(&lp->lock);
1667         if(lp->options & OPTION_DYN_IPG_ENABLE)
1668                 del_timer_sync(&lp->ipg_data.ipg_timer);
1669         amd8111e_stop_chip(lp);
1670         spin_unlock_irq(&lp->lock);
1671
1672         if(lp->options & OPTION_WOL_ENABLE){
1673                  /* enable wol */
1674                 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1675                         amd8111e_enable_magicpkt(lp);
1676                 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1677                         amd8111e_enable_link_change(lp);
1678
1679                 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1680                 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1681
1682         }
1683         else{
1684                 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1685                 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1686         }
1687
1688         pci_save_state(pci_dev);
1689         pci_set_power_state(pci_dev, PCI_D3hot);
1690
1691         return 0;
1692 }
1693 static int amd8111e_resume(struct pci_dev *pci_dev)
1694 {
1695         struct net_device *dev = pci_get_drvdata(pci_dev);
1696         struct amd8111e_priv *lp = netdev_priv(dev);
1697
1698         if (!netif_running(dev))
1699                 return 0;
1700
1701         pci_set_power_state(pci_dev, PCI_D0);
1702         pci_restore_state(pci_dev);
1703
1704         pci_enable_wake(pci_dev, PCI_D3hot, 0);
1705         pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1706
1707         netif_device_attach(dev);
1708
1709         spin_lock_irq(&lp->lock);
1710         amd8111e_restart(dev);
1711         /* Restart ipg timer */
1712         if(lp->options & OPTION_DYN_IPG_ENABLE)
1713                 mod_timer(&lp->ipg_data.ipg_timer,
1714                                 jiffies + IPG_CONVERGE_JIFFIES);
1715         spin_unlock_irq(&lp->lock);
1716
1717         return 0;
1718 }
1719
1720
1721 static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1722 {
1723         struct net_device *dev = pci_get_drvdata(pdev);
1724         if (dev) {
1725                 unregister_netdev(dev);
1726                 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1727                 free_netdev(dev);
1728                 pci_release_regions(pdev);
1729                 pci_disable_device(pdev);
1730                 pci_set_drvdata(pdev, NULL);
1731         }
1732 }
1733 static void amd8111e_config_ipg(struct net_device* dev)
1734 {
1735         struct amd8111e_priv *lp = netdev_priv(dev);
1736         struct ipg_info* ipg_data = &lp->ipg_data;
1737         void __iomem *mmio = lp->mmio;
1738         unsigned int prev_col_cnt = ipg_data->col_cnt;
1739         unsigned int total_col_cnt;
1740         unsigned int tmp_ipg;
1741
1742         if(lp->link_config.duplex == DUPLEX_FULL){
1743                 ipg_data->ipg = DEFAULT_IPG;
1744                 return;
1745         }
1746
1747         if(ipg_data->ipg_state == SSTATE){
1748
1749                 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1750
1751                         ipg_data->timer_tick = 0;
1752                         ipg_data->ipg = MIN_IPG - IPG_STEP;
1753                         ipg_data->current_ipg = MIN_IPG;
1754                         ipg_data->diff_col_cnt = 0xFFFFFFFF;
1755                         ipg_data->ipg_state = CSTATE;
1756                 }
1757                 else
1758                         ipg_data->timer_tick++;
1759         }
1760
1761         if(ipg_data->ipg_state == CSTATE){
1762
1763                 /* Get the current collision count */
1764
1765                 total_col_cnt = ipg_data->col_cnt =
1766                                 amd8111e_read_mib(mmio, xmt_collisions);
1767
1768                 if ((total_col_cnt - prev_col_cnt) <
1769                                 (ipg_data->diff_col_cnt)){
1770
1771                         ipg_data->diff_col_cnt =
1772                                 total_col_cnt - prev_col_cnt ;
1773
1774                         ipg_data->ipg = ipg_data->current_ipg;
1775                 }
1776
1777                 ipg_data->current_ipg += IPG_STEP;
1778
1779                 if (ipg_data->current_ipg <= MAX_IPG)
1780                         tmp_ipg = ipg_data->current_ipg;
1781                 else{
1782                         tmp_ipg = ipg_data->ipg;
1783                         ipg_data->ipg_state = SSTATE;
1784                 }
1785                 writew((u32)tmp_ipg, mmio + IPG);
1786                 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1787         }
1788          mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1789         return;
1790
1791 }
1792
1793 static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1794 {
1795         struct amd8111e_priv *lp = netdev_priv(dev);
1796         int i;
1797
1798         for (i = 0x1e; i >= 0; i--) {
1799                 u32 id1, id2;
1800
1801                 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1802                         continue;
1803                 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1804                         continue;
1805                 lp->ext_phy_id = (id1 << 16) | id2;
1806                 lp->ext_phy_addr = i;
1807                 return;
1808         }
1809         lp->ext_phy_id = 0;
1810         lp->ext_phy_addr = 1;
1811 }
1812
1813 static const struct net_device_ops amd8111e_netdev_ops = {
1814         .ndo_open               = amd8111e_open,
1815         .ndo_stop               = amd8111e_close,
1816         .ndo_start_xmit         = amd8111e_start_xmit,
1817         .ndo_tx_timeout         = amd8111e_tx_timeout,
1818         .ndo_get_stats          = amd8111e_get_stats,
1819         .ndo_set_multicast_list = amd8111e_set_multicast_list,
1820         .ndo_validate_addr      = eth_validate_addr,
1821         .ndo_set_mac_address    = amd8111e_set_mac_address,
1822         .ndo_do_ioctl           = amd8111e_ioctl,
1823         .ndo_change_mtu         = amd8111e_change_mtu,
1824 #if AMD8111E_VLAN_TAG_USED
1825         .ndo_vlan_rx_register   = amd8111e_vlan_rx_register,
1826 #endif
1827 #ifdef CONFIG_NET_POLL_CONTROLLER
1828         .ndo_poll_controller     = amd8111e_poll,
1829 #endif
1830 };
1831
1832 static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1833                                   const struct pci_device_id *ent)
1834 {
1835         int err,i,pm_cap;
1836         unsigned long reg_addr,reg_len;
1837         struct amd8111e_priv* lp;
1838         struct net_device* dev;
1839
1840         err = pci_enable_device(pdev);
1841         if(err){
1842                 printk(KERN_ERR "amd8111e: Cannot enable new PCI device, "
1843                         "exiting.\n");
1844                 return err;
1845         }
1846
1847         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1848                 printk(KERN_ERR "amd8111e: Cannot find PCI base address, "
1849                        "exiting.\n");
1850                 err = -ENODEV;
1851                 goto err_disable_pdev;
1852         }
1853
1854         err = pci_request_regions(pdev, MODULE_NAME);
1855         if(err){
1856                 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1857                        "exiting.\n");
1858                 goto err_disable_pdev;
1859         }
1860
1861         pci_set_master(pdev);
1862
1863         /* Find power-management capability. */
1864         if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1865                 printk(KERN_ERR "amd8111e: No Power Management capability, "
1866                        "exiting.\n");
1867                 goto err_free_reg;
1868         }
1869
1870         /* Initialize DMA */
1871         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) {
1872                 printk(KERN_ERR "amd8111e: DMA not supported,"
1873                         "exiting.\n");
1874                 goto err_free_reg;
1875         }
1876
1877         reg_addr = pci_resource_start(pdev, 0);
1878         reg_len = pci_resource_len(pdev, 0);
1879
1880         dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1881         if (!dev) {
1882                 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
1883                 err = -ENOMEM;
1884                 goto err_free_reg;
1885         }
1886
1887         SET_NETDEV_DEV(dev, &pdev->dev);
1888
1889 #if AMD8111E_VLAN_TAG_USED
1890         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
1891 #endif
1892
1893         lp = netdev_priv(dev);
1894         lp->pci_dev = pdev;
1895         lp->amd8111e_net_dev = dev;
1896         lp->pm_cap = pm_cap;
1897
1898         spin_lock_init(&lp->lock);
1899
1900         lp->mmio = ioremap(reg_addr, reg_len);
1901         if (!lp->mmio) {
1902                 printk(KERN_ERR "amd8111e: Cannot map device registers, "
1903                        "exiting\n");
1904                 err = -ENOMEM;
1905                 goto err_free_dev;
1906         }
1907
1908         /* Initializing MAC address */
1909         for(i = 0; i < ETH_ADDR_LEN; i++)
1910                 dev->dev_addr[i] = readb(lp->mmio + PADR + i);
1911
1912         /* Setting user defined parametrs */
1913         lp->ext_phy_option = speed_duplex[card_idx];
1914         if(coalesce[card_idx])
1915                 lp->options |= OPTION_INTR_COAL_ENABLE;
1916         if(dynamic_ipg[card_idx++])
1917                 lp->options |= OPTION_DYN_IPG_ENABLE;
1918
1919
1920         /* Initialize driver entry points */
1921         dev->netdev_ops = &amd8111e_netdev_ops;
1922         SET_ETHTOOL_OPS(dev, &ops);
1923         dev->irq =pdev->irq;
1924         dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1925         netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1926
1927 #if AMD8111E_VLAN_TAG_USED
1928         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1929 #endif
1930         /* Probe the external PHY */
1931         amd8111e_probe_ext_phy(dev);
1932
1933         /* setting mii default values */
1934         lp->mii_if.dev = dev;
1935         lp->mii_if.mdio_read = amd8111e_mdio_read;
1936         lp->mii_if.mdio_write = amd8111e_mdio_write;
1937         lp->mii_if.phy_id = lp->ext_phy_addr;
1938
1939         /* Set receive buffer length and set jumbo option*/
1940         amd8111e_set_rx_buff_len(dev);
1941
1942
1943         err = register_netdev(dev);
1944         if (err) {
1945                 printk(KERN_ERR "amd8111e: Cannot register net device, "
1946                        "exiting.\n");
1947                 goto err_iounmap;
1948         }
1949
1950         pci_set_drvdata(pdev, dev);
1951
1952         /* Initialize software ipg timer */
1953         if(lp->options & OPTION_DYN_IPG_ENABLE){
1954                 init_timer(&lp->ipg_data.ipg_timer);
1955                 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
1956                 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
1957                 lp->ipg_data.ipg_timer.expires = jiffies +
1958                                                  IPG_CONVERGE_JIFFIES;
1959                 lp->ipg_data.ipg = DEFAULT_IPG;
1960                 lp->ipg_data.ipg_state = CSTATE;
1961         };
1962
1963         /*  display driver and device information */
1964
1965         chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
1966         printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n",
1967                dev->name,MODULE_VERS);
1968         printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet %pM\n",
1969                dev->name, chip_version, dev->dev_addr);
1970         if (lp->ext_phy_id)
1971                 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
1972                        dev->name, lp->ext_phy_id, lp->ext_phy_addr);
1973         else
1974                 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
1975                        dev->name);
1976         return 0;
1977 err_iounmap:
1978         iounmap(lp->mmio);
1979
1980 err_free_dev:
1981         free_netdev(dev);
1982
1983 err_free_reg:
1984         pci_release_regions(pdev);
1985
1986 err_disable_pdev:
1987         pci_disable_device(pdev);
1988         pci_set_drvdata(pdev, NULL);
1989         return err;
1990
1991 }
1992
1993 static struct pci_driver amd8111e_driver = {
1994         .name           = MODULE_NAME,
1995         .id_table       = amd8111e_pci_tbl,
1996         .probe          = amd8111e_probe_one,
1997         .remove         = __devexit_p(amd8111e_remove_one),
1998         .suspend        = amd8111e_suspend,
1999         .resume         = amd8111e_resume
2000 };
2001
2002 static int __init amd8111e_init(void)
2003 {
2004         return pci_register_driver(&amd8111e_driver);
2005 }
2006
2007 static void __exit amd8111e_cleanup(void)
2008 {
2009         pci_unregister_driver(&amd8111e_driver);
2010 }
2011
2012 module_init(amd8111e_init);
2013 module_exit(amd8111e_cleanup);