drivers: remove duplicated #include
[linux-2.6.git] / drivers / mtd / onenand / omap2.c
1 /*
2  *  linux/drivers/mtd/onenand/omap2.c
3  *
4  *  OneNAND driver for OMAP2 / OMAP3
5  *
6  *  Copyright © 2005-2006 Nokia Corporation
7  *
8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
9  *  IRQ and DMA support written by Timo Teras
10  *
11  * This program is free software; you can redistribute it and/or modify it
12  * under the terms of the GNU General Public License version 2 as published by
13  * the Free Software Foundation.
14  *
15  * This program is distributed in the hope that it will be useful, but WITHOUT
16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18  * more details.
19  *
20  * You should have received a copy of the GNU General Public License along with
21  * this program; see the file COPYING. If not, write to the Free Software
22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23  *
24  */
25
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/onenand.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35
36 #include <asm/io.h>
37 #include <asm/mach/flash.h>
38 #include <asm/arch/gpmc.h>
39 #include <asm/arch/onenand.h>
40 #include <asm/arch/gpio.h>
41 #include <asm/arch/pm.h>
42
43 #include <linux/dma-mapping.h>
44 #include <asm/dma-mapping.h>
45 #include <asm/arch/dma.h>
46
47 #include <asm/arch/board.h>
48
49 #define DRIVER_NAME "omap2-onenand"
50
51 #define ONENAND_IO_SIZE         SZ_128K
52 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
53
54 struct omap2_onenand {
55         struct platform_device *pdev;
56         int gpmc_cs;
57         unsigned long phys_base;
58         int gpio_irq;
59         struct mtd_info mtd;
60         struct mtd_partition *parts;
61         struct onenand_chip onenand;
62         struct completion irq_done;
63         struct completion dma_done;
64         int dma_channel;
65         int freq;
66         int (*setup)(void __iomem *base, int freq);
67 };
68
69 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
70 {
71         struct omap2_onenand *c = data;
72
73         complete(&c->dma_done);
74 }
75
76 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
77 {
78         struct omap2_onenand *c = dev_id;
79
80         complete(&c->irq_done);
81
82         return IRQ_HANDLED;
83 }
84
85 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
86 {
87         return readw(c->onenand.base + reg);
88 }
89
90 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
91                              int reg)
92 {
93         writew(value, c->onenand.base + reg);
94 }
95
96 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
97 {
98         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
99                msg, state, ctrl, intr);
100 }
101
102 static void wait_warn(char *msg, int state, unsigned int ctrl,
103                       unsigned int intr)
104 {
105         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
106                "intr 0x%04x\n", msg, state, ctrl, intr);
107 }
108
109 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
110 {
111         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
112         unsigned int intr = 0;
113         unsigned int ctrl;
114         unsigned long timeout;
115         u32 syscfg;
116
117         if (state == FL_RESETING) {
118                 int i;
119
120                 for (i = 0; i < 20; i++) {
121                         udelay(1);
122                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
123                         if (intr & ONENAND_INT_MASTER)
124                                 break;
125                 }
126                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
127                 if (ctrl & ONENAND_CTRL_ERROR) {
128                         wait_err("controller error", state, ctrl, intr);
129                         return -EIO;
130                 }
131                 if (!(intr & ONENAND_INT_RESET)) {
132                         wait_err("timeout", state, ctrl, intr);
133                         return -EIO;
134                 }
135                 return 0;
136         }
137
138         if (state != FL_READING) {
139                 int result;
140
141                 /* Turn interrupts on */
142                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
143                 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
144                         syscfg |= ONENAND_SYS_CFG1_IOBE;
145                         write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
146                         if (cpu_is_omap34xx())
147                                 /* Add a delay to let GPIO settle */
148                                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
149                 }
150
151                 INIT_COMPLETION(c->irq_done);
152                 if (c->gpio_irq) {
153                         result = omap_get_gpio_datain(c->gpio_irq);
154                         if (result == -1) {
155                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
156                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
157                                 wait_err("gpio error", state, ctrl, intr);
158                                 return -EIO;
159                         }
160                 } else
161                         result = 0;
162                 if (result == 0) {
163                         int retry_cnt = 0;
164 retry:
165                         result = wait_for_completion_timeout(&c->irq_done,
166                                                     msecs_to_jiffies(20));
167                         if (result == 0) {
168                                 /* Timeout after 20ms */
169                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
170                                 if (ctrl & ONENAND_CTRL_ONGO) {
171                                         /*
172                                          * The operation seems to be still going
173                                          * so give it some more time.
174                                          */
175                                         retry_cnt += 1;
176                                         if (retry_cnt < 3)
177                                                 goto retry;
178                                         intr = read_reg(c,
179                                                         ONENAND_REG_INTERRUPT);
180                                         wait_err("timeout", state, ctrl, intr);
181                                         return -EIO;
182                                 }
183                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
184                                 if ((intr & ONENAND_INT_MASTER) == 0)
185                                         wait_warn("timeout", state, ctrl, intr);
186                         }
187                 }
188         } else {
189                 int retry_cnt = 0;
190
191                 /* Turn interrupts off */
192                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
193                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
194                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
195
196                 timeout = jiffies + msecs_to_jiffies(20);
197                 while (1) {
198                         if (time_before(jiffies, timeout)) {
199                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
200                                 if (intr & ONENAND_INT_MASTER)
201                                         break;
202                         } else {
203                                 /* Timeout after 20ms */
204                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
205                                 if (ctrl & ONENAND_CTRL_ONGO) {
206                                         /*
207                                          * The operation seems to be still going
208                                          * so give it some more time.
209                                          */
210                                         retry_cnt += 1;
211                                         if (retry_cnt < 3) {
212                                                 timeout = jiffies +
213                                                           msecs_to_jiffies(20);
214                                                 continue;
215                                         }
216                                 }
217                                 break;
218                         }
219                 }
220         }
221
222         intr = read_reg(c, ONENAND_REG_INTERRUPT);
223         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
224
225         if (intr & ONENAND_INT_READ) {
226                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
227
228                 if (ecc) {
229                         unsigned int addr1, addr8;
230
231                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
232                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
233                         if (ecc & ONENAND_ECC_2BIT_ALL) {
234                                 printk(KERN_ERR "onenand_wait: ECC error = "
235                                        "0x%04x, addr1 %#x, addr8 %#x\n",
236                                        ecc, addr1, addr8);
237                                 mtd->ecc_stats.failed++;
238                                 return -EBADMSG;
239                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
240                                 printk(KERN_NOTICE "onenand_wait: correctable "
241                                        "ECC error = 0x%04x, addr1 %#x, "
242                                        "addr8 %#x\n", ecc, addr1, addr8);
243                                 mtd->ecc_stats.corrected++;
244                         }
245                 }
246         } else if (state == FL_READING) {
247                 wait_err("timeout", state, ctrl, intr);
248                 return -EIO;
249         }
250
251         if (ctrl & ONENAND_CTRL_ERROR) {
252                 wait_err("controller error", state, ctrl, intr);
253                 if (ctrl & ONENAND_CTRL_LOCK)
254                         printk(KERN_ERR "onenand_wait: "
255                                         "Device is write protected!!!\n");
256                 return -EIO;
257         }
258
259         if (ctrl & 0xFE9F)
260                 wait_warn("unexpected controller status", state, ctrl, intr);
261
262         return 0;
263 }
264
265 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
266 {
267         struct onenand_chip *this = mtd->priv;
268
269         if (ONENAND_CURRENT_BUFFERRAM(this)) {
270                 if (area == ONENAND_DATARAM)
271                         return mtd->writesize;
272                 if (area == ONENAND_SPARERAM)
273                         return mtd->oobsize;
274         }
275
276         return 0;
277 }
278
279 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
280
281 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
282                                         unsigned char *buffer, int offset,
283                                         size_t count)
284 {
285         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
286         struct onenand_chip *this = mtd->priv;
287         dma_addr_t dma_src, dma_dst;
288         int bram_offset;
289         unsigned long timeout;
290         void *buf = (void *)buffer;
291         size_t xtra;
292         volatile unsigned *done;
293
294         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
295         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
296                 goto out_copy;
297
298         if (buf >= high_memory) {
299                 struct page *p1;
300
301                 if (((size_t)buf & PAGE_MASK) !=
302                     ((size_t)(buf + count - 1) & PAGE_MASK))
303                         goto out_copy;
304                 p1 = vmalloc_to_page(buf);
305                 if (!p1)
306                         goto out_copy;
307                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
308         }
309
310         xtra = count & 3;
311         if (xtra) {
312                 count -= xtra;
313                 memcpy(buf + count, this->base + bram_offset + count, xtra);
314         }
315
316         dma_src = c->phys_base + bram_offset;
317         dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
318         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
319                 dev_err(&c->pdev->dev,
320                         "Couldn't DMA map a %d byte buffer\n",
321                         count);
322                 goto out_copy;
323         }
324
325         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
326                                      count >> 2, 1, 0, 0, 0);
327         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
328                                 dma_src, 0, 0);
329         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
330                                  dma_dst, 0, 0);
331
332         INIT_COMPLETION(c->dma_done);
333         omap_start_dma(c->dma_channel);
334
335         timeout = jiffies + msecs_to_jiffies(20);
336         done = &c->dma_done.done;
337         while (time_before(jiffies, timeout))
338                 if (*done)
339                         break;
340
341         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
342
343         if (!*done) {
344                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
345                 goto out_copy;
346         }
347
348         return 0;
349
350 out_copy:
351         memcpy(buf, this->base + bram_offset, count);
352         return 0;
353 }
354
355 static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
356                                          const unsigned char *buffer,
357                                          int offset, size_t count)
358 {
359         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
360         struct onenand_chip *this = mtd->priv;
361         dma_addr_t dma_src, dma_dst;
362         int bram_offset;
363         unsigned long timeout;
364         void *buf = (void *)buffer;
365         volatile unsigned *done;
366
367         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
368         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
369                 goto out_copy;
370
371         /* panic_write() may be in an interrupt context */
372         if (in_interrupt())
373                 goto out_copy;
374
375         if (buf >= high_memory) {
376                 struct page *p1;
377
378                 if (((size_t)buf & PAGE_MASK) !=
379                     ((size_t)(buf + count - 1) & PAGE_MASK))
380                         goto out_copy;
381                 p1 = vmalloc_to_page(buf);
382                 if (!p1)
383                         goto out_copy;
384                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
385         }
386
387         dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
388         dma_dst = c->phys_base + bram_offset;
389         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
390                 dev_err(&c->pdev->dev,
391                         "Couldn't DMA map a %d byte buffer\n",
392                         count);
393                 return -1;
394         }
395
396         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
397                                      count >> 2, 1, 0, 0, 0);
398         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
399                                 dma_src, 0, 0);
400         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
401                                  dma_dst, 0, 0);
402
403         INIT_COMPLETION(c->dma_done);
404         omap_start_dma(c->dma_channel);
405
406         timeout = jiffies + msecs_to_jiffies(20);
407         done = &c->dma_done.done;
408         while (time_before(jiffies, timeout))
409                 if (*done)
410                         break;
411
412         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
413
414         if (!*done) {
415                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
416                 goto out_copy;
417         }
418
419         return 0;
420
421 out_copy:
422         memcpy(this->base + bram_offset, buf, count);
423         return 0;
424 }
425
426 #else
427
428 int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
429                                  unsigned char *buffer, int offset,
430                                  size_t count);
431
432 int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
433                                   const unsigned char *buffer,
434                                   int offset, size_t count);
435
436 #endif
437
438 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
439
440 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
441                                         unsigned char *buffer, int offset,
442                                         size_t count)
443 {
444         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
445         struct onenand_chip *this = mtd->priv;
446         dma_addr_t dma_src, dma_dst;
447         int bram_offset;
448
449         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
450         /* DMA is not used.  Revisit PM requirements before enabling it. */
451         if (1 || (c->dma_channel < 0) ||
452             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
453             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
454                 memcpy(buffer, (__force void *)(this->base + bram_offset),
455                        count);
456                 return 0;
457         }
458
459         dma_src = c->phys_base + bram_offset;
460         dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
461                                  DMA_FROM_DEVICE);
462         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
463                 dev_err(&c->pdev->dev,
464                         "Couldn't DMA map a %d byte buffer\n",
465                         count);
466                 return -1;
467         }
468
469         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
470                                      count / 4, 1, 0, 0, 0);
471         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
472                                 dma_src, 0, 0);
473         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
474                                  dma_dst, 0, 0);
475
476         INIT_COMPLETION(c->dma_done);
477         omap_start_dma(c->dma_channel);
478         wait_for_completion(&c->dma_done);
479
480         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
481
482         return 0;
483 }
484
485 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
486                                          const unsigned char *buffer,
487                                          int offset, size_t count)
488 {
489         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
490         struct onenand_chip *this = mtd->priv;
491         dma_addr_t dma_src, dma_dst;
492         int bram_offset;
493
494         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
495         /* DMA is not used.  Revisit PM requirements before enabling it. */
496         if (1 || (c->dma_channel < 0) ||
497             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
498             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
499                 memcpy((__force void *)(this->base + bram_offset), buffer,
500                        count);
501                 return 0;
502         }
503
504         dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
505                                  DMA_TO_DEVICE);
506         dma_dst = c->phys_base + bram_offset;
507         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
508                 dev_err(&c->pdev->dev,
509                         "Couldn't DMA map a %d byte buffer\n",
510                         count);
511                 return -1;
512         }
513
514         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
515                                      count / 2, 1, 0, 0, 0);
516         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
517                                 dma_src, 0, 0);
518         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
519                                  dma_dst, 0, 0);
520
521         INIT_COMPLETION(c->dma_done);
522         omap_start_dma(c->dma_channel);
523         wait_for_completion(&c->dma_done);
524
525         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
526
527         return 0;
528 }
529
530 #else
531
532 int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
533                                  unsigned char *buffer, int offset,
534                                  size_t count);
535
536 int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
537                                   const unsigned char *buffer,
538                                   int offset, size_t count);
539
540 #endif
541
542 static struct platform_driver omap2_onenand_driver;
543
544 static int __adjust_timing(struct device *dev, void *data)
545 {
546         int ret = 0;
547         struct omap2_onenand *c;
548
549         c = dev_get_drvdata(dev);
550
551         BUG_ON(c->setup == NULL);
552
553         /* DMA is not in use so this is all that is needed */
554         /* Revisit for OMAP3! */
555         ret = c->setup(c->onenand.base, c->freq);
556
557         return ret;
558 }
559
560 int omap2_onenand_rephase(void)
561 {
562         return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
563                                       NULL, __adjust_timing);
564 }
565
566 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
567 {
568         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
569
570         /* With certain content in the buffer RAM, the OMAP boot ROM code
571          * can recognize the flash chip incorrectly. Zero it out before
572          * soft reset.
573          */
574         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
575 }
576
577 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
578 {
579         struct omap_onenand_platform_data *pdata;
580         struct omap2_onenand *c;
581         int r;
582
583         pdata = pdev->dev.platform_data;
584         if (pdata == NULL) {
585                 dev_err(&pdev->dev, "platform data missing\n");
586                 return -ENODEV;
587         }
588
589         c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
590         if (!c)
591                 return -ENOMEM;
592
593         init_completion(&c->irq_done);
594         init_completion(&c->dma_done);
595         c->gpmc_cs = pdata->cs;
596         c->gpio_irq = pdata->gpio_irq;
597         c->dma_channel = pdata->dma_channel;
598         if (c->dma_channel < 0) {
599                 /* if -1, don't use DMA */
600                 c->gpio_irq = 0;
601         }
602
603         r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
604         if (r < 0) {
605                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
606                 goto err_kfree;
607         }
608
609         if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
610                                pdev->dev.driver->name) == NULL) {
611                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
612                         "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
613                 r = -EBUSY;
614                 goto err_free_cs;
615         }
616         c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
617         if (c->onenand.base == NULL) {
618                 r = -ENOMEM;
619                 goto err_release_mem_region;
620         }
621
622         if (pdata->onenand_setup != NULL) {
623                 r = pdata->onenand_setup(c->onenand.base, c->freq);
624                 if (r < 0) {
625                         dev_err(&pdev->dev, "Onenand platform setup failed: "
626                                 "%d\n", r);
627                         goto err_iounmap;
628                 }
629                 c->setup = pdata->onenand_setup;
630         }
631
632         if (c->gpio_irq) {
633                 if ((r = omap_request_gpio(c->gpio_irq)) < 0) {
634                         dev_err(&pdev->dev,  "Failed to request GPIO%d for "
635                                 "OneNAND\n", c->gpio_irq);
636                         goto err_iounmap;
637         }
638         omap_set_gpio_direction(c->gpio_irq, 1);
639
640         if ((r = request_irq(OMAP_GPIO_IRQ(c->gpio_irq),
641                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
642                              pdev->dev.driver->name, c)) < 0)
643                 goto err_release_gpio;
644         }
645
646         if (c->dma_channel >= 0) {
647                 r = omap_request_dma(0, pdev->dev.driver->name,
648                                      omap2_onenand_dma_cb, (void *) c,
649                                      &c->dma_channel);
650                 if (r == 0) {
651                         omap_set_dma_write_mode(c->dma_channel,
652                                                 OMAP_DMA_WRITE_NON_POSTED);
653                         omap_set_dma_src_data_pack(c->dma_channel, 1);
654                         omap_set_dma_src_burst_mode(c->dma_channel,
655                                                     OMAP_DMA_DATA_BURST_8);
656                         omap_set_dma_dest_data_pack(c->dma_channel, 1);
657                         omap_set_dma_dest_burst_mode(c->dma_channel,
658                                                      OMAP_DMA_DATA_BURST_8);
659                 } else {
660                         dev_info(&pdev->dev,
661                                  "failed to allocate DMA for OneNAND, "
662                                  "using PIO instead\n");
663                         c->dma_channel = -1;
664                 }
665         }
666
667         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
668                  "base %p\n", c->gpmc_cs, c->phys_base,
669                  c->onenand.base);
670
671         c->pdev = pdev;
672         c->mtd.name = pdev->dev.bus_id;
673         c->mtd.priv = &c->onenand;
674         c->mtd.owner = THIS_MODULE;
675
676         if (c->dma_channel >= 0) {
677                 struct onenand_chip *this = &c->onenand;
678
679                 this->wait = omap2_onenand_wait;
680                 if (cpu_is_omap34xx()) {
681                         this->read_bufferram = omap3_onenand_read_bufferram;
682                         this->write_bufferram = omap3_onenand_write_bufferram;
683                 } else {
684                         this->read_bufferram = omap2_onenand_read_bufferram;
685                         this->write_bufferram = omap2_onenand_write_bufferram;
686                 }
687         }
688
689         if ((r = onenand_scan(&c->mtd, 1)) < 0)
690                 goto err_release_dma;
691
692         switch ((c->onenand.version_id >> 4) & 0xf) {
693         case 0:
694                 c->freq = 40;
695                 break;
696         case 1:
697                 c->freq = 54;
698                 break;
699         case 2:
700                 c->freq = 66;
701                 break;
702         case 3:
703                 c->freq = 83;
704                 break;
705         }
706
707 #ifdef CONFIG_MTD_PARTITIONS
708         if (pdata->parts != NULL)
709                 r = add_mtd_partitions(&c->mtd, pdata->parts,
710                                        pdata->nr_parts);
711         else
712 #endif
713                 r = add_mtd_device(&c->mtd);
714         if (r < 0)
715                 goto err_release_onenand;
716
717         platform_set_drvdata(pdev, c);
718
719         return 0;
720
721 err_release_onenand:
722         onenand_release(&c->mtd);
723 err_release_dma:
724         if (c->dma_channel != -1)
725                 omap_free_dma(c->dma_channel);
726         if (c->gpio_irq)
727                 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
728 err_release_gpio:
729         if (c->gpio_irq)
730                 omap_free_gpio(c->gpio_irq);
731 err_iounmap:
732         iounmap(c->onenand.base);
733 err_release_mem_region:
734         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
735 err_free_cs:
736         gpmc_cs_free(c->gpmc_cs);
737 err_kfree:
738         kfree(c);
739
740         return r;
741 }
742
743 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
744 {
745         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
746
747         BUG_ON(c == NULL);
748
749 #ifdef CONFIG_MTD_PARTITIONS
750         if (c->parts)
751                 del_mtd_partitions(&c->mtd);
752         else
753                 del_mtd_device(&c->mtd);
754 #else
755         del_mtd_device(&c->mtd);
756 #endif
757
758         onenand_release(&c->mtd);
759         if (c->dma_channel != -1)
760                 omap_free_dma(c->dma_channel);
761         omap2_onenand_shutdown(pdev);
762         platform_set_drvdata(pdev, NULL);
763         if (c->gpio_irq) {
764                 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
765                 omap_free_gpio(c->gpio_irq);
766         }
767         iounmap(c->onenand.base);
768         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
769         kfree(c);
770
771         return 0;
772 }
773
774 static struct platform_driver omap2_onenand_driver = {
775         .probe          = omap2_onenand_probe,
776         .remove         = omap2_onenand_remove,
777         .shutdown       = omap2_onenand_shutdown,
778         .driver         = {
779                 .name   = DRIVER_NAME,
780                 .owner  = THIS_MODULE,
781         },
782 };
783
784 static int __init omap2_onenand_init(void)
785 {
786         printk(KERN_INFO "OneNAND driver initializing\n");
787         return platform_driver_register(&omap2_onenand_driver);
788 }
789
790 static void __exit omap2_onenand_exit(void)
791 {
792         platform_driver_unregister(&omap2_onenand_driver);
793 }
794
795 module_init(omap2_onenand_init);
796 module_exit(omap2_onenand_exit);
797
798 MODULE_ALIAS(DRIVER_NAME);
799 MODULE_LICENSE("GPL");
800 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
801 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");