8387e05daae2186ec32627407f9ee28eda757bd8
[linux-2.6.git] / drivers / mtd / onenand / omap2.c
1 /*
2  *  linux/drivers/mtd/onenand/omap2.c
3  *
4  *  OneNAND driver for OMAP2 / OMAP3
5  *
6  *  Copyright © 2005-2006 Nokia Corporation
7  *
8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
9  *  IRQ and DMA support written by Timo Teras
10  *
11  * This program is free software; you can redistribute it and/or modify it
12  * under the terms of the GNU General Public License version 2 as published by
13  * the Free Software Foundation.
14  *
15  * This program is distributed in the hope that it will be useful, but WITHOUT
16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18  * more details.
19  *
20  * You should have received a copy of the GNU General Public License along with
21  * this program; see the file COPYING. If not, write to the Free Software
22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23  *
24  */
25
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/onenand.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35
36 #include <asm/io.h>
37 #include <asm/mach/flash.h>
38 #include <asm/arch/gpmc.h>
39 #include <asm/arch/onenand.h>
40 #include <asm/arch/gpio.h>
41 #include <asm/arch/gpmc.h>
42 #include <asm/arch/pm.h>
43
44 #include <linux/dma-mapping.h>
45 #include <asm/dma-mapping.h>
46 #include <asm/arch/dma.h>
47
48 #include <asm/arch/board.h>
49
50 #define DRIVER_NAME "omap2-onenand"
51
52 #define ONENAND_IO_SIZE         SZ_128K
53 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
54
55 struct omap2_onenand {
56         struct platform_device *pdev;
57         int gpmc_cs;
58         unsigned long phys_base;
59         int gpio_irq;
60         struct mtd_info mtd;
61         struct mtd_partition *parts;
62         struct onenand_chip onenand;
63         struct completion irq_done;
64         struct completion dma_done;
65         int dma_channel;
66         int freq;
67         int (*setup)(void __iomem *base, int freq);
68 };
69
70 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
71 {
72         struct omap2_onenand *c = data;
73
74         complete(&c->dma_done);
75 }
76
77 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
78 {
79         struct omap2_onenand *c = dev_id;
80
81         complete(&c->irq_done);
82
83         return IRQ_HANDLED;
84 }
85
86 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
87 {
88         return readw(c->onenand.base + reg);
89 }
90
91 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
92                              int reg)
93 {
94         writew(value, c->onenand.base + reg);
95 }
96
97 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
98 {
99         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
100                msg, state, ctrl, intr);
101 }
102
103 static void wait_warn(char *msg, int state, unsigned int ctrl,
104                       unsigned int intr)
105 {
106         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
107                "intr 0x%04x\n", msg, state, ctrl, intr);
108 }
109
110 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
111 {
112         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
113         unsigned int intr = 0;
114         unsigned int ctrl;
115         unsigned long timeout;
116         u32 syscfg;
117
118         if (state == FL_RESETING) {
119                 int i;
120
121                 for (i = 0; i < 20; i++) {
122                         udelay(1);
123                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
124                         if (intr & ONENAND_INT_MASTER)
125                                 break;
126                 }
127                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
128                 if (ctrl & ONENAND_CTRL_ERROR) {
129                         wait_err("controller error", state, ctrl, intr);
130                         return -EIO;
131                 }
132                 if (!(intr & ONENAND_INT_RESET)) {
133                         wait_err("timeout", state, ctrl, intr);
134                         return -EIO;
135                 }
136                 return 0;
137         }
138
139         if (state != FL_READING) {
140                 int result;
141
142                 /* Turn interrupts on */
143                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
144                 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
145                         syscfg |= ONENAND_SYS_CFG1_IOBE;
146                         write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
147                         if (cpu_is_omap34xx())
148                                 /* Add a delay to let GPIO settle */
149                                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
150                 }
151
152                 INIT_COMPLETION(c->irq_done);
153                 if (c->gpio_irq) {
154                         result = omap_get_gpio_datain(c->gpio_irq);
155                         if (result == -1) {
156                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
157                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
158                                 wait_err("gpio error", state, ctrl, intr);
159                                 return -EIO;
160                         }
161                 } else
162                         result = 0;
163                 if (result == 0) {
164                         int retry_cnt = 0;
165 retry:
166                         result = wait_for_completion_timeout(&c->irq_done,
167                                                     msecs_to_jiffies(20));
168                         if (result == 0) {
169                                 /* Timeout after 20ms */
170                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
171                                 if (ctrl & ONENAND_CTRL_ONGO) {
172                                         /*
173                                          * The operation seems to be still going
174                                          * so give it some more time.
175                                          */
176                                         retry_cnt += 1;
177                                         if (retry_cnt < 3)
178                                                 goto retry;
179                                         intr = read_reg(c,
180                                                         ONENAND_REG_INTERRUPT);
181                                         wait_err("timeout", state, ctrl, intr);
182                                         return -EIO;
183                                 }
184                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
185                                 if ((intr & ONENAND_INT_MASTER) == 0)
186                                         wait_warn("timeout", state, ctrl, intr);
187                         }
188                 }
189         } else {
190                 int retry_cnt = 0;
191
192                 /* Turn interrupts off */
193                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
194                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
195                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
196
197                 timeout = jiffies + msecs_to_jiffies(20);
198                 while (1) {
199                         if (time_before(jiffies, timeout)) {
200                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
201                                 if (intr & ONENAND_INT_MASTER)
202                                         break;
203                         } else {
204                                 /* Timeout after 20ms */
205                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
206                                 if (ctrl & ONENAND_CTRL_ONGO) {
207                                         /*
208                                          * The operation seems to be still going
209                                          * so give it some more time.
210                                          */
211                                         retry_cnt += 1;
212                                         if (retry_cnt < 3) {
213                                                 timeout = jiffies +
214                                                           msecs_to_jiffies(20);
215                                                 continue;
216                                         }
217                                 }
218                                 break;
219                         }
220                 }
221         }
222
223         intr = read_reg(c, ONENAND_REG_INTERRUPT);
224         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
225
226         if (intr & ONENAND_INT_READ) {
227                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
228
229                 if (ecc) {
230                         unsigned int addr1, addr8;
231
232                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
233                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
234                         if (ecc & ONENAND_ECC_2BIT_ALL) {
235                                 printk(KERN_ERR "onenand_wait: ECC error = "
236                                        "0x%04x, addr1 %#x, addr8 %#x\n",
237                                        ecc, addr1, addr8);
238                                 mtd->ecc_stats.failed++;
239                                 return -EBADMSG;
240                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
241                                 printk(KERN_NOTICE "onenand_wait: correctable "
242                                        "ECC error = 0x%04x, addr1 %#x, "
243                                        "addr8 %#x\n", ecc, addr1, addr8);
244                                 mtd->ecc_stats.corrected++;
245                         }
246                 }
247         } else if (state == FL_READING) {
248                 wait_err("timeout", state, ctrl, intr);
249                 return -EIO;
250         }
251
252         if (ctrl & ONENAND_CTRL_ERROR) {
253                 wait_err("controller error", state, ctrl, intr);
254                 if (ctrl & ONENAND_CTRL_LOCK)
255                         printk(KERN_ERR "onenand_wait: "
256                                         "Device is write protected!!!\n");
257                 return -EIO;
258         }
259
260         if (ctrl & 0xFE9F)
261                 wait_warn("unexpected controller status", state, ctrl, intr);
262
263         return 0;
264 }
265
266 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
267 {
268         struct onenand_chip *this = mtd->priv;
269
270         if (ONENAND_CURRENT_BUFFERRAM(this)) {
271                 if (area == ONENAND_DATARAM)
272                         return mtd->writesize;
273                 if (area == ONENAND_SPARERAM)
274                         return mtd->oobsize;
275         }
276
277         return 0;
278 }
279
280 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
281
282 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
283                                         unsigned char *buffer, int offset,
284                                         size_t count)
285 {
286         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
287         struct onenand_chip *this = mtd->priv;
288         dma_addr_t dma_src, dma_dst;
289         int bram_offset;
290         unsigned long timeout;
291         void *buf = (void *)buffer;
292         size_t xtra;
293         volatile unsigned *done;
294
295         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
296         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
297                 goto out_copy;
298
299         if (buf >= high_memory) {
300                 struct page *p1;
301
302                 if (((size_t)buf & PAGE_MASK) !=
303                     ((size_t)(buf + count - 1) & PAGE_MASK))
304                         goto out_copy;
305                 p1 = vmalloc_to_page(buf);
306                 if (!p1)
307                         goto out_copy;
308                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
309         }
310
311         xtra = count & 3;
312         if (xtra) {
313                 count -= xtra;
314                 memcpy(buf + count, this->base + bram_offset + count, xtra);
315         }
316
317         dma_src = c->phys_base + bram_offset;
318         dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
319         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
320                 dev_err(&c->pdev->dev,
321                         "Couldn't DMA map a %d byte buffer\n",
322                         count);
323                 goto out_copy;
324         }
325
326         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
327                                      count >> 2, 1, 0, 0, 0);
328         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
329                                 dma_src, 0, 0);
330         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
331                                  dma_dst, 0, 0);
332
333         INIT_COMPLETION(c->dma_done);
334         omap_start_dma(c->dma_channel);
335
336         timeout = jiffies + msecs_to_jiffies(20);
337         done = &c->dma_done.done;
338         while (time_before(jiffies, timeout))
339                 if (*done)
340                         break;
341
342         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
343
344         if (!*done) {
345                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
346                 goto out_copy;
347         }
348
349         return 0;
350
351 out_copy:
352         memcpy(buf, this->base + bram_offset, count);
353         return 0;
354 }
355
356 static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
357                                          const unsigned char *buffer,
358                                          int offset, size_t count)
359 {
360         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
361         struct onenand_chip *this = mtd->priv;
362         dma_addr_t dma_src, dma_dst;
363         int bram_offset;
364         unsigned long timeout;
365         void *buf = (void *)buffer;
366         volatile unsigned *done;
367
368         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
369         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
370                 goto out_copy;
371
372         /* panic_write() may be in an interrupt context */
373         if (in_interrupt())
374                 goto out_copy;
375
376         if (buf >= high_memory) {
377                 struct page *p1;
378
379                 if (((size_t)buf & PAGE_MASK) !=
380                     ((size_t)(buf + count - 1) & PAGE_MASK))
381                         goto out_copy;
382                 p1 = vmalloc_to_page(buf);
383                 if (!p1)
384                         goto out_copy;
385                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
386         }
387
388         dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
389         dma_dst = c->phys_base + bram_offset;
390         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
391                 dev_err(&c->pdev->dev,
392                         "Couldn't DMA map a %d byte buffer\n",
393                         count);
394                 return -1;
395         }
396
397         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
398                                      count >> 2, 1, 0, 0, 0);
399         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
400                                 dma_src, 0, 0);
401         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
402                                  dma_dst, 0, 0);
403
404         INIT_COMPLETION(c->dma_done);
405         omap_start_dma(c->dma_channel);
406
407         timeout = jiffies + msecs_to_jiffies(20);
408         done = &c->dma_done.done;
409         while (time_before(jiffies, timeout))
410                 if (*done)
411                         break;
412
413         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
414
415         if (!*done) {
416                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
417                 goto out_copy;
418         }
419
420         return 0;
421
422 out_copy:
423         memcpy(this->base + bram_offset, buf, count);
424         return 0;
425 }
426
427 #else
428
429 int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
430                                  unsigned char *buffer, int offset,
431                                  size_t count);
432
433 int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
434                                   const unsigned char *buffer,
435                                   int offset, size_t count);
436
437 #endif
438
439 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
440
441 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
442                                         unsigned char *buffer, int offset,
443                                         size_t count)
444 {
445         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
446         struct onenand_chip *this = mtd->priv;
447         dma_addr_t dma_src, dma_dst;
448         int bram_offset;
449
450         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
451         /* DMA is not used.  Revisit PM requirements before enabling it. */
452         if (1 || (c->dma_channel < 0) ||
453             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
454             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
455                 memcpy(buffer, (__force void *)(this->base + bram_offset),
456                        count);
457                 return 0;
458         }
459
460         dma_src = c->phys_base + bram_offset;
461         dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
462                                  DMA_FROM_DEVICE);
463         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
464                 dev_err(&c->pdev->dev,
465                         "Couldn't DMA map a %d byte buffer\n",
466                         count);
467                 return -1;
468         }
469
470         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
471                                      count / 4, 1, 0, 0, 0);
472         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
473                                 dma_src, 0, 0);
474         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
475                                  dma_dst, 0, 0);
476
477         INIT_COMPLETION(c->dma_done);
478         omap_start_dma(c->dma_channel);
479         wait_for_completion(&c->dma_done);
480
481         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
482
483         return 0;
484 }
485
486 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
487                                          const unsigned char *buffer,
488                                          int offset, size_t count)
489 {
490         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
491         struct onenand_chip *this = mtd->priv;
492         dma_addr_t dma_src, dma_dst;
493         int bram_offset;
494
495         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
496         /* DMA is not used.  Revisit PM requirements before enabling it. */
497         if (1 || (c->dma_channel < 0) ||
498             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
499             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
500                 memcpy((__force void *)(this->base + bram_offset), buffer,
501                        count);
502                 return 0;
503         }
504
505         dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
506                                  DMA_TO_DEVICE);
507         dma_dst = c->phys_base + bram_offset;
508         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
509                 dev_err(&c->pdev->dev,
510                         "Couldn't DMA map a %d byte buffer\n",
511                         count);
512                 return -1;
513         }
514
515         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
516                                      count / 2, 1, 0, 0, 0);
517         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
518                                 dma_src, 0, 0);
519         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
520                                  dma_dst, 0, 0);
521
522         INIT_COMPLETION(c->dma_done);
523         omap_start_dma(c->dma_channel);
524         wait_for_completion(&c->dma_done);
525
526         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
527
528         return 0;
529 }
530
531 #else
532
533 int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
534                                  unsigned char *buffer, int offset,
535                                  size_t count);
536
537 int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
538                                   const unsigned char *buffer,
539                                   int offset, size_t count);
540
541 #endif
542
543 static struct platform_driver omap2_onenand_driver;
544
545 static int __adjust_timing(struct device *dev, void *data)
546 {
547         int ret = 0;
548         struct omap2_onenand *c;
549
550         c = dev_get_drvdata(dev);
551
552         BUG_ON(c->setup == NULL);
553
554         /* DMA is not in use so this is all that is needed */
555         /* Revisit for OMAP3! */
556         ret = c->setup(c->onenand.base, c->freq);
557
558         return ret;
559 }
560
561 int omap2_onenand_rephase(void)
562 {
563         return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
564                                       NULL, __adjust_timing);
565 }
566
567 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
568 {
569         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
570
571         /* With certain content in the buffer RAM, the OMAP boot ROM code
572          * can recognize the flash chip incorrectly. Zero it out before
573          * soft reset.
574          */
575         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
576 }
577
578 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
579 {
580         struct omap_onenand_platform_data *pdata;
581         struct omap2_onenand *c;
582         int r;
583
584         pdata = pdev->dev.platform_data;
585         if (pdata == NULL) {
586                 dev_err(&pdev->dev, "platform data missing\n");
587                 return -ENODEV;
588         }
589
590         c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
591         if (!c)
592                 return -ENOMEM;
593
594         init_completion(&c->irq_done);
595         init_completion(&c->dma_done);
596         c->gpmc_cs = pdata->cs;
597         c->gpio_irq = pdata->gpio_irq;
598         c->dma_channel = pdata->dma_channel;
599         if (c->dma_channel < 0) {
600                 /* if -1, don't use DMA */
601                 c->gpio_irq = 0;
602         }
603
604         r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
605         if (r < 0) {
606                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
607                 goto err_kfree;
608         }
609
610         if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
611                                pdev->dev.driver->name) == NULL) {
612                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
613                         "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
614                 r = -EBUSY;
615                 goto err_free_cs;
616         }
617         c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
618         if (c->onenand.base == NULL) {
619                 r = -ENOMEM;
620                 goto err_release_mem_region;
621         }
622
623         if (pdata->onenand_setup != NULL) {
624                 r = pdata->onenand_setup(c->onenand.base, c->freq);
625                 if (r < 0) {
626                         dev_err(&pdev->dev, "Onenand platform setup failed: "
627                                 "%d\n", r);
628                         goto err_iounmap;
629                 }
630                 c->setup = pdata->onenand_setup;
631         }
632
633         if (c->gpio_irq) {
634                 if ((r = omap_request_gpio(c->gpio_irq)) < 0) {
635                         dev_err(&pdev->dev,  "Failed to request GPIO%d for "
636                                 "OneNAND\n", c->gpio_irq);
637                         goto err_iounmap;
638         }
639         omap_set_gpio_direction(c->gpio_irq, 1);
640
641         if ((r = request_irq(OMAP_GPIO_IRQ(c->gpio_irq),
642                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
643                              pdev->dev.driver->name, c)) < 0)
644                 goto err_release_gpio;
645         }
646
647         if (c->dma_channel >= 0) {
648                 r = omap_request_dma(0, pdev->dev.driver->name,
649                                      omap2_onenand_dma_cb, (void *) c,
650                                      &c->dma_channel);
651                 if (r == 0) {
652                         omap_set_dma_write_mode(c->dma_channel,
653                                                 OMAP_DMA_WRITE_NON_POSTED);
654                         omap_set_dma_src_data_pack(c->dma_channel, 1);
655                         omap_set_dma_src_burst_mode(c->dma_channel,
656                                                     OMAP_DMA_DATA_BURST_8);
657                         omap_set_dma_dest_data_pack(c->dma_channel, 1);
658                         omap_set_dma_dest_burst_mode(c->dma_channel,
659                                                      OMAP_DMA_DATA_BURST_8);
660                 } else {
661                         dev_info(&pdev->dev,
662                                  "failed to allocate DMA for OneNAND, "
663                                  "using PIO instead\n");
664                         c->dma_channel = -1;
665                 }
666         }
667
668         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
669                  "base %p\n", c->gpmc_cs, c->phys_base,
670                  c->onenand.base);
671
672         c->pdev = pdev;
673         c->mtd.name = pdev->dev.bus_id;
674         c->mtd.priv = &c->onenand;
675         c->mtd.owner = THIS_MODULE;
676
677         if (c->dma_channel >= 0) {
678                 struct onenand_chip *this = &c->onenand;
679
680                 this->wait = omap2_onenand_wait;
681                 if (cpu_is_omap34xx()) {
682                         this->read_bufferram = omap3_onenand_read_bufferram;
683                         this->write_bufferram = omap3_onenand_write_bufferram;
684                 } else {
685                         this->read_bufferram = omap2_onenand_read_bufferram;
686                         this->write_bufferram = omap2_onenand_write_bufferram;
687                 }
688         }
689
690         if ((r = onenand_scan(&c->mtd, 1)) < 0)
691                 goto err_release_dma;
692
693         switch ((c->onenand.version_id >> 4) & 0xf) {
694         case 0:
695                 c->freq = 40;
696                 break;
697         case 1:
698                 c->freq = 54;
699                 break;
700         case 2:
701                 c->freq = 66;
702                 break;
703         case 3:
704                 c->freq = 83;
705                 break;
706         }
707
708 #ifdef CONFIG_MTD_PARTITIONS
709         if (pdata->parts != NULL)
710                 r = add_mtd_partitions(&c->mtd, pdata->parts,
711                                        pdata->nr_parts);
712         else
713 #endif
714                 r = add_mtd_device(&c->mtd);
715         if (r < 0)
716                 goto err_release_onenand;
717
718         platform_set_drvdata(pdev, c);
719
720         return 0;
721
722 err_release_onenand:
723         onenand_release(&c->mtd);
724 err_release_dma:
725         if (c->dma_channel != -1)
726                 omap_free_dma(c->dma_channel);
727         if (c->gpio_irq)
728                 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
729 err_release_gpio:
730         if (c->gpio_irq)
731                 omap_free_gpio(c->gpio_irq);
732 err_iounmap:
733         iounmap(c->onenand.base);
734 err_release_mem_region:
735         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
736 err_free_cs:
737         gpmc_cs_free(c->gpmc_cs);
738 err_kfree:
739         kfree(c);
740
741         return r;
742 }
743
744 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
745 {
746         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
747
748         BUG_ON(c == NULL);
749
750 #ifdef CONFIG_MTD_PARTITIONS
751         if (c->parts)
752                 del_mtd_partitions(&c->mtd);
753         else
754                 del_mtd_device(&c->mtd);
755 #else
756         del_mtd_device(&c->mtd);
757 #endif
758
759         onenand_release(&c->mtd);
760         if (c->dma_channel != -1)
761                 omap_free_dma(c->dma_channel);
762         omap2_onenand_shutdown(pdev);
763         platform_set_drvdata(pdev, NULL);
764         if (c->gpio_irq) {
765                 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
766                 omap_free_gpio(c->gpio_irq);
767         }
768         iounmap(c->onenand.base);
769         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
770         kfree(c);
771
772         return 0;
773 }
774
775 static struct platform_driver omap2_onenand_driver = {
776         .probe          = omap2_onenand_probe,
777         .remove         = omap2_onenand_remove,
778         .shutdown       = omap2_onenand_shutdown,
779         .driver         = {
780                 .name   = DRIVER_NAME,
781                 .owner  = THIS_MODULE,
782         },
783 };
784
785 static int __init omap2_onenand_init(void)
786 {
787         printk(KERN_INFO "OneNAND driver initializing\n");
788         return platform_driver_register(&omap2_onenand_driver);
789 }
790
791 static void __exit omap2_onenand_exit(void)
792 {
793         platform_driver_unregister(&omap2_onenand_driver);
794 }
795
796 module_init(omap2_onenand_init);
797 module_exit(omap2_onenand_exit);
798
799 MODULE_ALIAS(DRIVER_NAME);
800 MODULE_LICENSE("GPL");
801 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
802 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");