[MTD NAND] Indent all of drivers/mtd/nand/*.c.
[linux-2.6.git] / drivers / mtd / nand / sharpsl.c
1 /*
2  * drivers/mtd/nand/sharpsl.c
3  *
4  *  Copyright (C) 2004 Richard Purdie
5  *
6  *  $Id: sharpsl.c,v 1.7 2005/11/07 11:14:31 gleixner Exp $
7  *
8  *  Based on Sharp's NAND driver sharp_sl.c
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  *
14  */
15
16 #include <linux/genhd.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/nand.h>
22 #include <linux/mtd/nand_ecc.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/interrupt.h>
25 #include <asm/io.h>
26 #include <asm/hardware.h>
27 #include <asm/mach-types.h>
28
29 static void __iomem *sharpsl_io_base;
30 static int sharpsl_phys_base = 0x0C000000;
31
32 /* register offset */
33 #define ECCLPLB         sharpsl_io_base+0x00    /* line parity 7 - 0 bit */
34 #define ECCLPUB         sharpsl_io_base+0x04    /* line parity 15 - 8 bit */
35 #define ECCCP           sharpsl_io_base+0x08    /* column parity 5 - 0 bit */
36 #define ECCCNTR         sharpsl_io_base+0x0C    /* ECC byte counter */
37 #define ECCCLRR         sharpsl_io_base+0x10    /* cleare ECC */
38 #define FLASHIO         sharpsl_io_base+0x14    /* Flash I/O */
39 #define FLASHCTL        sharpsl_io_base+0x18    /* Flash Control */
40
41 /* Flash control bit */
42 #define FLRYBY          (1 << 5)
43 #define FLCE1           (1 << 4)
44 #define FLWP            (1 << 3)
45 #define FLALE           (1 << 2)
46 #define FLCLE           (1 << 1)
47 #define FLCE0           (1 << 0)
48
49 /*
50  * MTD structure for SharpSL
51  */
52 static struct mtd_info *sharpsl_mtd = NULL;
53
54 /*
55  * Define partitions for flash device
56  */
57 #define DEFAULT_NUM_PARTITIONS 3
58
59 static int nr_partitions;
60 static struct mtd_partition sharpsl_nand_default_partition_info[] = {
61         {
62          .name = "System Area",
63          .offset = 0,
64          .size = 7 * 1024 * 1024,
65          },
66         {
67          .name = "Root Filesystem",
68          .offset = 7 * 1024 * 1024,
69          .size = 30 * 1024 * 1024,
70          },
71         {
72          .name = "Home Filesystem",
73          .offset = MTDPART_OFS_APPEND,
74          .size = MTDPART_SIZ_FULL,
75          },
76 };
77
78 /*
79  *      hardware specific access to control-lines
80  */
81 static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd)
82 {
83         switch (cmd) {
84         case NAND_CTL_SETCLE:
85                 writeb(readb(FLASHCTL) | FLCLE, FLASHCTL);
86                 break;
87         case NAND_CTL_CLRCLE:
88                 writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL);
89                 break;
90
91         case NAND_CTL_SETALE:
92                 writeb(readb(FLASHCTL) | FLALE, FLASHCTL);
93                 break;
94         case NAND_CTL_CLRALE:
95                 writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL);
96                 break;
97
98         case NAND_CTL_SETNCE:
99                 writeb(readb(FLASHCTL) & ~(FLCE0 | FLCE1), FLASHCTL);
100                 break;
101         case NAND_CTL_CLRNCE:
102                 writeb(readb(FLASHCTL) | (FLCE0 | FLCE1), FLASHCTL);
103                 break;
104         }
105 }
106
107 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
108
109 static struct nand_bbt_descr sharpsl_bbt = {
110         .options = 0,
111         .offs = 4,
112         .len = 2,
113         .pattern = scan_ff_pattern
114 };
115
116 static struct nand_bbt_descr sharpsl_akita_bbt = {
117         .options = 0,
118         .offs = 4,
119         .len = 1,
120         .pattern = scan_ff_pattern
121 };
122
123 static struct nand_oobinfo akita_oobinfo = {
124         .useecc = MTD_NANDECC_AUTOPLACE,
125         .eccbytes = 24,
126         .eccpos = {
127                    0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
128                    0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
129                    0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
130         .oobfree = {{0x08, 0x09}}
131 };
132
133 static int sharpsl_nand_dev_ready(struct mtd_info *mtd)
134 {
135         return !((readb(FLASHCTL) & FLRYBY) == 0);
136 }
137
138 static void sharpsl_nand_enable_hwecc(struct mtd_info *mtd, int mode)
139 {
140         writeb(0, ECCCLRR);
141 }
142
143 static int sharpsl_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code)
144 {
145         ecc_code[0] = ~readb(ECCLPUB);
146         ecc_code[1] = ~readb(ECCLPLB);
147         ecc_code[2] = (~readb(ECCCP) << 2) | 0x03;
148         return readb(ECCCNTR) != 0;
149 }
150
151 #ifdef CONFIG_MTD_PARTITIONS
152 const char *part_probes[] = { "cmdlinepart", NULL };
153 #endif
154
155 /*
156  * Main initialization routine
157  */
158 int __init sharpsl_nand_init(void)
159 {
160         struct nand_chip *this;
161         struct mtd_partition *sharpsl_partition_info;
162         int err = 0;
163
164         /* Allocate memory for MTD device structure and private data */
165         sharpsl_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
166         if (!sharpsl_mtd) {
167                 printk("Unable to allocate SharpSL NAND MTD device structure.\n");
168                 return -ENOMEM;
169         }
170
171         /* map physical adress */
172         sharpsl_io_base = ioremap(sharpsl_phys_base, 0x1000);
173         if (!sharpsl_io_base) {
174                 printk("ioremap to access Sharp SL NAND chip failed\n");
175                 kfree(sharpsl_mtd);
176                 return -EIO;
177         }
178
179         /* Get pointer to private data */
180         this = (struct nand_chip *)(&sharpsl_mtd[1]);
181
182         /* Initialize structures */
183         memset(sharpsl_mtd, 0, sizeof(struct mtd_info));
184         memset(this, 0, sizeof(struct nand_chip));
185
186         /* Link the private data with the MTD structure */
187         sharpsl_mtd->priv = this;
188
189         /*
190          * PXA initialize
191          */
192         writeb(readb(FLASHCTL) | FLWP, FLASHCTL);
193
194         /* Set address of NAND IO lines */
195         this->IO_ADDR_R = FLASHIO;
196         this->IO_ADDR_W = FLASHIO;
197         /* Set address of hardware control function */
198         this->hwcontrol = sharpsl_nand_hwcontrol;
199         this->dev_ready = sharpsl_nand_dev_ready;
200         /* 15 us command delay time */
201         this->chip_delay = 15;
202         /* set eccmode using hardware ECC */
203         this->eccmode = NAND_ECC_HW3_256;
204         this->badblock_pattern = &sharpsl_bbt;
205         if (machine_is_akita() || machine_is_borzoi()) {
206                 this->badblock_pattern = &sharpsl_akita_bbt;
207                 this->autooob = &akita_oobinfo;
208         }
209         this->enable_hwecc = sharpsl_nand_enable_hwecc;
210         this->calculate_ecc = sharpsl_nand_calculate_ecc;
211         this->correct_data = nand_correct_data;
212
213         /* Scan to find existence of the device */
214         err = nand_scan(sharpsl_mtd, 1);
215         if (err) {
216                 iounmap(sharpsl_io_base);
217                 kfree(sharpsl_mtd);
218                 return err;
219         }
220
221         /* Register the partitions */
222         sharpsl_mtd->name = "sharpsl-nand";
223         nr_partitions = parse_mtd_partitions(sharpsl_mtd, part_probes, &sharpsl_partition_info, 0);
224
225         if (nr_partitions <= 0) {
226                 nr_partitions = DEFAULT_NUM_PARTITIONS;
227                 sharpsl_partition_info = sharpsl_nand_default_partition_info;
228                 if (machine_is_poodle()) {
229                         sharpsl_partition_info[1].size = 22 * 1024 * 1024;
230                 } else if (machine_is_corgi() || machine_is_shepherd()) {
231                         sharpsl_partition_info[1].size = 25 * 1024 * 1024;
232                 } else if (machine_is_husky()) {
233                         sharpsl_partition_info[1].size = 53 * 1024 * 1024;
234                 } else if (machine_is_spitz()) {
235                         sharpsl_partition_info[1].size = 5 * 1024 * 1024;
236                 } else if (machine_is_akita()) {
237                         sharpsl_partition_info[1].size = 58 * 1024 * 1024;
238                 } else if (machine_is_borzoi()) {
239                         sharpsl_partition_info[1].size = 32 * 1024 * 1024;
240                 }
241         }
242
243         if (machine_is_husky() || machine_is_borzoi() || machine_is_akita()) {
244                 /* Need to use small eraseblock size for backward compatibility */
245                 sharpsl_mtd->flags |= MTD_NO_VIRTBLOCKS;
246         }
247
248         add_mtd_partitions(sharpsl_mtd, sharpsl_partition_info, nr_partitions);
249
250         /* Return happy */
251         return 0;
252 }
253
254 module_init(sharpsl_nand_init);
255
256 /*
257  * Clean up routine
258  */
259 #ifdef MODULE
260 static void __exit sharpsl_nand_cleanup(void)
261 {
262         struct nand_chip *this = (struct nand_chip *)&sharpsl_mtd[1];
263
264         /* Release resources, unregister device */
265         nand_release(sharpsl_mtd);
266
267         iounmap(sharpsl_io_base);
268
269         /* Free the MTD device structure */
270         kfree(sharpsl_mtd);
271 }
272
273 module_exit(sharpsl_nand_cleanup);
274 #endif
275
276 MODULE_LICENSE("GPL");
277 MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
278 MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series");