mtd: s3c nand: parsing command-line partitions prior to set->partitions
[linux-2.6.git] / drivers / mtd / nand / s3c2410.c
1 /* linux/drivers/mtd/nand/s3c2410.c
2  *
3  * Copyright © 2004-2008 Simtec Electronics
4  *      http://armlinux.simtec.co.uk/
5  *      Ben Dooks <ben@simtec.co.uk>
6  *
7  * Samsung S3C2410/S3C2440/S3C2412 NAND driver
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
22 */
23
24 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
25 #define DEBUG
26 #endif
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/string.h>
33 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/delay.h>
36 #include <linux/err.h>
37 #include <linux/slab.h>
38 #include <linux/clk.h>
39 #include <linux/cpufreq.h>
40
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/nand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/partitions.h>
45
46 #include <asm/io.h>
47
48 #include <plat/regs-nand.h>
49 #include <plat/nand.h>
50
51 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
52 static int hardware_ecc = 1;
53 #else
54 static int hardware_ecc = 0;
55 #endif
56
57 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
58 static int clock_stop = 1;
59 #else
60 static const int clock_stop = 0;
61 #endif
62
63
64 /* new oob placement block for use with hardware ecc generation
65  */
66
67 static struct nand_ecclayout nand_hw_eccoob = {
68         .eccbytes = 3,
69         .eccpos = {0, 1, 2},
70         .oobfree = {{8, 8}}
71 };
72
73 /* controller and mtd information */
74
75 struct s3c2410_nand_info;
76
77 /**
78  * struct s3c2410_nand_mtd - driver MTD structure
79  * @mtd: The MTD instance to pass to the MTD layer.
80  * @chip: The NAND chip information.
81  * @set: The platform information supplied for this set of NAND chips.
82  * @info: Link back to the hardware information.
83  * @scan_res: The result from calling nand_scan_ident().
84 */
85 struct s3c2410_nand_mtd {
86         struct mtd_info                 mtd;
87         struct nand_chip                chip;
88         struct s3c2410_nand_set         *set;
89         struct s3c2410_nand_info        *info;
90         int                             scan_res;
91 };
92
93 enum s3c_cpu_type {
94         TYPE_S3C2410,
95         TYPE_S3C2412,
96         TYPE_S3C2440,
97 };
98
99 /* overview of the s3c2410 nand state */
100
101 /**
102  * struct s3c2410_nand_info - NAND controller state.
103  * @mtds: An array of MTD instances on this controoler.
104  * @platform: The platform data for this board.
105  * @device: The platform device we bound to.
106  * @area: The IO area resource that came from request_mem_region().
107  * @clk: The clock resource for this controller.
108  * @regs: The area mapped for the hardware registers described by @area.
109  * @sel_reg: Pointer to the register controlling the NAND selection.
110  * @sel_bit: The bit in @sel_reg to select the NAND chip.
111  * @mtd_count: The number of MTDs created from this controller.
112  * @save_sel: The contents of @sel_reg to be saved over suspend.
113  * @clk_rate: The clock rate from @clk.
114  * @cpu_type: The exact type of this controller.
115  */
116 struct s3c2410_nand_info {
117         /* mtd info */
118         struct nand_hw_control          controller;
119         struct s3c2410_nand_mtd         *mtds;
120         struct s3c2410_platform_nand    *platform;
121
122         /* device info */
123         struct device                   *device;
124         struct resource                 *area;
125         struct clk                      *clk;
126         void __iomem                    *regs;
127         void __iomem                    *sel_reg;
128         int                             sel_bit;
129         int                             mtd_count;
130         unsigned long                   save_sel;
131         unsigned long                   clk_rate;
132
133         enum s3c_cpu_type               cpu_type;
134
135 #ifdef CONFIG_CPU_FREQ
136         struct notifier_block   freq_transition;
137 #endif
138 };
139
140 /* conversion functions */
141
142 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
143 {
144         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
145 }
146
147 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
148 {
149         return s3c2410_nand_mtd_toours(mtd)->info;
150 }
151
152 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
153 {
154         return platform_get_drvdata(dev);
155 }
156
157 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
158 {
159         return dev->dev.platform_data;
160 }
161
162 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
163 {
164         return clock_stop;
165 }
166
167 /* timing calculations */
168
169 #define NS_IN_KHZ 1000000
170
171 /**
172  * s3c_nand_calc_rate - calculate timing data.
173  * @wanted: The cycle time in nanoseconds.
174  * @clk: The clock rate in kHz.
175  * @max: The maximum divider value.
176  *
177  * Calculate the timing value from the given parameters.
178  */
179 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
180 {
181         int result;
182
183         result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
184
185         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
186
187         if (result > max) {
188                 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
189                 return -1;
190         }
191
192         if (result < 1)
193                 result = 1;
194
195         return result;
196 }
197
198 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
199
200 /* controller setup */
201
202 /**
203  * s3c2410_nand_setrate - setup controller timing information.
204  * @info: The controller instance.
205  *
206  * Given the information supplied by the platform, calculate and set
207  * the necessary timing registers in the hardware to generate the
208  * necessary timing cycles to the hardware.
209  */
210 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
211 {
212         struct s3c2410_platform_nand *plat = info->platform;
213         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
214         int tacls, twrph0, twrph1;
215         unsigned long clkrate = clk_get_rate(info->clk);
216         unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
217         unsigned long flags;
218
219         /* calculate the timing information for the controller */
220
221         info->clk_rate = clkrate;
222         clkrate /= 1000;        /* turn clock into kHz for ease of use */
223
224         if (plat != NULL) {
225                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
226                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
227                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
228         } else {
229                 /* default timings */
230                 tacls = tacls_max;
231                 twrph0 = 8;
232                 twrph1 = 8;
233         }
234
235         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
236                 dev_err(info->device, "cannot get suitable timings\n");
237                 return -EINVAL;
238         }
239
240         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
241                tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
242
243         switch (info->cpu_type) {
244         case TYPE_S3C2410:
245                 mask = (S3C2410_NFCONF_TACLS(3) |
246                         S3C2410_NFCONF_TWRPH0(7) |
247                         S3C2410_NFCONF_TWRPH1(7));
248                 set = S3C2410_NFCONF_EN;
249                 set |= S3C2410_NFCONF_TACLS(tacls - 1);
250                 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
251                 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
252                 break;
253
254         case TYPE_S3C2440:
255         case TYPE_S3C2412:
256                 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
257                         S3C2440_NFCONF_TWRPH0(7) |
258                         S3C2440_NFCONF_TWRPH1(7));
259
260                 set = S3C2440_NFCONF_TACLS(tacls - 1);
261                 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
262                 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
263                 break;
264
265         default:
266                 BUG();
267         }
268
269         local_irq_save(flags);
270
271         cfg = readl(info->regs + S3C2410_NFCONF);
272         cfg &= ~mask;
273         cfg |= set;
274         writel(cfg, info->regs + S3C2410_NFCONF);
275
276         local_irq_restore(flags);
277
278         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
279
280         return 0;
281 }
282
283 /**
284  * s3c2410_nand_inithw - basic hardware initialisation
285  * @info: The hardware state.
286  *
287  * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
288  * to setup the hardware access speeds and set the controller to be enabled.
289 */
290 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
291 {
292         int ret;
293
294         ret = s3c2410_nand_setrate(info);
295         if (ret < 0)
296                 return ret;
297
298         switch (info->cpu_type) {
299         case TYPE_S3C2410:
300         default:
301                 break;
302
303         case TYPE_S3C2440:
304         case TYPE_S3C2412:
305                 /* enable the controller and de-assert nFCE */
306
307                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
308         }
309
310         return 0;
311 }
312
313 /**
314  * s3c2410_nand_select_chip - select the given nand chip
315  * @mtd: The MTD instance for this chip.
316  * @chip: The chip number.
317  *
318  * This is called by the MTD layer to either select a given chip for the
319  * @mtd instance, or to indicate that the access has finished and the
320  * chip can be de-selected.
321  *
322  * The routine ensures that the nFCE line is correctly setup, and any
323  * platform specific selection code is called to route nFCE to the specific
324  * chip.
325  */
326 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
327 {
328         struct s3c2410_nand_info *info;
329         struct s3c2410_nand_mtd *nmtd;
330         struct nand_chip *this = mtd->priv;
331         unsigned long cur;
332
333         nmtd = this->priv;
334         info = nmtd->info;
335
336         if (chip != -1 && allow_clk_stop(info))
337                 clk_enable(info->clk);
338
339         cur = readl(info->sel_reg);
340
341         if (chip == -1) {
342                 cur |= info->sel_bit;
343         } else {
344                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
345                         dev_err(info->device, "invalid chip %d\n", chip);
346                         return;
347                 }
348
349                 if (info->platform != NULL) {
350                         if (info->platform->select_chip != NULL)
351                                 (info->platform->select_chip) (nmtd->set, chip);
352                 }
353
354                 cur &= ~info->sel_bit;
355         }
356
357         writel(cur, info->sel_reg);
358
359         if (chip == -1 && allow_clk_stop(info))
360                 clk_disable(info->clk);
361 }
362
363 /* s3c2410_nand_hwcontrol
364  *
365  * Issue command and address cycles to the chip
366 */
367
368 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
369                                    unsigned int ctrl)
370 {
371         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
372
373         if (cmd == NAND_CMD_NONE)
374                 return;
375
376         if (ctrl & NAND_CLE)
377                 writeb(cmd, info->regs + S3C2410_NFCMD);
378         else
379                 writeb(cmd, info->regs + S3C2410_NFADDR);
380 }
381
382 /* command and control functions */
383
384 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
385                                    unsigned int ctrl)
386 {
387         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
388
389         if (cmd == NAND_CMD_NONE)
390                 return;
391
392         if (ctrl & NAND_CLE)
393                 writeb(cmd, info->regs + S3C2440_NFCMD);
394         else
395                 writeb(cmd, info->regs + S3C2440_NFADDR);
396 }
397
398 /* s3c2410_nand_devready()
399  *
400  * returns 0 if the nand is busy, 1 if it is ready
401 */
402
403 static int s3c2410_nand_devready(struct mtd_info *mtd)
404 {
405         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
406         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
407 }
408
409 static int s3c2440_nand_devready(struct mtd_info *mtd)
410 {
411         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
412         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
413 }
414
415 static int s3c2412_nand_devready(struct mtd_info *mtd)
416 {
417         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
418         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
419 }
420
421 /* ECC handling functions */
422
423 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
424                                      u_char *read_ecc, u_char *calc_ecc)
425 {
426         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
427         unsigned int diff0, diff1, diff2;
428         unsigned int bit, byte;
429
430         pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
431
432         diff0 = read_ecc[0] ^ calc_ecc[0];
433         diff1 = read_ecc[1] ^ calc_ecc[1];
434         diff2 = read_ecc[2] ^ calc_ecc[2];
435
436         pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
437                  __func__,
438                  read_ecc[0], read_ecc[1], read_ecc[2],
439                  calc_ecc[0], calc_ecc[1], calc_ecc[2],
440                  diff0, diff1, diff2);
441
442         if (diff0 == 0 && diff1 == 0 && diff2 == 0)
443                 return 0;               /* ECC is ok */
444
445         /* sometimes people do not think about using the ECC, so check
446          * to see if we have an 0xff,0xff,0xff read ECC and then ignore
447          * the error, on the assumption that this is an un-eccd page.
448          */
449         if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
450             && info->platform->ignore_unset_ecc)
451                 return 0;
452
453         /* Can we correct this ECC (ie, one row and column change).
454          * Note, this is similar to the 256 error code on smartmedia */
455
456         if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
457             ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
458             ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
459                 /* calculate the bit position of the error */
460
461                 bit  = ((diff2 >> 3) & 1) |
462                        ((diff2 >> 4) & 2) |
463                        ((diff2 >> 5) & 4);
464
465                 /* calculate the byte position of the error */
466
467                 byte = ((diff2 << 7) & 0x100) |
468                        ((diff1 << 0) & 0x80)  |
469                        ((diff1 << 1) & 0x40)  |
470                        ((diff1 << 2) & 0x20)  |
471                        ((diff1 << 3) & 0x10)  |
472                        ((diff0 >> 4) & 0x08)  |
473                        ((diff0 >> 3) & 0x04)  |
474                        ((diff0 >> 2) & 0x02)  |
475                        ((diff0 >> 1) & 0x01);
476
477                 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
478                         bit, byte);
479
480                 dat[byte] ^= (1 << bit);
481                 return 1;
482         }
483
484         /* if there is only one bit difference in the ECC, then
485          * one of only a row or column parity has changed, which
486          * means the error is most probably in the ECC itself */
487
488         diff0 |= (diff1 << 8);
489         diff0 |= (diff2 << 16);
490
491         if ((diff0 & ~(1<<fls(diff0))) == 0)
492                 return 1;
493
494         return -1;
495 }
496
497 /* ECC functions
498  *
499  * These allow the s3c2410 and s3c2440 to use the controller's ECC
500  * generator block to ECC the data as it passes through]
501 */
502
503 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
504 {
505         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
506         unsigned long ctrl;
507
508         ctrl = readl(info->regs + S3C2410_NFCONF);
509         ctrl |= S3C2410_NFCONF_INITECC;
510         writel(ctrl, info->regs + S3C2410_NFCONF);
511 }
512
513 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
514 {
515         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
516         unsigned long ctrl;
517
518         ctrl = readl(info->regs + S3C2440_NFCONT);
519         writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT);
520 }
521
522 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
523 {
524         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
525         unsigned long ctrl;
526
527         ctrl = readl(info->regs + S3C2440_NFCONT);
528         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
529 }
530
531 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
532 {
533         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
534
535         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
536         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
537         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
538
539         pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
540                  ecc_code[0], ecc_code[1], ecc_code[2]);
541
542         return 0;
543 }
544
545 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
546 {
547         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
548         unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
549
550         ecc_code[0] = ecc;
551         ecc_code[1] = ecc >> 8;
552         ecc_code[2] = ecc >> 16;
553
554         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
555
556         return 0;
557 }
558
559 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
560 {
561         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
562         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
563
564         ecc_code[0] = ecc;
565         ecc_code[1] = ecc >> 8;
566         ecc_code[2] = ecc >> 16;
567
568         pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
569
570         return 0;
571 }
572
573 /* over-ride the standard functions for a little more speed. We can
574  * use read/write block to move the data buffers to/from the controller
575 */
576
577 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
578 {
579         struct nand_chip *this = mtd->priv;
580         readsb(this->IO_ADDR_R, buf, len);
581 }
582
583 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
584 {
585         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
586
587         readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
588
589         /* cleanup if we've got less than a word to do */
590         if (len & 3) {
591                 buf += len & ~3;
592
593                 for (; len & 3; len--)
594                         *buf++ = readb(info->regs + S3C2440_NFDATA);
595         }
596 }
597
598 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
599 {
600         struct nand_chip *this = mtd->priv;
601         writesb(this->IO_ADDR_W, buf, len);
602 }
603
604 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
605 {
606         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
607
608         writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
609
610         /* cleanup any fractional write */
611         if (len & 3) {
612                 buf += len & ~3;
613
614                 for (; len & 3; len--, buf++)
615                         writeb(*buf, info->regs + S3C2440_NFDATA);
616         }
617 }
618
619 /* cpufreq driver support */
620
621 #ifdef CONFIG_CPU_FREQ
622
623 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
624                                           unsigned long val, void *data)
625 {
626         struct s3c2410_nand_info *info;
627         unsigned long newclk;
628
629         info = container_of(nb, struct s3c2410_nand_info, freq_transition);
630         newclk = clk_get_rate(info->clk);
631
632         if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
633             (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
634                 s3c2410_nand_setrate(info);
635         }
636
637         return 0;
638 }
639
640 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
641 {
642         info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
643
644         return cpufreq_register_notifier(&info->freq_transition,
645                                          CPUFREQ_TRANSITION_NOTIFIER);
646 }
647
648 static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
649 {
650         cpufreq_unregister_notifier(&info->freq_transition,
651                                     CPUFREQ_TRANSITION_NOTIFIER);
652 }
653
654 #else
655 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
656 {
657         return 0;
658 }
659
660 static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
661 {
662 }
663 #endif
664
665 /* device management functions */
666
667 static int s3c24xx_nand_remove(struct platform_device *pdev)
668 {
669         struct s3c2410_nand_info *info = to_nand_info(pdev);
670
671         platform_set_drvdata(pdev, NULL);
672
673         if (info == NULL)
674                 return 0;
675
676         s3c2410_nand_cpufreq_deregister(info);
677
678         /* Release all our mtds  and their partitions, then go through
679          * freeing the resources used
680          */
681
682         if (info->mtds != NULL) {
683                 struct s3c2410_nand_mtd *ptr = info->mtds;
684                 int mtdno;
685
686                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
687                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
688                         nand_release(&ptr->mtd);
689                 }
690
691                 kfree(info->mtds);
692         }
693
694         /* free the common resources */
695
696         if (info->clk != NULL && !IS_ERR(info->clk)) {
697                 if (!allow_clk_stop(info))
698                         clk_disable(info->clk);
699                 clk_put(info->clk);
700         }
701
702         if (info->regs != NULL) {
703                 iounmap(info->regs);
704                 info->regs = NULL;
705         }
706
707         if (info->area != NULL) {
708                 release_resource(info->area);
709                 kfree(info->area);
710                 info->area = NULL;
711         }
712
713         kfree(info);
714
715         return 0;
716 }
717
718 #ifdef CONFIG_MTD_PARTITIONS
719 const char *part_probes[] = { "cmdlinepart", NULL };
720 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
721                                       struct s3c2410_nand_mtd *mtd,
722                                       struct s3c2410_nand_set *set)
723 {
724         struct mtd_partition *part_info;
725         int nr_part = 0;
726
727         if (set == NULL)
728                 return add_mtd_device(&mtd->mtd);
729
730         mtd->mtd.name = set->name;
731         nr_part = parse_mtd_partitions(&mtd->mtd, part_probes, &part_info, 0);
732
733         if (nr_part <= 0 && set->nr_partitions > 0) {
734                 nr_part = set->nr_partitions;
735                 part_info = set->partitions;
736         }
737
738         if (nr_part > 0 && part_info)
739                 return add_mtd_partitions(&mtd->mtd, part_info, nr_part);
740
741         return add_mtd_device(&mtd->mtd);
742 }
743 #else
744 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
745                                       struct s3c2410_nand_mtd *mtd,
746                                       struct s3c2410_nand_set *set)
747 {
748         return add_mtd_device(&mtd->mtd);
749 }
750 #endif
751
752 /**
753  * s3c2410_nand_init_chip - initialise a single instance of an chip
754  * @info: The base NAND controller the chip is on.
755  * @nmtd: The new controller MTD instance to fill in.
756  * @set: The information passed from the board specific platform data.
757  *
758  * Initialise the given @nmtd from the information in @info and @set. This
759  * readies the structure for use with the MTD layer functions by ensuring
760  * all pointers are setup and the necessary control routines selected.
761  */
762 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
763                                    struct s3c2410_nand_mtd *nmtd,
764                                    struct s3c2410_nand_set *set)
765 {
766         struct nand_chip *chip = &nmtd->chip;
767         void __iomem *regs = info->regs;
768
769         chip->write_buf    = s3c2410_nand_write_buf;
770         chip->read_buf     = s3c2410_nand_read_buf;
771         chip->select_chip  = s3c2410_nand_select_chip;
772         chip->chip_delay   = 50;
773         chip->priv         = nmtd;
774         chip->options      = set->options;
775         chip->controller   = &info->controller;
776
777         switch (info->cpu_type) {
778         case TYPE_S3C2410:
779                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
780                 info->sel_reg   = regs + S3C2410_NFCONF;
781                 info->sel_bit   = S3C2410_NFCONF_nFCE;
782                 chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
783                 chip->dev_ready = s3c2410_nand_devready;
784                 break;
785
786         case TYPE_S3C2440:
787                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
788                 info->sel_reg   = regs + S3C2440_NFCONT;
789                 info->sel_bit   = S3C2440_NFCONT_nFCE;
790                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
791                 chip->dev_ready = s3c2440_nand_devready;
792                 chip->read_buf  = s3c2440_nand_read_buf;
793                 chip->write_buf = s3c2440_nand_write_buf;
794                 break;
795
796         case TYPE_S3C2412:
797                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
798                 info->sel_reg   = regs + S3C2440_NFCONT;
799                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
800                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
801                 chip->dev_ready = s3c2412_nand_devready;
802
803                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
804                         dev_info(info->device, "System booted from NAND\n");
805
806                 break;
807         }
808
809         chip->IO_ADDR_R = chip->IO_ADDR_W;
810
811         nmtd->info         = info;
812         nmtd->mtd.priv     = chip;
813         nmtd->mtd.owner    = THIS_MODULE;
814         nmtd->set          = set;
815
816         if (hardware_ecc) {
817                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
818                 chip->ecc.correct   = s3c2410_nand_correct_data;
819                 chip->ecc.mode      = NAND_ECC_HW;
820
821                 switch (info->cpu_type) {
822                 case TYPE_S3C2410:
823                         chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
824                         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
825                         break;
826
827                 case TYPE_S3C2412:
828                         chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
829                         chip->ecc.calculate = s3c2412_nand_calculate_ecc;
830                         break;
831
832                 case TYPE_S3C2440:
833                         chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
834                         chip->ecc.calculate = s3c2440_nand_calculate_ecc;
835                         break;
836
837                 }
838         } else {
839                 chip->ecc.mode      = NAND_ECC_SOFT;
840         }
841
842         if (set->ecc_layout != NULL)
843                 chip->ecc.layout = set->ecc_layout;
844
845         if (set->disable_ecc)
846                 chip->ecc.mode  = NAND_ECC_NONE;
847
848         switch (chip->ecc.mode) {
849         case NAND_ECC_NONE:
850                 dev_info(info->device, "NAND ECC disabled\n");
851                 break;
852         case NAND_ECC_SOFT:
853                 dev_info(info->device, "NAND soft ECC\n");
854                 break;
855         case NAND_ECC_HW:
856                 dev_info(info->device, "NAND hardware ECC\n");
857                 break;
858         default:
859                 dev_info(info->device, "NAND ECC UNKNOWN\n");
860                 break;
861         }
862
863         /* If you use u-boot BBT creation code, specifying this flag will
864          * let the kernel fish out the BBT from the NAND, and also skip the
865          * full NAND scan that can take 1/2s or so. Little things... */
866         if (set->flash_bbt)
867                 chip->options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
868 }
869
870 /**
871  * s3c2410_nand_update_chip - post probe update
872  * @info: The controller instance.
873  * @nmtd: The driver version of the MTD instance.
874  *
875  * This routine is called after the chip probe has successfully completed
876  * and the relevant per-chip information updated. This call ensure that
877  * we update the internal state accordingly.
878  *
879  * The internal state is currently limited to the ECC state information.
880 */
881 static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
882                                      struct s3c2410_nand_mtd *nmtd)
883 {
884         struct nand_chip *chip = &nmtd->chip;
885
886         dev_dbg(info->device, "chip %p => page shift %d\n",
887                 chip, chip->page_shift);
888
889         if (chip->ecc.mode != NAND_ECC_HW)
890                 return;
891
892                 /* change the behaviour depending on wether we are using
893                  * the large or small page nand device */
894
895         if (chip->page_shift > 10) {
896                 chip->ecc.size      = 256;
897                 chip->ecc.bytes     = 3;
898         } else {
899                 chip->ecc.size      = 512;
900                 chip->ecc.bytes     = 3;
901                 chip->ecc.layout    = &nand_hw_eccoob;
902         }
903 }
904
905 /* s3c24xx_nand_probe
906  *
907  * called by device layer when it finds a device matching
908  * one our driver can handled. This code checks to see if
909  * it can allocate all necessary resources then calls the
910  * nand layer to look for devices
911 */
912 static int s3c24xx_nand_probe(struct platform_device *pdev)
913 {
914         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
915         enum s3c_cpu_type cpu_type; 
916         struct s3c2410_nand_info *info;
917         struct s3c2410_nand_mtd *nmtd;
918         struct s3c2410_nand_set *sets;
919         struct resource *res;
920         int err = 0;
921         int size;
922         int nr_sets;
923         int setno;
924
925         cpu_type = platform_get_device_id(pdev)->driver_data;
926
927         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
928
929         info = kzalloc(sizeof(*info), GFP_KERNEL);
930         if (info == NULL) {
931                 dev_err(&pdev->dev, "no memory for flash info\n");
932                 err = -ENOMEM;
933                 goto exit_error;
934         }
935
936         platform_set_drvdata(pdev, info);
937
938         spin_lock_init(&info->controller.lock);
939         init_waitqueue_head(&info->controller.wq);
940
941         /* get the clock source and enable it */
942
943         info->clk = clk_get(&pdev->dev, "nand");
944         if (IS_ERR(info->clk)) {
945                 dev_err(&pdev->dev, "failed to get clock\n");
946                 err = -ENOENT;
947                 goto exit_error;
948         }
949
950         clk_enable(info->clk);
951
952         /* allocate and map the resource */
953
954         /* currently we assume we have the one resource */
955         res  = pdev->resource;
956         size = resource_size(res);
957
958         info->area = request_mem_region(res->start, size, pdev->name);
959
960         if (info->area == NULL) {
961                 dev_err(&pdev->dev, "cannot reserve register region\n");
962                 err = -ENOENT;
963                 goto exit_error;
964         }
965
966         info->device     = &pdev->dev;
967         info->platform   = plat;
968         info->regs       = ioremap(res->start, size);
969         info->cpu_type   = cpu_type;
970
971         if (info->regs == NULL) {
972                 dev_err(&pdev->dev, "cannot reserve register region\n");
973                 err = -EIO;
974                 goto exit_error;
975         }
976
977         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
978
979         /* initialise the hardware */
980
981         err = s3c2410_nand_inithw(info);
982         if (err != 0)
983                 goto exit_error;
984
985         sets = (plat != NULL) ? plat->sets : NULL;
986         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
987
988         info->mtd_count = nr_sets;
989
990         /* allocate our information */
991
992         size = nr_sets * sizeof(*info->mtds);
993         info->mtds = kzalloc(size, GFP_KERNEL);
994         if (info->mtds == NULL) {
995                 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
996                 err = -ENOMEM;
997                 goto exit_error;
998         }
999
1000         /* initialise all possible chips */
1001
1002         nmtd = info->mtds;
1003
1004         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
1005                 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
1006
1007                 s3c2410_nand_init_chip(info, nmtd, sets);
1008
1009                 nmtd->scan_res = nand_scan_ident(&nmtd->mtd,
1010                                                  (sets) ? sets->nr_chips : 1,
1011                                                  NULL);
1012
1013                 if (nmtd->scan_res == 0) {
1014                         s3c2410_nand_update_chip(info, nmtd);
1015                         nand_scan_tail(&nmtd->mtd);
1016                         s3c2410_nand_add_partition(info, nmtd, sets);
1017                 }
1018
1019                 if (sets != NULL)
1020                         sets++;
1021         }
1022
1023         err = s3c2410_nand_cpufreq_register(info);
1024         if (err < 0) {
1025                 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1026                 goto exit_error;
1027         }
1028
1029         if (allow_clk_stop(info)) {
1030                 dev_info(&pdev->dev, "clock idle support enabled\n");
1031                 clk_disable(info->clk);
1032         }
1033
1034         pr_debug("initialised ok\n");
1035         return 0;
1036
1037  exit_error:
1038         s3c24xx_nand_remove(pdev);
1039
1040         if (err == 0)
1041                 err = -EINVAL;
1042         return err;
1043 }
1044
1045 /* PM Support */
1046 #ifdef CONFIG_PM
1047
1048 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1049 {
1050         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1051
1052         if (info) {
1053                 info->save_sel = readl(info->sel_reg);
1054
1055                 /* For the moment, we must ensure nFCE is high during
1056                  * the time we are suspended. This really should be
1057                  * handled by suspending the MTDs we are using, but
1058                  * that is currently not the case. */
1059
1060                 writel(info->save_sel | info->sel_bit, info->sel_reg);
1061
1062                 if (!allow_clk_stop(info))
1063                         clk_disable(info->clk);
1064         }
1065
1066         return 0;
1067 }
1068
1069 static int s3c24xx_nand_resume(struct platform_device *dev)
1070 {
1071         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1072         unsigned long sel;
1073
1074         if (info) {
1075                 clk_enable(info->clk);
1076                 s3c2410_nand_inithw(info);
1077
1078                 /* Restore the state of the nFCE line. */
1079
1080                 sel = readl(info->sel_reg);
1081                 sel &= ~info->sel_bit;
1082                 sel |= info->save_sel & info->sel_bit;
1083                 writel(sel, info->sel_reg);
1084
1085                 if (allow_clk_stop(info))
1086                         clk_disable(info->clk);
1087         }
1088
1089         return 0;
1090 }
1091
1092 #else
1093 #define s3c24xx_nand_suspend NULL
1094 #define s3c24xx_nand_resume NULL
1095 #endif
1096
1097 /* driver device registration */
1098
1099 static struct platform_device_id s3c24xx_driver_ids[] = {
1100         {
1101                 .name           = "s3c2410-nand",
1102                 .driver_data    = TYPE_S3C2410,
1103         }, {
1104                 .name           = "s3c2440-nand",
1105                 .driver_data    = TYPE_S3C2440,
1106         }, {
1107                 .name           = "s3c2412-nand",
1108                 .driver_data    = TYPE_S3C2412,
1109         }, {
1110                 .name           = "s3c6400-nand",
1111                 .driver_data    = TYPE_S3C2412, /* compatible with 2412 */
1112         },
1113         { }
1114 };
1115
1116 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1117
1118 static struct platform_driver s3c24xx_nand_driver = {
1119         .probe          = s3c24xx_nand_probe,
1120         .remove         = s3c24xx_nand_remove,
1121         .suspend        = s3c24xx_nand_suspend,
1122         .resume         = s3c24xx_nand_resume,
1123         .id_table       = s3c24xx_driver_ids,
1124         .driver         = {
1125                 .name   = "s3c24xx-nand",
1126                 .owner  = THIS_MODULE,
1127         },
1128 };
1129
1130 static int __init s3c2410_nand_init(void)
1131 {
1132         printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
1133
1134         return platform_driver_register(&s3c24xx_nand_driver);
1135 }
1136
1137 static void __exit s3c2410_nand_exit(void)
1138 {
1139         platform_driver_unregister(&s3c24xx_nand_driver);
1140 }
1141
1142 module_init(s3c2410_nand_init);
1143 module_exit(s3c2410_nand_exit);
1144
1145 MODULE_LICENSE("GPL");
1146 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1147 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");