module: remove module_text_address()
[linux-2.6.git] / drivers / mtd / nand / nand_base.c
1 /*
2  *  drivers/mtd/nand.c
3  *
4  *  Overview:
5  *   This is the generic MTD driver for NAND flash devices. It should be
6  *   capable of working with almost all NAND chips currently available.
7  *   Basic support for AG-AND chips is provided.
8  *
9  *      Additional technical information is available on
10  *      http://www.linux-mtd.infradead.org/doc/nand.html
11  *
12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
14  *
15  *  Credits:
16  *      David Woodhouse for adding multichip support
17  *
18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19  *      rework for 2K page size chips
20  *
21  *  TODO:
22  *      Enable cached programming for 2k page size chips
23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
24  *      if we have HW ecc support.
25  *      The AG-AND chips have nice features for speed improvement,
26  *      which are not supported yet. Read / program 4 pages in one go.
27  *      BBT table is not serialized, has to be fixed
28  *
29  * This program is free software; you can redistribute it and/or modify
30  * it under the terms of the GNU General Public License version 2 as
31  * published by the Free Software Foundation.
32  *
33  */
34
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/compatmac.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
49 #include <asm/io.h>
50
51 #ifdef CONFIG_MTD_PARTITIONS
52 #include <linux/mtd/partitions.h>
53 #endif
54
55 /* Define default oob placement schemes for large and small page devices */
56 static struct nand_ecclayout nand_oob_8 = {
57         .eccbytes = 3,
58         .eccpos = {0, 1, 2},
59         .oobfree = {
60                 {.offset = 3,
61                  .length = 2},
62                 {.offset = 6,
63                  .length = 2}}
64 };
65
66 static struct nand_ecclayout nand_oob_16 = {
67         .eccbytes = 6,
68         .eccpos = {0, 1, 2, 3, 6, 7},
69         .oobfree = {
70                 {.offset = 8,
71                  . length = 8}}
72 };
73
74 static struct nand_ecclayout nand_oob_64 = {
75         .eccbytes = 24,
76         .eccpos = {
77                    40, 41, 42, 43, 44, 45, 46, 47,
78                    48, 49, 50, 51, 52, 53, 54, 55,
79                    56, 57, 58, 59, 60, 61, 62, 63},
80         .oobfree = {
81                 {.offset = 2,
82                  .length = 38}}
83 };
84
85 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
86                            int new_state);
87
88 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
89                              struct mtd_oob_ops *ops);
90
91 /*
92  * For devices which display every fart in the system on a separate LED. Is
93  * compiled away when LED support is disabled.
94  */
95 DEFINE_LED_TRIGGER(nand_led_trigger);
96
97 /**
98  * nand_release_device - [GENERIC] release chip
99  * @mtd:        MTD device structure
100  *
101  * Deselect, release chip lock and wake up anyone waiting on the device
102  */
103 static void nand_release_device(struct mtd_info *mtd)
104 {
105         struct nand_chip *chip = mtd->priv;
106
107         /* De-select the NAND device */
108         chip->select_chip(mtd, -1);
109
110         /* Release the controller and the chip */
111         spin_lock(&chip->controller->lock);
112         chip->controller->active = NULL;
113         chip->state = FL_READY;
114         wake_up(&chip->controller->wq);
115         spin_unlock(&chip->controller->lock);
116 }
117
118 /**
119  * nand_read_byte - [DEFAULT] read one byte from the chip
120  * @mtd:        MTD device structure
121  *
122  * Default read function for 8bit buswith
123  */
124 static uint8_t nand_read_byte(struct mtd_info *mtd)
125 {
126         struct nand_chip *chip = mtd->priv;
127         return readb(chip->IO_ADDR_R);
128 }
129
130 /**
131  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
132  * @mtd:        MTD device structure
133  *
134  * Default read function for 16bit buswith with
135  * endianess conversion
136  */
137 static uint8_t nand_read_byte16(struct mtd_info *mtd)
138 {
139         struct nand_chip *chip = mtd->priv;
140         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
141 }
142
143 /**
144  * nand_read_word - [DEFAULT] read one word from the chip
145  * @mtd:        MTD device structure
146  *
147  * Default read function for 16bit buswith without
148  * endianess conversion
149  */
150 static u16 nand_read_word(struct mtd_info *mtd)
151 {
152         struct nand_chip *chip = mtd->priv;
153         return readw(chip->IO_ADDR_R);
154 }
155
156 /**
157  * nand_select_chip - [DEFAULT] control CE line
158  * @mtd:        MTD device structure
159  * @chipnr:     chipnumber to select, -1 for deselect
160  *
161  * Default select function for 1 chip devices.
162  */
163 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
164 {
165         struct nand_chip *chip = mtd->priv;
166
167         switch (chipnr) {
168         case -1:
169                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
170                 break;
171         case 0:
172                 break;
173
174         default:
175                 BUG();
176         }
177 }
178
179 /**
180  * nand_write_buf - [DEFAULT] write buffer to chip
181  * @mtd:        MTD device structure
182  * @buf:        data buffer
183  * @len:        number of bytes to write
184  *
185  * Default write function for 8bit buswith
186  */
187 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
188 {
189         int i;
190         struct nand_chip *chip = mtd->priv;
191
192         for (i = 0; i < len; i++)
193                 writeb(buf[i], chip->IO_ADDR_W);
194 }
195
196 /**
197  * nand_read_buf - [DEFAULT] read chip data into buffer
198  * @mtd:        MTD device structure
199  * @buf:        buffer to store date
200  * @len:        number of bytes to read
201  *
202  * Default read function for 8bit buswith
203  */
204 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
205 {
206         int i;
207         struct nand_chip *chip = mtd->priv;
208
209         for (i = 0; i < len; i++)
210                 buf[i] = readb(chip->IO_ADDR_R);
211 }
212
213 /**
214  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
215  * @mtd:        MTD device structure
216  * @buf:        buffer containing the data to compare
217  * @len:        number of bytes to compare
218  *
219  * Default verify function for 8bit buswith
220  */
221 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
222 {
223         int i;
224         struct nand_chip *chip = mtd->priv;
225
226         for (i = 0; i < len; i++)
227                 if (buf[i] != readb(chip->IO_ADDR_R))
228                         return -EFAULT;
229         return 0;
230 }
231
232 /**
233  * nand_write_buf16 - [DEFAULT] write buffer to chip
234  * @mtd:        MTD device structure
235  * @buf:        data buffer
236  * @len:        number of bytes to write
237  *
238  * Default write function for 16bit buswith
239  */
240 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
241 {
242         int i;
243         struct nand_chip *chip = mtd->priv;
244         u16 *p = (u16 *) buf;
245         len >>= 1;
246
247         for (i = 0; i < len; i++)
248                 writew(p[i], chip->IO_ADDR_W);
249
250 }
251
252 /**
253  * nand_read_buf16 - [DEFAULT] read chip data into buffer
254  * @mtd:        MTD device structure
255  * @buf:        buffer to store date
256  * @len:        number of bytes to read
257  *
258  * Default read function for 16bit buswith
259  */
260 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
261 {
262         int i;
263         struct nand_chip *chip = mtd->priv;
264         u16 *p = (u16 *) buf;
265         len >>= 1;
266
267         for (i = 0; i < len; i++)
268                 p[i] = readw(chip->IO_ADDR_R);
269 }
270
271 /**
272  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
273  * @mtd:        MTD device structure
274  * @buf:        buffer containing the data to compare
275  * @len:        number of bytes to compare
276  *
277  * Default verify function for 16bit buswith
278  */
279 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
280 {
281         int i;
282         struct nand_chip *chip = mtd->priv;
283         u16 *p = (u16 *) buf;
284         len >>= 1;
285
286         for (i = 0; i < len; i++)
287                 if (p[i] != readw(chip->IO_ADDR_R))
288                         return -EFAULT;
289
290         return 0;
291 }
292
293 /**
294  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
295  * @mtd:        MTD device structure
296  * @ofs:        offset from device start
297  * @getchip:    0, if the chip is already selected
298  *
299  * Check, if the block is bad.
300  */
301 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
302 {
303         int page, chipnr, res = 0;
304         struct nand_chip *chip = mtd->priv;
305         u16 bad;
306
307         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
308
309         if (getchip) {
310                 chipnr = (int)(ofs >> chip->chip_shift);
311
312                 nand_get_device(chip, mtd, FL_READING);
313
314                 /* Select the NAND device */
315                 chip->select_chip(mtd, chipnr);
316         }
317
318         if (chip->options & NAND_BUSWIDTH_16) {
319                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
320                               page);
321                 bad = cpu_to_le16(chip->read_word(mtd));
322                 if (chip->badblockpos & 0x1)
323                         bad >>= 8;
324                 if ((bad & 0xFF) != 0xff)
325                         res = 1;
326         } else {
327                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
328                 if (chip->read_byte(mtd) != 0xff)
329                         res = 1;
330         }
331
332         if (getchip)
333                 nand_release_device(mtd);
334
335         return res;
336 }
337
338 /**
339  * nand_default_block_markbad - [DEFAULT] mark a block bad
340  * @mtd:        MTD device structure
341  * @ofs:        offset from device start
342  *
343  * This is the default implementation, which can be overridden by
344  * a hardware specific driver.
345 */
346 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
347 {
348         struct nand_chip *chip = mtd->priv;
349         uint8_t buf[2] = { 0, 0 };
350         int block, ret;
351
352         /* Get block number */
353         block = (int)(ofs >> chip->bbt_erase_shift);
354         if (chip->bbt)
355                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
356
357         /* Do we have a flash based bad block table ? */
358         if (chip->options & NAND_USE_FLASH_BBT)
359                 ret = nand_update_bbt(mtd, ofs);
360         else {
361                 /* We write two bytes, so we dont have to mess with 16 bit
362                  * access
363                  */
364                 nand_get_device(chip, mtd, FL_WRITING);
365                 ofs += mtd->oobsize;
366                 chip->ops.len = chip->ops.ooblen = 2;
367                 chip->ops.datbuf = NULL;
368                 chip->ops.oobbuf = buf;
369                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
370
371                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
372                 nand_release_device(mtd);
373         }
374         if (!ret)
375                 mtd->ecc_stats.badblocks++;
376
377         return ret;
378 }
379
380 /**
381  * nand_check_wp - [GENERIC] check if the chip is write protected
382  * @mtd:        MTD device structure
383  * Check, if the device is write protected
384  *
385  * The function expects, that the device is already selected
386  */
387 static int nand_check_wp(struct mtd_info *mtd)
388 {
389         struct nand_chip *chip = mtd->priv;
390         /* Check the WP bit */
391         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
392         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
393 }
394
395 /**
396  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
397  * @mtd:        MTD device structure
398  * @ofs:        offset from device start
399  * @getchip:    0, if the chip is already selected
400  * @allowbbt:   1, if its allowed to access the bbt area
401  *
402  * Check, if the block is bad. Either by reading the bad block table or
403  * calling of the scan function.
404  */
405 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
406                                int allowbbt)
407 {
408         struct nand_chip *chip = mtd->priv;
409
410         if (!chip->bbt)
411                 return chip->block_bad(mtd, ofs, getchip);
412
413         /* Return info from the table */
414         return nand_isbad_bbt(mtd, ofs, allowbbt);
415 }
416
417 /*
418  * Wait for the ready pin, after a command
419  * The timeout is catched later.
420  */
421 void nand_wait_ready(struct mtd_info *mtd)
422 {
423         struct nand_chip *chip = mtd->priv;
424         unsigned long timeo = jiffies + 2;
425
426         led_trigger_event(nand_led_trigger, LED_FULL);
427         /* wait until command is processed or timeout occures */
428         do {
429                 if (chip->dev_ready(mtd))
430                         break;
431                 touch_softlockup_watchdog();
432         } while (time_before(jiffies, timeo));
433         led_trigger_event(nand_led_trigger, LED_OFF);
434 }
435 EXPORT_SYMBOL_GPL(nand_wait_ready);
436
437 /**
438  * nand_command - [DEFAULT] Send command to NAND device
439  * @mtd:        MTD device structure
440  * @command:    the command to be sent
441  * @column:     the column address for this command, -1 if none
442  * @page_addr:  the page address for this command, -1 if none
443  *
444  * Send command to NAND device. This function is used for small page
445  * devices (256/512 Bytes per page)
446  */
447 static void nand_command(struct mtd_info *mtd, unsigned int command,
448                          int column, int page_addr)
449 {
450         register struct nand_chip *chip = mtd->priv;
451         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
452
453         /*
454          * Write out the command to the device.
455          */
456         if (command == NAND_CMD_SEQIN) {
457                 int readcmd;
458
459                 if (column >= mtd->writesize) {
460                         /* OOB area */
461                         column -= mtd->writesize;
462                         readcmd = NAND_CMD_READOOB;
463                 } else if (column < 256) {
464                         /* First 256 bytes --> READ0 */
465                         readcmd = NAND_CMD_READ0;
466                 } else {
467                         column -= 256;
468                         readcmd = NAND_CMD_READ1;
469                 }
470                 chip->cmd_ctrl(mtd, readcmd, ctrl);
471                 ctrl &= ~NAND_CTRL_CHANGE;
472         }
473         chip->cmd_ctrl(mtd, command, ctrl);
474
475         /*
476          * Address cycle, when necessary
477          */
478         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
479         /* Serially input address */
480         if (column != -1) {
481                 /* Adjust columns for 16 bit buswidth */
482                 if (chip->options & NAND_BUSWIDTH_16)
483                         column >>= 1;
484                 chip->cmd_ctrl(mtd, column, ctrl);
485                 ctrl &= ~NAND_CTRL_CHANGE;
486         }
487         if (page_addr != -1) {
488                 chip->cmd_ctrl(mtd, page_addr, ctrl);
489                 ctrl &= ~NAND_CTRL_CHANGE;
490                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
491                 /* One more address cycle for devices > 32MiB */
492                 if (chip->chipsize > (32 << 20))
493                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
494         }
495         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
496
497         /*
498          * program and erase have their own busy handlers
499          * status and sequential in needs no delay
500          */
501         switch (command) {
502
503         case NAND_CMD_PAGEPROG:
504         case NAND_CMD_ERASE1:
505         case NAND_CMD_ERASE2:
506         case NAND_CMD_SEQIN:
507         case NAND_CMD_STATUS:
508                 return;
509
510         case NAND_CMD_RESET:
511                 if (chip->dev_ready)
512                         break;
513                 udelay(chip->chip_delay);
514                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
515                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
516                 chip->cmd_ctrl(mtd,
517                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
518                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
519                 return;
520
521                 /* This applies to read commands */
522         default:
523                 /*
524                  * If we don't have access to the busy pin, we apply the given
525                  * command delay
526                  */
527                 if (!chip->dev_ready) {
528                         udelay(chip->chip_delay);
529                         return;
530                 }
531         }
532         /* Apply this short delay always to ensure that we do wait tWB in
533          * any case on any machine. */
534         ndelay(100);
535
536         nand_wait_ready(mtd);
537 }
538
539 /**
540  * nand_command_lp - [DEFAULT] Send command to NAND large page device
541  * @mtd:        MTD device structure
542  * @command:    the command to be sent
543  * @column:     the column address for this command, -1 if none
544  * @page_addr:  the page address for this command, -1 if none
545  *
546  * Send command to NAND device. This is the version for the new large page
547  * devices We dont have the separate regions as we have in the small page
548  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
549  */
550 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
551                             int column, int page_addr)
552 {
553         register struct nand_chip *chip = mtd->priv;
554
555         /* Emulate NAND_CMD_READOOB */
556         if (command == NAND_CMD_READOOB) {
557                 column += mtd->writesize;
558                 command = NAND_CMD_READ0;
559         }
560
561         /* Command latch cycle */
562         chip->cmd_ctrl(mtd, command & 0xff,
563                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
564
565         if (column != -1 || page_addr != -1) {
566                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
567
568                 /* Serially input address */
569                 if (column != -1) {
570                         /* Adjust columns for 16 bit buswidth */
571                         if (chip->options & NAND_BUSWIDTH_16)
572                                 column >>= 1;
573                         chip->cmd_ctrl(mtd, column, ctrl);
574                         ctrl &= ~NAND_CTRL_CHANGE;
575                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
576                 }
577                 if (page_addr != -1) {
578                         chip->cmd_ctrl(mtd, page_addr, ctrl);
579                         chip->cmd_ctrl(mtd, page_addr >> 8,
580                                        NAND_NCE | NAND_ALE);
581                         /* One more address cycle for devices > 128MiB */
582                         if (chip->chipsize > (128 << 20))
583                                 chip->cmd_ctrl(mtd, page_addr >> 16,
584                                                NAND_NCE | NAND_ALE);
585                 }
586         }
587         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
588
589         /*
590          * program and erase have their own busy handlers
591          * status, sequential in, and deplete1 need no delay
592          */
593         switch (command) {
594
595         case NAND_CMD_CACHEDPROG:
596         case NAND_CMD_PAGEPROG:
597         case NAND_CMD_ERASE1:
598         case NAND_CMD_ERASE2:
599         case NAND_CMD_SEQIN:
600         case NAND_CMD_RNDIN:
601         case NAND_CMD_STATUS:
602         case NAND_CMD_DEPLETE1:
603                 return;
604
605                 /*
606                  * read error status commands require only a short delay
607                  */
608         case NAND_CMD_STATUS_ERROR:
609         case NAND_CMD_STATUS_ERROR0:
610         case NAND_CMD_STATUS_ERROR1:
611         case NAND_CMD_STATUS_ERROR2:
612         case NAND_CMD_STATUS_ERROR3:
613                 udelay(chip->chip_delay);
614                 return;
615
616         case NAND_CMD_RESET:
617                 if (chip->dev_ready)
618                         break;
619                 udelay(chip->chip_delay);
620                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
621                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
622                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
623                                NAND_NCE | NAND_CTRL_CHANGE);
624                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
625                 return;
626
627         case NAND_CMD_RNDOUT:
628                 /* No ready / busy check necessary */
629                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
630                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
631                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
632                                NAND_NCE | NAND_CTRL_CHANGE);
633                 return;
634
635         case NAND_CMD_READ0:
636                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
637                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
638                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
639                                NAND_NCE | NAND_CTRL_CHANGE);
640
641                 /* This applies to read commands */
642         default:
643                 /*
644                  * If we don't have access to the busy pin, we apply the given
645                  * command delay
646                  */
647                 if (!chip->dev_ready) {
648                         udelay(chip->chip_delay);
649                         return;
650                 }
651         }
652
653         /* Apply this short delay always to ensure that we do wait tWB in
654          * any case on any machine. */
655         ndelay(100);
656
657         nand_wait_ready(mtd);
658 }
659
660 /**
661  * nand_get_device - [GENERIC] Get chip for selected access
662  * @chip:       the nand chip descriptor
663  * @mtd:        MTD device structure
664  * @new_state:  the state which is requested
665  *
666  * Get the device and lock it for exclusive access
667  */
668 static int
669 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
670 {
671         spinlock_t *lock = &chip->controller->lock;
672         wait_queue_head_t *wq = &chip->controller->wq;
673         DECLARE_WAITQUEUE(wait, current);
674  retry:
675         spin_lock(lock);
676
677         /* Hardware controller shared among independend devices */
678         /* Hardware controller shared among independend devices */
679         if (!chip->controller->active)
680                 chip->controller->active = chip;
681
682         if (chip->controller->active == chip && chip->state == FL_READY) {
683                 chip->state = new_state;
684                 spin_unlock(lock);
685                 return 0;
686         }
687         if (new_state == FL_PM_SUSPENDED) {
688                 spin_unlock(lock);
689                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
690         }
691         set_current_state(TASK_UNINTERRUPTIBLE);
692         add_wait_queue(wq, &wait);
693         spin_unlock(lock);
694         schedule();
695         remove_wait_queue(wq, &wait);
696         goto retry;
697 }
698
699 /**
700  * nand_wait - [DEFAULT]  wait until the command is done
701  * @mtd:        MTD device structure
702  * @chip:       NAND chip structure
703  *
704  * Wait for command done. This applies to erase and program only
705  * Erase can take up to 400ms and program up to 20ms according to
706  * general NAND and SmartMedia specs
707  */
708 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
709 {
710
711         unsigned long timeo = jiffies;
712         int status, state = chip->state;
713
714         if (state == FL_ERASING)
715                 timeo += (HZ * 400) / 1000;
716         else
717                 timeo += (HZ * 20) / 1000;
718
719         led_trigger_event(nand_led_trigger, LED_FULL);
720
721         /* Apply this short delay always to ensure that we do wait tWB in
722          * any case on any machine. */
723         ndelay(100);
724
725         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
726                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
727         else
728                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
729
730         while (time_before(jiffies, timeo)) {
731                 if (chip->dev_ready) {
732                         if (chip->dev_ready(mtd))
733                                 break;
734                 } else {
735                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
736                                 break;
737                 }
738                 cond_resched();
739         }
740         led_trigger_event(nand_led_trigger, LED_OFF);
741
742         status = (int)chip->read_byte(mtd);
743         return status;
744 }
745
746 /**
747  * nand_read_page_raw - [Intern] read raw page data without ecc
748  * @mtd:        mtd info structure
749  * @chip:       nand chip info structure
750  * @buf:        buffer to store read data
751  */
752 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
753                               uint8_t *buf)
754 {
755         chip->read_buf(mtd, buf, mtd->writesize);
756         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
757         return 0;
758 }
759
760 /**
761  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
762  * @mtd:        mtd info structure
763  * @chip:       nand chip info structure
764  * @buf:        buffer to store read data
765  */
766 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
767                                 uint8_t *buf)
768 {
769         int i, eccsize = chip->ecc.size;
770         int eccbytes = chip->ecc.bytes;
771         int eccsteps = chip->ecc.steps;
772         uint8_t *p = buf;
773         uint8_t *ecc_calc = chip->buffers->ecccalc;
774         uint8_t *ecc_code = chip->buffers->ecccode;
775         uint32_t *eccpos = chip->ecc.layout->eccpos;
776
777         chip->ecc.read_page_raw(mtd, chip, buf);
778
779         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
780                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
781
782         for (i = 0; i < chip->ecc.total; i++)
783                 ecc_code[i] = chip->oob_poi[eccpos[i]];
784
785         eccsteps = chip->ecc.steps;
786         p = buf;
787
788         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
789                 int stat;
790
791                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
792                 if (stat < 0)
793                         mtd->ecc_stats.failed++;
794                 else
795                         mtd->ecc_stats.corrected += stat;
796         }
797         return 0;
798 }
799
800 /**
801  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
802  * @mtd:        mtd info structure
803  * @chip:       nand chip info structure
804  * @data_offs:  offset of requested data within the page
805  * @readlen:    data length
806  * @bufpoi:     buffer to store read data
807  */
808 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
809 {
810         int start_step, end_step, num_steps;
811         uint32_t *eccpos = chip->ecc.layout->eccpos;
812         uint8_t *p;
813         int data_col_addr, i, gaps = 0;
814         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
815         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
816
817         /* Column address wihin the page aligned to ECC size (256bytes). */
818         start_step = data_offs / chip->ecc.size;
819         end_step = (data_offs + readlen - 1) / chip->ecc.size;
820         num_steps = end_step - start_step + 1;
821
822         /* Data size aligned to ECC ecc.size*/
823         datafrag_len = num_steps * chip->ecc.size;
824         eccfrag_len = num_steps * chip->ecc.bytes;
825
826         data_col_addr = start_step * chip->ecc.size;
827         /* If we read not a page aligned data */
828         if (data_col_addr != 0)
829                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
830
831         p = bufpoi + data_col_addr;
832         chip->read_buf(mtd, p, datafrag_len);
833
834         /* Calculate  ECC */
835         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
836                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
837
838         /* The performance is faster if to position offsets
839            according to ecc.pos. Let make sure here that
840            there are no gaps in ecc positions */
841         for (i = 0; i < eccfrag_len - 1; i++) {
842                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
843                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
844                         gaps = 1;
845                         break;
846                 }
847         }
848         if (gaps) {
849                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
850                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
851         } else {
852                 /* send the command to read the particular ecc bytes */
853                 /* take care about buswidth alignment in read_buf */
854                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
855                 aligned_len = eccfrag_len;
856                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
857                         aligned_len++;
858                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
859                         aligned_len++;
860
861                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
862                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
863         }
864
865         for (i = 0; i < eccfrag_len; i++)
866                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
867
868         p = bufpoi + data_col_addr;
869         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
870                 int stat;
871
872                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
873                 if (stat == -1)
874                         mtd->ecc_stats.failed++;
875                 else
876                         mtd->ecc_stats.corrected += stat;
877         }
878         return 0;
879 }
880
881 /**
882  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
883  * @mtd:        mtd info structure
884  * @chip:       nand chip info structure
885  * @buf:        buffer to store read data
886  *
887  * Not for syndrome calculating ecc controllers which need a special oob layout
888  */
889 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
890                                 uint8_t *buf)
891 {
892         int i, eccsize = chip->ecc.size;
893         int eccbytes = chip->ecc.bytes;
894         int eccsteps = chip->ecc.steps;
895         uint8_t *p = buf;
896         uint8_t *ecc_calc = chip->buffers->ecccalc;
897         uint8_t *ecc_code = chip->buffers->ecccode;
898         uint32_t *eccpos = chip->ecc.layout->eccpos;
899
900         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
901                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
902                 chip->read_buf(mtd, p, eccsize);
903                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
904         }
905         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
906
907         for (i = 0; i < chip->ecc.total; i++)
908                 ecc_code[i] = chip->oob_poi[eccpos[i]];
909
910         eccsteps = chip->ecc.steps;
911         p = buf;
912
913         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
914                 int stat;
915
916                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
917                 if (stat < 0)
918                         mtd->ecc_stats.failed++;
919                 else
920                         mtd->ecc_stats.corrected += stat;
921         }
922         return 0;
923 }
924
925 /**
926  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
927  * @mtd:        mtd info structure
928  * @chip:       nand chip info structure
929  * @buf:        buffer to store read data
930  *
931  * The hw generator calculates the error syndrome automatically. Therefor
932  * we need a special oob layout and handling.
933  */
934 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
935                                    uint8_t *buf)
936 {
937         int i, eccsize = chip->ecc.size;
938         int eccbytes = chip->ecc.bytes;
939         int eccsteps = chip->ecc.steps;
940         uint8_t *p = buf;
941         uint8_t *oob = chip->oob_poi;
942
943         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
944                 int stat;
945
946                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
947                 chip->read_buf(mtd, p, eccsize);
948
949                 if (chip->ecc.prepad) {
950                         chip->read_buf(mtd, oob, chip->ecc.prepad);
951                         oob += chip->ecc.prepad;
952                 }
953
954                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
955                 chip->read_buf(mtd, oob, eccbytes);
956                 stat = chip->ecc.correct(mtd, p, oob, NULL);
957
958                 if (stat < 0)
959                         mtd->ecc_stats.failed++;
960                 else
961                         mtd->ecc_stats.corrected += stat;
962
963                 oob += eccbytes;
964
965                 if (chip->ecc.postpad) {
966                         chip->read_buf(mtd, oob, chip->ecc.postpad);
967                         oob += chip->ecc.postpad;
968                 }
969         }
970
971         /* Calculate remaining oob bytes */
972         i = mtd->oobsize - (oob - chip->oob_poi);
973         if (i)
974                 chip->read_buf(mtd, oob, i);
975
976         return 0;
977 }
978
979 /**
980  * nand_transfer_oob - [Internal] Transfer oob to client buffer
981  * @chip:       nand chip structure
982  * @oob:        oob destination address
983  * @ops:        oob ops structure
984  * @len:        size of oob to transfer
985  */
986 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
987                                   struct mtd_oob_ops *ops, size_t len)
988 {
989         switch(ops->mode) {
990
991         case MTD_OOB_PLACE:
992         case MTD_OOB_RAW:
993                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
994                 return oob + len;
995
996         case MTD_OOB_AUTO: {
997                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
998                 uint32_t boffs = 0, roffs = ops->ooboffs;
999                 size_t bytes = 0;
1000
1001                 for(; free->length && len; free++, len -= bytes) {
1002                         /* Read request not from offset 0 ? */
1003                         if (unlikely(roffs)) {
1004                                 if (roffs >= free->length) {
1005                                         roffs -= free->length;
1006                                         continue;
1007                                 }
1008                                 boffs = free->offset + roffs;
1009                                 bytes = min_t(size_t, len,
1010                                               (free->length - roffs));
1011                                 roffs = 0;
1012                         } else {
1013                                 bytes = min_t(size_t, len, free->length);
1014                                 boffs = free->offset;
1015                         }
1016                         memcpy(oob, chip->oob_poi + boffs, bytes);
1017                         oob += bytes;
1018                 }
1019                 return oob;
1020         }
1021         default:
1022                 BUG();
1023         }
1024         return NULL;
1025 }
1026
1027 /**
1028  * nand_do_read_ops - [Internal] Read data with ECC
1029  *
1030  * @mtd:        MTD device structure
1031  * @from:       offset to read from
1032  * @ops:        oob ops structure
1033  *
1034  * Internal function. Called with chip held.
1035  */
1036 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1037                             struct mtd_oob_ops *ops)
1038 {
1039         int chipnr, page, realpage, col, bytes, aligned;
1040         struct nand_chip *chip = mtd->priv;
1041         struct mtd_ecc_stats stats;
1042         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1043         int sndcmd = 1;
1044         int ret = 0;
1045         uint32_t readlen = ops->len;
1046         uint32_t oobreadlen = ops->ooblen;
1047         uint8_t *bufpoi, *oob, *buf;
1048
1049         stats = mtd->ecc_stats;
1050
1051         chipnr = (int)(from >> chip->chip_shift);
1052         chip->select_chip(mtd, chipnr);
1053
1054         realpage = (int)(from >> chip->page_shift);
1055         page = realpage & chip->pagemask;
1056
1057         col = (int)(from & (mtd->writesize - 1));
1058
1059         buf = ops->datbuf;
1060         oob = ops->oobbuf;
1061
1062         while(1) {
1063                 bytes = min(mtd->writesize - col, readlen);
1064                 aligned = (bytes == mtd->writesize);
1065
1066                 /* Is the current page in the buffer ? */
1067                 if (realpage != chip->pagebuf || oob) {
1068                         bufpoi = aligned ? buf : chip->buffers->databuf;
1069
1070                         if (likely(sndcmd)) {
1071                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1072                                 sndcmd = 0;
1073                         }
1074
1075                         /* Now read the page into the buffer */
1076                         if (unlikely(ops->mode == MTD_OOB_RAW))
1077                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1078                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1079                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1080                         else
1081                                 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1082                         if (ret < 0)
1083                                 break;
1084
1085                         /* Transfer not aligned data */
1086                         if (!aligned) {
1087                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1088                                         chip->pagebuf = realpage;
1089                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1090                         }
1091
1092                         buf += bytes;
1093
1094                         if (unlikely(oob)) {
1095                                 /* Raw mode does data:oob:data:oob */
1096                                 if (ops->mode != MTD_OOB_RAW) {
1097                                         int toread = min(oobreadlen,
1098                                                 chip->ecc.layout->oobavail);
1099                                         if (toread) {
1100                                                 oob = nand_transfer_oob(chip,
1101                                                         oob, ops, toread);
1102                                                 oobreadlen -= toread;
1103                                         }
1104                                 } else
1105                                         buf = nand_transfer_oob(chip,
1106                                                 buf, ops, mtd->oobsize);
1107                         }
1108
1109                         if (!(chip->options & NAND_NO_READRDY)) {
1110                                 /*
1111                                  * Apply delay or wait for ready/busy pin. Do
1112                                  * this before the AUTOINCR check, so no
1113                                  * problems arise if a chip which does auto
1114                                  * increment is marked as NOAUTOINCR by the
1115                                  * board driver.
1116                                  */
1117                                 if (!chip->dev_ready)
1118                                         udelay(chip->chip_delay);
1119                                 else
1120                                         nand_wait_ready(mtd);
1121                         }
1122                 } else {
1123                         memcpy(buf, chip->buffers->databuf + col, bytes);
1124                         buf += bytes;
1125                 }
1126
1127                 readlen -= bytes;
1128
1129                 if (!readlen)
1130                         break;
1131
1132                 /* For subsequent reads align to page boundary. */
1133                 col = 0;
1134                 /* Increment page address */
1135                 realpage++;
1136
1137                 page = realpage & chip->pagemask;
1138                 /* Check, if we cross a chip boundary */
1139                 if (!page) {
1140                         chipnr++;
1141                         chip->select_chip(mtd, -1);
1142                         chip->select_chip(mtd, chipnr);
1143                 }
1144
1145                 /* Check, if the chip supports auto page increment
1146                  * or if we have hit a block boundary.
1147                  */
1148                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1149                         sndcmd = 1;
1150         }
1151
1152         ops->retlen = ops->len - (size_t) readlen;
1153         if (oob)
1154                 ops->oobretlen = ops->ooblen - oobreadlen;
1155
1156         if (ret)
1157                 return ret;
1158
1159         if (mtd->ecc_stats.failed - stats.failed)
1160                 return -EBADMSG;
1161
1162         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1163 }
1164
1165 /**
1166  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1167  * @mtd:        MTD device structure
1168  * @from:       offset to read from
1169  * @len:        number of bytes to read
1170  * @retlen:     pointer to variable to store the number of read bytes
1171  * @buf:        the databuffer to put data
1172  *
1173  * Get hold of the chip and call nand_do_read
1174  */
1175 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1176                      size_t *retlen, uint8_t *buf)
1177 {
1178         struct nand_chip *chip = mtd->priv;
1179         int ret;
1180
1181         /* Do not allow reads past end of device */
1182         if ((from + len) > mtd->size)
1183                 return -EINVAL;
1184         if (!len)
1185                 return 0;
1186
1187         nand_get_device(chip, mtd, FL_READING);
1188
1189         chip->ops.len = len;
1190         chip->ops.datbuf = buf;
1191         chip->ops.oobbuf = NULL;
1192
1193         ret = nand_do_read_ops(mtd, from, &chip->ops);
1194
1195         *retlen = chip->ops.retlen;
1196
1197         nand_release_device(mtd);
1198
1199         return ret;
1200 }
1201
1202 /**
1203  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1204  * @mtd:        mtd info structure
1205  * @chip:       nand chip info structure
1206  * @page:       page number to read
1207  * @sndcmd:     flag whether to issue read command or not
1208  */
1209 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1210                              int page, int sndcmd)
1211 {
1212         if (sndcmd) {
1213                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1214                 sndcmd = 0;
1215         }
1216         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1217         return sndcmd;
1218 }
1219
1220 /**
1221  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1222  *                          with syndromes
1223  * @mtd:        mtd info structure
1224  * @chip:       nand chip info structure
1225  * @page:       page number to read
1226  * @sndcmd:     flag whether to issue read command or not
1227  */
1228 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1229                                   int page, int sndcmd)
1230 {
1231         uint8_t *buf = chip->oob_poi;
1232         int length = mtd->oobsize;
1233         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1234         int eccsize = chip->ecc.size;
1235         uint8_t *bufpoi = buf;
1236         int i, toread, sndrnd = 0, pos;
1237
1238         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1239         for (i = 0; i < chip->ecc.steps; i++) {
1240                 if (sndrnd) {
1241                         pos = eccsize + i * (eccsize + chunk);
1242                         if (mtd->writesize > 512)
1243                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1244                         else
1245                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1246                 } else
1247                         sndrnd = 1;
1248                 toread = min_t(int, length, chunk);
1249                 chip->read_buf(mtd, bufpoi, toread);
1250                 bufpoi += toread;
1251                 length -= toread;
1252         }
1253         if (length > 0)
1254                 chip->read_buf(mtd, bufpoi, length);
1255
1256         return 1;
1257 }
1258
1259 /**
1260  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1261  * @mtd:        mtd info structure
1262  * @chip:       nand chip info structure
1263  * @page:       page number to write
1264  */
1265 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1266                               int page)
1267 {
1268         int status = 0;
1269         const uint8_t *buf = chip->oob_poi;
1270         int length = mtd->oobsize;
1271
1272         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1273         chip->write_buf(mtd, buf, length);
1274         /* Send command to program the OOB data */
1275         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1276
1277         status = chip->waitfunc(mtd, chip);
1278
1279         return status & NAND_STATUS_FAIL ? -EIO : 0;
1280 }
1281
1282 /**
1283  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1284  *                           with syndrome - only for large page flash !
1285  * @mtd:        mtd info structure
1286  * @chip:       nand chip info structure
1287  * @page:       page number to write
1288  */
1289 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1290                                    struct nand_chip *chip, int page)
1291 {
1292         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1293         int eccsize = chip->ecc.size, length = mtd->oobsize;
1294         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1295         const uint8_t *bufpoi = chip->oob_poi;
1296
1297         /*
1298          * data-ecc-data-ecc ... ecc-oob
1299          * or
1300          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1301          */
1302         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1303                 pos = steps * (eccsize + chunk);
1304                 steps = 0;
1305         } else
1306                 pos = eccsize;
1307
1308         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1309         for (i = 0; i < steps; i++) {
1310                 if (sndcmd) {
1311                         if (mtd->writesize <= 512) {
1312                                 uint32_t fill = 0xFFFFFFFF;
1313
1314                                 len = eccsize;
1315                                 while (len > 0) {
1316                                         int num = min_t(int, len, 4);
1317                                         chip->write_buf(mtd, (uint8_t *)&fill,
1318                                                         num);
1319                                         len -= num;
1320                                 }
1321                         } else {
1322                                 pos = eccsize + i * (eccsize + chunk);
1323                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1324                         }
1325                 } else
1326                         sndcmd = 1;
1327                 len = min_t(int, length, chunk);
1328                 chip->write_buf(mtd, bufpoi, len);
1329                 bufpoi += len;
1330                 length -= len;
1331         }
1332         if (length > 0)
1333                 chip->write_buf(mtd, bufpoi, length);
1334
1335         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1336         status = chip->waitfunc(mtd, chip);
1337
1338         return status & NAND_STATUS_FAIL ? -EIO : 0;
1339 }
1340
1341 /**
1342  * nand_do_read_oob - [Intern] NAND read out-of-band
1343  * @mtd:        MTD device structure
1344  * @from:       offset to read from
1345  * @ops:        oob operations description structure
1346  *
1347  * NAND read out-of-band data from the spare area
1348  */
1349 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1350                             struct mtd_oob_ops *ops)
1351 {
1352         int page, realpage, chipnr, sndcmd = 1;
1353         struct nand_chip *chip = mtd->priv;
1354         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1355         int readlen = ops->ooblen;
1356         int len;
1357         uint8_t *buf = ops->oobbuf;
1358
1359         DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1360               (unsigned long long)from, readlen);
1361
1362         if (ops->mode == MTD_OOB_AUTO)
1363                 len = chip->ecc.layout->oobavail;
1364         else
1365                 len = mtd->oobsize;
1366
1367         if (unlikely(ops->ooboffs >= len)) {
1368                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1369                         "Attempt to start read outside oob\n");
1370                 return -EINVAL;
1371         }
1372
1373         /* Do not allow reads past end of device */
1374         if (unlikely(from >= mtd->size ||
1375                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1376                                         (from >> chip->page_shift)) * len)) {
1377                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1378                         "Attempt read beyond end of device\n");
1379                 return -EINVAL;
1380         }
1381
1382         chipnr = (int)(from >> chip->chip_shift);
1383         chip->select_chip(mtd, chipnr);
1384
1385         /* Shift to get page */
1386         realpage = (int)(from >> chip->page_shift);
1387         page = realpage & chip->pagemask;
1388
1389         while(1) {
1390                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1391
1392                 len = min(len, readlen);
1393                 buf = nand_transfer_oob(chip, buf, ops, len);
1394
1395                 if (!(chip->options & NAND_NO_READRDY)) {
1396                         /*
1397                          * Apply delay or wait for ready/busy pin. Do this
1398                          * before the AUTOINCR check, so no problems arise if a
1399                          * chip which does auto increment is marked as
1400                          * NOAUTOINCR by the board driver.
1401                          */
1402                         if (!chip->dev_ready)
1403                                 udelay(chip->chip_delay);
1404                         else
1405                                 nand_wait_ready(mtd);
1406                 }
1407
1408                 readlen -= len;
1409                 if (!readlen)
1410                         break;
1411
1412                 /* Increment page address */
1413                 realpage++;
1414
1415                 page = realpage & chip->pagemask;
1416                 /* Check, if we cross a chip boundary */
1417                 if (!page) {
1418                         chipnr++;
1419                         chip->select_chip(mtd, -1);
1420                         chip->select_chip(mtd, chipnr);
1421                 }
1422
1423                 /* Check, if the chip supports auto page increment
1424                  * or if we have hit a block boundary.
1425                  */
1426                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1427                         sndcmd = 1;
1428         }
1429
1430         ops->oobretlen = ops->ooblen;
1431         return 0;
1432 }
1433
1434 /**
1435  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1436  * @mtd:        MTD device structure
1437  * @from:       offset to read from
1438  * @ops:        oob operation description structure
1439  *
1440  * NAND read data and/or out-of-band data
1441  */
1442 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1443                          struct mtd_oob_ops *ops)
1444 {
1445         struct nand_chip *chip = mtd->priv;
1446         int ret = -ENOTSUPP;
1447
1448         ops->retlen = 0;
1449
1450         /* Do not allow reads past end of device */
1451         if (ops->datbuf && (from + ops->len) > mtd->size) {
1452                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1453                       "Attempt read beyond end of device\n");
1454                 return -EINVAL;
1455         }
1456
1457         nand_get_device(chip, mtd, FL_READING);
1458
1459         switch(ops->mode) {
1460         case MTD_OOB_PLACE:
1461         case MTD_OOB_AUTO:
1462         case MTD_OOB_RAW:
1463                 break;
1464
1465         default:
1466                 goto out;
1467         }
1468
1469         if (!ops->datbuf)
1470                 ret = nand_do_read_oob(mtd, from, ops);
1471         else
1472                 ret = nand_do_read_ops(mtd, from, ops);
1473
1474  out:
1475         nand_release_device(mtd);
1476         return ret;
1477 }
1478
1479
1480 /**
1481  * nand_write_page_raw - [Intern] raw page write function
1482  * @mtd:        mtd info structure
1483  * @chip:       nand chip info structure
1484  * @buf:        data buffer
1485  */
1486 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1487                                 const uint8_t *buf)
1488 {
1489         chip->write_buf(mtd, buf, mtd->writesize);
1490         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1491 }
1492
1493 /**
1494  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1495  * @mtd:        mtd info structure
1496  * @chip:       nand chip info structure
1497  * @buf:        data buffer
1498  */
1499 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1500                                   const uint8_t *buf)
1501 {
1502         int i, eccsize = chip->ecc.size;
1503         int eccbytes = chip->ecc.bytes;
1504         int eccsteps = chip->ecc.steps;
1505         uint8_t *ecc_calc = chip->buffers->ecccalc;
1506         const uint8_t *p = buf;
1507         uint32_t *eccpos = chip->ecc.layout->eccpos;
1508
1509         /* Software ecc calculation */
1510         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1511                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1512
1513         for (i = 0; i < chip->ecc.total; i++)
1514                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1515
1516         chip->ecc.write_page_raw(mtd, chip, buf);
1517 }
1518
1519 /**
1520  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1521  * @mtd:        mtd info structure
1522  * @chip:       nand chip info structure
1523  * @buf:        data buffer
1524  */
1525 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1526                                   const uint8_t *buf)
1527 {
1528         int i, eccsize = chip->ecc.size;
1529         int eccbytes = chip->ecc.bytes;
1530         int eccsteps = chip->ecc.steps;
1531         uint8_t *ecc_calc = chip->buffers->ecccalc;
1532         const uint8_t *p = buf;
1533         uint32_t *eccpos = chip->ecc.layout->eccpos;
1534
1535         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1536                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1537                 chip->write_buf(mtd, p, eccsize);
1538                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1539         }
1540
1541         for (i = 0; i < chip->ecc.total; i++)
1542                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1543
1544         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1545 }
1546
1547 /**
1548  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1549  * @mtd:        mtd info structure
1550  * @chip:       nand chip info structure
1551  * @buf:        data buffer
1552  *
1553  * The hw generator calculates the error syndrome automatically. Therefor
1554  * we need a special oob layout and handling.
1555  */
1556 static void nand_write_page_syndrome(struct mtd_info *mtd,
1557                                     struct nand_chip *chip, const uint8_t *buf)
1558 {
1559         int i, eccsize = chip->ecc.size;
1560         int eccbytes = chip->ecc.bytes;
1561         int eccsteps = chip->ecc.steps;
1562         const uint8_t *p = buf;
1563         uint8_t *oob = chip->oob_poi;
1564
1565         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1566
1567                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1568                 chip->write_buf(mtd, p, eccsize);
1569
1570                 if (chip->ecc.prepad) {
1571                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1572                         oob += chip->ecc.prepad;
1573                 }
1574
1575                 chip->ecc.calculate(mtd, p, oob);
1576                 chip->write_buf(mtd, oob, eccbytes);
1577                 oob += eccbytes;
1578
1579                 if (chip->ecc.postpad) {
1580                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1581                         oob += chip->ecc.postpad;
1582                 }
1583         }
1584
1585         /* Calculate remaining oob bytes */
1586         i = mtd->oobsize - (oob - chip->oob_poi);
1587         if (i)
1588                 chip->write_buf(mtd, oob, i);
1589 }
1590
1591 /**
1592  * nand_write_page - [REPLACEABLE] write one page
1593  * @mtd:        MTD device structure
1594  * @chip:       NAND chip descriptor
1595  * @buf:        the data to write
1596  * @page:       page number to write
1597  * @cached:     cached programming
1598  * @raw:        use _raw version of write_page
1599  */
1600 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1601                            const uint8_t *buf, int page, int cached, int raw)
1602 {
1603         int status;
1604
1605         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1606
1607         if (unlikely(raw))
1608                 chip->ecc.write_page_raw(mtd, chip, buf);
1609         else
1610                 chip->ecc.write_page(mtd, chip, buf);
1611
1612         /*
1613          * Cached progamming disabled for now, Not sure if its worth the
1614          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1615          */
1616         cached = 0;
1617
1618         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1619
1620                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1621                 status = chip->waitfunc(mtd, chip);
1622                 /*
1623                  * See if operation failed and additional status checks are
1624                  * available
1625                  */
1626                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1627                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1628                                                page);
1629
1630                 if (status & NAND_STATUS_FAIL)
1631                         return -EIO;
1632         } else {
1633                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1634                 status = chip->waitfunc(mtd, chip);
1635         }
1636
1637 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1638         /* Send command to read back the data */
1639         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1640
1641         if (chip->verify_buf(mtd, buf, mtd->writesize))
1642                 return -EIO;
1643 #endif
1644         return 0;
1645 }
1646
1647 /**
1648  * nand_fill_oob - [Internal] Transfer client buffer to oob
1649  * @chip:       nand chip structure
1650  * @oob:        oob data buffer
1651  * @ops:        oob ops structure
1652  */
1653 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1654                                   struct mtd_oob_ops *ops)
1655 {
1656         size_t len = ops->ooblen;
1657
1658         switch(ops->mode) {
1659
1660         case MTD_OOB_PLACE:
1661         case MTD_OOB_RAW:
1662                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1663                 return oob + len;
1664
1665         case MTD_OOB_AUTO: {
1666                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1667                 uint32_t boffs = 0, woffs = ops->ooboffs;
1668                 size_t bytes = 0;
1669
1670                 for(; free->length && len; free++, len -= bytes) {
1671                         /* Write request not from offset 0 ? */
1672                         if (unlikely(woffs)) {
1673                                 if (woffs >= free->length) {
1674                                         woffs -= free->length;
1675                                         continue;
1676                                 }
1677                                 boffs = free->offset + woffs;
1678                                 bytes = min_t(size_t, len,
1679                                               (free->length - woffs));
1680                                 woffs = 0;
1681                         } else {
1682                                 bytes = min_t(size_t, len, free->length);
1683                                 boffs = free->offset;
1684                         }
1685                         memcpy(chip->oob_poi + boffs, oob, bytes);
1686                         oob += bytes;
1687                 }
1688                 return oob;
1689         }
1690         default:
1691                 BUG();
1692         }
1693         return NULL;
1694 }
1695
1696 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1697
1698 /**
1699  * nand_do_write_ops - [Internal] NAND write with ECC
1700  * @mtd:        MTD device structure
1701  * @to:         offset to write to
1702  * @ops:        oob operations description structure
1703  *
1704  * NAND write with ECC
1705  */
1706 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1707                              struct mtd_oob_ops *ops)
1708 {
1709         int chipnr, realpage, page, blockmask, column;
1710         struct nand_chip *chip = mtd->priv;
1711         uint32_t writelen = ops->len;
1712         uint8_t *oob = ops->oobbuf;
1713         uint8_t *buf = ops->datbuf;
1714         int ret, subpage;
1715
1716         ops->retlen = 0;
1717         if (!writelen)
1718                 return 0;
1719
1720         /* reject writes, which are not page aligned */
1721         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1722                 printk(KERN_NOTICE "nand_write: "
1723                        "Attempt to write not page aligned data\n");
1724                 return -EINVAL;
1725         }
1726
1727         column = to & (mtd->writesize - 1);
1728         subpage = column || (writelen & (mtd->writesize - 1));
1729
1730         if (subpage && oob)
1731                 return -EINVAL;
1732
1733         chipnr = (int)(to >> chip->chip_shift);
1734         chip->select_chip(mtd, chipnr);
1735
1736         /* Check, if it is write protected */
1737         if (nand_check_wp(mtd))
1738                 return -EIO;
1739
1740         realpage = (int)(to >> chip->page_shift);
1741         page = realpage & chip->pagemask;
1742         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1743
1744         /* Invalidate the page cache, when we write to the cached page */
1745         if (to <= (chip->pagebuf << chip->page_shift) &&
1746             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1747                 chip->pagebuf = -1;
1748
1749         /* If we're not given explicit OOB data, let it be 0xFF */
1750         if (likely(!oob))
1751                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1752
1753         while(1) {
1754                 int bytes = mtd->writesize;
1755                 int cached = writelen > bytes && page != blockmask;
1756                 uint8_t *wbuf = buf;
1757
1758                 /* Partial page write ? */
1759                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1760                         cached = 0;
1761                         bytes = min_t(int, bytes - column, (int) writelen);
1762                         chip->pagebuf = -1;
1763                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1764                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1765                         wbuf = chip->buffers->databuf;
1766                 }
1767
1768                 if (unlikely(oob))
1769                         oob = nand_fill_oob(chip, oob, ops);
1770
1771                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1772                                        (ops->mode == MTD_OOB_RAW));
1773                 if (ret)
1774                         break;
1775
1776                 writelen -= bytes;
1777                 if (!writelen)
1778                         break;
1779
1780                 column = 0;
1781                 buf += bytes;
1782                 realpage++;
1783
1784                 page = realpage & chip->pagemask;
1785                 /* Check, if we cross a chip boundary */
1786                 if (!page) {
1787                         chipnr++;
1788                         chip->select_chip(mtd, -1);
1789                         chip->select_chip(mtd, chipnr);
1790                 }
1791         }
1792
1793         ops->retlen = ops->len - writelen;
1794         if (unlikely(oob))
1795                 ops->oobretlen = ops->ooblen;
1796         return ret;
1797 }
1798
1799 /**
1800  * nand_write - [MTD Interface] NAND write with ECC
1801  * @mtd:        MTD device structure
1802  * @to:         offset to write to
1803  * @len:        number of bytes to write
1804  * @retlen:     pointer to variable to store the number of written bytes
1805  * @buf:        the data to write
1806  *
1807  * NAND write with ECC
1808  */
1809 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1810                           size_t *retlen, const uint8_t *buf)
1811 {
1812         struct nand_chip *chip = mtd->priv;
1813         int ret;
1814
1815         /* Do not allow reads past end of device */
1816         if ((to + len) > mtd->size)
1817                 return -EINVAL;
1818         if (!len)
1819                 return 0;
1820
1821         nand_get_device(chip, mtd, FL_WRITING);
1822
1823         chip->ops.len = len;
1824         chip->ops.datbuf = (uint8_t *)buf;
1825         chip->ops.oobbuf = NULL;
1826
1827         ret = nand_do_write_ops(mtd, to, &chip->ops);
1828
1829         *retlen = chip->ops.retlen;
1830
1831         nand_release_device(mtd);
1832
1833         return ret;
1834 }
1835
1836 /**
1837  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1838  * @mtd:        MTD device structure
1839  * @to:         offset to write to
1840  * @ops:        oob operation description structure
1841  *
1842  * NAND write out-of-band
1843  */
1844 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1845                              struct mtd_oob_ops *ops)
1846 {
1847         int chipnr, page, status, len;
1848         struct nand_chip *chip = mtd->priv;
1849
1850         DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1851               (unsigned int)to, (int)ops->ooblen);
1852
1853         if (ops->mode == MTD_OOB_AUTO)
1854                 len = chip->ecc.layout->oobavail;
1855         else
1856                 len = mtd->oobsize;
1857
1858         /* Do not allow write past end of page */
1859         if ((ops->ooboffs + ops->ooblen) > len) {
1860                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1861                       "Attempt to write past end of page\n");
1862                 return -EINVAL;
1863         }
1864
1865         if (unlikely(ops->ooboffs >= len)) {
1866                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1867                         "Attempt to start write outside oob\n");
1868                 return -EINVAL;
1869         }
1870
1871         /* Do not allow reads past end of device */
1872         if (unlikely(to >= mtd->size ||
1873                      ops->ooboffs + ops->ooblen >
1874                         ((mtd->size >> chip->page_shift) -
1875                          (to >> chip->page_shift)) * len)) {
1876                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1877                         "Attempt write beyond end of device\n");
1878                 return -EINVAL;
1879         }
1880
1881         chipnr = (int)(to >> chip->chip_shift);
1882         chip->select_chip(mtd, chipnr);
1883
1884         /* Shift to get page */
1885         page = (int)(to >> chip->page_shift);
1886
1887         /*
1888          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1889          * of my DiskOnChip 2000 test units) will clear the whole data page too
1890          * if we don't do this. I have no clue why, but I seem to have 'fixed'
1891          * it in the doc2000 driver in August 1999.  dwmw2.
1892          */
1893         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1894
1895         /* Check, if it is write protected */
1896         if (nand_check_wp(mtd))
1897                 return -EROFS;
1898
1899         /* Invalidate the page cache, if we write to the cached page */
1900         if (page == chip->pagebuf)
1901                 chip->pagebuf = -1;
1902
1903         memset(chip->oob_poi, 0xff, mtd->oobsize);
1904         nand_fill_oob(chip, ops->oobbuf, ops);
1905         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1906         memset(chip->oob_poi, 0xff, mtd->oobsize);
1907
1908         if (status)
1909                 return status;
1910
1911         ops->oobretlen = ops->ooblen;
1912
1913         return 0;
1914 }
1915
1916 /**
1917  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1918  * @mtd:        MTD device structure
1919  * @to:         offset to write to
1920  * @ops:        oob operation description structure
1921  */
1922 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1923                           struct mtd_oob_ops *ops)
1924 {
1925         struct nand_chip *chip = mtd->priv;
1926         int ret = -ENOTSUPP;
1927
1928         ops->retlen = 0;
1929
1930         /* Do not allow writes past end of device */
1931         if (ops->datbuf && (to + ops->len) > mtd->size) {
1932                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1933                       "Attempt read beyond end of device\n");
1934                 return -EINVAL;
1935         }
1936
1937         nand_get_device(chip, mtd, FL_WRITING);
1938
1939         switch(ops->mode) {
1940         case MTD_OOB_PLACE:
1941         case MTD_OOB_AUTO:
1942         case MTD_OOB_RAW:
1943                 break;
1944
1945         default:
1946                 goto out;
1947         }
1948
1949         if (!ops->datbuf)
1950                 ret = nand_do_write_oob(mtd, to, ops);
1951         else
1952                 ret = nand_do_write_ops(mtd, to, ops);
1953
1954  out:
1955         nand_release_device(mtd);
1956         return ret;
1957 }
1958
1959 /**
1960  * single_erease_cmd - [GENERIC] NAND standard block erase command function
1961  * @mtd:        MTD device structure
1962  * @page:       the page address of the block which will be erased
1963  *
1964  * Standard erase command for NAND chips
1965  */
1966 static void single_erase_cmd(struct mtd_info *mtd, int page)
1967 {
1968         struct nand_chip *chip = mtd->priv;
1969         /* Send commands to erase a block */
1970         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1971         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1972 }
1973
1974 /**
1975  * multi_erease_cmd - [GENERIC] AND specific block erase command function
1976  * @mtd:        MTD device structure
1977  * @page:       the page address of the block which will be erased
1978  *
1979  * AND multi block erase command function
1980  * Erase 4 consecutive blocks
1981  */
1982 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1983 {
1984         struct nand_chip *chip = mtd->priv;
1985         /* Send commands to erase a block */
1986         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1987         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1988         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1989         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1990         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1991 }
1992
1993 /**
1994  * nand_erase - [MTD Interface] erase block(s)
1995  * @mtd:        MTD device structure
1996  * @instr:      erase instruction
1997  *
1998  * Erase one ore more blocks
1999  */
2000 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2001 {
2002         return nand_erase_nand(mtd, instr, 0);
2003 }
2004
2005 #define BBT_PAGE_MASK   0xffffff3f
2006 /**
2007  * nand_erase_nand - [Internal] erase block(s)
2008  * @mtd:        MTD device structure
2009  * @instr:      erase instruction
2010  * @allowbbt:   allow erasing the bbt area
2011  *
2012  * Erase one ore more blocks
2013  */
2014 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2015                     int allowbbt)
2016 {
2017         int page, status, pages_per_block, ret, chipnr;
2018         struct nand_chip *chip = mtd->priv;
2019         loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2020         unsigned int bbt_masked_page = 0xffffffff;
2021         loff_t len;
2022
2023         DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, len = %llu\n",
2024               (unsigned long long)instr->addr, (unsigned long long)instr->len);
2025
2026         /* Start address must align on block boundary */
2027         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2028                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2029                 return -EINVAL;
2030         }
2031
2032         /* Length must align on block boundary */
2033         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2034                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2035                       "Length not block aligned\n");
2036                 return -EINVAL;
2037         }
2038
2039         /* Do not allow erase past end of device */
2040         if ((instr->len + instr->addr) > mtd->size) {
2041                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2042                       "Erase past end of device\n");
2043                 return -EINVAL;
2044         }
2045
2046         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2047
2048         /* Grab the lock and see if the device is available */
2049         nand_get_device(chip, mtd, FL_ERASING);
2050
2051         /* Shift to get first page */
2052         page = (int)(instr->addr >> chip->page_shift);
2053         chipnr = (int)(instr->addr >> chip->chip_shift);
2054
2055         /* Calculate pages in each block */
2056         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2057
2058         /* Select the NAND device */
2059         chip->select_chip(mtd, chipnr);
2060
2061         /* Check, if it is write protected */
2062         if (nand_check_wp(mtd)) {
2063                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2064                       "Device is write protected!!!\n");
2065                 instr->state = MTD_ERASE_FAILED;
2066                 goto erase_exit;
2067         }
2068
2069         /*
2070          * If BBT requires refresh, set the BBT page mask to see if the BBT
2071          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2072          * can not be matched. This is also done when the bbt is actually
2073          * erased to avoid recusrsive updates
2074          */
2075         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2076                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2077
2078         /* Loop through the pages */
2079         len = instr->len;
2080
2081         instr->state = MTD_ERASING;
2082
2083         while (len) {
2084                 /*
2085                  * heck if we have a bad block, we do not erase bad blocks !
2086                  */
2087                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2088                                         chip->page_shift, 0, allowbbt)) {
2089                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2090                                "bad block at page 0x%08x\n", page);
2091                         instr->state = MTD_ERASE_FAILED;
2092                         goto erase_exit;
2093                 }
2094
2095                 /*
2096                  * Invalidate the page cache, if we erase the block which
2097                  * contains the current cached page
2098                  */
2099                 if (page <= chip->pagebuf && chip->pagebuf <
2100                     (page + pages_per_block))
2101                         chip->pagebuf = -1;
2102
2103                 chip->erase_cmd(mtd, page & chip->pagemask);
2104
2105                 status = chip->waitfunc(mtd, chip);
2106
2107                 /*
2108                  * See if operation failed and additional status checks are
2109                  * available
2110                  */
2111                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2112                         status = chip->errstat(mtd, chip, FL_ERASING,
2113                                                status, page);
2114
2115                 /* See if block erase succeeded */
2116                 if (status & NAND_STATUS_FAIL) {
2117                         DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2118                               "Failed erase, page 0x%08x\n", page);
2119                         instr->state = MTD_ERASE_FAILED;
2120                         instr->fail_addr =
2121                                 ((loff_t)page << chip->page_shift);
2122                         goto erase_exit;
2123                 }
2124
2125                 /*
2126                  * If BBT requires refresh, set the BBT rewrite flag to the
2127                  * page being erased
2128                  */
2129                 if (bbt_masked_page != 0xffffffff &&
2130                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2131                             rewrite_bbt[chipnr] =
2132                                         ((loff_t)page << chip->page_shift);
2133
2134                 /* Increment page address and decrement length */
2135                 len -= (1 << chip->phys_erase_shift);
2136                 page += pages_per_block;
2137
2138                 /* Check, if we cross a chip boundary */
2139                 if (len && !(page & chip->pagemask)) {
2140                         chipnr++;
2141                         chip->select_chip(mtd, -1);
2142                         chip->select_chip(mtd, chipnr);
2143
2144                         /*
2145                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2146                          * page mask to see if this BBT should be rewritten
2147                          */
2148                         if (bbt_masked_page != 0xffffffff &&
2149                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2150                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2151                                         BBT_PAGE_MASK;
2152                 }
2153         }
2154         instr->state = MTD_ERASE_DONE;
2155
2156  erase_exit:
2157
2158         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2159
2160         /* Deselect and wake up anyone waiting on the device */
2161         nand_release_device(mtd);
2162
2163         /* Do call back function */
2164         if (!ret)
2165                 mtd_erase_callback(instr);
2166
2167         /*
2168          * If BBT requires refresh and erase was successful, rewrite any
2169          * selected bad block tables
2170          */
2171         if (bbt_masked_page == 0xffffffff || ret)
2172                 return ret;
2173
2174         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2175                 if (!rewrite_bbt[chipnr])
2176                         continue;
2177                 /* update the BBT for chip */
2178                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2179                       "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2180                       chip->bbt_td->pages[chipnr]);
2181                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2182         }
2183
2184         /* Return more or less happy */
2185         return ret;
2186 }
2187
2188 /**
2189  * nand_sync - [MTD Interface] sync
2190  * @mtd:        MTD device structure
2191  *
2192  * Sync is actually a wait for chip ready function
2193  */
2194 static void nand_sync(struct mtd_info *mtd)
2195 {
2196         struct nand_chip *chip = mtd->priv;
2197
2198         DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2199
2200         /* Grab the lock and see if the device is available */
2201         nand_get_device(chip, mtd, FL_SYNCING);
2202         /* Release it and go back */
2203         nand_release_device(mtd);
2204 }
2205
2206 /**
2207  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2208  * @mtd:        MTD device structure
2209  * @offs:       offset relative to mtd start
2210  */
2211 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2212 {
2213         /* Check for invalid offset */
2214         if (offs > mtd->size)
2215                 return -EINVAL;
2216
2217         return nand_block_checkbad(mtd, offs, 1, 0);
2218 }
2219
2220 /**
2221  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2222  * @mtd:        MTD device structure
2223  * @ofs:        offset relative to mtd start
2224  */
2225 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2226 {
2227         struct nand_chip *chip = mtd->priv;
2228         int ret;
2229
2230         if ((ret = nand_block_isbad(mtd, ofs))) {
2231                 /* If it was bad already, return success and do nothing. */
2232                 if (ret > 0)
2233                         return 0;
2234                 return ret;
2235         }
2236
2237         return chip->block_markbad(mtd, ofs);
2238 }
2239
2240 /**
2241  * nand_suspend - [MTD Interface] Suspend the NAND flash
2242  * @mtd:        MTD device structure
2243  */
2244 static int nand_suspend(struct mtd_info *mtd)
2245 {
2246         struct nand_chip *chip = mtd->priv;
2247
2248         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2249 }
2250
2251 /**
2252  * nand_resume - [MTD Interface] Resume the NAND flash
2253  * @mtd:        MTD device structure
2254  */
2255 static void nand_resume(struct mtd_info *mtd)
2256 {
2257         struct nand_chip *chip = mtd->priv;
2258
2259         if (chip->state == FL_PM_SUSPENDED)
2260                 nand_release_device(mtd);
2261         else
2262                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2263                        "in suspended state\n");
2264 }
2265
2266 /*
2267  * Set default functions
2268  */
2269 static void nand_set_defaults(struct nand_chip *chip, int busw)
2270 {
2271         /* check for proper chip_delay setup, set 20us if not */
2272         if (!chip->chip_delay)
2273                 chip->chip_delay = 20;
2274
2275         /* check, if a user supplied command function given */
2276         if (chip->cmdfunc == NULL)
2277                 chip->cmdfunc = nand_command;
2278
2279         /* check, if a user supplied wait function given */
2280         if (chip->waitfunc == NULL)
2281                 chip->waitfunc = nand_wait;
2282
2283         if (!chip->select_chip)
2284                 chip->select_chip = nand_select_chip;
2285         if (!chip->read_byte)
2286                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2287         if (!chip->read_word)
2288                 chip->read_word = nand_read_word;
2289         if (!chip->block_bad)
2290                 chip->block_bad = nand_block_bad;
2291         if (!chip->block_markbad)
2292                 chip->block_markbad = nand_default_block_markbad;
2293         if (!chip->write_buf)
2294                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2295         if (!chip->read_buf)
2296                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2297         if (!chip->verify_buf)
2298                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2299         if (!chip->scan_bbt)
2300                 chip->scan_bbt = nand_default_bbt;
2301
2302         if (!chip->controller) {
2303                 chip->controller = &chip->hwcontrol;
2304                 spin_lock_init(&chip->controller->lock);
2305                 init_waitqueue_head(&chip->controller->wq);
2306         }
2307
2308 }
2309
2310 /*
2311  * Get the flash and manufacturer id and lookup if the type is supported
2312  */
2313 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2314                                                   struct nand_chip *chip,
2315                                                   int busw, int *maf_id)
2316 {
2317         struct nand_flash_dev *type = NULL;
2318         int i, dev_id, maf_idx;
2319         int tmp_id, tmp_manf;
2320
2321         /* Select the device */
2322         chip->select_chip(mtd, 0);
2323
2324         /*
2325          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2326          * after power-up
2327          */
2328         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2329
2330         /* Send the command for reading device ID */
2331         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2332
2333         /* Read manufacturer and device IDs */
2334         *maf_id = chip->read_byte(mtd);
2335         dev_id = chip->read_byte(mtd);
2336
2337         /* Try again to make sure, as some systems the bus-hold or other
2338          * interface concerns can cause random data which looks like a
2339          * possibly credible NAND flash to appear. If the two results do
2340          * not match, ignore the device completely.
2341          */
2342
2343         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2344
2345         /* Read manufacturer and device IDs */
2346
2347         tmp_manf = chip->read_byte(mtd);
2348         tmp_id = chip->read_byte(mtd);
2349
2350         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2351                 printk(KERN_INFO "%s: second ID read did not match "
2352                        "%02x,%02x against %02x,%02x\n", __func__,
2353                        *maf_id, dev_id, tmp_manf, tmp_id);
2354                 return ERR_PTR(-ENODEV);
2355         }
2356
2357         /* Lookup the flash id */
2358         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2359                 if (dev_id == nand_flash_ids[i].id) {
2360                         type =  &nand_flash_ids[i];
2361                         break;
2362                 }
2363         }
2364
2365         if (!type)
2366                 return ERR_PTR(-ENODEV);
2367
2368         if (!mtd->name)
2369                 mtd->name = type->name;
2370
2371         chip->chipsize = (uint64_t)type->chipsize << 20;
2372
2373         /* Newer devices have all the information in additional id bytes */
2374         if (!type->pagesize) {
2375                 int extid;
2376                 /* The 3rd id byte holds MLC / multichip data */
2377                 chip->cellinfo = chip->read_byte(mtd);
2378                 /* The 4th id byte is the important one */
2379                 extid = chip->read_byte(mtd);
2380                 /* Calc pagesize */
2381                 mtd->writesize = 1024 << (extid & 0x3);
2382                 extid >>= 2;
2383                 /* Calc oobsize */
2384                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2385                 extid >>= 2;
2386                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2387                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2388                 extid >>= 2;
2389                 /* Get buswidth information */
2390                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2391
2392         } else {
2393                 /*
2394                  * Old devices have chip data hardcoded in the device id table
2395                  */
2396                 mtd->erasesize = type->erasesize;
2397                 mtd->writesize = type->pagesize;
2398                 mtd->oobsize = mtd->writesize / 32;
2399                 busw = type->options & NAND_BUSWIDTH_16;
2400         }
2401
2402         /* Try to identify manufacturer */
2403         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2404                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2405                         break;
2406         }
2407
2408         /*
2409          * Check, if buswidth is correct. Hardware drivers should set
2410          * chip correct !
2411          */
2412         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2413                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2414                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2415                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2416                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2417                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2418                        busw ? 16 : 8);
2419                 return ERR_PTR(-EINVAL);
2420         }
2421
2422         /* Calculate the address shift from the page size */
2423         chip->page_shift = ffs(mtd->writesize) - 1;
2424         /* Convert chipsize to number of pages per chip -1. */
2425         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2426
2427         chip->bbt_erase_shift = chip->phys_erase_shift =
2428                 ffs(mtd->erasesize) - 1;
2429         if (chip->chipsize & 0xffffffff)
2430                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2431         else
2432                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2433
2434         /* Set the bad block position */
2435         chip->badblockpos = mtd->writesize > 512 ?
2436                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2437
2438         /* Get chip options, preserve non chip based options */
2439         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2440         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2441
2442         /*
2443          * Set chip as a default. Board drivers can override it, if necessary
2444          */
2445         chip->options |= NAND_NO_AUTOINCR;
2446
2447         /* Check if chip is a not a samsung device. Do not clear the
2448          * options for chips which are not having an extended id.
2449          */
2450         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2451                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2452
2453         /* Check for AND chips with 4 page planes */
2454         if (chip->options & NAND_4PAGE_ARRAY)
2455                 chip->erase_cmd = multi_erase_cmd;
2456         else
2457                 chip->erase_cmd = single_erase_cmd;
2458
2459         /* Do not replace user supplied command function ! */
2460         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2461                 chip->cmdfunc = nand_command_lp;
2462
2463         printk(KERN_INFO "NAND device: Manufacturer ID:"
2464                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2465                nand_manuf_ids[maf_idx].name, type->name);
2466
2467         return type;
2468 }
2469
2470 /**
2471  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2472  * @mtd:             MTD device structure
2473  * @maxchips:        Number of chips to scan for
2474  *
2475  * This is the first phase of the normal nand_scan() function. It
2476  * reads the flash ID and sets up MTD fields accordingly.
2477  *
2478  * The mtd->owner field must be set to the module of the caller.
2479  */
2480 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2481 {
2482         int i, busw, nand_maf_id;
2483         struct nand_chip *chip = mtd->priv;
2484         struct nand_flash_dev *type;
2485
2486         /* Get buswidth to select the correct functions */
2487         busw = chip->options & NAND_BUSWIDTH_16;
2488         /* Set the default functions */
2489         nand_set_defaults(chip, busw);
2490
2491         /* Read the flash type */
2492         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2493
2494         if (IS_ERR(type)) {
2495                 printk(KERN_WARNING "No NAND device found!!!\n");
2496                 chip->select_chip(mtd, -1);
2497                 return PTR_ERR(type);
2498         }
2499
2500         /* Check for a chip array */
2501         for (i = 1; i < maxchips; i++) {
2502                 chip->select_chip(mtd, i);
2503                 /* See comment in nand_get_flash_type for reset */
2504                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2505                 /* Send the command for reading device ID */
2506                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2507                 /* Read manufacturer and device IDs */
2508                 if (nand_maf_id != chip->read_byte(mtd) ||
2509                     type->id != chip->read_byte(mtd))
2510                         break;
2511         }
2512         if (i > 1)
2513                 printk(KERN_INFO "%d NAND chips detected\n", i);
2514
2515         /* Store the number of chips and calc total size for mtd */
2516         chip->numchips = i;
2517         mtd->size = i * chip->chipsize;
2518
2519         return 0;
2520 }
2521
2522
2523 /**
2524  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2525  * @mtd:            MTD device structure
2526  *
2527  * This is the second phase of the normal nand_scan() function. It
2528  * fills out all the uninitialized function pointers with the defaults
2529  * and scans for a bad block table if appropriate.
2530  */
2531 int nand_scan_tail(struct mtd_info *mtd)
2532 {
2533         int i;
2534         struct nand_chip *chip = mtd->priv;
2535
2536         if (!(chip->options & NAND_OWN_BUFFERS))
2537                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2538         if (!chip->buffers)
2539                 return -ENOMEM;
2540
2541         /* Set the internal oob buffer location, just after the page data */
2542         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2543
2544         /*
2545          * If no default placement scheme is given, select an appropriate one
2546          */
2547         if (!chip->ecc.layout) {
2548                 switch (mtd->oobsize) {
2549                 case 8:
2550                         chip->ecc.layout = &nand_oob_8;
2551                         break;
2552                 case 16:
2553                         chip->ecc.layout = &nand_oob_16;
2554                         break;
2555                 case 64:
2556                         chip->ecc.layout = &nand_oob_64;
2557                         break;
2558                 default:
2559                         printk(KERN_WARNING "No oob scheme defined for "
2560                                "oobsize %d\n", mtd->oobsize);
2561                         BUG();
2562                 }
2563         }
2564
2565         if (!chip->write_page)
2566                 chip->write_page = nand_write_page;
2567
2568         /*
2569          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2570          * selected and we have 256 byte pagesize fallback to software ECC
2571          */
2572         if (!chip->ecc.read_page_raw)
2573                 chip->ecc.read_page_raw = nand_read_page_raw;
2574         if (!chip->ecc.write_page_raw)
2575                 chip->ecc.write_page_raw = nand_write_page_raw;
2576
2577         switch (chip->ecc.mode) {
2578         case NAND_ECC_HW:
2579                 /* Use standard hwecc read page function ? */
2580                 if (!chip->ecc.read_page)
2581                         chip->ecc.read_page = nand_read_page_hwecc;
2582                 if (!chip->ecc.write_page)
2583                         chip->ecc.write_page = nand_write_page_hwecc;
2584                 if (!chip->ecc.read_oob)
2585                         chip->ecc.read_oob = nand_read_oob_std;
2586                 if (!chip->ecc.write_oob)
2587                         chip->ecc.write_oob = nand_write_oob_std;
2588
2589         case NAND_ECC_HW_SYNDROME:
2590                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2591                      !chip->ecc.hwctl) &&
2592                     (!chip->ecc.read_page ||
2593                      chip->ecc.read_page == nand_read_page_hwecc ||
2594                      !chip->ecc.write_page ||
2595                      chip->ecc.write_page == nand_write_page_hwecc)) {
2596                         printk(KERN_WARNING "No ECC functions supplied, "
2597                                "Hardware ECC not possible\n");
2598                         BUG();
2599                 }
2600                 /* Use standard syndrome read/write page function ? */
2601                 if (!chip->ecc.read_page)
2602                         chip->ecc.read_page = nand_read_page_syndrome;
2603                 if (!chip->ecc.write_page)
2604                         chip->ecc.write_page = nand_write_page_syndrome;
2605                 if (!chip->ecc.read_oob)
2606                         chip->ecc.read_oob = nand_read_oob_syndrome;
2607                 if (!chip->ecc.write_oob)
2608                         chip->ecc.write_oob = nand_write_oob_syndrome;
2609
2610                 if (mtd->writesize >= chip->ecc.size)
2611                         break;
2612                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2613                        "%d byte page size, fallback to SW ECC\n",
2614                        chip->ecc.size, mtd->writesize);
2615                 chip->ecc.mode = NAND_ECC_SOFT;
2616
2617         case NAND_ECC_SOFT:
2618                 chip->ecc.calculate = nand_calculate_ecc;
2619                 chip->ecc.correct = nand_correct_data;
2620                 chip->ecc.read_page = nand_read_page_swecc;
2621                 chip->ecc.read_subpage = nand_read_subpage;
2622                 chip->ecc.write_page = nand_write_page_swecc;
2623                 chip->ecc.read_oob = nand_read_oob_std;
2624                 chip->ecc.write_oob = nand_write_oob_std;
2625                 chip->ecc.size = 256;
2626                 chip->ecc.bytes = 3;
2627                 break;
2628
2629         case NAND_ECC_NONE:
2630                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2631                        "This is not recommended !!\n");
2632                 chip->ecc.read_page = nand_read_page_raw;
2633                 chip->ecc.write_page = nand_write_page_raw;
2634                 chip->ecc.read_oob = nand_read_oob_std;
2635                 chip->ecc.write_oob = nand_write_oob_std;
2636                 chip->ecc.size = mtd->writesize;
2637                 chip->ecc.bytes = 0;
2638                 break;
2639
2640         default:
2641                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2642                        chip->ecc.mode);
2643                 BUG();
2644         }
2645
2646         /*
2647          * The number of bytes available for a client to place data into
2648          * the out of band area
2649          */
2650         chip->ecc.layout->oobavail = 0;
2651         for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2652                 chip->ecc.layout->oobavail +=
2653                         chip->ecc.layout->oobfree[i].length;
2654         mtd->oobavail = chip->ecc.layout->oobavail;
2655
2656         /*
2657          * Set the number of read / write steps for one page depending on ECC
2658          * mode
2659          */
2660         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2661         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2662                 printk(KERN_WARNING "Invalid ecc parameters\n");
2663                 BUG();
2664         }
2665         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2666
2667         /*
2668          * Allow subpage writes up to ecc.steps. Not possible for MLC
2669          * FLASH.
2670          */
2671         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2672             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2673                 switch(chip->ecc.steps) {
2674                 case 2:
2675                         mtd->subpage_sft = 1;
2676                         break;
2677                 case 4:
2678                 case 8:
2679                         mtd->subpage_sft = 2;
2680                         break;
2681                 }
2682         }
2683         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2684
2685         /* Initialize state */
2686         chip->state = FL_READY;
2687
2688         /* De-select the device */
2689         chip->select_chip(mtd, -1);
2690
2691         /* Invalidate the pagebuffer reference */
2692         chip->pagebuf = -1;
2693
2694         /* Fill in remaining MTD driver data */
2695         mtd->type = MTD_NANDFLASH;
2696         mtd->flags = MTD_CAP_NANDFLASH;
2697         mtd->erase = nand_erase;
2698         mtd->point = NULL;
2699         mtd->unpoint = NULL;
2700         mtd->read = nand_read;
2701         mtd->write = nand_write;
2702         mtd->read_oob = nand_read_oob;
2703         mtd->write_oob = nand_write_oob;
2704         mtd->sync = nand_sync;
2705         mtd->lock = NULL;
2706         mtd->unlock = NULL;
2707         mtd->suspend = nand_suspend;
2708         mtd->resume = nand_resume;
2709         mtd->block_isbad = nand_block_isbad;
2710         mtd->block_markbad = nand_block_markbad;
2711
2712         /* propagate ecc.layout to mtd_info */
2713         mtd->ecclayout = chip->ecc.layout;
2714
2715         /* Check, if we should skip the bad block table scan */
2716         if (chip->options & NAND_SKIP_BBTSCAN)
2717                 return 0;
2718
2719         /* Build bad block table */
2720         return chip->scan_bbt(mtd);
2721 }
2722
2723 /* is_module_text_address() isn't exported, and it's mostly a pointless
2724    test if this is a module _anyway_ -- they'd have to try _really_ hard
2725    to call us from in-kernel code if the core NAND support is modular. */
2726 #ifdef MODULE
2727 #define caller_is_module() (1)
2728 #else
2729 #define caller_is_module() \
2730         is_module_text_address((unsigned long)__builtin_return_address(0))
2731 #endif
2732
2733 /**
2734  * nand_scan - [NAND Interface] Scan for the NAND device
2735  * @mtd:        MTD device structure
2736  * @maxchips:   Number of chips to scan for
2737  *
2738  * This fills out all the uninitialized function pointers
2739  * with the defaults.
2740  * The flash ID is read and the mtd/chip structures are
2741  * filled with the appropriate values.
2742  * The mtd->owner field must be set to the module of the caller
2743  *
2744  */
2745 int nand_scan(struct mtd_info *mtd, int maxchips)
2746 {
2747         int ret;
2748
2749         /* Many callers got this wrong, so check for it for a while... */
2750         if (!mtd->owner && caller_is_module()) {
2751                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2752                 BUG();
2753         }
2754
2755         ret = nand_scan_ident(mtd, maxchips);
2756         if (!ret)
2757                 ret = nand_scan_tail(mtd);
2758         return ret;
2759 }
2760
2761 /**
2762  * nand_release - [NAND Interface] Free resources held by the NAND device
2763  * @mtd:        MTD device structure
2764 */
2765 void nand_release(struct mtd_info *mtd)
2766 {
2767         struct nand_chip *chip = mtd->priv;
2768
2769 #ifdef CONFIG_MTD_PARTITIONS
2770         /* Deregister partitions */
2771         del_mtd_partitions(mtd);
2772 #endif
2773         /* Deregister the device */
2774         del_mtd_device(mtd);
2775
2776         /* Free bad block table memory */
2777         kfree(chip->bbt);
2778         if (!(chip->options & NAND_OWN_BUFFERS))
2779                 kfree(chip->buffers);
2780 }
2781
2782 EXPORT_SYMBOL_GPL(nand_scan);
2783 EXPORT_SYMBOL_GPL(nand_scan_ident);
2784 EXPORT_SYMBOL_GPL(nand_scan_tail);
2785 EXPORT_SYMBOL_GPL(nand_release);
2786
2787 static int __init nand_base_init(void)
2788 {
2789         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2790         return 0;
2791 }
2792
2793 static void __exit nand_base_exit(void)
2794 {
2795         led_trigger_unregister_simple(nand_led_trigger);
2796 }
2797
2798 module_init(nand_base_init);
2799 module_exit(nand_base_exit);
2800
2801 MODULE_LICENSE("GPL");
2802 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2803 MODULE_DESCRIPTION("Generic NAND flash driver code");