drm/vmwgfx: Don't send bad flags to the host
[linux-2.6.git] / drivers / mtd / nand / nand_base.c
1 /*
2  *  drivers/mtd/nand.c
3  *
4  *  Overview:
5  *   This is the generic MTD driver for NAND flash devices. It should be
6  *   capable of working with almost all NAND chips currently available.
7  *   Basic support for AG-AND chips is provided.
8  *
9  *      Additional technical information is available on
10  *      http://www.linux-mtd.infradead.org/doc/nand.html
11  *
12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
14  *
15  *  Credits:
16  *      David Woodhouse for adding multichip support
17  *
18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19  *      rework for 2K page size chips
20  *
21  *  TODO:
22  *      Enable cached programming for 2k page size chips
23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
24  *      if we have HW ecc support.
25  *      The AG-AND chips have nice features for speed improvement,
26  *      which are not supported yet. Read / program 4 pages in one go.
27  *      BBT table is not serialized, has to be fixed
28  *
29  * This program is free software; you can redistribute it and/or modify
30  * it under the terms of the GNU General Public License version 2 as
31  * published by the Free Software Foundation.
32  *
33  */
34
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/compatmac.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
49 #include <asm/io.h>
50
51 #ifdef CONFIG_MTD_PARTITIONS
52 #include <linux/mtd/partitions.h>
53 #endif
54
55 /* Define default oob placement schemes for large and small page devices */
56 static struct nand_ecclayout nand_oob_8 = {
57         .eccbytes = 3,
58         .eccpos = {0, 1, 2},
59         .oobfree = {
60                 {.offset = 3,
61                  .length = 2},
62                 {.offset = 6,
63                  .length = 2}}
64 };
65
66 static struct nand_ecclayout nand_oob_16 = {
67         .eccbytes = 6,
68         .eccpos = {0, 1, 2, 3, 6, 7},
69         .oobfree = {
70                 {.offset = 8,
71                  . length = 8}}
72 };
73
74 static struct nand_ecclayout nand_oob_64 = {
75         .eccbytes = 24,
76         .eccpos = {
77                    40, 41, 42, 43, 44, 45, 46, 47,
78                    48, 49, 50, 51, 52, 53, 54, 55,
79                    56, 57, 58, 59, 60, 61, 62, 63},
80         .oobfree = {
81                 {.offset = 2,
82                  .length = 38}}
83 };
84
85 static struct nand_ecclayout nand_oob_128 = {
86         .eccbytes = 48,
87         .eccpos = {
88                    80, 81, 82, 83, 84, 85, 86, 87,
89                    88, 89, 90, 91, 92, 93, 94, 95,
90                    96, 97, 98, 99, 100, 101, 102, 103,
91                    104, 105, 106, 107, 108, 109, 110, 111,
92                    112, 113, 114, 115, 116, 117, 118, 119,
93                    120, 121, 122, 123, 124, 125, 126, 127},
94         .oobfree = {
95                 {.offset = 2,
96                  .length = 78}}
97 };
98
99 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
100                            int new_state);
101
102 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
103                              struct mtd_oob_ops *ops);
104
105 /*
106  * For devices which display every fart in the system on a separate LED. Is
107  * compiled away when LED support is disabled.
108  */
109 DEFINE_LED_TRIGGER(nand_led_trigger);
110
111 /**
112  * nand_release_device - [GENERIC] release chip
113  * @mtd:        MTD device structure
114  *
115  * Deselect, release chip lock and wake up anyone waiting on the device
116  */
117 static void nand_release_device(struct mtd_info *mtd)
118 {
119         struct nand_chip *chip = mtd->priv;
120
121         /* De-select the NAND device */
122         chip->select_chip(mtd, -1);
123
124         /* Release the controller and the chip */
125         spin_lock(&chip->controller->lock);
126         chip->controller->active = NULL;
127         chip->state = FL_READY;
128         wake_up(&chip->controller->wq);
129         spin_unlock(&chip->controller->lock);
130 }
131
132 /**
133  * nand_read_byte - [DEFAULT] read one byte from the chip
134  * @mtd:        MTD device structure
135  *
136  * Default read function for 8bit buswith
137  */
138 static uint8_t nand_read_byte(struct mtd_info *mtd)
139 {
140         struct nand_chip *chip = mtd->priv;
141         return readb(chip->IO_ADDR_R);
142 }
143
144 /**
145  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
146  * @mtd:        MTD device structure
147  *
148  * Default read function for 16bit buswith with
149  * endianess conversion
150  */
151 static uint8_t nand_read_byte16(struct mtd_info *mtd)
152 {
153         struct nand_chip *chip = mtd->priv;
154         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
155 }
156
157 /**
158  * nand_read_word - [DEFAULT] read one word from the chip
159  * @mtd:        MTD device structure
160  *
161  * Default read function for 16bit buswith without
162  * endianess conversion
163  */
164 static u16 nand_read_word(struct mtd_info *mtd)
165 {
166         struct nand_chip *chip = mtd->priv;
167         return readw(chip->IO_ADDR_R);
168 }
169
170 /**
171  * nand_select_chip - [DEFAULT] control CE line
172  * @mtd:        MTD device structure
173  * @chipnr:     chipnumber to select, -1 for deselect
174  *
175  * Default select function for 1 chip devices.
176  */
177 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
178 {
179         struct nand_chip *chip = mtd->priv;
180
181         switch (chipnr) {
182         case -1:
183                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
184                 break;
185         case 0:
186                 break;
187
188         default:
189                 BUG();
190         }
191 }
192
193 /**
194  * nand_write_buf - [DEFAULT] write buffer to chip
195  * @mtd:        MTD device structure
196  * @buf:        data buffer
197  * @len:        number of bytes to write
198  *
199  * Default write function for 8bit buswith
200  */
201 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
202 {
203         int i;
204         struct nand_chip *chip = mtd->priv;
205
206         for (i = 0; i < len; i++)
207                 writeb(buf[i], chip->IO_ADDR_W);
208 }
209
210 /**
211  * nand_read_buf - [DEFAULT] read chip data into buffer
212  * @mtd:        MTD device structure
213  * @buf:        buffer to store date
214  * @len:        number of bytes to read
215  *
216  * Default read function for 8bit buswith
217  */
218 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
219 {
220         int i;
221         struct nand_chip *chip = mtd->priv;
222
223         for (i = 0; i < len; i++)
224                 buf[i] = readb(chip->IO_ADDR_R);
225 }
226
227 /**
228  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
229  * @mtd:        MTD device structure
230  * @buf:        buffer containing the data to compare
231  * @len:        number of bytes to compare
232  *
233  * Default verify function for 8bit buswith
234  */
235 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
236 {
237         int i;
238         struct nand_chip *chip = mtd->priv;
239
240         for (i = 0; i < len; i++)
241                 if (buf[i] != readb(chip->IO_ADDR_R))
242                         return -EFAULT;
243         return 0;
244 }
245
246 /**
247  * nand_write_buf16 - [DEFAULT] write buffer to chip
248  * @mtd:        MTD device structure
249  * @buf:        data buffer
250  * @len:        number of bytes to write
251  *
252  * Default write function for 16bit buswith
253  */
254 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
255 {
256         int i;
257         struct nand_chip *chip = mtd->priv;
258         u16 *p = (u16 *) buf;
259         len >>= 1;
260
261         for (i = 0; i < len; i++)
262                 writew(p[i], chip->IO_ADDR_W);
263
264 }
265
266 /**
267  * nand_read_buf16 - [DEFAULT] read chip data into buffer
268  * @mtd:        MTD device structure
269  * @buf:        buffer to store date
270  * @len:        number of bytes to read
271  *
272  * Default read function for 16bit buswith
273  */
274 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
275 {
276         int i;
277         struct nand_chip *chip = mtd->priv;
278         u16 *p = (u16 *) buf;
279         len >>= 1;
280
281         for (i = 0; i < len; i++)
282                 p[i] = readw(chip->IO_ADDR_R);
283 }
284
285 /**
286  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
287  * @mtd:        MTD device structure
288  * @buf:        buffer containing the data to compare
289  * @len:        number of bytes to compare
290  *
291  * Default verify function for 16bit buswith
292  */
293 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
294 {
295         int i;
296         struct nand_chip *chip = mtd->priv;
297         u16 *p = (u16 *) buf;
298         len >>= 1;
299
300         for (i = 0; i < len; i++)
301                 if (p[i] != readw(chip->IO_ADDR_R))
302                         return -EFAULT;
303
304         return 0;
305 }
306
307 /**
308  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
309  * @mtd:        MTD device structure
310  * @ofs:        offset from device start
311  * @getchip:    0, if the chip is already selected
312  *
313  * Check, if the block is bad.
314  */
315 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
316 {
317         int page, chipnr, res = 0;
318         struct nand_chip *chip = mtd->priv;
319         u16 bad;
320
321         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
322
323         if (getchip) {
324                 chipnr = (int)(ofs >> chip->chip_shift);
325
326                 nand_get_device(chip, mtd, FL_READING);
327
328                 /* Select the NAND device */
329                 chip->select_chip(mtd, chipnr);
330         }
331
332         if (chip->options & NAND_BUSWIDTH_16) {
333                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
334                               page);
335                 bad = cpu_to_le16(chip->read_word(mtd));
336                 if (chip->badblockpos & 0x1)
337                         bad >>= 8;
338                 if ((bad & 0xFF) != 0xff)
339                         res = 1;
340         } else {
341                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
342                 if (chip->read_byte(mtd) != 0xff)
343                         res = 1;
344         }
345
346         if (getchip)
347                 nand_release_device(mtd);
348
349         return res;
350 }
351
352 /**
353  * nand_default_block_markbad - [DEFAULT] mark a block bad
354  * @mtd:        MTD device structure
355  * @ofs:        offset from device start
356  *
357  * This is the default implementation, which can be overridden by
358  * a hardware specific driver.
359 */
360 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
361 {
362         struct nand_chip *chip = mtd->priv;
363         uint8_t buf[2] = { 0, 0 };
364         int block, ret;
365
366         /* Get block number */
367         block = (int)(ofs >> chip->bbt_erase_shift);
368         if (chip->bbt)
369                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
370
371         /* Do we have a flash based bad block table ? */
372         if (chip->options & NAND_USE_FLASH_BBT)
373                 ret = nand_update_bbt(mtd, ofs);
374         else {
375                 /* We write two bytes, so we dont have to mess with 16 bit
376                  * access
377                  */
378                 nand_get_device(chip, mtd, FL_WRITING);
379                 ofs += mtd->oobsize;
380                 chip->ops.len = chip->ops.ooblen = 2;
381                 chip->ops.datbuf = NULL;
382                 chip->ops.oobbuf = buf;
383                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
384
385                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
386                 nand_release_device(mtd);
387         }
388         if (!ret)
389                 mtd->ecc_stats.badblocks++;
390
391         return ret;
392 }
393
394 /**
395  * nand_check_wp - [GENERIC] check if the chip is write protected
396  * @mtd:        MTD device structure
397  * Check, if the device is write protected
398  *
399  * The function expects, that the device is already selected
400  */
401 static int nand_check_wp(struct mtd_info *mtd)
402 {
403         struct nand_chip *chip = mtd->priv;
404         /* Check the WP bit */
405         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
406         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
407 }
408
409 /**
410  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
411  * @mtd:        MTD device structure
412  * @ofs:        offset from device start
413  * @getchip:    0, if the chip is already selected
414  * @allowbbt:   1, if its allowed to access the bbt area
415  *
416  * Check, if the block is bad. Either by reading the bad block table or
417  * calling of the scan function.
418  */
419 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
420                                int allowbbt)
421 {
422         struct nand_chip *chip = mtd->priv;
423
424         if (!chip->bbt)
425                 return chip->block_bad(mtd, ofs, getchip);
426
427         /* Return info from the table */
428         return nand_isbad_bbt(mtd, ofs, allowbbt);
429 }
430
431 /*
432  * Wait for the ready pin, after a command
433  * The timeout is catched later.
434  */
435 void nand_wait_ready(struct mtd_info *mtd)
436 {
437         struct nand_chip *chip = mtd->priv;
438         unsigned long timeo = jiffies + 2;
439
440         led_trigger_event(nand_led_trigger, LED_FULL);
441         /* wait until command is processed or timeout occures */
442         do {
443                 if (chip->dev_ready(mtd))
444                         break;
445                 touch_softlockup_watchdog();
446         } while (time_before(jiffies, timeo));
447         led_trigger_event(nand_led_trigger, LED_OFF);
448 }
449 EXPORT_SYMBOL_GPL(nand_wait_ready);
450
451 /**
452  * nand_command - [DEFAULT] Send command to NAND device
453  * @mtd:        MTD device structure
454  * @command:    the command to be sent
455  * @column:     the column address for this command, -1 if none
456  * @page_addr:  the page address for this command, -1 if none
457  *
458  * Send command to NAND device. This function is used for small page
459  * devices (256/512 Bytes per page)
460  */
461 static void nand_command(struct mtd_info *mtd, unsigned int command,
462                          int column, int page_addr)
463 {
464         register struct nand_chip *chip = mtd->priv;
465         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
466
467         /*
468          * Write out the command to the device.
469          */
470         if (command == NAND_CMD_SEQIN) {
471                 int readcmd;
472
473                 if (column >= mtd->writesize) {
474                         /* OOB area */
475                         column -= mtd->writesize;
476                         readcmd = NAND_CMD_READOOB;
477                 } else if (column < 256) {
478                         /* First 256 bytes --> READ0 */
479                         readcmd = NAND_CMD_READ0;
480                 } else {
481                         column -= 256;
482                         readcmd = NAND_CMD_READ1;
483                 }
484                 chip->cmd_ctrl(mtd, readcmd, ctrl);
485                 ctrl &= ~NAND_CTRL_CHANGE;
486         }
487         chip->cmd_ctrl(mtd, command, ctrl);
488
489         /*
490          * Address cycle, when necessary
491          */
492         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
493         /* Serially input address */
494         if (column != -1) {
495                 /* Adjust columns for 16 bit buswidth */
496                 if (chip->options & NAND_BUSWIDTH_16)
497                         column >>= 1;
498                 chip->cmd_ctrl(mtd, column, ctrl);
499                 ctrl &= ~NAND_CTRL_CHANGE;
500         }
501         if (page_addr != -1) {
502                 chip->cmd_ctrl(mtd, page_addr, ctrl);
503                 ctrl &= ~NAND_CTRL_CHANGE;
504                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
505                 /* One more address cycle for devices > 32MiB */
506                 if (chip->chipsize > (32 << 20))
507                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
508         }
509         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
510
511         /*
512          * program and erase have their own busy handlers
513          * status and sequential in needs no delay
514          */
515         switch (command) {
516
517         case NAND_CMD_PAGEPROG:
518         case NAND_CMD_ERASE1:
519         case NAND_CMD_ERASE2:
520         case NAND_CMD_SEQIN:
521         case NAND_CMD_STATUS:
522                 return;
523
524         case NAND_CMD_RESET:
525                 if (chip->dev_ready)
526                         break;
527                 udelay(chip->chip_delay);
528                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
529                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
530                 chip->cmd_ctrl(mtd,
531                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
532                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
533                 return;
534
535                 /* This applies to read commands */
536         default:
537                 /*
538                  * If we don't have access to the busy pin, we apply the given
539                  * command delay
540                  */
541                 if (!chip->dev_ready) {
542                         udelay(chip->chip_delay);
543                         return;
544                 }
545         }
546         /* Apply this short delay always to ensure that we do wait tWB in
547          * any case on any machine. */
548         ndelay(100);
549
550         nand_wait_ready(mtd);
551 }
552
553 /**
554  * nand_command_lp - [DEFAULT] Send command to NAND large page device
555  * @mtd:        MTD device structure
556  * @command:    the command to be sent
557  * @column:     the column address for this command, -1 if none
558  * @page_addr:  the page address for this command, -1 if none
559  *
560  * Send command to NAND device. This is the version for the new large page
561  * devices We dont have the separate regions as we have in the small page
562  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
563  */
564 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
565                             int column, int page_addr)
566 {
567         register struct nand_chip *chip = mtd->priv;
568
569         /* Emulate NAND_CMD_READOOB */
570         if (command == NAND_CMD_READOOB) {
571                 column += mtd->writesize;
572                 command = NAND_CMD_READ0;
573         }
574
575         /* Command latch cycle */
576         chip->cmd_ctrl(mtd, command & 0xff,
577                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
578
579         if (column != -1 || page_addr != -1) {
580                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
581
582                 /* Serially input address */
583                 if (column != -1) {
584                         /* Adjust columns for 16 bit buswidth */
585                         if (chip->options & NAND_BUSWIDTH_16)
586                                 column >>= 1;
587                         chip->cmd_ctrl(mtd, column, ctrl);
588                         ctrl &= ~NAND_CTRL_CHANGE;
589                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
590                 }
591                 if (page_addr != -1) {
592                         chip->cmd_ctrl(mtd, page_addr, ctrl);
593                         chip->cmd_ctrl(mtd, page_addr >> 8,
594                                        NAND_NCE | NAND_ALE);
595                         /* One more address cycle for devices > 128MiB */
596                         if (chip->chipsize > (128 << 20))
597                                 chip->cmd_ctrl(mtd, page_addr >> 16,
598                                                NAND_NCE | NAND_ALE);
599                 }
600         }
601         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
602
603         /*
604          * program and erase have their own busy handlers
605          * status, sequential in, and deplete1 need no delay
606          */
607         switch (command) {
608
609         case NAND_CMD_CACHEDPROG:
610         case NAND_CMD_PAGEPROG:
611         case NAND_CMD_ERASE1:
612         case NAND_CMD_ERASE2:
613         case NAND_CMD_SEQIN:
614         case NAND_CMD_RNDIN:
615         case NAND_CMD_STATUS:
616         case NAND_CMD_DEPLETE1:
617                 return;
618
619                 /*
620                  * read error status commands require only a short delay
621                  */
622         case NAND_CMD_STATUS_ERROR:
623         case NAND_CMD_STATUS_ERROR0:
624         case NAND_CMD_STATUS_ERROR1:
625         case NAND_CMD_STATUS_ERROR2:
626         case NAND_CMD_STATUS_ERROR3:
627                 udelay(chip->chip_delay);
628                 return;
629
630         case NAND_CMD_RESET:
631                 if (chip->dev_ready)
632                         break;
633                 udelay(chip->chip_delay);
634                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
635                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
636                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
637                                NAND_NCE | NAND_CTRL_CHANGE);
638                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
639                 return;
640
641         case NAND_CMD_RNDOUT:
642                 /* No ready / busy check necessary */
643                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
644                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
645                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
646                                NAND_NCE | NAND_CTRL_CHANGE);
647                 return;
648
649         case NAND_CMD_READ0:
650                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
651                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
652                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
653                                NAND_NCE | NAND_CTRL_CHANGE);
654
655                 /* This applies to read commands */
656         default:
657                 /*
658                  * If we don't have access to the busy pin, we apply the given
659                  * command delay
660                  */
661                 if (!chip->dev_ready) {
662                         udelay(chip->chip_delay);
663                         return;
664                 }
665         }
666
667         /* Apply this short delay always to ensure that we do wait tWB in
668          * any case on any machine. */
669         ndelay(100);
670
671         nand_wait_ready(mtd);
672 }
673
674 /**
675  * nand_get_device - [GENERIC] Get chip for selected access
676  * @chip:       the nand chip descriptor
677  * @mtd:        MTD device structure
678  * @new_state:  the state which is requested
679  *
680  * Get the device and lock it for exclusive access
681  */
682 static int
683 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
684 {
685         spinlock_t *lock = &chip->controller->lock;
686         wait_queue_head_t *wq = &chip->controller->wq;
687         DECLARE_WAITQUEUE(wait, current);
688  retry:
689         spin_lock(lock);
690
691         /* Hardware controller shared among independent devices */
692         if (!chip->controller->active)
693                 chip->controller->active = chip;
694
695         if (chip->controller->active == chip && chip->state == FL_READY) {
696                 chip->state = new_state;
697                 spin_unlock(lock);
698                 return 0;
699         }
700         if (new_state == FL_PM_SUSPENDED) {
701                 spin_unlock(lock);
702                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
703         }
704         set_current_state(TASK_UNINTERRUPTIBLE);
705         add_wait_queue(wq, &wait);
706         spin_unlock(lock);
707         schedule();
708         remove_wait_queue(wq, &wait);
709         goto retry;
710 }
711
712 /**
713  * nand_wait - [DEFAULT]  wait until the command is done
714  * @mtd:        MTD device structure
715  * @chip:       NAND chip structure
716  *
717  * Wait for command done. This applies to erase and program only
718  * Erase can take up to 400ms and program up to 20ms according to
719  * general NAND and SmartMedia specs
720  */
721 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
722 {
723
724         unsigned long timeo = jiffies;
725         int status, state = chip->state;
726
727         if (state == FL_ERASING)
728                 timeo += (HZ * 400) / 1000;
729         else
730                 timeo += (HZ * 20) / 1000;
731
732         led_trigger_event(nand_led_trigger, LED_FULL);
733
734         /* Apply this short delay always to ensure that we do wait tWB in
735          * any case on any machine. */
736         ndelay(100);
737
738         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
739                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
740         else
741                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
742
743         while (time_before(jiffies, timeo)) {
744                 if (chip->dev_ready) {
745                         if (chip->dev_ready(mtd))
746                                 break;
747                 } else {
748                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
749                                 break;
750                 }
751                 cond_resched();
752         }
753         led_trigger_event(nand_led_trigger, LED_OFF);
754
755         status = (int)chip->read_byte(mtd);
756         return status;
757 }
758
759 /**
760  * nand_read_page_raw - [Intern] read raw page data without ecc
761  * @mtd:        mtd info structure
762  * @chip:       nand chip info structure
763  * @buf:        buffer to store read data
764  * @page:       page number to read
765  *
766  * Not for syndrome calculating ecc controllers, which use a special oob layout
767  */
768 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
769                               uint8_t *buf, int page)
770 {
771         chip->read_buf(mtd, buf, mtd->writesize);
772         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
773         return 0;
774 }
775
776 /**
777  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
778  * @mtd:        mtd info structure
779  * @chip:       nand chip info structure
780  * @buf:        buffer to store read data
781  * @page:       page number to read
782  *
783  * We need a special oob layout and handling even when OOB isn't used.
784  */
785 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
786                               uint8_t *buf, int page)
787 {
788         int eccsize = chip->ecc.size;
789         int eccbytes = chip->ecc.bytes;
790         uint8_t *oob = chip->oob_poi;
791         int steps, size;
792
793         for (steps = chip->ecc.steps; steps > 0; steps--) {
794                 chip->read_buf(mtd, buf, eccsize);
795                 buf += eccsize;
796
797                 if (chip->ecc.prepad) {
798                         chip->read_buf(mtd, oob, chip->ecc.prepad);
799                         oob += chip->ecc.prepad;
800                 }
801
802                 chip->read_buf(mtd, oob, eccbytes);
803                 oob += eccbytes;
804
805                 if (chip->ecc.postpad) {
806                         chip->read_buf(mtd, oob, chip->ecc.postpad);
807                         oob += chip->ecc.postpad;
808                 }
809         }
810
811         size = mtd->oobsize - (oob - chip->oob_poi);
812         if (size)
813                 chip->read_buf(mtd, oob, size);
814
815         return 0;
816 }
817
818 /**
819  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
820  * @mtd:        mtd info structure
821  * @chip:       nand chip info structure
822  * @buf:        buffer to store read data
823  * @page:       page number to read
824  */
825 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
826                                 uint8_t *buf, int page)
827 {
828         int i, eccsize = chip->ecc.size;
829         int eccbytes = chip->ecc.bytes;
830         int eccsteps = chip->ecc.steps;
831         uint8_t *p = buf;
832         uint8_t *ecc_calc = chip->buffers->ecccalc;
833         uint8_t *ecc_code = chip->buffers->ecccode;
834         uint32_t *eccpos = chip->ecc.layout->eccpos;
835
836         chip->ecc.read_page_raw(mtd, chip, buf, page);
837
838         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
839                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
840
841         for (i = 0; i < chip->ecc.total; i++)
842                 ecc_code[i] = chip->oob_poi[eccpos[i]];
843
844         eccsteps = chip->ecc.steps;
845         p = buf;
846
847         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
848                 int stat;
849
850                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
851                 if (stat < 0)
852                         mtd->ecc_stats.failed++;
853                 else
854                         mtd->ecc_stats.corrected += stat;
855         }
856         return 0;
857 }
858
859 /**
860  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
861  * @mtd:        mtd info structure
862  * @chip:       nand chip info structure
863  * @data_offs:  offset of requested data within the page
864  * @readlen:    data length
865  * @bufpoi:     buffer to store read data
866  */
867 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
868 {
869         int start_step, end_step, num_steps;
870         uint32_t *eccpos = chip->ecc.layout->eccpos;
871         uint8_t *p;
872         int data_col_addr, i, gaps = 0;
873         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
874         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
875
876         /* Column address wihin the page aligned to ECC size (256bytes). */
877         start_step = data_offs / chip->ecc.size;
878         end_step = (data_offs + readlen - 1) / chip->ecc.size;
879         num_steps = end_step - start_step + 1;
880
881         /* Data size aligned to ECC ecc.size*/
882         datafrag_len = num_steps * chip->ecc.size;
883         eccfrag_len = num_steps * chip->ecc.bytes;
884
885         data_col_addr = start_step * chip->ecc.size;
886         /* If we read not a page aligned data */
887         if (data_col_addr != 0)
888                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
889
890         p = bufpoi + data_col_addr;
891         chip->read_buf(mtd, p, datafrag_len);
892
893         /* Calculate  ECC */
894         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
895                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
896
897         /* The performance is faster if to position offsets
898            according to ecc.pos. Let make sure here that
899            there are no gaps in ecc positions */
900         for (i = 0; i < eccfrag_len - 1; i++) {
901                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
902                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
903                         gaps = 1;
904                         break;
905                 }
906         }
907         if (gaps) {
908                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
909                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
910         } else {
911                 /* send the command to read the particular ecc bytes */
912                 /* take care about buswidth alignment in read_buf */
913                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
914                 aligned_len = eccfrag_len;
915                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
916                         aligned_len++;
917                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
918                         aligned_len++;
919
920                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
921                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
922         }
923
924         for (i = 0; i < eccfrag_len; i++)
925                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
926
927         p = bufpoi + data_col_addr;
928         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
929                 int stat;
930
931                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
932                 if (stat == -1)
933                         mtd->ecc_stats.failed++;
934                 else
935                         mtd->ecc_stats.corrected += stat;
936         }
937         return 0;
938 }
939
940 /**
941  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
942  * @mtd:        mtd info structure
943  * @chip:       nand chip info structure
944  * @buf:        buffer to store read data
945  * @page:       page number to read
946  *
947  * Not for syndrome calculating ecc controllers which need a special oob layout
948  */
949 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
950                                 uint8_t *buf, int page)
951 {
952         int i, eccsize = chip->ecc.size;
953         int eccbytes = chip->ecc.bytes;
954         int eccsteps = chip->ecc.steps;
955         uint8_t *p = buf;
956         uint8_t *ecc_calc = chip->buffers->ecccalc;
957         uint8_t *ecc_code = chip->buffers->ecccode;
958         uint32_t *eccpos = chip->ecc.layout->eccpos;
959
960         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
961                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
962                 chip->read_buf(mtd, p, eccsize);
963                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
964         }
965         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
966
967         for (i = 0; i < chip->ecc.total; i++)
968                 ecc_code[i] = chip->oob_poi[eccpos[i]];
969
970         eccsteps = chip->ecc.steps;
971         p = buf;
972
973         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
974                 int stat;
975
976                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
977                 if (stat < 0)
978                         mtd->ecc_stats.failed++;
979                 else
980                         mtd->ecc_stats.corrected += stat;
981         }
982         return 0;
983 }
984
985 /**
986  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
987  * @mtd:        mtd info structure
988  * @chip:       nand chip info structure
989  * @buf:        buffer to store read data
990  * @page:       page number to read
991  *
992  * Hardware ECC for large page chips, require OOB to be read first.
993  * For this ECC mode, the write_page method is re-used from ECC_HW.
994  * These methods read/write ECC from the OOB area, unlike the
995  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
996  * "infix ECC" scheme and reads/writes ECC from the data area, by
997  * overwriting the NAND manufacturer bad block markings.
998  */
999 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1000         struct nand_chip *chip, uint8_t *buf, int page)
1001 {
1002         int i, eccsize = chip->ecc.size;
1003         int eccbytes = chip->ecc.bytes;
1004         int eccsteps = chip->ecc.steps;
1005         uint8_t *p = buf;
1006         uint8_t *ecc_code = chip->buffers->ecccode;
1007         uint32_t *eccpos = chip->ecc.layout->eccpos;
1008         uint8_t *ecc_calc = chip->buffers->ecccalc;
1009
1010         /* Read the OOB area first */
1011         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1012         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1013         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1014
1015         for (i = 0; i < chip->ecc.total; i++)
1016                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1017
1018         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1019                 int stat;
1020
1021                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1022                 chip->read_buf(mtd, p, eccsize);
1023                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1024
1025                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1026                 if (stat < 0)
1027                         mtd->ecc_stats.failed++;
1028                 else
1029                         mtd->ecc_stats.corrected += stat;
1030         }
1031         return 0;
1032 }
1033
1034 /**
1035  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1036  * @mtd:        mtd info structure
1037  * @chip:       nand chip info structure
1038  * @buf:        buffer to store read data
1039  * @page:       page number to read
1040  *
1041  * The hw generator calculates the error syndrome automatically. Therefor
1042  * we need a special oob layout and handling.
1043  */
1044 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1045                                    uint8_t *buf, int page)
1046 {
1047         int i, eccsize = chip->ecc.size;
1048         int eccbytes = chip->ecc.bytes;
1049         int eccsteps = chip->ecc.steps;
1050         uint8_t *p = buf;
1051         uint8_t *oob = chip->oob_poi;
1052
1053         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1054                 int stat;
1055
1056                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1057                 chip->read_buf(mtd, p, eccsize);
1058
1059                 if (chip->ecc.prepad) {
1060                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1061                         oob += chip->ecc.prepad;
1062                 }
1063
1064                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1065                 chip->read_buf(mtd, oob, eccbytes);
1066                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1067
1068                 if (stat < 0)
1069                         mtd->ecc_stats.failed++;
1070                 else
1071                         mtd->ecc_stats.corrected += stat;
1072
1073                 oob += eccbytes;
1074
1075                 if (chip->ecc.postpad) {
1076                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1077                         oob += chip->ecc.postpad;
1078                 }
1079         }
1080
1081         /* Calculate remaining oob bytes */
1082         i = mtd->oobsize - (oob - chip->oob_poi);
1083         if (i)
1084                 chip->read_buf(mtd, oob, i);
1085
1086         return 0;
1087 }
1088
1089 /**
1090  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1091  * @chip:       nand chip structure
1092  * @oob:        oob destination address
1093  * @ops:        oob ops structure
1094  * @len:        size of oob to transfer
1095  */
1096 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1097                                   struct mtd_oob_ops *ops, size_t len)
1098 {
1099         switch(ops->mode) {
1100
1101         case MTD_OOB_PLACE:
1102         case MTD_OOB_RAW:
1103                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1104                 return oob + len;
1105
1106         case MTD_OOB_AUTO: {
1107                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1108                 uint32_t boffs = 0, roffs = ops->ooboffs;
1109                 size_t bytes = 0;
1110
1111                 for(; free->length && len; free++, len -= bytes) {
1112                         /* Read request not from offset 0 ? */
1113                         if (unlikely(roffs)) {
1114                                 if (roffs >= free->length) {
1115                                         roffs -= free->length;
1116                                         continue;
1117                                 }
1118                                 boffs = free->offset + roffs;
1119                                 bytes = min_t(size_t, len,
1120                                               (free->length - roffs));
1121                                 roffs = 0;
1122                         } else {
1123                                 bytes = min_t(size_t, len, free->length);
1124                                 boffs = free->offset;
1125                         }
1126                         memcpy(oob, chip->oob_poi + boffs, bytes);
1127                         oob += bytes;
1128                 }
1129                 return oob;
1130         }
1131         default:
1132                 BUG();
1133         }
1134         return NULL;
1135 }
1136
1137 /**
1138  * nand_do_read_ops - [Internal] Read data with ECC
1139  *
1140  * @mtd:        MTD device structure
1141  * @from:       offset to read from
1142  * @ops:        oob ops structure
1143  *
1144  * Internal function. Called with chip held.
1145  */
1146 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1147                             struct mtd_oob_ops *ops)
1148 {
1149         int chipnr, page, realpage, col, bytes, aligned;
1150         struct nand_chip *chip = mtd->priv;
1151         struct mtd_ecc_stats stats;
1152         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1153         int sndcmd = 1;
1154         int ret = 0;
1155         uint32_t readlen = ops->len;
1156         uint32_t oobreadlen = ops->ooblen;
1157         uint8_t *bufpoi, *oob, *buf;
1158
1159         stats = mtd->ecc_stats;
1160
1161         chipnr = (int)(from >> chip->chip_shift);
1162         chip->select_chip(mtd, chipnr);
1163
1164         realpage = (int)(from >> chip->page_shift);
1165         page = realpage & chip->pagemask;
1166
1167         col = (int)(from & (mtd->writesize - 1));
1168
1169         buf = ops->datbuf;
1170         oob = ops->oobbuf;
1171
1172         while(1) {
1173                 bytes = min(mtd->writesize - col, readlen);
1174                 aligned = (bytes == mtd->writesize);
1175
1176                 /* Is the current page in the buffer ? */
1177                 if (realpage != chip->pagebuf || oob) {
1178                         bufpoi = aligned ? buf : chip->buffers->databuf;
1179
1180                         if (likely(sndcmd)) {
1181                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1182                                 sndcmd = 0;
1183                         }
1184
1185                         /* Now read the page into the buffer */
1186                         if (unlikely(ops->mode == MTD_OOB_RAW))
1187                                 ret = chip->ecc.read_page_raw(mtd, chip,
1188                                                               bufpoi, page);
1189                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1190                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1191                         else
1192                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1193                                                           page);
1194                         if (ret < 0)
1195                                 break;
1196
1197                         /* Transfer not aligned data */
1198                         if (!aligned) {
1199                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1200                                         chip->pagebuf = realpage;
1201                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1202                         }
1203
1204                         buf += bytes;
1205
1206                         if (unlikely(oob)) {
1207                                 /* Raw mode does data:oob:data:oob */
1208                                 if (ops->mode != MTD_OOB_RAW) {
1209                                         int toread = min(oobreadlen,
1210                                                 chip->ecc.layout->oobavail);
1211                                         if (toread) {
1212                                                 oob = nand_transfer_oob(chip,
1213                                                         oob, ops, toread);
1214                                                 oobreadlen -= toread;
1215                                         }
1216                                 } else
1217                                         buf = nand_transfer_oob(chip,
1218                                                 buf, ops, mtd->oobsize);
1219                         }
1220
1221                         if (!(chip->options & NAND_NO_READRDY)) {
1222                                 /*
1223                                  * Apply delay or wait for ready/busy pin. Do
1224                                  * this before the AUTOINCR check, so no
1225                                  * problems arise if a chip which does auto
1226                                  * increment is marked as NOAUTOINCR by the
1227                                  * board driver.
1228                                  */
1229                                 if (!chip->dev_ready)
1230                                         udelay(chip->chip_delay);
1231                                 else
1232                                         nand_wait_ready(mtd);
1233                         }
1234                 } else {
1235                         memcpy(buf, chip->buffers->databuf + col, bytes);
1236                         buf += bytes;
1237                 }
1238
1239                 readlen -= bytes;
1240
1241                 if (!readlen)
1242                         break;
1243
1244                 /* For subsequent reads align to page boundary. */
1245                 col = 0;
1246                 /* Increment page address */
1247                 realpage++;
1248
1249                 page = realpage & chip->pagemask;
1250                 /* Check, if we cross a chip boundary */
1251                 if (!page) {
1252                         chipnr++;
1253                         chip->select_chip(mtd, -1);
1254                         chip->select_chip(mtd, chipnr);
1255                 }
1256
1257                 /* Check, if the chip supports auto page increment
1258                  * or if we have hit a block boundary.
1259                  */
1260                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1261                         sndcmd = 1;
1262         }
1263
1264         ops->retlen = ops->len - (size_t) readlen;
1265         if (oob)
1266                 ops->oobretlen = ops->ooblen - oobreadlen;
1267
1268         if (ret)
1269                 return ret;
1270
1271         if (mtd->ecc_stats.failed - stats.failed)
1272                 return -EBADMSG;
1273
1274         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1275 }
1276
1277 /**
1278  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1279  * @mtd:        MTD device structure
1280  * @from:       offset to read from
1281  * @len:        number of bytes to read
1282  * @retlen:     pointer to variable to store the number of read bytes
1283  * @buf:        the databuffer to put data
1284  *
1285  * Get hold of the chip and call nand_do_read
1286  */
1287 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1288                      size_t *retlen, uint8_t *buf)
1289 {
1290         struct nand_chip *chip = mtd->priv;
1291         int ret;
1292
1293         /* Do not allow reads past end of device */
1294         if ((from + len) > mtd->size)
1295                 return -EINVAL;
1296         if (!len)
1297                 return 0;
1298
1299         nand_get_device(chip, mtd, FL_READING);
1300
1301         chip->ops.len = len;
1302         chip->ops.datbuf = buf;
1303         chip->ops.oobbuf = NULL;
1304
1305         ret = nand_do_read_ops(mtd, from, &chip->ops);
1306
1307         *retlen = chip->ops.retlen;
1308
1309         nand_release_device(mtd);
1310
1311         return ret;
1312 }
1313
1314 /**
1315  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1316  * @mtd:        mtd info structure
1317  * @chip:       nand chip info structure
1318  * @page:       page number to read
1319  * @sndcmd:     flag whether to issue read command or not
1320  */
1321 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1322                              int page, int sndcmd)
1323 {
1324         if (sndcmd) {
1325                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1326                 sndcmd = 0;
1327         }
1328         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1329         return sndcmd;
1330 }
1331
1332 /**
1333  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1334  *                          with syndromes
1335  * @mtd:        mtd info structure
1336  * @chip:       nand chip info structure
1337  * @page:       page number to read
1338  * @sndcmd:     flag whether to issue read command or not
1339  */
1340 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1341                                   int page, int sndcmd)
1342 {
1343         uint8_t *buf = chip->oob_poi;
1344         int length = mtd->oobsize;
1345         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1346         int eccsize = chip->ecc.size;
1347         uint8_t *bufpoi = buf;
1348         int i, toread, sndrnd = 0, pos;
1349
1350         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1351         for (i = 0; i < chip->ecc.steps; i++) {
1352                 if (sndrnd) {
1353                         pos = eccsize + i * (eccsize + chunk);
1354                         if (mtd->writesize > 512)
1355                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1356                         else
1357                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1358                 } else
1359                         sndrnd = 1;
1360                 toread = min_t(int, length, chunk);
1361                 chip->read_buf(mtd, bufpoi, toread);
1362                 bufpoi += toread;
1363                 length -= toread;
1364         }
1365         if (length > 0)
1366                 chip->read_buf(mtd, bufpoi, length);
1367
1368         return 1;
1369 }
1370
1371 /**
1372  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1373  * @mtd:        mtd info structure
1374  * @chip:       nand chip info structure
1375  * @page:       page number to write
1376  */
1377 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1378                               int page)
1379 {
1380         int status = 0;
1381         const uint8_t *buf = chip->oob_poi;
1382         int length = mtd->oobsize;
1383
1384         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1385         chip->write_buf(mtd, buf, length);
1386         /* Send command to program the OOB data */
1387         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1388
1389         status = chip->waitfunc(mtd, chip);
1390
1391         return status & NAND_STATUS_FAIL ? -EIO : 0;
1392 }
1393
1394 /**
1395  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1396  *                           with syndrome - only for large page flash !
1397  * @mtd:        mtd info structure
1398  * @chip:       nand chip info structure
1399  * @page:       page number to write
1400  */
1401 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1402                                    struct nand_chip *chip, int page)
1403 {
1404         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1405         int eccsize = chip->ecc.size, length = mtd->oobsize;
1406         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1407         const uint8_t *bufpoi = chip->oob_poi;
1408
1409         /*
1410          * data-ecc-data-ecc ... ecc-oob
1411          * or
1412          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1413          */
1414         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1415                 pos = steps * (eccsize + chunk);
1416                 steps = 0;
1417         } else
1418                 pos = eccsize;
1419
1420         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1421         for (i = 0; i < steps; i++) {
1422                 if (sndcmd) {
1423                         if (mtd->writesize <= 512) {
1424                                 uint32_t fill = 0xFFFFFFFF;
1425
1426                                 len = eccsize;
1427                                 while (len > 0) {
1428                                         int num = min_t(int, len, 4);
1429                                         chip->write_buf(mtd, (uint8_t *)&fill,
1430                                                         num);
1431                                         len -= num;
1432                                 }
1433                         } else {
1434                                 pos = eccsize + i * (eccsize + chunk);
1435                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1436                         }
1437                 } else
1438                         sndcmd = 1;
1439                 len = min_t(int, length, chunk);
1440                 chip->write_buf(mtd, bufpoi, len);
1441                 bufpoi += len;
1442                 length -= len;
1443         }
1444         if (length > 0)
1445                 chip->write_buf(mtd, bufpoi, length);
1446
1447         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1448         status = chip->waitfunc(mtd, chip);
1449
1450         return status & NAND_STATUS_FAIL ? -EIO : 0;
1451 }
1452
1453 /**
1454  * nand_do_read_oob - [Intern] NAND read out-of-band
1455  * @mtd:        MTD device structure
1456  * @from:       offset to read from
1457  * @ops:        oob operations description structure
1458  *
1459  * NAND read out-of-band data from the spare area
1460  */
1461 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1462                             struct mtd_oob_ops *ops)
1463 {
1464         int page, realpage, chipnr, sndcmd = 1;
1465         struct nand_chip *chip = mtd->priv;
1466         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1467         int readlen = ops->ooblen;
1468         int len;
1469         uint8_t *buf = ops->oobbuf;
1470
1471         DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1472                         __func__, (unsigned long long)from, readlen);
1473
1474         if (ops->mode == MTD_OOB_AUTO)
1475                 len = chip->ecc.layout->oobavail;
1476         else
1477                 len = mtd->oobsize;
1478
1479         if (unlikely(ops->ooboffs >= len)) {
1480                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1481                                         "outside oob\n", __func__);
1482                 return -EINVAL;
1483         }
1484
1485         /* Do not allow reads past end of device */
1486         if (unlikely(from >= mtd->size ||
1487                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1488                                         (from >> chip->page_shift)) * len)) {
1489                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1490                                         "of device\n", __func__);
1491                 return -EINVAL;
1492         }
1493
1494         chipnr = (int)(from >> chip->chip_shift);
1495         chip->select_chip(mtd, chipnr);
1496
1497         /* Shift to get page */
1498         realpage = (int)(from >> chip->page_shift);
1499         page = realpage & chip->pagemask;
1500
1501         while(1) {
1502                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1503
1504                 len = min(len, readlen);
1505                 buf = nand_transfer_oob(chip, buf, ops, len);
1506
1507                 if (!(chip->options & NAND_NO_READRDY)) {
1508                         /*
1509                          * Apply delay or wait for ready/busy pin. Do this
1510                          * before the AUTOINCR check, so no problems arise if a
1511                          * chip which does auto increment is marked as
1512                          * NOAUTOINCR by the board driver.
1513                          */
1514                         if (!chip->dev_ready)
1515                                 udelay(chip->chip_delay);
1516                         else
1517                                 nand_wait_ready(mtd);
1518                 }
1519
1520                 readlen -= len;
1521                 if (!readlen)
1522                         break;
1523
1524                 /* Increment page address */
1525                 realpage++;
1526
1527                 page = realpage & chip->pagemask;
1528                 /* Check, if we cross a chip boundary */
1529                 if (!page) {
1530                         chipnr++;
1531                         chip->select_chip(mtd, -1);
1532                         chip->select_chip(mtd, chipnr);
1533                 }
1534
1535                 /* Check, if the chip supports auto page increment
1536                  * or if we have hit a block boundary.
1537                  */
1538                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1539                         sndcmd = 1;
1540         }
1541
1542         ops->oobretlen = ops->ooblen;
1543         return 0;
1544 }
1545
1546 /**
1547  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1548  * @mtd:        MTD device structure
1549  * @from:       offset to read from
1550  * @ops:        oob operation description structure
1551  *
1552  * NAND read data and/or out-of-band data
1553  */
1554 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1555                          struct mtd_oob_ops *ops)
1556 {
1557         struct nand_chip *chip = mtd->priv;
1558         int ret = -ENOTSUPP;
1559
1560         ops->retlen = 0;
1561
1562         /* Do not allow reads past end of device */
1563         if (ops->datbuf && (from + ops->len) > mtd->size) {
1564                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1565                                 "beyond end of device\n", __func__);
1566                 return -EINVAL;
1567         }
1568
1569         nand_get_device(chip, mtd, FL_READING);
1570
1571         switch(ops->mode) {
1572         case MTD_OOB_PLACE:
1573         case MTD_OOB_AUTO:
1574         case MTD_OOB_RAW:
1575                 break;
1576
1577         default:
1578                 goto out;
1579         }
1580
1581         if (!ops->datbuf)
1582                 ret = nand_do_read_oob(mtd, from, ops);
1583         else
1584                 ret = nand_do_read_ops(mtd, from, ops);
1585
1586  out:
1587         nand_release_device(mtd);
1588         return ret;
1589 }
1590
1591
1592 /**
1593  * nand_write_page_raw - [Intern] raw page write function
1594  * @mtd:        mtd info structure
1595  * @chip:       nand chip info structure
1596  * @buf:        data buffer
1597  *
1598  * Not for syndrome calculating ecc controllers, which use a special oob layout
1599  */
1600 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1601                                 const uint8_t *buf)
1602 {
1603         chip->write_buf(mtd, buf, mtd->writesize);
1604         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1605 }
1606
1607 /**
1608  * nand_write_page_raw_syndrome - [Intern] raw page write function
1609  * @mtd:        mtd info structure
1610  * @chip:       nand chip info structure
1611  * @buf:        data buffer
1612  *
1613  * We need a special oob layout and handling even when ECC isn't checked.
1614  */
1615 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1616                                 const uint8_t *buf)
1617 {
1618         int eccsize = chip->ecc.size;
1619         int eccbytes = chip->ecc.bytes;
1620         uint8_t *oob = chip->oob_poi;
1621         int steps, size;
1622
1623         for (steps = chip->ecc.steps; steps > 0; steps--) {
1624                 chip->write_buf(mtd, buf, eccsize);
1625                 buf += eccsize;
1626
1627                 if (chip->ecc.prepad) {
1628                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1629                         oob += chip->ecc.prepad;
1630                 }
1631
1632                 chip->read_buf(mtd, oob, eccbytes);
1633                 oob += eccbytes;
1634
1635                 if (chip->ecc.postpad) {
1636                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1637                         oob += chip->ecc.postpad;
1638                 }
1639         }
1640
1641         size = mtd->oobsize - (oob - chip->oob_poi);
1642         if (size)
1643                 chip->write_buf(mtd, oob, size);
1644 }
1645 /**
1646  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1647  * @mtd:        mtd info structure
1648  * @chip:       nand chip info structure
1649  * @buf:        data buffer
1650  */
1651 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1652                                   const uint8_t *buf)
1653 {
1654         int i, eccsize = chip->ecc.size;
1655         int eccbytes = chip->ecc.bytes;
1656         int eccsteps = chip->ecc.steps;
1657         uint8_t *ecc_calc = chip->buffers->ecccalc;
1658         const uint8_t *p = buf;
1659         uint32_t *eccpos = chip->ecc.layout->eccpos;
1660
1661         /* Software ecc calculation */
1662         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1663                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1664
1665         for (i = 0; i < chip->ecc.total; i++)
1666                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1667
1668         chip->ecc.write_page_raw(mtd, chip, buf);
1669 }
1670
1671 /**
1672  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1673  * @mtd:        mtd info structure
1674  * @chip:       nand chip info structure
1675  * @buf:        data buffer
1676  */
1677 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1678                                   const uint8_t *buf)
1679 {
1680         int i, eccsize = chip->ecc.size;
1681         int eccbytes = chip->ecc.bytes;
1682         int eccsteps = chip->ecc.steps;
1683         uint8_t *ecc_calc = chip->buffers->ecccalc;
1684         const uint8_t *p = buf;
1685         uint32_t *eccpos = chip->ecc.layout->eccpos;
1686
1687         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1688                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1689                 chip->write_buf(mtd, p, eccsize);
1690                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1691         }
1692
1693         for (i = 0; i < chip->ecc.total; i++)
1694                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1695
1696         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1697 }
1698
1699 /**
1700  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1701  * @mtd:        mtd info structure
1702  * @chip:       nand chip info structure
1703  * @buf:        data buffer
1704  *
1705  * The hw generator calculates the error syndrome automatically. Therefor
1706  * we need a special oob layout and handling.
1707  */
1708 static void nand_write_page_syndrome(struct mtd_info *mtd,
1709                                     struct nand_chip *chip, const uint8_t *buf)
1710 {
1711         int i, eccsize = chip->ecc.size;
1712         int eccbytes = chip->ecc.bytes;
1713         int eccsteps = chip->ecc.steps;
1714         const uint8_t *p = buf;
1715         uint8_t *oob = chip->oob_poi;
1716
1717         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1718
1719                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1720                 chip->write_buf(mtd, p, eccsize);
1721
1722                 if (chip->ecc.prepad) {
1723                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1724                         oob += chip->ecc.prepad;
1725                 }
1726
1727                 chip->ecc.calculate(mtd, p, oob);
1728                 chip->write_buf(mtd, oob, eccbytes);
1729                 oob += eccbytes;
1730
1731                 if (chip->ecc.postpad) {
1732                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1733                         oob += chip->ecc.postpad;
1734                 }
1735         }
1736
1737         /* Calculate remaining oob bytes */
1738         i = mtd->oobsize - (oob - chip->oob_poi);
1739         if (i)
1740                 chip->write_buf(mtd, oob, i);
1741 }
1742
1743 /**
1744  * nand_write_page - [REPLACEABLE] write one page
1745  * @mtd:        MTD device structure
1746  * @chip:       NAND chip descriptor
1747  * @buf:        the data to write
1748  * @page:       page number to write
1749  * @cached:     cached programming
1750  * @raw:        use _raw version of write_page
1751  */
1752 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1753                            const uint8_t *buf, int page, int cached, int raw)
1754 {
1755         int status;
1756
1757         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1758
1759         if (unlikely(raw))
1760                 chip->ecc.write_page_raw(mtd, chip, buf);
1761         else
1762                 chip->ecc.write_page(mtd, chip, buf);
1763
1764         /*
1765          * Cached progamming disabled for now, Not sure if its worth the
1766          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1767          */
1768         cached = 0;
1769
1770         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1771
1772                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1773                 status = chip->waitfunc(mtd, chip);
1774                 /*
1775                  * See if operation failed and additional status checks are
1776                  * available
1777                  */
1778                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1779                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1780                                                page);
1781
1782                 if (status & NAND_STATUS_FAIL)
1783                         return -EIO;
1784         } else {
1785                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1786                 status = chip->waitfunc(mtd, chip);
1787         }
1788
1789 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1790         /* Send command to read back the data */
1791         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1792
1793         if (chip->verify_buf(mtd, buf, mtd->writesize))
1794                 return -EIO;
1795 #endif
1796         return 0;
1797 }
1798
1799 /**
1800  * nand_fill_oob - [Internal] Transfer client buffer to oob
1801  * @chip:       nand chip structure
1802  * @oob:        oob data buffer
1803  * @ops:        oob ops structure
1804  */
1805 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1806                                   struct mtd_oob_ops *ops)
1807 {
1808         size_t len = ops->ooblen;
1809
1810         switch(ops->mode) {
1811
1812         case MTD_OOB_PLACE:
1813         case MTD_OOB_RAW:
1814                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1815                 return oob + len;
1816
1817         case MTD_OOB_AUTO: {
1818                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1819                 uint32_t boffs = 0, woffs = ops->ooboffs;
1820                 size_t bytes = 0;
1821
1822                 for(; free->length && len; free++, len -= bytes) {
1823                         /* Write request not from offset 0 ? */
1824                         if (unlikely(woffs)) {
1825                                 if (woffs >= free->length) {
1826                                         woffs -= free->length;
1827                                         continue;
1828                                 }
1829                                 boffs = free->offset + woffs;
1830                                 bytes = min_t(size_t, len,
1831                                               (free->length - woffs));
1832                                 woffs = 0;
1833                         } else {
1834                                 bytes = min_t(size_t, len, free->length);
1835                                 boffs = free->offset;
1836                         }
1837                         memcpy(chip->oob_poi + boffs, oob, bytes);
1838                         oob += bytes;
1839                 }
1840                 return oob;
1841         }
1842         default:
1843                 BUG();
1844         }
1845         return NULL;
1846 }
1847
1848 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1849
1850 /**
1851  * nand_do_write_ops - [Internal] NAND write with ECC
1852  * @mtd:        MTD device structure
1853  * @to:         offset to write to
1854  * @ops:        oob operations description structure
1855  *
1856  * NAND write with ECC
1857  */
1858 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1859                              struct mtd_oob_ops *ops)
1860 {
1861         int chipnr, realpage, page, blockmask, column;
1862         struct nand_chip *chip = mtd->priv;
1863         uint32_t writelen = ops->len;
1864         uint8_t *oob = ops->oobbuf;
1865         uint8_t *buf = ops->datbuf;
1866         int ret, subpage;
1867
1868         ops->retlen = 0;
1869         if (!writelen)
1870                 return 0;
1871
1872         /* reject writes, which are not page aligned */
1873         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1874                 printk(KERN_NOTICE "%s: Attempt to write not "
1875                                 "page aligned data\n", __func__);
1876                 return -EINVAL;
1877         }
1878
1879         column = to & (mtd->writesize - 1);
1880         subpage = column || (writelen & (mtd->writesize - 1));
1881
1882         if (subpage && oob)
1883                 return -EINVAL;
1884
1885         chipnr = (int)(to >> chip->chip_shift);
1886         chip->select_chip(mtd, chipnr);
1887
1888         /* Check, if it is write protected */
1889         if (nand_check_wp(mtd))
1890                 return -EIO;
1891
1892         realpage = (int)(to >> chip->page_shift);
1893         page = realpage & chip->pagemask;
1894         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1895
1896         /* Invalidate the page cache, when we write to the cached page */
1897         if (to <= (chip->pagebuf << chip->page_shift) &&
1898             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1899                 chip->pagebuf = -1;
1900
1901         /* If we're not given explicit OOB data, let it be 0xFF */
1902         if (likely(!oob))
1903                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1904
1905         while(1) {
1906                 int bytes = mtd->writesize;
1907                 int cached = writelen > bytes && page != blockmask;
1908                 uint8_t *wbuf = buf;
1909
1910                 /* Partial page write ? */
1911                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1912                         cached = 0;
1913                         bytes = min_t(int, bytes - column, (int) writelen);
1914                         chip->pagebuf = -1;
1915                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1916                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1917                         wbuf = chip->buffers->databuf;
1918                 }
1919
1920                 if (unlikely(oob))
1921                         oob = nand_fill_oob(chip, oob, ops);
1922
1923                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1924                                        (ops->mode == MTD_OOB_RAW));
1925                 if (ret)
1926                         break;
1927
1928                 writelen -= bytes;
1929                 if (!writelen)
1930                         break;
1931
1932                 column = 0;
1933                 buf += bytes;
1934                 realpage++;
1935
1936                 page = realpage & chip->pagemask;
1937                 /* Check, if we cross a chip boundary */
1938                 if (!page) {
1939                         chipnr++;
1940                         chip->select_chip(mtd, -1);
1941                         chip->select_chip(mtd, chipnr);
1942                 }
1943         }
1944
1945         ops->retlen = ops->len - writelen;
1946         if (unlikely(oob))
1947                 ops->oobretlen = ops->ooblen;
1948         return ret;
1949 }
1950
1951 /**
1952  * nand_write - [MTD Interface] NAND write with ECC
1953  * @mtd:        MTD device structure
1954  * @to:         offset to write to
1955  * @len:        number of bytes to write
1956  * @retlen:     pointer to variable to store the number of written bytes
1957  * @buf:        the data to write
1958  *
1959  * NAND write with ECC
1960  */
1961 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1962                           size_t *retlen, const uint8_t *buf)
1963 {
1964         struct nand_chip *chip = mtd->priv;
1965         int ret;
1966
1967         /* Do not allow reads past end of device */
1968         if ((to + len) > mtd->size)
1969                 return -EINVAL;
1970         if (!len)
1971                 return 0;
1972
1973         nand_get_device(chip, mtd, FL_WRITING);
1974
1975         chip->ops.len = len;
1976         chip->ops.datbuf = (uint8_t *)buf;
1977         chip->ops.oobbuf = NULL;
1978
1979         ret = nand_do_write_ops(mtd, to, &chip->ops);
1980
1981         *retlen = chip->ops.retlen;
1982
1983         nand_release_device(mtd);
1984
1985         return ret;
1986 }
1987
1988 /**
1989  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1990  * @mtd:        MTD device structure
1991  * @to:         offset to write to
1992  * @ops:        oob operation description structure
1993  *
1994  * NAND write out-of-band
1995  */
1996 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1997                              struct mtd_oob_ops *ops)
1998 {
1999         int chipnr, page, status, len;
2000         struct nand_chip *chip = mtd->priv;
2001
2002         DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2003                          __func__, (unsigned int)to, (int)ops->ooblen);
2004
2005         if (ops->mode == MTD_OOB_AUTO)
2006                 len = chip->ecc.layout->oobavail;
2007         else
2008                 len = mtd->oobsize;
2009
2010         /* Do not allow write past end of page */
2011         if ((ops->ooboffs + ops->ooblen) > len) {
2012                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2013                                 "past end of page\n", __func__);
2014                 return -EINVAL;
2015         }
2016
2017         if (unlikely(ops->ooboffs >= len)) {
2018                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2019                                 "write outside oob\n", __func__);
2020                 return -EINVAL;
2021         }
2022
2023         /* Do not allow reads past end of device */
2024         if (unlikely(to >= mtd->size ||
2025                      ops->ooboffs + ops->ooblen >
2026                         ((mtd->size >> chip->page_shift) -
2027                          (to >> chip->page_shift)) * len)) {
2028                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2029                                 "end of device\n", __func__);
2030                 return -EINVAL;
2031         }
2032
2033         chipnr = (int)(to >> chip->chip_shift);
2034         chip->select_chip(mtd, chipnr);
2035
2036         /* Shift to get page */
2037         page = (int)(to >> chip->page_shift);
2038
2039         /*
2040          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2041          * of my DiskOnChip 2000 test units) will clear the whole data page too
2042          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2043          * it in the doc2000 driver in August 1999.  dwmw2.
2044          */
2045         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2046
2047         /* Check, if it is write protected */
2048         if (nand_check_wp(mtd))
2049                 return -EROFS;
2050
2051         /* Invalidate the page cache, if we write to the cached page */
2052         if (page == chip->pagebuf)
2053                 chip->pagebuf = -1;
2054
2055         memset(chip->oob_poi, 0xff, mtd->oobsize);
2056         nand_fill_oob(chip, ops->oobbuf, ops);
2057         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2058         memset(chip->oob_poi, 0xff, mtd->oobsize);
2059
2060         if (status)
2061                 return status;
2062
2063         ops->oobretlen = ops->ooblen;
2064
2065         return 0;
2066 }
2067
2068 /**
2069  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2070  * @mtd:        MTD device structure
2071  * @to:         offset to write to
2072  * @ops:        oob operation description structure
2073  */
2074 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2075                           struct mtd_oob_ops *ops)
2076 {
2077         struct nand_chip *chip = mtd->priv;
2078         int ret = -ENOTSUPP;
2079
2080         ops->retlen = 0;
2081
2082         /* Do not allow writes past end of device */
2083         if (ops->datbuf && (to + ops->len) > mtd->size) {
2084                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2085                                 "end of device\n", __func__);
2086                 return -EINVAL;
2087         }
2088
2089         nand_get_device(chip, mtd, FL_WRITING);
2090
2091         switch(ops->mode) {
2092         case MTD_OOB_PLACE:
2093         case MTD_OOB_AUTO:
2094         case MTD_OOB_RAW:
2095                 break;
2096
2097         default:
2098                 goto out;
2099         }
2100
2101         if (!ops->datbuf)
2102                 ret = nand_do_write_oob(mtd, to, ops);
2103         else
2104                 ret = nand_do_write_ops(mtd, to, ops);
2105
2106  out:
2107         nand_release_device(mtd);
2108         return ret;
2109 }
2110
2111 /**
2112  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2113  * @mtd:        MTD device structure
2114  * @page:       the page address of the block which will be erased
2115  *
2116  * Standard erase command for NAND chips
2117  */
2118 static void single_erase_cmd(struct mtd_info *mtd, int page)
2119 {
2120         struct nand_chip *chip = mtd->priv;
2121         /* Send commands to erase a block */
2122         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2123         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2124 }
2125
2126 /**
2127  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2128  * @mtd:        MTD device structure
2129  * @page:       the page address of the block which will be erased
2130  *
2131  * AND multi block erase command function
2132  * Erase 4 consecutive blocks
2133  */
2134 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2135 {
2136         struct nand_chip *chip = mtd->priv;
2137         /* Send commands to erase a block */
2138         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2139         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2140         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2141         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2142         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2143 }
2144
2145 /**
2146  * nand_erase - [MTD Interface] erase block(s)
2147  * @mtd:        MTD device structure
2148  * @instr:      erase instruction
2149  *
2150  * Erase one ore more blocks
2151  */
2152 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2153 {
2154         return nand_erase_nand(mtd, instr, 0);
2155 }
2156
2157 #define BBT_PAGE_MASK   0xffffff3f
2158 /**
2159  * nand_erase_nand - [Internal] erase block(s)
2160  * @mtd:        MTD device structure
2161  * @instr:      erase instruction
2162  * @allowbbt:   allow erasing the bbt area
2163  *
2164  * Erase one ore more blocks
2165  */
2166 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2167                     int allowbbt)
2168 {
2169         int page, status, pages_per_block, ret, chipnr;
2170         struct nand_chip *chip = mtd->priv;
2171         loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2172         unsigned int bbt_masked_page = 0xffffffff;
2173         loff_t len;
2174
2175         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2176                                 __func__, (unsigned long long)instr->addr,
2177                                 (unsigned long long)instr->len);
2178
2179         /* Start address must align on block boundary */
2180         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2181                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
2182                 return -EINVAL;
2183         }
2184
2185         /* Length must align on block boundary */
2186         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2187                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
2188                                         __func__);
2189                 return -EINVAL;
2190         }
2191
2192         /* Do not allow erase past end of device */
2193         if ((instr->len + instr->addr) > mtd->size) {
2194                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Erase past end of device\n",
2195                                         __func__);
2196                 return -EINVAL;
2197         }
2198
2199         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2200
2201         /* Grab the lock and see if the device is available */
2202         nand_get_device(chip, mtd, FL_ERASING);
2203
2204         /* Shift to get first page */
2205         page = (int)(instr->addr >> chip->page_shift);
2206         chipnr = (int)(instr->addr >> chip->chip_shift);
2207
2208         /* Calculate pages in each block */
2209         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2210
2211         /* Select the NAND device */
2212         chip->select_chip(mtd, chipnr);
2213
2214         /* Check, if it is write protected */
2215         if (nand_check_wp(mtd)) {
2216                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2217                                         __func__);
2218                 instr->state = MTD_ERASE_FAILED;
2219                 goto erase_exit;
2220         }
2221
2222         /*
2223          * If BBT requires refresh, set the BBT page mask to see if the BBT
2224          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2225          * can not be matched. This is also done when the bbt is actually
2226          * erased to avoid recusrsive updates
2227          */
2228         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2229                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2230
2231         /* Loop through the pages */
2232         len = instr->len;
2233
2234         instr->state = MTD_ERASING;
2235
2236         while (len) {
2237                 /*
2238                  * heck if we have a bad block, we do not erase bad blocks !
2239                  */
2240                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2241                                         chip->page_shift, 0, allowbbt)) {
2242                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2243                                         "at page 0x%08x\n", __func__, page);
2244                         instr->state = MTD_ERASE_FAILED;
2245                         goto erase_exit;
2246                 }
2247
2248                 /*
2249                  * Invalidate the page cache, if we erase the block which
2250                  * contains the current cached page
2251                  */
2252                 if (page <= chip->pagebuf && chip->pagebuf <
2253                     (page + pages_per_block))
2254                         chip->pagebuf = -1;
2255
2256                 chip->erase_cmd(mtd, page & chip->pagemask);
2257
2258                 status = chip->waitfunc(mtd, chip);
2259
2260                 /*
2261                  * See if operation failed and additional status checks are
2262                  * available
2263                  */
2264                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2265                         status = chip->errstat(mtd, chip, FL_ERASING,
2266                                                status, page);
2267
2268                 /* See if block erase succeeded */
2269                 if (status & NAND_STATUS_FAIL) {
2270                         DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2271                                         "page 0x%08x\n", __func__, page);
2272                         instr->state = MTD_ERASE_FAILED;
2273                         instr->fail_addr =
2274                                 ((loff_t)page << chip->page_shift);
2275                         goto erase_exit;
2276                 }
2277
2278                 /*
2279                  * If BBT requires refresh, set the BBT rewrite flag to the
2280                  * page being erased
2281                  */
2282                 if (bbt_masked_page != 0xffffffff &&
2283                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2284                             rewrite_bbt[chipnr] =
2285                                         ((loff_t)page << chip->page_shift);
2286
2287                 /* Increment page address and decrement length */
2288                 len -= (1 << chip->phys_erase_shift);
2289                 page += pages_per_block;
2290
2291                 /* Check, if we cross a chip boundary */
2292                 if (len && !(page & chip->pagemask)) {
2293                         chipnr++;
2294                         chip->select_chip(mtd, -1);
2295                         chip->select_chip(mtd, chipnr);
2296
2297                         /*
2298                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2299                          * page mask to see if this BBT should be rewritten
2300                          */
2301                         if (bbt_masked_page != 0xffffffff &&
2302                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2303                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2304                                         BBT_PAGE_MASK;
2305                 }
2306         }
2307         instr->state = MTD_ERASE_DONE;
2308
2309  erase_exit:
2310
2311         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2312
2313         /* Deselect and wake up anyone waiting on the device */
2314         nand_release_device(mtd);
2315
2316         /* Do call back function */
2317         if (!ret)
2318                 mtd_erase_callback(instr);
2319
2320         /*
2321          * If BBT requires refresh and erase was successful, rewrite any
2322          * selected bad block tables
2323          */
2324         if (bbt_masked_page == 0xffffffff || ret)
2325                 return ret;
2326
2327         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2328                 if (!rewrite_bbt[chipnr])
2329                         continue;
2330                 /* update the BBT for chip */
2331                 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2332                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2333                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2334                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2335         }
2336
2337         /* Return more or less happy */
2338         return ret;
2339 }
2340
2341 /**
2342  * nand_sync - [MTD Interface] sync
2343  * @mtd:        MTD device structure
2344  *
2345  * Sync is actually a wait for chip ready function
2346  */
2347 static void nand_sync(struct mtd_info *mtd)
2348 {
2349         struct nand_chip *chip = mtd->priv;
2350
2351         DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2352
2353         /* Grab the lock and see if the device is available */
2354         nand_get_device(chip, mtd, FL_SYNCING);
2355         /* Release it and go back */
2356         nand_release_device(mtd);
2357 }
2358
2359 /**
2360  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2361  * @mtd:        MTD device structure
2362  * @offs:       offset relative to mtd start
2363  */
2364 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2365 {
2366         /* Check for invalid offset */
2367         if (offs > mtd->size)
2368                 return -EINVAL;
2369
2370         return nand_block_checkbad(mtd, offs, 1, 0);
2371 }
2372
2373 /**
2374  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2375  * @mtd:        MTD device structure
2376  * @ofs:        offset relative to mtd start
2377  */
2378 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2379 {
2380         struct nand_chip *chip = mtd->priv;
2381         int ret;
2382
2383         if ((ret = nand_block_isbad(mtd, ofs))) {
2384                 /* If it was bad already, return success and do nothing. */
2385                 if (ret > 0)
2386                         return 0;
2387                 return ret;
2388         }
2389
2390         return chip->block_markbad(mtd, ofs);
2391 }
2392
2393 /**
2394  * nand_suspend - [MTD Interface] Suspend the NAND flash
2395  * @mtd:        MTD device structure
2396  */
2397 static int nand_suspend(struct mtd_info *mtd)
2398 {
2399         struct nand_chip *chip = mtd->priv;
2400
2401         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2402 }
2403
2404 /**
2405  * nand_resume - [MTD Interface] Resume the NAND flash
2406  * @mtd:        MTD device structure
2407  */
2408 static void nand_resume(struct mtd_info *mtd)
2409 {
2410         struct nand_chip *chip = mtd->priv;
2411
2412         if (chip->state == FL_PM_SUSPENDED)
2413                 nand_release_device(mtd);
2414         else
2415                 printk(KERN_ERR "%s called for a chip which is not "
2416                        "in suspended state\n", __func__);
2417 }
2418
2419 /*
2420  * Set default functions
2421  */
2422 static void nand_set_defaults(struct nand_chip *chip, int busw)
2423 {
2424         /* check for proper chip_delay setup, set 20us if not */
2425         if (!chip->chip_delay)
2426                 chip->chip_delay = 20;
2427
2428         /* check, if a user supplied command function given */
2429         if (chip->cmdfunc == NULL)
2430                 chip->cmdfunc = nand_command;
2431
2432         /* check, if a user supplied wait function given */
2433         if (chip->waitfunc == NULL)
2434                 chip->waitfunc = nand_wait;
2435
2436         if (!chip->select_chip)
2437                 chip->select_chip = nand_select_chip;
2438         if (!chip->read_byte)
2439                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2440         if (!chip->read_word)
2441                 chip->read_word = nand_read_word;
2442         if (!chip->block_bad)
2443                 chip->block_bad = nand_block_bad;
2444         if (!chip->block_markbad)
2445                 chip->block_markbad = nand_default_block_markbad;
2446         if (!chip->write_buf)
2447                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2448         if (!chip->read_buf)
2449                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2450         if (!chip->verify_buf)
2451                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2452         if (!chip->scan_bbt)
2453                 chip->scan_bbt = nand_default_bbt;
2454
2455         if (!chip->controller) {
2456                 chip->controller = &chip->hwcontrol;
2457                 spin_lock_init(&chip->controller->lock);
2458                 init_waitqueue_head(&chip->controller->wq);
2459         }
2460
2461 }
2462
2463 /*
2464  * Get the flash and manufacturer id and lookup if the type is supported
2465  */
2466 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2467                                                   struct nand_chip *chip,
2468                                                   int busw, int *maf_id)
2469 {
2470         struct nand_flash_dev *type = NULL;
2471         int i, dev_id, maf_idx;
2472         int tmp_id, tmp_manf;
2473
2474         /* Select the device */
2475         chip->select_chip(mtd, 0);
2476
2477         /*
2478          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2479          * after power-up
2480          */
2481         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2482
2483         /* Send the command for reading device ID */
2484         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2485
2486         /* Read manufacturer and device IDs */
2487         *maf_id = chip->read_byte(mtd);
2488         dev_id = chip->read_byte(mtd);
2489
2490         /* Try again to make sure, as some systems the bus-hold or other
2491          * interface concerns can cause random data which looks like a
2492          * possibly credible NAND flash to appear. If the two results do
2493          * not match, ignore the device completely.
2494          */
2495
2496         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2497
2498         /* Read manufacturer and device IDs */
2499
2500         tmp_manf = chip->read_byte(mtd);
2501         tmp_id = chip->read_byte(mtd);
2502
2503         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2504                 printk(KERN_INFO "%s: second ID read did not match "
2505                        "%02x,%02x against %02x,%02x\n", __func__,
2506                        *maf_id, dev_id, tmp_manf, tmp_id);
2507                 return ERR_PTR(-ENODEV);
2508         }
2509
2510         /* Lookup the flash id */
2511         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2512                 if (dev_id == nand_flash_ids[i].id) {
2513                         type =  &nand_flash_ids[i];
2514                         break;
2515                 }
2516         }
2517
2518         if (!type)
2519                 return ERR_PTR(-ENODEV);
2520
2521         if (!mtd->name)
2522                 mtd->name = type->name;
2523
2524         chip->chipsize = (uint64_t)type->chipsize << 20;
2525
2526         /* Newer devices have all the information in additional id bytes */
2527         if (!type->pagesize) {
2528                 int extid;
2529                 /* The 3rd id byte holds MLC / multichip data */
2530                 chip->cellinfo = chip->read_byte(mtd);
2531                 /* The 4th id byte is the important one */
2532                 extid = chip->read_byte(mtd);
2533                 /* Calc pagesize */
2534                 mtd->writesize = 1024 << (extid & 0x3);
2535                 extid >>= 2;
2536                 /* Calc oobsize */
2537                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2538                 extid >>= 2;
2539                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2540                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2541                 extid >>= 2;
2542                 /* Get buswidth information */
2543                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2544
2545         } else {
2546                 /*
2547                  * Old devices have chip data hardcoded in the device id table
2548                  */
2549                 mtd->erasesize = type->erasesize;
2550                 mtd->writesize = type->pagesize;
2551                 mtd->oobsize = mtd->writesize / 32;
2552                 busw = type->options & NAND_BUSWIDTH_16;
2553         }
2554
2555         /* Try to identify manufacturer */
2556         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2557                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2558                         break;
2559         }
2560
2561         /*
2562          * Check, if buswidth is correct. Hardware drivers should set
2563          * chip correct !
2564          */
2565         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2566                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2567                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2568                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2569                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2570                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2571                        busw ? 16 : 8);
2572                 return ERR_PTR(-EINVAL);
2573         }
2574
2575         /* Calculate the address shift from the page size */
2576         chip->page_shift = ffs(mtd->writesize) - 1;
2577         /* Convert chipsize to number of pages per chip -1. */
2578         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2579
2580         chip->bbt_erase_shift = chip->phys_erase_shift =
2581                 ffs(mtd->erasesize) - 1;
2582         if (chip->chipsize & 0xffffffff)
2583                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2584         else
2585                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2586
2587         /* Set the bad block position */
2588         chip->badblockpos = mtd->writesize > 512 ?
2589                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2590
2591         /* Get chip options, preserve non chip based options */
2592         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2593         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2594
2595         /*
2596          * Set chip as a default. Board drivers can override it, if necessary
2597          */
2598         chip->options |= NAND_NO_AUTOINCR;
2599
2600         /* Check if chip is a not a samsung device. Do not clear the
2601          * options for chips which are not having an extended id.
2602          */
2603         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2604                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2605
2606         /* Check for AND chips with 4 page planes */
2607         if (chip->options & NAND_4PAGE_ARRAY)
2608                 chip->erase_cmd = multi_erase_cmd;
2609         else
2610                 chip->erase_cmd = single_erase_cmd;
2611
2612         /* Do not replace user supplied command function ! */
2613         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2614                 chip->cmdfunc = nand_command_lp;
2615
2616         printk(KERN_INFO "NAND device: Manufacturer ID:"
2617                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2618                nand_manuf_ids[maf_idx].name, type->name);
2619
2620         return type;
2621 }
2622
2623 /**
2624  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2625  * @mtd:             MTD device structure
2626  * @maxchips:        Number of chips to scan for
2627  *
2628  * This is the first phase of the normal nand_scan() function. It
2629  * reads the flash ID and sets up MTD fields accordingly.
2630  *
2631  * The mtd->owner field must be set to the module of the caller.
2632  */
2633 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2634 {
2635         int i, busw, nand_maf_id;
2636         struct nand_chip *chip = mtd->priv;
2637         struct nand_flash_dev *type;
2638
2639         /* Get buswidth to select the correct functions */
2640         busw = chip->options & NAND_BUSWIDTH_16;
2641         /* Set the default functions */
2642         nand_set_defaults(chip, busw);
2643
2644         /* Read the flash type */
2645         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2646
2647         if (IS_ERR(type)) {
2648                 printk(KERN_WARNING "No NAND device found!!!\n");
2649                 chip->select_chip(mtd, -1);
2650                 return PTR_ERR(type);
2651         }
2652
2653         /* Check for a chip array */
2654         for (i = 1; i < maxchips; i++) {
2655                 chip->select_chip(mtd, i);
2656                 /* See comment in nand_get_flash_type for reset */
2657                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2658                 /* Send the command for reading device ID */
2659                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2660                 /* Read manufacturer and device IDs */
2661                 if (nand_maf_id != chip->read_byte(mtd) ||
2662                     type->id != chip->read_byte(mtd))
2663                         break;
2664         }
2665         if (i > 1)
2666                 printk(KERN_INFO "%d NAND chips detected\n", i);
2667
2668         /* Store the number of chips and calc total size for mtd */
2669         chip->numchips = i;
2670         mtd->size = i * chip->chipsize;
2671
2672         return 0;
2673 }
2674
2675
2676 /**
2677  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2678  * @mtd:            MTD device structure
2679  *
2680  * This is the second phase of the normal nand_scan() function. It
2681  * fills out all the uninitialized function pointers with the defaults
2682  * and scans for a bad block table if appropriate.
2683  */
2684 int nand_scan_tail(struct mtd_info *mtd)
2685 {
2686         int i;
2687         struct nand_chip *chip = mtd->priv;
2688
2689         if (!(chip->options & NAND_OWN_BUFFERS))
2690                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2691         if (!chip->buffers)
2692                 return -ENOMEM;
2693
2694         /* Set the internal oob buffer location, just after the page data */
2695         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2696
2697         /*
2698          * If no default placement scheme is given, select an appropriate one
2699          */
2700         if (!chip->ecc.layout) {
2701                 switch (mtd->oobsize) {
2702                 case 8:
2703                         chip->ecc.layout = &nand_oob_8;
2704                         break;
2705                 case 16:
2706                         chip->ecc.layout = &nand_oob_16;
2707                         break;
2708                 case 64:
2709                         chip->ecc.layout = &nand_oob_64;
2710                         break;
2711                 case 128:
2712                         chip->ecc.layout = &nand_oob_128;
2713                         break;
2714                 default:
2715                         printk(KERN_WARNING "No oob scheme defined for "
2716                                "oobsize %d\n", mtd->oobsize);
2717                         BUG();
2718                 }
2719         }
2720
2721         if (!chip->write_page)
2722                 chip->write_page = nand_write_page;
2723
2724         /*
2725          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2726          * selected and we have 256 byte pagesize fallback to software ECC
2727          */
2728
2729         switch (chip->ecc.mode) {
2730         case NAND_ECC_HW_OOB_FIRST:
2731                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2732                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2733                      !chip->ecc.hwctl) {
2734                         printk(KERN_WARNING "No ECC functions supplied; "
2735                                "Hardware ECC not possible\n");
2736                         BUG();
2737                 }
2738                 if (!chip->ecc.read_page)
2739                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2740
2741         case NAND_ECC_HW:
2742                 /* Use standard hwecc read page function ? */
2743                 if (!chip->ecc.read_page)
2744                         chip->ecc.read_page = nand_read_page_hwecc;
2745                 if (!chip->ecc.write_page)
2746                         chip->ecc.write_page = nand_write_page_hwecc;
2747                 if (!chip->ecc.read_page_raw)
2748                         chip->ecc.read_page_raw = nand_read_page_raw;
2749                 if (!chip->ecc.write_page_raw)
2750                         chip->ecc.write_page_raw = nand_write_page_raw;
2751                 if (!chip->ecc.read_oob)
2752                         chip->ecc.read_oob = nand_read_oob_std;
2753                 if (!chip->ecc.write_oob)
2754                         chip->ecc.write_oob = nand_write_oob_std;
2755
2756         case NAND_ECC_HW_SYNDROME:
2757                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2758                      !chip->ecc.hwctl) &&
2759                     (!chip->ecc.read_page ||
2760                      chip->ecc.read_page == nand_read_page_hwecc ||
2761                      !chip->ecc.write_page ||
2762                      chip->ecc.write_page == nand_write_page_hwecc)) {
2763                         printk(KERN_WARNING "No ECC functions supplied; "
2764                                "Hardware ECC not possible\n");
2765                         BUG();
2766                 }
2767                 /* Use standard syndrome read/write page function ? */
2768                 if (!chip->ecc.read_page)
2769                         chip->ecc.read_page = nand_read_page_syndrome;
2770                 if (!chip->ecc.write_page)
2771                         chip->ecc.write_page = nand_write_page_syndrome;
2772                 if (!chip->ecc.read_page_raw)
2773                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2774                 if (!chip->ecc.write_page_raw)
2775                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2776                 if (!chip->ecc.read_oob)
2777                         chip->ecc.read_oob = nand_read_oob_syndrome;
2778                 if (!chip->ecc.write_oob)
2779                         chip->ecc.write_oob = nand_write_oob_syndrome;
2780
2781                 if (mtd->writesize >= chip->ecc.size)
2782                         break;
2783                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2784                        "%d byte page size, fallback to SW ECC\n",
2785                        chip->ecc.size, mtd->writesize);
2786                 chip->ecc.mode = NAND_ECC_SOFT;
2787
2788         case NAND_ECC_SOFT:
2789                 chip->ecc.calculate = nand_calculate_ecc;
2790                 chip->ecc.correct = nand_correct_data;
2791                 chip->ecc.read_page = nand_read_page_swecc;
2792                 chip->ecc.read_subpage = nand_read_subpage;
2793                 chip->ecc.write_page = nand_write_page_swecc;
2794                 chip->ecc.read_page_raw = nand_read_page_raw;
2795                 chip->ecc.write_page_raw = nand_write_page_raw;
2796                 chip->ecc.read_oob = nand_read_oob_std;
2797                 chip->ecc.write_oob = nand_write_oob_std;
2798                 if (!chip->ecc.size)
2799                         chip->ecc.size = 256;
2800                 chip->ecc.bytes = 3;
2801                 break;
2802
2803         case NAND_ECC_NONE:
2804                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2805                        "This is not recommended !!\n");
2806                 chip->ecc.read_page = nand_read_page_raw;
2807                 chip->ecc.write_page = nand_write_page_raw;
2808                 chip->ecc.read_oob = nand_read_oob_std;
2809                 chip->ecc.read_page_raw = nand_read_page_raw;
2810                 chip->ecc.write_page_raw = nand_write_page_raw;
2811                 chip->ecc.write_oob = nand_write_oob_std;
2812                 chip->ecc.size = mtd->writesize;
2813                 chip->ecc.bytes = 0;
2814                 break;
2815
2816         default:
2817                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2818                        chip->ecc.mode);
2819                 BUG();
2820         }
2821
2822         /*
2823          * The number of bytes available for a client to place data into
2824          * the out of band area
2825          */
2826         chip->ecc.layout->oobavail = 0;
2827         for (i = 0; chip->ecc.layout->oobfree[i].length
2828                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2829                 chip->ecc.layout->oobavail +=
2830                         chip->ecc.layout->oobfree[i].length;
2831         mtd->oobavail = chip->ecc.layout->oobavail;
2832
2833         /*
2834          * Set the number of read / write steps for one page depending on ECC
2835          * mode
2836          */
2837         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2838         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2839                 printk(KERN_WARNING "Invalid ecc parameters\n");
2840                 BUG();
2841         }
2842         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2843
2844         /*
2845          * Allow subpage writes up to ecc.steps. Not possible for MLC
2846          * FLASH.
2847          */
2848         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2849             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2850                 switch(chip->ecc.steps) {
2851                 case 2:
2852                         mtd->subpage_sft = 1;
2853                         break;
2854                 case 4:
2855                 case 8:
2856                 case 16:
2857                         mtd->subpage_sft = 2;
2858                         break;
2859                 }
2860         }
2861         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2862
2863         /* Initialize state */
2864         chip->state = FL_READY;
2865
2866         /* De-select the device */
2867         chip->select_chip(mtd, -1);
2868
2869         /* Invalidate the pagebuffer reference */
2870         chip->pagebuf = -1;
2871
2872         /* Fill in remaining MTD driver data */
2873         mtd->type = MTD_NANDFLASH;
2874         mtd->flags = MTD_CAP_NANDFLASH;
2875         mtd->erase = nand_erase;
2876         mtd->point = NULL;
2877         mtd->unpoint = NULL;
2878         mtd->read = nand_read;
2879         mtd->write = nand_write;
2880         mtd->read_oob = nand_read_oob;
2881         mtd->write_oob = nand_write_oob;
2882         mtd->sync = nand_sync;
2883         mtd->lock = NULL;
2884         mtd->unlock = NULL;
2885         mtd->suspend = nand_suspend;
2886         mtd->resume = nand_resume;
2887         mtd->block_isbad = nand_block_isbad;
2888         mtd->block_markbad = nand_block_markbad;
2889
2890         /* propagate ecc.layout to mtd_info */
2891         mtd->ecclayout = chip->ecc.layout;
2892
2893         /* Check, if we should skip the bad block table scan */
2894         if (chip->options & NAND_SKIP_BBTSCAN)
2895                 return 0;
2896
2897         /* Build bad block table */
2898         return chip->scan_bbt(mtd);
2899 }
2900
2901 /* is_module_text_address() isn't exported, and it's mostly a pointless
2902    test if this is a module _anyway_ -- they'd have to try _really_ hard
2903    to call us from in-kernel code if the core NAND support is modular. */
2904 #ifdef MODULE
2905 #define caller_is_module() (1)
2906 #else
2907 #define caller_is_module() \
2908         is_module_text_address((unsigned long)__builtin_return_address(0))
2909 #endif
2910
2911 /**
2912  * nand_scan - [NAND Interface] Scan for the NAND device
2913  * @mtd:        MTD device structure
2914  * @maxchips:   Number of chips to scan for
2915  *
2916  * This fills out all the uninitialized function pointers
2917  * with the defaults.
2918  * The flash ID is read and the mtd/chip structures are
2919  * filled with the appropriate values.
2920  * The mtd->owner field must be set to the module of the caller
2921  *
2922  */
2923 int nand_scan(struct mtd_info *mtd, int maxchips)
2924 {
2925         int ret;
2926
2927         /* Many callers got this wrong, so check for it for a while... */
2928         if (!mtd->owner && caller_is_module()) {
2929                 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
2930                                 __func__);
2931                 BUG();
2932         }
2933
2934         ret = nand_scan_ident(mtd, maxchips);
2935         if (!ret)
2936                 ret = nand_scan_tail(mtd);
2937         return ret;
2938 }
2939
2940 /**
2941  * nand_release - [NAND Interface] Free resources held by the NAND device
2942  * @mtd:        MTD device structure
2943 */
2944 void nand_release(struct mtd_info *mtd)
2945 {
2946         struct nand_chip *chip = mtd->priv;
2947
2948 #ifdef CONFIG_MTD_PARTITIONS
2949         /* Deregister partitions */
2950         del_mtd_partitions(mtd);
2951 #endif
2952         /* Deregister the device */
2953         del_mtd_device(mtd);
2954
2955         /* Free bad block table memory */
2956         kfree(chip->bbt);
2957         if (!(chip->options & NAND_OWN_BUFFERS))
2958                 kfree(chip->buffers);
2959 }
2960
2961 EXPORT_SYMBOL_GPL(nand_scan);
2962 EXPORT_SYMBOL_GPL(nand_scan_ident);
2963 EXPORT_SYMBOL_GPL(nand_scan_tail);
2964 EXPORT_SYMBOL_GPL(nand_release);
2965
2966 static int __init nand_base_init(void)
2967 {
2968         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2969         return 0;
2970 }
2971
2972 static void __exit nand_base_exit(void)
2973 {
2974         led_trigger_unregister_simple(nand_led_trigger);
2975 }
2976
2977 module_init(nand_base_init);
2978 module_exit(nand_base_exit);
2979
2980 MODULE_LICENSE("GPL");
2981 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2982 MODULE_DESCRIPTION("Generic NAND flash driver code");