drm/vmwgfx: Don't send bad flags to the host
[linux-2.6.git] / drivers / mtd / nand / atmel_nand.c
1 /*
2  *  Copyright (C) 2003 Rick Bronson
3  *
4  *  Derived from drivers/mtd/nand/autcpu12.c
5  *       Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
6  *
7  *  Derived from drivers/mtd/spia.c
8  *       Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
9  *
10  *
11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
13  *
14  *     Derived from Das U-Boot source code
15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16  *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17  *
18  *
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License version 2 as
21  * published by the Free Software Foundation.
22  *
23  */
24
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/mtd/partitions.h>
32
33 #include <linux/gpio.h>
34 #include <linux/io.h>
35
36 #include <mach/board.h>
37 #include <mach/cpu.h>
38
39 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
40 #define hard_ecc        1
41 #else
42 #define hard_ecc        0
43 #endif
44
45 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
46 #define no_ecc          1
47 #else
48 #define no_ecc          0
49 #endif
50
51 static int on_flash_bbt = 0;
52 module_param(on_flash_bbt, int, 0);
53
54 /* Register access macros */
55 #define ecc_readl(add, reg)                             \
56         __raw_readl(add + ATMEL_ECC_##reg)
57 #define ecc_writel(add, reg, value)                     \
58         __raw_writel((value), add + ATMEL_ECC_##reg)
59
60 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
61
62 /* oob layout for large page size
63  * bad block info is on bytes 0 and 1
64  * the bytes have to be consecutives to avoid
65  * several NAND_CMD_RNDOUT during read
66  */
67 static struct nand_ecclayout atmel_oobinfo_large = {
68         .eccbytes = 4,
69         .eccpos = {60, 61, 62, 63},
70         .oobfree = {
71                 {2, 58}
72         },
73 };
74
75 /* oob layout for small page size
76  * bad block info is on bytes 4 and 5
77  * the bytes have to be consecutives to avoid
78  * several NAND_CMD_RNDOUT during read
79  */
80 static struct nand_ecclayout atmel_oobinfo_small = {
81         .eccbytes = 4,
82         .eccpos = {0, 1, 2, 3},
83         .oobfree = {
84                 {6, 10}
85         },
86 };
87
88 struct atmel_nand_host {
89         struct nand_chip        nand_chip;
90         struct mtd_info         mtd;
91         void __iomem            *io_base;
92         struct atmel_nand_data  *board;
93         struct device           *dev;
94         void __iomem            *ecc;
95 };
96
97 /*
98  * Enable NAND.
99  */
100 static void atmel_nand_enable(struct atmel_nand_host *host)
101 {
102         if (host->board->enable_pin)
103                 gpio_set_value(host->board->enable_pin, 0);
104 }
105
106 /*
107  * Disable NAND.
108  */
109 static void atmel_nand_disable(struct atmel_nand_host *host)
110 {
111         if (host->board->enable_pin)
112                 gpio_set_value(host->board->enable_pin, 1);
113 }
114
115 /*
116  * Hardware specific access to control-lines
117  */
118 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
119 {
120         struct nand_chip *nand_chip = mtd->priv;
121         struct atmel_nand_host *host = nand_chip->priv;
122
123         if (ctrl & NAND_CTRL_CHANGE) {
124                 if (ctrl & NAND_NCE)
125                         atmel_nand_enable(host);
126                 else
127                         atmel_nand_disable(host);
128         }
129         if (cmd == NAND_CMD_NONE)
130                 return;
131
132         if (ctrl & NAND_CLE)
133                 writeb(cmd, host->io_base + (1 << host->board->cle));
134         else
135                 writeb(cmd, host->io_base + (1 << host->board->ale));
136 }
137
138 /*
139  * Read the Device Ready pin.
140  */
141 static int atmel_nand_device_ready(struct mtd_info *mtd)
142 {
143         struct nand_chip *nand_chip = mtd->priv;
144         struct atmel_nand_host *host = nand_chip->priv;
145
146         return gpio_get_value(host->board->rdy_pin) ^
147                 !!host->board->rdy_pin_active_low;
148 }
149
150 /*
151  * Minimal-overhead PIO for data access.
152  */
153 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
154 {
155         struct nand_chip        *nand_chip = mtd->priv;
156
157         __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
158 }
159
160 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
161 {
162         struct nand_chip        *nand_chip = mtd->priv;
163
164         __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
165 }
166
167 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
168 {
169         struct nand_chip        *nand_chip = mtd->priv;
170
171         __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
172 }
173
174 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
175 {
176         struct nand_chip        *nand_chip = mtd->priv;
177
178         __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
179 }
180
181 /*
182  * Calculate HW ECC
183  *
184  * function called after a write
185  *
186  * mtd:        MTD block structure
187  * dat:        raw data (unused)
188  * ecc_code:   buffer for ECC
189  */
190 static int atmel_nand_calculate(struct mtd_info *mtd,
191                 const u_char *dat, unsigned char *ecc_code)
192 {
193         struct nand_chip *nand_chip = mtd->priv;
194         struct atmel_nand_host *host = nand_chip->priv;
195         uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
196         unsigned int ecc_value;
197
198         /* get the first 2 ECC bytes */
199         ecc_value = ecc_readl(host->ecc, PR);
200
201         ecc_code[0] = ecc_value & 0xFF;
202         ecc_code[1] = (ecc_value >> 8) & 0xFF;
203
204         /* get the last 2 ECC bytes */
205         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
206
207         ecc_code[2] = ecc_value & 0xFF;
208         ecc_code[3] = (ecc_value >> 8) & 0xFF;
209
210         return 0;
211 }
212
213 /*
214  * HW ECC read page function
215  *
216  * mtd:        mtd info structure
217  * chip:       nand chip info structure
218  * buf:        buffer to store read data
219  */
220 static int atmel_nand_read_page(struct mtd_info *mtd,
221                 struct nand_chip *chip, uint8_t *buf, int page)
222 {
223         int eccsize = chip->ecc.size;
224         int eccbytes = chip->ecc.bytes;
225         uint32_t *eccpos = chip->ecc.layout->eccpos;
226         uint8_t *p = buf;
227         uint8_t *oob = chip->oob_poi;
228         uint8_t *ecc_pos;
229         int stat;
230
231         /*
232          * Errata: ALE is incorrectly wired up to the ECC controller
233          * on the AP7000, so it will include the address cycles in the
234          * ECC calculation.
235          *
236          * Workaround: Reset the parity registers before reading the
237          * actual data.
238          */
239         if (cpu_is_at32ap7000()) {
240                 struct atmel_nand_host *host = chip->priv;
241                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
242         }
243
244         /* read the page */
245         chip->read_buf(mtd, p, eccsize);
246
247         /* move to ECC position if needed */
248         if (eccpos[0] != 0) {
249                 /* This only works on large pages
250                  * because the ECC controller waits for
251                  * NAND_CMD_RNDOUTSTART after the
252                  * NAND_CMD_RNDOUT.
253                  * anyway, for small pages, the eccpos[0] == 0
254                  */
255                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
256                                 mtd->writesize + eccpos[0], -1);
257         }
258
259         /* the ECC controller needs to read the ECC just after the data */
260         ecc_pos = oob + eccpos[0];
261         chip->read_buf(mtd, ecc_pos, eccbytes);
262
263         /* check if there's an error */
264         stat = chip->ecc.correct(mtd, p, oob, NULL);
265
266         if (stat < 0)
267                 mtd->ecc_stats.failed++;
268         else
269                 mtd->ecc_stats.corrected += stat;
270
271         /* get back to oob start (end of page) */
272         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
273
274         /* read the oob */
275         chip->read_buf(mtd, oob, mtd->oobsize);
276
277         return 0;
278 }
279
280 /*
281  * HW ECC Correction
282  *
283  * function called after a read
284  *
285  * mtd:        MTD block structure
286  * dat:        raw data read from the chip
287  * read_ecc:   ECC from the chip (unused)
288  * isnull:     unused
289  *
290  * Detect and correct a 1 bit error for a page
291  */
292 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
293                 u_char *read_ecc, u_char *isnull)
294 {
295         struct nand_chip *nand_chip = mtd->priv;
296         struct atmel_nand_host *host = nand_chip->priv;
297         unsigned int ecc_status;
298         unsigned int ecc_word, ecc_bit;
299
300         /* get the status from the Status Register */
301         ecc_status = ecc_readl(host->ecc, SR);
302
303         /* if there's no error */
304         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
305                 return 0;
306
307         /* get error bit offset (4 bits) */
308         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
309         /* get word address (12 bits) */
310         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
311         ecc_word >>= 4;
312
313         /* if there are multiple errors */
314         if (ecc_status & ATMEL_ECC_MULERR) {
315                 /* check if it is a freshly erased block
316                  * (filled with 0xff) */
317                 if ((ecc_bit == ATMEL_ECC_BITADDR)
318                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
319                         /* the block has just been erased, return OK */
320                         return 0;
321                 }
322                 /* it doesn't seems to be a freshly
323                  * erased block.
324                  * We can't correct so many errors */
325                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
326                                 " Unable to correct.\n");
327                 return -EIO;
328         }
329
330         /* if there's a single bit error : we can correct it */
331         if (ecc_status & ATMEL_ECC_ECCERR) {
332                 /* there's nothing much to do here.
333                  * the bit error is on the ECC itself.
334                  */
335                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
336                                 " Nothing to correct\n");
337                 return 0;
338         }
339
340         dev_dbg(host->dev, "atmel_nand : one bit error on data."
341                         " (word offset in the page :"
342                         " 0x%x bit offset : 0x%x)\n",
343                         ecc_word, ecc_bit);
344         /* correct the error */
345         if (nand_chip->options & NAND_BUSWIDTH_16) {
346                 /* 16 bits words */
347                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
348         } else {
349                 /* 8 bits words */
350                 dat[ecc_word] ^= (1 << ecc_bit);
351         }
352         dev_dbg(host->dev, "atmel_nand : error corrected\n");
353         return 1;
354 }
355
356 /*
357  * Enable HW ECC : unused on most chips
358  */
359 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
360 {
361         if (cpu_is_at32ap7000()) {
362                 struct nand_chip *nand_chip = mtd->priv;
363                 struct atmel_nand_host *host = nand_chip->priv;
364                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
365         }
366 }
367
368 #ifdef CONFIG_MTD_PARTITIONS
369 static const char *part_probes[] = { "cmdlinepart", NULL };
370 #endif
371
372 /*
373  * Probe for the NAND device.
374  */
375 static int __init atmel_nand_probe(struct platform_device *pdev)
376 {
377         struct atmel_nand_host *host;
378         struct mtd_info *mtd;
379         struct nand_chip *nand_chip;
380         struct resource *regs;
381         struct resource *mem;
382         int res;
383
384 #ifdef CONFIG_MTD_PARTITIONS
385         struct mtd_partition *partitions = NULL;
386         int num_partitions = 0;
387 #endif
388
389         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
390         if (!mem) {
391                 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
392                 return -ENXIO;
393         }
394
395         /* Allocate memory for the device structure (and zero it) */
396         host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
397         if (!host) {
398                 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
399                 return -ENOMEM;
400         }
401
402         host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
403         if (host->io_base == NULL) {
404                 printk(KERN_ERR "atmel_nand: ioremap failed\n");
405                 res = -EIO;
406                 goto err_nand_ioremap;
407         }
408
409         mtd = &host->mtd;
410         nand_chip = &host->nand_chip;
411         host->board = pdev->dev.platform_data;
412         host->dev = &pdev->dev;
413
414         nand_chip->priv = host;         /* link the private data structures */
415         mtd->priv = nand_chip;
416         mtd->owner = THIS_MODULE;
417
418         /* Set address of NAND IO lines */
419         nand_chip->IO_ADDR_R = host->io_base;
420         nand_chip->IO_ADDR_W = host->io_base;
421         nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
422
423         if (host->board->rdy_pin)
424                 nand_chip->dev_ready = atmel_nand_device_ready;
425
426         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
427         if (!regs && hard_ecc) {
428                 printk(KERN_ERR "atmel_nand: can't get I/O resource "
429                                 "regs\nFalling back on software ECC\n");
430         }
431
432         nand_chip->ecc.mode = NAND_ECC_SOFT;    /* enable ECC */
433         if (no_ecc)
434                 nand_chip->ecc.mode = NAND_ECC_NONE;
435         if (hard_ecc && regs) {
436                 host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
437                 if (host->ecc == NULL) {
438                         printk(KERN_ERR "atmel_nand: ioremap failed\n");
439                         res = -EIO;
440                         goto err_ecc_ioremap;
441                 }
442                 nand_chip->ecc.mode = NAND_ECC_HW;
443                 nand_chip->ecc.calculate = atmel_nand_calculate;
444                 nand_chip->ecc.correct = atmel_nand_correct;
445                 nand_chip->ecc.hwctl = atmel_nand_hwctl;
446                 nand_chip->ecc.read_page = atmel_nand_read_page;
447                 nand_chip->ecc.bytes = 4;
448         }
449
450         nand_chip->chip_delay = 20;             /* 20us command delay time */
451
452         if (host->board->bus_width_16) {        /* 16-bit bus width */
453                 nand_chip->options |= NAND_BUSWIDTH_16;
454                 nand_chip->read_buf = atmel_read_buf16;
455                 nand_chip->write_buf = atmel_write_buf16;
456         } else {
457                 nand_chip->read_buf = atmel_read_buf;
458                 nand_chip->write_buf = atmel_write_buf;
459         }
460
461         platform_set_drvdata(pdev, host);
462         atmel_nand_enable(host);
463
464         if (host->board->det_pin) {
465                 if (gpio_get_value(host->board->det_pin)) {
466                         printk(KERN_INFO "No SmartMedia card inserted.\n");
467                         res = ENXIO;
468                         goto err_no_card;
469                 }
470         }
471
472         if (on_flash_bbt) {
473                 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
474                 nand_chip->options |= NAND_USE_FLASH_BBT;
475         }
476
477         /* first scan to find the device and get the page size */
478         if (nand_scan_ident(mtd, 1)) {
479                 res = -ENXIO;
480                 goto err_scan_ident;
481         }
482
483         if (nand_chip->ecc.mode == NAND_ECC_HW) {
484                 /* ECC is calculated for the whole page (1 step) */
485                 nand_chip->ecc.size = mtd->writesize;
486
487                 /* set ECC page size and oob layout */
488                 switch (mtd->writesize) {
489                 case 512:
490                         nand_chip->ecc.layout = &atmel_oobinfo_small;
491                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
492                         break;
493                 case 1024:
494                         nand_chip->ecc.layout = &atmel_oobinfo_large;
495                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
496                         break;
497                 case 2048:
498                         nand_chip->ecc.layout = &atmel_oobinfo_large;
499                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
500                         break;
501                 case 4096:
502                         nand_chip->ecc.layout = &atmel_oobinfo_large;
503                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
504                         break;
505                 default:
506                         /* page size not handled by HW ECC */
507                         /* switching back to soft ECC */
508                         nand_chip->ecc.mode = NAND_ECC_SOFT;
509                         nand_chip->ecc.calculate = NULL;
510                         nand_chip->ecc.correct = NULL;
511                         nand_chip->ecc.hwctl = NULL;
512                         nand_chip->ecc.read_page = NULL;
513                         nand_chip->ecc.postpad = 0;
514                         nand_chip->ecc.prepad = 0;
515                         nand_chip->ecc.bytes = 0;
516                         break;
517                 }
518         }
519
520         /* second phase scan */
521         if (nand_scan_tail(mtd)) {
522                 res = -ENXIO;
523                 goto err_scan_tail;
524         }
525
526 #ifdef CONFIG_MTD_PARTITIONS
527 #ifdef CONFIG_MTD_CMDLINE_PARTS
528         mtd->name = "atmel_nand";
529         num_partitions = parse_mtd_partitions(mtd, part_probes,
530                                               &partitions, 0);
531 #endif
532         if (num_partitions <= 0 && host->board->partition_info)
533                 partitions = host->board->partition_info(mtd->size,
534                                                          &num_partitions);
535
536         if ((!partitions) || (num_partitions == 0)) {
537                 printk(KERN_ERR "atmel_nand: No partitions defined, or unsupported device.\n");
538                 res = ENXIO;
539                 goto err_no_partitions;
540         }
541
542         res = add_mtd_partitions(mtd, partitions, num_partitions);
543 #else
544         res = add_mtd_device(mtd);
545 #endif
546
547         if (!res)
548                 return res;
549
550 #ifdef CONFIG_MTD_PARTITIONS
551 err_no_partitions:
552 #endif
553         nand_release(mtd);
554 err_scan_tail:
555 err_scan_ident:
556 err_no_card:
557         atmel_nand_disable(host);
558         platform_set_drvdata(pdev, NULL);
559         if (host->ecc)
560                 iounmap(host->ecc);
561 err_ecc_ioremap:
562         iounmap(host->io_base);
563 err_nand_ioremap:
564         kfree(host);
565         return res;
566 }
567
568 /*
569  * Remove a NAND device.
570  */
571 static int __exit atmel_nand_remove(struct platform_device *pdev)
572 {
573         struct atmel_nand_host *host = platform_get_drvdata(pdev);
574         struct mtd_info *mtd = &host->mtd;
575
576         nand_release(mtd);
577
578         atmel_nand_disable(host);
579
580         if (host->ecc)
581                 iounmap(host->ecc);
582         iounmap(host->io_base);
583         kfree(host);
584
585         return 0;
586 }
587
588 static struct platform_driver atmel_nand_driver = {
589         .remove         = __exit_p(atmel_nand_remove),
590         .driver         = {
591                 .name   = "atmel_nand",
592                 .owner  = THIS_MODULE,
593         },
594 };
595
596 static int __init atmel_nand_init(void)
597 {
598         return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
599 }
600
601
602 static void __exit atmel_nand_exit(void)
603 {
604         platform_driver_unregister(&atmel_nand_driver);
605 }
606
607
608 module_init(atmel_nand_init);
609 module_exit(atmel_nand_exit);
610
611 MODULE_LICENSE("GPL");
612 MODULE_AUTHOR("Rick Bronson");
613 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
614 MODULE_ALIAS("platform:atmel_nand");