mmc: sdhci: add quirk for lack of 1.8v support
[linux-2.6.git] / drivers / mmc / host / sdhci.c
1 /*
2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3  *
4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or (at
9  * your option) any later version.
10  *
11  * Thanks to the following companies for their support:
12  *
13  *     - JMicron (hardware and technical support)
14  */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <linux/leds.h>
25
26 #include <linux/mmc/mmc.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/card.h>
29
30 #include "sdhci.h"
31
32 #define DRIVER_NAME "sdhci"
33
34 #define DBG(f, x...) \
35         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
36
37 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
38         defined(CONFIG_MMC_SDHCI_MODULE))
39 #define SDHCI_USE_LEDS_CLASS
40 #endif
41
42 #define MAX_TUNING_LOOP 40
43
44 static unsigned int debug_quirks = 0;
45
46 static void sdhci_finish_data(struct sdhci_host *);
47
48 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
49 static void sdhci_finish_command(struct sdhci_host *);
50 static int sdhci_execute_tuning(struct mmc_host *mmc);
51 static void sdhci_tuning_timer(unsigned long data);
52
53 static void sdhci_dumpregs(struct sdhci_host *host)
54 {
55         printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
56                 mmc_hostname(host->mmc));
57
58         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
59                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60                 sdhci_readw(host, SDHCI_HOST_VERSION));
61         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
62                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
64         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
65                 sdhci_readl(host, SDHCI_ARGUMENT),
66                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
67         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
68                 sdhci_readl(host, SDHCI_PRESENT_STATE),
69                 sdhci_readb(host, SDHCI_HOST_CONTROL));
70         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
71                 sdhci_readb(host, SDHCI_POWER_CONTROL),
72                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
73         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
74                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
76         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
77                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78                 sdhci_readl(host, SDHCI_INT_STATUS));
79         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
80                 sdhci_readl(host, SDHCI_INT_ENABLE),
81                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
82         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
83                 sdhci_readw(host, SDHCI_ACMD12_ERR),
84                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
85         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
86                 sdhci_readl(host, SDHCI_CAPABILITIES),
87                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
88         printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
89                 sdhci_readw(host, SDHCI_COMMAND),
90                 sdhci_readl(host, SDHCI_MAX_CURRENT));
91         printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
92                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
93
94         if (host->flags & SDHCI_USE_ADMA)
95                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
96                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
97                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
98
99         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
100 }
101
102 /*****************************************************************************\
103  *                                                                           *
104  * Low level functions                                                       *
105  *                                                                           *
106 \*****************************************************************************/
107
108 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
109 {
110         u32 ier;
111
112         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
113         ier &= ~clear;
114         ier |= set;
115         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
116         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
117 }
118
119 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
120 {
121         sdhci_clear_set_irqs(host, 0, irqs);
122 }
123
124 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
125 {
126         sdhci_clear_set_irqs(host, irqs, 0);
127 }
128
129 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
130 {
131         u32 present, irqs;
132
133         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
134                 return;
135
136         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
137                               SDHCI_CARD_PRESENT;
138         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
139
140         if (enable)
141                 sdhci_unmask_irqs(host, irqs);
142         else
143                 sdhci_mask_irqs(host, irqs);
144 }
145
146 static void sdhci_enable_card_detection(struct sdhci_host *host)
147 {
148         sdhci_set_card_detection(host, true);
149 }
150
151 static void sdhci_disable_card_detection(struct sdhci_host *host)
152 {
153         sdhci_set_card_detection(host, false);
154 }
155
156 static void sdhci_reset(struct sdhci_host *host, u8 mask)
157 {
158         unsigned long timeout;
159         u32 uninitialized_var(ier);
160
161         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
162                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
163                         SDHCI_CARD_PRESENT))
164                         return;
165         }
166
167         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
168                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
169
170         if (host->ops->platform_reset_enter)
171                 host->ops->platform_reset_enter(host, mask);
172
173         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
174
175         if (mask & SDHCI_RESET_ALL)
176                 host->clock = 0;
177
178         /* Wait max 100 ms */
179         timeout = 100;
180
181         /* hw clears the bit when it's done */
182         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
183                 if (timeout == 0) {
184                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
185                                 mmc_hostname(host->mmc), (int)mask);
186                         sdhci_dumpregs(host);
187                         return;
188                 }
189                 timeout--;
190                 mdelay(1);
191         }
192
193         if (host->ops->platform_reset_exit)
194                 host->ops->platform_reset_exit(host, mask);
195
196         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
197                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
198 }
199
200 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
201
202 static void sdhci_init(struct sdhci_host *host, int soft)
203 {
204         if (soft)
205                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
206         else
207                 sdhci_reset(host, SDHCI_RESET_ALL);
208
209         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
210                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
211                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
212                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
213                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
214
215         if (soft) {
216                 /* force clock reconfiguration */
217                 host->clock = 0;
218                 sdhci_set_ios(host->mmc, &host->mmc->ios);
219         }
220 }
221
222 static void sdhci_reinit(struct sdhci_host *host)
223 {
224         sdhci_init(host, 0);
225         sdhci_enable_card_detection(host);
226 }
227
228 static void sdhci_activate_led(struct sdhci_host *host)
229 {
230         u8 ctrl;
231
232         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
233         ctrl |= SDHCI_CTRL_LED;
234         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
235 }
236
237 static void sdhci_deactivate_led(struct sdhci_host *host)
238 {
239         u8 ctrl;
240
241         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
242         ctrl &= ~SDHCI_CTRL_LED;
243         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
244 }
245
246 #ifdef SDHCI_USE_LEDS_CLASS
247 static void sdhci_led_control(struct led_classdev *led,
248         enum led_brightness brightness)
249 {
250         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
251         unsigned long flags;
252
253         spin_lock_irqsave(&host->lock, flags);
254
255         if (brightness == LED_OFF)
256                 sdhci_deactivate_led(host);
257         else
258                 sdhci_activate_led(host);
259
260         spin_unlock_irqrestore(&host->lock, flags);
261 }
262 #endif
263
264 /*****************************************************************************\
265  *                                                                           *
266  * Core functions                                                            *
267  *                                                                           *
268 \*****************************************************************************/
269
270 static void sdhci_read_block_pio(struct sdhci_host *host)
271 {
272         unsigned long flags;
273         size_t blksize, len, chunk;
274         u32 uninitialized_var(scratch);
275         u8 *buf;
276
277         DBG("PIO reading\n");
278
279         blksize = host->data->blksz;
280         chunk = 0;
281
282         local_irq_save(flags);
283
284         while (blksize) {
285                 if (!sg_miter_next(&host->sg_miter))
286                         BUG();
287
288                 len = min(host->sg_miter.length, blksize);
289
290                 blksize -= len;
291                 host->sg_miter.consumed = len;
292
293                 buf = host->sg_miter.addr;
294
295                 while (len) {
296                         if (chunk == 0) {
297                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
298                                 chunk = 4;
299                         }
300
301                         *buf = scratch & 0xFF;
302
303                         buf++;
304                         scratch >>= 8;
305                         chunk--;
306                         len--;
307                 }
308         }
309
310         sg_miter_stop(&host->sg_miter);
311
312         local_irq_restore(flags);
313 }
314
315 static void sdhci_write_block_pio(struct sdhci_host *host)
316 {
317         unsigned long flags;
318         size_t blksize, len, chunk;
319         u32 scratch;
320         u8 *buf;
321
322         DBG("PIO writing\n");
323
324         blksize = host->data->blksz;
325         chunk = 0;
326         scratch = 0;
327
328         local_irq_save(flags);
329
330         while (blksize) {
331                 if (!sg_miter_next(&host->sg_miter))
332                         BUG();
333
334                 len = min(host->sg_miter.length, blksize);
335
336                 blksize -= len;
337                 host->sg_miter.consumed = len;
338
339                 buf = host->sg_miter.addr;
340
341                 while (len) {
342                         scratch |= (u32)*buf << (chunk * 8);
343
344                         buf++;
345                         chunk++;
346                         len--;
347
348                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
349                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
350                                 chunk = 0;
351                                 scratch = 0;
352                         }
353                 }
354         }
355
356         sg_miter_stop(&host->sg_miter);
357
358         local_irq_restore(flags);
359 }
360
361 static void sdhci_transfer_pio(struct sdhci_host *host)
362 {
363         u32 mask;
364
365         BUG_ON(!host->data);
366
367         if (host->blocks == 0)
368                 return;
369
370         if (host->data->flags & MMC_DATA_READ)
371                 mask = SDHCI_DATA_AVAILABLE;
372         else
373                 mask = SDHCI_SPACE_AVAILABLE;
374
375         /*
376          * Some controllers (JMicron JMB38x) mess up the buffer bits
377          * for transfers < 4 bytes. As long as it is just one block,
378          * we can ignore the bits.
379          */
380         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
381                 (host->data->blocks == 1))
382                 mask = ~0;
383
384         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
385                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
386                         udelay(100);
387
388                 if (host->data->flags & MMC_DATA_READ)
389                         sdhci_read_block_pio(host);
390                 else
391                         sdhci_write_block_pio(host);
392
393                 host->blocks--;
394                 if (host->blocks == 0)
395                         break;
396         }
397
398         DBG("PIO transfer complete.\n");
399 }
400
401 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
402 {
403         local_irq_save(*flags);
404         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
405 }
406
407 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
408 {
409         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
410         local_irq_restore(*flags);
411 }
412
413 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
414 {
415         __le32 *dataddr = (__le32 __force *)(desc + 4);
416         __le16 *cmdlen = (__le16 __force *)desc;
417
418         /* SDHCI specification says ADMA descriptors should be 4 byte
419          * aligned, so using 16 or 32bit operations should be safe. */
420
421         cmdlen[0] = cpu_to_le16(cmd);
422         cmdlen[1] = cpu_to_le16(len);
423
424         dataddr[0] = cpu_to_le32(addr);
425 }
426
427 static int sdhci_adma_table_pre(struct sdhci_host *host,
428         struct mmc_data *data)
429 {
430         int direction;
431
432         u8 *desc;
433         u8 *align;
434         dma_addr_t addr;
435         dma_addr_t align_addr;
436         int len, offset;
437
438         struct scatterlist *sg;
439         int i;
440         char *buffer;
441         unsigned long flags;
442
443         /*
444          * The spec does not specify endianness of descriptor table.
445          * We currently guess that it is LE.
446          */
447
448         if (data->flags & MMC_DATA_READ)
449                 direction = DMA_FROM_DEVICE;
450         else
451                 direction = DMA_TO_DEVICE;
452
453         /*
454          * The ADMA descriptor table is mapped further down as we
455          * need to fill it with data first.
456          */
457
458         host->align_addr = dma_map_single(mmc_dev(host->mmc),
459                 host->align_buffer, 128 * 4, direction);
460         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
461                 goto fail;
462         BUG_ON(host->align_addr & 0x3);
463
464         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
465                 data->sg, data->sg_len, direction);
466         if (host->sg_count == 0)
467                 goto unmap_align;
468
469         desc = host->adma_desc;
470         align = host->align_buffer;
471
472         align_addr = host->align_addr;
473
474         for_each_sg(data->sg, sg, host->sg_count, i) {
475                 addr = sg_dma_address(sg);
476                 len = sg_dma_len(sg);
477
478                 /*
479                  * The SDHCI specification states that ADMA
480                  * addresses must be 32-bit aligned. If they
481                  * aren't, then we use a bounce buffer for
482                  * the (up to three) bytes that screw up the
483                  * alignment.
484                  */
485                 offset = (4 - (addr & 0x3)) & 0x3;
486                 if (offset) {
487                         if (data->flags & MMC_DATA_WRITE) {
488                                 buffer = sdhci_kmap_atomic(sg, &flags);
489                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
490                                 memcpy(align, buffer, offset);
491                                 sdhci_kunmap_atomic(buffer, &flags);
492                         }
493
494                         /* tran, valid */
495                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
496
497                         BUG_ON(offset > 65536);
498
499                         align += 4;
500                         align_addr += 4;
501
502                         desc += 8;
503
504                         addr += offset;
505                         len -= offset;
506                 }
507
508                 BUG_ON(len > 65536);
509
510                 /* tran, valid */
511                 sdhci_set_adma_desc(desc, addr, len, 0x21);
512                 desc += 8;
513
514                 /*
515                  * If this triggers then we have a calculation bug
516                  * somewhere. :/
517                  */
518                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
519         }
520
521         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
522                 /*
523                 * Mark the last descriptor as the terminating descriptor
524                 */
525                 if (desc != host->adma_desc) {
526                         desc -= 8;
527                         desc[0] |= 0x2; /* end */
528                 }
529         } else {
530                 /*
531                 * Add a terminating entry.
532                 */
533
534                 /* nop, end, valid */
535                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
536         }
537
538         /*
539          * Resync align buffer as we might have changed it.
540          */
541         if (data->flags & MMC_DATA_WRITE) {
542                 dma_sync_single_for_device(mmc_dev(host->mmc),
543                         host->align_addr, 128 * 4, direction);
544         }
545
546         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
547                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
548         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
549                 goto unmap_entries;
550         BUG_ON(host->adma_addr & 0x3);
551
552         return 0;
553
554 unmap_entries:
555         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
556                 data->sg_len, direction);
557 unmap_align:
558         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
559                 128 * 4, direction);
560 fail:
561         return -EINVAL;
562 }
563
564 static void sdhci_adma_table_post(struct sdhci_host *host,
565         struct mmc_data *data)
566 {
567         int direction;
568
569         struct scatterlist *sg;
570         int i, size;
571         u8 *align;
572         char *buffer;
573         unsigned long flags;
574
575         if (data->flags & MMC_DATA_READ)
576                 direction = DMA_FROM_DEVICE;
577         else
578                 direction = DMA_TO_DEVICE;
579
580         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
581                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
582
583         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
584                 128 * 4, direction);
585
586         if (data->flags & MMC_DATA_READ) {
587                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
588                         data->sg_len, direction);
589
590                 align = host->align_buffer;
591
592                 for_each_sg(data->sg, sg, host->sg_count, i) {
593                         if (sg_dma_address(sg) & 0x3) {
594                                 size = 4 - (sg_dma_address(sg) & 0x3);
595
596                                 buffer = sdhci_kmap_atomic(sg, &flags);
597                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
598                                 memcpy(buffer, align, size);
599                                 sdhci_kunmap_atomic(buffer, &flags);
600
601                                 align += 4;
602                         }
603                 }
604         }
605
606         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
607                 data->sg_len, direction);
608 }
609
610 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
611 {
612         u8 count;
613         struct mmc_data *data = cmd->data;
614         unsigned target_timeout, current_timeout;
615
616         /*
617          * If the host controller provides us with an incorrect timeout
618          * value, just skip the check and use 0xE.  The hardware may take
619          * longer to time out, but that's much better than having a too-short
620          * timeout value.
621          */
622         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
623                 return 0xE;
624
625         /* Unspecified timeout, assume max */
626         if (!data && !cmd->cmd_timeout_ms)
627                 return 0xE;
628
629         /* timeout in us */
630         if (!data)
631                 target_timeout = cmd->cmd_timeout_ms * 1000;
632         else {
633                 target_timeout = data->timeout_ns / 1000;
634                 if (host->clock)
635                         target_timeout += data->timeout_clks / host->clock;
636         }
637
638         /*
639          * Figure out needed cycles.
640          * We do this in steps in order to fit inside a 32 bit int.
641          * The first step is the minimum timeout, which will have a
642          * minimum resolution of 6 bits:
643          * (1) 2^13*1000 > 2^22,
644          * (2) host->timeout_clk < 2^16
645          *     =>
646          *     (1) / (2) > 2^6
647          */
648         count = 0;
649         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
650         while (current_timeout < target_timeout) {
651                 count++;
652                 current_timeout <<= 1;
653                 if (count >= 0xF)
654                         break;
655         }
656
657         if (count >= 0xF) {
658                 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
659                        mmc_hostname(host->mmc), cmd->opcode);
660                 count = 0xE;
661         }
662
663         return count;
664 }
665
666 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
667 {
668         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
669         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
670
671         if (host->flags & SDHCI_REQ_USE_DMA)
672                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
673         else
674                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
675 }
676
677 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
678 {
679         u8 count;
680         u8 ctrl;
681         struct mmc_data *data = cmd->data;
682         int ret;
683
684         WARN_ON(host->data);
685
686         if (data || (cmd->flags & MMC_RSP_BUSY)) {
687                 count = sdhci_calc_timeout(host, cmd);
688                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
689         }
690
691         if (!data)
692                 return;
693
694         /* Sanity checks */
695         BUG_ON(data->blksz * data->blocks > 524288);
696         BUG_ON(data->blksz > host->mmc->max_blk_size);
697         BUG_ON(data->blocks > 65535);
698
699         host->data = data;
700         host->data_early = 0;
701         host->data->bytes_xfered = 0;
702
703         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
704                 host->flags |= SDHCI_REQ_USE_DMA;
705
706         /*
707          * FIXME: This doesn't account for merging when mapping the
708          * scatterlist.
709          */
710         if (host->flags & SDHCI_REQ_USE_DMA) {
711                 int broken, i;
712                 struct scatterlist *sg;
713
714                 broken = 0;
715                 if (host->flags & SDHCI_USE_ADMA) {
716                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
717                                 broken = 1;
718                 } else {
719                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
720                                 broken = 1;
721                 }
722
723                 if (unlikely(broken)) {
724                         for_each_sg(data->sg, sg, data->sg_len, i) {
725                                 if (sg->length & 0x3) {
726                                         DBG("Reverting to PIO because of "
727                                                 "transfer size (%d)\n",
728                                                 sg->length);
729                                         host->flags &= ~SDHCI_REQ_USE_DMA;
730                                         break;
731                                 }
732                         }
733                 }
734         }
735
736         /*
737          * The assumption here being that alignment is the same after
738          * translation to device address space.
739          */
740         if (host->flags & SDHCI_REQ_USE_DMA) {
741                 int broken, i;
742                 struct scatterlist *sg;
743
744                 broken = 0;
745                 if (host->flags & SDHCI_USE_ADMA) {
746                         /*
747                          * As we use 3 byte chunks to work around
748                          * alignment problems, we need to check this
749                          * quirk.
750                          */
751                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
752                                 broken = 1;
753                 } else {
754                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
755                                 broken = 1;
756                 }
757
758                 if (unlikely(broken)) {
759                         for_each_sg(data->sg, sg, data->sg_len, i) {
760                                 if (sg->offset & 0x3) {
761                                         DBG("Reverting to PIO because of "
762                                                 "bad alignment\n");
763                                         host->flags &= ~SDHCI_REQ_USE_DMA;
764                                         break;
765                                 }
766                         }
767                 }
768         }
769
770         if (host->flags & SDHCI_REQ_USE_DMA) {
771                 if (host->flags & SDHCI_USE_ADMA) {
772                         ret = sdhci_adma_table_pre(host, data);
773                         if (ret) {
774                                 /*
775                                  * This only happens when someone fed
776                                  * us an invalid request.
777                                  */
778                                 WARN_ON(1);
779                                 host->flags &= ~SDHCI_REQ_USE_DMA;
780                         } else {
781                                 sdhci_writel(host, host->adma_addr,
782                                         SDHCI_ADMA_ADDRESS);
783                         }
784                 } else {
785                         int sg_cnt;
786
787                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
788                                         data->sg, data->sg_len,
789                                         (data->flags & MMC_DATA_READ) ?
790                                                 DMA_FROM_DEVICE :
791                                                 DMA_TO_DEVICE);
792                         if (sg_cnt == 0) {
793                                 /*
794                                  * This only happens when someone fed
795                                  * us an invalid request.
796                                  */
797                                 WARN_ON(1);
798                                 host->flags &= ~SDHCI_REQ_USE_DMA;
799                         } else {
800                                 WARN_ON(sg_cnt != 1);
801                                 sdhci_writel(host, sg_dma_address(data->sg),
802                                         SDHCI_DMA_ADDRESS);
803                         }
804                 }
805         }
806
807         /*
808          * Always adjust the DMA selection as some controllers
809          * (e.g. JMicron) can't do PIO properly when the selection
810          * is ADMA.
811          */
812         if (host->version >= SDHCI_SPEC_200) {
813                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
814                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
815                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
816                         (host->flags & SDHCI_USE_ADMA))
817                         ctrl |= SDHCI_CTRL_ADMA32;
818                 else
819                         ctrl |= SDHCI_CTRL_SDMA;
820                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
821         }
822
823         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
824                 int flags;
825
826                 flags = SG_MITER_ATOMIC;
827                 if (host->data->flags & MMC_DATA_READ)
828                         flags |= SG_MITER_TO_SG;
829                 else
830                         flags |= SG_MITER_FROM_SG;
831                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
832                 host->blocks = data->blocks;
833         }
834
835         sdhci_set_transfer_irqs(host);
836
837         /* Set the DMA boundary value and block size */
838         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
839                 data->blksz), SDHCI_BLOCK_SIZE);
840         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
841 }
842
843 static void sdhci_set_transfer_mode(struct sdhci_host *host,
844         struct mmc_command *cmd)
845 {
846         u16 mode;
847         struct mmc_data *data = cmd->data;
848
849         if (data == NULL)
850                 return;
851
852         WARN_ON(!host->data);
853
854         mode = SDHCI_TRNS_BLK_CNT_EN;
855         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
856                 mode |= SDHCI_TRNS_MULTI;
857                 /*
858                  * If we are sending CMD23, CMD12 never gets sent
859                  * on successful completion (so no Auto-CMD12).
860                  */
861                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
862                         mode |= SDHCI_TRNS_AUTO_CMD12;
863                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
864                         mode |= SDHCI_TRNS_AUTO_CMD23;
865                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
866                 }
867         }
868
869         if (data->flags & MMC_DATA_READ)
870                 mode |= SDHCI_TRNS_READ;
871         if (host->flags & SDHCI_REQ_USE_DMA)
872                 mode |= SDHCI_TRNS_DMA;
873
874         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
875 }
876
877 static void sdhci_finish_data(struct sdhci_host *host)
878 {
879         struct mmc_data *data;
880
881         BUG_ON(!host->data);
882
883         data = host->data;
884         host->data = NULL;
885
886         if (host->flags & SDHCI_REQ_USE_DMA) {
887                 if (host->flags & SDHCI_USE_ADMA)
888                         sdhci_adma_table_post(host, data);
889                 else {
890                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
891                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
892                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
893                 }
894         }
895
896         /*
897          * The specification states that the block count register must
898          * be updated, but it does not specify at what point in the
899          * data flow. That makes the register entirely useless to read
900          * back so we have to assume that nothing made it to the card
901          * in the event of an error.
902          */
903         if (data->error)
904                 data->bytes_xfered = 0;
905         else
906                 data->bytes_xfered = data->blksz * data->blocks;
907
908         /*
909          * Need to send CMD12 if -
910          * a) open-ended multiblock transfer (no CMD23)
911          * b) error in multiblock transfer
912          */
913         if (data->stop &&
914             (data->error ||
915              !host->mrq->sbc)) {
916
917                 /*
918                  * The controller needs a reset of internal state machines
919                  * upon error conditions.
920                  */
921                 if (data->error) {
922                         sdhci_reset(host, SDHCI_RESET_CMD);
923                         sdhci_reset(host, SDHCI_RESET_DATA);
924                 }
925
926                 sdhci_send_command(host, data->stop);
927         } else
928                 tasklet_schedule(&host->finish_tasklet);
929 }
930
931 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
932 {
933         int flags;
934         u32 mask;
935         unsigned long timeout;
936
937         WARN_ON(host->cmd);
938
939         /* Wait max 10 ms */
940         timeout = 10;
941
942         mask = SDHCI_CMD_INHIBIT;
943         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
944                 mask |= SDHCI_DATA_INHIBIT;
945
946         /* We shouldn't wait for data inihibit for stop commands, even
947            though they might use busy signaling */
948         if (host->mrq->data && (cmd == host->mrq->data->stop))
949                 mask &= ~SDHCI_DATA_INHIBIT;
950
951         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
952                 if (timeout == 0) {
953                         printk(KERN_ERR "%s: Controller never released "
954                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
955                         sdhci_dumpregs(host);
956                         cmd->error = -EIO;
957                         tasklet_schedule(&host->finish_tasklet);
958                         return;
959                 }
960                 timeout--;
961                 mdelay(1);
962         }
963
964         mod_timer(&host->timer, jiffies + 10 * HZ);
965
966         host->cmd = cmd;
967
968         sdhci_prepare_data(host, cmd);
969
970         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
971
972         sdhci_set_transfer_mode(host, cmd);
973
974         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
975                 printk(KERN_ERR "%s: Unsupported response type!\n",
976                         mmc_hostname(host->mmc));
977                 cmd->error = -EINVAL;
978                 tasklet_schedule(&host->finish_tasklet);
979                 return;
980         }
981
982         if (!(cmd->flags & MMC_RSP_PRESENT))
983                 flags = SDHCI_CMD_RESP_NONE;
984         else if (cmd->flags & MMC_RSP_136)
985                 flags = SDHCI_CMD_RESP_LONG;
986         else if (cmd->flags & MMC_RSP_BUSY)
987                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
988         else
989                 flags = SDHCI_CMD_RESP_SHORT;
990
991         if (cmd->flags & MMC_RSP_CRC)
992                 flags |= SDHCI_CMD_CRC;
993         if (cmd->flags & MMC_RSP_OPCODE)
994                 flags |= SDHCI_CMD_INDEX;
995
996         /* CMD19 is special in that the Data Present Select should be set */
997         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
998                 flags |= SDHCI_CMD_DATA;
999
1000         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1001 }
1002
1003 static void sdhci_finish_command(struct sdhci_host *host)
1004 {
1005         int i;
1006
1007         BUG_ON(host->cmd == NULL);
1008
1009         if (host->cmd->flags & MMC_RSP_PRESENT) {
1010                 if (host->cmd->flags & MMC_RSP_136) {
1011                         /* CRC is stripped so we need to do some shifting. */
1012                         for (i = 0;i < 4;i++) {
1013                                 host->cmd->resp[i] = sdhci_readl(host,
1014                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1015                                 if (i != 3)
1016                                         host->cmd->resp[i] |=
1017                                                 sdhci_readb(host,
1018                                                 SDHCI_RESPONSE + (3-i)*4-1);
1019                         }
1020                 } else {
1021                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1022                 }
1023         }
1024
1025         host->cmd->error = 0;
1026
1027         /* Finished CMD23, now send actual command. */
1028         if (host->cmd == host->mrq->sbc) {
1029                 host->cmd = NULL;
1030                 sdhci_send_command(host, host->mrq->cmd);
1031         } else {
1032
1033                 /* Processed actual command. */
1034                 if (host->data && host->data_early)
1035                         sdhci_finish_data(host);
1036
1037                 if (!host->cmd->data)
1038                         tasklet_schedule(&host->finish_tasklet);
1039
1040                 host->cmd = NULL;
1041         }
1042 }
1043
1044 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1045 {
1046         int div = 0; /* Initialized for compiler warning */
1047         u16 clk = 0;
1048         unsigned long timeout;
1049
1050         if (clock && clock == host->clock)
1051                 return;
1052
1053         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1054                 return;
1055
1056         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1057
1058         if (clock == 0)
1059                 goto out;
1060
1061         if (host->version >= SDHCI_SPEC_300) {
1062                 /*
1063                  * Check if the Host Controller supports Programmable Clock
1064                  * Mode.
1065                  */
1066                 if (host->clk_mul) {
1067                         u16 ctrl;
1068
1069                         /*
1070                          * We need to figure out whether the Host Driver needs
1071                          * to select Programmable Clock Mode, or the value can
1072                          * be set automatically by the Host Controller based on
1073                          * the Preset Value registers.
1074                          */
1075                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1076                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1077                                 for (div = 1; div <= 1024; div++) {
1078                                         if (((host->max_clk * host->clk_mul) /
1079                                               div) <= clock)
1080                                                 break;
1081                                 }
1082                                 /*
1083                                  * Set Programmable Clock Mode in the Clock
1084                                  * Control register.
1085                                  */
1086                                 clk = SDHCI_PROG_CLOCK_MODE;
1087                                 div--;
1088                         }
1089                 } else {
1090                         /* Version 3.00 divisors must be a multiple of 2. */
1091                         if (host->max_clk <= clock)
1092                                 div = 1;
1093                         else {
1094                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1095                                      div += 2) {
1096                                         if ((host->max_clk / div) <= clock)
1097                                                 break;
1098                                 }
1099                         }
1100                         div >>= 1;
1101                 }
1102         } else {
1103                 /* Version 2.00 divisors must be a power of 2. */
1104                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1105                         if ((host->max_clk / div) <= clock)
1106                                 break;
1107                 }
1108                 div >>= 1;
1109         }
1110
1111         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1112         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1113                 << SDHCI_DIVIDER_HI_SHIFT;
1114         clk |= SDHCI_CLOCK_INT_EN;
1115         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1116
1117         /* Wait max 20 ms */
1118         timeout = 20;
1119         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1120                 & SDHCI_CLOCK_INT_STABLE)) {
1121                 if (timeout == 0) {
1122                         printk(KERN_ERR "%s: Internal clock never "
1123                                 "stabilised.\n", mmc_hostname(host->mmc));
1124                         sdhci_dumpregs(host);
1125                         return;
1126                 }
1127                 timeout--;
1128                 mdelay(1);
1129         }
1130
1131         clk |= SDHCI_CLOCK_CARD_EN;
1132         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1133
1134 out:
1135         host->clock = clock;
1136 }
1137
1138 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1139 {
1140         u8 pwr = 0;
1141
1142         if (power != (unsigned short)-1) {
1143                 switch (1 << power) {
1144                 case MMC_VDD_165_195:
1145                         pwr = SDHCI_POWER_180;
1146                         break;
1147                 case MMC_VDD_29_30:
1148                 case MMC_VDD_30_31:
1149                         pwr = SDHCI_POWER_300;
1150                         break;
1151                 case MMC_VDD_32_33:
1152                 case MMC_VDD_33_34:
1153                         pwr = SDHCI_POWER_330;
1154                         break;
1155                 default:
1156                         BUG();
1157                 }
1158         }
1159
1160         if (host->pwr == pwr)
1161                 return;
1162
1163         host->pwr = pwr;
1164
1165         if (pwr == 0) {
1166                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1167                 return;
1168         }
1169
1170         /*
1171          * Spec says that we should clear the power reg before setting
1172          * a new value. Some controllers don't seem to like this though.
1173          */
1174         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1175                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1176
1177         /*
1178          * At least the Marvell CaFe chip gets confused if we set the voltage
1179          * and set turn on power at the same time, so set the voltage first.
1180          */
1181         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1182                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1183
1184         pwr |= SDHCI_POWER_ON;
1185
1186         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1187
1188         /*
1189          * Some controllers need an extra 10ms delay of 10ms before they
1190          * can apply clock after applying power
1191          */
1192         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1193                 mdelay(10);
1194 }
1195
1196 /*****************************************************************************\
1197  *                                                                           *
1198  * MMC callbacks                                                             *
1199  *                                                                           *
1200 \*****************************************************************************/
1201
1202 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1203 {
1204         struct sdhci_host *host;
1205         bool present;
1206         unsigned long flags;
1207
1208         host = mmc_priv(mmc);
1209
1210         spin_lock_irqsave(&host->lock, flags);
1211
1212         WARN_ON(host->mrq != NULL);
1213
1214 #ifndef SDHCI_USE_LEDS_CLASS
1215         sdhci_activate_led(host);
1216 #endif
1217
1218         /*
1219          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1220          * requests if Auto-CMD12 is enabled.
1221          */
1222         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1223                 if (mrq->stop) {
1224                         mrq->data->stop = NULL;
1225                         mrq->stop = NULL;
1226                 }
1227         }
1228
1229         host->mrq = mrq;
1230
1231         /* If polling, assume that the card is always present. */
1232         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
1233                 if (host->ops->get_cd)
1234                         present = host->ops->get_cd(host);
1235                 else
1236                         present = true;
1237         } else {
1238                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1239                                 SDHCI_CARD_PRESENT;
1240         }
1241
1242         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1243                 host->mrq->cmd->error = -ENOMEDIUM;
1244                 tasklet_schedule(&host->finish_tasklet);
1245         } else {
1246                 u32 present_state;
1247
1248                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1249                 /*
1250                  * Check if the re-tuning timer has already expired and there
1251                  * is no on-going data transfer. If so, we need to execute
1252                  * tuning procedure before sending command.
1253                  */
1254                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1255                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1256                         spin_unlock_irqrestore(&host->lock, flags);
1257                         sdhci_execute_tuning(mmc);
1258                         spin_lock_irqsave(&host->lock, flags);
1259
1260                         /* Restore original mmc_request structure */
1261                         host->mrq = mrq;
1262                 }
1263
1264                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1265                         sdhci_send_command(host, mrq->sbc);
1266                 else
1267                         sdhci_send_command(host, mrq->cmd);
1268         }
1269
1270         mmiowb();
1271         spin_unlock_irqrestore(&host->lock, flags);
1272 }
1273
1274 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1275 {
1276         struct sdhci_host *host;
1277         unsigned long flags;
1278         u8 ctrl;
1279
1280         host = mmc_priv(mmc);
1281
1282         /*
1283          * Controller registers should not be updated without the
1284          * controller clock enabled. Set the minimum controller
1285          * clock if there is no clock.
1286          */
1287         if (host->ops->set_clock) {
1288                 if (!host->clock && !ios->clock) {
1289                         host->ops->set_clock(host, host->mmc->f_min);
1290                         host->clock = host->mmc->f_min;
1291                 } else if (ios->clock && (ios->clock != host->clock)) {
1292                         host->ops->set_clock(host, ios->clock);
1293                 }
1294         }
1295
1296         spin_lock_irqsave(&host->lock, flags);
1297
1298         if (host->flags & SDHCI_DEVICE_DEAD)
1299                 goto out;
1300
1301         /*
1302          * Reset the chip on each power off.
1303          * Should clear out any weird states.
1304          */
1305         if (ios->power_mode == MMC_POWER_OFF) {
1306                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1307                 sdhci_reinit(host);
1308         }
1309
1310         if (ios->power_mode == MMC_POWER_OFF)
1311                 sdhci_set_power(host, -1);
1312         else
1313                 sdhci_set_power(host, ios->vdd);
1314
1315         sdhci_set_clock(host, ios->clock);
1316
1317         if (host->ops->platform_send_init_74_clocks)
1318                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1319
1320         /*
1321          * If your platform has 8-bit width support but is not a v3 controller,
1322          * or if it requires special setup code, you should implement that in
1323          * platform_8bit_width().
1324          */
1325         if (host->ops->platform_8bit_width)
1326                 host->ops->platform_8bit_width(host, ios->bus_width);
1327         else {
1328                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1329                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1330                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1331                         if (host->version >= SDHCI_SPEC_300)
1332                                 ctrl |= SDHCI_CTRL_8BITBUS;
1333                 } else {
1334                         if (host->version >= SDHCI_SPEC_300)
1335                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1336                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1337                                 ctrl |= SDHCI_CTRL_4BITBUS;
1338                         else
1339                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1340                 }
1341                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1342         }
1343
1344         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1345
1346         if ((ios->timing == MMC_TIMING_SD_HS ||
1347              ios->timing == MMC_TIMING_MMC_HS)
1348             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1349                 ctrl |= SDHCI_CTRL_HISPD;
1350         else
1351                 ctrl &= ~SDHCI_CTRL_HISPD;
1352
1353         if (host->version >= SDHCI_SPEC_300) {
1354                 u16 clk, ctrl_2;
1355
1356                 /* In case of UHS-I modes, set High Speed Enable */
1357                 if (((ios->timing == MMC_TIMING_UHS_SDR50) ||
1358                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1359                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1360                     (ios->timing == MMC_TIMING_UHS_SDR25) ||
1361                     (ios->timing == MMC_TIMING_UHS_SDR12))
1362                     && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1363                         ctrl |= SDHCI_CTRL_HISPD;
1364
1365                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1366                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1367                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1368                         /*
1369                          * We only need to set Driver Strength if the
1370                          * preset value enable is not set.
1371                          */
1372                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1373                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1374                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1375                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1376                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1377
1378                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1379                 } else {
1380                         /*
1381                          * According to SDHC Spec v3.00, if the Preset Value
1382                          * Enable in the Host Control 2 register is set, we
1383                          * need to reset SD Clock Enable before changing High
1384                          * Speed Enable to avoid generating clock gliches.
1385                          */
1386
1387                         /* Reset SD Clock Enable */
1388                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1389                         clk &= ~SDHCI_CLOCK_CARD_EN;
1390                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1391
1392                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1393
1394                         /* Re-enable SD Clock */
1395                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1396                         clk |= SDHCI_CLOCK_CARD_EN;
1397                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1398                 }
1399
1400
1401                 /* Reset SD Clock Enable */
1402                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1403                 clk &= ~SDHCI_CLOCK_CARD_EN;
1404                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1405
1406                 if (host->ops->set_uhs_signaling)
1407                         host->ops->set_uhs_signaling(host, ios->timing);
1408                 else {
1409                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1410                         /* Select Bus Speed Mode for host */
1411                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1412                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1413                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1414                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1415                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1416                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1417                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1418                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1419                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1420                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1421                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1422                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1423                 }
1424
1425                 /* Re-enable SD Clock */
1426                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1427                 clk |= SDHCI_CLOCK_CARD_EN;
1428                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1429         } else
1430                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1431
1432         /*
1433          * Some (ENE) controllers go apeshit on some ios operation,
1434          * signalling timeout and CRC errors even on CMD0. Resetting
1435          * it on each ios seems to solve the problem.
1436          */
1437         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1438                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1439
1440 out:
1441         mmiowb();
1442         spin_unlock_irqrestore(&host->lock, flags);
1443         /*
1444          * Controller clock should only be disabled after all the register
1445          * writes are done.
1446          */
1447         if (!ios->clock && host->ops->set_clock)
1448                 host->ops->set_clock(host, ios->clock);
1449 }
1450
1451 static int check_ro(struct sdhci_host *host)
1452 {
1453         unsigned long flags;
1454         int is_readonly;
1455
1456         spin_lock_irqsave(&host->lock, flags);
1457
1458         if (host->flags & SDHCI_DEVICE_DEAD)
1459                 is_readonly = 0;
1460         else if (host->ops->get_ro)
1461                 is_readonly = host->ops->get_ro(host);
1462         else
1463                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1464                                 & SDHCI_WRITE_PROTECT);
1465
1466         spin_unlock_irqrestore(&host->lock, flags);
1467
1468         /* This quirk needs to be replaced by a callback-function later */
1469         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1470                 !is_readonly : is_readonly;
1471 }
1472
1473 #define SAMPLE_COUNT    5
1474
1475 static int sdhci_get_ro(struct mmc_host *mmc)
1476 {
1477         struct sdhci_host *host;
1478         int i, ro_count;
1479
1480         host = mmc_priv(mmc);
1481
1482         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1483                 return check_ro(host);
1484
1485         ro_count = 0;
1486         for (i = 0; i < SAMPLE_COUNT; i++) {
1487                 if (check_ro(host)) {
1488                         if (++ro_count > SAMPLE_COUNT / 2)
1489                                 return 1;
1490                 }
1491                 msleep(30);
1492         }
1493         return 0;
1494 }
1495
1496 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1497 {
1498         struct sdhci_host *host;
1499         unsigned long flags;
1500
1501         host = mmc_priv(mmc);
1502
1503         spin_lock_irqsave(&host->lock, flags);
1504
1505         if (host->flags & SDHCI_DEVICE_DEAD)
1506                 goto out;
1507
1508         if (enable)
1509                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1510         else
1511                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1512 out:
1513         mmiowb();
1514
1515         spin_unlock_irqrestore(&host->lock, flags);
1516 }
1517
1518 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1519         struct mmc_ios *ios)
1520 {
1521         struct sdhci_host *host;
1522         u8 pwr;
1523         u16 clk, ctrl;
1524         u32 present_state;
1525
1526         host = mmc_priv(mmc);
1527
1528         /*
1529          * Signal Voltage Switching is only applicable for Host Controllers
1530          * v3.00 and above.
1531          */
1532         if (host->version < SDHCI_SPEC_300)
1533                 return 0;
1534
1535         if (host->quirks & SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING) {
1536                 if (host->ops->switch_signal_voltage)
1537                         return host->ops->switch_signal_voltage(
1538                                 host, ios->signal_voltage);
1539         }
1540
1541         /*
1542          * We first check whether the request is to set signalling voltage
1543          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1544          */
1545         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1546         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1547                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1548                 ctrl &= ~SDHCI_CTRL_VDD_180;
1549                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1550
1551                 /* Wait for 5ms */
1552                 usleep_range(5000, 5500);
1553
1554                 /* 3.3V regulator output should be stable within 5 ms */
1555                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1556                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1557                         return 0;
1558                 else {
1559                         printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1560                                 "signalling voltage failed\n");
1561                         return -EIO;
1562                 }
1563         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1564                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1565                 /* Stop SDCLK */
1566                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1567                 clk &= ~SDHCI_CLOCK_CARD_EN;
1568                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1569
1570                 /* Check whether DAT[3:0] is 0000 */
1571                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1572                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1573                        SDHCI_DATA_LVL_SHIFT)) {
1574                         /*
1575                          * Enable 1.8V Signal Enable in the Host Control2
1576                          * register
1577                          */
1578                         ctrl |= SDHCI_CTRL_VDD_180;
1579                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1580
1581                         /* Wait for 5ms */
1582                         usleep_range(5000, 5500);
1583                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1584                         if (ctrl & SDHCI_CTRL_VDD_180) {
1585                                 /* Provide SDCLK again and wait for 1ms*/
1586                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1587                                 clk |= SDHCI_CLOCK_CARD_EN;
1588                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1589                                 usleep_range(1000, 1500);
1590
1591                                 /*
1592                                  * If DAT[3:0] level is 1111b, then the card
1593                                  * was successfully switched to 1.8V signaling.
1594                                  */
1595                                 present_state = sdhci_readl(host,
1596                                                         SDHCI_PRESENT_STATE);
1597                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1598                                      SDHCI_DATA_LVL_MASK)
1599                                         return 0;
1600                         }
1601                 }
1602
1603                 /*
1604                  * If we are here, that means the switch to 1.8V signaling
1605                  * failed. We power cycle the card, and retry initialization
1606                  * sequence by setting S18R to 0.
1607                  */
1608                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1609                 pwr &= ~SDHCI_POWER_ON;
1610                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1611
1612                 /* Wait for 1ms as per the spec */
1613                 usleep_range(1000, 1500);
1614                 pwr |= SDHCI_POWER_ON;
1615                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1616
1617                 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1618                         "voltage failed, retrying with S18R set to 0\n");
1619                 return -EAGAIN;
1620         } else
1621                 /* No signal voltage switch required */
1622                 return 0;
1623 }
1624
1625 static int sdhci_execute_tuning(struct mmc_host *mmc)
1626 {
1627         struct sdhci_host *host;
1628         u16 ctrl;
1629         u32 ier;
1630         int tuning_loop_counter = MAX_TUNING_LOOP;
1631         unsigned long timeout;
1632         int err = 0;
1633
1634         host = mmc_priv(mmc);
1635
1636         disable_irq(host->irq);
1637         spin_lock(&host->lock);
1638
1639         if ((host->quirks & SDHCI_QUIRK_NON_STANDARD_TUNING) &&
1640                 host->ops->execute_freq_tuning) {
1641                 err = host->ops->execute_freq_tuning(host);
1642                 spin_unlock(&host->lock);
1643                 enable_irq(host->irq);
1644                 return err;
1645         }
1646
1647         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1648
1649         /*
1650          * Host Controller needs tuning only in case of SDR104 mode
1651          * and for SDR50 mode when Use Tuning for SDR50 is set in
1652          * Capabilities register.
1653          */
1654         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1655             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1656             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1657                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1658         else {
1659                 spin_unlock(&host->lock);
1660                 enable_irq(host->irq);
1661                 return 0;
1662         }
1663
1664         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1665
1666         /*
1667          * As per the Host Controller spec v3.00, tuning command
1668          * generates Buffer Read Ready interrupt, so enable that.
1669          *
1670          * Note: The spec clearly says that when tuning sequence
1671          * is being performed, the controller does not generate
1672          * interrupts other than Buffer Read Ready interrupt. But
1673          * to make sure we don't hit a controller bug, we _only_
1674          * enable Buffer Read Ready interrupt here.
1675          */
1676         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1677         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1678
1679         /*
1680          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1681          * of loops reaches 40 times or a timeout of 150ms occurs.
1682          */
1683         timeout = 150;
1684         do {
1685                 struct mmc_command cmd = {0};
1686                 struct mmc_request mrq = {0};
1687
1688                 if (!tuning_loop_counter && !timeout)
1689                         break;
1690
1691                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1692                 cmd.arg = 0;
1693                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1694                 cmd.retries = 0;
1695                 cmd.data = NULL;
1696                 cmd.error = 0;
1697
1698                 mrq.cmd = &cmd;
1699                 host->mrq = &mrq;
1700
1701                 /*
1702                  * In response to CMD19, the card sends 64 bytes of tuning
1703                  * block to the Host Controller. So we set the block size
1704                  * to 64 here.
1705                  */
1706                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1707
1708                 /*
1709                  * The tuning block is sent by the card to the host controller.
1710                  * So we set the TRNS_READ bit in the Transfer Mode register.
1711                  * This also takes care of setting DMA Enable and Multi Block
1712                  * Select in the same register to 0.
1713                  */
1714                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1715
1716                 sdhci_send_command(host, &cmd);
1717
1718                 host->cmd = NULL;
1719                 host->mrq = NULL;
1720
1721                 spin_unlock(&host->lock);
1722                 enable_irq(host->irq);
1723
1724                 /* Wait for Buffer Read Ready interrupt */
1725                 wait_event_interruptible_timeout(host->buf_ready_int,
1726                                         (host->tuning_done == 1),
1727                                         msecs_to_jiffies(50));
1728                 disable_irq(host->irq);
1729                 spin_lock(&host->lock);
1730
1731                 if (!host->tuning_done) {
1732                         printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1733                                 "Buffer Read Ready interrupt during tuning "
1734                                 "procedure, falling back to fixed sampling "
1735                                 "clock\n");
1736                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1737                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1738                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1739                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1740
1741                         err = -EIO;
1742                         goto out;
1743                 }
1744
1745                 host->tuning_done = 0;
1746
1747                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1748                 tuning_loop_counter--;
1749                 timeout--;
1750                 mdelay(1);
1751         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1752
1753         /*
1754          * The Host Driver has exhausted the maximum number of loops allowed,
1755          * so use fixed sampling frequency.
1756          */
1757         if (!tuning_loop_counter || !timeout) {
1758                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1759                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1760         } else {
1761                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1762                         printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1763                                 " failed, falling back to fixed sampling"
1764                                 " clock\n");
1765                         err = -EIO;
1766                 }
1767         }
1768
1769 out:
1770         /*
1771          * If this is the very first time we are here, we start the retuning
1772          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1773          * flag won't be set, we check this condition before actually starting
1774          * the timer.
1775          */
1776         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1777             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1778                 mod_timer(&host->tuning_timer, jiffies +
1779                         host->tuning_count * HZ);
1780                 /* Tuning mode 1 limits the maximum data length to 4MB */
1781                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1782         } else {
1783                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1784                 /* Reload the new initial value for timer */
1785                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1786                         mod_timer(&host->tuning_timer, jiffies +
1787                                 host->tuning_count * HZ);
1788         }
1789
1790         /*
1791          * In case tuning fails, host controllers which support re-tuning can
1792          * try tuning again at a later time, when the re-tuning timer expires.
1793          * So for these controllers, we return 0. Since there might be other
1794          * controllers who do not have this capability, we return error for
1795          * them.
1796          */
1797         if (err && host->tuning_count &&
1798             host->tuning_mode == SDHCI_TUNING_MODE_1)
1799                 err = 0;
1800
1801         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1802         spin_unlock(&host->lock);
1803         enable_irq(host->irq);
1804
1805         return err;
1806 }
1807
1808 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1809 {
1810         struct sdhci_host *host;
1811         u16 ctrl;
1812         unsigned long flags;
1813
1814         host = mmc_priv(mmc);
1815
1816         /* Host Controller v3.00 defines preset value registers */
1817         if (host->version < SDHCI_SPEC_300)
1818                 return;
1819
1820         /*
1821          * Enabling preset value would make programming clock
1822          * divider ineffective. The controller would use the
1823          * values present in the preset value registers. In
1824          * case of non-standard clock, let the platform driver
1825          * decide whether to enable preset or not.
1826          */
1827         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1828                 return;
1829
1830         spin_lock_irqsave(&host->lock, flags);
1831
1832         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1833
1834         /*
1835          * We only enable or disable Preset Value if they are not already
1836          * enabled or disabled respectively. Otherwise, we bail out.
1837          */
1838         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1839                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1840                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1841         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1842                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1843                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1844         }
1845
1846         spin_unlock_irqrestore(&host->lock, flags);
1847 }
1848
1849 int sdhci_enable(struct mmc_host *mmc)
1850 {
1851         struct sdhci_host *host = mmc_priv(mmc);
1852         u16 clk;
1853
1854         if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO)
1855                 return 0;
1856
1857         if (mmc->ios.clock) {
1858                 if (host->ops->set_clock)
1859                         host->ops->set_clock(host, mmc->ios.clock);
1860                 sdhci_set_clock(host, mmc->ios.clock);
1861         }
1862
1863         return 0;
1864 }
1865
1866 int sdhci_disable(struct mmc_host *mmc, int lazy)
1867 {
1868         struct sdhci_host *host = mmc_priv(mmc);
1869         u16 clk;
1870
1871         if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO)
1872                 return 0;
1873
1874         sdhci_set_clock(host, 0);
1875         if (host->ops->set_clock)
1876                 host->ops->set_clock(host, 0);
1877
1878         return 0;
1879 }
1880
1881 static const struct mmc_host_ops sdhci_ops = {
1882         .request        = sdhci_request,
1883         .set_ios        = sdhci_set_ios,
1884         .get_ro         = sdhci_get_ro,
1885         .enable         = sdhci_enable,
1886         .disable        = sdhci_disable,
1887         .enable_sdio_irq = sdhci_enable_sdio_irq,
1888         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1889         .execute_tuning                 = sdhci_execute_tuning,
1890         .enable_preset_value            = sdhci_enable_preset_value,
1891 };
1892
1893 /*****************************************************************************\
1894  *                                                                           *
1895  * Tasklets                                                                  *
1896  *                                                                           *
1897 \*****************************************************************************/
1898
1899 static void sdhci_tasklet_card(unsigned long param)
1900 {
1901         struct sdhci_host *host;
1902         unsigned long flags;
1903
1904         host = (struct sdhci_host*)param;
1905
1906         spin_lock_irqsave(&host->lock, flags);
1907
1908         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1909                 if (host->mrq) {
1910                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1911                                 mmc_hostname(host->mmc));
1912                         printk(KERN_ERR "%s: Resetting controller.\n",
1913                                 mmc_hostname(host->mmc));
1914
1915                         sdhci_reset(host, SDHCI_RESET_CMD);
1916                         sdhci_reset(host, SDHCI_RESET_DATA);
1917
1918                         host->mrq->cmd->error = -ENOMEDIUM;
1919                         tasklet_schedule(&host->finish_tasklet);
1920                 }
1921         }
1922
1923         spin_unlock_irqrestore(&host->lock, flags);
1924
1925         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1926 }
1927
1928 static void sdhci_tasklet_finish(unsigned long param)
1929 {
1930         struct sdhci_host *host;
1931         unsigned long flags;
1932         struct mmc_request *mrq;
1933
1934         host = (struct sdhci_host*)param;
1935
1936         /*
1937          * If this tasklet gets rescheduled while running, it will
1938          * be run again afterwards but without any active request.
1939          */
1940         if (!host->mrq)
1941                 return;
1942
1943         spin_lock_irqsave(&host->lock, flags);
1944
1945         del_timer(&host->timer);
1946
1947         mrq = host->mrq;
1948
1949         /*
1950          * The controller needs a reset of internal state machines
1951          * upon error conditions.
1952          */
1953         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1954             ((mrq->cmd && mrq->cmd->error) ||
1955                  (mrq->data && (mrq->data->error ||
1956                   (mrq->data->stop && mrq->data->stop->error))) ||
1957                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1958
1959                 /* Some controllers need this kick or reset won't work here */
1960                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1961                         unsigned int clock;
1962
1963                         /* This is to force an update */
1964                         clock = host->clock;
1965                         host->clock = 0;
1966                         if (host->ops->set_clock)
1967                                 host->ops->set_clock(host, clock);
1968                         sdhci_set_clock(host, clock);
1969                 }
1970
1971                 /* Spec says we should do both at the same time, but Ricoh
1972                    controllers do not like that. */
1973                 sdhci_reset(host, SDHCI_RESET_CMD);
1974                 sdhci_reset(host, SDHCI_RESET_DATA);
1975         }
1976
1977         host->mrq = NULL;
1978         host->cmd = NULL;
1979         host->data = NULL;
1980
1981 #ifndef SDHCI_USE_LEDS_CLASS
1982         sdhci_deactivate_led(host);
1983 #endif
1984
1985         mmiowb();
1986         spin_unlock_irqrestore(&host->lock, flags);
1987
1988         mmc_request_done(host->mmc, mrq);
1989 }
1990
1991 static void sdhci_timeout_timer(unsigned long data)
1992 {
1993         struct sdhci_host *host;
1994         unsigned long flags;
1995
1996         host = (struct sdhci_host*)data;
1997
1998         spin_lock_irqsave(&host->lock, flags);
1999
2000         if (host->mrq) {
2001                 printk(KERN_ERR "%s: Timeout waiting for hardware "
2002                         "interrupt.\n", mmc_hostname(host->mmc));
2003                 sdhci_dumpregs(host);
2004
2005                 if (host->data) {
2006                         host->data->error = -ETIMEDOUT;
2007                         sdhci_finish_data(host);
2008                 } else {
2009                         if (host->cmd)
2010                                 host->cmd->error = -ETIMEDOUT;
2011                         else
2012                                 host->mrq->cmd->error = -ETIMEDOUT;
2013
2014                         tasklet_schedule(&host->finish_tasklet);
2015                 }
2016         }
2017
2018         mmiowb();
2019         spin_unlock_irqrestore(&host->lock, flags);
2020 }
2021
2022 static void sdhci_tuning_timer(unsigned long data)
2023 {
2024         struct sdhci_host *host;
2025         unsigned long flags;
2026
2027         host = (struct sdhci_host *)data;
2028
2029         spin_lock_irqsave(&host->lock, flags);
2030
2031         host->flags |= SDHCI_NEEDS_RETUNING;
2032
2033         spin_unlock_irqrestore(&host->lock, flags);
2034 }
2035
2036 /*****************************************************************************\
2037  *                                                                           *
2038  * Interrupt handling                                                        *
2039  *                                                                           *
2040 \*****************************************************************************/
2041
2042 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2043 {
2044         BUG_ON(intmask == 0);
2045
2046         if (!host->cmd) {
2047                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
2048                         "though no command operation was in progress.\n",
2049                         mmc_hostname(host->mmc), (unsigned)intmask);
2050                 sdhci_dumpregs(host);
2051                 return;
2052         }
2053
2054         if (intmask & SDHCI_INT_TIMEOUT)
2055                 host->cmd->error = -ETIMEDOUT;
2056         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2057                         SDHCI_INT_INDEX))
2058                 host->cmd->error = -EILSEQ;
2059
2060         if (host->cmd->error) {
2061                 tasklet_schedule(&host->finish_tasklet);
2062                 return;
2063         }
2064
2065         /*
2066          * The host can send and interrupt when the busy state has
2067          * ended, allowing us to wait without wasting CPU cycles.
2068          * Unfortunately this is overloaded on the "data complete"
2069          * interrupt, so we need to take some care when handling
2070          * it.
2071          *
2072          * Note: The 1.0 specification is a bit ambiguous about this
2073          *       feature so there might be some problems with older
2074          *       controllers.
2075          */
2076         if (host->cmd->flags & MMC_RSP_BUSY) {
2077                 if (host->cmd->data)
2078                         DBG("Cannot wait for busy signal when also "
2079                                 "doing a data transfer");
2080                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2081                         return;
2082
2083                 /* The controller does not support the end-of-busy IRQ,
2084                  * fall through and take the SDHCI_INT_RESPONSE */
2085         }
2086
2087         if (intmask & SDHCI_INT_RESPONSE)
2088                 sdhci_finish_command(host);
2089 }
2090
2091 #ifdef CONFIG_MMC_DEBUG
2092 static void sdhci_show_adma_error(struct sdhci_host *host)
2093 {
2094         const char *name = mmc_hostname(host->mmc);
2095         u8 *desc = host->adma_desc;
2096         __le32 *dma;
2097         __le16 *len;
2098         u8 attr;
2099
2100         sdhci_dumpregs(host);
2101
2102         while (true) {
2103                 dma = (__le32 *)(desc + 4);
2104                 len = (__le16 *)(desc + 2);
2105                 attr = *desc;
2106
2107                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2108                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2109
2110                 desc += 8;
2111
2112                 if (attr & 2)
2113                         break;
2114         }
2115 }
2116 #else
2117 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2118 #endif
2119
2120 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2121 {
2122         BUG_ON(intmask == 0);
2123
2124         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2125         if (intmask & SDHCI_INT_DATA_AVAIL) {
2126                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2127                     MMC_SEND_TUNING_BLOCK) {
2128                         host->tuning_done = 1;
2129                         wake_up(&host->buf_ready_int);
2130                         return;
2131                 }
2132         }
2133
2134         if (!host->data) {
2135                 /*
2136                  * The "data complete" interrupt is also used to
2137                  * indicate that a busy state has ended. See comment
2138                  * above in sdhci_cmd_irq().
2139                  */
2140                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2141                         if (intmask & SDHCI_INT_DATA_END) {
2142                                 sdhci_finish_command(host);
2143                                 return;
2144                         }
2145                 }
2146
2147                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2148                         "though no data operation was in progress.\n",
2149                         mmc_hostname(host->mmc), (unsigned)intmask);
2150                 sdhci_dumpregs(host);
2151
2152                 return;
2153         }
2154
2155         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2156                 host->data->error = -ETIMEDOUT;
2157         else if (intmask & SDHCI_INT_DATA_END_BIT)
2158                 host->data->error = -EILSEQ;
2159         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2160                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2161                         != MMC_BUS_TEST_R)
2162                 host->data->error = -EILSEQ;
2163         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2164                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2165                 sdhci_show_adma_error(host);
2166                 host->data->error = -EIO;
2167         }
2168
2169         if (host->data->error)
2170                 sdhci_finish_data(host);
2171         else {
2172                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2173                         sdhci_transfer_pio(host);
2174
2175                 /*
2176                  * We currently don't do anything fancy with DMA
2177                  * boundaries, but as we can't disable the feature
2178                  * we need to at least restart the transfer.
2179                  *
2180                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2181                  * should return a valid address to continue from, but as
2182                  * some controllers are faulty, don't trust them.
2183                  */
2184                 if (intmask & SDHCI_INT_DMA_END) {
2185                         u32 dmastart, dmanow;
2186                         dmastart = sg_dma_address(host->data->sg);
2187                         dmanow = dmastart + host->data->bytes_xfered;
2188                         /*
2189                          * Force update to the next DMA block boundary.
2190                          */
2191                         dmanow = (dmanow &
2192                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2193                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2194                         host->data->bytes_xfered = dmanow - dmastart;
2195                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2196                                 " next 0x%08x\n",
2197                                 mmc_hostname(host->mmc), dmastart,
2198                                 host->data->bytes_xfered, dmanow);
2199                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2200                 }
2201
2202                 if (intmask & SDHCI_INT_DATA_END) {
2203                         if (host->cmd) {
2204                                 /*
2205                                  * Data managed to finish before the
2206                                  * command completed. Make sure we do
2207                                  * things in the proper order.
2208                                  */
2209                                 host->data_early = 1;
2210                         } else {
2211                                 sdhci_finish_data(host);
2212                         }
2213                 }
2214         }
2215 }
2216
2217 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2218 {
2219         irqreturn_t result;
2220         struct sdhci_host* host = dev_id;
2221         u32 intmask;
2222         int cardint = 0;
2223
2224         spin_lock(&host->lock);
2225
2226         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2227
2228         if (!intmask || intmask == 0xffffffff) {
2229                 result = IRQ_NONE;
2230                 goto out;
2231         }
2232
2233         DBG("*** %s got interrupt: 0x%08x\n",
2234                 mmc_hostname(host->mmc), intmask);
2235
2236         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2237                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2238                               SDHCI_CARD_PRESENT;
2239
2240                 /*
2241                  * There is a observation on i.mx esdhc.  INSERT bit will be
2242                  * immediately set again when it gets cleared, if a card is
2243                  * inserted.  We have to mask the irq to prevent interrupt
2244                  * storm which will freeze the system.  And the REMOVE gets
2245                  * the same situation.
2246                  *
2247                  * More testing are needed here to ensure it works for other
2248                  * platforms though.
2249                  */
2250                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2251                                                 SDHCI_INT_CARD_REMOVE);
2252                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2253                                                   SDHCI_INT_CARD_INSERT);
2254
2255                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2256                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2257                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2258                 tasklet_schedule(&host->card_tasklet);
2259         }
2260
2261         if (intmask & SDHCI_INT_CMD_MASK) {
2262                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2263                         SDHCI_INT_STATUS);
2264                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2265         }
2266
2267         if (intmask & SDHCI_INT_DATA_MASK) {
2268                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2269                         SDHCI_INT_STATUS);
2270                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2271         }
2272
2273         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2274
2275         intmask &= ~SDHCI_INT_ERROR;
2276
2277         if (intmask & SDHCI_INT_BUS_POWER) {
2278                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
2279                         mmc_hostname(host->mmc));
2280                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2281         }
2282
2283         intmask &= ~SDHCI_INT_BUS_POWER;
2284
2285         if (intmask & SDHCI_INT_CARD_INT)
2286                 cardint = 1;
2287
2288         intmask &= ~SDHCI_INT_CARD_INT;
2289
2290         if (intmask) {
2291                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
2292                         mmc_hostname(host->mmc), intmask);
2293                 sdhci_dumpregs(host);
2294
2295                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2296         }
2297
2298         result = IRQ_HANDLED;
2299
2300         mmiowb();
2301 out:
2302         spin_unlock(&host->lock);
2303
2304         /*
2305          * We have to delay this as it calls back into the driver.
2306          */
2307         if (cardint)
2308                 mmc_signal_sdio_irq(host->mmc);
2309
2310         return result;
2311 }
2312
2313 /*****************************************************************************\
2314  *                                                                           *
2315  * Suspend/resume                                                            *
2316  *                                                                           *
2317 \*****************************************************************************/
2318
2319 #ifdef CONFIG_PM
2320
2321 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
2322 {
2323         int ret = 0;
2324         bool has_tuning_timer;
2325         struct mmc_host *mmc = host->mmc;
2326
2327         sdhci_disable_card_detection(host);
2328
2329         /* Disable tuning since we are suspending */
2330         has_tuning_timer = host->version >= SDHCI_SPEC_300 &&
2331                 host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1;
2332         if (has_tuning_timer) {
2333                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2334                 mod_timer(&host->tuning_timer, jiffies +
2335                         host->tuning_count * HZ);
2336         }
2337
2338         if (mmc->card) {
2339                 /*
2340                  * If eMMC cards are put in sleep state, Vccq can be disabled
2341                  * but Vcc would still be powered on. In resume, we only restore
2342                  * the controller context. So, set MMC_PM_KEEP_POWER flag.
2343                  */
2344                 if (mmc_card_can_sleep(mmc) &&
2345                         !(mmc->caps & MMC_CAP2_NO_SLEEP_CMD))
2346                         mmc->pm_flags = MMC_PM_KEEP_POWER;
2347
2348                 ret = mmc_suspend_host(host->mmc);
2349                 if (ret) {
2350                         if (has_tuning_timer) {
2351                                 host->flags |= SDHCI_NEEDS_RETUNING;
2352                                 mod_timer(&host->tuning_timer, jiffies +
2353                                                 host->tuning_count * HZ);
2354                         }
2355
2356                         sdhci_enable_card_detection(host);
2357
2358                         return ret;
2359                 }
2360         }
2361
2362         if (mmc->pm_flags & MMC_PM_KEEP_POWER)
2363                 host->card_int_set = sdhci_readl(host, SDHCI_INT_ENABLE) &
2364                         SDHCI_INT_CARD_INT;
2365
2366         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2367
2368         if (host->vmmc)
2369                 ret = regulator_disable(host->vmmc);
2370
2371         if (host->irq)
2372                 disable_irq(host->irq);
2373
2374         return ret;
2375 }
2376
2377 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2378
2379 int sdhci_resume_host(struct sdhci_host *host)
2380 {
2381         int ret = 0;
2382         struct mmc_host *mmc = host->mmc;
2383
2384         if (host->vmmc) {
2385                 int ret = regulator_enable(host->vmmc);
2386                 if (ret)
2387                         return ret;
2388         }
2389
2390
2391         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2392                 if (host->ops->enable_dma)
2393                         host->ops->enable_dma(host);
2394         }
2395
2396         if (host->irq)
2397                 enable_irq(host->irq);
2398
2399         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2400         mmiowb();
2401
2402         if (mmc->card) {
2403                 ret = mmc_resume_host(host->mmc);
2404                 /* Enable card interrupt as it is overwritten in sdhci_init */
2405                 if ((mmc->caps & MMC_CAP_SDIO_IRQ) &&
2406                         (mmc->pm_flags & MMC_PM_KEEP_POWER))
2407                                 if (host->card_int_set)
2408                                         mmc->ops->enable_sdio_irq(mmc, true);
2409         }
2410
2411         sdhci_enable_card_detection(host);
2412
2413         /* Set the re-tuning expiration flag */
2414         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2415             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2416                 host->flags |= SDHCI_NEEDS_RETUNING;
2417
2418         return ret;
2419 }
2420
2421 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2422
2423 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2424 {
2425         u8 val;
2426         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2427         val |= SDHCI_WAKE_ON_INT;
2428         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2429 }
2430
2431 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2432
2433 #endif /* CONFIG_PM */
2434
2435 /*****************************************************************************\
2436  *                                                                           *
2437  * Device allocation/registration                                            *
2438  *                                                                           *
2439 \*****************************************************************************/
2440
2441 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2442         size_t priv_size)
2443 {
2444         struct mmc_host *mmc;
2445         struct sdhci_host *host;
2446
2447         WARN_ON(dev == NULL);
2448
2449         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2450         if (!mmc)
2451                 return ERR_PTR(-ENOMEM);
2452
2453         host = mmc_priv(mmc);
2454         host->mmc = mmc;
2455
2456         return host;
2457 }
2458
2459 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2460
2461 int sdhci_add_host(struct sdhci_host *host)
2462 {
2463         struct mmc_host *mmc;
2464         u32 caps[2];
2465         u32 max_current_caps;
2466         unsigned int ocr_avail;
2467         int ret;
2468
2469         WARN_ON(host == NULL);
2470         if (host == NULL)
2471                 return -EINVAL;
2472
2473         mmc = host->mmc;
2474
2475         if (debug_quirks)
2476                 host->quirks = debug_quirks;
2477
2478         sdhci_reset(host, SDHCI_RESET_ALL);
2479
2480         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2481         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2482                                 >> SDHCI_SPEC_VER_SHIFT;
2483         if (host->version > SDHCI_SPEC_300) {
2484                 printk(KERN_ERR "%s: Unknown controller version (%d). "
2485                         "You may experience problems.\n", mmc_hostname(mmc),
2486                         host->version);
2487         }
2488
2489         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2490                 sdhci_readl(host, SDHCI_CAPABILITIES);
2491
2492         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2493                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2494
2495         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2496                 host->flags |= SDHCI_USE_SDMA;
2497         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2498                 DBG("Controller doesn't have SDMA capability\n");
2499         else
2500                 host->flags |= SDHCI_USE_SDMA;
2501
2502         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2503                 (host->flags & SDHCI_USE_SDMA)) {
2504                 DBG("Disabling DMA as it is marked broken\n");
2505                 host->flags &= ~SDHCI_USE_SDMA;
2506         }
2507
2508         if ((host->version >= SDHCI_SPEC_200) &&
2509                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2510                 host->flags |= SDHCI_USE_ADMA;
2511
2512         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2513                 (host->flags & SDHCI_USE_ADMA)) {
2514                 DBG("Disabling ADMA as it is marked broken\n");
2515                 host->flags &= ~SDHCI_USE_ADMA;
2516         }
2517
2518         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2519                 if (host->ops->enable_dma) {
2520                         if (host->ops->enable_dma(host)) {
2521                                 printk(KERN_WARNING "%s: No suitable DMA "
2522                                         "available. Falling back to PIO.\n",
2523                                         mmc_hostname(mmc));
2524                                 host->flags &=
2525                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2526                         }
2527                 }
2528         }
2529
2530         if (host->flags & SDHCI_USE_ADMA) {
2531                 /*
2532                  * We need to allocate descriptors for all sg entries
2533                  * (128) and potentially one alignment transfer for
2534                  * each of those entries.
2535                  */
2536                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2537                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2538                 if (!host->adma_desc || !host->align_buffer) {
2539                         kfree(host->adma_desc);
2540                         kfree(host->align_buffer);
2541                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
2542                                 "buffers. Falling back to standard DMA.\n",
2543                                 mmc_hostname(mmc));
2544                         host->flags &= ~SDHCI_USE_ADMA;
2545                 }
2546         }
2547
2548         /*
2549          * If we use DMA, then it's up to the caller to set the DMA
2550          * mask, but PIO does not need the hw shim so we set a new
2551          * mask here in that case.
2552          */
2553         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2554                 host->dma_mask = DMA_BIT_MASK(64);
2555                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2556         }
2557
2558         if (host->version >= SDHCI_SPEC_300)
2559                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2560                         >> SDHCI_CLOCK_BASE_SHIFT;
2561         else
2562                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2563                         >> SDHCI_CLOCK_BASE_SHIFT;
2564
2565         host->max_clk *= 1000000;
2566         if (host->max_clk == 0 || host->quirks &
2567                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2568                 if (!host->ops->get_max_clock) {
2569                         printk(KERN_ERR
2570                                "%s: Hardware doesn't specify base clock "
2571                                "frequency.\n", mmc_hostname(mmc));
2572                         return -ENODEV;
2573                 }
2574                 host->max_clk = host->ops->get_max_clock(host);
2575         }
2576
2577         /*
2578          * In case of Host Controller v3.00, find out whether clock
2579          * multiplier is supported.
2580          */
2581         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2582                         SDHCI_CLOCK_MUL_SHIFT;
2583
2584         /*
2585          * In case the value in Clock Multiplier is 0, then programmable
2586          * clock mode is not supported, otherwise the actual clock
2587          * multiplier is one more than the value of Clock Multiplier
2588          * in the Capabilities Register.
2589          */
2590         if (host->clk_mul)
2591                 host->clk_mul += 1;
2592
2593         /*
2594          * Set host parameters.
2595          */
2596         mmc->ops = &sdhci_ops;
2597         mmc->f_max = host->max_clk;
2598         if (host->ops->get_min_clock)
2599                 mmc->f_min = host->ops->get_min_clock(host);
2600         else if (host->version >= SDHCI_SPEC_300) {
2601                 if (host->clk_mul) {
2602                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2603                         mmc->f_max = host->max_clk * host->clk_mul;
2604                 } else
2605                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2606         } else
2607                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2608
2609         host->timeout_clk =
2610                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2611         if (host->timeout_clk == 0) {
2612                 if (host->ops->get_timeout_clock) {
2613                         host->timeout_clk = host->ops->get_timeout_clock(host);
2614                 } else if (!(host->quirks &
2615                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2616                         printk(KERN_ERR
2617                                "%s: Hardware doesn't specify timeout clock "
2618                                "frequency.\n", mmc_hostname(mmc));
2619                         return -ENODEV;
2620                 }
2621         }
2622         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2623                 host->timeout_clk *= 1000;
2624
2625         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2626                 host->timeout_clk = mmc->f_max / 1000;
2627
2628         if (!(host->quirks & SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO))
2629                 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2630
2631         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2632                 host->flags |= SDHCI_AUTO_CMD12;
2633
2634         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2635         if ((host->version >= SDHCI_SPEC_300) &&
2636             ((host->flags & SDHCI_USE_ADMA) ||
2637              !(host->flags & SDHCI_USE_SDMA))) {
2638                 host->flags |= SDHCI_AUTO_CMD23;
2639                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2640         } else {
2641                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2642         }
2643
2644         /*
2645          * A controller may support 8-bit width, but the board itself
2646          * might not have the pins brought out.  Boards that support
2647          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2648          * their platform code before calling sdhci_add_host(), and we
2649          * won't assume 8-bit width for hosts without that CAP.
2650          */
2651         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2652                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2653
2654         if (caps[0] & SDHCI_CAN_DO_HISPD)
2655                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2656
2657         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2658             mmc_card_is_removable(mmc) && !(host->ops->get_cd))
2659                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2660
2661         if (host->quirks & SDHCI_QUIRK2_NO_1_8_V)
2662                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2663                              SDHCI_SUPPORT_DDR50);
2664         else
2665                 /* UHS-I mode(s) supported by the host controller. */
2666                 if (host->version >= SDHCI_SPEC_300)
2667                         mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2668
2669         /* SDR104 supports also implies SDR50 support */
2670         if (caps[1] & SDHCI_SUPPORT_SDR104)
2671                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2672         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2673                 mmc->caps |= MMC_CAP_UHS_SDR50;
2674
2675         if (caps[1] & SDHCI_SUPPORT_DDR50)
2676                 mmc->caps |= MMC_CAP_UHS_DDR50;
2677
2678         /* Does the host needs tuning for SDR50? */
2679         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2680                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2681
2682         /* Driver Type(s) (A, C, D) supported by the host */
2683         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2684                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2685         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2686                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2687         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2688                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2689
2690         /* Initial value for re-tuning timer count */
2691         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2692                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2693
2694         /*
2695          * In case Re-tuning Timer is not disabled, the actual value of
2696          * re-tuning timer will be 2 ^ (n - 1).
2697          */
2698         if (host->tuning_count)
2699                 host->tuning_count = 1 << (host->tuning_count - 1);
2700
2701         /* Re-tuning mode supported by the Host Controller */
2702         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2703                              SDHCI_RETUNING_MODE_SHIFT;
2704
2705         ocr_avail = 0;
2706         /*
2707          * According to SD Host Controller spec v3.00, if the Host System
2708          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2709          * the value is meaningful only if Voltage Support in the Capabilities
2710          * register is set. The actual current value is 4 times the register
2711          * value.
2712          */
2713         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2714
2715         if (caps[0] & SDHCI_CAN_VDD_330) {
2716                 int max_current_330;
2717
2718                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2719
2720                 max_current_330 = ((max_current_caps &
2721                                    SDHCI_MAX_CURRENT_330_MASK) >>
2722                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2723                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2724
2725                 if (max_current_330 > 150)
2726                         mmc->caps |= MMC_CAP_SET_XPC_330;
2727         }
2728         if (caps[0] & SDHCI_CAN_VDD_300) {
2729                 int max_current_300;
2730
2731                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2732
2733                 max_current_300 = ((max_current_caps &
2734                                    SDHCI_MAX_CURRENT_300_MASK) >>
2735                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2736                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2737
2738                 if (max_current_300 > 150)
2739                         mmc->caps |= MMC_CAP_SET_XPC_300;
2740         }
2741         if (caps[0] & SDHCI_CAN_VDD_180) {
2742                 int max_current_180;
2743
2744                 ocr_avail |= MMC_VDD_165_195;
2745
2746                 max_current_180 = ((max_current_caps &
2747                                    SDHCI_MAX_CURRENT_180_MASK) >>
2748                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2749                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2750
2751                 if (max_current_180 > 150)
2752                         mmc->caps |= MMC_CAP_SET_XPC_180;
2753
2754                 /* Maximum current capabilities of the host at 1.8V */
2755                 if (max_current_180 >= 800)
2756                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2757                 else if (max_current_180 >= 600)
2758                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2759                 else if (max_current_180 >= 400)
2760                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2761                 else
2762                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2763         }
2764
2765         mmc->ocr_avail = ocr_avail;
2766         mmc->ocr_avail_sdio = ocr_avail;
2767         if (host->ocr_avail_sdio)
2768                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2769         mmc->ocr_avail_sd = ocr_avail;
2770         if (host->ocr_avail_sd)
2771                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2772         else /* normal SD controllers don't support 1.8V */
2773                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2774         mmc->ocr_avail_mmc = ocr_avail;
2775         if (host->ocr_avail_mmc)
2776                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2777
2778         if (mmc->ocr_avail == 0) {
2779                 printk(KERN_ERR "%s: Hardware doesn't report any "
2780                         "support voltages.\n", mmc_hostname(mmc));
2781                 return -ENODEV;
2782         }
2783
2784         spin_lock_init(&host->lock);
2785
2786         /*
2787          * Maximum number of segments. Depends on if the hardware
2788          * can do scatter/gather or not.
2789          */
2790         if (host->flags & SDHCI_USE_ADMA)
2791                 mmc->max_segs = 128;
2792         else if (host->flags & SDHCI_USE_SDMA)
2793                 mmc->max_segs = 1;
2794         else /* PIO */
2795                 mmc->max_segs = 128;
2796
2797         /*
2798          * Maximum number of sectors in one transfer. Limited by DMA boundary
2799          * size (512KiB).
2800          */
2801         mmc->max_req_size = 524288;
2802
2803         /*
2804          * Maximum segment size. Could be one segment with the maximum number
2805          * of bytes. When doing hardware scatter/gather, each entry cannot
2806          * be larger than 64 KiB though.
2807          */
2808         if (host->flags & SDHCI_USE_ADMA) {
2809                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2810                         mmc->max_seg_size = 65535;
2811                 else
2812                         mmc->max_seg_size = 65536;
2813         } else {
2814                 mmc->max_seg_size = mmc->max_req_size;
2815         }
2816
2817         /*
2818          * Maximum block size. This varies from controller to controller and
2819          * is specified in the capabilities register.
2820          */
2821         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2822                 mmc->max_blk_size = 2;
2823         } else {
2824                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2825                                 SDHCI_MAX_BLOCK_SHIFT;
2826                 if (mmc->max_blk_size >= 3) {
2827                         printk(KERN_WARNING "%s: Invalid maximum block size, "
2828                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2829                         mmc->max_blk_size = 0;
2830                 }
2831         }
2832
2833         mmc->max_blk_size = 512 << mmc->max_blk_size;
2834
2835         /*
2836          * Maximum block count.
2837          */
2838         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2839
2840         /*
2841          * Init tasklets.
2842          */
2843         tasklet_init(&host->card_tasklet,
2844                 sdhci_tasklet_card, (unsigned long)host);
2845         tasklet_init(&host->finish_tasklet,
2846                 sdhci_tasklet_finish, (unsigned long)host);
2847
2848         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2849
2850         if (host->version >= SDHCI_SPEC_300) {
2851                 init_waitqueue_head(&host->buf_ready_int);
2852
2853                 /* Initialize re-tuning timer */
2854                 init_timer(&host->tuning_timer);
2855                 host->tuning_timer.data = (unsigned long)host;
2856                 host->tuning_timer.function = sdhci_tuning_timer;
2857         }
2858
2859         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2860                 mmc_hostname(mmc), host);
2861         if (ret)
2862                 goto untasklet;
2863
2864         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2865         if (IS_ERR(host->vmmc)) {
2866                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2867                 host->vmmc = NULL;
2868         } else {
2869                 regulator_enable(host->vmmc);
2870         }
2871
2872         sdhci_init(host, 0);
2873
2874 #ifdef CONFIG_MMC_DEBUG
2875         sdhci_dumpregs(host);
2876 #endif
2877
2878 #ifdef SDHCI_USE_LEDS_CLASS
2879         snprintf(host->led_name, sizeof(host->led_name),
2880                 "%s::", mmc_hostname(mmc));
2881         host->led.name = host->led_name;
2882         host->led.brightness = LED_OFF;
2883         host->led.default_trigger = mmc_hostname(mmc);
2884         host->led.brightness_set = sdhci_led_control;
2885
2886         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2887         if (ret)
2888                 goto reset;
2889 #endif
2890
2891         mmiowb();
2892
2893         mmc_add_host(mmc);
2894
2895         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2896                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2897                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2898                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2899
2900         sdhci_enable_card_detection(host);
2901
2902         return 0;
2903
2904 #ifdef SDHCI_USE_LEDS_CLASS
2905 reset:
2906         sdhci_reset(host, SDHCI_RESET_ALL);
2907         free_irq(host->irq, host);
2908 #endif
2909 untasklet:
2910         tasklet_kill(&host->card_tasklet);
2911         tasklet_kill(&host->finish_tasklet);
2912
2913         return ret;
2914 }
2915
2916 EXPORT_SYMBOL_GPL(sdhci_add_host);
2917
2918 void sdhci_remove_host(struct sdhci_host *host, int dead)
2919 {
2920         unsigned long flags;
2921
2922         if (dead) {
2923                 spin_lock_irqsave(&host->lock, flags);
2924
2925                 host->flags |= SDHCI_DEVICE_DEAD;
2926
2927                 if (host->mrq) {
2928                         printk(KERN_ERR "%s: Controller removed during "
2929                                 " transfer!\n", mmc_hostname(host->mmc));
2930
2931                         host->mrq->cmd->error = -ENOMEDIUM;
2932                         tasklet_schedule(&host->finish_tasklet);
2933                 }
2934
2935                 spin_unlock_irqrestore(&host->lock, flags);
2936         }
2937
2938         sdhci_disable_card_detection(host);
2939
2940         mmc_remove_host(host->mmc);
2941
2942 #ifdef SDHCI_USE_LEDS_CLASS
2943         led_classdev_unregister(&host->led);
2944 #endif
2945
2946         if (!dead)
2947                 sdhci_reset(host, SDHCI_RESET_ALL);
2948
2949         free_irq(host->irq, host);
2950
2951         del_timer_sync(&host->timer);
2952         if (host->version >= SDHCI_SPEC_300)
2953                 del_timer_sync(&host->tuning_timer);
2954
2955         tasklet_kill(&host->card_tasklet);
2956         tasklet_kill(&host->finish_tasklet);
2957
2958         if (host->vmmc) {
2959                 regulator_disable(host->vmmc);
2960                 regulator_put(host->vmmc);
2961         }
2962
2963         kfree(host->adma_desc);
2964         kfree(host->align_buffer);
2965
2966         host->adma_desc = NULL;
2967         host->align_buffer = NULL;
2968 }
2969
2970 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2971
2972 void sdhci_free_host(struct sdhci_host *host)
2973 {
2974         mmc_free_host(host->mmc);
2975 }
2976
2977 EXPORT_SYMBOL_GPL(sdhci_free_host);
2978
2979 /*****************************************************************************\
2980  *                                                                           *
2981  * Driver init/exit                                                          *
2982  *                                                                           *
2983 \*****************************************************************************/
2984
2985 static int __init sdhci_drv_init(void)
2986 {
2987         printk(KERN_INFO DRIVER_NAME
2988                 ": Secure Digital Host Controller Interface driver\n");
2989         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2990
2991         return 0;
2992 }
2993
2994 static void __exit sdhci_drv_exit(void)
2995 {
2996 }
2997
2998 module_init(sdhci_drv_init);
2999 module_exit(sdhci_drv_exit);
3000
3001 module_param(debug_quirks, uint, 0444);
3002
3003 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3004 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3005 MODULE_LICENSE("GPL");
3006
3007 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");