Merge commit 'main-jb-2012.08.03-B4' into t114-0806
[linux-2.6.git] / drivers / mmc / host / sdhci.c
1 /*
2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3  *
4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or (at
9  * your option) any later version.
10  *
11  * Thanks to the following companies for their support:
12  *
13  *     - JMicron (hardware and technical support)
14  */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31
32 #include "sdhci.h"
33
34 #define DRIVER_NAME "sdhci"
35
36 #define DBG(f, x...) \
37         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
38
39 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
40         defined(CONFIG_MMC_SDHCI_MODULE))
41 #define SDHCI_USE_LEDS_CLASS
42 #endif
43
44 #define MAX_TUNING_LOOP 40
45
46 static unsigned int debug_quirks = 0;
47 static unsigned int debug_quirks2;
48
49 static void sdhci_finish_data(struct sdhci_host *);
50
51 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
52 static void sdhci_finish_command(struct sdhci_host *);
53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54 static void sdhci_tuning_timer(unsigned long data);
55
56 #ifdef CONFIG_PM_RUNTIME
57 static int sdhci_runtime_pm_get(struct sdhci_host *host);
58 static int sdhci_runtime_pm_put(struct sdhci_host *host);
59 #else
60 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
61 {
62         return 0;
63 }
64 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
65 {
66         return 0;
67 }
68 #endif
69
70 static void sdhci_dumpregs(struct sdhci_host *host)
71 {
72         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
73                 mmc_hostname(host->mmc));
74
75         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
76                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
77                 sdhci_readw(host, SDHCI_HOST_VERSION));
78         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
79                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
80                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
81         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
82                 sdhci_readl(host, SDHCI_ARGUMENT),
83                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
84         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
85                 sdhci_readl(host, SDHCI_PRESENT_STATE),
86                 sdhci_readb(host, SDHCI_HOST_CONTROL));
87         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
88                 sdhci_readb(host, SDHCI_POWER_CONTROL),
89                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
90         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
91                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
92                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
93         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
94                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
95                 sdhci_readl(host, SDHCI_INT_STATUS));
96         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
97                 sdhci_readl(host, SDHCI_INT_ENABLE),
98                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
99         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
100                 sdhci_readw(host, SDHCI_ACMD12_ERR),
101                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
102         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
103                 sdhci_readl(host, SDHCI_CAPABILITIES),
104                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
105         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
106                 sdhci_readw(host, SDHCI_COMMAND),
107                 sdhci_readl(host, SDHCI_MAX_CURRENT));
108         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
109                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
110
111         if (host->flags & SDHCI_USE_ADMA)
112                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
113                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
114                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
115
116         pr_debug(DRIVER_NAME ": ===========================================\n");
117 }
118
119 /*****************************************************************************\
120  *                                                                           *
121  * Low level functions                                                       *
122  *                                                                           *
123 \*****************************************************************************/
124
125 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
126 {
127         u32 ier;
128
129         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
130         ier &= ~clear;
131         ier |= set;
132         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
133         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
134 }
135
136 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
137 {
138         sdhci_clear_set_irqs(host, 0, irqs);
139 }
140
141 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
142 {
143         sdhci_clear_set_irqs(host, irqs, 0);
144 }
145
146 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
147 {
148         u32 present, irqs;
149
150         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
151             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
152                 return;
153
154         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155                               SDHCI_CARD_PRESENT;
156         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
157
158         if (enable)
159                 sdhci_unmask_irqs(host, irqs);
160         else
161                 sdhci_mask_irqs(host, irqs);
162 }
163
164 static void sdhci_enable_card_detection(struct sdhci_host *host)
165 {
166         sdhci_set_card_detection(host, true);
167 }
168
169 static void sdhci_disable_card_detection(struct sdhci_host *host)
170 {
171         sdhci_set_card_detection(host, false);
172 }
173
174 static void sdhci_reset(struct sdhci_host *host, u8 mask)
175 {
176         unsigned long timeout;
177         u32 uninitialized_var(ier);
178
179         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
180                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
181                         SDHCI_CARD_PRESENT))
182                         return;
183         }
184
185         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
186                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
187
188         if (host->ops->platform_reset_enter)
189                 host->ops->platform_reset_enter(host, mask);
190
191         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
192
193         if (mask & SDHCI_RESET_ALL)
194                 host->clock = 0;
195
196         /* Wait max 100 ms */
197         timeout = 100;
198
199         /* hw clears the bit when it's done */
200         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
201                 if (timeout == 0) {
202                         pr_err("%s: Reset 0x%x never completed.\n",
203                                 mmc_hostname(host->mmc), (int)mask);
204                         sdhci_dumpregs(host);
205                         return;
206                 }
207                 timeout--;
208                 mdelay(1);
209         }
210
211         if (host->ops->platform_reset_exit)
212                 host->ops->platform_reset_exit(host, mask);
213
214         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
215                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
216
217         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
219                         host->ops->enable_dma(host);
220         }
221 }
222
223 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
224
225 static void sdhci_init(struct sdhci_host *host, int soft)
226 {
227         if (soft)
228                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
229         else
230                 sdhci_reset(host, SDHCI_RESET_ALL);
231
232         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
233                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
235                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
236                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
237
238         if (soft) {
239                 /* force clock reconfiguration */
240                 host->clock = 0;
241                 sdhci_set_ios(host->mmc, &host->mmc->ios);
242         }
243 }
244
245 static void sdhci_reinit(struct sdhci_host *host)
246 {
247         sdhci_init(host, 0);
248         sdhci_enable_card_detection(host);
249 }
250
251 static void sdhci_activate_led(struct sdhci_host *host)
252 {
253         u8 ctrl;
254
255         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
256         ctrl |= SDHCI_CTRL_LED;
257         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
258 }
259
260 static void sdhci_deactivate_led(struct sdhci_host *host)
261 {
262         u8 ctrl;
263
264         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
265         ctrl &= ~SDHCI_CTRL_LED;
266         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
267 }
268
269 #ifdef SDHCI_USE_LEDS_CLASS
270 static void sdhci_led_control(struct led_classdev *led,
271         enum led_brightness brightness)
272 {
273         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
274         unsigned long flags;
275
276         spin_lock_irqsave(&host->lock, flags);
277
278         if (host->runtime_suspended)
279                 goto out;
280
281         if (brightness == LED_OFF)
282                 sdhci_deactivate_led(host);
283         else
284                 sdhci_activate_led(host);
285 out:
286         spin_unlock_irqrestore(&host->lock, flags);
287 }
288 #endif
289
290 /*****************************************************************************\
291  *                                                                           *
292  * Core functions                                                            *
293  *                                                                           *
294 \*****************************************************************************/
295
296 static void sdhci_read_block_pio(struct sdhci_host *host)
297 {
298         unsigned long flags;
299         size_t blksize, len, chunk;
300         u32 uninitialized_var(scratch);
301         u8 *buf;
302
303         DBG("PIO reading\n");
304
305         blksize = host->data->blksz;
306         chunk = 0;
307
308         local_irq_save(flags);
309
310         while (blksize) {
311                 if (!sg_miter_next(&host->sg_miter))
312                         BUG();
313
314                 len = min(host->sg_miter.length, blksize);
315
316                 blksize -= len;
317                 host->sg_miter.consumed = len;
318
319                 buf = host->sg_miter.addr;
320
321                 while (len) {
322                         if (chunk == 0) {
323                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
324                                 chunk = 4;
325                         }
326
327                         *buf = scratch & 0xFF;
328
329                         buf++;
330                         scratch >>= 8;
331                         chunk--;
332                         len--;
333                 }
334         }
335
336         sg_miter_stop(&host->sg_miter);
337
338         local_irq_restore(flags);
339 }
340
341 static void sdhci_write_block_pio(struct sdhci_host *host)
342 {
343         unsigned long flags;
344         size_t blksize, len, chunk;
345         u32 scratch;
346         u8 *buf;
347
348         DBG("PIO writing\n");
349
350         blksize = host->data->blksz;
351         chunk = 0;
352         scratch = 0;
353
354         local_irq_save(flags);
355
356         while (blksize) {
357                 if (!sg_miter_next(&host->sg_miter))
358                         BUG();
359
360                 len = min(host->sg_miter.length, blksize);
361
362                 blksize -= len;
363                 host->sg_miter.consumed = len;
364
365                 buf = host->sg_miter.addr;
366
367                 while (len) {
368                         scratch |= (u32)*buf << (chunk * 8);
369
370                         buf++;
371                         chunk++;
372                         len--;
373
374                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
375                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
376                                 chunk = 0;
377                                 scratch = 0;
378                         }
379                 }
380         }
381
382         sg_miter_stop(&host->sg_miter);
383
384         local_irq_restore(flags);
385 }
386
387 static void sdhci_transfer_pio(struct sdhci_host *host)
388 {
389         u32 mask;
390
391         BUG_ON(!host->data);
392
393         if (host->blocks == 0)
394                 return;
395
396         if (host->data->flags & MMC_DATA_READ)
397                 mask = SDHCI_DATA_AVAILABLE;
398         else
399                 mask = SDHCI_SPACE_AVAILABLE;
400
401         /*
402          * Some controllers (JMicron JMB38x) mess up the buffer bits
403          * for transfers < 4 bytes. As long as it is just one block,
404          * we can ignore the bits.
405          */
406         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
407                 (host->data->blocks == 1))
408                 mask = ~0;
409
410         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
411                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
412                         udelay(100);
413
414                 if (host->data->flags & MMC_DATA_READ)
415                         sdhci_read_block_pio(host);
416                 else
417                         sdhci_write_block_pio(host);
418
419                 host->blocks--;
420                 if (host->blocks == 0)
421                         break;
422         }
423
424         DBG("PIO transfer complete.\n");
425 }
426
427 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
428 {
429         local_irq_save(*flags);
430         return kmap_atomic(sg_page(sg)) + sg->offset;
431 }
432
433 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
434 {
435         kunmap_atomic(buffer);
436         local_irq_restore(*flags);
437 }
438
439 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
440 {
441         __le32 *dataddr = (__le32 __force *)(desc + 4);
442         __le16 *cmdlen = (__le16 __force *)desc;
443
444         /* SDHCI specification says ADMA descriptors should be 4 byte
445          * aligned, so using 16 or 32bit operations should be safe. */
446
447         cmdlen[0] = cpu_to_le16(cmd);
448         cmdlen[1] = cpu_to_le16(len);
449
450         dataddr[0] = cpu_to_le32(addr);
451 }
452
453 static int sdhci_adma_table_pre(struct sdhci_host *host,
454         struct mmc_data *data)
455 {
456         int direction;
457
458         u8 *desc;
459         u8 *align;
460         dma_addr_t addr;
461         dma_addr_t align_addr;
462         int len, offset;
463
464         struct scatterlist *sg;
465         int i;
466         char *buffer;
467         unsigned long flags;
468
469         /*
470          * The spec does not specify endianness of descriptor table.
471          * We currently guess that it is LE.
472          */
473
474         if (data->flags & MMC_DATA_READ)
475                 direction = DMA_FROM_DEVICE;
476         else
477                 direction = DMA_TO_DEVICE;
478
479         /*
480          * The ADMA descriptor table is mapped further down as we
481          * need to fill it with data first.
482          */
483
484         host->align_addr = dma_map_single(mmc_dev(host->mmc),
485                 host->align_buffer, 128 * 4, direction);
486         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
487                 goto fail;
488         BUG_ON(host->align_addr & 0x3);
489
490         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
491                 data->sg, data->sg_len, direction);
492         if (host->sg_count == 0)
493                 goto unmap_align;
494
495         desc = host->adma_desc;
496         align = host->align_buffer;
497
498         align_addr = host->align_addr;
499
500         for_each_sg(data->sg, sg, host->sg_count, i) {
501                 addr = sg_dma_address(sg);
502                 len = sg_dma_len(sg);
503
504                 /*
505                  * The SDHCI specification states that ADMA
506                  * addresses must be 32-bit aligned. If they
507                  * aren't, then we use a bounce buffer for
508                  * the (up to three) bytes that screw up the
509                  * alignment.
510                  */
511                 offset = (4 - (addr & 0x3)) & 0x3;
512                 if (offset) {
513                         if (data->flags & MMC_DATA_WRITE) {
514                                 buffer = sdhci_kmap_atomic(sg, &flags);
515                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
516                                 memcpy(align, buffer, offset);
517                                 sdhci_kunmap_atomic(buffer, &flags);
518                         }
519
520                         /* tran, valid */
521                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
522
523                         BUG_ON(offset > 65536);
524
525                         align += 4;
526                         align_addr += 4;
527
528                         desc += 8;
529
530                         addr += offset;
531                         len -= offset;
532                 }
533
534                 BUG_ON(len > 65536);
535
536                 /* tran, valid */
537                 sdhci_set_adma_desc(desc, addr, len, 0x21);
538                 desc += 8;
539
540                 /*
541                  * If this triggers then we have a calculation bug
542                  * somewhere. :/
543                  */
544                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
545         }
546
547         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
548                 /*
549                 * Mark the last descriptor as the terminating descriptor
550                 */
551                 if (desc != host->adma_desc) {
552                         desc -= 8;
553                         desc[0] |= 0x2; /* end */
554                 }
555         } else {
556                 /*
557                 * Add a terminating entry.
558                 */
559
560                 /* nop, end, valid */
561                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
562         }
563
564         /*
565          * Resync align buffer as we might have changed it.
566          */
567         if (data->flags & MMC_DATA_WRITE) {
568                 dma_sync_single_for_device(mmc_dev(host->mmc),
569                         host->align_addr, 128 * 4, direction);
570         }
571
572         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
573                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
574         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
575                 goto unmap_entries;
576         BUG_ON(host->adma_addr & 0x3);
577
578         return 0;
579
580 unmap_entries:
581         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
582                 data->sg_len, direction);
583 unmap_align:
584         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
585                 128 * 4, direction);
586 fail:
587         return -EINVAL;
588 }
589
590 static void sdhci_adma_table_post(struct sdhci_host *host,
591         struct mmc_data *data)
592 {
593         int direction;
594
595         struct scatterlist *sg;
596         int i, size;
597         u8 *align;
598         char *buffer;
599         unsigned long flags;
600
601         if (data->flags & MMC_DATA_READ)
602                 direction = DMA_FROM_DEVICE;
603         else
604                 direction = DMA_TO_DEVICE;
605
606         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
607                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
608
609         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
610                 128 * 4, direction);
611
612         if (data->flags & MMC_DATA_READ) {
613                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
614                         data->sg_len, direction);
615
616                 align = host->align_buffer;
617
618                 for_each_sg(data->sg, sg, host->sg_count, i) {
619                         if (sg_dma_address(sg) & 0x3) {
620                                 size = 4 - (sg_dma_address(sg) & 0x3);
621
622                                 buffer = sdhci_kmap_atomic(sg, &flags);
623                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
624                                 memcpy(buffer, align, size);
625                                 sdhci_kunmap_atomic(buffer, &flags);
626
627                                 align += 4;
628                         }
629                 }
630         }
631
632         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
633                 data->sg_len, direction);
634 }
635
636 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
637 {
638         u8 count;
639         struct mmc_data *data = cmd->data;
640         unsigned target_timeout, current_timeout;
641
642         /*
643          * If the host controller provides us with an incorrect timeout
644          * value, just skip the check and use 0xE.  The hardware may take
645          * longer to time out, but that's much better than having a too-short
646          * timeout value.
647          */
648         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
649                 return 0xE;
650
651         /* Unspecified timeout, assume max */
652         if (!data && !cmd->cmd_timeout_ms)
653                 return 0xE;
654
655         /* timeout in us */
656         if (!data)
657                 target_timeout = cmd->cmd_timeout_ms * 1000;
658         else {
659                 target_timeout = data->timeout_ns / 1000;
660                 if (host->clock)
661                         target_timeout += data->timeout_clks / host->clock;
662         }
663
664         /*
665          * Figure out needed cycles.
666          * We do this in steps in order to fit inside a 32 bit int.
667          * The first step is the minimum timeout, which will have a
668          * minimum resolution of 6 bits:
669          * (1) 2^13*1000 > 2^22,
670          * (2) host->timeout_clk < 2^16
671          *     =>
672          *     (1) / (2) > 2^6
673          */
674         count = 0;
675         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
676         while (current_timeout < target_timeout) {
677                 count++;
678                 current_timeout <<= 1;
679                 if (count >= 0xF)
680                         break;
681         }
682
683         if (count >= 0xF)
684                 count = 0xE;
685
686         return count;
687 }
688
689 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
690 {
691         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
692         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
693
694         if (host->flags & SDHCI_REQ_USE_DMA)
695                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
696         else
697                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
698 }
699
700 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
701 {
702         u8 count;
703         u8 ctrl;
704         struct mmc_data *data = cmd->data;
705         int ret;
706
707         WARN_ON(host->data);
708
709         if (data || (cmd->flags & MMC_RSP_BUSY)) {
710                 count = sdhci_calc_timeout(host, cmd);
711                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
712         }
713
714         if (!data)
715                 return;
716
717         /* Sanity checks */
718         BUG_ON(data->blksz * data->blocks > 524288);
719         BUG_ON(data->blksz > host->mmc->max_blk_size);
720         BUG_ON(data->blocks > 65535);
721
722         host->data = data;
723         host->data_early = 0;
724         host->data->bytes_xfered = 0;
725
726         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
727                 host->flags |= SDHCI_REQ_USE_DMA;
728
729         /*
730          * FIXME: This doesn't account for merging when mapping the
731          * scatterlist.
732          */
733         if (host->flags & SDHCI_REQ_USE_DMA) {
734                 int broken, i;
735                 struct scatterlist *sg;
736
737                 broken = 0;
738                 if (host->flags & SDHCI_USE_ADMA) {
739                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
740                                 broken = 1;
741                 } else {
742                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
743                                 broken = 1;
744                 }
745
746                 if (unlikely(broken)) {
747                         for_each_sg(data->sg, sg, data->sg_len, i) {
748                                 if (sg->length & 0x3) {
749                                         DBG("Reverting to PIO because of "
750                                                 "transfer size (%d)\n",
751                                                 sg->length);
752                                         host->flags &= ~SDHCI_REQ_USE_DMA;
753                                         break;
754                                 }
755                         }
756                 }
757         }
758
759         /*
760          * The assumption here being that alignment is the same after
761          * translation to device address space.
762          */
763         if (host->flags & SDHCI_REQ_USE_DMA) {
764                 int broken, i;
765                 struct scatterlist *sg;
766
767                 broken = 0;
768                 if (host->flags & SDHCI_USE_ADMA) {
769                         /*
770                          * As we use 3 byte chunks to work around
771                          * alignment problems, we need to check this
772                          * quirk.
773                          */
774                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
775                                 broken = 1;
776                 } else {
777                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
778                                 broken = 1;
779                 }
780
781                 if (unlikely(broken)) {
782                         for_each_sg(data->sg, sg, data->sg_len, i) {
783                                 if (sg->offset & 0x3) {
784                                         DBG("Reverting to PIO because of "
785                                                 "bad alignment\n");
786                                         host->flags &= ~SDHCI_REQ_USE_DMA;
787                                         break;
788                                 }
789                         }
790                 }
791         }
792
793         if (host->flags & SDHCI_REQ_USE_DMA) {
794                 if (host->flags & SDHCI_USE_ADMA) {
795                         ret = sdhci_adma_table_pre(host, data);
796                         if (ret) {
797                                 /*
798                                  * This only happens when someone fed
799                                  * us an invalid request.
800                                  */
801                                 WARN_ON(1);
802                                 host->flags &= ~SDHCI_REQ_USE_DMA;
803                         } else {
804                                 sdhci_writel(host, host->adma_addr,
805                                         SDHCI_ADMA_ADDRESS);
806                         }
807                 } else {
808                         int sg_cnt;
809
810                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
811                                         data->sg, data->sg_len,
812                                         (data->flags & MMC_DATA_READ) ?
813                                                 DMA_FROM_DEVICE :
814                                                 DMA_TO_DEVICE);
815                         if (sg_cnt == 0) {
816                                 /*
817                                  * This only happens when someone fed
818                                  * us an invalid request.
819                                  */
820                                 WARN_ON(1);
821                                 host->flags &= ~SDHCI_REQ_USE_DMA;
822                         } else {
823                                 WARN_ON(sg_cnt != 1);
824                                 sdhci_writel(host, sg_dma_address(data->sg),
825                                         SDHCI_DMA_ADDRESS);
826                         }
827                 }
828         }
829
830         /*
831          * Always adjust the DMA selection as some controllers
832          * (e.g. JMicron) can't do PIO properly when the selection
833          * is ADMA.
834          */
835         if (host->version >= SDHCI_SPEC_200) {
836                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
837                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
838                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
839                         (host->flags & SDHCI_USE_ADMA))
840                         ctrl |= SDHCI_CTRL_ADMA32;
841                 else
842                         ctrl |= SDHCI_CTRL_SDMA;
843                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
844         }
845
846         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
847                 int flags;
848
849                 flags = SG_MITER_ATOMIC;
850                 if (host->data->flags & MMC_DATA_READ)
851                         flags |= SG_MITER_TO_SG;
852                 else
853                         flags |= SG_MITER_FROM_SG;
854                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
855                 host->blocks = data->blocks;
856         }
857
858         sdhci_set_transfer_irqs(host);
859
860         /* Set the DMA boundary value and block size */
861         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
862                 data->blksz), SDHCI_BLOCK_SIZE);
863         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
864 }
865
866 static void sdhci_set_transfer_mode(struct sdhci_host *host,
867         struct mmc_command *cmd)
868 {
869         u16 mode;
870         struct mmc_data *data = cmd->data;
871
872         if (data == NULL)
873                 return;
874
875         WARN_ON(!host->data);
876
877         mode = SDHCI_TRNS_BLK_CNT_EN;
878         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
879                 mode |= SDHCI_TRNS_MULTI;
880                 /*
881                  * If we are sending CMD23, CMD12 never gets sent
882                  * on successful completion (so no Auto-CMD12).
883                  */
884                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
885                         mode |= SDHCI_TRNS_AUTO_CMD12;
886                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
887                         mode |= SDHCI_TRNS_AUTO_CMD23;
888                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
889                 }
890         }
891
892         if (data->flags & MMC_DATA_READ)
893                 mode |= SDHCI_TRNS_READ;
894         if (host->flags & SDHCI_REQ_USE_DMA)
895                 mode |= SDHCI_TRNS_DMA;
896
897         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
898 }
899
900 static void sdhci_finish_data(struct sdhci_host *host)
901 {
902         struct mmc_data *data;
903
904         BUG_ON(!host->data);
905
906         data = host->data;
907         host->data = NULL;
908
909         if (host->flags & SDHCI_REQ_USE_DMA) {
910                 if (host->flags & SDHCI_USE_ADMA)
911                         sdhci_adma_table_post(host, data);
912                 else {
913                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
914                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
915                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
916                 }
917         }
918
919         /*
920          * The specification states that the block count register must
921          * be updated, but it does not specify at what point in the
922          * data flow. That makes the register entirely useless to read
923          * back so we have to assume that nothing made it to the card
924          * in the event of an error.
925          */
926         if (data->error)
927                 data->bytes_xfered = 0;
928         else
929                 data->bytes_xfered = data->blksz * data->blocks;
930
931         /*
932          * Need to send CMD12 if -
933          * a) open-ended multiblock transfer (no CMD23)
934          * b) error in multiblock transfer
935          */
936         if (data->stop &&
937             (data->error ||
938              !host->mrq->sbc)) {
939
940                 /*
941                  * The controller needs a reset of internal state machines
942                  * upon error conditions.
943                  */
944                 if (data->error) {
945                         sdhci_reset(host, SDHCI_RESET_CMD);
946                         sdhci_reset(host, SDHCI_RESET_DATA);
947                 }
948
949                 sdhci_send_command(host, data->stop);
950         } else
951                 tasklet_schedule(&host->finish_tasklet);
952 }
953
954 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
955 {
956         int flags;
957         u32 mask;
958         unsigned long timeout;
959
960         WARN_ON(host->cmd);
961
962         /* Wait max 10 ms */
963         timeout = 10;
964
965         mask = SDHCI_CMD_INHIBIT;
966         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
967                 mask |= SDHCI_DATA_INHIBIT;
968
969         /* We shouldn't wait for data inihibit for stop commands, even
970            though they might use busy signaling */
971         if (host->mrq->data && (cmd == host->mrq->data->stop))
972                 mask &= ~SDHCI_DATA_INHIBIT;
973
974         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
975                 if (timeout == 0) {
976                         pr_err("%s: Controller never released "
977                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
978                         sdhci_dumpregs(host);
979                         cmd->error = -EIO;
980                         tasklet_schedule(&host->finish_tasklet);
981                         return;
982                 }
983                 timeout--;
984                 mdelay(1);
985         }
986
987         mod_timer(&host->timer, jiffies + 10 * HZ);
988
989         host->cmd = cmd;
990
991         sdhci_prepare_data(host, cmd);
992
993         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
994
995         sdhci_set_transfer_mode(host, cmd);
996
997         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
998                 pr_err("%s: Unsupported response type!\n",
999                         mmc_hostname(host->mmc));
1000                 cmd->error = -EINVAL;
1001                 tasklet_schedule(&host->finish_tasklet);
1002                 return;
1003         }
1004
1005         if (!(cmd->flags & MMC_RSP_PRESENT))
1006                 flags = SDHCI_CMD_RESP_NONE;
1007         else if (cmd->flags & MMC_RSP_136)
1008                 flags = SDHCI_CMD_RESP_LONG;
1009         else if (cmd->flags & MMC_RSP_BUSY)
1010                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1011         else
1012                 flags = SDHCI_CMD_RESP_SHORT;
1013
1014         if (cmd->flags & MMC_RSP_CRC)
1015                 flags |= SDHCI_CMD_CRC;
1016         if (cmd->flags & MMC_RSP_OPCODE)
1017                 flags |= SDHCI_CMD_INDEX;
1018
1019         /* CMD19, CMD21 is special in that the Data Present Select should be set */
1020         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1021             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1022                 flags |= SDHCI_CMD_DATA;
1023
1024         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1025 }
1026
1027 static void sdhci_finish_command(struct sdhci_host *host)
1028 {
1029         int i;
1030
1031         BUG_ON(host->cmd == NULL);
1032
1033         if (host->cmd->flags & MMC_RSP_PRESENT) {
1034                 if (host->cmd->flags & MMC_RSP_136) {
1035                         /* CRC is stripped so we need to do some shifting. */
1036                         for (i = 0;i < 4;i++) {
1037                                 host->cmd->resp[i] = sdhci_readl(host,
1038                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1039                                 if (i != 3)
1040                                         host->cmd->resp[i] |=
1041                                                 sdhci_readb(host,
1042                                                 SDHCI_RESPONSE + (3-i)*4-1);
1043                         }
1044                 } else {
1045                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1046                 }
1047         }
1048
1049         host->cmd->error = 0;
1050
1051         /* Finished CMD23, now send actual command. */
1052         if (host->cmd == host->mrq->sbc) {
1053                 host->cmd = NULL;
1054                 sdhci_send_command(host, host->mrq->cmd);
1055         } else {
1056
1057                 /* Processed actual command. */
1058                 if (host->data && host->data_early)
1059                         sdhci_finish_data(host);
1060
1061                 if (!host->cmd->data)
1062                         tasklet_schedule(&host->finish_tasklet);
1063
1064                 host->cmd = NULL;
1065         }
1066 }
1067
1068 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1069 {
1070         int div = 0; /* Initialized for compiler warning */
1071         int real_div = div, clk_mul = 1;
1072         u16 clk = 0;
1073         unsigned long timeout;
1074
1075         if (clock && clock == host->clock)
1076                 return;
1077
1078         host->mmc->actual_clock = 0;
1079
1080         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1081                 return;
1082
1083         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1084
1085         if (clock == 0)
1086                 goto out;
1087
1088         if (host->version >= SDHCI_SPEC_300) {
1089                 /*
1090                  * Check if the Host Controller supports Programmable Clock
1091                  * Mode.
1092                  */
1093                 if (host->clk_mul) {
1094                         u16 ctrl;
1095
1096                         /*
1097                          * We need to figure out whether the Host Driver needs
1098                          * to select Programmable Clock Mode, or the value can
1099                          * be set automatically by the Host Controller based on
1100                          * the Preset Value registers.
1101                          */
1102                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1103                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1104                                 for (div = 1; div <= 1024; div++) {
1105                                         if (((host->max_clk * host->clk_mul) /
1106                                               div) <= clock)
1107                                                 break;
1108                                 }
1109                                 /*
1110                                  * Set Programmable Clock Mode in the Clock
1111                                  * Control register.
1112                                  */
1113                                 clk = SDHCI_PROG_CLOCK_MODE;
1114                                 real_div = div;
1115                                 clk_mul = host->clk_mul;
1116                                 div--;
1117                         }
1118                 } else {
1119                         /* Version 3.00 divisors must be a multiple of 2. */
1120                         if (host->max_clk <= clock)
1121                                 div = 1;
1122                         else {
1123                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1124                                      div += 2) {
1125                                         if ((host->max_clk / div) <= clock)
1126                                                 break;
1127                                 }
1128                         }
1129                         real_div = div;
1130                         div >>= 1;
1131                 }
1132         } else {
1133                 /* Version 2.00 divisors must be a power of 2. */
1134                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1135                         if ((host->max_clk / div) <= clock)
1136                                 break;
1137                 }
1138                 real_div = div;
1139                 div >>= 1;
1140         }
1141
1142         if (real_div)
1143                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1144
1145 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
1146         if(clock > 400000)
1147                 div = 1;
1148 #endif
1149         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1150         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1151                 << SDHCI_DIVIDER_HI_SHIFT;
1152         clk |= SDHCI_CLOCK_INT_EN;
1153         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1154
1155         /* Wait max 20 ms */
1156         timeout = 20;
1157         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1158                 & SDHCI_CLOCK_INT_STABLE)) {
1159                 if (timeout == 0) {
1160                         pr_err("%s: Internal clock never "
1161                                 "stabilised.\n", mmc_hostname(host->mmc));
1162                         sdhci_dumpregs(host);
1163                         return;
1164                 }
1165                 timeout--;
1166                 mdelay(1);
1167         }
1168
1169         clk |= SDHCI_CLOCK_CARD_EN;
1170         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1171
1172 out:
1173         host->clock = clock;
1174 }
1175
1176 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1177 {
1178         u8 pwr = 0;
1179
1180         if (power != (unsigned short)-1) {
1181                 switch (1 << power) {
1182                 case MMC_VDD_165_195:
1183                         pwr = SDHCI_POWER_180;
1184                         break;
1185                 case MMC_VDD_29_30:
1186                 case MMC_VDD_30_31:
1187                         pwr = SDHCI_POWER_300;
1188                         break;
1189                 case MMC_VDD_32_33:
1190                 case MMC_VDD_33_34:
1191                         pwr = SDHCI_POWER_330;
1192                         break;
1193                 default:
1194                         BUG();
1195                 }
1196         }
1197
1198         if (host->pwr == pwr)
1199                 return -1;
1200
1201         host->pwr = pwr;
1202
1203         if (pwr == 0) {
1204                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1205                 return 0;
1206         }
1207
1208         /*
1209          * Spec says that we should clear the power reg before setting
1210          * a new value. Some controllers don't seem to like this though.
1211          */
1212         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1213                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1214
1215         /*
1216          * At least the Marvell CaFe chip gets confused if we set the voltage
1217          * and set turn on power at the same time, so set the voltage first.
1218          */
1219         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1220                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1221
1222         pwr |= SDHCI_POWER_ON;
1223
1224         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1225
1226         /*
1227          * Some controllers need an extra 10ms delay of 10ms before they
1228          * can apply clock after applying power
1229          */
1230         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1231                 mdelay(10);
1232
1233         return power;
1234 }
1235
1236 /*****************************************************************************\
1237  *                                                                           *
1238  * MMC callbacks                                                             *
1239  *                                                                           *
1240 \*****************************************************************************/
1241
1242 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1243 {
1244         struct sdhci_host *host;
1245         bool present;
1246         unsigned long flags;
1247
1248         host = mmc_priv(mmc);
1249
1250         sdhci_runtime_pm_get(host);
1251
1252         spin_lock_irqsave(&host->lock, flags);
1253
1254         WARN_ON(host->mrq != NULL);
1255
1256 #ifndef SDHCI_USE_LEDS_CLASS
1257         sdhci_activate_led(host);
1258 #endif
1259
1260         /*
1261          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1262          * requests if Auto-CMD12 is enabled.
1263          */
1264         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1265                 if (mrq->stop) {
1266                         mrq->data->stop = NULL;
1267                         mrq->stop = NULL;
1268                 }
1269         }
1270
1271         host->mrq = mrq;
1272
1273         /* If polling, assume that the card is always present. */
1274         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
1275                 if (host->ops->get_cd)
1276                         present = host->ops->get_cd(host);
1277                 else
1278                         present = true;
1279         } else {
1280                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1281                                 SDHCI_CARD_PRESENT;
1282         }
1283
1284         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1285                 host->mrq->cmd->error = -ENOMEDIUM;
1286                 tasklet_schedule(&host->finish_tasklet);
1287         } else {
1288                 u32 present_state;
1289
1290                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1291                 /*
1292                  * Check if the re-tuning timer has already expired and there
1293                  * is no on-going data transfer. If so, we need to execute
1294                  * tuning procedure before sending command.
1295                  */
1296                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1297                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1298                         spin_unlock_irqrestore(&host->lock, flags);
1299                         sdhci_execute_tuning(mmc, mrq->cmd->opcode);
1300                         spin_lock_irqsave(&host->lock, flags);
1301
1302                         /* Restore original mmc_request structure */
1303                         host->mrq = mrq;
1304                 }
1305
1306                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1307                         sdhci_send_command(host, mrq->sbc);
1308                 else
1309                         sdhci_send_command(host, mrq->cmd);
1310         }
1311
1312         mmiowb();
1313         spin_unlock_irqrestore(&host->lock, flags);
1314 }
1315
1316 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1317 {
1318         unsigned long flags;
1319         int vdd_bit = -1;
1320         u8 ctrl;
1321
1322         /*
1323          * Controller registers should not be updated without the
1324          * controller clock enabled. Set the minimum controller
1325          * clock if there is no clock.
1326          */
1327         if (host->ops->set_clock) {
1328                 if (!host->clock && !ios->clock) {
1329                         host->ops->set_clock(host, host->mmc->f_min);
1330                         host->clock = host->mmc->f_min;
1331                 } else if (ios->clock && (ios->clock != host->clock)) {
1332                         host->ops->set_clock(host, ios->clock);
1333                 }
1334         }
1335
1336         spin_lock_irqsave(&host->lock, flags);
1337
1338         if (host->flags & SDHCI_DEVICE_DEAD) {
1339                 spin_unlock_irqrestore(&host->lock, flags);
1340                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1341                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1342                 return;
1343         }
1344
1345         /*
1346          * Reset the chip on each power off.
1347          * Should clear out any weird states.
1348          */
1349         if (ios->power_mode == MMC_POWER_OFF) {
1350                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1351                 sdhci_reinit(host);
1352         }
1353
1354         if (ios->power_mode == MMC_POWER_OFF)
1355                 vdd_bit = sdhci_set_power(host, -1);
1356         else
1357                 vdd_bit = sdhci_set_power(host, ios->vdd);
1358
1359         if (host->vmmc && vdd_bit != -1) {
1360                 spin_unlock_irqrestore(&host->lock, flags);
1361                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1362                 spin_lock_irqsave(&host->lock, flags);
1363         }
1364
1365         sdhci_set_clock(host, ios->clock);
1366
1367         if (host->ops->platform_send_init_74_clocks)
1368                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1369
1370         /*
1371          * If your platform has 8-bit width support but is not a v3 controller,
1372          * or if it requires special setup code, you should implement that in
1373          * platform_8bit_width().
1374          */
1375         if (host->ops->platform_8bit_width)
1376                 host->ops->platform_8bit_width(host, ios->bus_width);
1377         else {
1378                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1379                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1380                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1381                         if (host->version >= SDHCI_SPEC_300)
1382                                 ctrl |= SDHCI_CTRL_8BITBUS;
1383                 } else {
1384                         if (host->version >= SDHCI_SPEC_300)
1385                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1386                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1387                                 ctrl |= SDHCI_CTRL_4BITBUS;
1388                         else
1389                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1390                 }
1391                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1392         }
1393
1394         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1395
1396         if ((ios->timing == MMC_TIMING_SD_HS ||
1397              ios->timing == MMC_TIMING_MMC_HS)
1398             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1399                 ctrl |= SDHCI_CTRL_HISPD;
1400         else
1401                 ctrl &= ~SDHCI_CTRL_HISPD;
1402
1403         if (host->version >= SDHCI_SPEC_300) {
1404                 u16 clk, ctrl_2;
1405
1406                 /* In case of UHS-I modes, set High Speed Enable */
1407                 if (((ios->timing == MMC_TIMING_MMC_HS200) ||
1408                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1409                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1410                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1411                     (ios->timing == MMC_TIMING_UHS_SDR25))
1412                     && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1413                         ctrl |= SDHCI_CTRL_HISPD;
1414
1415                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1416                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1417                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1418                         /*
1419                          * We only need to set Driver Strength if the
1420                          * preset value enable is not set.
1421                          */
1422                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1423                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1424                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1425                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1426                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1427
1428                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1429                 } else {
1430                         /*
1431                          * According to SDHC Spec v3.00, if the Preset Value
1432                          * Enable in the Host Control 2 register is set, we
1433                          * need to reset SD Clock Enable before changing High
1434                          * Speed Enable to avoid generating clock gliches.
1435                          */
1436
1437                         /* Reset SD Clock Enable */
1438                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1439                         clk &= ~SDHCI_CLOCK_CARD_EN;
1440                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1441
1442                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1443
1444                         /* Re-enable SD Clock */
1445                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1446                         clk |= SDHCI_CLOCK_CARD_EN;
1447                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1448                 }
1449
1450
1451                 /* Reset SD Clock Enable */
1452                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1453                 clk &= ~SDHCI_CLOCK_CARD_EN;
1454                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1455
1456                 if (host->ops->set_uhs_signaling)
1457                         host->ops->set_uhs_signaling(host, ios->timing);
1458                 else {
1459                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1460                         /* Select Bus Speed Mode for host */
1461                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1462                         if (ios->timing == MMC_TIMING_MMC_HS200)
1463                                 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1464                         else if (ios->timing == MMC_TIMING_UHS_SDR12)
1465                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1466                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1467                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1468                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1469                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1470                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1471                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1472                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1473                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1474                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1475                 }
1476
1477                 /* Re-enable SD Clock */
1478                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1479                 clk |= SDHCI_CLOCK_CARD_EN;
1480                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1481         } else
1482                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1483
1484         /*
1485          * Some (ENE) controllers go apeshit on some ios operation,
1486          * signalling timeout and CRC errors even on CMD0. Resetting
1487          * it on each ios seems to solve the problem.
1488          */
1489         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1490                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1491
1492         mmiowb();
1493         spin_unlock_irqrestore(&host->lock, flags);
1494         /*
1495          * Controller clock should only be disabled after all the register
1496          * writes are done.
1497          */
1498         if (!ios->clock && host->ops->set_clock)
1499                 host->ops->set_clock(host, ios->clock);
1500 }
1501
1502 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1503 {
1504         struct sdhci_host *host = mmc_priv(mmc);
1505
1506         sdhci_runtime_pm_get(host);
1507         sdhci_do_set_ios(host, ios);
1508         sdhci_runtime_pm_put(host);
1509 }
1510
1511 static int sdhci_check_ro(struct sdhci_host *host)
1512 {
1513         unsigned long flags;
1514         int is_readonly;
1515
1516         spin_lock_irqsave(&host->lock, flags);
1517
1518         if (host->flags & SDHCI_DEVICE_DEAD)
1519                 is_readonly = 0;
1520         else if (host->ops->get_ro)
1521                 is_readonly = host->ops->get_ro(host);
1522         else
1523                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1524                                 & SDHCI_WRITE_PROTECT);
1525
1526         spin_unlock_irqrestore(&host->lock, flags);
1527
1528         /* This quirk needs to be replaced by a callback-function later */
1529         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1530                 !is_readonly : is_readonly;
1531 }
1532
1533 #define SAMPLE_COUNT    5
1534
1535 static int sdhci_do_get_ro(struct sdhci_host *host)
1536 {
1537         int i, ro_count;
1538
1539         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1540                 return sdhci_check_ro(host);
1541
1542         ro_count = 0;
1543         for (i = 0; i < SAMPLE_COUNT; i++) {
1544                 if (sdhci_check_ro(host)) {
1545                         if (++ro_count > SAMPLE_COUNT / 2)
1546                                 return 1;
1547                 }
1548                 msleep(30);
1549         }
1550         return 0;
1551 }
1552
1553 static void sdhci_hw_reset(struct mmc_host *mmc)
1554 {
1555         struct sdhci_host *host = mmc_priv(mmc);
1556
1557         if (host->ops && host->ops->hw_reset)
1558                 host->ops->hw_reset(host);
1559 }
1560
1561 static int sdhci_get_ro(struct mmc_host *mmc)
1562 {
1563         struct sdhci_host *host = mmc_priv(mmc);
1564         int ret;
1565
1566         sdhci_runtime_pm_get(host);
1567         ret = sdhci_do_get_ro(host);
1568         sdhci_runtime_pm_put(host);
1569         return ret;
1570 }
1571
1572 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1573 {
1574         if (host->flags & SDHCI_DEVICE_DEAD)
1575                 goto out;
1576
1577         if (enable)
1578                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1579         else
1580                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1581
1582         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1583         if (host->runtime_suspended)
1584                 goto out;
1585
1586         if (enable)
1587                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1588         else
1589                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1590 out:
1591         mmiowb();
1592 }
1593
1594 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1595 {
1596         struct sdhci_host *host = mmc_priv(mmc);
1597         unsigned long flags;
1598
1599         spin_lock_irqsave(&host->lock, flags);
1600         sdhci_enable_sdio_irq_nolock(host, enable);
1601         spin_unlock_irqrestore(&host->lock, flags);
1602 }
1603
1604 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1605                                                 struct mmc_ios *ios)
1606 {
1607         u8 pwr;
1608         u16 clk, ctrl;
1609         u32 present_state;
1610
1611         /*
1612          * Signal Voltage Switching is only applicable for Host Controllers
1613          * v3.00 and above.
1614          */
1615         if (host->version < SDHCI_SPEC_300)
1616                 return 0;
1617
1618         if (host->quirks & SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING) {
1619                 if (host->ops->switch_signal_voltage)
1620                         return host->ops->switch_signal_voltage(
1621                                 host, ios->signal_voltage);
1622         }
1623
1624         /*
1625          * We first check whether the request is to set signalling voltage
1626          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1627          */
1628         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1629         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1630                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1631                 ctrl &= ~SDHCI_CTRL_VDD_180;
1632                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1633
1634                 /* Wait for 5ms */
1635                 usleep_range(5000, 5500);
1636
1637                 /* 3.3V regulator output should be stable within 5 ms */
1638                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1639                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1640                         return 0;
1641                 else {
1642                         pr_info(DRIVER_NAME ": Switching to 3.3V "
1643                                 "signalling voltage failed\n");
1644                         return -EIO;
1645                 }
1646         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1647                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1648                 /* Stop SDCLK */
1649                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1650                 clk &= ~SDHCI_CLOCK_CARD_EN;
1651                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1652
1653                 /* Check whether DAT[3:0] is 0000 */
1654                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1655                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1656                        SDHCI_DATA_LVL_SHIFT)) {
1657                         /*
1658                          * Enable 1.8V Signal Enable in the Host Control2
1659                          * register
1660                          */
1661                         ctrl |= SDHCI_CTRL_VDD_180;
1662                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1663
1664                         /* Wait for 5ms */
1665                         usleep_range(5000, 5500);
1666                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1667                         if (ctrl & SDHCI_CTRL_VDD_180) {
1668                                 /* Provide SDCLK again and wait for 1ms*/
1669                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1670                                 clk |= SDHCI_CLOCK_CARD_EN;
1671                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1672                                 usleep_range(1000, 1500);
1673
1674                                 /*
1675                                  * If DAT[3:0] level is 1111b, then the card
1676                                  * was successfully switched to 1.8V signaling.
1677                                  */
1678                                 present_state = sdhci_readl(host,
1679                                                         SDHCI_PRESENT_STATE);
1680                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1681                                      SDHCI_DATA_LVL_MASK)
1682                                         return 0;
1683                         }
1684                 }
1685
1686                 /*
1687                  * If we are here, that means the switch to 1.8V signaling
1688                  * failed. We power cycle the card, and retry initialization
1689                  * sequence by setting S18R to 0.
1690                  */
1691                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1692                 pwr &= ~SDHCI_POWER_ON;
1693                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1694
1695                 /* Wait for 1ms as per the spec */
1696                 usleep_range(1000, 1500);
1697                 pwr |= SDHCI_POWER_ON;
1698                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1699
1700                 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1701                         "voltage failed, retrying with S18R set to 0\n");
1702                 return -EAGAIN;
1703         } else
1704                 /* No signal voltage switch required */
1705                 return 0;
1706 }
1707
1708 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1709         struct mmc_ios *ios)
1710 {
1711         struct sdhci_host *host = mmc_priv(mmc);
1712         int err;
1713
1714         if (host->version < SDHCI_SPEC_300)
1715                 return 0;
1716         sdhci_runtime_pm_get(host);
1717         err = sdhci_do_start_signal_voltage_switch(host, ios);
1718         sdhci_runtime_pm_put(host);
1719         return err;
1720 }
1721
1722 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1723 {
1724         struct sdhci_host *host;
1725         u16 ctrl;
1726         u32 ier;
1727         int tuning_loop_counter = MAX_TUNING_LOOP;
1728         unsigned long timeout;
1729         int err = 0;
1730         bool requires_tuning_nonuhs = false;
1731
1732         host = mmc_priv(mmc);
1733
1734         sdhci_runtime_pm_get(host);
1735         disable_irq(host->irq);
1736         spin_lock(&host->lock);
1737
1738         if ((host->quirks & SDHCI_QUIRK_NON_STANDARD_TUNING) &&
1739                 host->ops->execute_freq_tuning) {
1740                 err = host->ops->execute_freq_tuning(host, opcode);
1741                 spin_unlock(&host->lock);
1742                 enable_irq(host->irq);
1743                 return err;
1744         }
1745
1746         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1747
1748         /*
1749          * The Host Controller needs tuning only in case of SDR104 mode
1750          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1751          * Capabilities register.
1752          * If the Host Controller supports the HS200 mode then the
1753          * tuning function has to be executed.
1754          */
1755         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1756             (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1757              host->flags & SDHCI_HS200_NEEDS_TUNING))
1758                 requires_tuning_nonuhs = true;
1759
1760         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1761             requires_tuning_nonuhs)
1762                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1763         else {
1764                 spin_unlock(&host->lock);
1765                 enable_irq(host->irq);
1766                 sdhci_runtime_pm_put(host);
1767                 return 0;
1768         }
1769
1770         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1771
1772         /*
1773          * As per the Host Controller spec v3.00, tuning command
1774          * generates Buffer Read Ready interrupt, so enable that.
1775          *
1776          * Note: The spec clearly says that when tuning sequence
1777          * is being performed, the controller does not generate
1778          * interrupts other than Buffer Read Ready interrupt. But
1779          * to make sure we don't hit a controller bug, we _only_
1780          * enable Buffer Read Ready interrupt here.
1781          */
1782         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1783         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1784
1785         /*
1786          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1787          * of loops reaches 40 times or a timeout of 150ms occurs.
1788          */
1789         timeout = 150;
1790         do {
1791                 struct mmc_command cmd = {0};
1792                 struct mmc_request mrq = {NULL};
1793
1794                 if (!tuning_loop_counter && !timeout)
1795                         break;
1796
1797                 cmd.opcode = opcode;
1798                 cmd.arg = 0;
1799                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1800                 cmd.retries = 0;
1801                 cmd.data = NULL;
1802                 cmd.error = 0;
1803
1804                 mrq.cmd = &cmd;
1805                 host->mrq = &mrq;
1806
1807                 /*
1808                  * In response to CMD19, the card sends 64 bytes of tuning
1809                  * block to the Host Controller. So we set the block size
1810                  * to 64 here.
1811                  * In response to CMD21, the card sends 128 bytes of tuning
1812                  * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
1813                  * to the Host Controller. So we set the block size to 64 here.
1814                  */
1815                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1816                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1817                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1818                                              SDHCI_BLOCK_SIZE);
1819                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1820                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1821                                              SDHCI_BLOCK_SIZE);
1822                 } else {
1823                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1824                                      SDHCI_BLOCK_SIZE);
1825                 }
1826
1827                 /*
1828                  * The tuning block is sent by the card to the host controller.
1829                  * So we set the TRNS_READ bit in the Transfer Mode register.
1830                  * This also takes care of setting DMA Enable and Multi Block
1831                  * Select in the same register to 0.
1832                  */
1833                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1834
1835                 sdhci_send_command(host, &cmd);
1836
1837                 host->cmd = NULL;
1838                 host->mrq = NULL;
1839
1840                 spin_unlock(&host->lock);
1841                 enable_irq(host->irq);
1842
1843                 /* Wait for Buffer Read Ready interrupt */
1844                 wait_event_interruptible_timeout(host->buf_ready_int,
1845                                         (host->tuning_done == 1),
1846                                         msecs_to_jiffies(50));
1847                 disable_irq(host->irq);
1848                 spin_lock(&host->lock);
1849
1850                 if (!host->tuning_done) {
1851                         pr_info(DRIVER_NAME ": Timeout waiting for "
1852                                 "Buffer Read Ready interrupt during tuning "
1853                                 "procedure, falling back to fixed sampling "
1854                                 "clock\n");
1855                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1856                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1857                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1858                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1859
1860                         err = -EIO;
1861                         goto out;
1862                 }
1863
1864                 host->tuning_done = 0;
1865
1866                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1867                 tuning_loop_counter--;
1868                 timeout--;
1869                 mdelay(1);
1870         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1871
1872         /*
1873          * The Host Driver has exhausted the maximum number of loops allowed,
1874          * so use fixed sampling frequency.
1875          */
1876         if (!tuning_loop_counter || !timeout) {
1877                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1878                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1879         } else {
1880                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1881                         pr_info(DRIVER_NAME ": Tuning procedure"
1882                                 " failed, falling back to fixed sampling"
1883                                 " clock\n");
1884                         err = -EIO;
1885                 }
1886         }
1887
1888 out:
1889         /*
1890          * If this is the very first time we are here, we start the retuning
1891          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1892          * flag won't be set, we check this condition before actually starting
1893          * the timer.
1894          */
1895         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1896             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1897                 mod_timer(&host->tuning_timer, jiffies +
1898                         host->tuning_count * HZ);
1899                 /* Tuning mode 1 limits the maximum data length to 4MB */
1900                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1901         } else {
1902                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1903                 /* Reload the new initial value for timer */
1904                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1905                         mod_timer(&host->tuning_timer, jiffies +
1906                                 host->tuning_count * HZ);
1907         }
1908
1909         /*
1910          * In case tuning fails, host controllers which support re-tuning can
1911          * try tuning again at a later time, when the re-tuning timer expires.
1912          * So for these controllers, we return 0. Since there might be other
1913          * controllers who do not have this capability, we return error for
1914          * them.
1915          */
1916         if (err && host->tuning_count &&
1917             host->tuning_mode == SDHCI_TUNING_MODE_1)
1918                 err = 0;
1919
1920         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1921         spin_unlock(&host->lock);
1922         enable_irq(host->irq);
1923         sdhci_runtime_pm_put(host);
1924
1925         return err;
1926 }
1927
1928 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1929 {
1930         u16 ctrl;
1931         unsigned long flags;
1932
1933         /* Host Controller v3.00 defines preset value registers */
1934         if (host->version < SDHCI_SPEC_300)
1935                 return;
1936
1937         /*
1938          * Enabling preset value would make programming clock
1939          * divider ineffective. The controller would use the
1940          * values present in the preset value registers. In
1941          * case of non-standard clock, let the platform driver
1942          * decide whether to enable preset or not.
1943          */
1944         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1945                 return;
1946
1947         spin_lock_irqsave(&host->lock, flags);
1948
1949         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1950
1951         /*
1952          * We only enable or disable Preset Value if they are not already
1953          * enabled or disabled respectively. Otherwise, we bail out.
1954          */
1955         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1956                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1957                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1958                 host->flags |= SDHCI_PV_ENABLED;
1959         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1960                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1961                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1962                 host->flags &= ~SDHCI_PV_ENABLED;
1963         }
1964
1965         spin_unlock_irqrestore(&host->lock, flags);
1966 }
1967
1968 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1969 {
1970         struct sdhci_host *host = mmc_priv(mmc);
1971
1972         sdhci_runtime_pm_get(host);
1973         sdhci_do_enable_preset_value(host, enable);
1974         sdhci_runtime_pm_put(host);
1975 }
1976
1977 int sdhci_enable(struct mmc_host *mmc)
1978 {
1979         struct sdhci_host *host = mmc_priv(mmc);
1980         u16 clk;
1981
1982         if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO)
1983                 return 0;
1984
1985         if (mmc->ios.clock) {
1986                 if (host->ops->set_clock)
1987                         host->ops->set_clock(host, mmc->ios.clock);
1988                 sdhci_set_clock(host, mmc->ios.clock);
1989         }
1990
1991         return 0;
1992 }
1993
1994 int sdhci_disable(struct mmc_host *mmc, int lazy)
1995 {
1996         struct sdhci_host *host = mmc_priv(mmc);
1997         u16 clk;
1998
1999         if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO)
2000                 return 0;
2001
2002         sdhci_set_clock(host, 0);
2003         if (host->ops->set_clock)
2004                 host->ops->set_clock(host, 0);
2005
2006         return 0;
2007 }
2008
2009 static const struct mmc_host_ops sdhci_ops = {
2010         .request        = sdhci_request,
2011         .set_ios        = sdhci_set_ios,
2012         .get_ro         = sdhci_get_ro,
2013         .hw_reset       = sdhci_hw_reset,
2014         .enable         = sdhci_enable,
2015         .disable        = sdhci_disable,
2016         .enable_sdio_irq = sdhci_enable_sdio_irq,
2017         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2018         .execute_tuning                 = sdhci_execute_tuning,
2019         .enable_preset_value            = sdhci_enable_preset_value,
2020 };
2021
2022 /*****************************************************************************\
2023  *                                                                           *
2024  * Tasklets                                                                  *
2025  *                                                                           *
2026 \*****************************************************************************/
2027
2028 static void sdhci_tasklet_card(unsigned long param)
2029 {
2030         struct sdhci_host *host;
2031         unsigned long flags;
2032
2033         host = (struct sdhci_host*)param;
2034
2035         spin_lock_irqsave(&host->lock, flags);
2036
2037         /* Check host->mrq first in case we are runtime suspended */
2038         if (host->mrq &&
2039             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2040                 pr_err("%s: Card removed during transfer!\n",
2041                         mmc_hostname(host->mmc));
2042                 pr_err("%s: Resetting controller.\n",
2043                         mmc_hostname(host->mmc));
2044
2045                 sdhci_reset(host, SDHCI_RESET_CMD);
2046                 sdhci_reset(host, SDHCI_RESET_DATA);
2047
2048                 host->mrq->cmd->error = -ENOMEDIUM;
2049                 tasklet_schedule(&host->finish_tasklet);
2050         }
2051
2052         spin_unlock_irqrestore(&host->lock, flags);
2053
2054         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2055 }
2056
2057 static void sdhci_tasklet_finish(unsigned long param)
2058 {
2059         struct sdhci_host *host;
2060         unsigned long flags;
2061         struct mmc_request *mrq;
2062
2063         host = (struct sdhci_host*)param;
2064
2065         spin_lock_irqsave(&host->lock, flags);
2066
2067         /*
2068          * If this tasklet gets rescheduled while running, it will
2069          * be run again afterwards but without any active request.
2070          */
2071         if (!host->mrq) {
2072                 spin_unlock_irqrestore(&host->lock, flags);
2073                 return;
2074         }
2075
2076         del_timer(&host->timer);
2077
2078         mrq = host->mrq;
2079
2080         /*
2081          * The controller needs a reset of internal state machines
2082          * upon error conditions.
2083          */
2084         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2085             ((mrq->cmd && mrq->cmd->error) ||
2086                  (mrq->data && (mrq->data->error ||
2087                   (mrq->data->stop && mrq->data->stop->error))) ||
2088                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2089
2090                 /* Some controllers need this kick or reset won't work here */
2091                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2092                         unsigned int clock;
2093
2094                         /* This is to force an update */
2095                         clock = host->clock;
2096                         host->clock = 0;
2097                         if (host->ops->set_clock)
2098                                 host->ops->set_clock(host, clock);
2099                         sdhci_set_clock(host, clock);
2100                 }
2101
2102                 /* Spec says we should do both at the same time, but Ricoh
2103                    controllers do not like that. */
2104                 sdhci_reset(host, SDHCI_RESET_CMD);
2105                 sdhci_reset(host, SDHCI_RESET_DATA);
2106         }
2107
2108         host->mrq = NULL;
2109         host->cmd = NULL;
2110         host->data = NULL;
2111
2112 #ifndef SDHCI_USE_LEDS_CLASS
2113         sdhci_deactivate_led(host);
2114 #endif
2115
2116         mmiowb();
2117         spin_unlock_irqrestore(&host->lock, flags);
2118
2119         mmc_request_done(host->mmc, mrq);
2120         sdhci_runtime_pm_put(host);
2121 }
2122
2123 static void sdhci_timeout_timer(unsigned long data)
2124 {
2125         struct sdhci_host *host;
2126         unsigned long flags;
2127
2128         host = (struct sdhci_host*)data;
2129
2130         spin_lock_irqsave(&host->lock, flags);
2131
2132         if (host->mrq) {
2133                 pr_err("%s: Timeout waiting for hardware "
2134                         "interrupt.\n", mmc_hostname(host->mmc));
2135                 sdhci_dumpregs(host);
2136
2137                 if (host->data) {
2138                         host->data->error = -ETIMEDOUT;
2139                         sdhci_finish_data(host);
2140                 } else {
2141                         if (host->cmd)
2142                                 host->cmd->error = -ETIMEDOUT;
2143                         else
2144                                 host->mrq->cmd->error = -ETIMEDOUT;
2145
2146                         tasklet_schedule(&host->finish_tasklet);
2147                 }
2148         }
2149
2150         mmiowb();
2151         spin_unlock_irqrestore(&host->lock, flags);
2152 }
2153
2154 static void sdhci_tuning_timer(unsigned long data)
2155 {
2156         struct sdhci_host *host;
2157         unsigned long flags;
2158
2159         host = (struct sdhci_host *)data;
2160
2161         spin_lock_irqsave(&host->lock, flags);
2162
2163         host->flags |= SDHCI_NEEDS_RETUNING;
2164
2165         spin_unlock_irqrestore(&host->lock, flags);
2166 }
2167
2168 /*****************************************************************************\
2169  *                                                                           *
2170  * Interrupt handling                                                        *
2171  *                                                                           *
2172 \*****************************************************************************/
2173
2174 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2175 {
2176         BUG_ON(intmask == 0);
2177
2178         if (!host->cmd) {
2179                 pr_err("%s: Got command interrupt 0x%08x even "
2180                         "though no command operation was in progress.\n",
2181                         mmc_hostname(host->mmc), (unsigned)intmask);
2182                 sdhci_dumpregs(host);
2183                 return;
2184         }
2185
2186         if (intmask & SDHCI_INT_TIMEOUT)
2187                 host->cmd->error = -ETIMEDOUT;
2188         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2189                         SDHCI_INT_INDEX))
2190                 host->cmd->error = -EILSEQ;
2191
2192         if (host->cmd->error) {
2193                 tasklet_schedule(&host->finish_tasklet);
2194                 return;
2195         }
2196
2197         /*
2198          * The host can send and interrupt when the busy state has
2199          * ended, allowing us to wait without wasting CPU cycles.
2200          * Unfortunately this is overloaded on the "data complete"
2201          * interrupt, so we need to take some care when handling
2202          * it.
2203          *
2204          * Note: The 1.0 specification is a bit ambiguous about this
2205          *       feature so there might be some problems with older
2206          *       controllers.
2207          */
2208         if (host->cmd->flags & MMC_RSP_BUSY) {
2209                 if (host->cmd->data)
2210                         DBG("Cannot wait for busy signal when also "
2211                                 "doing a data transfer");
2212                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2213                         return;
2214
2215                 /* The controller does not support the end-of-busy IRQ,
2216                  * fall through and take the SDHCI_INT_RESPONSE */
2217         }
2218
2219         if (intmask & SDHCI_INT_RESPONSE)
2220                 sdhci_finish_command(host);
2221 }
2222
2223 #ifdef CONFIG_MMC_DEBUG
2224 static void sdhci_show_adma_error(struct sdhci_host *host)
2225 {
2226         const char *name = mmc_hostname(host->mmc);
2227         u8 *desc = host->adma_desc;
2228         __le32 *dma;
2229         __le16 *len;
2230         u8 attr;
2231
2232         sdhci_dumpregs(host);
2233
2234         while (true) {
2235                 dma = (__le32 *)(desc + 4);
2236                 len = (__le16 *)(desc + 2);
2237                 attr = *desc;
2238
2239                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2240                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2241
2242                 desc += 8;
2243
2244                 if (attr & 2)
2245                         break;
2246         }
2247 }
2248 #else
2249 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2250 #endif
2251
2252 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2253 {
2254         u32 command;
2255         BUG_ON(intmask == 0);
2256
2257         /* CMD19, CMD21 generates _only_ Buffer Read Ready interrupt */
2258         if (intmask & SDHCI_INT_DATA_AVAIL) {
2259                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2260                 if (command == MMC_SEND_TUNING_BLOCK ||
2261                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2262                         host->tuning_done = 1;
2263                         wake_up(&host->buf_ready_int);
2264                         return;
2265                 }
2266         }
2267
2268         if (!host->data) {
2269                 /*
2270                  * The "data complete" interrupt is also used to
2271                  * indicate that a busy state has ended. See comment
2272                  * above in sdhci_cmd_irq().
2273                  */
2274                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2275                         if (intmask & SDHCI_INT_DATA_END) {
2276                                 sdhci_finish_command(host);
2277                                 return;
2278                         }
2279                 }
2280
2281                 pr_err("%s: Got data interrupt 0x%08x even "
2282                         "though no data operation was in progress.\n",
2283                         mmc_hostname(host->mmc), (unsigned)intmask);
2284                 sdhci_dumpregs(host);
2285
2286                 return;
2287         }
2288
2289         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2290                 host->data->error = -ETIMEDOUT;
2291         else if (intmask & SDHCI_INT_DATA_END_BIT)
2292                 host->data->error = -EILSEQ;
2293         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2294                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2295                         != MMC_BUS_TEST_R)
2296                 host->data->error = -EILSEQ;
2297         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2298                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2299                 sdhci_show_adma_error(host);
2300                 host->data->error = -EIO;
2301         }
2302
2303         if (host->data->error)
2304                 sdhci_finish_data(host);
2305         else {
2306                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2307                         sdhci_transfer_pio(host);
2308
2309                 /*
2310                  * We currently don't do anything fancy with DMA
2311                  * boundaries, but as we can't disable the feature
2312                  * we need to at least restart the transfer.
2313                  *
2314                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2315                  * should return a valid address to continue from, but as
2316                  * some controllers are faulty, don't trust them.
2317                  */
2318                 if (intmask & SDHCI_INT_DMA_END) {
2319                         u32 dmastart, dmanow;
2320                         dmastart = sg_dma_address(host->data->sg);
2321                         dmanow = dmastart + host->data->bytes_xfered;
2322                         /*
2323                          * Force update to the next DMA block boundary.
2324                          */
2325                         dmanow = (dmanow &
2326                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2327                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2328                         host->data->bytes_xfered = dmanow - dmastart;
2329                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2330                                 " next 0x%08x\n",
2331                                 mmc_hostname(host->mmc), dmastart,
2332                                 host->data->bytes_xfered, dmanow);
2333                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2334                 }
2335
2336                 if (intmask & SDHCI_INT_DATA_END) {
2337                         if (host->cmd) {
2338                                 /*
2339                                  * Data managed to finish before the
2340                                  * command completed. Make sure we do
2341                                  * things in the proper order.
2342                                  */
2343                                 host->data_early = 1;
2344                         } else {
2345                                 sdhci_finish_data(host);
2346                         }
2347                 }
2348         }
2349 }
2350
2351 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2352 {
2353         irqreturn_t result;
2354         struct sdhci_host *host = dev_id;
2355         u32 intmask, unexpected = 0;
2356         int cardint = 0, max_loops = 16;
2357
2358         spin_lock(&host->lock);
2359
2360         if (host->runtime_suspended) {
2361                 spin_unlock(&host->lock);
2362                 pr_warning("%s: got irq while runtime suspended\n",
2363                        mmc_hostname(host->mmc));
2364                 return IRQ_HANDLED;
2365         }
2366
2367         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2368
2369         if (!intmask || intmask == 0xffffffff) {
2370                 result = IRQ_NONE;
2371                 goto out;
2372         }
2373
2374 again:
2375         DBG("*** %s got interrupt: 0x%08x\n",
2376                 mmc_hostname(host->mmc), intmask);
2377
2378         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2379                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2380                               SDHCI_CARD_PRESENT;
2381
2382                 /*
2383                  * There is a observation on i.mx esdhc.  INSERT bit will be
2384                  * immediately set again when it gets cleared, if a card is
2385                  * inserted.  We have to mask the irq to prevent interrupt
2386                  * storm which will freeze the system.  And the REMOVE gets
2387                  * the same situation.
2388                  *
2389                  * More testing are needed here to ensure it works for other
2390                  * platforms though.
2391                  */
2392                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2393                                                 SDHCI_INT_CARD_REMOVE);
2394                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2395                                                   SDHCI_INT_CARD_INSERT);
2396
2397                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2398                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2399                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2400                 tasklet_schedule(&host->card_tasklet);
2401         }
2402
2403         if (intmask & SDHCI_INT_CMD_MASK) {
2404                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2405                         SDHCI_INT_STATUS);
2406                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2407         }
2408
2409         if (intmask & SDHCI_INT_DATA_MASK) {
2410                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2411                         SDHCI_INT_STATUS);
2412                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2413         }
2414
2415         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2416
2417         intmask &= ~SDHCI_INT_ERROR;
2418
2419         if (intmask & SDHCI_INT_BUS_POWER) {
2420                 pr_err("%s: Card is consuming too much power!\n",
2421                         mmc_hostname(host->mmc));
2422                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2423         }
2424
2425         intmask &= ~SDHCI_INT_BUS_POWER;
2426
2427         if (intmask & SDHCI_INT_CARD_INT)
2428                 cardint = 1;
2429
2430         intmask &= ~SDHCI_INT_CARD_INT;
2431
2432         if (intmask) {
2433                 unexpected |= intmask;
2434                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2435         }
2436
2437         result = IRQ_HANDLED;
2438
2439         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2440         if (intmask && --max_loops)
2441                 goto again;
2442 out:
2443         spin_unlock(&host->lock);
2444
2445         if (unexpected) {
2446                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2447                            mmc_hostname(host->mmc), unexpected);
2448                 sdhci_dumpregs(host);
2449         }
2450         /*
2451          * We have to delay this as it calls back into the driver.
2452          */
2453         if (cardint)
2454                 mmc_signal_sdio_irq(host->mmc);
2455
2456         return result;
2457 }
2458
2459 /*****************************************************************************\
2460  *                                                                           *
2461  * Suspend/resume                                                            *
2462  *                                                                           *
2463 \*****************************************************************************/
2464
2465 #ifdef CONFIG_PM
2466
2467 int sdhci_suspend_host(struct sdhci_host *host)
2468 {
2469         int ret = 0;
2470         bool has_tuning_timer;
2471         struct mmc_host *mmc = host->mmc;
2472
2473         if (host->ops->platform_suspend)
2474                 host->ops->platform_suspend(host);
2475
2476         sdhci_disable_card_detection(host);
2477
2478         /* Disable tuning since we are suspending */
2479         has_tuning_timer = host->version >= SDHCI_SPEC_300 &&
2480                 host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1;
2481         if (has_tuning_timer) {
2482                 del_timer_sync(&host->tuning_timer);
2483                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2484         }
2485
2486         if (mmc->card) {
2487                 /*
2488                  * If eMMC cards are put in sleep state, Vccq can be disabled
2489                  * but Vcc would still be powered on. In resume, we only restore
2490                  * the controller context. So, set MMC_PM_KEEP_POWER flag.
2491                  */
2492                 if (mmc_card_can_sleep(mmc) &&
2493                         !(mmc->caps & MMC_CAP2_NO_SLEEP_CMD))
2494                         mmc->pm_flags = MMC_PM_KEEP_POWER;
2495
2496                 ret = mmc_suspend_host(host->mmc);
2497         if (ret) {
2498                 if (has_tuning_timer) {
2499                         host->flags |= SDHCI_NEEDS_RETUNING;
2500                         mod_timer(&host->tuning_timer, jiffies +
2501                                         host->tuning_count * HZ);
2502                 }
2503
2504                 sdhci_enable_card_detection(host);
2505
2506                 return ret;
2507         }
2508
2509         if (mmc->pm_flags & MMC_PM_KEEP_POWER)
2510                 host->card_int_set = sdhci_readl(host, SDHCI_INT_ENABLE) &
2511                         SDHCI_INT_CARD_INT;
2512
2513         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2514
2515         if (host->irq)
2516                 disable_irq(host->irq);
2517
2518         return ret;
2519 }
2520
2521 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2522
2523 int sdhci_resume_host(struct sdhci_host *host)
2524 {
2525         int ret = 0;
2526         struct mmc_host *mmc = host->mmc;
2527
2528         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2529                 if (host->ops->enable_dma)
2530                         host->ops->enable_dma(host);
2531         }
2532
2533         if (host->irq)
2534                 enable_irq(host->irq);
2535
2536         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2537             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2538                 /* Card keeps power but host controller does not */
2539                 sdhci_init(host, 0);
2540                 host->pwr = 0;
2541                 host->clock = 0;
2542                 sdhci_do_set_ios(host, &host->mmc->ios);
2543         } else {
2544                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2545                 mmiowb();
2546         }
2547
2548         if (mmc->card) {
2549                 ret = mmc_resume_host(host->mmc);
2550                 /* Enable card interrupt as it is overwritten in sdhci_init */
2551                 if ((mmc->caps & MMC_CAP_SDIO_IRQ) &&
2552                         (mmc->pm_flags & MMC_PM_KEEP_POWER))
2553                                 if (host->card_int_set)
2554                                         mmc->ops->enable_sdio_irq(mmc, true);
2555         }
2556
2557         sdhci_enable_card_detection(host);
2558
2559         if (host->ops->platform_resume)
2560                 host->ops->platform_resume(host);
2561
2562         /* Set the re-tuning expiration flag */
2563         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2564             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2565                 host->flags |= SDHCI_NEEDS_RETUNING;
2566
2567         return ret;
2568 }
2569
2570 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2571
2572 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2573 {
2574         u8 val;
2575         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2576         val |= SDHCI_WAKE_ON_INT;
2577         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2578 }
2579
2580 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2581
2582 #endif /* CONFIG_PM */
2583
2584 #ifdef CONFIG_PM_RUNTIME
2585
2586 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2587 {
2588         return pm_runtime_get_sync(host->mmc->parent);
2589 }
2590
2591 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2592 {
2593         pm_runtime_mark_last_busy(host->mmc->parent);
2594         return pm_runtime_put_autosuspend(host->mmc->parent);
2595 }
2596
2597 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2598 {
2599         unsigned long flags;
2600         int ret = 0;
2601
2602         /* Disable tuning since we are suspending */
2603         if (host->version >= SDHCI_SPEC_300 &&
2604             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2605                 del_timer_sync(&host->tuning_timer);
2606                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2607         }
2608
2609         spin_lock_irqsave(&host->lock, flags);
2610         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2611         spin_unlock_irqrestore(&host->lock, flags);
2612
2613         synchronize_irq(host->irq);
2614
2615         spin_lock_irqsave(&host->lock, flags);
2616         host->runtime_suspended = true;
2617         spin_unlock_irqrestore(&host->lock, flags);
2618
2619         return ret;
2620 }
2621 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2622
2623 int sdhci_runtime_resume_host(struct sdhci_host *host)
2624 {
2625         unsigned long flags;
2626         int ret = 0, host_flags = host->flags;
2627
2628         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2629                 if (host->ops->enable_dma)
2630                         host->ops->enable_dma(host);
2631         }
2632
2633         sdhci_init(host, 0);
2634
2635         /* Force clock and power re-program */
2636         host->pwr = 0;
2637         host->clock = 0;
2638         sdhci_do_set_ios(host, &host->mmc->ios);
2639
2640         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2641         if (host_flags & SDHCI_PV_ENABLED)
2642                 sdhci_do_enable_preset_value(host, true);
2643
2644         /* Set the re-tuning expiration flag */
2645         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2646             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2647                 host->flags |= SDHCI_NEEDS_RETUNING;
2648
2649         spin_lock_irqsave(&host->lock, flags);
2650
2651         host->runtime_suspended = false;
2652
2653         /* Enable SDIO IRQ */
2654         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2655                 sdhci_enable_sdio_irq_nolock(host, true);
2656
2657         /* Enable Card Detection */
2658         sdhci_enable_card_detection(host);
2659
2660         spin_unlock_irqrestore(&host->lock, flags);
2661
2662         return ret;
2663 }
2664 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2665
2666 #endif
2667
2668 /*****************************************************************************\
2669  *                                                                           *
2670  * Device allocation/registration                                            *
2671  *                                                                           *
2672 \*****************************************************************************/
2673
2674 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2675         size_t priv_size)
2676 {
2677         struct mmc_host *mmc;
2678         struct sdhci_host *host;
2679
2680         WARN_ON(dev == NULL);
2681
2682         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2683         if (!mmc)
2684                 return ERR_PTR(-ENOMEM);
2685
2686         host = mmc_priv(mmc);
2687         host->mmc = mmc;
2688
2689         return host;
2690 }
2691
2692 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2693
2694 int sdhci_add_host(struct sdhci_host *host)
2695 {
2696         struct mmc_host *mmc;
2697         u32 caps[2];
2698         u32 max_current_caps;
2699         unsigned int ocr_avail;
2700         int ret;
2701
2702         WARN_ON(host == NULL);
2703         if (host == NULL)
2704                 return -EINVAL;
2705
2706         mmc = host->mmc;
2707
2708         if (debug_quirks)
2709                 host->quirks = debug_quirks;
2710         if (debug_quirks2)
2711                 host->quirks2 = debug_quirks2;
2712
2713         sdhci_reset(host, SDHCI_RESET_ALL);
2714
2715         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2716         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2717                                 >> SDHCI_SPEC_VER_SHIFT;
2718         if (host->version > SDHCI_SPEC_300) {
2719                 pr_err("%s: Unknown controller version (%d). "
2720                         "You may experience problems.\n", mmc_hostname(mmc),
2721                         host->version);
2722         }
2723
2724         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2725                 sdhci_readl(host, SDHCI_CAPABILITIES);
2726
2727         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2728                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2729
2730         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2731                 host->flags |= SDHCI_USE_SDMA;
2732         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2733                 DBG("Controller doesn't have SDMA capability\n");
2734         else
2735                 host->flags |= SDHCI_USE_SDMA;
2736
2737         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2738                 (host->flags & SDHCI_USE_SDMA)) {
2739                 DBG("Disabling DMA as it is marked broken\n");
2740                 host->flags &= ~SDHCI_USE_SDMA;
2741         }
2742
2743         if ((host->version >= SDHCI_SPEC_200) &&
2744                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2745                 host->flags |= SDHCI_USE_ADMA;
2746
2747         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2748                 (host->flags & SDHCI_USE_ADMA)) {
2749                 DBG("Disabling ADMA as it is marked broken\n");
2750                 host->flags &= ~SDHCI_USE_ADMA;
2751         }
2752
2753         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2754                 if (host->ops->enable_dma) {
2755                         if (host->ops->enable_dma(host)) {
2756                                 pr_warning("%s: No suitable DMA "
2757                                         "available. Falling back to PIO.\n",
2758                                         mmc_hostname(mmc));
2759                                 host->flags &=
2760                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2761                         }
2762                 }
2763         }
2764
2765         if (host->flags & SDHCI_USE_ADMA) {
2766                 /*
2767                  * We need to allocate descriptors for all sg entries
2768                  * (128) and potentially one alignment transfer for
2769                  * each of those entries.
2770                  */
2771                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2772                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2773                 if (!host->adma_desc || !host->align_buffer) {
2774                         kfree(host->adma_desc);
2775                         kfree(host->align_buffer);
2776                         pr_warning("%s: Unable to allocate ADMA "
2777                                 "buffers. Falling back to standard DMA.\n",
2778                                 mmc_hostname(mmc));
2779                         host->flags &= ~SDHCI_USE_ADMA;
2780                 }
2781         }
2782
2783         /*
2784          * If we use DMA, then it's up to the caller to set the DMA
2785          * mask, but PIO does not need the hw shim so we set a new
2786          * mask here in that case.
2787          */
2788         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2789                 host->dma_mask = DMA_BIT_MASK(64);
2790                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2791         }
2792
2793         if (host->version >= SDHCI_SPEC_300)
2794                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2795                         >> SDHCI_CLOCK_BASE_SHIFT;
2796         else
2797                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2798                         >> SDHCI_CLOCK_BASE_SHIFT;
2799
2800         host->max_clk *= 1000000;
2801         if (host->max_clk == 0 || host->quirks &
2802                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2803                 if (!host->ops->get_max_clock) {
2804                         pr_err("%s: Hardware doesn't specify base clock "
2805                                "frequency.\n", mmc_hostname(mmc));
2806                         return -ENODEV;
2807                 }
2808                 host->max_clk = host->ops->get_max_clock(host);
2809         }
2810
2811         /*
2812          * In case of Host Controller v3.00, find out whether clock
2813          * multiplier is supported.
2814          */
2815         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2816                         SDHCI_CLOCK_MUL_SHIFT;
2817
2818         /*
2819          * In case the value in Clock Multiplier is 0, then programmable
2820          * clock mode is not supported, otherwise the actual clock
2821          * multiplier is one more than the value of Clock Multiplier
2822          * in the Capabilities Register.
2823          */
2824         if (host->clk_mul)
2825                 host->clk_mul += 1;
2826
2827         /*
2828          * Set host parameters.
2829          */
2830         mmc->ops = &sdhci_ops;
2831         mmc->f_max = host->max_clk;
2832         if (host->ops->get_min_clock)
2833                 mmc->f_min = host->ops->get_min_clock(host);
2834         else if (host->version >= SDHCI_SPEC_300) {
2835                 if (host->clk_mul) {
2836                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2837                         mmc->f_max = host->max_clk * host->clk_mul;
2838                 } else
2839                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2840         } else
2841                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2842
2843         host->timeout_clk =
2844                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2845         if (host->timeout_clk == 0) {
2846                 if (host->ops->get_timeout_clock) {
2847                         host->timeout_clk = host->ops->get_timeout_clock(host);
2848                 } else if (!(host->quirks &
2849                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2850                         pr_err("%s: Hardware doesn't specify timeout clock "
2851                                "frequency.\n", mmc_hostname(mmc));
2852                         return -ENODEV;
2853                 }
2854         }
2855         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2856                 host->timeout_clk *= 1000;
2857
2858         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2859                 host->timeout_clk = mmc->f_max / 1000;
2860
2861         if (!(host->quirks & SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO))
2862                 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2863
2864         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2865                 host->flags |= SDHCI_AUTO_CMD12;
2866
2867         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2868         if ((host->version >= SDHCI_SPEC_300) &&
2869             ((host->flags & SDHCI_USE_ADMA) ||
2870              !(host->flags & SDHCI_USE_SDMA))) {
2871                 host->flags |= SDHCI_AUTO_CMD23;
2872                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2873         } else {
2874                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2875         }
2876
2877         /*
2878          * A controller may support 8-bit width, but the board itself
2879          * might not have the pins brought out.  Boards that support
2880          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2881          * their platform code before calling sdhci_add_host(), and we
2882          * won't assume 8-bit width for hosts without that CAP.
2883          */
2884         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2885                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2886
2887         if (caps[0] & SDHCI_CAN_DO_HISPD)
2888                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2889
2890         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2891             mmc_card_is_removable(mmc) && !(host->ops->get_cd))
2892                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2893
2894         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2895         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2896                        SDHCI_SUPPORT_DDR50))
2897                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2898
2899         /* SDR104 supports also implies SDR50 support */
2900         if (caps[1] & SDHCI_SUPPORT_SDR104)
2901                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2902         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2903                 mmc->caps |= MMC_CAP_UHS_SDR50;
2904
2905         if (caps[1] & SDHCI_SUPPORT_DDR50)
2906                 mmc->caps |= MMC_CAP_UHS_DDR50;
2907
2908         /* Does the host need tuning for SDR50? */
2909         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2910                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2911
2912         /* Does the host need tuning for HS200? */
2913         if (mmc->caps2 & MMC_CAP2_HS200)
2914                 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2915
2916         /* Driver Type(s) (A, C, D) supported by the host */
2917         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2918                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2919         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2920                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2921         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2922                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2923
2924         /*
2925          * If Power Off Notify capability is enabled by the host,
2926          * set notify to short power off notify timeout value.
2927          */
2928         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2929                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2930         else
2931                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2932
2933         /* Initial value for re-tuning timer count */
2934         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2935                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2936
2937         /*
2938          * In case Re-tuning Timer is not disabled, the actual value of
2939          * re-tuning timer will be 2 ^ (n - 1).
2940          */
2941         if (host->tuning_count)
2942                 host->tuning_count = 1 << (host->tuning_count - 1);
2943
2944         /* Re-tuning mode supported by the Host Controller */
2945         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2946                              SDHCI_RETUNING_MODE_SHIFT;
2947
2948         ocr_avail = 0;
2949         /*
2950          * According to SD Host Controller spec v3.00, if the Host System
2951          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2952          * the value is meaningful only if Voltage Support in the Capabilities
2953          * register is set. The actual current value is 4 times the register
2954          * value.
2955          */
2956         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2957
2958         if (caps[0] & SDHCI_CAN_VDD_330) {
2959                 int max_current_330;
2960
2961                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2962
2963                 max_current_330 = ((max_current_caps &
2964                                    SDHCI_MAX_CURRENT_330_MASK) >>
2965                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2966                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2967
2968                 if (max_current_330 > 150)
2969                         mmc->caps |= MMC_CAP_SET_XPC_330;
2970         }
2971         if (caps[0] & SDHCI_CAN_VDD_300) {
2972                 int max_current_300;
2973
2974                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2975
2976                 max_current_300 = ((max_current_caps &
2977                                    SDHCI_MAX_CURRENT_300_MASK) >>
2978                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2979                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2980
2981                 if (max_current_300 > 150)
2982                         mmc->caps |= MMC_CAP_SET_XPC_300;
2983         }
2984         if (caps[0] & SDHCI_CAN_VDD_180) {
2985                 int max_current_180;
2986
2987                 ocr_avail |= MMC_VDD_165_195;
2988
2989                 max_current_180 = ((max_current_caps &
2990                                    SDHCI_MAX_CURRENT_180_MASK) >>
2991                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2992                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2993
2994                 if (max_current_180 > 150)
2995                         mmc->caps |= MMC_CAP_SET_XPC_180;
2996
2997                 /* Maximum current capabilities of the host at 1.8V */
2998                 if (max_current_180 >= 800)
2999                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
3000                 else if (max_current_180 >= 600)
3001                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
3002                 else if (max_current_180 >= 400)
3003                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
3004                 else
3005                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
3006         }
3007
3008         mmc->ocr_avail = ocr_avail;
3009         mmc->ocr_avail_sdio = ocr_avail;
3010         if (host->ocr_avail_sdio)
3011                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3012         mmc->ocr_avail_sd = ocr_avail;
3013         if (host->ocr_avail_sd)
3014                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3015         else /* normal SD controllers don't support 1.8V */
3016                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3017         mmc->ocr_avail_mmc = ocr_avail;
3018         if (host->ocr_avail_mmc)
3019                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3020
3021         if (mmc->ocr_avail == 0) {
3022                 pr_err("%s: Hardware doesn't report any "
3023                         "support voltages.\n", mmc_hostname(mmc));
3024                 return -ENODEV;
3025         }
3026
3027         spin_lock_init(&host->lock);
3028
3029         /*
3030          * Maximum number of segments. Depends on if the hardware
3031          * can do scatter/gather or not.
3032          */
3033         if (host->flags & SDHCI_USE_ADMA)
3034                 mmc->max_segs = 128;
3035         else if (host->flags & SDHCI_USE_SDMA)
3036                 mmc->max_segs = 1;
3037         else /* PIO */
3038                 mmc->max_segs = 128;
3039
3040         /*
3041          * Maximum number of sectors in one transfer. Limited by DMA boundary
3042          * size (512KiB).
3043          */
3044         mmc->max_req_size = 524288;
3045
3046         /*
3047          * Maximum segment size. Could be one segment with the maximum number
3048          * of bytes. When doing hardware scatter/gather, each entry cannot
3049          * be larger than 64 KiB though.
3050          */
3051         if (host->flags & SDHCI_USE_ADMA) {
3052                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3053                         mmc->max_seg_size = 65535;
3054                 else
3055                         mmc->max_seg_size = 65536;
3056         } else {
3057                 mmc->max_seg_size = mmc->max_req_size;
3058         }
3059
3060         /*
3061          * Maximum block size. This varies from controller to controller and
3062          * is specified in the capabilities register.
3063          */
3064         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3065                 mmc->max_blk_size = 2;
3066         } else {
3067                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3068                                 SDHCI_MAX_BLOCK_SHIFT;
3069                 if (mmc->max_blk_size >= 3) {
3070                         pr_warning("%s: Invalid maximum block size, "
3071                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3072                         mmc->max_blk_size = 0;
3073                 }
3074         }
3075
3076         mmc->max_blk_size = 512 << mmc->max_blk_size;
3077
3078         /*
3079          * Maximum block count.
3080          */
3081         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3082
3083         /*
3084          * Init tasklets.
3085          */
3086         tasklet_init(&host->card_tasklet,
3087                 sdhci_tasklet_card, (unsigned long)host);
3088         tasklet_init(&host->finish_tasklet,
3089                 sdhci_tasklet_finish, (unsigned long)host);
3090
3091         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3092
3093         if (host->version >= SDHCI_SPEC_300) {
3094                 init_waitqueue_head(&host->buf_ready_int);
3095
3096                 /* Initialize re-tuning timer */
3097                 init_timer(&host->tuning_timer);
3098                 host->tuning_timer.data = (unsigned long)host;
3099                 host->tuning_timer.function = sdhci_tuning_timer;
3100         }
3101
3102         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3103                 mmc_hostname(mmc), host);
3104         if (ret)
3105                 goto untasklet;
3106
3107         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3108         if (IS_ERR(host->vmmc)) {
3109                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3110                 host->vmmc = NULL;
3111         }
3112
3113         sdhci_init(host, 0);
3114
3115 #ifdef CONFIG_MMC_DEBUG
3116         sdhci_dumpregs(host);
3117 #endif
3118
3119 #ifdef SDHCI_USE_LEDS_CLASS
3120         snprintf(host->led_name, sizeof(host->led_name),
3121                 "%s::", mmc_hostname(mmc));
3122         host->led.name = host->led_name;
3123         host->led.brightness = LED_OFF;
3124         host->led.default_trigger = mmc_hostname(mmc);
3125         host->led.brightness_set = sdhci_led_control;
3126
3127         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3128         if (ret)
3129                 goto reset;
3130 #endif
3131
3132         mmiowb();
3133
3134         mmc_add_host(mmc);
3135
3136         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3137                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3138                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3139                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3140
3141         sdhci_enable_card_detection(host);
3142
3143         return 0;
3144
3145 #ifdef SDHCI_USE_LEDS_CLASS
3146 reset:
3147         sdhci_reset(host, SDHCI_RESET_ALL);
3148         free_irq(host->irq, host);
3149 #endif
3150 untasklet:
3151         tasklet_kill(&host->card_tasklet);
3152         tasklet_kill(&host->finish_tasklet);
3153
3154         return ret;
3155 }
3156
3157 EXPORT_SYMBOL_GPL(sdhci_add_host);
3158
3159 void sdhci_remove_host(struct sdhci_host *host, int dead)
3160 {
3161         unsigned long flags;
3162
3163         if (dead) {
3164                 spin_lock_irqsave(&host->lock, flags);
3165
3166                 host->flags |= SDHCI_DEVICE_DEAD;
3167
3168                 if (host->mrq) {
3169                         pr_err("%s: Controller removed during "
3170                                 " transfer!\n", mmc_hostname(host->mmc));
3171
3172                         host->mrq->cmd->error = -ENOMEDIUM;
3173                         tasklet_schedule(&host->finish_tasklet);
3174                 }
3175
3176                 spin_unlock_irqrestore(&host->lock, flags);
3177         }
3178
3179         sdhci_disable_card_detection(host);
3180
3181         mmc_remove_host(host->mmc);
3182
3183 #ifdef SDHCI_USE_LEDS_CLASS
3184         led_classdev_unregister(&host->led);
3185 #endif
3186
3187         if (!dead)
3188                 sdhci_reset(host, SDHCI_RESET_ALL);
3189
3190         free_irq(host->irq, host);
3191
3192         del_timer_sync(&host->timer);
3193         if (host->version >= SDHCI_SPEC_300)
3194                 del_timer_sync(&host->tuning_timer);
3195
3196         tasklet_kill(&host->card_tasklet);
3197         tasklet_kill(&host->finish_tasklet);
3198
3199         if (host->vmmc)
3200                 regulator_put(host->vmmc);
3201
3202         kfree(host->adma_desc);
3203         kfree(host->align_buffer);
3204
3205         host->adma_desc = NULL;
3206         host->align_buffer = NULL;
3207 }
3208
3209 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3210
3211 void sdhci_free_host(struct sdhci_host *host)
3212 {
3213         mmc_free_host(host->mmc);
3214 }
3215
3216 EXPORT_SYMBOL_GPL(sdhci_free_host);
3217
3218 /*****************************************************************************\
3219  *                                                                           *
3220  * Driver init/exit                                                          *
3221  *                                                                           *
3222 \*****************************************************************************/
3223
3224 static int __init sdhci_drv_init(void)
3225 {
3226         pr_info(DRIVER_NAME
3227                 ": Secure Digital Host Controller Interface driver\n");
3228         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3229
3230         return 0;
3231 }
3232
3233 static void __exit sdhci_drv_exit(void)
3234 {
3235 }
3236
3237 module_init(sdhci_drv_init);
3238 module_exit(sdhci_drv_exit);
3239
3240 module_param(debug_quirks, uint, 0444);
3241 module_param(debug_quirks2, uint, 0444);
3242
3243 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3244 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3245 MODULE_LICENSE("GPL");
3246
3247 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3248 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");