mmc: host: sdhci: do not force mmc caps by default
[linux-2.6.git] / drivers / mmc / host / sdhci.c
1 /*
2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3  *
4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or (at
9  * your option) any later version.
10  *
11  * Thanks to the following companies for their support:
12  *
13  *     - JMicron (hardware and technical support)
14  */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <linux/leds.h>
25
26 #include <linux/mmc/mmc.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/card.h>
29
30 #include "sdhci.h"
31
32 #define DRIVER_NAME "sdhci"
33
34 #define DBG(f, x...) \
35         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
36
37 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
38         defined(CONFIG_MMC_SDHCI_MODULE))
39 #define SDHCI_USE_LEDS_CLASS
40 #endif
41
42 #define MAX_TUNING_LOOP 40
43
44 static unsigned int debug_quirks = 0;
45
46 static void sdhci_finish_data(struct sdhci_host *);
47
48 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
49 static void sdhci_finish_command(struct sdhci_host *);
50 static int sdhci_execute_tuning(struct mmc_host *mmc);
51 static void sdhci_tuning_timer(unsigned long data);
52
53 static void sdhci_dumpregs(struct sdhci_host *host)
54 {
55         printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
56                 mmc_hostname(host->mmc));
57
58         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
59                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60                 sdhci_readw(host, SDHCI_HOST_VERSION));
61         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
62                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
64         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
65                 sdhci_readl(host, SDHCI_ARGUMENT),
66                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
67         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
68                 sdhci_readl(host, SDHCI_PRESENT_STATE),
69                 sdhci_readb(host, SDHCI_HOST_CONTROL));
70         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
71                 sdhci_readb(host, SDHCI_POWER_CONTROL),
72                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
73         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
74                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
76         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
77                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78                 sdhci_readl(host, SDHCI_INT_STATUS));
79         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
80                 sdhci_readl(host, SDHCI_INT_ENABLE),
81                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
82         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
83                 sdhci_readw(host, SDHCI_ACMD12_ERR),
84                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
85         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
86                 sdhci_readl(host, SDHCI_CAPABILITIES),
87                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
88         printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
89                 sdhci_readw(host, SDHCI_COMMAND),
90                 sdhci_readl(host, SDHCI_MAX_CURRENT));
91         printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
92                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
93
94         if (host->flags & SDHCI_USE_ADMA)
95                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
96                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
97                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
98
99         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
100 }
101
102 /*****************************************************************************\
103  *                                                                           *
104  * Low level functions                                                       *
105  *                                                                           *
106 \*****************************************************************************/
107
108 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
109 {
110         u32 ier;
111
112         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
113         ier &= ~clear;
114         ier |= set;
115         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
116         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
117 }
118
119 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
120 {
121         sdhci_clear_set_irqs(host, 0, irqs);
122 }
123
124 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
125 {
126         sdhci_clear_set_irqs(host, irqs, 0);
127 }
128
129 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
130 {
131         u32 present, irqs;
132
133         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
134                 return;
135
136         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
137                               SDHCI_CARD_PRESENT;
138         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
139
140         if (enable)
141                 sdhci_unmask_irqs(host, irqs);
142         else
143                 sdhci_mask_irqs(host, irqs);
144 }
145
146 static void sdhci_enable_card_detection(struct sdhci_host *host)
147 {
148         sdhci_set_card_detection(host, true);
149 }
150
151 static void sdhci_disable_card_detection(struct sdhci_host *host)
152 {
153         sdhci_set_card_detection(host, false);
154 }
155
156 static void sdhci_reset(struct sdhci_host *host, u8 mask)
157 {
158         unsigned long timeout;
159         u32 uninitialized_var(ier);
160
161         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
162                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
163                         SDHCI_CARD_PRESENT))
164                         return;
165         }
166
167         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
168                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
169
170         if (host->ops->platform_reset_enter)
171                 host->ops->platform_reset_enter(host, mask);
172
173         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
174
175         if (mask & SDHCI_RESET_ALL)
176                 host->clock = 0;
177
178         /* Wait max 100 ms */
179         timeout = 100;
180
181         /* hw clears the bit when it's done */
182         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
183                 if (timeout == 0) {
184                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
185                                 mmc_hostname(host->mmc), (int)mask);
186                         sdhci_dumpregs(host);
187                         return;
188                 }
189                 timeout--;
190                 mdelay(1);
191         }
192
193         if (host->ops->platform_reset_exit)
194                 host->ops->platform_reset_exit(host, mask);
195
196         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
197                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
198 }
199
200 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
201
202 static void sdhci_init(struct sdhci_host *host, int soft)
203 {
204         if (soft)
205                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
206         else
207                 sdhci_reset(host, SDHCI_RESET_ALL);
208
209         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
210                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
211                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
212                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
213                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
214
215         if (soft) {
216                 /* force clock reconfiguration */
217                 host->clock = 0;
218                 sdhci_set_ios(host->mmc, &host->mmc->ios);
219         }
220 }
221
222 static void sdhci_reinit(struct sdhci_host *host)
223 {
224         sdhci_init(host, 0);
225         sdhci_enable_card_detection(host);
226 }
227
228 static void sdhci_activate_led(struct sdhci_host *host)
229 {
230         u8 ctrl;
231
232         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
233         ctrl |= SDHCI_CTRL_LED;
234         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
235 }
236
237 static void sdhci_deactivate_led(struct sdhci_host *host)
238 {
239         u8 ctrl;
240
241         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
242         ctrl &= ~SDHCI_CTRL_LED;
243         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
244 }
245
246 #ifdef SDHCI_USE_LEDS_CLASS
247 static void sdhci_led_control(struct led_classdev *led,
248         enum led_brightness brightness)
249 {
250         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
251         unsigned long flags;
252
253         spin_lock_irqsave(&host->lock, flags);
254
255         if (brightness == LED_OFF)
256                 sdhci_deactivate_led(host);
257         else
258                 sdhci_activate_led(host);
259
260         spin_unlock_irqrestore(&host->lock, flags);
261 }
262 #endif
263
264 /*****************************************************************************\
265  *                                                                           *
266  * Core functions                                                            *
267  *                                                                           *
268 \*****************************************************************************/
269
270 static void sdhci_read_block_pio(struct sdhci_host *host)
271 {
272         unsigned long flags;
273         size_t blksize, len, chunk;
274         u32 uninitialized_var(scratch);
275         u8 *buf;
276
277         DBG("PIO reading\n");
278
279         blksize = host->data->blksz;
280         chunk = 0;
281
282         local_irq_save(flags);
283
284         while (blksize) {
285                 if (!sg_miter_next(&host->sg_miter))
286                         BUG();
287
288                 len = min(host->sg_miter.length, blksize);
289
290                 blksize -= len;
291                 host->sg_miter.consumed = len;
292
293                 buf = host->sg_miter.addr;
294
295                 while (len) {
296                         if (chunk == 0) {
297                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
298                                 chunk = 4;
299                         }
300
301                         *buf = scratch & 0xFF;
302
303                         buf++;
304                         scratch >>= 8;
305                         chunk--;
306                         len--;
307                 }
308         }
309
310         sg_miter_stop(&host->sg_miter);
311
312         local_irq_restore(flags);
313 }
314
315 static void sdhci_write_block_pio(struct sdhci_host *host)
316 {
317         unsigned long flags;
318         size_t blksize, len, chunk;
319         u32 scratch;
320         u8 *buf;
321
322         DBG("PIO writing\n");
323
324         blksize = host->data->blksz;
325         chunk = 0;
326         scratch = 0;
327
328         local_irq_save(flags);
329
330         while (blksize) {
331                 if (!sg_miter_next(&host->sg_miter))
332                         BUG();
333
334                 len = min(host->sg_miter.length, blksize);
335
336                 blksize -= len;
337                 host->sg_miter.consumed = len;
338
339                 buf = host->sg_miter.addr;
340
341                 while (len) {
342                         scratch |= (u32)*buf << (chunk * 8);
343
344                         buf++;
345                         chunk++;
346                         len--;
347
348                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
349                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
350                                 chunk = 0;
351                                 scratch = 0;
352                         }
353                 }
354         }
355
356         sg_miter_stop(&host->sg_miter);
357
358         local_irq_restore(flags);
359 }
360
361 static void sdhci_transfer_pio(struct sdhci_host *host)
362 {
363         u32 mask;
364
365         BUG_ON(!host->data);
366
367         if (host->blocks == 0)
368                 return;
369
370         if (host->data->flags & MMC_DATA_READ)
371                 mask = SDHCI_DATA_AVAILABLE;
372         else
373                 mask = SDHCI_SPACE_AVAILABLE;
374
375         /*
376          * Some controllers (JMicron JMB38x) mess up the buffer bits
377          * for transfers < 4 bytes. As long as it is just one block,
378          * we can ignore the bits.
379          */
380         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
381                 (host->data->blocks == 1))
382                 mask = ~0;
383
384         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
385                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
386                         udelay(100);
387
388                 if (host->data->flags & MMC_DATA_READ)
389                         sdhci_read_block_pio(host);
390                 else
391                         sdhci_write_block_pio(host);
392
393                 host->blocks--;
394                 if (host->blocks == 0)
395                         break;
396         }
397
398         DBG("PIO transfer complete.\n");
399 }
400
401 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
402 {
403         local_irq_save(*flags);
404         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
405 }
406
407 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
408 {
409         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
410         local_irq_restore(*flags);
411 }
412
413 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
414 {
415         __le32 *dataddr = (__le32 __force *)(desc + 4);
416         __le16 *cmdlen = (__le16 __force *)desc;
417
418         /* SDHCI specification says ADMA descriptors should be 4 byte
419          * aligned, so using 16 or 32bit operations should be safe. */
420
421         cmdlen[0] = cpu_to_le16(cmd);
422         cmdlen[1] = cpu_to_le16(len);
423
424         dataddr[0] = cpu_to_le32(addr);
425 }
426
427 static int sdhci_adma_table_pre(struct sdhci_host *host,
428         struct mmc_data *data)
429 {
430         int direction;
431
432         u8 *desc;
433         u8 *align;
434         dma_addr_t addr;
435         dma_addr_t align_addr;
436         int len, offset;
437
438         struct scatterlist *sg;
439         int i;
440         char *buffer;
441         unsigned long flags;
442
443         /*
444          * The spec does not specify endianness of descriptor table.
445          * We currently guess that it is LE.
446          */
447
448         if (data->flags & MMC_DATA_READ)
449                 direction = DMA_FROM_DEVICE;
450         else
451                 direction = DMA_TO_DEVICE;
452
453         /*
454          * The ADMA descriptor table is mapped further down as we
455          * need to fill it with data first.
456          */
457
458         host->align_addr = dma_map_single(mmc_dev(host->mmc),
459                 host->align_buffer, 128 * 4, direction);
460         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
461                 goto fail;
462         BUG_ON(host->align_addr & 0x3);
463
464         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
465                 data->sg, data->sg_len, direction);
466         if (host->sg_count == 0)
467                 goto unmap_align;
468
469         desc = host->adma_desc;
470         align = host->align_buffer;
471
472         align_addr = host->align_addr;
473
474         for_each_sg(data->sg, sg, host->sg_count, i) {
475                 addr = sg_dma_address(sg);
476                 len = sg_dma_len(sg);
477
478                 /*
479                  * The SDHCI specification states that ADMA
480                  * addresses must be 32-bit aligned. If they
481                  * aren't, then we use a bounce buffer for
482                  * the (up to three) bytes that screw up the
483                  * alignment.
484                  */
485                 offset = (4 - (addr & 0x3)) & 0x3;
486                 if (offset) {
487                         if (data->flags & MMC_DATA_WRITE) {
488                                 buffer = sdhci_kmap_atomic(sg, &flags);
489                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
490                                 memcpy(align, buffer, offset);
491                                 sdhci_kunmap_atomic(buffer, &flags);
492                         }
493
494                         /* tran, valid */
495                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
496
497                         BUG_ON(offset > 65536);
498
499                         align += 4;
500                         align_addr += 4;
501
502                         desc += 8;
503
504                         addr += offset;
505                         len -= offset;
506                 }
507
508                 BUG_ON(len > 65536);
509
510                 /* tran, valid */
511                 sdhci_set_adma_desc(desc, addr, len, 0x21);
512                 desc += 8;
513
514                 /*
515                  * If this triggers then we have a calculation bug
516                  * somewhere. :/
517                  */
518                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
519         }
520
521         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
522                 /*
523                 * Mark the last descriptor as the terminating descriptor
524                 */
525                 if (desc != host->adma_desc) {
526                         desc -= 8;
527                         desc[0] |= 0x2; /* end */
528                 }
529         } else {
530                 /*
531                 * Add a terminating entry.
532                 */
533
534                 /* nop, end, valid */
535                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
536         }
537
538         /*
539          * Resync align buffer as we might have changed it.
540          */
541         if (data->flags & MMC_DATA_WRITE) {
542                 dma_sync_single_for_device(mmc_dev(host->mmc),
543                         host->align_addr, 128 * 4, direction);
544         }
545
546         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
547                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
548         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
549                 goto unmap_entries;
550         BUG_ON(host->adma_addr & 0x3);
551
552         return 0;
553
554 unmap_entries:
555         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
556                 data->sg_len, direction);
557 unmap_align:
558         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
559                 128 * 4, direction);
560 fail:
561         return -EINVAL;
562 }
563
564 static void sdhci_adma_table_post(struct sdhci_host *host,
565         struct mmc_data *data)
566 {
567         int direction;
568
569         struct scatterlist *sg;
570         int i, size;
571         u8 *align;
572         char *buffer;
573         unsigned long flags;
574
575         if (data->flags & MMC_DATA_READ)
576                 direction = DMA_FROM_DEVICE;
577         else
578                 direction = DMA_TO_DEVICE;
579
580         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
581                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
582
583         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
584                 128 * 4, direction);
585
586         if (data->flags & MMC_DATA_READ) {
587                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
588                         data->sg_len, direction);
589
590                 align = host->align_buffer;
591
592                 for_each_sg(data->sg, sg, host->sg_count, i) {
593                         if (sg_dma_address(sg) & 0x3) {
594                                 size = 4 - (sg_dma_address(sg) & 0x3);
595
596                                 buffer = sdhci_kmap_atomic(sg, &flags);
597                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
598                                 memcpy(buffer, align, size);
599                                 sdhci_kunmap_atomic(buffer, &flags);
600
601                                 align += 4;
602                         }
603                 }
604         }
605
606         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
607                 data->sg_len, direction);
608 }
609
610 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
611 {
612         u8 count;
613         struct mmc_data *data = cmd->data;
614         unsigned target_timeout, current_timeout;
615
616         /*
617          * If the host controller provides us with an incorrect timeout
618          * value, just skip the check and use 0xE.  The hardware may take
619          * longer to time out, but that's much better than having a too-short
620          * timeout value.
621          */
622         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
623                 return 0xE;
624
625         /* Unspecified timeout, assume max */
626         if (!data && !cmd->cmd_timeout_ms)
627                 return 0xE;
628
629         /* timeout in us */
630         if (!data)
631                 target_timeout = cmd->cmd_timeout_ms * 1000;
632         else {
633                 target_timeout = data->timeout_ns / 1000;
634                 if (host->clock)
635                         target_timeout += data->timeout_clks / host->clock;
636         }
637
638         /*
639          * Figure out needed cycles.
640          * We do this in steps in order to fit inside a 32 bit int.
641          * The first step is the minimum timeout, which will have a
642          * minimum resolution of 6 bits:
643          * (1) 2^13*1000 > 2^22,
644          * (2) host->timeout_clk < 2^16
645          *     =>
646          *     (1) / (2) > 2^6
647          */
648         count = 0;
649         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
650         while (current_timeout < target_timeout) {
651                 count++;
652                 current_timeout <<= 1;
653                 if (count >= 0xF)
654                         break;
655         }
656
657         if (count >= 0xF) {
658                 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
659                        mmc_hostname(host->mmc), cmd->opcode);
660                 count = 0xE;
661         }
662
663         return count;
664 }
665
666 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
667 {
668         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
669         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
670
671         if (host->flags & SDHCI_REQ_USE_DMA)
672                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
673         else
674                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
675 }
676
677 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
678 {
679         u8 count;
680         u8 ctrl;
681         struct mmc_data *data = cmd->data;
682         int ret;
683
684         WARN_ON(host->data);
685
686         if (data || (cmd->flags & MMC_RSP_BUSY)) {
687                 count = sdhci_calc_timeout(host, cmd);
688                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
689         }
690
691         if (!data)
692                 return;
693
694         /* Sanity checks */
695         BUG_ON(data->blksz * data->blocks > 524288);
696         BUG_ON(data->blksz > host->mmc->max_blk_size);
697         BUG_ON(data->blocks > 65535);
698
699         host->data = data;
700         host->data_early = 0;
701         host->data->bytes_xfered = 0;
702
703         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
704                 host->flags |= SDHCI_REQ_USE_DMA;
705
706         /*
707          * FIXME: This doesn't account for merging when mapping the
708          * scatterlist.
709          */
710         if (host->flags & SDHCI_REQ_USE_DMA) {
711                 int broken, i;
712                 struct scatterlist *sg;
713
714                 broken = 0;
715                 if (host->flags & SDHCI_USE_ADMA) {
716                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
717                                 broken = 1;
718                 } else {
719                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
720                                 broken = 1;
721                 }
722
723                 if (unlikely(broken)) {
724                         for_each_sg(data->sg, sg, data->sg_len, i) {
725                                 if (sg->length & 0x3) {
726                                         DBG("Reverting to PIO because of "
727                                                 "transfer size (%d)\n",
728                                                 sg->length);
729                                         host->flags &= ~SDHCI_REQ_USE_DMA;
730                                         break;
731                                 }
732                         }
733                 }
734         }
735
736         /*
737          * The assumption here being that alignment is the same after
738          * translation to device address space.
739          */
740         if (host->flags & SDHCI_REQ_USE_DMA) {
741                 int broken, i;
742                 struct scatterlist *sg;
743
744                 broken = 0;
745                 if (host->flags & SDHCI_USE_ADMA) {
746                         /*
747                          * As we use 3 byte chunks to work around
748                          * alignment problems, we need to check this
749                          * quirk.
750                          */
751                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
752                                 broken = 1;
753                 } else {
754                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
755                                 broken = 1;
756                 }
757
758                 if (unlikely(broken)) {
759                         for_each_sg(data->sg, sg, data->sg_len, i) {
760                                 if (sg->offset & 0x3) {
761                                         DBG("Reverting to PIO because of "
762                                                 "bad alignment\n");
763                                         host->flags &= ~SDHCI_REQ_USE_DMA;
764                                         break;
765                                 }
766                         }
767                 }
768         }
769
770         if (host->flags & SDHCI_REQ_USE_DMA) {
771                 if (host->flags & SDHCI_USE_ADMA) {
772                         ret = sdhci_adma_table_pre(host, data);
773                         if (ret) {
774                                 /*
775                                  * This only happens when someone fed
776                                  * us an invalid request.
777                                  */
778                                 WARN_ON(1);
779                                 host->flags &= ~SDHCI_REQ_USE_DMA;
780                         } else {
781                                 sdhci_writel(host, host->adma_addr,
782                                         SDHCI_ADMA_ADDRESS);
783                         }
784                 } else {
785                         int sg_cnt;
786
787                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
788                                         data->sg, data->sg_len,
789                                         (data->flags & MMC_DATA_READ) ?
790                                                 DMA_FROM_DEVICE :
791                                                 DMA_TO_DEVICE);
792                         if (sg_cnt == 0) {
793                                 /*
794                                  * This only happens when someone fed
795                                  * us an invalid request.
796                                  */
797                                 WARN_ON(1);
798                                 host->flags &= ~SDHCI_REQ_USE_DMA;
799                         } else {
800                                 WARN_ON(sg_cnt != 1);
801                                 sdhci_writel(host, sg_dma_address(data->sg),
802                                         SDHCI_DMA_ADDRESS);
803                         }
804                 }
805         }
806
807         /*
808          * Always adjust the DMA selection as some controllers
809          * (e.g. JMicron) can't do PIO properly when the selection
810          * is ADMA.
811          */
812         if (host->version >= SDHCI_SPEC_200) {
813                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
814                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
815                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
816                         (host->flags & SDHCI_USE_ADMA))
817                         ctrl |= SDHCI_CTRL_ADMA32;
818                 else
819                         ctrl |= SDHCI_CTRL_SDMA;
820                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
821         }
822
823         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
824                 int flags;
825
826                 flags = SG_MITER_ATOMIC;
827                 if (host->data->flags & MMC_DATA_READ)
828                         flags |= SG_MITER_TO_SG;
829                 else
830                         flags |= SG_MITER_FROM_SG;
831                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
832                 host->blocks = data->blocks;
833         }
834
835         sdhci_set_transfer_irqs(host);
836
837         /* Set the DMA boundary value and block size */
838         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
839                 data->blksz), SDHCI_BLOCK_SIZE);
840         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
841 }
842
843 static void sdhci_set_transfer_mode(struct sdhci_host *host,
844         struct mmc_command *cmd)
845 {
846         u16 mode;
847         struct mmc_data *data = cmd->data;
848
849         if (data == NULL)
850                 return;
851
852         WARN_ON(!host->data);
853
854         mode = SDHCI_TRNS_BLK_CNT_EN;
855         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
856                 mode |= SDHCI_TRNS_MULTI;
857                 /*
858                  * If we are sending CMD23, CMD12 never gets sent
859                  * on successful completion (so no Auto-CMD12).
860                  */
861                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
862                         mode |= SDHCI_TRNS_AUTO_CMD12;
863                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
864                         mode |= SDHCI_TRNS_AUTO_CMD23;
865                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
866                 }
867         }
868
869         if (data->flags & MMC_DATA_READ)
870                 mode |= SDHCI_TRNS_READ;
871         if (host->flags & SDHCI_REQ_USE_DMA)
872                 mode |= SDHCI_TRNS_DMA;
873
874         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
875 }
876
877 static void sdhci_finish_data(struct sdhci_host *host)
878 {
879         struct mmc_data *data;
880
881         BUG_ON(!host->data);
882
883         data = host->data;
884         host->data = NULL;
885
886         if (host->flags & SDHCI_REQ_USE_DMA) {
887                 if (host->flags & SDHCI_USE_ADMA)
888                         sdhci_adma_table_post(host, data);
889                 else {
890                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
891                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
892                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
893                 }
894         }
895
896         /*
897          * The specification states that the block count register must
898          * be updated, but it does not specify at what point in the
899          * data flow. That makes the register entirely useless to read
900          * back so we have to assume that nothing made it to the card
901          * in the event of an error.
902          */
903         if (data->error)
904                 data->bytes_xfered = 0;
905         else
906                 data->bytes_xfered = data->blksz * data->blocks;
907
908         /*
909          * Need to send CMD12 if -
910          * a) open-ended multiblock transfer (no CMD23)
911          * b) error in multiblock transfer
912          */
913         if (data->stop &&
914             (data->error ||
915              !host->mrq->sbc)) {
916
917                 /*
918                  * The controller needs a reset of internal state machines
919                  * upon error conditions.
920                  */
921                 if (data->error) {
922                         sdhci_reset(host, SDHCI_RESET_CMD);
923                         sdhci_reset(host, SDHCI_RESET_DATA);
924                 }
925
926                 sdhci_send_command(host, data->stop);
927         } else
928                 tasklet_schedule(&host->finish_tasklet);
929 }
930
931 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
932 {
933         int flags;
934         u32 mask;
935         unsigned long timeout;
936
937         WARN_ON(host->cmd);
938
939         /* Wait max 10 ms */
940         timeout = 10;
941
942         mask = SDHCI_CMD_INHIBIT;
943         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
944                 mask |= SDHCI_DATA_INHIBIT;
945
946         /* We shouldn't wait for data inihibit for stop commands, even
947            though they might use busy signaling */
948         if (host->mrq->data && (cmd == host->mrq->data->stop))
949                 mask &= ~SDHCI_DATA_INHIBIT;
950
951         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
952                 if (timeout == 0) {
953                         printk(KERN_ERR "%s: Controller never released "
954                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
955                         sdhci_dumpregs(host);
956                         cmd->error = -EIO;
957                         tasklet_schedule(&host->finish_tasklet);
958                         return;
959                 }
960                 timeout--;
961                 mdelay(1);
962         }
963
964         mod_timer(&host->timer, jiffies + 10 * HZ);
965
966         host->cmd = cmd;
967
968         sdhci_prepare_data(host, cmd);
969
970         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
971
972         sdhci_set_transfer_mode(host, cmd);
973
974         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
975                 printk(KERN_ERR "%s: Unsupported response type!\n",
976                         mmc_hostname(host->mmc));
977                 cmd->error = -EINVAL;
978                 tasklet_schedule(&host->finish_tasklet);
979                 return;
980         }
981
982         if (!(cmd->flags & MMC_RSP_PRESENT))
983                 flags = SDHCI_CMD_RESP_NONE;
984         else if (cmd->flags & MMC_RSP_136)
985                 flags = SDHCI_CMD_RESP_LONG;
986         else if (cmd->flags & MMC_RSP_BUSY)
987                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
988         else
989                 flags = SDHCI_CMD_RESP_SHORT;
990
991         if (cmd->flags & MMC_RSP_CRC)
992                 flags |= SDHCI_CMD_CRC;
993         if (cmd->flags & MMC_RSP_OPCODE)
994                 flags |= SDHCI_CMD_INDEX;
995
996         /* CMD19 is special in that the Data Present Select should be set */
997         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
998                 flags |= SDHCI_CMD_DATA;
999
1000         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1001 }
1002
1003 static void sdhci_finish_command(struct sdhci_host *host)
1004 {
1005         int i;
1006
1007         BUG_ON(host->cmd == NULL);
1008
1009         if (host->cmd->flags & MMC_RSP_PRESENT) {
1010                 if (host->cmd->flags & MMC_RSP_136) {
1011                         /* CRC is stripped so we need to do some shifting. */
1012                         for (i = 0;i < 4;i++) {
1013                                 host->cmd->resp[i] = sdhci_readl(host,
1014                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1015                                 if (i != 3)
1016                                         host->cmd->resp[i] |=
1017                                                 sdhci_readb(host,
1018                                                 SDHCI_RESPONSE + (3-i)*4-1);
1019                         }
1020                 } else {
1021                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1022                 }
1023         }
1024
1025         host->cmd->error = 0;
1026
1027         /* Finished CMD23, now send actual command. */
1028         if (host->cmd == host->mrq->sbc) {
1029                 host->cmd = NULL;
1030                 sdhci_send_command(host, host->mrq->cmd);
1031         } else {
1032
1033                 /* Processed actual command. */
1034                 if (host->data && host->data_early)
1035                         sdhci_finish_data(host);
1036
1037                 if (!host->cmd->data)
1038                         tasklet_schedule(&host->finish_tasklet);
1039
1040                 host->cmd = NULL;
1041         }
1042 }
1043
1044 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1045 {
1046         int div = 0; /* Initialized for compiler warning */
1047         u16 clk = 0;
1048         unsigned long timeout;
1049
1050         if (clock && clock == host->clock)
1051                 return;
1052
1053         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1054                 return;
1055
1056         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1057
1058         if (clock == 0)
1059                 goto out;
1060
1061         if (host->version >= SDHCI_SPEC_300) {
1062                 /*
1063                  * Check if the Host Controller supports Programmable Clock
1064                  * Mode.
1065                  */
1066                 if (host->clk_mul) {
1067                         u16 ctrl;
1068
1069                         /*
1070                          * We need to figure out whether the Host Driver needs
1071                          * to select Programmable Clock Mode, or the value can
1072                          * be set automatically by the Host Controller based on
1073                          * the Preset Value registers.
1074                          */
1075                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1076                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1077                                 for (div = 1; div <= 1024; div++) {
1078                                         if (((host->max_clk * host->clk_mul) /
1079                                               div) <= clock)
1080                                                 break;
1081                                 }
1082                                 /*
1083                                  * Set Programmable Clock Mode in the Clock
1084                                  * Control register.
1085                                  */
1086                                 clk = SDHCI_PROG_CLOCK_MODE;
1087                                 div--;
1088                         }
1089                 } else {
1090                         /* Version 3.00 divisors must be a multiple of 2. */
1091                         if (host->max_clk <= clock)
1092                                 div = 1;
1093                         else {
1094                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1095                                      div += 2) {
1096                                         if ((host->max_clk / div) <= clock)
1097                                                 break;
1098                                 }
1099                         }
1100                         div >>= 1;
1101                 }
1102         } else {
1103                 /* Version 2.00 divisors must be a power of 2. */
1104                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1105                         if ((host->max_clk / div) <= clock)
1106                                 break;
1107                 }
1108                 div >>= 1;
1109         }
1110
1111         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1112         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1113                 << SDHCI_DIVIDER_HI_SHIFT;
1114         clk |= SDHCI_CLOCK_INT_EN;
1115         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1116
1117         /* Wait max 20 ms */
1118         timeout = 20;
1119         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1120                 & SDHCI_CLOCK_INT_STABLE)) {
1121                 if (timeout == 0) {
1122                         printk(KERN_ERR "%s: Internal clock never "
1123                                 "stabilised.\n", mmc_hostname(host->mmc));
1124                         sdhci_dumpregs(host);
1125                         return;
1126                 }
1127                 timeout--;
1128                 mdelay(1);
1129         }
1130
1131         clk |= SDHCI_CLOCK_CARD_EN;
1132         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1133
1134 out:
1135         host->clock = clock;
1136 }
1137
1138 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1139 {
1140         u8 pwr = 0;
1141
1142         if (power != (unsigned short)-1) {
1143                 switch (1 << power) {
1144                 case MMC_VDD_165_195:
1145                         pwr = SDHCI_POWER_180;
1146                         break;
1147                 case MMC_VDD_29_30:
1148                 case MMC_VDD_30_31:
1149                         pwr = SDHCI_POWER_300;
1150                         break;
1151                 case MMC_VDD_32_33:
1152                 case MMC_VDD_33_34:
1153                         pwr = SDHCI_POWER_330;
1154                         break;
1155                 default:
1156                         BUG();
1157                 }
1158         }
1159
1160         if (host->pwr == pwr)
1161                 return;
1162
1163         host->pwr = pwr;
1164
1165         if (pwr == 0) {
1166                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1167                 return;
1168         }
1169
1170         /*
1171          * Spec says that we should clear the power reg before setting
1172          * a new value. Some controllers don't seem to like this though.
1173          */
1174         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1175                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1176
1177         /*
1178          * At least the Marvell CaFe chip gets confused if we set the voltage
1179          * and set turn on power at the same time, so set the voltage first.
1180          */
1181         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1182                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1183
1184         pwr |= SDHCI_POWER_ON;
1185
1186         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1187
1188         /*
1189          * Some controllers need an extra 10ms delay of 10ms before they
1190          * can apply clock after applying power
1191          */
1192         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1193                 mdelay(10);
1194 }
1195
1196 /*****************************************************************************\
1197  *                                                                           *
1198  * MMC callbacks                                                             *
1199  *                                                                           *
1200 \*****************************************************************************/
1201
1202 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1203 {
1204         struct sdhci_host *host;
1205         bool present;
1206         unsigned long flags;
1207
1208         host = mmc_priv(mmc);
1209
1210         spin_lock_irqsave(&host->lock, flags);
1211
1212         WARN_ON(host->mrq != NULL);
1213
1214 #ifndef SDHCI_USE_LEDS_CLASS
1215         sdhci_activate_led(host);
1216 #endif
1217
1218         /*
1219          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1220          * requests if Auto-CMD12 is enabled.
1221          */
1222         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1223                 if (mrq->stop) {
1224                         mrq->data->stop = NULL;
1225                         mrq->stop = NULL;
1226                 }
1227         }
1228
1229         host->mrq = mrq;
1230
1231         /* If polling, assume that the card is always present. */
1232         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1233                 present = true;
1234         else
1235                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1236                                 SDHCI_CARD_PRESENT;
1237
1238         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1239                 host->mrq->cmd->error = -ENOMEDIUM;
1240                 tasklet_schedule(&host->finish_tasklet);
1241         } else {
1242                 u32 present_state;
1243
1244                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1245                 /*
1246                  * Check if the re-tuning timer has already expired and there
1247                  * is no on-going data transfer. If so, we need to execute
1248                  * tuning procedure before sending command.
1249                  */
1250                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1251                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1252                         spin_unlock_irqrestore(&host->lock, flags);
1253                         sdhci_execute_tuning(mmc);
1254                         spin_lock_irqsave(&host->lock, flags);
1255
1256                         /* Restore original mmc_request structure */
1257                         host->mrq = mrq;
1258                 }
1259
1260                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1261                         sdhci_send_command(host, mrq->sbc);
1262                 else
1263                         sdhci_send_command(host, mrq->cmd);
1264         }
1265
1266         mmiowb();
1267         spin_unlock_irqrestore(&host->lock, flags);
1268 }
1269
1270 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1271 {
1272         struct sdhci_host *host;
1273         unsigned long flags;
1274         u8 ctrl;
1275
1276         host = mmc_priv(mmc);
1277
1278         /*
1279          * Controller registers should not be updated without the
1280          * controller clock enabled. Set the minimum controller
1281          * clock if there is no clock.
1282          */
1283         if (host->ops->set_clock) {
1284                 if (!host->clock && !ios->clock) {
1285                         host->ops->set_clock(host, host->mmc->f_min);
1286                         host->clock = host->mmc->f_min;
1287                 } else if (ios->clock && (ios->clock != host->clock)) {
1288                         host->ops->set_clock(host, ios->clock);
1289                 }
1290         }
1291
1292         spin_lock_irqsave(&host->lock, flags);
1293
1294         if (host->flags & SDHCI_DEVICE_DEAD)
1295                 goto out;
1296
1297         /*
1298          * Reset the chip on each power off.
1299          * Should clear out any weird states.
1300          */
1301         if (ios->power_mode == MMC_POWER_OFF) {
1302                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1303                 sdhci_reinit(host);
1304         }
1305
1306         if (ios->power_mode == MMC_POWER_OFF)
1307                 sdhci_set_power(host, -1);
1308         else
1309                 sdhci_set_power(host, ios->vdd);
1310
1311         sdhci_set_clock(host, ios->clock);
1312
1313         if (host->ops->platform_send_init_74_clocks)
1314                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1315
1316         /*
1317          * If your platform has 8-bit width support but is not a v3 controller,
1318          * or if it requires special setup code, you should implement that in
1319          * platform_8bit_width().
1320          */
1321         if (host->ops->platform_8bit_width)
1322                 host->ops->platform_8bit_width(host, ios->bus_width);
1323         else {
1324                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1325                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1326                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1327                         if (host->version >= SDHCI_SPEC_300)
1328                                 ctrl |= SDHCI_CTRL_8BITBUS;
1329                 } else {
1330                         if (host->version >= SDHCI_SPEC_300)
1331                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1332                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1333                                 ctrl |= SDHCI_CTRL_4BITBUS;
1334                         else
1335                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1336                 }
1337                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1338         }
1339
1340         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1341
1342         if ((ios->timing == MMC_TIMING_SD_HS ||
1343              ios->timing == MMC_TIMING_MMC_HS)
1344             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1345                 ctrl |= SDHCI_CTRL_HISPD;
1346         else
1347                 ctrl &= ~SDHCI_CTRL_HISPD;
1348
1349         if (host->version >= SDHCI_SPEC_300) {
1350                 u16 clk, ctrl_2;
1351                 unsigned int clock;
1352
1353                 /* In case of UHS-I modes, set High Speed Enable */
1354                 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1355                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1356                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1357                     (ios->timing == MMC_TIMING_UHS_SDR25) ||
1358                     (ios->timing == MMC_TIMING_UHS_SDR12))
1359                         ctrl |= SDHCI_CTRL_HISPD;
1360
1361                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1362                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1363                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1364                         /*
1365                          * We only need to set Driver Strength if the
1366                          * preset value enable is not set.
1367                          */
1368                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1369                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1370                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1371                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1372                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1373
1374                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1375                 } else {
1376                         /*
1377                          * According to SDHC Spec v3.00, if the Preset Value
1378                          * Enable in the Host Control 2 register is set, we
1379                          * need to reset SD Clock Enable before changing High
1380                          * Speed Enable to avoid generating clock gliches.
1381                          */
1382
1383                         /* Reset SD Clock Enable */
1384                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1385                         clk &= ~SDHCI_CLOCK_CARD_EN;
1386                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1387
1388                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1389
1390                         /* Re-enable SD Clock */
1391                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1392                         clk |= SDHCI_CLOCK_CARD_EN;
1393                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1394                 }
1395
1396
1397                 /* Reset SD Clock Enable */
1398                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1399                 clk &= ~SDHCI_CLOCK_CARD_EN;
1400                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1401
1402                 if (host->ops->set_uhs_signaling)
1403                         host->ops->set_uhs_signaling(host, ios->timing);
1404                 else {
1405                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1406                         /* Select Bus Speed Mode for host */
1407                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1408                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1409                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1410                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1411                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1412                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1413                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1414                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1415                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1416                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1417                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1418                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1419                 }
1420
1421                 /* Re-enable SD Clock */
1422                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1423                 clk |= SDHCI_CLOCK_CARD_EN;
1424                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1425         } else
1426                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1427
1428         /*
1429          * Some (ENE) controllers go apeshit on some ios operation,
1430          * signalling timeout and CRC errors even on CMD0. Resetting
1431          * it on each ios seems to solve the problem.
1432          */
1433         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1434                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1435
1436 out:
1437         mmiowb();
1438         spin_unlock_irqrestore(&host->lock, flags);
1439         /*
1440          * Controller clock should only be disabled after all the register
1441          * writes are done.
1442          */
1443         if (!ios->clock && host->ops->set_clock)
1444                 host->ops->set_clock(host, ios->clock);
1445 }
1446
1447 static int check_ro(struct sdhci_host *host)
1448 {
1449         unsigned long flags;
1450         int is_readonly;
1451
1452         spin_lock_irqsave(&host->lock, flags);
1453
1454         if (host->flags & SDHCI_DEVICE_DEAD)
1455                 is_readonly = 0;
1456         else if (host->ops->get_ro)
1457                 is_readonly = host->ops->get_ro(host);
1458         else
1459                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1460                                 & SDHCI_WRITE_PROTECT);
1461
1462         spin_unlock_irqrestore(&host->lock, flags);
1463
1464         /* This quirk needs to be replaced by a callback-function later */
1465         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1466                 !is_readonly : is_readonly;
1467 }
1468
1469 #define SAMPLE_COUNT    5
1470
1471 static int sdhci_get_ro(struct mmc_host *mmc)
1472 {
1473         struct sdhci_host *host;
1474         int i, ro_count;
1475
1476         host = mmc_priv(mmc);
1477
1478         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1479                 return check_ro(host);
1480
1481         ro_count = 0;
1482         for (i = 0; i < SAMPLE_COUNT; i++) {
1483                 if (check_ro(host)) {
1484                         if (++ro_count > SAMPLE_COUNT / 2)
1485                                 return 1;
1486                 }
1487                 msleep(30);
1488         }
1489         return 0;
1490 }
1491
1492 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1493 {
1494         struct sdhci_host *host;
1495         unsigned long flags;
1496
1497         host = mmc_priv(mmc);
1498
1499         spin_lock_irqsave(&host->lock, flags);
1500
1501         if (host->flags & SDHCI_DEVICE_DEAD)
1502                 goto out;
1503
1504         if (enable)
1505                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1506         else
1507                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1508 out:
1509         mmiowb();
1510
1511         spin_unlock_irqrestore(&host->lock, flags);
1512 }
1513
1514 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1515         struct mmc_ios *ios)
1516 {
1517         struct sdhci_host *host;
1518         u8 pwr;
1519         u16 clk, ctrl;
1520         u32 present_state;
1521
1522         host = mmc_priv(mmc);
1523
1524         /*
1525          * Signal Voltage Switching is only applicable for Host Controllers
1526          * v3.00 and above.
1527          */
1528         if (host->version < SDHCI_SPEC_300)
1529                 return 0;
1530
1531         if (host->quirks & SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING) {
1532                 if (host->ops->switch_signal_voltage)
1533                         return host->ops->switch_signal_voltage(
1534                                 host, ios->signal_voltage);
1535         }
1536
1537         /*
1538          * We first check whether the request is to set signalling voltage
1539          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1540          */
1541         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1542         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1543                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1544                 ctrl &= ~SDHCI_CTRL_VDD_180;
1545                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1546
1547                 /* Wait for 5ms */
1548                 usleep_range(5000, 5500);
1549
1550                 /* 3.3V regulator output should be stable within 5 ms */
1551                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1552                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1553                         return 0;
1554                 else {
1555                         printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1556                                 "signalling voltage failed\n");
1557                         return -EIO;
1558                 }
1559         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1560                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1561                 /* Stop SDCLK */
1562                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1563                 clk &= ~SDHCI_CLOCK_CARD_EN;
1564                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1565
1566                 /* Check whether DAT[3:0] is 0000 */
1567                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1568                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1569                        SDHCI_DATA_LVL_SHIFT)) {
1570                         /*
1571                          * Enable 1.8V Signal Enable in the Host Control2
1572                          * register
1573                          */
1574                         ctrl |= SDHCI_CTRL_VDD_180;
1575                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1576
1577                         /* Wait for 5ms */
1578                         usleep_range(5000, 5500);
1579                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1580                         if (ctrl & SDHCI_CTRL_VDD_180) {
1581                                 /* Provide SDCLK again and wait for 1ms*/
1582                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1583                                 clk |= SDHCI_CLOCK_CARD_EN;
1584                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1585                                 usleep_range(1000, 1500);
1586
1587                                 /*
1588                                  * If DAT[3:0] level is 1111b, then the card
1589                                  * was successfully switched to 1.8V signaling.
1590                                  */
1591                                 present_state = sdhci_readl(host,
1592                                                         SDHCI_PRESENT_STATE);
1593                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1594                                      SDHCI_DATA_LVL_MASK)
1595                                         return 0;
1596                         }
1597                 }
1598
1599                 /*
1600                  * If we are here, that means the switch to 1.8V signaling
1601                  * failed. We power cycle the card, and retry initialization
1602                  * sequence by setting S18R to 0.
1603                  */
1604                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1605                 pwr &= ~SDHCI_POWER_ON;
1606                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1607
1608                 /* Wait for 1ms as per the spec */
1609                 usleep_range(1000, 1500);
1610                 pwr |= SDHCI_POWER_ON;
1611                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1612
1613                 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1614                         "voltage failed, retrying with S18R set to 0\n");
1615                 return -EAGAIN;
1616         } else
1617                 /* No signal voltage switch required */
1618                 return 0;
1619 }
1620
1621 static int sdhci_execute_tuning(struct mmc_host *mmc)
1622 {
1623         struct sdhci_host *host;
1624         u16 ctrl;
1625         u32 ier;
1626         int tuning_loop_counter = MAX_TUNING_LOOP;
1627         unsigned long timeout;
1628         int err = 0;
1629
1630         host = mmc_priv(mmc);
1631
1632         disable_irq(host->irq);
1633         spin_lock(&host->lock);
1634
1635         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1636
1637         /*
1638          * Host Controller needs tuning only in case of SDR104 mode
1639          * and for SDR50 mode when Use Tuning for SDR50 is set in
1640          * Capabilities register.
1641          */
1642         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1643             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1644             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1645                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1646         else {
1647                 spin_unlock(&host->lock);
1648                 enable_irq(host->irq);
1649                 return 0;
1650         }
1651
1652         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1653
1654         /*
1655          * As per the Host Controller spec v3.00, tuning command
1656          * generates Buffer Read Ready interrupt, so enable that.
1657          *
1658          * Note: The spec clearly says that when tuning sequence
1659          * is being performed, the controller does not generate
1660          * interrupts other than Buffer Read Ready interrupt. But
1661          * to make sure we don't hit a controller bug, we _only_
1662          * enable Buffer Read Ready interrupt here.
1663          */
1664         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1665         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1666
1667         /*
1668          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1669          * of loops reaches 40 times or a timeout of 150ms occurs.
1670          */
1671         timeout = 150;
1672         do {
1673                 struct mmc_command cmd = {0};
1674                 struct mmc_request mrq = {0};
1675
1676                 if (!tuning_loop_counter && !timeout)
1677                         break;
1678
1679                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1680                 cmd.arg = 0;
1681                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1682                 cmd.retries = 0;
1683                 cmd.data = NULL;
1684                 cmd.error = 0;
1685
1686                 mrq.cmd = &cmd;
1687                 host->mrq = &mrq;
1688
1689                 /*
1690                  * In response to CMD19, the card sends 64 bytes of tuning
1691                  * block to the Host Controller. So we set the block size
1692                  * to 64 here.
1693                  */
1694                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1695
1696                 /*
1697                  * The tuning block is sent by the card to the host controller.
1698                  * So we set the TRNS_READ bit in the Transfer Mode register.
1699                  * This also takes care of setting DMA Enable and Multi Block
1700                  * Select in the same register to 0.
1701                  */
1702                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1703
1704                 sdhci_send_command(host, &cmd);
1705
1706                 host->cmd = NULL;
1707                 host->mrq = NULL;
1708
1709                 spin_unlock(&host->lock);
1710                 enable_irq(host->irq);
1711
1712                 /* Wait for Buffer Read Ready interrupt */
1713                 wait_event_interruptible_timeout(host->buf_ready_int,
1714                                         (host->tuning_done == 1),
1715                                         msecs_to_jiffies(50));
1716                 disable_irq(host->irq);
1717                 spin_lock(&host->lock);
1718
1719                 if (!host->tuning_done) {
1720                         printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1721                                 "Buffer Read Ready interrupt during tuning "
1722                                 "procedure, falling back to fixed sampling "
1723                                 "clock\n");
1724                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1725                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1726                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1727                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1728
1729                         err = -EIO;
1730                         goto out;
1731                 }
1732
1733                 host->tuning_done = 0;
1734
1735                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1736                 tuning_loop_counter--;
1737                 timeout--;
1738                 mdelay(1);
1739         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1740
1741         /*
1742          * The Host Driver has exhausted the maximum number of loops allowed,
1743          * so use fixed sampling frequency.
1744          */
1745         if (!tuning_loop_counter || !timeout) {
1746                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1747                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1748         } else {
1749                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1750                         printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1751                                 " failed, falling back to fixed sampling"
1752                                 " clock\n");
1753                         err = -EIO;
1754                 }
1755         }
1756
1757 out:
1758         /*
1759          * If this is the very first time we are here, we start the retuning
1760          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1761          * flag won't be set, we check this condition before actually starting
1762          * the timer.
1763          */
1764         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1765             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1766                 mod_timer(&host->tuning_timer, jiffies +
1767                         host->tuning_count * HZ);
1768                 /* Tuning mode 1 limits the maximum data length to 4MB */
1769                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1770         } else {
1771                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1772                 /* Reload the new initial value for timer */
1773                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1774                         mod_timer(&host->tuning_timer, jiffies +
1775                                 host->tuning_count * HZ);
1776         }
1777
1778         /*
1779          * In case tuning fails, host controllers which support re-tuning can
1780          * try tuning again at a later time, when the re-tuning timer expires.
1781          * So for these controllers, we return 0. Since there might be other
1782          * controllers who do not have this capability, we return error for
1783          * them.
1784          */
1785         if (err && host->tuning_count &&
1786             host->tuning_mode == SDHCI_TUNING_MODE_1)
1787                 err = 0;
1788
1789         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1790         spin_unlock(&host->lock);
1791         enable_irq(host->irq);
1792
1793         return err;
1794 }
1795
1796 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1797 {
1798         struct sdhci_host *host;
1799         u16 ctrl;
1800         unsigned long flags;
1801
1802         host = mmc_priv(mmc);
1803
1804         /* Host Controller v3.00 defines preset value registers */
1805         if (host->version < SDHCI_SPEC_300)
1806                 return;
1807
1808         spin_lock_irqsave(&host->lock, flags);
1809
1810         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1811
1812         /*
1813          * We only enable or disable Preset Value if they are not already
1814          * enabled or disabled respectively. Otherwise, we bail out.
1815          */
1816         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1817                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1818                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1819         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1820                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1821                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1822         }
1823
1824         spin_unlock_irqrestore(&host->lock, flags);
1825 }
1826
1827 int sdhci_enable(struct mmc_host *mmc)
1828 {
1829         struct sdhci_host *host = mmc_priv(mmc);
1830
1831         if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO)
1832                 return 0;
1833
1834         if (mmc->ios.clock) {
1835                 if (host->ops->set_clock)
1836                         host->ops->set_clock(host, mmc->ios.clock);
1837                 sdhci_set_clock(host, mmc->ios.clock);
1838         }
1839
1840         return 0;
1841 }
1842
1843 int sdhci_disable(struct mmc_host *mmc, int lazy)
1844 {
1845         struct sdhci_host *host = mmc_priv(mmc);
1846
1847         if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO)
1848                 return 0;
1849
1850         sdhci_set_clock(host, 0);
1851         if (host->ops->set_clock)
1852                 host->ops->set_clock(host, 0);
1853
1854         return 0;
1855 }
1856
1857 static const struct mmc_host_ops sdhci_ops = {
1858         .request        = sdhci_request,
1859         .set_ios        = sdhci_set_ios,
1860         .get_ro         = sdhci_get_ro,
1861         .enable         = sdhci_enable,
1862         .disable        = sdhci_disable,
1863         .enable_sdio_irq = sdhci_enable_sdio_irq,
1864         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1865         .execute_tuning                 = sdhci_execute_tuning,
1866         .enable_preset_value            = sdhci_enable_preset_value,
1867 };
1868
1869 /*****************************************************************************\
1870  *                                                                           *
1871  * Tasklets                                                                  *
1872  *                                                                           *
1873 \*****************************************************************************/
1874
1875 static void sdhci_tasklet_card(unsigned long param)
1876 {
1877         struct sdhci_host *host;
1878         unsigned long flags;
1879
1880         host = (struct sdhci_host*)param;
1881
1882         spin_lock_irqsave(&host->lock, flags);
1883
1884         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1885                 if (host->mrq) {
1886                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1887                                 mmc_hostname(host->mmc));
1888                         printk(KERN_ERR "%s: Resetting controller.\n",
1889                                 mmc_hostname(host->mmc));
1890
1891                         sdhci_reset(host, SDHCI_RESET_CMD);
1892                         sdhci_reset(host, SDHCI_RESET_DATA);
1893
1894                         host->mrq->cmd->error = -ENOMEDIUM;
1895                         tasklet_schedule(&host->finish_tasklet);
1896                 }
1897         }
1898
1899         spin_unlock_irqrestore(&host->lock, flags);
1900
1901         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1902 }
1903
1904 static void sdhci_tasklet_finish(unsigned long param)
1905 {
1906         struct sdhci_host *host;
1907         unsigned long flags;
1908         struct mmc_request *mrq;
1909
1910         host = (struct sdhci_host*)param;
1911
1912         /*
1913          * If this tasklet gets rescheduled while running, it will
1914          * be run again afterwards but without any active request.
1915          */
1916         if (!host->mrq)
1917                 return;
1918
1919         spin_lock_irqsave(&host->lock, flags);
1920
1921         del_timer(&host->timer);
1922
1923         mrq = host->mrq;
1924
1925         /*
1926          * The controller needs a reset of internal state machines
1927          * upon error conditions.
1928          */
1929         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1930             ((mrq->cmd && mrq->cmd->error) ||
1931                  (mrq->data && (mrq->data->error ||
1932                   (mrq->data->stop && mrq->data->stop->error))) ||
1933                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1934
1935                 /* Some controllers need this kick or reset won't work here */
1936                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1937                         unsigned int clock;
1938
1939                         /* This is to force an update */
1940                         clock = host->clock;
1941                         host->clock = 0;
1942                         if (host->ops->set_clock)
1943                                 host->ops->set_clock(host, clock);
1944                         sdhci_set_clock(host, clock);
1945                 }
1946
1947                 /* Spec says we should do both at the same time, but Ricoh
1948                    controllers do not like that. */
1949                 sdhci_reset(host, SDHCI_RESET_CMD);
1950                 sdhci_reset(host, SDHCI_RESET_DATA);
1951         }
1952
1953         host->mrq = NULL;
1954         host->cmd = NULL;
1955         host->data = NULL;
1956
1957 #ifndef SDHCI_USE_LEDS_CLASS
1958         sdhci_deactivate_led(host);
1959 #endif
1960
1961         mmiowb();
1962         spin_unlock_irqrestore(&host->lock, flags);
1963
1964         mmc_request_done(host->mmc, mrq);
1965 }
1966
1967 static void sdhci_timeout_timer(unsigned long data)
1968 {
1969         struct sdhci_host *host;
1970         unsigned long flags;
1971
1972         host = (struct sdhci_host*)data;
1973
1974         spin_lock_irqsave(&host->lock, flags);
1975
1976         if (host->mrq) {
1977                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1978                         "interrupt.\n", mmc_hostname(host->mmc));
1979                 sdhci_dumpregs(host);
1980
1981                 if (host->data) {
1982                         host->data->error = -ETIMEDOUT;
1983                         sdhci_finish_data(host);
1984                 } else {
1985                         if (host->cmd)
1986                                 host->cmd->error = -ETIMEDOUT;
1987                         else
1988                                 host->mrq->cmd->error = -ETIMEDOUT;
1989
1990                         tasklet_schedule(&host->finish_tasklet);
1991                 }
1992         }
1993
1994         mmiowb();
1995         spin_unlock_irqrestore(&host->lock, flags);
1996 }
1997
1998 static void sdhci_tuning_timer(unsigned long data)
1999 {
2000         struct sdhci_host *host;
2001         unsigned long flags;
2002
2003         host = (struct sdhci_host *)data;
2004
2005         spin_lock_irqsave(&host->lock, flags);
2006
2007         host->flags |= SDHCI_NEEDS_RETUNING;
2008
2009         spin_unlock_irqrestore(&host->lock, flags);
2010 }
2011
2012 /*****************************************************************************\
2013  *                                                                           *
2014  * Interrupt handling                                                        *
2015  *                                                                           *
2016 \*****************************************************************************/
2017
2018 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2019 {
2020         BUG_ON(intmask == 0);
2021
2022         if (!host->cmd) {
2023                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
2024                         "though no command operation was in progress.\n",
2025                         mmc_hostname(host->mmc), (unsigned)intmask);
2026                 sdhci_dumpregs(host);
2027                 return;
2028         }
2029
2030         if (intmask & SDHCI_INT_TIMEOUT)
2031                 host->cmd->error = -ETIMEDOUT;
2032         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2033                         SDHCI_INT_INDEX))
2034                 host->cmd->error = -EILSEQ;
2035
2036         if (host->cmd->error) {
2037                 tasklet_schedule(&host->finish_tasklet);
2038                 return;
2039         }
2040
2041         /*
2042          * The host can send and interrupt when the busy state has
2043          * ended, allowing us to wait without wasting CPU cycles.
2044          * Unfortunately this is overloaded on the "data complete"
2045          * interrupt, so we need to take some care when handling
2046          * it.
2047          *
2048          * Note: The 1.0 specification is a bit ambiguous about this
2049          *       feature so there might be some problems with older
2050          *       controllers.
2051          */
2052         if (host->cmd->flags & MMC_RSP_BUSY) {
2053                 if (host->cmd->data)
2054                         DBG("Cannot wait for busy signal when also "
2055                                 "doing a data transfer");
2056                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2057                         return;
2058
2059                 /* The controller does not support the end-of-busy IRQ,
2060                  * fall through and take the SDHCI_INT_RESPONSE */
2061         }
2062
2063         if (intmask & SDHCI_INT_RESPONSE)
2064                 sdhci_finish_command(host);
2065 }
2066
2067 #ifdef CONFIG_MMC_DEBUG
2068 static void sdhci_show_adma_error(struct sdhci_host *host)
2069 {
2070         const char *name = mmc_hostname(host->mmc);
2071         u8 *desc = host->adma_desc;
2072         __le32 *dma;
2073         __le16 *len;
2074         u8 attr;
2075
2076         sdhci_dumpregs(host);
2077
2078         while (true) {
2079                 dma = (__le32 *)(desc + 4);
2080                 len = (__le16 *)(desc + 2);
2081                 attr = *desc;
2082
2083                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2084                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2085
2086                 desc += 8;
2087
2088                 if (attr & 2)
2089                         break;
2090         }
2091 }
2092 #else
2093 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2094 #endif
2095
2096 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2097 {
2098         BUG_ON(intmask == 0);
2099
2100         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2101         if (intmask & SDHCI_INT_DATA_AVAIL) {
2102                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2103                     MMC_SEND_TUNING_BLOCK) {
2104                         host->tuning_done = 1;
2105                         wake_up(&host->buf_ready_int);
2106                         return;
2107                 }
2108         }
2109
2110         if (!host->data) {
2111                 /*
2112                  * The "data complete" interrupt is also used to
2113                  * indicate that a busy state has ended. See comment
2114                  * above in sdhci_cmd_irq().
2115                  */
2116                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2117                         if (intmask & SDHCI_INT_DATA_END) {
2118                                 sdhci_finish_command(host);
2119                                 return;
2120                         }
2121                 }
2122
2123                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2124                         "though no data operation was in progress.\n",
2125                         mmc_hostname(host->mmc), (unsigned)intmask);
2126                 sdhci_dumpregs(host);
2127
2128                 return;
2129         }
2130
2131         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2132                 host->data->error = -ETIMEDOUT;
2133         else if (intmask & SDHCI_INT_DATA_END_BIT)
2134                 host->data->error = -EILSEQ;
2135         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2136                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2137                         != MMC_BUS_TEST_R)
2138                 host->data->error = -EILSEQ;
2139         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2140                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2141                 sdhci_show_adma_error(host);
2142                 host->data->error = -EIO;
2143         }
2144
2145         if (host->data->error)
2146                 sdhci_finish_data(host);
2147         else {
2148                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2149                         sdhci_transfer_pio(host);
2150
2151                 /*
2152                  * We currently don't do anything fancy with DMA
2153                  * boundaries, but as we can't disable the feature
2154                  * we need to at least restart the transfer.
2155                  *
2156                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2157                  * should return a valid address to continue from, but as
2158                  * some controllers are faulty, don't trust them.
2159                  */
2160                 if (intmask & SDHCI_INT_DMA_END) {
2161                         u32 dmastart, dmanow;
2162                         dmastart = sg_dma_address(host->data->sg);
2163                         dmanow = dmastart + host->data->bytes_xfered;
2164                         /*
2165                          * Force update to the next DMA block boundary.
2166                          */
2167                         dmanow = (dmanow &
2168                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2169                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2170                         host->data->bytes_xfered = dmanow - dmastart;
2171                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2172                                 " next 0x%08x\n",
2173                                 mmc_hostname(host->mmc), dmastart,
2174                                 host->data->bytes_xfered, dmanow);
2175                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2176                 }
2177
2178                 if (intmask & SDHCI_INT_DATA_END) {
2179                         if (host->cmd) {
2180                                 /*
2181                                  * Data managed to finish before the
2182                                  * command completed. Make sure we do
2183                                  * things in the proper order.
2184                                  */
2185                                 host->data_early = 1;
2186                         } else {
2187                                 sdhci_finish_data(host);
2188                         }
2189                 }
2190         }
2191 }
2192
2193 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2194 {
2195         irqreturn_t result;
2196         struct sdhci_host* host = dev_id;
2197         u32 intmask;
2198         int cardint = 0;
2199
2200         spin_lock(&host->lock);
2201
2202         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2203
2204         if (!intmask || intmask == 0xffffffff) {
2205                 result = IRQ_NONE;
2206                 goto out;
2207         }
2208
2209         DBG("*** %s got interrupt: 0x%08x\n",
2210                 mmc_hostname(host->mmc), intmask);
2211
2212         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2213                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2214                               SDHCI_CARD_PRESENT;
2215
2216                 /*
2217                  * There is a observation on i.mx esdhc.  INSERT bit will be
2218                  * immediately set again when it gets cleared, if a card is
2219                  * inserted.  We have to mask the irq to prevent interrupt
2220                  * storm which will freeze the system.  And the REMOVE gets
2221                  * the same situation.
2222                  *
2223                  * More testing are needed here to ensure it works for other
2224                  * platforms though.
2225                  */
2226                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2227                                                 SDHCI_INT_CARD_REMOVE);
2228                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2229                                                   SDHCI_INT_CARD_INSERT);
2230
2231                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2232                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2233                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2234                 tasklet_schedule(&host->card_tasklet);
2235         }
2236
2237         if (intmask & SDHCI_INT_CMD_MASK) {
2238                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2239                         SDHCI_INT_STATUS);
2240                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2241         }
2242
2243         if (intmask & SDHCI_INT_DATA_MASK) {
2244                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2245                         SDHCI_INT_STATUS);
2246                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2247         }
2248
2249         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2250
2251         intmask &= ~SDHCI_INT_ERROR;
2252
2253         if (intmask & SDHCI_INT_BUS_POWER) {
2254                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
2255                         mmc_hostname(host->mmc));
2256                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2257         }
2258
2259         intmask &= ~SDHCI_INT_BUS_POWER;
2260
2261         if (intmask & SDHCI_INT_CARD_INT)
2262                 cardint = 1;
2263
2264         intmask &= ~SDHCI_INT_CARD_INT;
2265
2266         if (intmask) {
2267                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
2268                         mmc_hostname(host->mmc), intmask);
2269                 sdhci_dumpregs(host);
2270
2271                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2272         }
2273
2274         result = IRQ_HANDLED;
2275
2276         mmiowb();
2277 out:
2278         spin_unlock(&host->lock);
2279
2280         /*
2281          * We have to delay this as it calls back into the driver.
2282          */
2283         if (cardint)
2284                 mmc_signal_sdio_irq(host->mmc);
2285
2286         return result;
2287 }
2288
2289 /*****************************************************************************\
2290  *                                                                           *
2291  * Suspend/resume                                                            *
2292  *                                                                           *
2293 \*****************************************************************************/
2294
2295 #ifdef CONFIG_PM
2296
2297 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
2298 {
2299         int ret = 0;
2300         struct mmc_host *mmc = host->mmc;
2301
2302         sdhci_disable_card_detection(host);
2303
2304         /* Disable tuning since we are suspending */
2305         if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2306             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2307                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2308                 mod_timer(&host->tuning_timer, jiffies +
2309                         host->tuning_count * HZ);
2310         }
2311
2312         if (mmc->card && (mmc->card->type != MMC_TYPE_SDIO))
2313                 ret = mmc_suspend_host(host->mmc);
2314
2315         if (host->flags & MMC_PM_KEEP_POWER)
2316                 host->card_int_set = sdhci_readl(host, SDHCI_INT_ENABLE) &
2317                         SDHCI_INT_CARD_INT;
2318
2319         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2320
2321         if (host->vmmc)
2322                 ret = regulator_disable(host->vmmc);
2323
2324         if (host->irq)
2325                 disable_irq(host->irq);
2326
2327         return ret;
2328 }
2329
2330 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2331
2332 int sdhci_resume_host(struct sdhci_host *host)
2333 {
2334         int ret = 0;
2335         struct mmc_host *mmc = host->mmc;
2336
2337         if (host->vmmc) {
2338                 int ret = regulator_enable(host->vmmc);
2339                 if (ret)
2340                         return ret;
2341         }
2342
2343
2344         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2345                 if (host->ops->enable_dma)
2346                         host->ops->enable_dma(host);
2347         }
2348
2349         if (host->irq)
2350                 enable_irq(host->irq);
2351
2352         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2353         mmiowb();
2354
2355         if (mmc->card) {
2356                 if (mmc->card->type != MMC_TYPE_SDIO) {
2357                         ret = mmc_resume_host(host->mmc);
2358                 } else {
2359                         /* Enable card interrupt as it is overwritten in sdhci_init */
2360                         if ((mmc->caps & MMC_CAP_SDIO_IRQ) &&
2361                                 (mmc->pm_flags & MMC_PM_KEEP_POWER))
2362                                         if (host->card_int_set)
2363                                                 mmc->ops->enable_sdio_irq(mmc, true);
2364                 }
2365         }
2366
2367         sdhci_enable_card_detection(host);
2368
2369         /* Set the re-tuning expiration flag */
2370         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2371             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2372                 host->flags |= SDHCI_NEEDS_RETUNING;
2373
2374         return ret;
2375 }
2376
2377 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2378
2379 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2380 {
2381         u8 val;
2382         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2383         val |= SDHCI_WAKE_ON_INT;
2384         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2385 }
2386
2387 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2388
2389 #endif /* CONFIG_PM */
2390
2391 /*****************************************************************************\
2392  *                                                                           *
2393  * Device allocation/registration                                            *
2394  *                                                                           *
2395 \*****************************************************************************/
2396
2397 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2398         size_t priv_size)
2399 {
2400         struct mmc_host *mmc;
2401         struct sdhci_host *host;
2402
2403         WARN_ON(dev == NULL);
2404
2405         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2406         if (!mmc)
2407                 return ERR_PTR(-ENOMEM);
2408
2409         host = mmc_priv(mmc);
2410         host->mmc = mmc;
2411
2412         return host;
2413 }
2414
2415 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2416
2417 int sdhci_add_host(struct sdhci_host *host)
2418 {
2419         struct mmc_host *mmc;
2420         u32 caps[2];
2421         u32 max_current_caps;
2422         unsigned int ocr_avail;
2423         int ret;
2424
2425         WARN_ON(host == NULL);
2426         if (host == NULL)
2427                 return -EINVAL;
2428
2429         mmc = host->mmc;
2430
2431         if (debug_quirks)
2432                 host->quirks = debug_quirks;
2433
2434         sdhci_reset(host, SDHCI_RESET_ALL);
2435
2436         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2437         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2438                                 >> SDHCI_SPEC_VER_SHIFT;
2439         if (host->version > SDHCI_SPEC_300) {
2440                 printk(KERN_ERR "%s: Unknown controller version (%d). "
2441                         "You may experience problems.\n", mmc_hostname(mmc),
2442                         host->version);
2443         }
2444
2445         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2446                 sdhci_readl(host, SDHCI_CAPABILITIES);
2447
2448         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2449                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2450
2451         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2452                 host->flags |= SDHCI_USE_SDMA;
2453         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2454                 DBG("Controller doesn't have SDMA capability\n");
2455         else
2456                 host->flags |= SDHCI_USE_SDMA;
2457
2458         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2459                 (host->flags & SDHCI_USE_SDMA)) {
2460                 DBG("Disabling DMA as it is marked broken\n");
2461                 host->flags &= ~SDHCI_USE_SDMA;
2462         }
2463
2464         if ((host->version >= SDHCI_SPEC_200) &&
2465                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2466                 host->flags |= SDHCI_USE_ADMA;
2467
2468         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2469                 (host->flags & SDHCI_USE_ADMA)) {
2470                 DBG("Disabling ADMA as it is marked broken\n");
2471                 host->flags &= ~SDHCI_USE_ADMA;
2472         }
2473
2474         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2475                 if (host->ops->enable_dma) {
2476                         if (host->ops->enable_dma(host)) {
2477                                 printk(KERN_WARNING "%s: No suitable DMA "
2478                                         "available. Falling back to PIO.\n",
2479                                         mmc_hostname(mmc));
2480                                 host->flags &=
2481                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2482                         }
2483                 }
2484         }
2485
2486         if (host->flags & SDHCI_USE_ADMA) {
2487                 /*
2488                  * We need to allocate descriptors for all sg entries
2489                  * (128) and potentially one alignment transfer for
2490                  * each of those entries.
2491                  */
2492                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2493                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2494                 if (!host->adma_desc || !host->align_buffer) {
2495                         kfree(host->adma_desc);
2496                         kfree(host->align_buffer);
2497                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
2498                                 "buffers. Falling back to standard DMA.\n",
2499                                 mmc_hostname(mmc));
2500                         host->flags &= ~SDHCI_USE_ADMA;
2501                 }
2502         }
2503
2504         /*
2505          * If we use DMA, then it's up to the caller to set the DMA
2506          * mask, but PIO does not need the hw shim so we set a new
2507          * mask here in that case.
2508          */
2509         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2510                 host->dma_mask = DMA_BIT_MASK(64);
2511                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2512         }
2513
2514         if (host->version >= SDHCI_SPEC_300)
2515                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2516                         >> SDHCI_CLOCK_BASE_SHIFT;
2517         else
2518                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2519                         >> SDHCI_CLOCK_BASE_SHIFT;
2520
2521         host->max_clk *= 1000000;
2522         if (host->max_clk == 0 || host->quirks &
2523                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2524                 if (!host->ops->get_max_clock) {
2525                         printk(KERN_ERR
2526                                "%s: Hardware doesn't specify base clock "
2527                                "frequency.\n", mmc_hostname(mmc));
2528                         return -ENODEV;
2529                 }
2530                 host->max_clk = host->ops->get_max_clock(host);
2531         }
2532
2533         /*
2534          * In case of Host Controller v3.00, find out whether clock
2535          * multiplier is supported.
2536          */
2537         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2538                         SDHCI_CLOCK_MUL_SHIFT;
2539
2540         /*
2541          * In case the value in Clock Multiplier is 0, then programmable
2542          * clock mode is not supported, otherwise the actual clock
2543          * multiplier is one more than the value of Clock Multiplier
2544          * in the Capabilities Register.
2545          */
2546         if (host->clk_mul)
2547                 host->clk_mul += 1;
2548
2549         /*
2550          * Set host parameters.
2551          */
2552         mmc->ops = &sdhci_ops;
2553         mmc->f_max = host->max_clk;
2554         if (host->ops->get_min_clock)
2555                 mmc->f_min = host->ops->get_min_clock(host);
2556         else if (host->version >= SDHCI_SPEC_300) {
2557                 if (host->clk_mul) {
2558                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2559                         mmc->f_max = host->max_clk * host->clk_mul;
2560                 } else
2561                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2562         } else
2563                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2564
2565         host->timeout_clk =
2566                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2567         if (host->timeout_clk == 0) {
2568                 if (host->ops->get_timeout_clock) {
2569                         host->timeout_clk = host->ops->get_timeout_clock(host);
2570                 } else if (!(host->quirks &
2571                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2572                         printk(KERN_ERR
2573                                "%s: Hardware doesn't specify timeout clock "
2574                                "frequency.\n", mmc_hostname(mmc));
2575                         return -ENODEV;
2576                 }
2577         }
2578         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2579                 host->timeout_clk *= 1000;
2580
2581         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2582                 host->timeout_clk = mmc->f_max / 1000;
2583
2584         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2585
2586         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2587                 host->flags |= SDHCI_AUTO_CMD12;
2588
2589         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2590         if ((host->version >= SDHCI_SPEC_300) &&
2591             ((host->flags & SDHCI_USE_ADMA) ||
2592              !(host->flags & SDHCI_USE_SDMA))) {
2593                 host->flags |= SDHCI_AUTO_CMD23;
2594                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2595         } else {
2596                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2597         }
2598
2599         /*
2600          * A controller may support 8-bit width, but the board itself
2601          * might not have the pins brought out.  Boards that support
2602          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2603          * their platform code before calling sdhci_add_host(), and we
2604          * won't assume 8-bit width for hosts without that CAP.
2605          */
2606         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2607                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2608
2609         if (caps[0] & SDHCI_CAN_DO_HISPD)
2610                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2611
2612         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2613             mmc_card_is_removable(mmc))
2614                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2615
2616         /* UHS-I mode(s) supported by the host controller. */
2617         if (host->version >= SDHCI_SPEC_300)
2618                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2619
2620         /* SDR104 supports also implies SDR50 support */
2621         if (caps[1] & SDHCI_SUPPORT_SDR104)
2622                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2623         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2624                 mmc->caps |= MMC_CAP_UHS_SDR50;
2625
2626         if (caps[1] & SDHCI_SUPPORT_DDR50)
2627                 mmc->caps |= MMC_CAP_UHS_DDR50;
2628
2629         /* Does the host needs tuning for SDR50? */
2630         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2631                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2632
2633         /* Driver Type(s) (A, C, D) supported by the host */
2634         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2635                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2636         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2637                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2638         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2639                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2640
2641         /* Initial value for re-tuning timer count */
2642         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2643                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2644
2645         /*
2646          * In case Re-tuning Timer is not disabled, the actual value of
2647          * re-tuning timer will be 2 ^ (n - 1).
2648          */
2649         if (host->tuning_count)
2650                 host->tuning_count = 1 << (host->tuning_count - 1);
2651
2652         /* Re-tuning mode supported by the Host Controller */
2653         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2654                              SDHCI_RETUNING_MODE_SHIFT;
2655
2656         ocr_avail = 0;
2657         /*
2658          * According to SD Host Controller spec v3.00, if the Host System
2659          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2660          * the value is meaningful only if Voltage Support in the Capabilities
2661          * register is set. The actual current value is 4 times the register
2662          * value.
2663          */
2664         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2665
2666         if (caps[0] & SDHCI_CAN_VDD_330) {
2667                 int max_current_330;
2668
2669                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2670
2671                 max_current_330 = ((max_current_caps &
2672                                    SDHCI_MAX_CURRENT_330_MASK) >>
2673                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2674                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2675
2676                 if (max_current_330 > 150)
2677                         mmc->caps |= MMC_CAP_SET_XPC_330;
2678         }
2679         if (caps[0] & SDHCI_CAN_VDD_300) {
2680                 int max_current_300;
2681
2682                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2683
2684                 max_current_300 = ((max_current_caps &
2685                                    SDHCI_MAX_CURRENT_300_MASK) >>
2686                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2687                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2688
2689                 if (max_current_300 > 150)
2690                         mmc->caps |= MMC_CAP_SET_XPC_300;
2691         }
2692         if (caps[0] & SDHCI_CAN_VDD_180) {
2693                 int max_current_180;
2694
2695                 ocr_avail |= MMC_VDD_165_195;
2696
2697                 max_current_180 = ((max_current_caps &
2698                                    SDHCI_MAX_CURRENT_180_MASK) >>
2699                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2700                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2701
2702                 if (max_current_180 > 150)
2703                         mmc->caps |= MMC_CAP_SET_XPC_180;
2704
2705                 /* Maximum current capabilities of the host at 1.8V */
2706                 if (max_current_180 >= 800)
2707                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2708                 else if (max_current_180 >= 600)
2709                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2710                 else if (max_current_180 >= 400)
2711                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2712                 else
2713                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2714         }
2715
2716         mmc->ocr_avail = ocr_avail;
2717         mmc->ocr_avail_sdio = ocr_avail;
2718         if (host->ocr_avail_sdio)
2719                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2720         mmc->ocr_avail_sd = ocr_avail;
2721         if (host->ocr_avail_sd)
2722                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2723         else /* normal SD controllers don't support 1.8V */
2724                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2725         mmc->ocr_avail_mmc = ocr_avail;
2726         if (host->ocr_avail_mmc)
2727                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2728
2729         if (mmc->ocr_avail == 0) {
2730                 printk(KERN_ERR "%s: Hardware doesn't report any "
2731                         "support voltages.\n", mmc_hostname(mmc));
2732                 return -ENODEV;
2733         }
2734
2735         spin_lock_init(&host->lock);
2736
2737         /*
2738          * Maximum number of segments. Depends on if the hardware
2739          * can do scatter/gather or not.
2740          */
2741         if (host->flags & SDHCI_USE_ADMA)
2742                 mmc->max_segs = 128;
2743         else if (host->flags & SDHCI_USE_SDMA)
2744                 mmc->max_segs = 1;
2745         else /* PIO */
2746                 mmc->max_segs = 128;
2747
2748         /*
2749          * Maximum number of sectors in one transfer. Limited by DMA boundary
2750          * size (512KiB).
2751          */
2752         mmc->max_req_size = 524288;
2753
2754         /*
2755          * Maximum segment size. Could be one segment with the maximum number
2756          * of bytes. When doing hardware scatter/gather, each entry cannot
2757          * be larger than 64 KiB though.
2758          */
2759         if (host->flags & SDHCI_USE_ADMA) {
2760                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2761                         mmc->max_seg_size = 65535;
2762                 else
2763                         mmc->max_seg_size = 65536;
2764         } else {
2765                 mmc->max_seg_size = mmc->max_req_size;
2766         }
2767
2768         /*
2769          * Maximum block size. This varies from controller to controller and
2770          * is specified in the capabilities register.
2771          */
2772         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2773                 mmc->max_blk_size = 2;
2774         } else {
2775                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2776                                 SDHCI_MAX_BLOCK_SHIFT;
2777                 if (mmc->max_blk_size >= 3) {
2778                         printk(KERN_WARNING "%s: Invalid maximum block size, "
2779                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2780                         mmc->max_blk_size = 0;
2781                 }
2782         }
2783
2784         mmc->max_blk_size = 512 << mmc->max_blk_size;
2785
2786         /*
2787          * Maximum block count.
2788          */
2789         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2790
2791         /*
2792          * Init tasklets.
2793          */
2794         tasklet_init(&host->card_tasklet,
2795                 sdhci_tasklet_card, (unsigned long)host);
2796         tasklet_init(&host->finish_tasklet,
2797                 sdhci_tasklet_finish, (unsigned long)host);
2798
2799         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2800
2801         if (host->version >= SDHCI_SPEC_300) {
2802                 init_waitqueue_head(&host->buf_ready_int);
2803
2804                 /* Initialize re-tuning timer */
2805                 init_timer(&host->tuning_timer);
2806                 host->tuning_timer.data = (unsigned long)host;
2807                 host->tuning_timer.function = sdhci_tuning_timer;
2808         }
2809
2810         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2811                 mmc_hostname(mmc), host);
2812         if (ret)
2813                 goto untasklet;
2814
2815         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2816         if (IS_ERR(host->vmmc)) {
2817                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2818                 host->vmmc = NULL;
2819         } else {
2820                 regulator_enable(host->vmmc);
2821         }
2822
2823         sdhci_init(host, 0);
2824
2825 #ifdef CONFIG_MMC_DEBUG
2826         sdhci_dumpregs(host);
2827 #endif
2828
2829 #ifdef SDHCI_USE_LEDS_CLASS
2830         snprintf(host->led_name, sizeof(host->led_name),
2831                 "%s::", mmc_hostname(mmc));
2832         host->led.name = host->led_name;
2833         host->led.brightness = LED_OFF;
2834         host->led.default_trigger = mmc_hostname(mmc);
2835         host->led.brightness_set = sdhci_led_control;
2836
2837         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2838         if (ret)
2839                 goto reset;
2840 #endif
2841
2842         mmiowb();
2843
2844         mmc_add_host(mmc);
2845
2846         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2847                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2848                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2849                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2850
2851         sdhci_enable_card_detection(host);
2852
2853         return 0;
2854
2855 #ifdef SDHCI_USE_LEDS_CLASS
2856 reset:
2857         sdhci_reset(host, SDHCI_RESET_ALL);
2858         free_irq(host->irq, host);
2859 #endif
2860 untasklet:
2861         tasklet_kill(&host->card_tasklet);
2862         tasklet_kill(&host->finish_tasklet);
2863
2864         return ret;
2865 }
2866
2867 EXPORT_SYMBOL_GPL(sdhci_add_host);
2868
2869 void sdhci_remove_host(struct sdhci_host *host, int dead)
2870 {
2871         unsigned long flags;
2872
2873         if (dead) {
2874                 spin_lock_irqsave(&host->lock, flags);
2875
2876                 host->flags |= SDHCI_DEVICE_DEAD;
2877
2878                 if (host->mrq) {
2879                         printk(KERN_ERR "%s: Controller removed during "
2880                                 " transfer!\n", mmc_hostname(host->mmc));
2881
2882                         host->mrq->cmd->error = -ENOMEDIUM;
2883                         tasklet_schedule(&host->finish_tasklet);
2884                 }
2885
2886                 spin_unlock_irqrestore(&host->lock, flags);
2887         }
2888
2889         sdhci_disable_card_detection(host);
2890
2891         mmc_remove_host(host->mmc);
2892
2893 #ifdef SDHCI_USE_LEDS_CLASS
2894         led_classdev_unregister(&host->led);
2895 #endif
2896
2897         if (!dead)
2898                 sdhci_reset(host, SDHCI_RESET_ALL);
2899
2900         free_irq(host->irq, host);
2901
2902         del_timer_sync(&host->timer);
2903         if (host->version >= SDHCI_SPEC_300)
2904                 del_timer_sync(&host->tuning_timer);
2905
2906         tasklet_kill(&host->card_tasklet);
2907         tasklet_kill(&host->finish_tasklet);
2908
2909         if (host->vmmc) {
2910                 regulator_disable(host->vmmc);
2911                 regulator_put(host->vmmc);
2912         }
2913
2914         kfree(host->adma_desc);
2915         kfree(host->align_buffer);
2916
2917         host->adma_desc = NULL;
2918         host->align_buffer = NULL;
2919 }
2920
2921 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2922
2923 void sdhci_free_host(struct sdhci_host *host)
2924 {
2925         mmc_free_host(host->mmc);
2926 }
2927
2928 EXPORT_SYMBOL_GPL(sdhci_free_host);
2929
2930 /*****************************************************************************\
2931  *                                                                           *
2932  * Driver init/exit                                                          *
2933  *                                                                           *
2934 \*****************************************************************************/
2935
2936 static int __init sdhci_drv_init(void)
2937 {
2938         printk(KERN_INFO DRIVER_NAME
2939                 ": Secure Digital Host Controller Interface driver\n");
2940         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2941
2942         return 0;
2943 }
2944
2945 static void __exit sdhci_drv_exit(void)
2946 {
2947 }
2948
2949 module_init(sdhci_drv_init);
2950 module_exit(sdhci_drv_exit);
2951
2952 module_param(debug_quirks, uint, 0444);
2953
2954 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2955 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2956 MODULE_LICENSE("GPL");
2957
2958 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");