2 * Copyright (C) 2010 Google, Inc.
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/err.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
24 #include <linux/of_gpio.h>
25 #include <linux/gpio.h>
26 #include <linux/slab.h>
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/host.h>
29 #include <linux/module.h>
30 #include <linux/mmc/sd.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/delay.h>
36 #include <mach/gpio-tegra.h>
37 #include <mach/sdhci.h>
38 #include <mach/io_dpd.h>
40 #include "sdhci-pltfm.h"
42 #define SDHCI_VENDOR_CLOCK_CNTRL 0x100
43 #define SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK 0x1
44 #define SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE 0x8
45 #define SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE 0x4
46 #define SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT 8
47 #define SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT 16
48 #define SDHCI_VENDOR_CLOCK_CNTRL_SDR50_TUNING 0x20
50 #define SDHCI_VENDOR_MISC_CNTRL 0x120
51 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT 0x8
52 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT 0x10
53 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SD_3_0 0x20
55 #define SDMMC_SDMEMCOMPPADCTRL 0x1E0
56 #define SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK 0xF
58 #define SDMMC_AUTO_CAL_CONFIG 0x1E4
59 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE 0x20000000
60 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT 0x8
61 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET 0x70
62 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET 0x62
64 #define SDHOST_1V8_OCR_MASK 0x8
65 #define SDHOST_HIGH_VOLT_MIN 2700000
66 #define SDHOST_HIGH_VOLT_MAX 3600000
67 #define SDHOST_LOW_VOLT_MIN 1800000
68 #define SDHOST_LOW_VOLT_MAX 1800000
70 #define TEGRA_SDHOST_MIN_FREQ 50000000
71 #define TEGRA2_SDHOST_STD_FREQ 50000000
72 #define TEGRA3_SDHOST_STD_FREQ 104000000
74 #define SD_SEND_TUNING_PATTERN 19
75 #define MAX_TAP_VALUES 256
77 static unsigned int tegra_sdhost_min_freq;
78 static unsigned int tegra_sdhost_std_freq;
79 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock);
80 static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci);
82 static unsigned int tegra3_sdhost_max_clk[4] = {
83 208000000, 104000000, 208000000, 104000000 };
85 struct tegra_sdhci_hw_ops{
86 /* Set the internal clk and card clk.*/
87 void (*set_card_clock)(struct sdhci_host *sdhci, unsigned int clock);
88 /* Post reset vendor registers configuration */
89 void (*sdhost_init)(struct sdhci_host *sdhci);
92 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
93 static struct tegra_sdhci_hw_ops tegra_2x_sdhci_ops = {
97 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
98 static struct tegra_sdhci_hw_ops tegra_3x_sdhci_ops = {
99 .set_card_clock = tegra_3x_sdhci_set_card_clock,
100 .sdhost_init = tegra3_sdhci_post_reset_init,
104 struct tegra_sdhci_host {
105 struct tegra_sdhci_platform_data *pdata;
107 struct regulator *vdd_io_reg;
108 struct regulator *vdd_slot_reg;
109 /* Pointer to the chip specific HW ops */
110 struct tegra_sdhci_hw_ops *hw_ops;
111 /* Host controller instance */
112 unsigned int instance;
114 unsigned int vddio_min_uv;
116 unsigned int vddio_max_uv;
117 /* max clk supported by the platform */
118 unsigned int max_clk_limit;
119 struct tegra_io_dpd *dpd;
121 bool is_rail_enabled;
124 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
128 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
129 /* Use wp_gpio here instead? */
130 val = readl(host->ioaddr + reg);
131 return val | SDHCI_WRITE_PROTECT;
134 return readl(host->ioaddr + reg);
137 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
139 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
140 if (unlikely(reg == SDHCI_HOST_VERSION)) {
141 /* Erratum: Version register is invalid in HW. */
142 return SDHCI_SPEC_200;
145 return readw(host->ioaddr + reg);
148 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
150 /* Seems like we're getting spurious timeout and crc errors, so
151 * disable signalling of them. In case of real errors software
152 * timers should take care of eventually detecting them.
154 if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
155 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
157 writel(val, host->ioaddr + reg);
159 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
160 if (unlikely(reg == SDHCI_INT_ENABLE)) {
161 /* Erratum: Must enable block gap interrupt detection */
162 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
163 if (val & SDHCI_INT_CARD_INT)
167 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
172 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
174 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
175 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
176 struct tegra_sdhci_platform_data *plat = tegra_host->pdata;
178 if (!gpio_is_valid(plat->wp_gpio))
181 return gpio_get_value(plat->wp_gpio);
184 static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci)
188 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
189 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
190 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
191 struct tegra_sdhci_platform_data *plat;
193 plat = pdev->dev.platform_data;
194 /* Set the base clock frequency */
195 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
196 vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT);
197 vendor_ctrl |= (tegra3_sdhost_max_clk[tegra_host->instance] / 1000000) <<
198 SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT;
199 vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
200 vendor_ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE;
203 if (plat->tap_delay) {
204 vendor_ctrl &= ~(0xFF <<
205 SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
206 vendor_ctrl |= (plat->tap_delay <<
207 SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
209 /* Enable frequency tuning for SDR50 mode */
210 vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDR50_TUNING;
211 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
213 /* Enable SDHOST v3.0 support */
214 misc_ctrl = sdhci_readw(sdhci, SDHCI_VENDOR_MISC_CNTRL);
215 misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_SD_3_0 |
216 SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT |
217 SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT;
218 sdhci_writew(sdhci, misc_ctrl, SDHCI_VENDOR_MISC_CNTRL);
221 static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
225 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
227 /* Select Bus Speed Mode for host */
228 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
230 case MMC_TIMING_UHS_SDR12:
231 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
233 case MMC_TIMING_UHS_SDR25:
234 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
236 case MMC_TIMING_UHS_SDR50:
237 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
239 case MMC_TIMING_UHS_SDR104:
240 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
242 case MMC_TIMING_UHS_DDR50:
243 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
247 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
249 if (uhs == MMC_TIMING_UHS_DDR50) {
250 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
251 clk &= ~(0xFF << SDHCI_DIVIDER_SHIFT);
252 clk |= 1 << SDHCI_DIVIDER_SHIFT;
253 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
258 static void tegra_sdhci_reset_exit(struct sdhci_host *sdhci, u8 mask)
260 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
261 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
263 if (mask & SDHCI_RESET_ALL) {
264 if (tegra_host->hw_ops->sdhost_init)
265 tegra_host->hw_ops->sdhost_init(sdhci);
269 static void sdhci_status_notify_cb(int card_present, void *dev_id)
271 struct sdhci_host *sdhci = (struct sdhci_host *)dev_id;
272 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
273 struct tegra_sdhci_platform_data *plat;
274 unsigned int status, oldstat;
276 pr_debug("%s: card_present %d\n", mmc_hostname(sdhci->mmc),
279 plat = pdev->dev.platform_data;
280 if (!plat->mmc_data.status) {
281 mmc_detect_change(sdhci->mmc, 0);
285 status = plat->mmc_data.status(mmc_dev(sdhci->mmc));
287 oldstat = plat->mmc_data.card_present;
288 plat->mmc_data.card_present = status;
289 if (status ^ oldstat) {
290 pr_debug("%s: Slot status change detected (%d -> %d)\n",
291 mmc_hostname(sdhci->mmc), oldstat, status);
292 if (status && !plat->mmc_data.built_in)
293 mmc_detect_change(sdhci->mmc, (5 * HZ) / 2);
295 mmc_detect_change(sdhci->mmc, 0);
299 static irqreturn_t carddetect_irq(int irq, void *data)
301 struct sdhci_host *sdhost = (struct sdhci_host *)data;
302 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
303 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
304 struct platform_device *pdev = to_platform_device(mmc_dev(sdhost->mmc));
305 struct tegra_sdhci_platform_data *plat;
307 plat = pdev->dev.platform_data;
309 tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
311 if (tegra_host->card_present) {
312 if (!tegra_host->is_rail_enabled) {
313 if (tegra_host->vdd_slot_reg)
314 regulator_enable(tegra_host->vdd_slot_reg);
315 if (tegra_host->vdd_io_reg)
316 regulator_enable(tegra_host->vdd_io_reg);
317 tegra_host->is_rail_enabled = 1;
320 if (tegra_host->is_rail_enabled) {
321 if (tegra_host->vdd_io_reg)
322 regulator_disable(tegra_host->vdd_io_reg);
323 if (tegra_host->vdd_slot_reg)
324 regulator_disable(tegra_host->vdd_slot_reg);
325 tegra_host->is_rail_enabled = 0;
329 tasklet_schedule(&sdhost->card_tasklet);
333 static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width)
335 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
336 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
337 struct tegra_sdhci_platform_data *plat = tegra_host->pdata;
340 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
341 if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
342 ctrl &= ~SDHCI_CTRL_4BITBUS;
343 ctrl |= SDHCI_CTRL_8BITBUS;
345 ctrl &= ~SDHCI_CTRL_8BITBUS;
346 if (bus_width == MMC_BUS_WIDTH_4)
347 ctrl |= SDHCI_CTRL_4BITBUS;
349 ctrl &= ~SDHCI_CTRL_4BITBUS;
351 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
355 static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci,
358 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
359 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
360 unsigned int clk_rate;
362 if (sdhci->mmc->card &&
363 mmc_card_ddr_mode(sdhci->mmc->card)) {
365 * In ddr mode, tegra sdmmc controller clock frequency
366 * should be double the card clock frequency.
368 clk_rate = clock * 2;
370 if (clock <= tegra_sdhost_min_freq)
371 clk_rate = tegra_sdhost_min_freq;
372 else if (clock <= tegra_sdhost_std_freq)
373 clk_rate = tegra_sdhost_std_freq;
378 * In SDR50 mode, run the sdmmc controller at 208MHz to ensure
379 * the core voltage is at 1.2V. If the core voltage is below 1.2V, CRC
380 * errors would occur during data transfers.
382 if ((sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50) &&
383 (clk_rate == tegra_sdhost_std_freq))
387 if (tegra_host->max_clk_limit &&
388 (clk_rate > tegra_host->max_clk_limit))
389 clk_rate = tegra_host->max_clk_limit;
391 clk_set_rate(pltfm_host->clk, clk_rate);
392 sdhci->max_clk = clk_get_rate(pltfm_host->clk);
395 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock)
399 unsigned long timeout;
402 if (clock && clock == sdhci->clock)
405 sdhci_writew(sdhci, 0, SDHCI_CLOCK_CONTROL);
409 if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
414 if (sdhci->version >= SDHCI_SPEC_300) {
415 /* Version 3.00 divisors must be a multiple of 2. */
416 if (sdhci->max_clk <= clock) {
419 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
420 if ((sdhci->max_clk / div) <= clock)
425 /* Version 2.00 divisors must be a power of 2. */
426 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
427 if ((sdhci->max_clk / div) <= clock)
434 * Tegra3 sdmmc controller internal clock will not be stabilized when
435 * we use a clock divider value greater than 4. The WAR is as follows.
436 * - Enable internal clock.
437 * - Wait for 5 usec and do a dummy write.
438 * - Poll for clk stable.
441 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
442 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
443 << SDHCI_DIVIDER_HI_SHIFT;
444 clk |= SDHCI_CLOCK_INT_EN;
445 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
447 /* Wait for 5 usec */
450 /* Do a dummy write */
451 ctrl = sdhci_readb(sdhci, SDHCI_CAPABILITIES);
453 sdhci_writeb(sdhci, ctrl, SDHCI_CAPABILITIES);
457 while (!((clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL))
458 & SDHCI_CLOCK_INT_STABLE)) {
460 dev_err(mmc_dev(sdhci->mmc), "Internal clock never stabilised\n");
467 clk |= SDHCI_CLOCK_CARD_EN;
468 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
470 sdhci->clock = clock;
473 static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock)
475 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
476 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
479 pr_debug("%s %s %u enabled=%u\n", __func__,
480 mmc_hostname(sdhci->mmc), clock, tegra_host->clk_enabled);
483 /* bring out sd instance from io dpd mode */
484 tegra_io_dpd_disable(tegra_host->dpd);
486 if (!tegra_host->clk_enabled) {
487 clk_enable(pltfm_host->clk);
488 ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
489 ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
490 sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
491 tegra_host->clk_enabled = true;
493 tegra_sdhci_set_clk_rate(sdhci, clock);
494 if (tegra_host->hw_ops->set_card_clock)
495 tegra_host->hw_ops->set_card_clock(sdhci, clock);
496 } else if (!clock && tegra_host->clk_enabled) {
497 if (tegra_host->hw_ops->set_card_clock)
498 tegra_host->hw_ops->set_card_clock(sdhci, clock);
499 ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
500 ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
501 sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
502 clk_disable(pltfm_host->clk);
503 tegra_host->clk_enabled = false;
504 /* io dpd enable call for sd instance */
505 tegra_io_dpd_enable(tegra_host->dpd);
509 static int tegra_sdhci_signal_voltage_switch(struct sdhci_host *sdhci,
510 unsigned int signal_voltage)
512 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
513 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
514 unsigned int min_uV = SDHOST_HIGH_VOLT_MIN;
515 unsigned int max_uV = SDHOST_HIGH_VOLT_MAX;
520 /* Switch OFF the card clock to prevent glitches on the clock line */
521 clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
522 clk &= ~SDHCI_CLOCK_CARD_EN;
523 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
525 ctrl = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
526 if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
527 ctrl |= SDHCI_CTRL_VDD_180;
528 min_uV = SDHOST_LOW_VOLT_MIN;
529 max_uV = SDHOST_LOW_VOLT_MAX;
530 } else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
531 if (ctrl & SDHCI_CTRL_VDD_180)
532 ctrl &= ~SDHCI_CTRL_VDD_180;
534 sdhci_writew(sdhci, ctrl, SDHCI_HOST_CONTROL2);
536 /* Switch the I/O rail voltage */
537 if (tegra_host->vdd_io_reg) {
538 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
541 dev_err(mmc_dev(sdhci->mmc), "switching to 1.8V"
542 "failed . Switching back to 3.3V\n");
543 regulator_set_voltage(tegra_host->vdd_io_reg,
544 SDHOST_HIGH_VOLT_MIN,
545 SDHOST_HIGH_VOLT_MAX);
550 /* Wait for 10 msec for the voltage to be switched */
553 /* Enable the card clock */
554 clk |= SDHCI_CLOCK_CARD_EN;
555 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
557 /* Wait for 1 msec after enabling clock */
560 if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
561 /* Do Auto Calibration for 1.8V signal voltage */
562 val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
563 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
564 /* Program Auto cal PD offset(bits 8:14) */
566 SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
567 val |= (SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET <<
568 SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
569 /* Program Auto cal PU offset(bits 0:6) */
571 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET;
572 sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
574 val = sdhci_readl(sdhci, SDMMC_SDMEMCOMPPADCTRL);
575 val &= ~SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK;
577 sdhci_writel(sdhci, val, SDMMC_SDMEMCOMPPADCTRL);
582 /* Enable the card clock */
583 clk |= SDHCI_CLOCK_CARD_EN;
584 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
586 /* Wait for 1 msec for the clock to stabilize */
592 static void tegra_sdhci_reset(struct sdhci_host *sdhci, u8 mask)
594 unsigned long timeout;
596 sdhci_writeb(sdhci, mask, SDHCI_SOFTWARE_RESET);
598 /* Wait max 100 ms */
601 /* hw clears the bit when it's done */
602 while (sdhci_readb(sdhci, SDHCI_SOFTWARE_RESET) & mask) {
604 dev_err(mmc_dev(sdhci->mmc), "Reset 0x%x never"
605 "completed.\n", (int)mask);
613 static void sdhci_tegra_set_tap_delay(struct sdhci_host *sdhci,
614 unsigned int tap_delay)
618 /* Max tap delay value is 255 */
619 BUG_ON(tap_delay > MAX_TAP_VALUES);
621 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
622 vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
623 vendor_ctrl |= (tap_delay << SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
624 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
627 static void sdhci_tegra_clear_set_irqs(struct sdhci_host *host,
632 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
635 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
636 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
639 static int sdhci_tegra_run_frequency_tuning(struct sdhci_host *sdhci)
645 unsigned int timeout = 10;
650 * As per the Host Controller spec v3.00, tuning command
651 * generates Buffer Read Ready interrupt only, so enable that.
653 ier = sdhci_readl(sdhci, SDHCI_INT_ENABLE);
654 sdhci_tegra_clear_set_irqs(sdhci, ier, SDHCI_INT_DATA_AVAIL |
657 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
658 while (sdhci_readl(sdhci, SDHCI_PRESENT_STATE) & mask) {
660 dev_err(mmc_dev(sdhci->mmc), "Controller never"
661 "released inhibit bit(s).\n");
669 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
670 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
671 sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
673 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
674 ctrl |= SDHCI_CTRL_EXEC_TUNING;
675 sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
678 * In response to CMD19, the card sends 64 bytes of tuning
679 * block to the Host Controller. So we set the block size
682 sdhci_writew(sdhci, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
684 sdhci_writeb(sdhci, 0xE, SDHCI_TIMEOUT_CONTROL);
686 sdhci_writeb(sdhci, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
688 sdhci_writel(sdhci, 0x0, SDHCI_ARGUMENT);
690 /* Set the cmd flags */
691 flags = SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_DATA;
692 /* Issue the command */
693 sdhci_writew(sdhci, SDHCI_MAKE_CMD(
694 SD_SEND_TUNING_PATTERN, flags), SDHCI_COMMAND);
700 intstatus = sdhci_readl(sdhci, SDHCI_INT_STATUS);
702 sdhci_writel(sdhci, intstatus, SDHCI_INT_STATUS);
707 if ((intstatus & SDHCI_INT_DATA_AVAIL) &&
708 !(intstatus & SDHCI_INT_DATA_CRC)) {
710 sdhci->tuning_done = 1;
712 tegra_sdhci_reset(sdhci, SDHCI_RESET_CMD);
713 tegra_sdhci_reset(sdhci, SDHCI_RESET_DATA);
717 if (sdhci->tuning_done) {
718 sdhci->tuning_done = 0;
719 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
720 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING) &&
721 (ctrl & SDHCI_CTRL_TUNED_CLK))
728 sdhci_tegra_clear_set_irqs(sdhci, SDHCI_INT_DATA_AVAIL, ier);
732 static int sdhci_tegra_execute_tuning(struct sdhci_host *sdhci)
736 u8 *tap_delay_status;
738 unsigned int temp_low_pass_tap = 0;
739 unsigned int temp_pass_window = 0;
740 unsigned int best_low_pass_tap = 0;
741 unsigned int best_pass_window = 0;
743 /* Tuning is valid only in SDR104 and SDR50 modes */
744 ctrl_2 = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
745 if (!(((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
746 (((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
747 (sdhci->flags & SDHCI_SDR50_NEEDS_TUNING))))
750 tap_delay_status = kzalloc(MAX_TAP_VALUES, GFP_KERNEL);
751 if (tap_delay_status == NULL) {
752 dev_err(mmc_dev(sdhci->mmc), "failed to allocate memory"
753 "for storing tap_delay_status\n");
759 * Set each tap delay value and run frequency tuning. After each
760 * run, update the tap delay status as working or not working.
763 /* Set the tap delay */
764 sdhci_tegra_set_tap_delay(sdhci, i);
766 /* Run frequency tuning */
767 err = sdhci_tegra_run_frequency_tuning(sdhci);
769 /* Update whether the tap delay worked or not */
770 tap_delay_status[i] = (err) ? 0: 1;
774 /* Find the best possible tap range */
775 for (i = 0; i < 0xFF; i++) {
776 temp_pass_window = 0;
778 /* Find the first passing tap in the current window */
779 if (tap_delay_status[i]) {
780 temp_low_pass_tap = i;
782 /* Find the pass window */
788 } while (tap_delay_status[i]);
790 if ((temp_pass_window > best_pass_window) && (temp_pass_window > 1)){
791 best_low_pass_tap = temp_low_pass_tap;
792 best_pass_window = temp_pass_window;
798 pr_debug("%s: best pass tap window: start %d, end %d\n",
799 mmc_hostname(sdhci->mmc), best_low_pass_tap,
800 (best_low_pass_tap + best_pass_window));
802 /* Set the best tap */
803 sdhci_tegra_set_tap_delay(sdhci,
804 (best_low_pass_tap + ((best_pass_window * 3) / 4)));
806 /* Run frequency tuning */
807 err = sdhci_tegra_run_frequency_tuning(sdhci);
810 if (tap_delay_status)
811 kfree(tap_delay_status);
816 static int tegra_sdhci_suspend(struct sdhci_host *sdhci)
818 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
819 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
821 tegra_sdhci_set_clock(sdhci, 0);
823 /* Disable the power rails if any */
824 if (tegra_host->card_present) {
825 if (tegra_host->is_rail_enabled) {
826 if (tegra_host->vdd_io_reg)
827 regulator_disable(tegra_host->vdd_io_reg);
828 if (tegra_host->vdd_slot_reg)
829 regulator_disable(tegra_host->vdd_slot_reg);
830 tegra_host->is_rail_enabled = 0;
837 static int tegra_sdhci_resume(struct sdhci_host *sdhci)
839 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
840 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
842 /* Enable the power rails if any */
843 if (tegra_host->card_present) {
844 if (!tegra_host->is_rail_enabled) {
845 if (tegra_host->vdd_slot_reg)
846 regulator_enable(tegra_host->vdd_slot_reg);
847 if (tegra_host->vdd_io_reg) {
848 regulator_enable(tegra_host->vdd_io_reg);
849 tegra_sdhci_signal_voltage_switch(sdhci, MMC_SIGNAL_VOLTAGE_330);
851 tegra_host->is_rail_enabled = 1;
854 /* Setting the min identification clock of freq 400KHz */
855 tegra_sdhci_set_clock(sdhci, 400000);
857 /* Reset the controller and power on if MMC_KEEP_POWER flag is set*/
858 if (sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER) {
859 tegra_sdhci_reset(sdhci, SDHCI_RESET_ALL);
860 sdhci_writeb(sdhci, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
867 static struct sdhci_ops tegra_sdhci_ops = {
868 .get_ro = tegra_sdhci_get_ro,
869 .read_l = tegra_sdhci_readl,
870 .read_w = tegra_sdhci_readw,
871 .write_l = tegra_sdhci_writel,
872 .platform_8bit_width = tegra_sdhci_8bit,
873 .set_clock = tegra_sdhci_set_clock,
874 .suspend = tegra_sdhci_suspend,
875 .resume = tegra_sdhci_resume,
876 .platform_reset_exit = tegra_sdhci_reset_exit,
877 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
878 .switch_signal_voltage = tegra_sdhci_signal_voltage_switch,
879 .execute_freq_tuning = sdhci_tegra_execute_tuning,
882 static struct sdhci_pltfm_data sdhci_tegra_pdata = {
883 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
884 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
885 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
886 SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING |
888 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
889 SDHCI_QUIRK_NONSTANDARD_CLOCK |
890 SDHCI_QUIRK_NON_STANDARD_TUNING |
892 SDHCI_QUIRK_SINGLE_POWER_WRITE |
893 SDHCI_QUIRK_NO_HISPD_BIT |
894 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
895 SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO,
896 .ops = &tegra_sdhci_ops,
899 static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = {
900 { .compatible = "nvidia,tegra20-sdhci", },
903 MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
905 static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata(
906 struct platform_device *pdev)
908 struct tegra_sdhci_platform_data *plat;
909 struct device_node *np = pdev->dev.of_node;
914 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
916 dev_err(&pdev->dev, "Can't allocate platform data\n");
920 plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
921 plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
922 plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
923 if (of_find_property(np, "support-8bit", NULL))
929 static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
931 struct sdhci_pltfm_host *pltfm_host;
932 struct tegra_sdhci_platform_data *plat;
933 struct sdhci_host *host;
934 struct tegra_sdhci_host *tegra_host;
938 host = sdhci_pltfm_init(pdev, &sdhci_tegra_pdata);
940 return PTR_ERR(host);
942 pltfm_host = sdhci_priv(host);
944 plat = pdev->dev.platform_data;
947 plat = sdhci_tegra_dt_parse_pdata(pdev);
950 dev_err(mmc_dev(host->mmc), "missing platform data\n");
955 tegra_host = kzalloc(sizeof(struct tegra_sdhci_host), GFP_KERNEL);
956 if (tegra_host == NULL) {
957 dev_err(mmc_dev(host->mmc), "failed to allocate tegra host\n");
962 tegra_host->pdata = plat;
963 pltfm_host->priv = tegra_host;
965 #ifdef CONFIG_MMC_EMBEDDED_SDIO
966 if (plat->mmc_data.embedded_sdio)
967 mmc_set_embedded_sdio_data(host->mmc,
968 &plat->mmc_data.embedded_sdio->cis,
969 &plat->mmc_data.embedded_sdio->cccr,
970 plat->mmc_data.embedded_sdio->funcs,
971 plat->mmc_data.embedded_sdio->num_funcs);
974 if (gpio_is_valid(plat->power_gpio)) {
975 rc = gpio_request(plat->power_gpio, "sdhci_power");
977 dev_err(mmc_dev(host->mmc),
978 "failed to allocate power gpio\n");
981 tegra_gpio_enable(plat->power_gpio);
982 gpio_direction_output(plat->power_gpio, 1);
985 if (gpio_is_valid(plat->cd_gpio)) {
986 rc = gpio_request(plat->cd_gpio, "sdhci_cd");
988 dev_err(mmc_dev(host->mmc),
989 "failed to allocate cd gpio\n");
992 tegra_gpio_enable(plat->cd_gpio);
993 gpio_direction_input(plat->cd_gpio);
995 tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
997 rc = request_threaded_irq(gpio_to_irq(plat->cd_gpio), NULL,
999 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1000 mmc_hostname(host->mmc), host);
1003 dev_err(mmc_dev(host->mmc), "request irq error\n");
1004 goto err_cd_irq_req;
1006 rc = enable_irq_wake(gpio_to_irq(plat->cd_gpio));
1008 dev_err(mmc_dev(host->mmc),
1009 "SD card wake-up event registration"
1010 "failed with eroor: %d\n", rc);
1012 } else if (plat->mmc_data.register_status_notify) {
1013 plat->mmc_data.register_status_notify(sdhci_status_notify_cb, host);
1016 if (plat->mmc_data.status) {
1017 plat->mmc_data.card_present = plat->mmc_data.status(mmc_dev(host->mmc));
1020 if (gpio_is_valid(plat->wp_gpio)) {
1021 rc = gpio_request(plat->wp_gpio, "sdhci_wp");
1023 dev_err(mmc_dev(host->mmc),
1024 "failed to allocate wp gpio\n");
1027 tegra_gpio_enable(plat->wp_gpio);
1028 gpio_direction_input(plat->wp_gpio);
1032 if (!plat->mmc_data.built_in) {
1033 if (plat->mmc_data.ocr_mask & SDHOST_1V8_OCR_MASK) {
1034 tegra_host->vddio_min_uv = SDHOST_LOW_VOLT_MIN;
1035 tegra_host->vddio_max_uv = SDHOST_LOW_VOLT_MAX;
1038 * Set the minV and maxV to default
1039 * voltage range of 2.7V - 3.6V
1041 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_MIN;
1042 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
1044 tegra_host->vdd_io_reg = regulator_get(mmc_dev(host->mmc), "vddio_sdmmc");
1045 if (IS_ERR_OR_NULL(tegra_host->vdd_io_reg)) {
1046 dev_err(mmc_dev(host->mmc), "%s regulator not found: %ld\n",
1047 "vddio_sdmmc", PTR_ERR(tegra_host->vdd_io_reg));
1048 tegra_host->vdd_io_reg = NULL;
1050 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1051 tegra_host->vddio_min_uv,
1052 tegra_host->vddio_max_uv);
1054 dev_err(mmc_dev(host->mmc), "%s regulator_set_voltage failed: %d",
1059 tegra_host->vdd_slot_reg = regulator_get(mmc_dev(host->mmc), "vddio_sd_slot");
1060 if (IS_ERR_OR_NULL(tegra_host->vdd_slot_reg)) {
1061 dev_err(mmc_dev(host->mmc), "%s regulator not found: %ld\n",
1062 "vddio_sd_slot", PTR_ERR(tegra_host->vdd_slot_reg));
1063 tegra_host->vdd_slot_reg = NULL;
1066 if (tegra_host->card_present) {
1067 if (tegra_host->vdd_slot_reg)
1068 regulator_enable(tegra_host->vdd_slot_reg);
1069 if (tegra_host->vdd_io_reg)
1070 regulator_enable(tegra_host->vdd_io_reg);
1071 tegra_host->is_rail_enabled = 1;
1075 clk = clk_get(mmc_dev(host->mmc), NULL);
1077 dev_err(mmc_dev(host->mmc), "clk err\n");
1081 rc = clk_enable(clk);
1084 pltfm_host->clk = clk;
1085 pltfm_host->priv = tegra_host;
1086 tegra_host->clk_enabled = true;
1087 tegra_host->max_clk_limit = plat->max_clk_limit;
1088 tegra_host->instance = pdev->id;
1089 tegra_host->dpd = tegra_io_dpd_get(mmc_dev(host->mmc));
1091 host->mmc->pm_caps = plat->pm_flags;
1093 host->mmc->caps |= MMC_CAP_ERASE;
1094 host->mmc->caps |= MMC_CAP_DISABLE;
1095 /* enable 1/8V DDR capable */
1096 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1098 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
1099 host->mmc->caps |= MMC_CAP_SDIO_IRQ;
1101 if (plat->mmc_data.built_in) {
1102 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1104 /* Do not turn OFF embedded sdio cards as it support Wake on Wireless */
1105 if (plat->mmc_data.embedded_sdio)
1106 host->mmc->pm_flags = MMC_PM_KEEP_POWER;
1108 tegra_sdhost_min_freq = TEGRA_SDHOST_MIN_FREQ;
1109 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1110 tegra_host->hw_ops = &tegra_2x_sdhci_ops;
1111 tegra_sdhost_std_freq = TEGRA2_SDHOST_STD_FREQ;
1113 tegra_host->hw_ops = &tegra_3x_sdhci_ops;
1114 tegra_sdhost_std_freq = TEGRA3_SDHOST_STD_FREQ;
1117 rc = sdhci_add_host(host);
1124 clk_disable(pltfm_host->clk);
1126 clk_put(pltfm_host->clk);
1128 if (gpio_is_valid(plat->wp_gpio)) {
1129 tegra_gpio_disable(plat->wp_gpio);
1130 gpio_free(plat->wp_gpio);
1133 if (gpio_is_valid(plat->cd_gpio))
1134 free_irq(gpio_to_irq(plat->cd_gpio), host);
1136 if (gpio_is_valid(plat->cd_gpio)) {
1137 tegra_gpio_disable(plat->cd_gpio);
1138 gpio_free(plat->cd_gpio);
1141 if (gpio_is_valid(plat->power_gpio)) {
1142 tegra_gpio_disable(plat->power_gpio);
1143 gpio_free(plat->power_gpio);
1149 sdhci_pltfm_free(pdev);
1153 static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
1155 struct sdhci_host *host = platform_get_drvdata(pdev);
1156 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1157 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
1158 struct tegra_sdhci_platform_data *plat = tegra_host->pdata;
1159 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1161 sdhci_remove_host(host, dead);
1163 disable_irq_wake(gpio_to_irq(plat->cd_gpio));
1165 if (tegra_host->vdd_slot_reg) {
1166 regulator_disable(tegra_host->vdd_slot_reg);
1167 regulator_put(tegra_host->vdd_slot_reg);
1170 if (tegra_host->vdd_io_reg) {
1171 regulator_disable(tegra_host->vdd_io_reg);
1172 regulator_put(tegra_host->vdd_io_reg);
1175 if (gpio_is_valid(plat->wp_gpio)) {
1176 tegra_gpio_disable(plat->wp_gpio);
1177 gpio_free(plat->wp_gpio);
1180 if (gpio_is_valid(plat->cd_gpio)) {
1181 free_irq(gpio_to_irq(plat->cd_gpio), host);
1182 tegra_gpio_disable(plat->cd_gpio);
1183 gpio_free(plat->cd_gpio);
1186 if (gpio_is_valid(plat->power_gpio)) {
1187 tegra_gpio_disable(plat->power_gpio);
1188 gpio_free(plat->power_gpio);
1191 if (tegra_host->clk_enabled)
1192 clk_disable(pltfm_host->clk);
1193 clk_put(pltfm_host->clk);
1195 sdhci_pltfm_free(pdev);
1201 static struct platform_driver sdhci_tegra_driver = {
1203 .name = "sdhci-tegra",
1204 .owner = THIS_MODULE,
1205 .of_match_table = sdhci_tegra_dt_match,
1206 .pm = SDHCI_PLTFM_PMOPS,
1208 .probe = sdhci_tegra_probe,
1209 .remove = __devexit_p(sdhci_tegra_remove),
1212 module_platform_driver(sdhci_tegra_driver);
1214 MODULE_DESCRIPTION("SDHCI driver for Tegra");
1215 MODULE_AUTHOR(" Google, Inc.");
1216 MODULE_LICENSE("GPL v2");