2 * Copyright (C) 2010 Google, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/err.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
22 #include <linux/of_gpio.h>
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/mmc/card.h>
26 #include <linux/mmc/host.h>
27 #include <linux/module.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/delay.h>
33 #include <mach/gpio-tegra.h>
34 #include <mach/sdhci.h>
35 #include <mach/io_dpd.h>
37 #include "sdhci-pltfm.h"
39 #define SDHCI_VENDOR_CLOCK_CNTRL 0x100
40 #define SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK 0x1
41 #define SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE 0x8
42 #define SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT 8
43 #define SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT 16
45 #define SDHCI_VENDOR_MISC_CNTRL 0x120
46 #define SDHCI_VENDOR_MISC_CNTRL_SDMMC_SPARE0_ENABLE_SD_3_0 0x20
48 #define SDMMC_AUTO_CAL_CONFIG 0x1E4
49 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE 0x20000000
50 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT 0x8
51 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET 0x70
52 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET 0x62
54 #define SDHOST_1V8_OCR_MASK 0x8
55 #define SDHOST_HIGH_VOLT_MIN 2700000
56 #define SDHOST_HIGH_VOLT_MAX 3600000
57 #define SDHOST_LOW_VOLT_MIN 1800000
58 #define SDHOST_LOW_VOLT_MAX 1800000
60 #define TEGRA_SDHOST_MIN_FREQ 50000000
61 #define TEGRA2_SDHOST_STD_FREQ 50000000
62 #define TEGRA3_SDHOST_STD_FREQ 104000000
64 static unsigned int tegra_sdhost_min_freq;
65 static unsigned int tegra_sdhost_std_freq;
66 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock);
67 static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci);
69 static unsigned int tegra3_sdhost_max_clk[4] = {
70 208000000, 104000000, 208000000, 104000000 };
72 struct tegra_sdhci_hw_ops{
73 /* Set the internal clk and card clk.*/
74 void (*set_card_clock)(struct sdhci_host *sdhci, unsigned int clock);
75 /* Post reset vendor registers configuration */
76 void (*sdhost_init)(struct sdhci_host *sdhci);
79 static struct tegra_sdhci_hw_ops tegra_2x_sdhci_ops = {
82 static struct tegra_sdhci_hw_ops tegra_3x_sdhci_ops = {
83 .set_card_clock = tegra_3x_sdhci_set_card_clock,
84 .sdhost_init = tegra3_sdhci_post_reset_init,
87 struct tegra_sdhci_host {
88 struct tegra_sdhci_platform_data *pdata;
90 struct regulator *vdd_io_reg;
91 struct regulator *vdd_slot_reg;
92 /* Pointer to the chip specific HW ops */
93 struct tegra_sdhci_hw_ops *hw_ops;
94 /* Host controller instance */
95 unsigned int instance;
97 unsigned int vddio_min_uv;
99 unsigned int vddio_max_uv;
100 /* max clk supported by the platform */
101 unsigned int max_clk_limit;
102 struct tegra_io_dpd *dpd;
105 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
109 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
110 /* Use wp_gpio here instead? */
111 val = readl(host->ioaddr + reg);
112 return val | SDHCI_WRITE_PROTECT;
115 return readl(host->ioaddr + reg);
118 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
120 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
121 if (unlikely(reg == SDHCI_HOST_VERSION)) {
122 /* Erratum: Version register is invalid in HW. */
123 return SDHCI_SPEC_200;
126 return readw(host->ioaddr + reg);
129 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
131 /* Seems like we're getting spurious timeout and crc errors, so
132 * disable signalling of them. In case of real errors software
133 * timers should take care of eventually detecting them.
135 if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
136 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
138 writel(val, host->ioaddr + reg);
140 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
141 if (unlikely(reg == SDHCI_INT_ENABLE)) {
142 /* Erratum: Must enable block gap interrupt detection */
143 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
144 if (val & SDHCI_INT_CARD_INT)
148 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
153 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
155 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
156 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
157 struct tegra_sdhci_platform_data *plat = tegra_host->pdata;
159 if (!gpio_is_valid(plat->wp_gpio))
162 return gpio_get_value(plat->wp_gpio);
165 static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci)
169 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
170 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
171 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
172 struct tegra_sdhci_platform_data *plat;
174 plat = pdev->dev.platform_data;
175 /* Set the base clock frequency */
176 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
177 vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT);
178 vendor_ctrl |= (tegra3_sdhost_max_clk[tegra_host->instance] / 1000000) <<
179 SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT;
181 if (plat->tap_delay) {
182 vendor_ctrl &= ~(0xFF <<
183 SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
184 vendor_ctrl |= (plat->tap_delay <<
185 SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
187 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
189 /* Enable SDHOST v3.0 support */
190 misc_ctrl = sdhci_readw(sdhci, SDHCI_VENDOR_MISC_CNTRL);
191 misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_SDMMC_SPARE0_ENABLE_SD_3_0;
192 sdhci_writew(sdhci, misc_ctrl, SDHCI_VENDOR_MISC_CNTRL);
195 static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
199 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
201 /* Select Bus Speed Mode for host */
202 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
204 case MMC_TIMING_UHS_SDR12:
205 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
207 case MMC_TIMING_UHS_SDR25:
208 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
210 case MMC_TIMING_UHS_SDR50:
211 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
213 case MMC_TIMING_UHS_SDR104:
214 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
216 case MMC_TIMING_UHS_DDR50:
217 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
221 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
223 if (uhs == MMC_TIMING_UHS_DDR50) {
224 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
225 clk &= ~(0xFF << SDHCI_DIVIDER_SHIFT);
226 clk |= 1 << SDHCI_DIVIDER_SHIFT;
227 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
232 static void tegra_sdhci_reset_exit(struct sdhci_host *sdhci, u8 mask)
234 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
235 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
237 if (mask & SDHCI_RESET_ALL) {
238 if (tegra_host->hw_ops->sdhost_init)
239 tegra_host->hw_ops->sdhost_init(sdhci);
243 static void sdhci_status_notify_cb(int card_present, void *dev_id)
245 struct sdhci_host *sdhci = (struct sdhci_host *)dev_id;
246 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
247 struct tegra_sdhci_platform_data *plat;
248 unsigned int status, oldstat;
250 pr_debug("%s: card_present %d\n", mmc_hostname(sdhci->mmc),
253 plat = pdev->dev.platform_data;
254 if (!plat->mmc_data.status) {
255 mmc_detect_change(sdhci->mmc, 0);
259 status = plat->mmc_data.status(mmc_dev(sdhci->mmc));
261 oldstat = plat->mmc_data.card_present;
262 plat->mmc_data.card_present = status;
263 if (status ^ oldstat) {
264 pr_debug("%s: Slot status change detected (%d -> %d)\n",
265 mmc_hostname(sdhci->mmc), oldstat, status);
266 if (status && !plat->mmc_data.built_in)
267 mmc_detect_change(sdhci->mmc, (5 * HZ) / 2);
269 mmc_detect_change(sdhci->mmc, 0);
273 static irqreturn_t carddetect_irq(int irq, void *data)
275 struct sdhci_host *sdhost = (struct sdhci_host *)data;
277 tasklet_schedule(&sdhost->card_tasklet);
281 static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width)
283 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
284 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
285 struct tegra_sdhci_platform_data *plat = tegra_host->pdata;
288 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
289 if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
290 ctrl &= ~SDHCI_CTRL_4BITBUS;
291 ctrl |= SDHCI_CTRL_8BITBUS;
293 ctrl &= ~SDHCI_CTRL_8BITBUS;
294 if (bus_width == MMC_BUS_WIDTH_4)
295 ctrl |= SDHCI_CTRL_4BITBUS;
297 ctrl &= ~SDHCI_CTRL_4BITBUS;
299 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
303 static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci,
306 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
307 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
308 unsigned int clk_rate;
310 if (sdhci->mmc->card &&
311 mmc_card_ddr_mode(sdhci->mmc->card)) {
313 * In ddr mode, tegra sdmmc controller clock frequency
314 * should be double the card clock frequency.
316 clk_rate = clock * 2;
318 if (clock <= tegra_sdhost_min_freq)
319 clk_rate = tegra_sdhost_min_freq;
320 else if (clock <= tegra_sdhost_std_freq)
321 clk_rate = tegra_sdhost_std_freq;
326 if (tegra_host->max_clk_limit &&
327 (clk_rate > tegra_host->max_clk_limit))
328 clk_rate = tegra_host->max_clk_limit;
330 clk_set_rate(pltfm_host->clk, clk_rate);
331 sdhci->max_clk = clk_get_rate(pltfm_host->clk);
334 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock)
338 unsigned long timeout;
341 if (clock && clock == sdhci->clock)
344 sdhci_writew(sdhci, 0, SDHCI_CLOCK_CONTROL);
348 if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
353 if (sdhci->version >= SDHCI_SPEC_300) {
354 /* Version 3.00 divisors must be a multiple of 2. */
355 if (sdhci->max_clk <= clock) {
358 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
359 if ((sdhci->max_clk / div) <= clock)
364 /* Version 2.00 divisors must be a power of 2. */
365 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
366 if ((sdhci->max_clk / div) <= clock)
373 * Tegra3 sdmmc controller internal clock will not be stabilized when
374 * we use a clock divider value greater than 4. The WAR is as follows.
375 * - Enable PADPIPE_CLK_OVERRIDE in the vendr clk cntrl register.
376 * - Enable internal clock.
377 * - Wait for 5 usec and do a dummy write.
378 * - Poll for clk stable and disable PADPIPE_CLK_OVERRIDE.
381 /* Enable PADPIPE clk override */
382 ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
383 ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
384 sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
386 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
387 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
388 << SDHCI_DIVIDER_HI_SHIFT;
389 clk |= SDHCI_CLOCK_INT_EN;
390 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
392 /* Wait for 5 usec */
395 /* Do a dummy write */
396 ctrl = sdhci_readb(sdhci, SDHCI_CAPABILITIES);
398 sdhci_writeb(sdhci, ctrl, SDHCI_CAPABILITIES);
402 while (!((clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL))
403 & SDHCI_CLOCK_INT_STABLE)) {
405 dev_err(mmc_dev(sdhci->mmc), "Internal clock never stabilised\n");
412 /* Disable PADPIPE clk override */
413 ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
414 ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
415 sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
417 clk |= SDHCI_CLOCK_CARD_EN;
418 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
420 sdhci->clock = clock;
423 static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock)
425 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
426 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
429 pr_debug("%s %s %u enabled=%u\n", __func__,
430 mmc_hostname(sdhci->mmc), clock, tegra_host->clk_enabled);
433 /* bring out sd instance from io dpd mode */
434 tegra_io_dpd_disable(tegra_host->dpd);
436 if (!tegra_host->clk_enabled) {
437 clk_enable(pltfm_host->clk);
438 ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
439 ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
440 sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
441 tegra_host->clk_enabled = true;
443 tegra_sdhci_set_clk_rate(sdhci, clock);
444 if (tegra_host->hw_ops->set_card_clock)
445 tegra_host->hw_ops->set_card_clock(sdhci, clock);
446 } else if (!clock && tegra_host->clk_enabled) {
447 if (tegra_host->hw_ops->set_card_clock)
448 tegra_host->hw_ops->set_card_clock(sdhci, clock);
449 ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
450 ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
451 sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
452 clk_disable(pltfm_host->clk);
453 tegra_host->clk_enabled = false;
454 /* io dpd enable call for sd instance */
455 tegra_io_dpd_enable(tegra_host->dpd);
459 static int tegra_sdhci_signal_voltage_switch(struct sdhci_host *sdhci,
460 unsigned int signal_voltage)
462 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
463 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
464 unsigned int min_uV = SDHOST_HIGH_VOLT_MIN;
465 unsigned int max_uV = SDHOST_HIGH_VOLT_MAX;
470 /* Switch OFF the card clock to prevent glitches on the clock line */
471 clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
472 clk &= ~SDHCI_CLOCK_CARD_EN;
473 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
475 ctrl = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
476 if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
477 ctrl |= SDHCI_CTRL_VDD_180;
478 min_uV = SDHOST_LOW_VOLT_MIN;
479 max_uV = SDHOST_LOW_VOLT_MAX;
480 } else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
481 if (ctrl & SDHCI_CTRL_VDD_180)
482 ctrl &= ~SDHCI_CTRL_VDD_180;
484 sdhci_writew(sdhci, ctrl, SDHCI_HOST_CONTROL2);
486 /* Switch the I/O rail voltage */
487 if (tegra_host->vdd_io_reg) {
488 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
491 dev_err(mmc_dev(sdhci->mmc), "switching to 1.8V"
492 "failed . Switching back to 3.3V\n");
493 regulator_set_voltage(tegra_host->vdd_io_reg,
494 SDHOST_HIGH_VOLT_MIN,
495 SDHOST_HIGH_VOLT_MAX);
500 /* Wait for 10 msec for the voltage to be switched */
503 /* Enable the card clock */
504 clk |= SDHCI_CLOCK_CARD_EN;
505 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
507 /* Wait for 1 msec after enabling clock */
510 if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
511 /* Do Auto Calibration for 1.8V signal voltage */
512 val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
513 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
514 /* Program Auto cal PD offset(bits 8:14) */
516 SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
517 val |= (SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET <<
518 SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
519 /* Program Auto cal PU offset(bits 0:6) */
521 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET;
522 sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
528 static int tegra_sdhci_suspend(struct sdhci_host *sdhci)
530 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
531 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
533 tegra_sdhci_set_clock(sdhci, 0);
535 /* Disable the power rails if any */
536 if (tegra_host->vdd_slot_reg)
537 regulator_disable(tegra_host->vdd_slot_reg);
538 if (tegra_host->vdd_io_reg)
539 regulator_disable(tegra_host->vdd_io_reg);
543 static int tegra_sdhci_resume(struct sdhci_host *sdhci)
545 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
546 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
547 unsigned long timeout;
549 /* Enable the power rails if any */
550 if (tegra_host->vdd_io_reg)
551 regulator_enable(tegra_host->vdd_io_reg);
552 if (tegra_host->vdd_slot_reg)
553 regulator_enable(tegra_host->vdd_slot_reg);
555 /* Setting the min identification clock of freq 400KHz */
556 tegra_sdhci_set_clock(sdhci, 400000);
558 /* Reset the controller and power on if MMC_KEEP_POWER flag is set*/
559 if (sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER) {
560 sdhci_writeb(sdhci, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
562 /* Wait max 100 ms */
565 /* hw clears the bit when it's done */
566 while (sdhci_readb(sdhci, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
568 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
569 mmc_hostname(sdhci->mmc), (int)SDHCI_RESET_ALL);
576 sdhci_writeb(sdhci, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
583 static struct sdhci_ops tegra_sdhci_ops = {
584 .get_ro = tegra_sdhci_get_ro,
585 .read_l = tegra_sdhci_readl,
586 .read_w = tegra_sdhci_readw,
587 .write_l = tegra_sdhci_writel,
588 .platform_8bit_width = tegra_sdhci_8bit,
589 .set_clock = tegra_sdhci_set_clock,
590 .suspend = tegra_sdhci_suspend,
591 .resume = tegra_sdhci_resume,
592 .platform_reset_exit = tegra_sdhci_reset_exit,
593 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
594 .switch_signal_voltage = tegra_sdhci_signal_voltage_switch,
597 static struct sdhci_pltfm_data sdhci_tegra_pdata = {
598 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
599 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
600 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
601 SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING |
603 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
604 SDHCI_QUIRK_NONSTANDARD_CLOCK |
606 SDHCI_QUIRK_SINGLE_POWER_WRITE |
607 SDHCI_QUIRK_NO_HISPD_BIT |
608 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
609 .ops = &tegra_sdhci_ops,
612 static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = {
613 { .compatible = "nvidia,tegra20-sdhci", },
616 MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
618 static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata(
619 struct platform_device *pdev)
621 struct tegra_sdhci_platform_data *plat;
622 struct device_node *np = pdev->dev.of_node;
627 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
629 dev_err(&pdev->dev, "Can't allocate platform data\n");
633 plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
634 plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
635 plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
636 if (of_find_property(np, "support-8bit", NULL))
642 static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
644 struct sdhci_pltfm_host *pltfm_host;
645 struct tegra_sdhci_platform_data *plat;
646 struct sdhci_host *host;
647 struct tegra_sdhci_host *tegra_host;
651 host = sdhci_pltfm_init(pdev, &sdhci_tegra_pdata);
653 return PTR_ERR(host);
655 pltfm_host = sdhci_priv(host);
657 plat = pdev->dev.platform_data;
660 plat = sdhci_tegra_dt_parse_pdata(pdev);
663 dev_err(mmc_dev(host->mmc), "missing platform data\n");
668 tegra_host = kzalloc(sizeof(struct tegra_sdhci_host), GFP_KERNEL);
669 if (tegra_host == NULL) {
670 dev_err(mmc_dev(host->mmc), "failed to allocate tegra host\n");
675 tegra_host->pdata = plat;
676 pltfm_host->priv = tegra_host;
678 #ifdef CONFIG_MMC_EMBEDDED_SDIO
679 if (plat->mmc_data.embedded_sdio)
680 mmc_set_embedded_sdio_data(host->mmc,
681 &plat->mmc_data.embedded_sdio->cis,
682 &plat->mmc_data.embedded_sdio->cccr,
683 plat->mmc_data.embedded_sdio->funcs,
684 plat->mmc_data.embedded_sdio->num_funcs);
687 if (gpio_is_valid(plat->power_gpio)) {
688 rc = gpio_request(plat->power_gpio, "sdhci_power");
690 dev_err(mmc_dev(host->mmc),
691 "failed to allocate power gpio\n");
694 tegra_gpio_enable(plat->power_gpio);
695 gpio_direction_output(plat->power_gpio, 1);
698 if (gpio_is_valid(plat->cd_gpio)) {
699 rc = gpio_request(plat->cd_gpio, "sdhci_cd");
701 dev_err(mmc_dev(host->mmc),
702 "failed to allocate cd gpio\n");
705 tegra_gpio_enable(plat->cd_gpio);
706 gpio_direction_input(plat->cd_gpio);
708 rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
709 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
710 mmc_hostname(host->mmc), host);
713 dev_err(mmc_dev(host->mmc), "request irq error\n");
716 rc = enable_irq_wake(gpio_to_irq(plat->cd_gpio));
718 dev_err(mmc_dev(host->mmc),
719 "SD card wake-up event registration"
720 "failed with eroor: %d\n", rc);
722 } else if (plat->mmc_data.register_status_notify) {
723 plat->mmc_data.register_status_notify(sdhci_status_notify_cb, host);
726 if (plat->mmc_data.status) {
727 plat->mmc_data.card_present = plat->mmc_data.status(mmc_dev(host->mmc));
730 if (gpio_is_valid(plat->wp_gpio)) {
731 rc = gpio_request(plat->wp_gpio, "sdhci_wp");
733 dev_err(mmc_dev(host->mmc),
734 "failed to allocate wp gpio\n");
737 tegra_gpio_enable(plat->wp_gpio);
738 gpio_direction_input(plat->wp_gpio);
742 if (!plat->mmc_data.built_in) {
743 if (plat->mmc_data.ocr_mask & SDHOST_1V8_OCR_MASK) {
744 tegra_host->vddio_min_uv = SDHOST_LOW_VOLT_MIN;
745 tegra_host->vddio_max_uv = SDHOST_LOW_VOLT_MAX;
748 * Set the minV and maxV to default
749 * voltage range of 2.7V - 3.6V
751 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_MIN;
752 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
754 tegra_host->vdd_io_reg = regulator_get(mmc_dev(host->mmc), "vddio_sdmmc");
755 if (IS_ERR_OR_NULL(tegra_host->vdd_io_reg)) {
756 dev_err(mmc_dev(host->mmc), "%s regulator not found: %ld\n",
757 "vddio_sdmmc", PTR_ERR(tegra_host->vdd_io_reg));
758 tegra_host->vdd_io_reg = NULL;
760 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
761 tegra_host->vddio_min_uv,
762 tegra_host->vddio_max_uv);
764 dev_err(mmc_dev(host->mmc), "%s regulator_set_voltage failed: %d",
767 regulator_enable(tegra_host->vdd_io_reg);
771 tegra_host->vdd_slot_reg = regulator_get(mmc_dev(host->mmc), "vddio_sd_slot");
772 if (IS_ERR_OR_NULL(tegra_host->vdd_slot_reg)) {
773 dev_err(mmc_dev(host->mmc), "%s regulator not found: %ld\n",
774 "vddio_sd_slot", PTR_ERR(tegra_host->vdd_slot_reg));
775 tegra_host->vdd_slot_reg = NULL;
777 regulator_enable(tegra_host->vdd_slot_reg);
781 clk = clk_get(mmc_dev(host->mmc), NULL);
783 dev_err(mmc_dev(host->mmc), "clk err\n");
787 rc = clk_enable(clk);
790 pltfm_host->clk = clk;
791 pltfm_host->priv = tegra_host;
792 tegra_host->clk_enabled = true;
793 tegra_host->max_clk_limit = plat->max_clk_limit;
794 tegra_host->instance = pdev->id;
795 tegra_host->dpd = tegra_io_dpd_get(mmc_dev(host->mmc));
797 host->mmc->pm_caps = plat->pm_flags;
799 host->mmc->caps |= MMC_CAP_ERASE;
800 host->mmc->caps |= MMC_CAP_DISABLE;
801 /* enable 1/8V DDR capable */
802 host->mmc->caps |= MMC_CAP_1_8V_DDR;
804 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
805 host->mmc->caps |= MMC_CAP_SDIO_IRQ;
807 if (plat->mmc_data.built_in) {
808 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
810 /* Do not turn OFF embedded sdio cards as it support Wake on Wireless */
811 if (plat->mmc_data.embedded_sdio)
812 host->mmc->pm_flags = MMC_PM_KEEP_POWER;
814 tegra_sdhost_min_freq = TEGRA_SDHOST_MIN_FREQ;
815 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
816 tegra_host->hw_ops = &tegra_2x_sdhci_ops;
817 tegra_sdhost_std_freq = TEGRA2_SDHOST_STD_FREQ;
819 tegra_host->hw_ops = &tegra_3x_sdhci_ops;
820 tegra_sdhost_std_freq = TEGRA3_SDHOST_STD_FREQ;
823 rc = sdhci_add_host(host);
830 clk_disable(pltfm_host->clk);
832 clk_put(pltfm_host->clk);
834 if (gpio_is_valid(plat->wp_gpio)) {
835 tegra_gpio_disable(plat->wp_gpio);
836 gpio_free(plat->wp_gpio);
839 if (gpio_is_valid(plat->cd_gpio))
840 free_irq(gpio_to_irq(plat->cd_gpio), host);
842 if (gpio_is_valid(plat->cd_gpio)) {
843 tegra_gpio_disable(plat->cd_gpio);
844 gpio_free(plat->cd_gpio);
847 if (gpio_is_valid(plat->power_gpio)) {
848 tegra_gpio_disable(plat->power_gpio);
849 gpio_free(plat->power_gpio);
855 sdhci_pltfm_free(pdev);
859 static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
861 struct sdhci_host *host = platform_get_drvdata(pdev);
862 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
863 struct tegra_sdhci_host *tegra_host = pltfm_host->priv;
864 struct tegra_sdhci_platform_data *plat = tegra_host->pdata;
865 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
867 sdhci_remove_host(host, dead);
869 disable_irq_wake(gpio_to_irq(plat->cd_gpio));
871 if (tegra_host->vdd_slot_reg) {
872 regulator_disable(tegra_host->vdd_slot_reg);
873 regulator_put(tegra_host->vdd_slot_reg);
876 if (tegra_host->vdd_io_reg) {
877 regulator_disable(tegra_host->vdd_io_reg);
878 regulator_put(tegra_host->vdd_io_reg);
881 if (gpio_is_valid(plat->wp_gpio)) {
882 tegra_gpio_disable(plat->wp_gpio);
883 gpio_free(plat->wp_gpio);
886 if (gpio_is_valid(plat->cd_gpio)) {
887 free_irq(gpio_to_irq(plat->cd_gpio), host);
888 tegra_gpio_disable(plat->cd_gpio);
889 gpio_free(plat->cd_gpio);
892 if (gpio_is_valid(plat->power_gpio)) {
893 tegra_gpio_disable(plat->power_gpio);
894 gpio_free(plat->power_gpio);
897 if (tegra_host->clk_enabled)
898 clk_disable(pltfm_host->clk);
899 clk_put(pltfm_host->clk);
901 sdhci_pltfm_free(pdev);
907 static struct platform_driver sdhci_tegra_driver = {
909 .name = "sdhci-tegra",
910 .owner = THIS_MODULE,
911 .of_match_table = sdhci_tegra_dt_match,
912 .pm = SDHCI_PLTFM_PMOPS,
914 .probe = sdhci_tegra_probe,
915 .remove = __devexit_p(sdhci_tegra_remove),
918 module_platform_driver(sdhci_tegra_driver);
920 MODULE_DESCRIPTION("SDHCI driver for Tegra");
921 MODULE_AUTHOR(" Google, Inc.");
922 MODULE_LICENSE("GPL v2");