mmc: Tegra: Fix calculation for partial_win_tap
[linux-2.6.git] / drivers / mmc / host / sdhci-tegra.c
1 /*
2  * Copyright (C) 2010 Google, Inc.
3  *
4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/err.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/gpio.h>
27 #include <linux/slab.h>
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/host.h>
30 #include <linux/module.h>
31 #include <linux/mmc/sd.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/delay.h>
34 #include <linux/pm_runtime.h>
35 #include <asm/gpio.h>
36 #include <linux/debugfs.h>
37 #include <linux/seq_file.h>
38
39 #include <mach/gpio-tegra.h>
40 #include <mach/sdhci.h>
41 #include <mach/io_dpd.h>
42 #include <mach/pinmux.h>
43
44 #include "sdhci-pltfm.h"
45
46 #define SDHCI_VNDR_CLK_CTRL     0x100
47 #define SDHCI_VNDR_CLK_CTRL_SDMMC_CLK   0x1
48 #define SDHCI_VNDR_CLK_CTRL_PADPIPE_CLKEN_OVERRIDE      0x8
49 #define SDHCI_VNDR_CLK_CTRL_SPI_MODE_CLKEN_OVERRIDE     0x4
50 #define SDHCI_VNDR_CLK_CTRL_BASE_CLK_FREQ_SHIFT 8
51 #define SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT     16
52 #define SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT    24
53 #define SDHCI_VNDR_CLK_CTRL_SDR50_TUNING                0x20
54
55 #define SDHCI_VNDR_MISC_CTRL            0x120
56 #define SDHCI_VNDR_MISC_CTRL_ENABLE_SDR104_SUPPORT      0x8
57 #define SDHCI_VNDR_MISC_CTRL_ENABLE_SDR50_SUPPORT       0x10
58 #define SDHCI_VNDR_MISC_CTRL_ENABLE_DDR50_SUPPORT       0x200
59 #define SDHCI_VNDR_MISC_CTRL_ENABLE_SD_3_0      0x20
60 #define SDHCI_VNDR_MISC_CTRL_INFINITE_ERASE_TIMEOUT     0x1
61
62 #define SDMMC_SDMEMCOMPPADCTRL  0x1E0
63 #define SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK    0xF
64
65 #define SDMMC_AUTO_CAL_CONFIG   0x1E4
66 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START    0x80000000
67 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE   0x20000000
68 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT  0x8
69 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET        0x70
70 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET        0x62
71
72 #define SDMMC_AUTO_CAL_STATUS   0x1EC
73 #define SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE   0x80000000
74 #define SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET   24
75 #define PULLUP_ADJUSTMENT_OFFSET        20
76
77 #define SDHOST_1V8_OCR_MASK     0x8
78 #define SDHOST_HIGH_VOLT_MIN    2700000
79 #define SDHOST_HIGH_VOLT_MAX    3600000
80 #define SDHOST_HIGH_VOLT_2V8    2800000
81 #define SDHOST_LOW_VOLT_MIN     1800000
82 #define SDHOST_LOW_VOLT_MAX     1800000
83
84 #define TEGRA_SDHOST_MIN_FREQ   50000000
85 #define TEGRA2_SDHOST_STD_FREQ  50000000
86 #define TEGRA3_SDHOST_STD_FREQ  104000000
87
88 #define MAX_DIVISOR_VALUE       128
89
90 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8       128
91 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4       64
92 #define MAX_TAP_VALUES  255
93 #define TUNING_FREQ_COUNT       2
94 #define TUNING_VOLTAGES_COUNT   2
95
96 static unsigned int uhs_max_freq_MHz[] = {
97         [MMC_TIMING_UHS_SDR50] = 100,
98         [MMC_TIMING_UHS_SDR104] = 208,
99         [MMC_TIMING_MMC_HS200] = 200,
100 };
101
102 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
103 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock);
104 #endif
105
106 static unsigned int tegra_sdhost_min_freq;
107 static unsigned int tegra_sdhost_std_freq;
108
109
110 struct tegra_sdhci_hw_ops {
111         /* Set the internal clk and card clk.*/
112         void    (*set_card_clock)(struct sdhci_host *sdhci, unsigned int clock);
113 };
114
115 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
116 static struct tegra_sdhci_hw_ops tegra_2x_sdhci_ops = {
117 };
118 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
119 static struct tegra_sdhci_hw_ops tegra_3x_sdhci_ops = {
120         .set_card_clock = tegra_3x_sdhci_set_card_clock,
121 };
122 #else
123 static struct tegra_sdhci_hw_ops tegra_11x_sdhci_ops = {
124 };
125 #endif
126
127 /* Erratum: Version register is invalid in HW */
128 #define NVQUIRK_FORCE_SDHCI_SPEC_200            BIT(0)
129 /* Erratum: Enable block gap interrupt detection */
130 #define NVQUIRK_ENABLE_BLOCK_GAP_DET            BIT(1)
131 /* Do not enable auto calibration if the platform doesn't support */
132 #define NVQUIRK_DISABLE_AUTO_CALIBRATION        BIT(2)
133 /* Set Calibration Offsets */
134 #define NVQUIRK_SET_CALIBRATION_OFFSETS         BIT(3)
135 /* Set Drive Strengths */
136 #define NVQUIRK_SET_DRIVE_STRENGTH              BIT(4)
137 /* Enable PADPIPE CLKEN */
138 #define NVQUIRK_ENABLE_PADPIPE_CLKEN            BIT(5)
139 /* DISABLE SPI_MODE CLKEN */
140 #define NVQUIRK_DISABLE_SPI_MODE_CLKEN          BIT(6)
141 /* Set tap delay */
142 #define NVQUIRK_SET_TAP_DELAY                   BIT(7)
143 /* Set trim delay */
144 #define NVQUIRK_SET_TRIM_DELAY                  BIT(8)
145 /* Enable SDHOST v3.0 support */
146 #define NVQUIRK_ENABLE_SD_3_0                   BIT(9)
147 /* Enable SDR50 mode */
148 #define NVQUIRK_ENABLE_SDR50                    BIT(10)
149 /* Enable SDR104 mode */
150 #define NVQUIRK_ENABLE_SDR104                   BIT(11)
151 /*Enable DDR50 mode */
152 #define NVQUIRK_ENABLE_DDR50                    BIT(12)
153 /* Enable Frequency Tuning for SDR50 mode */
154 #define NVQUIRK_ENABLE_SDR50_TUNING             BIT(13)
155 /* Enable Infinite Erase Timeout*/
156 #define NVQUIRK_INFINITE_ERASE_TIMEOUT          BIT(14)
157
158 struct sdhci_tegra_soc_data {
159         struct sdhci_pltfm_data *pdata;
160         u32 nvquirks;
161 };
162
163 struct sdhci_tegra_sd_stats {
164         unsigned int data_crc_count;
165         unsigned int cmd_crc_count;
166         unsigned int data_to_count;
167         unsigned int cmd_to_count;
168 };
169
170 enum tegra_tuning_freq {
171         TUNING_LOW_FREQ,
172         TUNING_HIGH_FREQ,
173 };
174
175 struct freq_tuning_params {
176         unsigned int    freq_hz;
177         unsigned int    nr_voltages;
178         unsigned int    voltages[TUNING_VOLTAGES_COUNT];
179 };
180
181 static struct freq_tuning_params tuning_params[TUNING_FREQ_COUNT] = {
182         [TUNING_LOW_FREQ] = {
183                 .freq_hz = 82000000,
184                 .nr_voltages = 1,
185                 .voltages = {ULONG_MAX},
186         },
187         [TUNING_HIGH_FREQ] = {
188                 .freq_hz = 156000000,
189                 .nr_voltages = 2,
190                 .voltages = {ULONG_MAX, 1100000},
191         },
192 };
193
194 struct tap_window_data {
195         unsigned int    partial_win;
196         unsigned int    full_win_begin;
197         unsigned int    full_win_end;
198         unsigned int    tuning_ui;
199         unsigned int    sampling_point;
200         bool            abandon_partial_win;
201         bool            abandon_full_win;
202 };
203
204 struct tegra_tuning_data {
205         unsigned int            best_tap_value;
206         bool                    select_partial_win;
207         struct tap_window_data  *tap_data[TUNING_VOLTAGES_COUNT];
208 };
209
210 struct sdhci_tegra {
211         const struct tegra_sdhci_platform_data *plat;
212         const struct sdhci_tegra_soc_data *soc_data;
213         bool    clk_enabled;
214         struct regulator *vdd_io_reg;
215         struct regulator *vdd_slot_reg;
216         struct regulator *vcore_reg;
217         /* Pointer to the chip specific HW ops */
218         struct tegra_sdhci_hw_ops *hw_ops;
219         /* Host controller instance */
220         unsigned int instance;
221         /* vddio_min */
222         unsigned int vddio_min_uv;
223         /* vddio_max */
224         unsigned int vddio_max_uv;
225         /* max clk supported by the platform */
226         unsigned int max_clk_limit;
227         /* max ddr clk supported by the platform */
228         unsigned int ddr_clk_limit;
229         /* SD Hot Plug in Suspend State */
230         unsigned int sd_detect_in_suspend;
231         struct tegra_io_dpd *dpd;
232         bool card_present;
233         bool is_rail_enabled;
234         struct clk *emc_clk;
235         unsigned int emc_max_clk;
236         struct sdhci_tegra_sd_stats *sd_stat_head;
237         unsigned int nominal_vcore_uV;
238         /* Tuning related structures and variables */
239         /* Tuning opcode to be used */
240         unsigned int tuning_opcode;
241         /* Tuning packet size */
242         unsigned int tuning_bsize;
243         /* Tuning status */
244         unsigned int tuning_status;
245 #define TUNING_STATUS_DONE      1
246 #define TUNING_STATUS_RETUNE    2
247         /* Freq tuning information for each sampling clock freq */
248         struct tegra_tuning_data tuning_data;
249         bool is_parent_pllc;
250 };
251
252 static struct clk *pll_c;
253 static struct clk *pll_p;
254 static unsigned long pll_c_rate;
255 static unsigned long pll_p_rate;
256
257 static int show_error_stats_dump(struct seq_file *s, void *data)
258 {
259         struct sdhci_host *host = s->private;
260         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
261         struct sdhci_tegra *tegra_host = pltfm_host->priv;
262         struct sdhci_tegra_sd_stats *head;
263
264         seq_printf(s, "ErrorStatistics:\n");
265         seq_printf(s, "DataCRC\tCmdCRC\tDataTimeout\tCmdTimeout\n");
266         head = tegra_host->sd_stat_head;
267         if (head != NULL)
268                 seq_printf(s, "%d\t%d\t%d\t%d\n", head->data_crc_count,
269                         head->cmd_crc_count, head->data_to_count,
270                         head->cmd_to_count);
271         return 0;
272 }
273
274 static int sdhci_error_stats_dump(struct inode *inode, struct file *file)
275 {
276         return single_open(file, show_error_stats_dump, inode->i_private);
277 }
278
279 static const struct file_operations sdhci_host_fops = {
280         .open           = sdhci_error_stats_dump,
281         .read           = seq_read,
282         .llseek         = seq_lseek,
283         .release        = single_release,
284 };
285
286 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
287 {
288 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
289         u32 val;
290
291         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
292                 /* Use wp_gpio here instead? */
293                 val = readl(host->ioaddr + reg);
294                 return val | SDHCI_WRITE_PROTECT;
295         }
296 #endif
297         return readl(host->ioaddr + reg);
298 }
299
300 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
301 {
302 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
303         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
304         struct sdhci_tegra *tegra_host = pltfm_host->priv;
305         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
306
307         if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
308                         (reg == SDHCI_HOST_VERSION))) {
309                 return SDHCI_SPEC_200;
310         }
311 #endif
312         return readw(host->ioaddr + reg);
313 }
314
315 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
316 {
317 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
318         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
319         struct sdhci_tegra *tegra_host = pltfm_host->priv;
320         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
321 #endif
322
323         /* Seems like we're getting spurious timeout and crc errors, so
324          * disable signalling of them. In case of real errors software
325          * timers should take care of eventually detecting them.
326          */
327         if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
328                 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
329
330         writel(val, host->ioaddr + reg);
331
332 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
333         if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
334                         (reg == SDHCI_INT_ENABLE))) {
335                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
336                 if (val & SDHCI_INT_CARD_INT)
337                         gap_ctrl |= 0x8;
338                 else
339                         gap_ctrl &= ~0x8;
340                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
341         }
342 #endif
343 }
344
345 static unsigned int tegra_sdhci_get_cd(struct sdhci_host *sdhci)
346 {
347         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
348         struct sdhci_tegra *tegra_host = pltfm_host->priv;
349
350         return tegra_host->card_present;
351 }
352
353 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
354 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
355 {
356         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
357         struct sdhci_tegra *tegra_host = pltfm_host->priv;
358         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
359
360         if (!gpio_is_valid(plat->wp_gpio))
361                 return -1;
362
363         return gpio_get_value(plat->wp_gpio);
364 }
365 #endif
366
367 static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
368                 unsigned int uhs)
369 {
370         u16 clk, ctrl_2;
371         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
372
373         /* Select Bus Speed Mode for host */
374         /* For HS200 we need to set UHS_MODE_SEL to SDR104.
375          * It works as SDR 104 in SD 4-bit mode and HS200 in eMMC 8-bit mode.
376          */
377         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
378         switch (uhs) {
379         case MMC_TIMING_UHS_SDR12:
380                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
381                 break;
382         case MMC_TIMING_UHS_SDR25:
383                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
384                 break;
385         case MMC_TIMING_UHS_SDR50:
386                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
387                 break;
388         case MMC_TIMING_UHS_SDR104:
389         case MMC_TIMING_MMC_HS200:
390                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
391                 break;
392         case MMC_TIMING_UHS_DDR50:
393                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
394                 break;
395         }
396
397         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
398
399         if (uhs == MMC_TIMING_UHS_DDR50) {
400                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
401                 clk &= ~(0xFF << SDHCI_DIVIDER_SHIFT);
402                 clk |= 1 << SDHCI_DIVIDER_SHIFT;
403                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
404         }
405         return 0;
406 }
407
408 static void tegra_sdhci_reset_exit(struct sdhci_host *sdhci, u8 mask)
409 {
410         u16 misc_ctrl;
411         u32 vendor_ctrl;
412         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
413         struct sdhci_tegra *tegra_host = pltfm_host->priv;
414         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
415         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
416
417         if (mask & SDHCI_RESET_ALL) {
418                 if (tegra_host->sd_stat_head != NULL) {
419                         tegra_host->sd_stat_head->data_crc_count = 0;
420                         tegra_host->sd_stat_head->cmd_crc_count = 0;
421                         tegra_host->sd_stat_head->data_to_count = 0;
422                         tegra_host->sd_stat_head->cmd_to_count = 0;
423                 }
424                 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
425                 if (soc_data->nvquirks & NVQUIRK_ENABLE_PADPIPE_CLKEN) {
426                         vendor_ctrl |=
427                                 SDHCI_VNDR_CLK_CTRL_PADPIPE_CLKEN_OVERRIDE;
428                 }
429                 if (soc_data->nvquirks & NVQUIRK_DISABLE_SPI_MODE_CLKEN) {
430                         vendor_ctrl &=
431                                 ~SDHCI_VNDR_CLK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
432                 }
433                 if (soc_data->nvquirks & NVQUIRK_SET_TAP_DELAY) {
434                         if ((tegra_host->tuning_status == TUNING_STATUS_DONE) &&
435                                 (sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
436                                         vendor_ctrl &= ~(0xFF <<
437                                         SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
438                                         vendor_ctrl |=
439                                         (tegra_host->tuning_data.best_tap_value
440                                         << SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
441                         } else {
442                                 if (plat->tap_delay) {
443                                         vendor_ctrl &= ~(0xFF <<
444                                         SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
445                                         vendor_ctrl |= (plat->tap_delay <<
446                                         SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
447                                 }
448                         }
449                 }
450                 if (soc_data->nvquirks & NVQUIRK_SET_TRIM_DELAY) {
451                         if (plat->trim_delay) {
452                                 vendor_ctrl &= ~(0x1F <<
453                                 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
454                                 vendor_ctrl |= (plat->trim_delay <<
455                                 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
456                         }
457                 }
458                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50_TUNING)
459                         vendor_ctrl |= SDHCI_VNDR_CLK_CTRL_SDR50_TUNING;
460                 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
461
462                 misc_ctrl = sdhci_readw(sdhci, SDHCI_VNDR_MISC_CTRL);
463                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SD_3_0)
464                         misc_ctrl |= SDHCI_VNDR_MISC_CTRL_ENABLE_SD_3_0;
465                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) {
466                         misc_ctrl |=
467                         SDHCI_VNDR_MISC_CTRL_ENABLE_SDR104_SUPPORT;
468                 }
469                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) {
470                         misc_ctrl |=
471                         SDHCI_VNDR_MISC_CTRL_ENABLE_SDR50_SUPPORT;
472                 }
473                 /* Enable DDR mode support only for SDMMC4 */
474                 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) {
475                         if (tegra_host->instance == 3) {
476                                 misc_ctrl |=
477                                 SDHCI_VNDR_MISC_CTRL_ENABLE_DDR50_SUPPORT;
478                         }
479                 }
480                 if (soc_data->nvquirks & NVQUIRK_INFINITE_ERASE_TIMEOUT) {
481                         misc_ctrl |=
482                         SDHCI_VNDR_MISC_CTRL_INFINITE_ERASE_TIMEOUT;
483                 }
484                 sdhci_writew(sdhci, misc_ctrl, SDHCI_VNDR_MISC_CTRL);
485
486                 /* Mask the support for any UHS modes if specified */
487                 if (plat->uhs_mask & MMC_UHS_MASK_SDR104)
488                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR104;
489
490                 if (plat->uhs_mask & MMC_UHS_MASK_DDR50)
491                         sdhci->mmc->caps &= ~MMC_CAP_UHS_DDR50;
492
493                 if (plat->uhs_mask & MMC_UHS_MASK_SDR50)
494                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR50;
495
496                 if (plat->uhs_mask & MMC_UHS_MASK_SDR25)
497                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR25;
498
499                 if (plat->uhs_mask & MMC_UHS_MASK_SDR12)
500                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR12;
501
502                 if (plat->uhs_mask & MMC_MASK_HS200)
503                         sdhci->mmc->caps2 &= ~MMC_CAP2_HS200;
504         }
505 }
506
507 static void sdhci_status_notify_cb(int card_present, void *dev_id)
508 {
509         struct sdhci_host *sdhci = (struct sdhci_host *)dev_id;
510         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
511         struct tegra_sdhci_platform_data *plat;
512         unsigned int status, oldstat;
513
514         pr_debug("%s: card_present %d\n", mmc_hostname(sdhci->mmc),
515                 card_present);
516
517         plat = pdev->dev.platform_data;
518         if (!plat->mmc_data.status) {
519                 mmc_detect_change(sdhci->mmc, 0);
520                 return;
521         }
522
523         status = plat->mmc_data.status(mmc_dev(sdhci->mmc));
524
525         oldstat = plat->mmc_data.card_present;
526         plat->mmc_data.card_present = status;
527         if (status ^ oldstat) {
528                 pr_debug("%s: Slot status change detected (%d -> %d)\n",
529                         mmc_hostname(sdhci->mmc), oldstat, status);
530                 if (status && !plat->mmc_data.built_in)
531                         mmc_detect_change(sdhci->mmc, (5 * HZ) / 2);
532                 else
533                         mmc_detect_change(sdhci->mmc, 0);
534         }
535 }
536
537 static irqreturn_t carddetect_irq(int irq, void *data)
538 {
539         struct sdhci_host *sdhost = (struct sdhci_host *)data;
540         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
541         struct sdhci_tegra *tegra_host = pltfm_host->priv;
542         struct platform_device *pdev = to_platform_device(mmc_dev(sdhost->mmc));
543         struct tegra_sdhci_platform_data *plat;
544
545         plat = pdev->dev.platform_data;
546
547         tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
548
549         if (tegra_host->card_present) {
550                 if (!tegra_host->is_rail_enabled) {
551                         if (tegra_host->vdd_slot_reg)
552                                 regulator_enable(tegra_host->vdd_slot_reg);
553                         if (tegra_host->vdd_io_reg)
554                                 regulator_enable(tegra_host->vdd_io_reg);
555                         tegra_host->is_rail_enabled = 1;
556                 }
557         } else {
558                 if (tegra_host->is_rail_enabled) {
559                         if (tegra_host->vdd_io_reg)
560                                 regulator_disable(tegra_host->vdd_io_reg);
561                         if (tegra_host->vdd_slot_reg)
562                                 regulator_disable(tegra_host->vdd_slot_reg);
563                         tegra_host->is_rail_enabled = 0;
564                 }
565                 /*
566                  * Set retune request as tuning should be done next time
567                  * a card is inserted.
568                  */
569                 tegra_host->tuning_status = TUNING_STATUS_RETUNE;
570         }
571
572         tasklet_schedule(&sdhost->card_tasklet);
573         return IRQ_HANDLED;
574 };
575
576 static int tegra_sdhci_8bit(struct sdhci_host *sdhci, int bus_width)
577 {
578         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
579         const struct tegra_sdhci_platform_data *plat;
580         u32 ctrl;
581
582         plat = pdev->dev.platform_data;
583
584         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL);
585         if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
586                 ctrl &= ~SDHCI_CTRL_4BITBUS;
587                 ctrl |= SDHCI_CTRL_8BITBUS;
588         } else {
589                 ctrl &= ~SDHCI_CTRL_8BITBUS;
590                 if (bus_width == MMC_BUS_WIDTH_4)
591                         ctrl |= SDHCI_CTRL_4BITBUS;
592                 else
593                         ctrl &= ~SDHCI_CTRL_4BITBUS;
594         }
595         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL);
596         return 0;
597 }
598
599 /*
600 * Calculation of nearest clock frequency for desired rate:
601 * Get the divisor value, div = p / d_rate
602 * 1. If it is nearer to ceil(p/d_rate) then increment the div value by 0.5 and
603 * nearest_rate, i.e. result = p / (div + 0.5) = (p << 1)/((div << 1) + 1).
604 * 2. If not, result = p / div
605 * As the nearest clk freq should be <= to desired_rate,
606 * 3. If result > desired_rate then increment the div by 0.5
607 * and do, (p << 1)/((div << 1) + 1)
608 * 4. Else return result
609 * Here, If condtions 1 & 3 are both satisfied then to keep track of div value,
610 * defined index variable.
611 */
612 static unsigned long get_nearest_clock_freq(unsigned long pll_rate,
613                 unsigned long desired_rate)
614 {
615         unsigned long result;
616         int div;
617         int index = 1;
618
619         div = pll_rate / desired_rate;
620         if (div > MAX_DIVISOR_VALUE) {
621                 div = MAX_DIVISOR_VALUE;
622                 result = pll_rate / div;
623         } else {
624                 if ((pll_rate % desired_rate) >= (desired_rate / 2))
625                         result = (pll_rate << 1) / ((div << 1) + index++);
626                 else
627                         result = pll_rate / div;
628
629                 if (desired_rate < result) {
630                         /*
631                         * Trying to get lower clock freq than desired clock,
632                         * by increasing the divisor value by 0.5
633                         */
634                         result = (pll_rate << 1) / ((div << 1) + index);
635                 }
636         }
637
638         return result;
639 }
640
641 static void tegra_sdhci_clock_set_parent(struct sdhci_host *host,
642                 unsigned long desired_rate)
643 {
644         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
645         struct sdhci_tegra *tegra_host = pltfm_host->priv;
646         struct clk *parent_clk;
647         unsigned long pll_c_freq;
648         unsigned long pll_p_freq;
649         int rc;
650
651         pll_c_freq = get_nearest_clock_freq(pll_c_rate, desired_rate);
652         pll_p_freq = get_nearest_clock_freq(pll_p_rate, desired_rate);
653
654         if (pll_c_freq > pll_p_freq) {
655                 if (!tegra_host->is_parent_pllc) {
656                         parent_clk = pll_c;
657                         tegra_host->is_parent_pllc = true;
658                 } else
659                         return;
660         } else if (tegra_host->is_parent_pllc) {
661                 parent_clk = pll_p;
662                 tegra_host->is_parent_pllc = false;
663         } else
664                 return;
665
666         rc = clk_set_parent(pltfm_host->clk, parent_clk);
667         if (rc)
668                 pr_err("%s: failed to set pll parent clock %d\n",
669                         mmc_hostname(host->mmc), rc);
670 }
671
672 static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci,
673         unsigned int clock)
674 {
675         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
676         struct sdhci_tegra *tegra_host = pltfm_host->priv;
677         unsigned int clk_rate;
678         unsigned int emc_clk;
679
680         if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
681                 /*
682                  * In ddr mode, tegra sdmmc controller clock frequency
683                  * should be double the card clock frequency.
684                  */
685                 if (tegra_host->ddr_clk_limit) {
686                         clk_rate = tegra_host->ddr_clk_limit * 2;
687                         if (tegra_host->emc_clk) {
688                                 emc_clk = clk_get_rate(tegra_host->emc_clk);
689                                 if (emc_clk == tegra_host->emc_max_clk)
690                                         clk_rate = clock * 2;
691                         }
692                 } else {
693                         clk_rate = clock * 2;
694                 }
695         } else  if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50) {
696                 /*
697                  * In SDR50 mode, run the sdmmc controller at freq greater than
698                  * 104MHz to ensure the core voltage is at 1.2V. If the core voltage
699                  * is below 1.2V, CRC errors would occur during data transfers.
700                  */
701                 clk_rate = clock * 2;
702         } else {
703                 if (clock <= tegra_sdhost_min_freq)
704                         clk_rate = tegra_sdhost_min_freq;
705                 else if (clock <= tegra_sdhost_std_freq)
706                         clk_rate = tegra_sdhost_std_freq;
707                 else
708                         clk_rate = clock;
709         }
710
711         if (tegra_host->max_clk_limit &&
712                 (clk_rate > tegra_host->max_clk_limit))
713                 clk_rate = tegra_host->max_clk_limit;
714
715         tegra_sdhci_clock_set_parent(sdhci, clk_rate);
716         clk_set_rate(pltfm_host->clk, clk_rate);
717         sdhci->max_clk = clk_get_rate(pltfm_host->clk);
718 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
719         /* FPGA supports 26MHz of clock for SDMMC. */
720         sdhci->max_clk = 26000000;
721 #endif
722 }
723 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
724 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock)
725 {
726         int div;
727         u16 clk;
728         unsigned long timeout;
729         u8 ctrl;
730
731         if (clock && clock == sdhci->clock)
732                 return;
733
734         /*
735          * Disable the card clock before disabling the internal
736          * clock to avoid abnormal clock waveforms.
737          */
738         clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
739         clk &= ~SDHCI_CLOCK_CARD_EN;
740         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
741         sdhci_writew(sdhci, 0, SDHCI_CLOCK_CONTROL);
742
743         if (clock == 0)
744                 goto out;
745         if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
746                 div = 1;
747                 goto set_clk;
748         }
749
750         if (sdhci->version >= SDHCI_SPEC_300) {
751                 /* Version 3.00 divisors must be a multiple of 2. */
752                 if (sdhci->max_clk <= clock) {
753                         div = 1;
754                 } else {
755                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
756                                 if ((sdhci->max_clk / div) <= clock)
757                                         break;
758                         }
759                 }
760         } else {
761                 /* Version 2.00 divisors must be a power of 2. */
762                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
763                         if ((sdhci->max_clk / div) <= clock)
764                                 break;
765                 }
766         }
767         div >>= 1;
768
769         /*
770          * Tegra3 sdmmc controller internal clock will not be stabilized when
771          * we use a clock divider value greater than 4. The WAR is as follows.
772          * - Enable internal clock.
773          * - Wait for 5 usec and do a dummy write.
774          * - Poll for clk stable.
775          */
776 set_clk:
777         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
778         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
779                 << SDHCI_DIVIDER_HI_SHIFT;
780         clk |= SDHCI_CLOCK_INT_EN;
781         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
782
783         /* Wait for 5 usec */
784         udelay(5);
785
786         /* Do a dummy write */
787         ctrl = sdhci_readb(sdhci, SDHCI_CAPABILITIES);
788         ctrl |= 1;
789         sdhci_writeb(sdhci, ctrl, SDHCI_CAPABILITIES);
790
791         /* Wait max 20 ms */
792         timeout = 20;
793         while (!((clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL))
794                 & SDHCI_CLOCK_INT_STABLE)) {
795                 if (timeout == 0) {
796                         dev_err(mmc_dev(sdhci->mmc), "Internal clock never stabilised\n");
797                         return;
798                 }
799                 timeout--;
800                 mdelay(1);
801         }
802
803         clk |= SDHCI_CLOCK_CARD_EN;
804         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
805 out:
806         sdhci->clock = clock;
807 }
808 #endif /*       #ifdef CONFIG_ARCH_TEGRA_3x_SOC */
809
810 static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock)
811 {
812         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
813         struct sdhci_tegra *tegra_host = pltfm_host->priv;
814         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
815         u8 ctrl;
816
817         pr_debug("%s %s %u enabled=%u\n", __func__,
818                 mmc_hostname(sdhci->mmc), clock, tegra_host->clk_enabled);
819
820         if (clock) {
821                 /* bring out sd instance from io dpd mode */
822                 if (tegra_host->dpd) {
823                         mutex_lock(&tegra_host->dpd->delay_lock);
824                         cancel_delayed_work_sync(&tegra_host->dpd->delay_dpd);
825                         tegra_io_dpd_disable(tegra_host->dpd);
826                         mutex_unlock(&tegra_host->dpd->delay_lock);
827                 }
828
829                 if (!tegra_host->clk_enabled) {
830                         pm_runtime_get_sync(&pdev->dev);
831                         clk_prepare_enable(pltfm_host->clk);
832                         ctrl = sdhci_readb(sdhci, SDHCI_VNDR_CLK_CTRL);
833                         ctrl |= SDHCI_VNDR_CLK_CTRL_SDMMC_CLK;
834                         sdhci_writeb(sdhci, ctrl, SDHCI_VNDR_CLK_CTRL);
835                         tegra_host->clk_enabled = true;
836                 }
837                 tegra_sdhci_set_clk_rate(sdhci, clock);
838                 if (tegra_host->hw_ops->set_card_clock)
839                         tegra_host->hw_ops->set_card_clock(sdhci, clock);
840         } else if (!clock && tegra_host->clk_enabled) {
841                 if (tegra_host->hw_ops->set_card_clock)
842                         tegra_host->hw_ops->set_card_clock(sdhci, clock);
843                 ctrl = sdhci_readb(sdhci, SDHCI_VNDR_CLK_CTRL);
844                 ctrl &= ~SDHCI_VNDR_CLK_CTRL_SDMMC_CLK;
845                 sdhci_writeb(sdhci, ctrl, SDHCI_VNDR_CLK_CTRL);
846                 clk_disable_unprepare(pltfm_host->clk);
847                 pm_runtime_put_sync(&pdev->dev);
848                 tegra_host->clk_enabled = false;
849                 /* io dpd enable call for sd instance */
850
851                 if (tegra_host->dpd) {
852                         mutex_lock(&tegra_host->dpd->delay_lock);
853                         if (tegra_host->dpd->need_delay_dpd) {
854                                 schedule_delayed_work(
855                                         &tegra_host->dpd->delay_dpd,
856                                         msecs_to_jiffies(100));
857                         } else {
858                                 tegra_io_dpd_enable(tegra_host->dpd);
859                         }
860                         mutex_unlock(&tegra_host->dpd->delay_lock);
861                 }
862         }
863 }
864 static void tegra_sdhci_do_calibration(struct sdhci_host *sdhci)
865 {
866         unsigned int val;
867         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
868         struct sdhci_tegra *tegra_host = pltfm_host->priv;
869         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
870         unsigned int timeout = 10;
871
872         /* No Calibration for sdmmc4 */
873         if (tegra_host->instance == 3)
874                 return;
875
876         if (unlikely(soc_data->nvquirks & NVQUIRK_DISABLE_AUTO_CALIBRATION))
877                 return;
878
879         val = sdhci_readl(sdhci, SDMMC_SDMEMCOMPPADCTRL);
880         val &= ~SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK;
881         val |= 0x7;
882         sdhci_writel(sdhci, val, SDMMC_SDMEMCOMPPADCTRL);
883
884         /* Enable Auto Calibration*/
885         val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
886         val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
887         val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
888         if (unlikely(soc_data->nvquirks & NVQUIRK_SET_CALIBRATION_OFFSETS)) {
889                 /* Program Auto cal PD offset(bits 8:14) */
890                 val &= ~(0x7F <<
891                         SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
892                 val |= (SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET <<
893                         SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
894                 /* Program Auto cal PU offset(bits 0:6) */
895                 val &= ~0x7F;
896                 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET;
897         }
898         sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
899
900         /* Wait until the calibration is done */
901         do {
902                 if (!(sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) &
903                         SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE))
904                         break;
905
906                 mdelay(1);
907                 timeout--;
908         } while (timeout);
909
910         if (!timeout)
911                 dev_err(mmc_dev(sdhci->mmc), "Auto calibration failed\n");
912
913         /* Disable Auto calibration */
914         val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
915         val &= ~SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
916         sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
917
918         if (unlikely(soc_data->nvquirks & NVQUIRK_SET_DRIVE_STRENGTH)) {
919                 unsigned int pulldown_code;
920                 unsigned int pullup_code;
921                 int pg;
922                 int err;
923
924                 pg = tegra_drive_get_pingroup(mmc_dev(sdhci->mmc));
925                 if (pg != -1) {
926                         /* Get the pull down codes from auto cal status reg */
927                         pulldown_code = (
928                                 sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) >>
929                                 SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET);
930                         /* Set the pull down in the pinmux reg */
931                         err = tegra_drive_pinmux_set_pull_down(pg,
932                                 pulldown_code);
933                         if (err)
934                                 dev_err(mmc_dev(sdhci->mmc),
935                                 "Failed to set pulldown codes %d err %d\n",
936                                 pulldown_code, err);
937
938                         /* Calculate the pull up codes */
939                         pullup_code = pulldown_code + PULLUP_ADJUSTMENT_OFFSET;
940                         if (pullup_code >= TEGRA_MAX_PULL)
941                                 pullup_code = TEGRA_MAX_PULL - 1;
942                         /* Set the pull up code in the pinmux reg */
943                         err = tegra_drive_pinmux_set_pull_up(pg, pullup_code);
944                         if (err)
945                                 dev_err(mmc_dev(sdhci->mmc),
946                                 "Failed to set pullup codes %d err %d\n",
947                                 pullup_code, err);
948                 }
949         }
950 }
951
952 static int tegra_sdhci_signal_voltage_switch(struct sdhci_host *sdhci,
953         unsigned int signal_voltage)
954 {
955         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
956         struct sdhci_tegra *tegra_host = pltfm_host->priv;
957         unsigned int min_uV = tegra_host->vddio_min_uv;
958         unsigned int max_uV = tegra_host->vddio_max_uv;
959         unsigned int rc = 0;
960         u16 clk, ctrl;
961
962
963         ctrl = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
964         if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
965                 ctrl |= SDHCI_CTRL_VDD_180;
966                 min_uV = SDHOST_LOW_VOLT_MIN;
967                 max_uV = SDHOST_LOW_VOLT_MAX;
968         } else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
969                 if (ctrl & SDHCI_CTRL_VDD_180)
970                         ctrl &= ~SDHCI_CTRL_VDD_180;
971         }
972
973         /* Check if the slot can support the required voltage */
974         if (min_uV > tegra_host->vddio_max_uv)
975                 return 0;
976
977         /* Switch OFF the card clock to prevent glitches on the clock line */
978         clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
979         clk &= ~SDHCI_CLOCK_CARD_EN;
980         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
981
982         /* Set/clear the 1.8V signalling */
983         sdhci_writew(sdhci, ctrl, SDHCI_HOST_CONTROL2);
984
985         /* Switch the I/O rail voltage */
986         if (tegra_host->vdd_io_reg) {
987                 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
988                         min_uV, max_uV);
989                 if (rc) {
990                         dev_err(mmc_dev(sdhci->mmc), "switching to 1.8V"
991                         "failed . Switching back to 3.3V\n");
992                         rc = regulator_set_voltage(tegra_host->vdd_io_reg,
993                                 SDHOST_HIGH_VOLT_MIN,
994                                 SDHOST_HIGH_VOLT_MAX);
995                         if (rc)
996                                 dev_err(mmc_dev(sdhci->mmc),
997                                 "switching to 3.3V also failed\n");
998                 }
999         }
1000
1001         /* Wait for 10 msec for the voltage to be switched */
1002         mdelay(10);
1003
1004         /* Enable the card clock */
1005         clk |= SDHCI_CLOCK_CARD_EN;
1006         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
1007
1008         /* Wait for 1 msec after enabling clock */
1009         mdelay(1);
1010
1011         return rc;
1012 }
1013
1014 static void tegra_sdhci_reset(struct sdhci_host *sdhci, u8 mask)
1015 {
1016         unsigned long timeout;
1017
1018         sdhci_writeb(sdhci, mask, SDHCI_SOFTWARE_RESET);
1019
1020         /* Wait max 100 ms */
1021         timeout = 100;
1022
1023         /* hw clears the bit when it's done */
1024         while (sdhci_readb(sdhci, SDHCI_SOFTWARE_RESET) & mask) {
1025                 if (timeout == 0) {
1026                         dev_err(mmc_dev(sdhci->mmc), "Reset 0x%x never"
1027                                 "completed.\n", (int)mask);
1028                         return;
1029                 }
1030                 timeout--;
1031                 mdelay(1);
1032         }
1033
1034         tegra_sdhci_reset_exit(sdhci, mask);
1035 }
1036
1037 static void sdhci_tegra_set_tap_delay(struct sdhci_host *sdhci,
1038         unsigned int tap_delay)
1039 {
1040         u32 vendor_ctrl;
1041
1042         /* Max tap delay value is 255 */
1043         BUG_ON(tap_delay > MAX_TAP_VALUES);
1044
1045         vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
1046         vendor_ctrl &= ~(0xFF << SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
1047         vendor_ctrl |= (tap_delay << SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
1048         sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
1049 }
1050
1051 static int sdhci_tegra_sd_error_stats(struct sdhci_host *host, u32 int_status)
1052 {
1053         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1054         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1055         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
1056         struct sdhci_tegra_sd_stats *head;
1057
1058         if (tegra_host->sd_stat_head == NULL) {
1059                 tegra_host->sd_stat_head = devm_kzalloc(&pdev->dev, sizeof(
1060                                                 struct sdhci_tegra_sd_stats),
1061                                                 GFP_KERNEL);
1062                 if (tegra_host->sd_stat_head == NULL)
1063                         return -ENOMEM;
1064         }
1065         head = tegra_host->sd_stat_head;
1066         if (int_status & SDHCI_INT_DATA_CRC)
1067                 head->data_crc_count++;
1068         if (int_status & SDHCI_INT_CRC)
1069                 head->cmd_crc_count++;
1070         if (int_status & SDHCI_INT_TIMEOUT)
1071                 head->cmd_to_count++;
1072         if (int_status & SDHCI_INT_DATA_TIMEOUT)
1073                 head->data_to_count++;
1074         return 0;
1075 }
1076
1077 /*
1078  * Calculation of best tap value for low frequencies(82MHz).
1079  * X = Partial win, Y = Full win start, Z = Full win end.
1080  * UI = Z - X.
1081  * Full Window = Z - Y.
1082  * Taps margin = mid-point of 1/2*(curr_freq/max_frequency)*UI
1083  *                    = (1/2)*(1/2)*(82/200)*UI
1084  *                    = (0.1025)*UI
1085  * if Partial win<(0.22)*UI
1086  * best tap = Y+(0.1025*UI)
1087  * else
1088  * best tap = (X-(Z-Y))+(0.1025*UI)
1089  * If best tap<0, best tap = 0
1090  */
1091 static void calculate_low_freq_tap_value(struct sdhci_host *sdhci)
1092 {
1093         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1094         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1095         unsigned int curr_clock;
1096         unsigned int max_clock;
1097         int best_tap_value;
1098         struct tap_window_data *tap_data;
1099         struct tegra_tuning_data *tuning_data;
1100
1101         tuning_data = &tegra_host->tuning_data;
1102         tap_data = tuning_data->tap_data[0];
1103
1104         if (tap_data->abandon_full_win) {
1105                 if (tap_data->abandon_partial_win) {
1106                         tuning_data->best_tap_value = 0;
1107                         return;
1108                 } else {
1109                         tuning_data->select_partial_win = true;
1110                         goto calculate_best_tap;
1111                 }
1112         }
1113
1114         tap_data->tuning_ui = tap_data->full_win_end - tap_data->partial_win;
1115
1116         /* Calculate the sampling point */
1117         curr_clock = sdhci->max_clk / 1000000;
1118         max_clock = uhs_max_freq_MHz[sdhci->mmc->ios.timing];
1119         tap_data->sampling_point = ((tap_data->tuning_ui * curr_clock) /
1120                 max_clock);
1121         tap_data->sampling_point >>= 2;
1122
1123         /*
1124          * Check whether partial window should be used. Use partial window
1125          * if partial window > 0.22(UI).
1126          */
1127         if ((!tap_data->abandon_partial_win) &&
1128                 (tap_data->partial_win > ((22 * tap_data->tuning_ui) / 100)))
1129                         tuning_data->select_partial_win = true;
1130
1131 calculate_best_tap:
1132         if (tuning_data->select_partial_win) {
1133                 best_tap_value = (tap_data->partial_win -
1134                         (tap_data->full_win_end - tap_data->full_win_begin)) +
1135                         tap_data->sampling_point;
1136                 tuning_data->best_tap_value = (best_tap_value < 0) ? 0 :
1137                         best_tap_value;
1138         } else {
1139                 tuning_data->best_tap_value = tap_data->full_win_begin +
1140                         tap_data->sampling_point;
1141         }
1142 }
1143
1144 /*
1145  * Calculation of best tap value for high frequencies(156MHz).
1146  * Tap window data at 1.25V core voltage
1147  * X = Partial win, Y = Full win start, Z = Full win end.
1148  * Full Window = Z-Y.
1149  * UI = Z-X.
1150  * Tap_margin = (0.20375)UI
1151  *
1152  * Tap window data at 1.1V core voltage
1153  * X' = Partial win, Y' = Full win start, Z' = Full win end.
1154  * UI' = Z'-X'.
1155  * Full Window' = Z'-Y'.
1156  * Tap_margin' = (0.20375)UI'
1157  *
1158  * Full_window_tap=[(Z'-0.20375UI')+(Y+0.20375UI)]/2
1159  * Partial_window_tap=[(X'-0.20375UI')+(X-(Z-Y)+0x20375UI)]/2
1160  * if(Partial_window_tap < 0), Partial_window_tap=0
1161  *
1162  * Full_window_quality=[(Z'-0.20375UI')-(Y+0.20375UI)]/2
1163  * Partial_window_quality=(X'-0.20375UI')-Partial_window_tap
1164  * if(Full_window_quality>Partial_window_quality) choose full window,
1165  * else choose partial window.
1166  * If there is no margin window for both cases,
1167  * best tap=(Y+Z')/2.
1168  */
1169 static void calculate_high_freq_tap_value(struct sdhci_host *sdhci)
1170 {
1171         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1172         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1173         unsigned int curr_clock;
1174         unsigned int max_clock;
1175         struct tap_window_data *vmax_tap_data;
1176         struct tap_window_data *vmid_tap_data;
1177         struct tegra_tuning_data *tuning_data;
1178         unsigned int full_win_tap;
1179         int partial_win_start;
1180         int partial_win_tap;
1181         int full_win_quality;
1182         int partial_win_quality;
1183
1184         tuning_data = &tegra_host->tuning_data;
1185         vmax_tap_data = tuning_data->tap_data[0];
1186         vmid_tap_data = tuning_data->tap_data[1];
1187
1188         curr_clock = sdhci->max_clk / 1000000;
1189         max_clock = uhs_max_freq_MHz[sdhci->mmc->ios.timing];
1190
1191         /*
1192          * Calculate the tuning_ui and sampling points for tap windows found
1193          * at all core voltages.
1194          */
1195         vmax_tap_data->tuning_ui = vmax_tap_data->full_win_end -
1196                 vmax_tap_data->partial_win;
1197         vmax_tap_data->sampling_point =
1198                 (vmax_tap_data->tuning_ui * curr_clock) / max_clock;
1199         vmax_tap_data->sampling_point >>= 2;
1200
1201         vmid_tap_data->tuning_ui = vmid_tap_data->full_win_end -
1202                 vmid_tap_data->partial_win;
1203         vmid_tap_data->sampling_point =
1204                 (vmid_tap_data->tuning_ui * curr_clock) / max_clock;
1205         vmid_tap_data->sampling_point >>= 2;
1206
1207         full_win_tap = ((vmid_tap_data->full_win_end -
1208                 vmid_tap_data->sampling_point) +
1209                 (vmax_tap_data->full_win_begin +
1210                 vmax_tap_data->sampling_point));
1211         full_win_tap >>= 1;
1212         full_win_quality = (vmid_tap_data->full_win_end -
1213                 vmid_tap_data->sampling_point) -
1214                 (vmax_tap_data->full_win_begin +
1215                 vmax_tap_data->sampling_point);
1216         full_win_quality >>= 1;
1217
1218         partial_win_start = (vmax_tap_data->partial_win -
1219                 (vmax_tap_data->full_win_end -
1220                 vmax_tap_data->full_win_begin));
1221         partial_win_tap = ((vmid_tap_data->partial_win -
1222                 vmid_tap_data->sampling_point) +
1223                 (partial_win_start + vmax_tap_data->sampling_point));
1224         partial_win_tap >>= 1;
1225         if (partial_win_tap < 0)
1226                 partial_win_tap = 0;
1227         partial_win_quality = (vmid_tap_data->partial_win -
1228                 vmid_tap_data->sampling_point) - partial_win_tap;
1229
1230         if ((full_win_quality <= 0) && (partial_win_quality)) {
1231                 dev_warn(mmc_dev(sdhci->mmc),
1232                         "No margin window for both windows\n");
1233                 tuning_data->best_tap_value = vmax_tap_data->full_win_begin +
1234                         vmid_tap_data->full_win_end;
1235                 tuning_data->best_tap_value >>= 1;
1236         } else {
1237                 if (full_win_quality > partial_win_quality) {
1238                         tuning_data->best_tap_value = full_win_tap;
1239                 } else {
1240                         tuning_data->best_tap_value = partial_win_tap;
1241                         tuning_data->select_partial_win = true;
1242                 }
1243         }
1244 }
1245
1246 static int sdhci_tegra_run_frequency_tuning(struct sdhci_host *sdhci)
1247 {
1248         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1249         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1250         int err = 0;
1251         u8 ctrl;
1252         u32 mask;
1253         unsigned int timeout = 10;
1254         int flags;
1255         u32 intstatus;
1256
1257         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
1258         while (sdhci_readl(sdhci, SDHCI_PRESENT_STATE) & mask) {
1259                 if (timeout == 0) {
1260                         dev_err(mmc_dev(sdhci->mmc), "Controller never"
1261                                 "released inhibit bit(s).\n");
1262                         err = -ETIMEDOUT;
1263                         goto out;
1264                 }
1265                 timeout--;
1266                 mdelay(1);
1267         }
1268
1269         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1270         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1271         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1272
1273         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1274         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1275         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1276
1277         /*
1278          * In response to CMD19, the card sends 64 bytes of tuning
1279          * block to the Host Controller. So we set the block size
1280          * to 64 here.
1281          * In response to CMD21, the card sends 128 bytes of tuning
1282          * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
1283          * to the Host Controller. So we set the block size to 64 here.
1284          */
1285         sdhci_writew(sdhci, SDHCI_MAKE_BLKSZ(7, tegra_host->tuning_bsize),
1286                 SDHCI_BLOCK_SIZE);
1287
1288         sdhci_writeb(sdhci, 0xE, SDHCI_TIMEOUT_CONTROL);
1289
1290         sdhci_writeb(sdhci, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1291
1292         sdhci_writel(sdhci, 0x0, SDHCI_ARGUMENT);
1293
1294         /* Set the cmd flags */
1295         flags = SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_DATA;
1296         /* Issue the command */
1297         sdhci_writew(sdhci, SDHCI_MAKE_CMD(
1298                 tegra_host->tuning_opcode, flags), SDHCI_COMMAND);
1299
1300         timeout = 5;
1301         do {
1302                 timeout--;
1303                 mdelay(1);
1304                 intstatus = sdhci_readl(sdhci, SDHCI_INT_STATUS);
1305                 if (intstatus) {
1306                         sdhci_writel(sdhci, intstatus, SDHCI_INT_STATUS);
1307                         break;
1308                 }
1309         } while(timeout);
1310
1311         if ((intstatus & SDHCI_INT_DATA_AVAIL) &&
1312                 !(intstatus & SDHCI_INT_DATA_CRC)) {
1313                 err = 0;
1314                 sdhci->tuning_done = 1;
1315         } else {
1316                 tegra_sdhci_reset(sdhci, SDHCI_RESET_CMD);
1317                 tegra_sdhci_reset(sdhci, SDHCI_RESET_DATA);
1318                 err = -EIO;
1319         }
1320
1321         if (sdhci->tuning_done) {
1322                 sdhci->tuning_done = 0;
1323                 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1324                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING) &&
1325                         (ctrl & SDHCI_CTRL_TUNED_CLK))
1326                         err = 0;
1327                 else
1328                         err = -EIO;
1329         }
1330         mdelay(1);
1331 out:
1332         return err;
1333 }
1334
1335 static int sdhci_tegra_scan_tap_values(struct sdhci_host *sdhci,
1336         unsigned int starting_tap, bool expect_failure)
1337 {
1338         unsigned int tap_value = starting_tap;
1339         int err;
1340
1341         do {
1342                 /* Set the tap delay */
1343                 sdhci_tegra_set_tap_delay(sdhci, tap_value);
1344
1345                 /* Run frequency tuning */
1346                 err = sdhci_tegra_run_frequency_tuning(sdhci);
1347                 if ((expect_failure && !err) ||
1348                         (!expect_failure && err))
1349                         break;
1350                 tap_value++;
1351         } while (tap_value <= MAX_TAP_VALUES);
1352
1353         return tap_value;
1354 }
1355
1356 /*
1357  * While scanning for tap values, first get the partial window followed by the
1358  * full window. Note that, when scanning for full win start, tuning has to be
1359  * run until a passing tap value is found. Hence, failure is expected during
1360  * this process and ignored.
1361  */
1362 static int sdhci_tegra_get_tap_window_data(struct sdhci_host *sdhci,
1363         struct tap_window_data *tap_data)
1364 {
1365         unsigned int tap_value;
1366         int err = 0;
1367
1368         if (!tap_data) {
1369                 dev_err(mmc_dev(sdhci->mmc), "Invalid tap data\n");
1370                 return -ENODATA;
1371         }
1372
1373         /* Get the partial window data */
1374         tap_value = 0;
1375         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, false);
1376         if (!tap_value) {
1377                 tap_data->abandon_partial_win = true;
1378                 tap_data->partial_win = 0;
1379         } else if (tap_value > MAX_TAP_VALUES) {
1380                 /*
1381                  * If tap value is more than 0xFF, we have hit the miracle case
1382                  * of all tap values passing. Discard full window as passing
1383                  * window has covered all taps.
1384                  */
1385                 tap_data->partial_win = MAX_TAP_VALUES;
1386                 tap_data->abandon_full_win = true;
1387                 goto out;
1388         } else {
1389                 tap_data->partial_win = tap_value - 1;
1390                 if (tap_value == MAX_TAP_VALUES) {
1391                         /* All tap values exhausted. No full window */
1392                         tap_data->abandon_full_win = true;
1393                         goto out;
1394                 }
1395         }
1396
1397         /* Get the full window start */
1398         tap_value++;
1399         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, true);
1400         if (tap_value > MAX_TAP_VALUES) {
1401                 /* All tap values exhausted. No full window */
1402                 tap_data->abandon_full_win = true;
1403                 goto out;
1404         } else {
1405                 tap_data->full_win_begin = tap_value;
1406                 /*
1407                  * If full win start is 0xFF, then set that as full win end
1408                  * and exit.
1409                  */
1410                 if (tap_value == MAX_TAP_VALUES) {
1411                         tap_data->full_win_end = tap_value;
1412                         goto out;
1413                 }
1414         }
1415
1416         /* Get the full window end */
1417         tap_value++;
1418         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, false);
1419         tap_data->full_win_end = tap_value - 1;
1420         if (tap_value > MAX_TAP_VALUES)
1421                 tap_data->full_win_end = MAX_TAP_VALUES;
1422 out:
1423         /*
1424          * Mark tuning as failed if both partial and full windows are
1425          * abandoned.
1426          */
1427         if (tap_data->abandon_partial_win && tap_data->abandon_full_win)
1428                 err = -EIO;
1429         return err;
1430 }
1431
1432 static int sdhci_tegra_execute_tuning(struct sdhci_host *sdhci, u32 opcode)
1433 {
1434         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1435         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1436         struct tegra_tuning_data *tuning_data;
1437         struct tap_window_data *tap_data;
1438         int err;
1439         u16 ctrl_2;
1440         u32 ier;
1441         unsigned int freq_band;
1442         unsigned int i;
1443         unsigned int voltage;
1444
1445         /* Tuning is valid only in SDR104 and SDR50 modes */
1446         ctrl_2 = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
1447         if (!(((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1448                 (((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1449                 (sdhci->flags & SDHCI_SDR50_NEEDS_TUNING))))
1450                         return 0;
1451
1452         /* Tuning should be done only for MMC_BUS_WIDTH_8 and MMC_BUS_WIDTH_4 */
1453         if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1454                 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8;
1455         else if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1456                 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4;
1457         else
1458                 return -EINVAL;
1459
1460         /* Set the tuning command to be used */
1461         tegra_host->tuning_opcode = opcode;
1462
1463         /*
1464          * Disable all interrupts signalling.Enable interrupt status
1465          * detection for buffer read ready and data crc. We use
1466          * polling for tuning as it involves less overhead.
1467          */
1468         ier = sdhci_readl(sdhci, SDHCI_INT_ENABLE);
1469         sdhci_writel(sdhci, 0, SDHCI_SIGNAL_ENABLE);
1470         sdhci_writel(sdhci, SDHCI_INT_DATA_AVAIL |
1471                 SDHCI_INT_DATA_CRC, SDHCI_INT_ENABLE);
1472
1473         /*
1474          * If tuning is already done and retune request is not set, then skip
1475          * best tap value calculation and use the old best tap value.
1476          */
1477         if (tegra_host->tuning_status == TUNING_STATUS_DONE)
1478                 goto set_best_tap;
1479
1480         if (sdhci->max_clk > tuning_params[TUNING_LOW_FREQ].freq_hz)
1481                 freq_band = TUNING_HIGH_FREQ;
1482         else
1483                 freq_band = TUNING_LOW_FREQ;
1484
1485         /*
1486          * Run tuning and get the passing tap window info for all frequencies
1487          * and core voltages required to calculate the final tap value. The
1488          * standard driver calls this platform specific tuning callback after
1489          * holding a lock. The spinlock needs to be released when calling
1490          * non-atomic context functions like regulator calls etc.
1491          */
1492         tuning_data = &tegra_host->tuning_data;
1493         for (i = 0; i < tuning_params[freq_band].nr_voltages; i++) {
1494                 spin_unlock(&sdhci->lock);
1495                 if (!tuning_data->tap_data[i]) {
1496                         tuning_data->tap_data[i] = devm_kzalloc(
1497                                 mmc_dev(sdhci->mmc),
1498                                 sizeof(struct tap_window_data), GFP_KERNEL);
1499                         if (!tuning_data->tap_data[i]) {
1500                                 err = -ENOMEM;
1501                                 dev_err(mmc_dev(sdhci->mmc),
1502                                         "Insufficient memory for tap window info\n");
1503                                 spin_lock(&sdhci->lock);
1504                                 goto out;
1505                         }
1506                 }
1507                 tap_data = tuning_data->tap_data[i];
1508
1509                 if (tegra_host->nominal_vcore_uV) {
1510                         if (!tegra_host->vcore_reg)
1511                                 tegra_host->vcore_reg = regulator_get(
1512                                 mmc_dev(sdhci->mmc), "vdd_core");
1513                         if (IS_ERR_OR_NULL(tegra_host->vcore_reg)) {
1514                                 dev_info(mmc_dev(sdhci->mmc),
1515                                         "No vdd_core %ld. Tuning might fail.\n",
1516                                         PTR_ERR(tegra_host->vcore_reg));
1517                                 tegra_host->vcore_reg = NULL;
1518                         } else {
1519                                 voltage = tuning_params[freq_band].voltages[i];
1520                                 if (voltage > tegra_host->nominal_vcore_uV)
1521                                         voltage = tegra_host->nominal_vcore_uV;
1522                                 err = regulator_set_voltage(
1523                                         tegra_host->vcore_reg, voltage,
1524                                         voltage);
1525                                 if (err)
1526                                         dev_err(mmc_dev(sdhci->mmc),
1527                                                 "Setting nominal core voltage failed\n");
1528                         }
1529                 }
1530                 spin_lock(&sdhci->lock);
1531
1532                 /* Get the tuning window info */
1533                 err = sdhci_tegra_get_tap_window_data(sdhci, tap_data);
1534                 if (err) {
1535                         dev_err(mmc_dev(sdhci->mmc), "Failed to tuning window info\n");
1536                         goto out;
1537                 }
1538         }
1539
1540         /* Calculate best tap for current freq band */
1541         if (freq_band == TUNING_LOW_FREQ)
1542                 calculate_low_freq_tap_value(sdhci);
1543         else
1544                 calculate_high_freq_tap_value(sdhci);
1545
1546 set_best_tap:
1547         sdhci_tegra_set_tap_delay(sdhci,
1548                 tegra_host->tuning_data.best_tap_value);
1549
1550         /*
1551          * Run tuning with the best tap value. If tuning fails, set the status
1552          * for retuning next time enumeration is done.
1553          */
1554         err = sdhci_tegra_run_frequency_tuning(sdhci);
1555         if (err)
1556                 tegra_host->tuning_status = TUNING_STATUS_RETUNE;
1557         else
1558                 tegra_host->tuning_status = TUNING_STATUS_DONE;
1559
1560 out:
1561         /* Enable the full range for core voltage if vcore_reg exists */
1562         if (tegra_host->vcore_reg) {
1563                 spin_unlock(&sdhci->lock);
1564                 regulator_put(tegra_host->vcore_reg);
1565                 tegra_host->vcore_reg = NULL;
1566                 spin_lock(&sdhci->lock);
1567         }
1568
1569         /* Enable interrupts. Enable full range for core voltage */
1570         sdhci_writel(sdhci, ier, SDHCI_INT_ENABLE);
1571         sdhci_writel(sdhci, ier, SDHCI_SIGNAL_ENABLE);
1572         return err;
1573 }
1574
1575 static int tegra_sdhci_suspend(struct sdhci_host *sdhci)
1576 {
1577         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1578         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1579
1580         tegra_sdhci_set_clock(sdhci, 0);
1581
1582         /* Disable the power rails if any */
1583         if (tegra_host->card_present) {
1584                 if (tegra_host->is_rail_enabled) {
1585                         if (tegra_host->vdd_io_reg)
1586                                 regulator_disable(tegra_host->vdd_io_reg);
1587                         if (tegra_host->vdd_slot_reg)
1588                                 regulator_disable(tegra_host->vdd_slot_reg);
1589                         tegra_host->is_rail_enabled = 0;
1590                 }
1591         }
1592
1593         if (tegra_host->dpd) {
1594                 mutex_lock(&tegra_host->dpd->delay_lock);
1595                 tegra_host->dpd->need_delay_dpd = 1;
1596                 mutex_unlock(&tegra_host->dpd->delay_lock);
1597         }
1598
1599         return 0;
1600 }
1601
1602 static int tegra_sdhci_resume(struct sdhci_host *sdhci)
1603 {
1604         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1605         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1606         struct platform_device *pdev;
1607         struct tegra_sdhci_platform_data *plat;
1608
1609         pdev = to_platform_device(mmc_dev(sdhci->mmc));
1610         plat = pdev->dev.platform_data;
1611
1612         if (gpio_is_valid(plat->cd_gpio))
1613                 tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
1614
1615         /* Enable the power rails if any */
1616         if (tegra_host->card_present) {
1617                 if (!tegra_host->is_rail_enabled) {
1618                         if (tegra_host->vdd_slot_reg)
1619                                 regulator_enable(tegra_host->vdd_slot_reg);
1620                         if (tegra_host->vdd_io_reg) {
1621                                 regulator_enable(tegra_host->vdd_io_reg);
1622                                 if (plat->mmc_data.ocr_mask &
1623                                                         SDHOST_1V8_OCR_MASK)
1624                                         tegra_sdhci_signal_voltage_switch(sdhci,
1625                                                         MMC_SIGNAL_VOLTAGE_180);
1626                                 else
1627                                         tegra_sdhci_signal_voltage_switch(sdhci,
1628                                                         MMC_SIGNAL_VOLTAGE_330);
1629                         }
1630                         tegra_host->is_rail_enabled = 1;
1631                 }
1632         }
1633
1634         /* Setting the min identification clock of freq 400KHz */
1635         tegra_sdhci_set_clock(sdhci, 400000);
1636
1637         /* Reset the controller and power on if MMC_KEEP_POWER flag is set*/
1638         if (sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER) {
1639                 tegra_sdhci_reset(sdhci, SDHCI_RESET_ALL);
1640                 sdhci_writeb(sdhci, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1641                 sdhci->pwr = 0;
1642         }
1643
1644         return 0;
1645 }
1646
1647 static void tegra_sdhci_post_resume(struct sdhci_host *sdhci)
1648 {
1649         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1650         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1651
1652         if (tegra_host->card_present) {
1653                 if (tegra_host->sd_detect_in_suspend)
1654                         tasklet_schedule(&sdhci->card_tasklet);
1655         } else if (tegra_host->clk_enabled) {
1656                 /* Turn OFF the clocks if the card is not present */
1657                 tegra_sdhci_set_clock(sdhci, 0);
1658         }
1659 }
1660
1661 static void sdhci_tegra_error_stats_debugfs(struct sdhci_host *host)
1662 {
1663         struct dentry *root;
1664
1665         root = debugfs_create_dir(dev_name(mmc_dev(host->mmc)), NULL);
1666         if (IS_ERR(root))
1667                 /* Don't complain -- debugfs just isn't enabled */
1668                 return;
1669         if (!root)
1670                 /* Complain -- debugfs is enabled, but it failed to
1671                  * create the directory. */
1672                 goto err_root;
1673
1674         host->debugfs_root = root;
1675
1676         if (!debugfs_create_file("error_stats", S_IRUSR, root, host,
1677                                 &sdhci_host_fops))
1678                 goto err_node;
1679         return;
1680
1681 err_node:
1682         debugfs_remove_recursive(root);
1683         host->debugfs_root = NULL;
1684 err_root:
1685         pr_err("%s: Failed to initialize debugfs functionality\n", __func__);
1686         return;
1687 }
1688
1689 static struct sdhci_ops tegra_sdhci_ops = {
1690 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
1691         .get_ro     = tegra_sdhci_get_ro,
1692 #endif
1693         .get_cd     = tegra_sdhci_get_cd,
1694         .read_l     = tegra_sdhci_readl,
1695         .read_w     = tegra_sdhci_readw,
1696         .write_l    = tegra_sdhci_writel,
1697         .platform_8bit_width = tegra_sdhci_8bit,
1698         .set_clock              = tegra_sdhci_set_clock,
1699         .suspend                = tegra_sdhci_suspend,
1700         .resume                 = tegra_sdhci_resume,
1701         .platform_resume        = tegra_sdhci_post_resume,
1702         .platform_reset_exit    = tegra_sdhci_reset_exit,
1703         .set_uhs_signaling      = tegra_sdhci_set_uhs_signaling,
1704         .switch_signal_voltage  = tegra_sdhci_signal_voltage_switch,
1705         .switch_signal_voltage_exit = tegra_sdhci_do_calibration,
1706         .execute_freq_tuning    = sdhci_tegra_execute_tuning,
1707         .sd_error_stats         = sdhci_tegra_sd_error_stats,
1708 };
1709
1710 static struct sdhci_pltfm_data sdhci_tegra20_pdata = {
1711         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1712 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1713                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1714                   SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING |
1715                   SDHCI_QUIRK_NON_STANDARD_TUNING |
1716 #endif
1717 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1718                   SDHCI_QUIRK_NONSTANDARD_CLOCK |
1719 #endif
1720                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1721                   SDHCI_QUIRK_NO_HISPD_BIT |
1722                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1723                   SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1724                   SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO,
1725         .quirks2 = SDHCI_QUIRK2_BROKEN_PRESET_VALUES,
1726         .ops  = &tegra_sdhci_ops,
1727 };
1728
1729 static struct sdhci_tegra_soc_data soc_data_tegra20 = {
1730         .pdata = &sdhci_tegra20_pdata,
1731         .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1732 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1733                    NVQUIRK_ENABLE_PADPIPE_CLKEN |
1734                    NVQUIRK_DISABLE_SPI_MODE_CLKEN |
1735                    NVQUIRK_SET_TAP_DELAY |
1736                    NVQUIRK_ENABLE_SDR50_TUNING |
1737                    NVQUIRK_ENABLE_SDR50 |
1738                    NVQUIRK_ENABLE_SDR104 |
1739 #endif
1740 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
1741                     NVQUIRK_SET_DRIVE_STRENGTH |
1742 #endif
1743 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1744                     NVQUIRK_DISABLE_AUTO_CALIBRATION |
1745 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
1746                     NVQUIRK_SET_CALIBRATION_OFFSETS |
1747                     NVQUIRK_ENABLE_SD_3_0 |
1748 #else
1749                     NVQUIRK_SET_TRIM_DELAY |
1750                     NVQUIRK_ENABLE_DDR50 |
1751                     NVQUIRK_INFINITE_ERASE_TIMEOUT |
1752 #endif
1753                     NVQUIRK_ENABLE_BLOCK_GAP_DET,
1754 };
1755
1756 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1757 static struct sdhci_pltfm_data sdhci_tegra30_pdata = {
1758         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1759                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1760                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1761                   SDHCI_QUIRK_NO_HISPD_BIT |
1762                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
1763         .ops  = &tegra_sdhci_ops,
1764 };
1765
1766 static struct sdhci_tegra_soc_data soc_data_tegra30 = {
1767         .pdata = &sdhci_tegra30_pdata,
1768 };
1769 #endif
1770
1771 static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = {
1772 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1773         { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1774 #endif
1775 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1776         { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1777 #endif
1778         {}
1779 };
1780 MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
1781
1782 static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata(
1783                                                 struct platform_device *pdev)
1784 {
1785         struct tegra_sdhci_platform_data *plat;
1786         struct device_node *np = pdev->dev.of_node;
1787
1788         if (!np)
1789                 return NULL;
1790
1791         plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1792         if (!plat) {
1793                 dev_err(&pdev->dev, "Can't allocate platform data\n");
1794                 return NULL;
1795         }
1796
1797         plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1798         plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1799         plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
1800         if (of_find_property(np, "support-8bit", NULL))
1801                 plat->is_8bit = 1;
1802
1803         return plat;
1804 }
1805
1806 static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
1807 {
1808         const struct of_device_id *match;
1809         const struct sdhci_tegra_soc_data *soc_data;
1810         struct sdhci_host *host;
1811         struct sdhci_pltfm_host *pltfm_host;
1812         struct tegra_sdhci_platform_data *plat;
1813         struct sdhci_tegra *tegra_host;
1814         int rc;
1815
1816         match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
1817         if (match)
1818                 soc_data = match->data;
1819         else
1820                 soc_data = &soc_data_tegra20;
1821
1822         host = sdhci_pltfm_init(pdev, soc_data->pdata);
1823         if (IS_ERR(host))
1824                 return PTR_ERR(host);
1825
1826         pltfm_host = sdhci_priv(host);
1827
1828         plat = pdev->dev.platform_data;
1829
1830         if (plat == NULL)
1831                 plat = sdhci_tegra_dt_parse_pdata(pdev);
1832
1833         if (plat == NULL) {
1834                 dev_err(mmc_dev(host->mmc), "missing platform data\n");
1835                 rc = -ENXIO;
1836                 goto err_no_plat;
1837         }
1838
1839         tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
1840         if (!tegra_host) {
1841                 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
1842                 rc = -ENOMEM;
1843                 goto err_no_plat;
1844         }
1845
1846         tegra_host->plat = plat;
1847         tegra_host->sd_stat_head = NULL;
1848         tegra_host->soc_data = soc_data;
1849
1850         pltfm_host->priv = tegra_host;
1851
1852         pll_c = clk_get_sys(NULL, "pll_c");
1853         if (IS_ERR(pll_c)) {
1854                 rc = PTR_ERR(pll_c);
1855                 dev_err(mmc_dev(host->mmc),
1856                         "clk error in getting pll_c: %d\n", rc);
1857         }
1858
1859         pll_p = clk_get_sys(NULL, "pll_p");
1860         if (IS_ERR(pll_p)) {
1861                 rc = PTR_ERR(pll_p);
1862                 dev_err(mmc_dev(host->mmc),
1863                         "clk error in getting pll_p: %d\n", rc);
1864         }
1865
1866         pll_c_rate = clk_get_rate(pll_c);
1867         pll_p_rate = clk_get_rate(pll_p);
1868
1869 #ifdef CONFIG_MMC_EMBEDDED_SDIO
1870         if (plat->mmc_data.embedded_sdio)
1871                 mmc_set_embedded_sdio_data(host->mmc,
1872                         &plat->mmc_data.embedded_sdio->cis,
1873                         &plat->mmc_data.embedded_sdio->cccr,
1874                         plat->mmc_data.embedded_sdio->funcs,
1875                         plat->mmc_data.embedded_sdio->num_funcs);
1876 #endif
1877
1878         if (gpio_is_valid(plat->power_gpio)) {
1879                 rc = gpio_request(plat->power_gpio, "sdhci_power");
1880                 if (rc) {
1881                         dev_err(mmc_dev(host->mmc),
1882                                 "failed to allocate power gpio\n");
1883                         goto err_power_req;
1884                 }
1885                 gpio_direction_output(plat->power_gpio, 1);
1886         }
1887
1888         if (gpio_is_valid(plat->cd_gpio)) {
1889                 rc = gpio_request(plat->cd_gpio, "sdhci_cd");
1890                 if (rc) {
1891                         dev_err(mmc_dev(host->mmc),
1892                                 "failed to allocate cd gpio\n");
1893                         goto err_cd_req;
1894                 }
1895                 gpio_direction_input(plat->cd_gpio);
1896
1897                 tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
1898
1899                 rc = request_threaded_irq(gpio_to_irq(plat->cd_gpio), NULL,
1900                                  carddetect_irq,
1901                                  IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1902                                  mmc_hostname(host->mmc), host);
1903
1904                 if (rc) {
1905                         dev_err(mmc_dev(host->mmc), "request irq error\n");
1906                         goto err_cd_irq_req;
1907                 }
1908                 rc = enable_irq_wake(gpio_to_irq(plat->cd_gpio));
1909                 if (rc < 0)
1910                         dev_err(mmc_dev(host->mmc),
1911                                 "SD card wake-up event registration"
1912                                         "failed with eroor: %d\n", rc);
1913
1914         } else if (plat->mmc_data.register_status_notify) {
1915                 plat->mmc_data.register_status_notify(sdhci_status_notify_cb, host);
1916         }
1917
1918         if (plat->mmc_data.status) {
1919                 plat->mmc_data.card_present = plat->mmc_data.status(mmc_dev(host->mmc));
1920         }
1921
1922         if (gpio_is_valid(plat->wp_gpio)) {
1923                 rc = gpio_request(plat->wp_gpio, "sdhci_wp");
1924                 if (rc) {
1925                         dev_err(mmc_dev(host->mmc),
1926                                 "failed to allocate wp gpio\n");
1927                         goto err_wp_req;
1928                 }
1929                 gpio_direction_input(plat->wp_gpio);
1930         }
1931
1932         /*
1933          * If there is no card detect gpio, assume that the
1934          * card is always present.
1935          */
1936         if (!gpio_is_valid(plat->cd_gpio))
1937                 tegra_host->card_present = 1;
1938
1939         if (plat->mmc_data.ocr_mask & SDHOST_1V8_OCR_MASK) {
1940                 tegra_host->vddio_min_uv = SDHOST_LOW_VOLT_MIN;
1941                 tegra_host->vddio_max_uv = SDHOST_LOW_VOLT_MAX;
1942         } else if (plat->mmc_data.ocr_mask & MMC_OCR_2V8_MASK) {
1943                         tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_2V8;
1944                         tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
1945         } else {
1946                 /*
1947                  * Set the minV and maxV to default
1948                  * voltage range of 2.7V - 3.6V
1949                  */
1950                 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_MIN;
1951                 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
1952         }
1953
1954         tegra_host->vdd_io_reg = regulator_get(mmc_dev(host->mmc),
1955                                                         "vddio_sdmmc");
1956         if (IS_ERR_OR_NULL(tegra_host->vdd_io_reg)) {
1957                 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
1958                         "Assuming vddio_sdmmc is not required.\n",
1959                         "vddio_sdmmc", PTR_ERR(tegra_host->vdd_io_reg));
1960                 tegra_host->vdd_io_reg = NULL;
1961         } else {
1962                 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1963                         tegra_host->vddio_min_uv,
1964                         tegra_host->vddio_max_uv);
1965                 if (rc) {
1966                         dev_err(mmc_dev(host->mmc), "%s regulator_set_voltage failed: %d",
1967                                 "vddio_sdmmc", rc);
1968                         regulator_put(tegra_host->vdd_io_reg);
1969                         tegra_host->vdd_io_reg = NULL;
1970                 }
1971         }
1972
1973         tegra_host->vdd_slot_reg = regulator_get(mmc_dev(host->mmc),
1974                                                         "vddio_sd_slot");
1975         if (IS_ERR_OR_NULL(tegra_host->vdd_slot_reg)) {
1976                 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
1977                         " Assuming vddio_sd_slot is not required.\n",
1978                         "vddio_sd_slot", PTR_ERR(tegra_host->vdd_slot_reg));
1979                 tegra_host->vdd_slot_reg = NULL;
1980         }
1981
1982         if (tegra_host->card_present) {
1983                 if (tegra_host->vdd_slot_reg)
1984                         regulator_enable(tegra_host->vdd_slot_reg);
1985                 if (tegra_host->vdd_io_reg)
1986                         regulator_enable(tegra_host->vdd_io_reg);
1987                 tegra_host->is_rail_enabled = 1;
1988         }
1989
1990         pm_runtime_enable(&pdev->dev);
1991         pltfm_host->clk = clk_get(mmc_dev(host->mmc), NULL);
1992         if (IS_ERR(pltfm_host->clk)) {
1993                 dev_err(mmc_dev(host->mmc), "clk err\n");
1994                 rc = PTR_ERR(pltfm_host->clk);
1995                 goto err_clk_get;
1996         }
1997
1998         if (clk_get_parent(pltfm_host->clk) == pll_c)
1999                 tegra_host->is_parent_pllc = true;
2000
2001         pm_runtime_get_sync(&pdev->dev);
2002         rc = clk_prepare_enable(pltfm_host->clk);
2003         if (rc != 0)
2004                 goto err_clk_put;
2005
2006         if (!strcmp(dev_name(mmc_dev(host->mmc)), "sdhci-tegra.3")) {
2007                 tegra_host->emc_clk = clk_get(mmc_dev(host->mmc), "emc");
2008                 if (IS_ERR(tegra_host->emc_clk)) {
2009                         dev_err(mmc_dev(host->mmc), "clk err\n");
2010                         rc = PTR_ERR(tegra_host->emc_clk);
2011                         goto err_clk_put;
2012                 }
2013                 tegra_host->emc_max_clk =
2014                         clk_round_rate(tegra_host->emc_clk, ULONG_MAX);
2015         }
2016
2017         pltfm_host->priv = tegra_host;
2018         tegra_host->clk_enabled = true;
2019         tegra_host->max_clk_limit = plat->max_clk_limit;
2020         tegra_host->ddr_clk_limit = plat->ddr_clk_limit;
2021         tegra_host->sd_detect_in_suspend = plat->sd_detect_in_suspend;
2022         tegra_host->instance = pdev->id;
2023         tegra_host->dpd = tegra_io_dpd_get(mmc_dev(host->mmc));
2024
2025         host->mmc->pm_caps |= plat->pm_caps;
2026         host->mmc->pm_flags |= plat->pm_flags;
2027
2028         host->mmc->caps |= MMC_CAP_ERASE;
2029         /* enable 1/8V DDR capable */
2030         host->mmc->caps |= MMC_CAP_1_8V_DDR;
2031         if (plat->is_8bit)
2032                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
2033         host->mmc->caps |= MMC_CAP_SDIO_IRQ;
2034         host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_IGNORE_PM_NOTIFY;
2035         if (plat->mmc_data.built_in) {
2036                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
2037         }
2038         host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY;
2039
2040 #ifdef CONFIG_MMC_BKOPS
2041         host->mmc->caps2 |= MMC_CAP2_BKOPS;
2042 #endif
2043         tegra_sdhost_min_freq = TEGRA_SDHOST_MIN_FREQ;
2044 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
2045         tegra_host->hw_ops = &tegra_2x_sdhci_ops;
2046         tegra_sdhost_std_freq = TEGRA2_SDHOST_STD_FREQ;
2047 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
2048         tegra_host->hw_ops = &tegra_3x_sdhci_ops;
2049         tegra_sdhost_std_freq = TEGRA3_SDHOST_STD_FREQ;
2050 #else
2051         tegra_host->hw_ops = &tegra_11x_sdhci_ops;
2052         tegra_sdhost_std_freq = TEGRA3_SDHOST_STD_FREQ;
2053         host->mmc->caps2 |= MMC_CAP2_HS200;
2054 #endif
2055
2056         if (plat->nominal_vcore_uV)
2057                 tegra_host->nominal_vcore_uV = plat->nominal_vcore_uV;
2058         host->edp_support = plat->edp_support ? true : false;
2059         if (host->edp_support)
2060                 for (rc = 0; rc < SD_EDP_NUM_STATES; rc++)
2061                         host->edp_states[rc] = plat->edp_states[rc];
2062
2063         rc = sdhci_add_host(host);
2064
2065         sdhci_tegra_error_stats_debugfs(host);
2066         if (rc)
2067                 goto err_add_host;
2068
2069         /* Enable async suspend/resume to reduce LP0 latency */
2070         device_enable_async_suspend(&pdev->dev);
2071
2072         return 0;
2073
2074 err_add_host:
2075         clk_put(tegra_host->emc_clk);
2076         clk_disable_unprepare(pltfm_host->clk);
2077         pm_runtime_put_sync(&pdev->dev);
2078 err_clk_put:
2079         clk_put(pltfm_host->clk);
2080 err_clk_get:
2081         if (gpio_is_valid(plat->wp_gpio))
2082                 gpio_free(plat->wp_gpio);
2083 err_wp_req:
2084         if (gpio_is_valid(plat->cd_gpio))
2085                 free_irq(gpio_to_irq(plat->cd_gpio), host);
2086 err_cd_irq_req:
2087         if (gpio_is_valid(plat->cd_gpio))
2088                 gpio_free(plat->cd_gpio);
2089 err_cd_req:
2090         if (gpio_is_valid(plat->power_gpio))
2091                 gpio_free(plat->power_gpio);
2092 err_power_req:
2093 err_no_plat:
2094         sdhci_pltfm_free(pdev);
2095         return rc;
2096 }
2097
2098 static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
2099 {
2100         struct sdhci_host *host = platform_get_drvdata(pdev);
2101         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2102         struct sdhci_tegra *tegra_host = pltfm_host->priv;
2103         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
2104         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
2105
2106         sdhci_remove_host(host, dead);
2107
2108         disable_irq_wake(gpio_to_irq(plat->cd_gpio));
2109
2110         if (tegra_host->vdd_slot_reg) {
2111                 regulator_disable(tegra_host->vdd_slot_reg);
2112                 regulator_put(tegra_host->vdd_slot_reg);
2113         }
2114
2115         if (tegra_host->vdd_io_reg) {
2116                 regulator_disable(tegra_host->vdd_io_reg);
2117                 regulator_put(tegra_host->vdd_io_reg);
2118         }
2119
2120         if (gpio_is_valid(plat->wp_gpio))
2121                 gpio_free(plat->wp_gpio);
2122
2123         if (gpio_is_valid(plat->cd_gpio)) {
2124                 free_irq(gpio_to_irq(plat->cd_gpio), host);
2125                 gpio_free(plat->cd_gpio);
2126         }
2127
2128         if (gpio_is_valid(plat->power_gpio))
2129                 gpio_free(plat->power_gpio);
2130
2131         if (tegra_host->clk_enabled) {
2132                 clk_disable_unprepare(pltfm_host->clk);
2133                 pm_runtime_put_sync(&pdev->dev);
2134         }
2135         clk_put(pltfm_host->clk);
2136
2137         sdhci_pltfm_free(pdev);
2138
2139         return 0;
2140 }
2141
2142 static struct platform_driver sdhci_tegra_driver = {
2143         .driver         = {
2144                 .name   = "sdhci-tegra",
2145                 .owner  = THIS_MODULE,
2146                 .of_match_table = sdhci_tegra_dt_match,
2147                 .pm     = SDHCI_PLTFM_PMOPS,
2148         },
2149         .probe          = sdhci_tegra_probe,
2150         .remove         = __devexit_p(sdhci_tegra_remove),
2151 };
2152
2153 module_platform_driver(sdhci_tegra_driver);
2154
2155 MODULE_DESCRIPTION("SDHCI driver for Tegra");
2156 MODULE_AUTHOR("Google, Inc.");
2157 MODULE_LICENSE("GPL v2");