mmc: tegra: Restore tuned tap value in resume
[linux-2.6.git] / drivers / mmc / host / sdhci-tegra.c
1 /*
2  * Copyright (C) 2010 Google, Inc.
3  *
4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/err.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/gpio.h>
27 #include <linux/slab.h>
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/host.h>
30 #include <linux/module.h>
31 #include <linux/mmc/sd.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/delay.h>
34 #include <linux/pm_runtime.h>
35 #include <asm/gpio.h>
36 #include <linux/debugfs.h>
37 #include <linux/seq_file.h>
38
39 #include <mach/gpio-tegra.h>
40 #include <mach/sdhci.h>
41 #include <mach/io_dpd.h>
42 #include <mach/pinmux.h>
43
44 #include "sdhci-pltfm.h"
45
46 #define SDHCI_VENDOR_CLOCK_CNTRL        0x100
47 #define SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK      0x1
48 #define SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE 0x8
49 #define SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE        0x4
50 #define SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT    8
51 #define SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT        16
52 #define SDHCI_VENDOR_CLOCK_CNTRL_TRIM_VALUE_SHIFT       24
53 #define SDHCI_VENDOR_CLOCK_CNTRL_SDR50_TUNING           0x20
54
55 #define SDHCI_VENDOR_MISC_CNTRL         0x120
56 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT   0x8
57 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT    0x10
58 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_DDR50_SUPPORT    0x200
59 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SD_3_0   0x20
60 #define SDHCI_VENDOR_MISC_CNTRL_INFINITE_ERASE_TIMEOUT  0x1
61
62 #define SDMMC_SDMEMCOMPPADCTRL  0x1E0
63 #define SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK    0xF
64
65 #define SDMMC_AUTO_CAL_CONFIG   0x1E4
66 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START    0x80000000
67 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE   0x20000000
68 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT  0x8
69 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET        0x70
70 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET        0x62
71
72 #define SDMMC_AUTO_CAL_STATUS   0x1EC
73 #define SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE   0x80000000
74 #define SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET   24
75 #define PULLUP_ADJUSTMENT_OFFSET        20
76
77 #define SDHOST_1V8_OCR_MASK     0x8
78 #define SDHOST_HIGH_VOLT_MIN    2700000
79 #define SDHOST_HIGH_VOLT_MAX    3600000
80 #define SDHOST_HIGH_VOLT_2V8    2800000
81 #define SDHOST_LOW_VOLT_MIN     1800000
82 #define SDHOST_LOW_VOLT_MAX     1800000
83
84 #define TEGRA_SDHOST_MIN_FREQ   50000000
85 #define TEGRA2_SDHOST_STD_FREQ  50000000
86 #define TEGRA3_SDHOST_STD_FREQ  104000000
87
88 #define MAX_DIVISOR_VALUE       128
89
90 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8       128
91 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4       64
92 #define MAX_TAP_VALUES  255
93 #define TUNING_FREQ_COUNT       2
94 #define TUNING_VOLTAGES_COUNT   2
95
96 static unsigned int uhs_max_freq_MHz[] = {
97         [MMC_TIMING_UHS_SDR50] = 100,
98         [MMC_TIMING_UHS_SDR104] = 208,
99         [MMC_TIMING_MMC_HS200] = 200,
100 };
101
102 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
103 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock);
104 static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci);
105 #endif
106
107 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
108 static void tegra11x_sdhci_post_reset_init(struct sdhci_host *sdhci);
109 #endif
110
111 static unsigned int tegra_sdhost_min_freq;
112 static unsigned int tegra_sdhost_std_freq;
113
114 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
115 static unsigned int tegra3_sdhost_max_clk[4] = {
116         208000000,      104000000,      208000000,      104000000 };
117 #endif
118
119 struct tegra_sdhci_hw_ops{
120         /* Set the internal clk and card clk.*/
121         void    (*set_card_clock)(struct sdhci_host *sdhci, unsigned int clock);
122         /* Post reset vendor registers configuration */
123         void    (*sdhost_init)(struct sdhci_host *sdhci);
124 };
125
126 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
127 static struct tegra_sdhci_hw_ops tegra_2x_sdhci_ops = {
128 };
129 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
130 static struct tegra_sdhci_hw_ops tegra_3x_sdhci_ops = {
131         .set_card_clock = tegra_3x_sdhci_set_card_clock,
132         .sdhost_init = tegra3_sdhci_post_reset_init,
133 };
134 #else
135 static struct tegra_sdhci_hw_ops tegra_11x_sdhci_ops = {
136         .sdhost_init = tegra11x_sdhci_post_reset_init,
137 };
138 #endif
139
140 #define NVQUIRK_FORCE_SDHCI_SPEC_200            BIT(0)
141 #define NVQUIRK_ENABLE_BLOCK_GAP_DET            BIT(1)
142 #define NVQUIRK_DISABLE_AUTO_CALIBRATION        BIT(2)
143 #define NVQUIRK_SET_CALIBRATION_OFFSETS BIT(3)
144 #define NVQUIRK_SET_DRIVE_STRENGTH              BIT(4)
145
146 struct sdhci_tegra_soc_data {
147         struct sdhci_pltfm_data *pdata;
148         u32 nvquirks;
149 };
150
151 struct sdhci_tegra_sd_stats {
152         unsigned int data_crc_count;
153         unsigned int cmd_crc_count;
154         unsigned int data_to_count;
155         unsigned int cmd_to_count;
156 };
157
158 enum tegra_tuning_freq {
159         TUNING_LOW_FREQ,
160         TUNING_HIGH_FREQ,
161 };
162
163 struct freq_tuning_params {
164         unsigned int    freq_hz;
165         unsigned int    nr_voltages;
166         unsigned int    voltages[TUNING_VOLTAGES_COUNT];
167 };
168
169 static struct freq_tuning_params tuning_params[TUNING_FREQ_COUNT] = {
170         [TUNING_LOW_FREQ] = {
171                 .freq_hz = 82000000,
172                 .nr_voltages = 1,
173                 .voltages = {ULONG_MAX},
174         },
175         [TUNING_HIGH_FREQ] = {
176                 .freq_hz = 156000000,
177                 .nr_voltages = 2,
178                 .voltages = {ULONG_MAX, 1100000},
179         },
180 };
181
182 struct tap_window_data {
183         unsigned int    partial_win;
184         unsigned int    full_win_begin;
185         unsigned int    full_win_end;
186         unsigned int    tuning_ui;
187         unsigned int    sampling_point;
188         bool            abandon_partial_win;
189         bool            abandon_full_win;
190 };
191
192 struct tegra_tuning_data {
193         unsigned int            best_tap_value;
194         bool                    select_partial_win;
195         struct tap_window_data  *tap_data[TUNING_VOLTAGES_COUNT];
196 };
197
198 struct sdhci_tegra {
199         const struct tegra_sdhci_platform_data *plat;
200         const struct sdhci_tegra_soc_data *soc_data;
201         bool    clk_enabled;
202         struct regulator *vdd_io_reg;
203         struct regulator *vdd_slot_reg;
204         struct regulator *vcore_reg;
205         /* Pointer to the chip specific HW ops */
206         struct tegra_sdhci_hw_ops *hw_ops;
207         /* Host controller instance */
208         unsigned int instance;
209         /* vddio_min */
210         unsigned int vddio_min_uv;
211         /* vddio_max */
212         unsigned int vddio_max_uv;
213         /* max clk supported by the platform */
214         unsigned int max_clk_limit;
215         /* max ddr clk supported by the platform */
216         unsigned int ddr_clk_limit;
217         /* SD Hot Plug in Suspend State */
218         unsigned int sd_detect_in_suspend;
219         struct tegra_io_dpd *dpd;
220         bool card_present;
221         bool is_rail_enabled;
222         struct clk *emc_clk;
223         unsigned int emc_max_clk;
224         struct sdhci_tegra_sd_stats *sd_stat_head;
225         unsigned int nominal_vcore_uV;
226         /* Tuning related structures and variables */
227         /* Tuning opcode to be used */
228         unsigned int tuning_opcode;
229         /* Tuning packet size */
230         unsigned int tuning_bsize;
231         /* Tuning status */
232         unsigned int tuning_status;
233 #define TUNING_STATUS_DONE      1
234 #define TUNING_STATUS_RETUNE    2
235         /* Freq tuning information for each sampling clock freq */
236         struct tegra_tuning_data tuning_data;
237         bool is_parent_pllc;
238 };
239
240 static struct clk *pll_c;
241 static struct clk *pll_p;
242 static unsigned long pll_c_rate;
243 static unsigned long pll_p_rate;
244
245 static int show_error_stats_dump(struct seq_file *s, void *data)
246 {
247         struct sdhci_host *host = s->private;
248         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
249         struct sdhci_tegra *tegra_host = pltfm_host->priv;
250         struct sdhci_tegra_sd_stats *head;
251
252         seq_printf(s, "ErrorStatistics:\n");
253         seq_printf(s, "DataCRC\tCmdCRC\tDataTimeout\tCmdTimeout\n");
254         head = tegra_host->sd_stat_head;
255         if (head != NULL)
256                 seq_printf(s, "%d\t%d\t%d\t%d\n", head->data_crc_count,
257                         head->cmd_crc_count, head->data_to_count,
258                         head->cmd_to_count);
259         return 0;
260 }
261
262 static int sdhci_error_stats_dump(struct inode *inode, struct file *file)
263 {
264         return single_open(file, show_error_stats_dump, inode->i_private);
265 }
266
267 static const struct file_operations sdhci_host_fops = {
268         .open           = sdhci_error_stats_dump,
269         .read           = seq_read,
270         .llseek         = seq_lseek,
271         .release        = single_release,
272 };
273
274 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
275 {
276 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
277         u32 val;
278
279         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
280                 /* Use wp_gpio here instead? */
281                 val = readl(host->ioaddr + reg);
282                 return val | SDHCI_WRITE_PROTECT;
283         }
284 #endif
285         return readl(host->ioaddr + reg);
286 }
287
288 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
289 {
290 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
291         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
292         struct sdhci_tegra *tegra_host = pltfm_host->priv;
293         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
294
295         if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
296                         (reg == SDHCI_HOST_VERSION))) {
297                 /* Erratum: Version register is invalid in HW. */
298                 return SDHCI_SPEC_200;
299         }
300 #endif
301         return readw(host->ioaddr + reg);
302 }
303
304 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
305 {
306 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
307         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
308         struct sdhci_tegra *tegra_host = pltfm_host->priv;
309         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
310 #endif
311
312         /* Seems like we're getting spurious timeout and crc errors, so
313          * disable signalling of them. In case of real errors software
314          * timers should take care of eventually detecting them.
315          */
316         if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
317                 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
318
319         writel(val, host->ioaddr + reg);
320
321 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
322         if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
323                         (reg == SDHCI_INT_ENABLE))) {
324                 /* Erratum: Must enable block gap interrupt detection */
325                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
326                 if (val & SDHCI_INT_CARD_INT)
327                         gap_ctrl |= 0x8;
328                 else
329                         gap_ctrl &= ~0x8;
330                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
331         }
332 #endif
333 }
334
335 static unsigned int tegra_sdhci_get_cd(struct sdhci_host *sdhci)
336 {
337         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
338         struct sdhci_tegra *tegra_host = pltfm_host->priv;
339
340         return tegra_host->card_present;
341 }
342
343 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
344 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
345 {
346         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
347         struct sdhci_tegra *tegra_host = pltfm_host->priv;
348         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
349
350         if (!gpio_is_valid(plat->wp_gpio))
351                 return -1;
352
353         return gpio_get_value(plat->wp_gpio);
354 }
355 #endif
356
357 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
358 static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci)
359 {
360         u16 misc_ctrl;
361         u32 vendor_ctrl;
362         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
363         struct sdhci_tegra *tegra_host = pltfm_host->priv;
364         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
365
366         if (tegra_host->sd_stat_head != NULL) {
367                 tegra_host->sd_stat_head->data_crc_count = 0;
368                 tegra_host->sd_stat_head->cmd_crc_count = 0;
369                 tegra_host->sd_stat_head->data_to_count = 0;
370                 tegra_host->sd_stat_head->cmd_to_count = 0;
371         }
372         /* Set the base clock frequency */
373         vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
374         vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT);
375         vendor_ctrl |= (tegra3_sdhost_max_clk[tegra_host->instance] / 1000000) <<
376                 SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT;
377         vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
378         vendor_ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE;
379
380         /* Set tap delay */
381         if (plat->tap_delay) {
382                 vendor_ctrl &= ~(0xFF <<
383                         SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
384                 vendor_ctrl |= (plat->tap_delay <<
385                         SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
386         }
387         /* Enable frequency tuning for SDR50 mode */
388         vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDR50_TUNING;
389         sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
390
391         /* Enable SDHOST v3.0 support */
392         misc_ctrl = sdhci_readw(sdhci, SDHCI_VENDOR_MISC_CNTRL);
393         misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_SD_3_0 |
394                 SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT |
395                 SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT;
396         sdhci_writew(sdhci, misc_ctrl, SDHCI_VENDOR_MISC_CNTRL);
397 }
398 #endif
399
400 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
401 static void tegra11x_sdhci_post_reset_init(struct sdhci_host *sdhci)
402 {
403         u16 misc_ctrl;
404         u32 vendor_ctrl;
405         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
406         struct sdhci_tegra *tegra_host = pltfm_host->priv;
407         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
408         struct tegra_sdhci_platform_data *plat;
409
410         if (tegra_host->sd_stat_head != NULL) {
411                 tegra_host->sd_stat_head->data_crc_count = 0;
412                 tegra_host->sd_stat_head->cmd_crc_count = 0;
413                 tegra_host->sd_stat_head->data_to_count = 0;
414                 tegra_host->sd_stat_head->cmd_to_count = 0;
415         }
416
417         plat = pdev->dev.platform_data;
418         /* Set the base clock frequency */
419         vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
420         vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT);
421         vendor_ctrl |= (tegra3_sdhost_max_clk[tegra_host->instance] / 1000000) <<
422                 SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT;
423         vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
424         vendor_ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE;
425
426         /*
427          * Set tap delay
428          * If tuning is already done and the card is powered ON across
429          * suspend, then program the tap value obtained through tuning
430          * as only the controller context is restored. In other cases, set
431          * the default tap delay value.
432          */
433         if ((tegra_host->tuning_status == TUNING_STATUS_DONE) &&
434                 (sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
435                         vendor_ctrl &= ~(0xFF <<
436                                 SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
437                         vendor_ctrl |=
438                                 (tegra_host->tuning_data.best_tap_value <<
439                                 SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
440         } else {
441                 if (plat->tap_delay) {
442                         vendor_ctrl &= ~(0xFF <<
443                                 SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
444                         vendor_ctrl |= (plat->tap_delay <<
445                                 SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
446                 }
447         }
448
449         /* Set trim delay */
450         vendor_ctrl &= ~(0x1F <<
451                 SDHCI_VENDOR_CLOCK_CNTRL_TRIM_VALUE_SHIFT);
452         vendor_ctrl |= (plat->trim_delay <<
453                 SDHCI_VENDOR_CLOCK_CNTRL_TRIM_VALUE_SHIFT);
454         sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
455
456         /* Enable SDHOST v3.0 support */
457         misc_ctrl = sdhci_readw(sdhci, SDHCI_VENDOR_MISC_CNTRL);
458         misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT |
459                 SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT;
460         /* Enable DDR mode support only for SDMMC4 */
461         if (tegra_host->instance == 3)
462                 misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_DDR50_SUPPORT;
463         misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_INFINITE_ERASE_TIMEOUT;
464         sdhci_writew(sdhci, misc_ctrl, SDHCI_VENDOR_MISC_CNTRL);
465 }
466 #endif
467
468 static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
469                 unsigned int uhs)
470 {
471         u16 clk, ctrl_2;
472         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
473
474         /* Select Bus Speed Mode for host */
475         /* For HS200 we need to set UHS_MODE_SEL to SDR104.
476          * It works as SDR 104 in SD 4-bit mode and HS200 in eMMC 8-bit mode.
477          */
478         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
479         switch (uhs) {
480         case MMC_TIMING_UHS_SDR12:
481                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
482                 break;
483         case MMC_TIMING_UHS_SDR25:
484                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
485                 break;
486         case MMC_TIMING_UHS_SDR50:
487                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
488                 break;
489         case MMC_TIMING_UHS_SDR104:
490         case MMC_TIMING_MMC_HS200:
491                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
492                 break;
493         case MMC_TIMING_UHS_DDR50:
494                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
495                 break;
496         }
497
498         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
499
500         if (uhs == MMC_TIMING_UHS_DDR50) {
501                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
502                 clk &= ~(0xFF << SDHCI_DIVIDER_SHIFT);
503                 clk |= 1 << SDHCI_DIVIDER_SHIFT;
504                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
505         }
506         return 0;
507 }
508
509 static void tegra_sdhci_reset_exit(struct sdhci_host *sdhci, u8 mask)
510 {
511         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
512         struct sdhci_tegra *tegra_host = pltfm_host->priv;
513         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
514
515         if (mask & SDHCI_RESET_ALL) {
516                 if (tegra_host->hw_ops->sdhost_init)
517                         tegra_host->hw_ops->sdhost_init(sdhci);
518
519                 /* Mask the support for any UHS modes if specified */
520                 if (plat->uhs_mask & MMC_UHS_MASK_SDR104)
521                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR104;
522
523                 if (plat->uhs_mask & MMC_UHS_MASK_DDR50)
524                         sdhci->mmc->caps &= ~MMC_CAP_UHS_DDR50;
525
526                 if (plat->uhs_mask & MMC_UHS_MASK_SDR50)
527                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR50;
528
529                 if (plat->uhs_mask & MMC_UHS_MASK_SDR25)
530                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR25;
531
532                 if (plat->uhs_mask & MMC_UHS_MASK_SDR12)
533                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR12;
534
535                 if (plat->uhs_mask & MMC_MASK_HS200)
536                         sdhci->mmc->caps2 &= ~MMC_CAP2_HS200;
537         }
538 }
539
540 static void sdhci_status_notify_cb(int card_present, void *dev_id)
541 {
542         struct sdhci_host *sdhci = (struct sdhci_host *)dev_id;
543         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
544         struct tegra_sdhci_platform_data *plat;
545         unsigned int status, oldstat;
546
547         pr_debug("%s: card_present %d\n", mmc_hostname(sdhci->mmc),
548                 card_present);
549
550         plat = pdev->dev.platform_data;
551         if (!plat->mmc_data.status) {
552                 mmc_detect_change(sdhci->mmc, 0);
553                 return;
554         }
555
556         status = plat->mmc_data.status(mmc_dev(sdhci->mmc));
557
558         oldstat = plat->mmc_data.card_present;
559         plat->mmc_data.card_present = status;
560         if (status ^ oldstat) {
561                 pr_debug("%s: Slot status change detected (%d -> %d)\n",
562                         mmc_hostname(sdhci->mmc), oldstat, status);
563                 if (status && !plat->mmc_data.built_in)
564                         mmc_detect_change(sdhci->mmc, (5 * HZ) / 2);
565                 else
566                         mmc_detect_change(sdhci->mmc, 0);
567         }
568 }
569
570 static irqreturn_t carddetect_irq(int irq, void *data)
571 {
572         struct sdhci_host *sdhost = (struct sdhci_host *)data;
573         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
574         struct sdhci_tegra *tegra_host = pltfm_host->priv;
575         struct platform_device *pdev = to_platform_device(mmc_dev(sdhost->mmc));
576         struct tegra_sdhci_platform_data *plat;
577
578         plat = pdev->dev.platform_data;
579
580         tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
581
582         if (tegra_host->card_present) {
583                 if (!tegra_host->is_rail_enabled) {
584                         if (tegra_host->vdd_slot_reg)
585                                 regulator_enable(tegra_host->vdd_slot_reg);
586                         if (tegra_host->vdd_io_reg)
587                                 regulator_enable(tegra_host->vdd_io_reg);
588                         tegra_host->is_rail_enabled = 1;
589                 }
590         } else {
591                 if (tegra_host->is_rail_enabled) {
592                         if (tegra_host->vdd_io_reg)
593                                 regulator_disable(tegra_host->vdd_io_reg);
594                         if (tegra_host->vdd_slot_reg)
595                                 regulator_disable(tegra_host->vdd_slot_reg);
596                         tegra_host->is_rail_enabled = 0;
597                 }
598                 /*
599                  * Set retune request as tuning should be done next time
600                  * a card is inserted.
601                  */
602                 tegra_host->tuning_status = TUNING_STATUS_RETUNE;
603         }
604
605         tasklet_schedule(&sdhost->card_tasklet);
606         return IRQ_HANDLED;
607 };
608
609 static int tegra_sdhci_8bit(struct sdhci_host *sdhci, int bus_width)
610 {
611         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
612         const struct tegra_sdhci_platform_data *plat;
613         u32 ctrl;
614
615         plat = pdev->dev.platform_data;
616
617         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL);
618         if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
619                 ctrl &= ~SDHCI_CTRL_4BITBUS;
620                 ctrl |= SDHCI_CTRL_8BITBUS;
621         } else {
622                 ctrl &= ~SDHCI_CTRL_8BITBUS;
623                 if (bus_width == MMC_BUS_WIDTH_4)
624                         ctrl |= SDHCI_CTRL_4BITBUS;
625                 else
626                         ctrl &= ~SDHCI_CTRL_4BITBUS;
627         }
628         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL);
629         return 0;
630 }
631
632 /*
633 * Calculation of nearest clock frequency for desired rate:
634 * Get the divisor value, div = p / d_rate
635 * 1. If it is nearer to ceil(p/d_rate) then increment the div value by 0.5 and
636 * nearest_rate, i.e. result = p / (div + 0.5) = (p << 1)/((div << 1) + 1).
637 * 2. If not, result = p / div
638 * As the nearest clk freq should be <= to desired_rate,
639 * 3. If result > desired_rate then increment the div by 0.5
640 * and do, (p << 1)/((div << 1) + 1)
641 * 4. Else return result
642 * Here, If condtions 1 & 3 are both satisfied then to keep track of div value,
643 * defined index variable.
644 */
645 static unsigned long get_nearest_clock_freq(unsigned long pll_rate,
646                 unsigned long desired_rate)
647 {
648         unsigned long result;
649         int div;
650         int index = 1;
651
652         div = pll_rate / desired_rate;
653         if (div > MAX_DIVISOR_VALUE) {
654                 div = MAX_DIVISOR_VALUE;
655                 result = pll_rate / div;
656         } else {
657                 if ((pll_rate % desired_rate) >= (desired_rate / 2))
658                         result = (pll_rate << 1) / ((div << 1) + index++);
659                 else
660                         result = pll_rate / div;
661
662                 if (desired_rate < result) {
663                         /*
664                         * Trying to get lower clock freq than desired clock,
665                         * by increasing the divisor value by 0.5
666                         */
667                         result = (pll_rate << 1) / ((div << 1) + index);
668                 }
669         }
670
671         return result;
672 }
673
674 static void tegra_sdhci_clock_set_parent(struct sdhci_host *host,
675                 unsigned long desired_rate)
676 {
677         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
678         struct sdhci_tegra *tegra_host = pltfm_host->priv;
679         struct clk *parent_clk;
680         unsigned long pll_c_freq;
681         unsigned long pll_p_freq;
682         int rc;
683
684         pll_c_freq = get_nearest_clock_freq(pll_c_rate, desired_rate);
685         pll_p_freq = get_nearest_clock_freq(pll_p_rate, desired_rate);
686
687         if (pll_c_freq > pll_p_freq) {
688                 if (!tegra_host->is_parent_pllc) {
689                         parent_clk = pll_c;
690                         tegra_host->is_parent_pllc = true;
691                 } else
692                         return;
693         } else if (tegra_host->is_parent_pllc) {
694                 parent_clk = pll_p;
695                 tegra_host->is_parent_pllc = false;
696         } else
697                 return;
698
699         rc = clk_set_parent(pltfm_host->clk, parent_clk);
700         if (rc)
701                 pr_err("%s: failed to set pll parent clock %d\n",
702                         mmc_hostname(host->mmc), rc);
703 }
704
705 static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci,
706         unsigned int clock)
707 {
708         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
709         struct sdhci_tegra *tegra_host = pltfm_host->priv;
710         unsigned int clk_rate;
711         unsigned int emc_clk;
712
713         if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
714                 /*
715                  * In ddr mode, tegra sdmmc controller clock frequency
716                  * should be double the card clock frequency.
717                  */
718                 if (tegra_host->ddr_clk_limit) {
719                         clk_rate = tegra_host->ddr_clk_limit * 2;
720                         if (tegra_host->emc_clk) {
721                                 emc_clk = clk_get_rate(tegra_host->emc_clk);
722                                 if (emc_clk == tegra_host->emc_max_clk)
723                                         clk_rate = clock * 2;
724                         }
725                 } else {
726                         clk_rate = clock * 2;
727                 }
728         } else  if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50) {
729                 /*
730                  * In SDR50 mode, run the sdmmc controller at freq greater than
731                  * 104MHz to ensure the core voltage is at 1.2V. If the core voltage
732                  * is below 1.2V, CRC errors would occur during data transfers.
733                  */
734                 clk_rate = clock * 2;
735         } else {
736                 if (clock <= tegra_sdhost_min_freq)
737                         clk_rate = tegra_sdhost_min_freq;
738                 else if (clock <= tegra_sdhost_std_freq)
739                         clk_rate = tegra_sdhost_std_freq;
740                 else
741                         clk_rate = clock;
742         }
743
744         if (tegra_host->max_clk_limit &&
745                 (clk_rate > tegra_host->max_clk_limit))
746                 clk_rate = tegra_host->max_clk_limit;
747
748         tegra_sdhci_clock_set_parent(sdhci, clk_rate);
749         clk_set_rate(pltfm_host->clk, clk_rate);
750         sdhci->max_clk = clk_get_rate(pltfm_host->clk);
751 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
752         /* FPGA supports 26MHz of clock for SDMMC. */
753         sdhci->max_clk = 26000000;
754 #endif
755 }
756 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
757 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock)
758 {
759         int div;
760         u16 clk;
761         unsigned long timeout;
762         u8 ctrl;
763
764         if (clock && clock == sdhci->clock)
765                 return;
766
767         /*
768          * Disable the card clock before disabling the internal
769          * clock to avoid abnormal clock waveforms.
770          */
771         clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
772         clk &= ~SDHCI_CLOCK_CARD_EN;
773         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
774         sdhci_writew(sdhci, 0, SDHCI_CLOCK_CONTROL);
775
776         if (clock == 0)
777                 goto out;
778         if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
779                 div = 1;
780                 goto set_clk;
781         }
782
783         if (sdhci->version >= SDHCI_SPEC_300) {
784                 /* Version 3.00 divisors must be a multiple of 2. */
785                 if (sdhci->max_clk <= clock) {
786                         div = 1;
787                 } else {
788                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
789                                 if ((sdhci->max_clk / div) <= clock)
790                                         break;
791                         }
792                 }
793         } else {
794                 /* Version 2.00 divisors must be a power of 2. */
795                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
796                         if ((sdhci->max_clk / div) <= clock)
797                                 break;
798                 }
799         }
800         div >>= 1;
801
802         /*
803          * Tegra3 sdmmc controller internal clock will not be stabilized when
804          * we use a clock divider value greater than 4. The WAR is as follows.
805          * - Enable internal clock.
806          * - Wait for 5 usec and do a dummy write.
807          * - Poll for clk stable.
808          */
809 set_clk:
810         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
811         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
812                 << SDHCI_DIVIDER_HI_SHIFT;
813         clk |= SDHCI_CLOCK_INT_EN;
814         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
815
816         /* Wait for 5 usec */
817         udelay(5);
818
819         /* Do a dummy write */
820         ctrl = sdhci_readb(sdhci, SDHCI_CAPABILITIES);
821         ctrl |= 1;
822         sdhci_writeb(sdhci, ctrl, SDHCI_CAPABILITIES);
823
824         /* Wait max 20 ms */
825         timeout = 20;
826         while (!((clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL))
827                 & SDHCI_CLOCK_INT_STABLE)) {
828                 if (timeout == 0) {
829                         dev_err(mmc_dev(sdhci->mmc), "Internal clock never stabilised\n");
830                         return;
831                 }
832                 timeout--;
833                 mdelay(1);
834         }
835
836         clk |= SDHCI_CLOCK_CARD_EN;
837         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
838 out:
839         sdhci->clock = clock;
840 }
841 #endif /*       #ifdef CONFIG_ARCH_TEGRA_3x_SOC */
842
843 static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock)
844 {
845         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
846         struct sdhci_tegra *tegra_host = pltfm_host->priv;
847         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
848         u8 ctrl;
849
850         pr_debug("%s %s %u enabled=%u\n", __func__,
851                 mmc_hostname(sdhci->mmc), clock, tegra_host->clk_enabled);
852
853         if (clock) {
854                 /* bring out sd instance from io dpd mode */
855                 if (tegra_host->dpd) {
856                         mutex_lock(&tegra_host->dpd->delay_lock);
857                         cancel_delayed_work_sync(&tegra_host->dpd->delay_dpd);
858                         tegra_io_dpd_disable(tegra_host->dpd);
859                         mutex_unlock(&tegra_host->dpd->delay_lock);
860                 }
861
862                 if (!tegra_host->clk_enabled) {
863                         pm_runtime_get_sync(&pdev->dev);
864                         clk_prepare_enable(pltfm_host->clk);
865                         ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
866                         ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
867                         sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
868                         tegra_host->clk_enabled = true;
869                 }
870                 tegra_sdhci_set_clk_rate(sdhci, clock);
871                 if (tegra_host->hw_ops->set_card_clock)
872                         tegra_host->hw_ops->set_card_clock(sdhci, clock);
873         } else if (!clock && tegra_host->clk_enabled) {
874                 if (tegra_host->hw_ops->set_card_clock)
875                         tegra_host->hw_ops->set_card_clock(sdhci, clock);
876                 ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
877                 ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
878                 sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
879                 clk_disable_unprepare(pltfm_host->clk);
880                 pm_runtime_put_sync(&pdev->dev);
881                 tegra_host->clk_enabled = false;
882                 /* io dpd enable call for sd instance */
883
884                 if (tegra_host->dpd) {
885                         mutex_lock(&tegra_host->dpd->delay_lock);
886                         if (tegra_host->dpd->need_delay_dpd) {
887                                 schedule_delayed_work(
888                                         &tegra_host->dpd->delay_dpd,
889                                         msecs_to_jiffies(100));
890                         } else {
891                                 tegra_io_dpd_enable(tegra_host->dpd);
892                         }
893                         mutex_unlock(&tegra_host->dpd->delay_lock);
894                 }
895         }
896 }
897 static void tegra_sdhci_do_calibration(struct sdhci_host *sdhci)
898 {
899         unsigned int val;
900         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
901         struct sdhci_tegra *tegra_host = pltfm_host->priv;
902         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
903         unsigned int timeout = 10;
904
905         /* No Calibration for sdmmc4 */
906         if (tegra_host->instance == 3)
907                 return;
908
909         /*
910          * Do not enable auto calibration if the platform doesn't
911          * support it.
912          */
913         if (unlikely(soc_data->nvquirks & NVQUIRK_DISABLE_AUTO_CALIBRATION))
914                 return;
915
916         val = sdhci_readl(sdhci, SDMMC_SDMEMCOMPPADCTRL);
917         val &= ~SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK;
918         val |= 0x7;
919         sdhci_writel(sdhci, val, SDMMC_SDMEMCOMPPADCTRL);
920
921         /* Enable Auto Calibration*/
922         val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
923         val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
924         val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
925         if (unlikely(soc_data->nvquirks & NVQUIRK_SET_CALIBRATION_OFFSETS)) {
926                 /* Program Auto cal PD offset(bits 8:14) */
927                 val &= ~(0x7F <<
928                         SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
929                 val |= (SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET <<
930                         SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
931                 /* Program Auto cal PU offset(bits 0:6) */
932                 val &= ~0x7F;
933                 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET;
934         }
935         sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
936
937         /* Wait until the calibration is done */
938         do {
939                 if (!(sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) &
940                         SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE))
941                         break;
942
943                 mdelay(1);
944                 timeout--;
945         } while (timeout);
946
947         if (!timeout)
948                 dev_err(mmc_dev(sdhci->mmc), "Auto calibration failed\n");
949
950         /* Disable Auto calibration */
951         val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
952         val &= ~SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
953         sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
954
955         if (unlikely(soc_data->nvquirks & NVQUIRK_SET_DRIVE_STRENGTH)) {
956                 unsigned int pulldown_code;
957                 unsigned int pullup_code;
958                 int pg;
959                 int err;
960
961                 pg = tegra_drive_get_pingroup(mmc_dev(sdhci->mmc));
962                 if (pg != -1) {
963                         /* Get the pull down codes from auto cal status reg */
964                         pulldown_code = (
965                                 sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) >>
966                                 SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET);
967                         /* Set the pull down in the pinmux reg */
968                         err = tegra_drive_pinmux_set_pull_down(pg,
969                                 pulldown_code);
970                         if (err)
971                                 dev_err(mmc_dev(sdhci->mmc),
972                                 "Failed to set pulldown codes %d err %d\n",
973                                 pulldown_code, err);
974
975                         /* Calculate the pull up codes */
976                         pullup_code = pulldown_code + PULLUP_ADJUSTMENT_OFFSET;
977                         if (pullup_code >= TEGRA_MAX_PULL)
978                                 pullup_code = TEGRA_MAX_PULL - 1;
979                         /* Set the pull up code in the pinmux reg */
980                         err = tegra_drive_pinmux_set_pull_up(pg, pullup_code);
981                         if (err)
982                                 dev_err(mmc_dev(sdhci->mmc),
983                                 "Failed to set pullup codes %d err %d\n",
984                                 pullup_code, err);
985                 }
986         }
987 }
988
989 static int tegra_sdhci_signal_voltage_switch(struct sdhci_host *sdhci,
990         unsigned int signal_voltage)
991 {
992         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
993         struct sdhci_tegra *tegra_host = pltfm_host->priv;
994         unsigned int min_uV = tegra_host->vddio_min_uv;
995         unsigned int max_uV = tegra_host->vddio_max_uv;
996         unsigned int rc = 0;
997         u16 clk, ctrl;
998
999
1000         ctrl = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
1001         if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1002                 ctrl |= SDHCI_CTRL_VDD_180;
1003                 min_uV = SDHOST_LOW_VOLT_MIN;
1004                 max_uV = SDHOST_LOW_VOLT_MAX;
1005         } else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1006                 if (ctrl & SDHCI_CTRL_VDD_180)
1007                         ctrl &= ~SDHCI_CTRL_VDD_180;
1008         }
1009
1010         /* Check if the slot can support the required voltage */
1011         if (min_uV > tegra_host->vddio_max_uv)
1012                 return 0;
1013
1014         /* Switch OFF the card clock to prevent glitches on the clock line */
1015         clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
1016         clk &= ~SDHCI_CLOCK_CARD_EN;
1017         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
1018
1019         /* Set/clear the 1.8V signalling */
1020         sdhci_writew(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1021
1022         /* Switch the I/O rail voltage */
1023         if (tegra_host->vdd_io_reg) {
1024                 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1025                         min_uV, max_uV);
1026                 if (rc) {
1027                         dev_err(mmc_dev(sdhci->mmc), "switching to 1.8V"
1028                         "failed . Switching back to 3.3V\n");
1029                         rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1030                                 SDHOST_HIGH_VOLT_MIN,
1031                                 SDHOST_HIGH_VOLT_MAX);
1032                         if (rc)
1033                                 dev_err(mmc_dev(sdhci->mmc),
1034                                 "switching to 3.3V also failed\n");
1035                 }
1036         }
1037
1038         /* Wait for 10 msec for the voltage to be switched */
1039         mdelay(10);
1040
1041         /* Enable the card clock */
1042         clk |= SDHCI_CLOCK_CARD_EN;
1043         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
1044
1045         /* Wait for 1 msec after enabling clock */
1046         mdelay(1);
1047
1048         return rc;
1049 }
1050
1051 static void tegra_sdhci_reset(struct sdhci_host *sdhci, u8 mask)
1052 {
1053         unsigned long timeout;
1054
1055         sdhci_writeb(sdhci, mask, SDHCI_SOFTWARE_RESET);
1056
1057         /* Wait max 100 ms */
1058         timeout = 100;
1059
1060         /* hw clears the bit when it's done */
1061         while (sdhci_readb(sdhci, SDHCI_SOFTWARE_RESET) & mask) {
1062                 if (timeout == 0) {
1063                         dev_err(mmc_dev(sdhci->mmc), "Reset 0x%x never"
1064                                 "completed.\n", (int)mask);
1065                         return;
1066                 }
1067                 timeout--;
1068                 mdelay(1);
1069         }
1070
1071         tegra_sdhci_reset_exit(sdhci, mask);
1072 }
1073
1074 static void sdhci_tegra_set_tap_delay(struct sdhci_host *sdhci,
1075         unsigned int tap_delay)
1076 {
1077         u32 vendor_ctrl;
1078
1079         /* Max tap delay value is 255 */
1080         BUG_ON(tap_delay > MAX_TAP_VALUES);
1081
1082         vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
1083         vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
1084         vendor_ctrl |= (tap_delay << SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
1085         sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
1086 }
1087
1088 static int sdhci_tegra_sd_error_stats(struct sdhci_host *host, u32 int_status)
1089 {
1090         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1091         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1092         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
1093         struct sdhci_tegra_sd_stats *head;
1094
1095         if (tegra_host->sd_stat_head == NULL) {
1096                 tegra_host->sd_stat_head = devm_kzalloc(&pdev->dev, sizeof(
1097                                                 struct sdhci_tegra_sd_stats),
1098                                                 GFP_KERNEL);
1099                 if (tegra_host->sd_stat_head == NULL)
1100                         return -ENOMEM;
1101         }
1102         head = tegra_host->sd_stat_head;
1103         if (int_status & SDHCI_INT_DATA_CRC)
1104                 head->data_crc_count++;
1105         if (int_status & SDHCI_INT_CRC)
1106                 head->cmd_crc_count++;
1107         if (int_status & SDHCI_INT_TIMEOUT)
1108                 head->cmd_to_count++;
1109         if (int_status & SDHCI_INT_DATA_TIMEOUT)
1110                 head->data_to_count++;
1111         return 0;
1112 }
1113
1114 /*
1115  * Calculation of best tap value for low frequencies(82MHz).
1116  * X = Partial win, Y = Full win start, Z = Full win end.
1117  * UI = Z - X.
1118  * Full Window = Z - Y.
1119  * Taps margin = mid-point of 1/2*(curr_freq/max_frequency)*UI
1120  *                    = (1/2)*(1/2)*(82/200)*UI
1121  *                    = (0.1025)*UI
1122  * if Partial win<(0.22)*UI
1123  * best tap = Y+(0.1025*UI)
1124  * else
1125  * best tap = (X-(Z-Y))+(0.1025*UI)
1126  * If best tap<0, best tap = 0
1127  */
1128 static void calculate_low_freq_tap_value(struct sdhci_host *sdhci)
1129 {
1130         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1131         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1132         unsigned int curr_clock;
1133         unsigned int max_clock;
1134         int best_tap_value;
1135         struct tap_window_data *tap_data;
1136         struct tegra_tuning_data *tuning_data;
1137
1138         tuning_data = &tegra_host->tuning_data;
1139         tap_data = tuning_data->tap_data[0];
1140
1141         if (tap_data->abandon_full_win) {
1142                 if (tap_data->abandon_partial_win) {
1143                         tuning_data->best_tap_value = 0;
1144                         return;
1145                 } else {
1146                         tuning_data->select_partial_win = true;
1147                         goto calculate_best_tap;
1148                 }
1149         }
1150
1151         tap_data->tuning_ui = tap_data->full_win_end - tap_data->partial_win;
1152
1153         /* Calculate the sampling point */
1154         curr_clock = sdhci->max_clk / 1000000;
1155         max_clock = uhs_max_freq_MHz[sdhci->mmc->ios.timing];
1156         tap_data->sampling_point = ((tap_data->tuning_ui * curr_clock) /
1157                 max_clock);
1158         tap_data->sampling_point >>= 2;
1159
1160         /*
1161          * Check whether partial window should be used. Use partial window
1162          * if partial window > 0.22(UI).
1163          */
1164         if ((!tap_data->abandon_partial_win) &&
1165                 (tap_data->partial_win > ((22 * tap_data->tuning_ui) / 100)))
1166                         tuning_data->select_partial_win = true;
1167
1168 calculate_best_tap:
1169         if (tuning_data->select_partial_win) {
1170                 best_tap_value = (tap_data->partial_win -
1171                         (tap_data->full_win_end - tap_data->full_win_begin)) +
1172                         tap_data->sampling_point;
1173                 tuning_data->best_tap_value = (best_tap_value < 0) ? 0 :
1174                         best_tap_value;
1175         } else {
1176                 tuning_data->best_tap_value = tap_data->full_win_begin +
1177                         tap_data->sampling_point;
1178         }
1179 }
1180
1181 /*
1182  * Calculation of best tap value for high frequencies(156MHz).
1183  * Tap window data at 1.25V core voltage
1184  * X = Partial win, Y = Full win start, Z = Full win end.
1185  * Full Window = Z-Y.
1186  * UI = Z-X.
1187  * Tap_margin = (0.20375)UI
1188  *
1189  * Tap window data at 1.1V core voltage
1190  * X' = Partial win, Y' = Full win start, Z' = Full win end.
1191  * UI' = Z'-X'.
1192  * Full Window' = Z'-Y'.
1193  * Tap_margin' = (0.20375)UI'
1194  *
1195  * Full_window_tap=[(Z'-0.20375UI')+(Y+0.20375UI)]/2
1196  * Partial_window_tap=[(X'-0.20375UI')+(X-(Z-Y)+0x20375UI)]/2
1197  * if(Partial_window_tap < 0), Partial_window_tap=0
1198  *
1199  * Full_window_quality=[(Z'-0.20375UI')-(Y+0.20375UI)]/2
1200  * Partial_window_quality=(X'-0.20375UI')-Partial_window_tap
1201  * if(Full_window_quality>Partial_window_quality) choose full window,
1202  * else choose partial window.
1203  * If there is no margin window for both cases,
1204  * best tap=(Y+Z')/2.
1205  */
1206 static void calculate_high_freq_tap_value(struct sdhci_host *sdhci)
1207 {
1208         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1209         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1210         unsigned int curr_clock;
1211         unsigned int max_clock;
1212         struct tap_window_data *vmax_tap_data;
1213         struct tap_window_data *vmid_tap_data;
1214         struct tegra_tuning_data *tuning_data;
1215         unsigned int full_win_tap;
1216         int partial_win_start;
1217         int partial_win_tap;
1218         int full_win_quality;
1219         int partial_win_quality;
1220
1221         tuning_data = &tegra_host->tuning_data;
1222         vmax_tap_data = tuning_data->tap_data[0];
1223         vmid_tap_data = tuning_data->tap_data[1];
1224
1225         curr_clock = sdhci->max_clk / 1000000;
1226         max_clock = uhs_max_freq_MHz[sdhci->mmc->ios.timing];
1227
1228         /*
1229          * Calculate the tuning_ui and sampling points for tap windows found
1230          * at all core voltages.
1231          */
1232         vmax_tap_data->tuning_ui = vmax_tap_data->full_win_end -
1233                 vmax_tap_data->partial_win;
1234         vmax_tap_data->sampling_point =
1235                 (vmax_tap_data->tuning_ui * curr_clock) / max_clock;
1236         vmax_tap_data->sampling_point >>= 2;
1237
1238         vmid_tap_data->tuning_ui = vmid_tap_data->full_win_end -
1239                 vmid_tap_data->partial_win;
1240         vmid_tap_data->sampling_point =
1241                 (vmid_tap_data->tuning_ui * curr_clock) / max_clock;
1242         vmid_tap_data->sampling_point >>= 2;
1243
1244         full_win_tap = ((vmid_tap_data->full_win_end -
1245                 vmid_tap_data->sampling_point) +
1246                 (vmax_tap_data->full_win_begin +
1247                 vmax_tap_data->sampling_point));
1248         full_win_tap >>= 1;
1249         full_win_quality = (vmid_tap_data->full_win_end -
1250                 vmid_tap_data->sampling_point) -
1251                 (vmax_tap_data->full_win_begin +
1252                 vmax_tap_data->sampling_point);
1253         full_win_quality >>= 1;
1254
1255         partial_win_start = (vmax_tap_data->partial_win -
1256                 (vmax_tap_data->full_win_end -
1257                 vmax_tap_data->full_win_begin));
1258         partial_win_tap = ((vmid_tap_data->partial_win -
1259                 vmid_tap_data->sampling_point) +
1260                 (partial_win_start + vmax_tap_data->sampling_point)) / 2;
1261         if (partial_win_tap < 0)
1262                 partial_win_tap = 0;
1263         partial_win_quality = (vmid_tap_data->partial_win -
1264                 vmid_tap_data->sampling_point) - partial_win_tap;
1265
1266         if ((full_win_quality <= 0) && (partial_win_quality)) {
1267                 dev_warn(mmc_dev(sdhci->mmc),
1268                         "No margin window for both windows\n");
1269                 tuning_data->best_tap_value = vmax_tap_data->full_win_begin +
1270                         vmid_tap_data->full_win_end;
1271                 tuning_data->best_tap_value >>= 1;
1272         } else {
1273                 if (full_win_quality > partial_win_quality) {
1274                         tuning_data->best_tap_value = full_win_tap;
1275                 } else {
1276                         tuning_data->best_tap_value = partial_win_tap;
1277                         tuning_data->select_partial_win = true;
1278                 }
1279         }
1280 }
1281
1282 static int sdhci_tegra_run_frequency_tuning(struct sdhci_host *sdhci)
1283 {
1284         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1285         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1286         int err = 0;
1287         u8 ctrl;
1288         u32 mask;
1289         unsigned int timeout = 10;
1290         int flags;
1291         u32 intstatus;
1292
1293         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
1294         while (sdhci_readl(sdhci, SDHCI_PRESENT_STATE) & mask) {
1295                 if (timeout == 0) {
1296                         dev_err(mmc_dev(sdhci->mmc), "Controller never"
1297                                 "released inhibit bit(s).\n");
1298                         err = -ETIMEDOUT;
1299                         goto out;
1300                 }
1301                 timeout--;
1302                 mdelay(1);
1303         }
1304
1305         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1306         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1307         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1308
1309         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1310         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1311         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1312
1313         /*
1314          * In response to CMD19, the card sends 64 bytes of tuning
1315          * block to the Host Controller. So we set the block size
1316          * to 64 here.
1317          * In response to CMD21, the card sends 128 bytes of tuning
1318          * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
1319          * to the Host Controller. So we set the block size to 64 here.
1320          */
1321         sdhci_writew(sdhci, SDHCI_MAKE_BLKSZ(7, tegra_host->tuning_bsize),
1322                 SDHCI_BLOCK_SIZE);
1323
1324         sdhci_writeb(sdhci, 0xE, SDHCI_TIMEOUT_CONTROL);
1325
1326         sdhci_writeb(sdhci, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1327
1328         sdhci_writel(sdhci, 0x0, SDHCI_ARGUMENT);
1329
1330         /* Set the cmd flags */
1331         flags = SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_DATA;
1332         /* Issue the command */
1333         sdhci_writew(sdhci, SDHCI_MAKE_CMD(
1334                 tegra_host->tuning_opcode, flags), SDHCI_COMMAND);
1335
1336         timeout = 5;
1337         do {
1338                 timeout--;
1339                 mdelay(1);
1340                 intstatus = sdhci_readl(sdhci, SDHCI_INT_STATUS);
1341                 if (intstatus) {
1342                         sdhci_writel(sdhci, intstatus, SDHCI_INT_STATUS);
1343                         break;
1344                 }
1345         } while(timeout);
1346
1347         if ((intstatus & SDHCI_INT_DATA_AVAIL) &&
1348                 !(intstatus & SDHCI_INT_DATA_CRC)) {
1349                 err = 0;
1350                 sdhci->tuning_done = 1;
1351         } else {
1352                 tegra_sdhci_reset(sdhci, SDHCI_RESET_CMD);
1353                 tegra_sdhci_reset(sdhci, SDHCI_RESET_DATA);
1354                 err = -EIO;
1355         }
1356
1357         if (sdhci->tuning_done) {
1358                 sdhci->tuning_done = 0;
1359                 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1360                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING) &&
1361                         (ctrl & SDHCI_CTRL_TUNED_CLK))
1362                         err = 0;
1363                 else
1364                         err = -EIO;
1365         }
1366         mdelay(1);
1367 out:
1368         return err;
1369 }
1370
1371 static int sdhci_tegra_scan_tap_values(struct sdhci_host *sdhci,
1372         unsigned int starting_tap, bool expect_failure)
1373 {
1374         unsigned int tap_value = starting_tap;
1375         int err;
1376
1377         do {
1378                 /* Set the tap delay */
1379                 sdhci_tegra_set_tap_delay(sdhci, tap_value);
1380
1381                 /* Run frequency tuning */
1382                 err = sdhci_tegra_run_frequency_tuning(sdhci);
1383                 if ((expect_failure && !err) ||
1384                         (!expect_failure && err))
1385                         break;
1386                 tap_value++;
1387         } while (tap_value <= MAX_TAP_VALUES);
1388
1389         return tap_value;
1390 }
1391
1392 /*
1393  * While scanning for tap values, first get the partial window followed by the
1394  * full window. Note that, when scanning for full win start, tuning has to be
1395  * run until a passing tap value is found. Hence, failure is expected during
1396  * this process and ignored.
1397  */
1398 static int sdhci_tegra_get_tap_window_data(struct sdhci_host *sdhci,
1399         struct tap_window_data *tap_data)
1400 {
1401         unsigned int tap_value;
1402         int err = 0;
1403
1404         if (!tap_data) {
1405                 dev_err(mmc_dev(sdhci->mmc), "Invalid tap data\n");
1406                 return -ENODATA;
1407         }
1408
1409         /* Get the partial window data */
1410         tap_value = 0;
1411         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, false);
1412         if (!tap_value) {
1413                 tap_data->abandon_partial_win = true;
1414                 tap_data->partial_win = 0;
1415         } else if (tap_value > MAX_TAP_VALUES) {
1416                 /*
1417                  * If tap value is more than 0xFF, we have hit the miracle case
1418                  * of all tap values passing. Discard full window as passing
1419                  * window has covered all taps.
1420                  */
1421                 tap_data->partial_win = MAX_TAP_VALUES;
1422                 tap_data->abandon_full_win = true;
1423                 goto out;
1424         } else {
1425                 tap_data->partial_win = tap_value - 1;
1426                 if (tap_value == MAX_TAP_VALUES) {
1427                         /* All tap values exhausted. No full window */
1428                         tap_data->abandon_full_win = true;
1429                         goto out;
1430                 }
1431         }
1432
1433         /* Get the full window start */
1434         tap_value++;
1435         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, true);
1436         if (tap_value > MAX_TAP_VALUES) {
1437                 /* All tap values exhausted. No full window */
1438                 tap_data->abandon_full_win = true;
1439                 goto out;
1440         } else {
1441                 tap_data->full_win_begin = tap_value;
1442                 /*
1443                  * If full win start is 0xFF, then set that as full win end
1444                  * and exit.
1445                  */
1446                 if (tap_value == MAX_TAP_VALUES) {
1447                         tap_data->full_win_end = tap_value;
1448                         goto out;
1449                 }
1450         }
1451
1452         /* Get the full window end */
1453         tap_value++;
1454         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, false);
1455         tap_data->full_win_end = tap_value - 1;
1456         if (tap_value > MAX_TAP_VALUES)
1457                 tap_data->full_win_end = MAX_TAP_VALUES;
1458 out:
1459         /*
1460          * Mark tuning as failed if both partial and full windows are
1461          * abandoned.
1462          */
1463         if (tap_data->abandon_partial_win && tap_data->abandon_full_win)
1464                 err = -EIO;
1465         return err;
1466 }
1467
1468 static int sdhci_tegra_execute_tuning(struct sdhci_host *sdhci, u32 opcode)
1469 {
1470         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1471         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1472         struct tegra_tuning_data *tuning_data;
1473         struct tap_window_data *tap_data;
1474         int err;
1475         u16 ctrl_2;
1476         u32 ier;
1477         unsigned int freq_band;
1478         unsigned int i;
1479         unsigned int voltage;
1480
1481         /* Tuning is valid only in SDR104 and SDR50 modes */
1482         ctrl_2 = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
1483         if (!(((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1484                 (((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1485                 (sdhci->flags & SDHCI_SDR50_NEEDS_TUNING))))
1486                         return 0;
1487
1488         /* Tuning should be done only for MMC_BUS_WIDTH_8 and MMC_BUS_WIDTH_4 */
1489         if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1490                 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8;
1491         else if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1492                 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4;
1493         else
1494                 return -EINVAL;
1495
1496         /* Set the tuning command to be used */
1497         tegra_host->tuning_opcode = opcode;
1498
1499         /*
1500          * Disable all interrupts signalling.Enable interrupt status
1501          * detection for buffer read ready and data crc. We use
1502          * polling for tuning as it involves less overhead.
1503          */
1504         ier = sdhci_readl(sdhci, SDHCI_INT_ENABLE);
1505         sdhci_writel(sdhci, 0, SDHCI_SIGNAL_ENABLE);
1506         sdhci_writel(sdhci, SDHCI_INT_DATA_AVAIL |
1507                 SDHCI_INT_DATA_CRC, SDHCI_INT_ENABLE);
1508
1509         /*
1510          * If tuning is already done and retune request is not set, then skip
1511          * best tap value calculation and use the old best tap value.
1512          */
1513         if (tegra_host->tuning_status == TUNING_STATUS_DONE)
1514                 goto set_best_tap;
1515
1516         if (sdhci->max_clk > tuning_params[TUNING_LOW_FREQ].freq_hz)
1517                 freq_band = TUNING_HIGH_FREQ;
1518         else
1519                 freq_band = TUNING_LOW_FREQ;
1520
1521         /*
1522          * Run tuning and get the passing tap window info for all frequencies
1523          * and core voltages required to calculate the final tap value. The
1524          * standard driver calls this platform specific tuning callback after
1525          * holding a lock. The spinlock needs to be released when calling
1526          * non-atomic context functions like regulator calls etc.
1527          */
1528         tuning_data = &tegra_host->tuning_data;
1529         for (i = 0; i < tuning_params[freq_band].nr_voltages; i++) {
1530                 spin_unlock(&sdhci->lock);
1531                 if (!tuning_data->tap_data[i]) {
1532                         tuning_data->tap_data[i] = devm_kzalloc(
1533                                 mmc_dev(sdhci->mmc),
1534                                 sizeof(struct tap_window_data), GFP_KERNEL);
1535                         if (!tuning_data->tap_data[i]) {
1536                                 err = -ENOMEM;
1537                                 dev_err(mmc_dev(sdhci->mmc),
1538                                         "Insufficient memory for tap window info\n");
1539                                 spin_lock(&sdhci->lock);
1540                                 goto out;
1541                         }
1542                 }
1543                 tap_data = tuning_data->tap_data[i];
1544
1545                 if (tegra_host->nominal_vcore_uV) {
1546                         if (!tegra_host->vcore_reg)
1547                                 tegra_host->vcore_reg = regulator_get(
1548                                 mmc_dev(sdhci->mmc), "vdd_core");
1549                         if (IS_ERR_OR_NULL(tegra_host->vcore_reg)) {
1550                                 dev_info(mmc_dev(sdhci->mmc),
1551                                         "No vdd_core %ld. Tuning might fail.\n",
1552                                         PTR_ERR(tegra_host->vcore_reg));
1553                                 tegra_host->vcore_reg = NULL;
1554                         } else {
1555                                 voltage = tuning_params[freq_band].voltages[i];
1556                                 if (voltage > tegra_host->nominal_vcore_uV)
1557                                         voltage = tegra_host->nominal_vcore_uV;
1558                                 err = regulator_set_voltage(
1559                                         tegra_host->vcore_reg, voltage,
1560                                         voltage);
1561                                 if (err)
1562                                         dev_err(mmc_dev(sdhci->mmc),
1563                                                 "Setting nominal core voltage failed\n");
1564                         }
1565                 }
1566                 spin_lock(&sdhci->lock);
1567
1568                 /* Get the tuning window info */
1569                 err = sdhci_tegra_get_tap_window_data(sdhci, tap_data);
1570                 if (err) {
1571                         dev_err(mmc_dev(sdhci->mmc), "Failed to tuning window info\n");
1572                         goto out;
1573                 }
1574         }
1575
1576         /* Calculate best tap for current freq band */
1577         if (freq_band == TUNING_LOW_FREQ)
1578                 calculate_low_freq_tap_value(sdhci);
1579         else
1580                 calculate_high_freq_tap_value(sdhci);
1581
1582 set_best_tap:
1583         sdhci_tegra_set_tap_delay(sdhci,
1584                 tegra_host->tuning_data.best_tap_value);
1585
1586         /*
1587          * Run tuning with the best tap value. If tuning fails, set the status
1588          * for retuning next time enumeration is done.
1589          */
1590         err = sdhci_tegra_run_frequency_tuning(sdhci);
1591         if (err)
1592                 tegra_host->tuning_status = TUNING_STATUS_RETUNE;
1593         else
1594                 tegra_host->tuning_status = TUNING_STATUS_DONE;
1595
1596 out:
1597         /* Enable the full range for core voltage if vcore_reg exists */
1598         if (tegra_host->vcore_reg) {
1599                 spin_unlock(&sdhci->lock);
1600                 regulator_put(tegra_host->vcore_reg);
1601                 tegra_host->vcore_reg = NULL;
1602                 spin_lock(&sdhci->lock);
1603         }
1604
1605         /* Enable interrupts. Enable full range for core voltage */
1606         sdhci_writel(sdhci, ier, SDHCI_INT_ENABLE);
1607         sdhci_writel(sdhci, ier, SDHCI_SIGNAL_ENABLE);
1608         return err;
1609 }
1610
1611 static int tegra_sdhci_suspend(struct sdhci_host *sdhci)
1612 {
1613         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1614         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1615
1616         tegra_sdhci_set_clock(sdhci, 0);
1617
1618         /* Disable the power rails if any */
1619         if (tegra_host->card_present) {
1620                 if (tegra_host->is_rail_enabled) {
1621                         if (tegra_host->vdd_io_reg)
1622                                 regulator_disable(tegra_host->vdd_io_reg);
1623                         if (tegra_host->vdd_slot_reg)
1624                                 regulator_disable(tegra_host->vdd_slot_reg);
1625                         tegra_host->is_rail_enabled = 0;
1626                 }
1627         }
1628
1629         if (tegra_host->dpd) {
1630                 mutex_lock(&tegra_host->dpd->delay_lock);
1631                 tegra_host->dpd->need_delay_dpd = 1;
1632                 mutex_unlock(&tegra_host->dpd->delay_lock);
1633         }
1634
1635         return 0;
1636 }
1637
1638 static int tegra_sdhci_resume(struct sdhci_host *sdhci)
1639 {
1640         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1641         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1642         struct platform_device *pdev;
1643         struct tegra_sdhci_platform_data *plat;
1644
1645         pdev = to_platform_device(mmc_dev(sdhci->mmc));
1646         plat = pdev->dev.platform_data;
1647
1648         if (gpio_is_valid(plat->cd_gpio))
1649                 tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
1650
1651         /* Enable the power rails if any */
1652         if (tegra_host->card_present) {
1653                 if (!tegra_host->is_rail_enabled) {
1654                         if (tegra_host->vdd_slot_reg)
1655                                 regulator_enable(tegra_host->vdd_slot_reg);
1656                         if (tegra_host->vdd_io_reg) {
1657                                 regulator_enable(tegra_host->vdd_io_reg);
1658                                 if (plat->mmc_data.ocr_mask &
1659                                                         SDHOST_1V8_OCR_MASK)
1660                                         tegra_sdhci_signal_voltage_switch(sdhci,
1661                                                         MMC_SIGNAL_VOLTAGE_180);
1662                                 else
1663                                         tegra_sdhci_signal_voltage_switch(sdhci,
1664                                                         MMC_SIGNAL_VOLTAGE_330);
1665                         }
1666                         tegra_host->is_rail_enabled = 1;
1667                 }
1668         }
1669
1670         /* Setting the min identification clock of freq 400KHz */
1671         tegra_sdhci_set_clock(sdhci, 400000);
1672
1673         /* Reset the controller and power on if MMC_KEEP_POWER flag is set*/
1674         if (sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER) {
1675                 tegra_sdhci_reset(sdhci, SDHCI_RESET_ALL);
1676                 sdhci_writeb(sdhci, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1677                 sdhci->pwr = 0;
1678         }
1679
1680         return 0;
1681 }
1682
1683 static void tegra_sdhci_post_resume(struct sdhci_host *sdhci)
1684 {
1685         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1686         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1687
1688         if (tegra_host->card_present) {
1689                 if (tegra_host->sd_detect_in_suspend)
1690                         tasklet_schedule(&sdhci->card_tasklet);
1691         } else if (tegra_host->clk_enabled) {
1692                 /* Turn OFF the clocks if the card is not present */
1693                 tegra_sdhci_set_clock(sdhci, 0);
1694         }
1695 }
1696
1697 static void sdhci_tegra_error_stats_debugfs(struct sdhci_host *host)
1698 {
1699         struct dentry *root;
1700
1701         root = debugfs_create_dir(dev_name(mmc_dev(host->mmc)), NULL);
1702         if (IS_ERR(root))
1703                 /* Don't complain -- debugfs just isn't enabled */
1704                 return;
1705         if (!root)
1706                 /* Complain -- debugfs is enabled, but it failed to
1707                  * create the directory. */
1708                 goto err_root;
1709
1710         host->debugfs_root = root;
1711
1712         if (!debugfs_create_file("error_stats", S_IRUSR, root, host,
1713                                 &sdhci_host_fops))
1714                 goto err_node;
1715         return;
1716
1717 err_node:
1718         debugfs_remove_recursive(root);
1719         host->debugfs_root = NULL;
1720 err_root:
1721         pr_err("%s: Failed to initialize debugfs functionality\n", __func__);
1722         return;
1723 }
1724
1725 static struct sdhci_ops tegra_sdhci_ops = {
1726 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
1727         .get_ro     = tegra_sdhci_get_ro,
1728 #endif
1729         .get_cd     = tegra_sdhci_get_cd,
1730         .read_l     = tegra_sdhci_readl,
1731         .read_w     = tegra_sdhci_readw,
1732         .write_l    = tegra_sdhci_writel,
1733         .platform_8bit_width = tegra_sdhci_8bit,
1734         .set_clock              = tegra_sdhci_set_clock,
1735         .suspend                = tegra_sdhci_suspend,
1736         .resume                 = tegra_sdhci_resume,
1737         .platform_resume        = tegra_sdhci_post_resume,
1738         .platform_reset_exit    = tegra_sdhci_reset_exit,
1739         .set_uhs_signaling      = tegra_sdhci_set_uhs_signaling,
1740         .switch_signal_voltage  = tegra_sdhci_signal_voltage_switch,
1741         .switch_signal_voltage_exit = tegra_sdhci_do_calibration,
1742         .execute_freq_tuning    = sdhci_tegra_execute_tuning,
1743         .sd_error_stats         = sdhci_tegra_sd_error_stats,
1744 };
1745
1746 static struct sdhci_pltfm_data sdhci_tegra20_pdata = {
1747         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1748 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1749                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1750                   SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING |
1751                   SDHCI_QUIRK_NON_STANDARD_TUNING |
1752 #endif
1753 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1754                   SDHCI_QUIRK_NONSTANDARD_CLOCK |
1755 #endif
1756                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1757                   SDHCI_QUIRK_NO_HISPD_BIT |
1758                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1759                   SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1760                   SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO,
1761         .quirks2 = SDHCI_QUIRK2_BROKEN_PRESET_VALUES,
1762         .ops  = &tegra_sdhci_ops,
1763 };
1764
1765 static struct sdhci_tegra_soc_data soc_data_tegra20 = {
1766         .pdata = &sdhci_tegra20_pdata,
1767         .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1768 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
1769                     NVQUIRK_SET_DRIVE_STRENGTH |
1770 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
1771                     NVQUIRK_DISABLE_AUTO_CALIBRATION |
1772 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
1773                     NVQUIRK_SET_CALIBRATION_OFFSETS |
1774 #endif
1775                     NVQUIRK_ENABLE_BLOCK_GAP_DET,
1776 };
1777
1778 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1779 static struct sdhci_pltfm_data sdhci_tegra30_pdata = {
1780         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1781                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1782                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1783                   SDHCI_QUIRK_NO_HISPD_BIT |
1784                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
1785         .ops  = &tegra_sdhci_ops,
1786 };
1787
1788 static struct sdhci_tegra_soc_data soc_data_tegra30 = {
1789         .pdata = &sdhci_tegra30_pdata,
1790 };
1791 #endif
1792
1793 static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = {
1794 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1795         { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1796 #endif
1797 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1798         { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1799 #endif
1800         {}
1801 };
1802 MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
1803
1804 static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata(
1805                                                 struct platform_device *pdev)
1806 {
1807         struct tegra_sdhci_platform_data *plat;
1808         struct device_node *np = pdev->dev.of_node;
1809
1810         if (!np)
1811                 return NULL;
1812
1813         plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1814         if (!plat) {
1815                 dev_err(&pdev->dev, "Can't allocate platform data\n");
1816                 return NULL;
1817         }
1818
1819         plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1820         plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1821         plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
1822         if (of_find_property(np, "support-8bit", NULL))
1823                 plat->is_8bit = 1;
1824
1825         return plat;
1826 }
1827
1828 static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
1829 {
1830         const struct of_device_id *match;
1831         const struct sdhci_tegra_soc_data *soc_data;
1832         struct sdhci_host *host;
1833         struct sdhci_pltfm_host *pltfm_host;
1834         struct tegra_sdhci_platform_data *plat;
1835         struct sdhci_tegra *tegra_host;
1836         int rc;
1837
1838         match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
1839         if (match)
1840                 soc_data = match->data;
1841         else
1842                 soc_data = &soc_data_tegra20;
1843
1844         host = sdhci_pltfm_init(pdev, soc_data->pdata);
1845         if (IS_ERR(host))
1846                 return PTR_ERR(host);
1847
1848         pltfm_host = sdhci_priv(host);
1849
1850         plat = pdev->dev.platform_data;
1851
1852         if (plat == NULL)
1853                 plat = sdhci_tegra_dt_parse_pdata(pdev);
1854
1855         if (plat == NULL) {
1856                 dev_err(mmc_dev(host->mmc), "missing platform data\n");
1857                 rc = -ENXIO;
1858                 goto err_no_plat;
1859         }
1860
1861         tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
1862         if (!tegra_host) {
1863                 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
1864                 rc = -ENOMEM;
1865                 goto err_no_plat;
1866         }
1867
1868         tegra_host->plat = plat;
1869         tegra_host->sd_stat_head = NULL;
1870         tegra_host->soc_data = soc_data;
1871
1872         pltfm_host->priv = tegra_host;
1873
1874         pll_c = clk_get_sys(NULL, "pll_c");
1875         if (IS_ERR(pll_c)) {
1876                 rc = PTR_ERR(pll_c);
1877                 dev_err(mmc_dev(host->mmc),
1878                         "clk error in getting pll_c: %d\n", rc);
1879         }
1880
1881         pll_p = clk_get_sys(NULL, "pll_p");
1882         if (IS_ERR(pll_p)) {
1883                 rc = PTR_ERR(pll_p);
1884                 dev_err(mmc_dev(host->mmc),
1885                         "clk error in getting pll_p: %d\n", rc);
1886         }
1887
1888         pll_c_rate = clk_get_rate(pll_c);
1889         pll_p_rate = clk_get_rate(pll_p);
1890
1891 #ifdef CONFIG_MMC_EMBEDDED_SDIO
1892         if (plat->mmc_data.embedded_sdio)
1893                 mmc_set_embedded_sdio_data(host->mmc,
1894                         &plat->mmc_data.embedded_sdio->cis,
1895                         &plat->mmc_data.embedded_sdio->cccr,
1896                         plat->mmc_data.embedded_sdio->funcs,
1897                         plat->mmc_data.embedded_sdio->num_funcs);
1898 #endif
1899
1900         if (gpio_is_valid(plat->power_gpio)) {
1901                 rc = gpio_request(plat->power_gpio, "sdhci_power");
1902                 if (rc) {
1903                         dev_err(mmc_dev(host->mmc),
1904                                 "failed to allocate power gpio\n");
1905                         goto err_power_req;
1906                 }
1907                 gpio_direction_output(plat->power_gpio, 1);
1908         }
1909
1910         if (gpio_is_valid(plat->cd_gpio)) {
1911                 rc = gpio_request(plat->cd_gpio, "sdhci_cd");
1912                 if (rc) {
1913                         dev_err(mmc_dev(host->mmc),
1914                                 "failed to allocate cd gpio\n");
1915                         goto err_cd_req;
1916                 }
1917                 gpio_direction_input(plat->cd_gpio);
1918
1919                 tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
1920
1921                 rc = request_threaded_irq(gpio_to_irq(plat->cd_gpio), NULL,
1922                                  carddetect_irq,
1923                                  IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1924                                  mmc_hostname(host->mmc), host);
1925
1926                 if (rc) {
1927                         dev_err(mmc_dev(host->mmc), "request irq error\n");
1928                         goto err_cd_irq_req;
1929                 }
1930                 rc = enable_irq_wake(gpio_to_irq(plat->cd_gpio));
1931                 if (rc < 0)
1932                         dev_err(mmc_dev(host->mmc),
1933                                 "SD card wake-up event registration"
1934                                         "failed with eroor: %d\n", rc);
1935
1936         } else if (plat->mmc_data.register_status_notify) {
1937                 plat->mmc_data.register_status_notify(sdhci_status_notify_cb, host);
1938         }
1939
1940         if (plat->mmc_data.status) {
1941                 plat->mmc_data.card_present = plat->mmc_data.status(mmc_dev(host->mmc));
1942         }
1943
1944         if (gpio_is_valid(plat->wp_gpio)) {
1945                 rc = gpio_request(plat->wp_gpio, "sdhci_wp");
1946                 if (rc) {
1947                         dev_err(mmc_dev(host->mmc),
1948                                 "failed to allocate wp gpio\n");
1949                         goto err_wp_req;
1950                 }
1951                 gpio_direction_input(plat->wp_gpio);
1952         }
1953
1954         /*
1955          * If there is no card detect gpio, assume that the
1956          * card is always present.
1957          */
1958         if (!gpio_is_valid(plat->cd_gpio))
1959                 tegra_host->card_present = 1;
1960
1961         if (plat->mmc_data.ocr_mask & SDHOST_1V8_OCR_MASK) {
1962                 tegra_host->vddio_min_uv = SDHOST_LOW_VOLT_MIN;
1963                 tegra_host->vddio_max_uv = SDHOST_LOW_VOLT_MAX;
1964         } else if (plat->mmc_data.ocr_mask & MMC_OCR_2V8_MASK) {
1965                         tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_2V8;
1966                         tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
1967         } else {
1968                 /*
1969                  * Set the minV and maxV to default
1970                  * voltage range of 2.7V - 3.6V
1971                  */
1972                 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_MIN;
1973                 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
1974         }
1975
1976         tegra_host->vdd_io_reg = regulator_get(mmc_dev(host->mmc),
1977                                                         "vddio_sdmmc");
1978         if (IS_ERR_OR_NULL(tegra_host->vdd_io_reg)) {
1979                 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
1980                         "Assuming vddio_sdmmc is not required.\n",
1981                         "vddio_sdmmc", PTR_ERR(tegra_host->vdd_io_reg));
1982                 tegra_host->vdd_io_reg = NULL;
1983         } else {
1984                 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1985                         tegra_host->vddio_min_uv,
1986                         tegra_host->vddio_max_uv);
1987                 if (rc) {
1988                         dev_err(mmc_dev(host->mmc), "%s regulator_set_voltage failed: %d",
1989                                 "vddio_sdmmc", rc);
1990                         regulator_put(tegra_host->vdd_io_reg);
1991                         tegra_host->vdd_io_reg = NULL;
1992                 }
1993         }
1994
1995         tegra_host->vdd_slot_reg = regulator_get(mmc_dev(host->mmc),
1996                                                         "vddio_sd_slot");
1997         if (IS_ERR_OR_NULL(tegra_host->vdd_slot_reg)) {
1998                 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
1999                         " Assuming vddio_sd_slot is not required.\n",
2000                         "vddio_sd_slot", PTR_ERR(tegra_host->vdd_slot_reg));
2001                 tegra_host->vdd_slot_reg = NULL;
2002         }
2003
2004         if (tegra_host->card_present) {
2005                 if (tegra_host->vdd_slot_reg)
2006                         regulator_enable(tegra_host->vdd_slot_reg);
2007                 if (tegra_host->vdd_io_reg)
2008                         regulator_enable(tegra_host->vdd_io_reg);
2009                 tegra_host->is_rail_enabled = 1;
2010         }
2011
2012         pm_runtime_enable(&pdev->dev);
2013         pltfm_host->clk = clk_get(mmc_dev(host->mmc), NULL);
2014         if (IS_ERR(pltfm_host->clk)) {
2015                 dev_err(mmc_dev(host->mmc), "clk err\n");
2016                 rc = PTR_ERR(pltfm_host->clk);
2017                 goto err_clk_get;
2018         }
2019
2020         if (clk_get_parent(pltfm_host->clk) == pll_c)
2021                 tegra_host->is_parent_pllc = true;
2022
2023         pm_runtime_get_sync(&pdev->dev);
2024         rc = clk_prepare_enable(pltfm_host->clk);
2025         if (rc != 0)
2026                 goto err_clk_put;
2027
2028         if (!strcmp(dev_name(mmc_dev(host->mmc)), "sdhci-tegra.3")) {
2029                 tegra_host->emc_clk = clk_get(mmc_dev(host->mmc), "emc");
2030                 if (IS_ERR(tegra_host->emc_clk)) {
2031                         dev_err(mmc_dev(host->mmc), "clk err\n");
2032                         rc = PTR_ERR(tegra_host->emc_clk);
2033                         goto err_clk_put;
2034                 }
2035                 tegra_host->emc_max_clk =
2036                         clk_round_rate(tegra_host->emc_clk, ULONG_MAX);
2037         }
2038
2039         pltfm_host->priv = tegra_host;
2040         tegra_host->clk_enabled = true;
2041         tegra_host->max_clk_limit = plat->max_clk_limit;
2042         tegra_host->ddr_clk_limit = plat->ddr_clk_limit;
2043         tegra_host->sd_detect_in_suspend = plat->sd_detect_in_suspend;
2044         tegra_host->instance = pdev->id;
2045         tegra_host->dpd = tegra_io_dpd_get(mmc_dev(host->mmc));
2046
2047         host->mmc->pm_caps |= plat->pm_caps;
2048         host->mmc->pm_flags |= plat->pm_flags;
2049
2050         host->mmc->caps |= MMC_CAP_ERASE;
2051         /* enable 1/8V DDR capable */
2052         host->mmc->caps |= MMC_CAP_1_8V_DDR;
2053         if (plat->is_8bit)
2054                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
2055         host->mmc->caps |= MMC_CAP_SDIO_IRQ;
2056         host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_IGNORE_PM_NOTIFY;
2057         if (plat->mmc_data.built_in) {
2058                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
2059         }
2060         host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY;
2061
2062 #ifdef CONFIG_MMC_BKOPS
2063         host->mmc->caps2 |= MMC_CAP2_BKOPS;
2064 #endif
2065
2066         tegra_sdhost_min_freq = TEGRA_SDHOST_MIN_FREQ;
2067 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
2068         tegra_host->hw_ops = &tegra_2x_sdhci_ops;
2069         tegra_sdhost_std_freq = TEGRA2_SDHOST_STD_FREQ;
2070 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
2071         tegra_host->hw_ops = &tegra_3x_sdhci_ops;
2072         tegra_sdhost_std_freq = TEGRA3_SDHOST_STD_FREQ;
2073 #else
2074         tegra_host->hw_ops = &tegra_11x_sdhci_ops;
2075         tegra_sdhost_std_freq = TEGRA3_SDHOST_STD_FREQ;
2076 #endif
2077
2078         if (plat->nominal_vcore_uV)
2079                 tegra_host->nominal_vcore_uV = plat->nominal_vcore_uV;
2080
2081         rc = sdhci_add_host(host);
2082
2083         sdhci_tegra_error_stats_debugfs(host);
2084         if (rc)
2085                 goto err_add_host;
2086
2087         /* Enable async suspend/resume to reduce LP0 latency */
2088         device_enable_async_suspend(&pdev->dev);
2089
2090         return 0;
2091
2092 err_add_host:
2093         clk_put(tegra_host->emc_clk);
2094         clk_disable_unprepare(pltfm_host->clk);
2095         pm_runtime_put_sync(&pdev->dev);
2096 err_clk_put:
2097         clk_put(pltfm_host->clk);
2098 err_clk_get:
2099         if (gpio_is_valid(plat->wp_gpio))
2100                 gpio_free(plat->wp_gpio);
2101 err_wp_req:
2102         if (gpio_is_valid(plat->cd_gpio))
2103                 free_irq(gpio_to_irq(plat->cd_gpio), host);
2104 err_cd_irq_req:
2105         if (gpio_is_valid(plat->cd_gpio))
2106                 gpio_free(plat->cd_gpio);
2107 err_cd_req:
2108         if (gpio_is_valid(plat->power_gpio))
2109                 gpio_free(plat->power_gpio);
2110 err_power_req:
2111 err_no_plat:
2112         sdhci_pltfm_free(pdev);
2113         return rc;
2114 }
2115
2116 static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
2117 {
2118         struct sdhci_host *host = platform_get_drvdata(pdev);
2119         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2120         struct sdhci_tegra *tegra_host = pltfm_host->priv;
2121         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
2122         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
2123
2124         sdhci_remove_host(host, dead);
2125
2126         disable_irq_wake(gpio_to_irq(plat->cd_gpio));
2127
2128         if (tegra_host->vdd_slot_reg) {
2129                 regulator_disable(tegra_host->vdd_slot_reg);
2130                 regulator_put(tegra_host->vdd_slot_reg);
2131         }
2132
2133         if (tegra_host->vdd_io_reg) {
2134                 regulator_disable(tegra_host->vdd_io_reg);
2135                 regulator_put(tegra_host->vdd_io_reg);
2136         }
2137
2138         if (gpio_is_valid(plat->wp_gpio))
2139                 gpio_free(plat->wp_gpio);
2140
2141         if (gpio_is_valid(plat->cd_gpio)) {
2142                 free_irq(gpio_to_irq(plat->cd_gpio), host);
2143                 gpio_free(plat->cd_gpio);
2144         }
2145
2146         if (gpio_is_valid(plat->power_gpio))
2147                 gpio_free(plat->power_gpio);
2148
2149         if (tegra_host->clk_enabled) {
2150                 clk_disable_unprepare(pltfm_host->clk);
2151                 pm_runtime_put_sync(&pdev->dev);
2152         }
2153         clk_put(pltfm_host->clk);
2154
2155         sdhci_pltfm_free(pdev);
2156
2157         return 0;
2158 }
2159
2160 static struct platform_driver sdhci_tegra_driver = {
2161         .driver         = {
2162                 .name   = "sdhci-tegra",
2163                 .owner  = THIS_MODULE,
2164                 .of_match_table = sdhci_tegra_dt_match,
2165                 .pm     = SDHCI_PLTFM_PMOPS,
2166         },
2167         .probe          = sdhci_tegra_probe,
2168         .remove         = __devexit_p(sdhci_tegra_remove),
2169 };
2170
2171 module_platform_driver(sdhci_tegra_driver);
2172
2173 MODULE_DESCRIPTION("SDHCI driver for Tegra");
2174 MODULE_AUTHOR("Google, Inc.");
2175 MODULE_LICENSE("GPL v2");