2c173fd278a77098b2738c736a8248dadfee44cf
[linux-2.6.git] / drivers / mmc / host / sdhci-tegra.c
1 /*
2  * Copyright (C) 2010 Google, Inc.
3  *
4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/err.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/gpio.h>
27 #include <linux/slab.h>
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/host.h>
30 #include <linux/module.h>
31 #include <linux/mmc/sd.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/delay.h>
34 #include <linux/pm_runtime.h>
35 #include <asm/gpio.h>
36 #include <linux/debugfs.h>
37 #include <linux/seq_file.h>
38
39 #include <mach/gpio-tegra.h>
40 #include <mach/sdhci.h>
41 #include <mach/io_dpd.h>
42 #include <mach/pinmux.h>
43
44 #include "sdhci-pltfm.h"
45
46 #define SDHCI_VENDOR_CLOCK_CNTRL        0x100
47 #define SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK      0x1
48 #define SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE 0x8
49 #define SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE        0x4
50 #define SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT    8
51 #define SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT        16
52 #define SDHCI_VENDOR_CLOCK_CNTRL_TRIM_VALUE_SHIFT       24
53 #define SDHCI_VENDOR_CLOCK_CNTRL_SDR50_TUNING           0x20
54
55 #define SDHCI_VENDOR_MISC_CNTRL         0x120
56 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT   0x8
57 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT    0x10
58 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_DDR50_SUPPORT    0x200
59 #define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SD_3_0   0x20
60 #define SDHCI_VENDOR_MISC_CNTRL_INFINITE_ERASE_TIMEOUT  0x1
61
62 #define SDMMC_SDMEMCOMPPADCTRL  0x1E0
63 #define SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK    0xF
64
65 #define SDMMC_AUTO_CAL_CONFIG   0x1E4
66 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START    0x80000000
67 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE   0x20000000
68 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT  0x8
69 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET        0x70
70 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET        0x62
71
72 #define SDMMC_AUTO_CAL_STATUS   0x1EC
73 #define SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE   0x80000000
74 #define SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET   24
75 #define PULLUP_ADJUSTMENT_OFFSET        20
76
77 #define SDHOST_1V8_OCR_MASK     0x8
78 #define SDHOST_HIGH_VOLT_MIN    2700000
79 #define SDHOST_HIGH_VOLT_MAX    3600000
80 #define SDHOST_HIGH_VOLT_2V8    2800000
81 #define SDHOST_LOW_VOLT_MIN     1800000
82 #define SDHOST_LOW_VOLT_MAX     1800000
83
84 #define TEGRA_SDHOST_MIN_FREQ   50000000
85 #define TEGRA2_SDHOST_STD_FREQ  50000000
86 #define TEGRA3_SDHOST_STD_FREQ  104000000
87
88 #define MAX_DIVISOR_VALUE       128
89
90 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8       128
91 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4       64
92 #define MAX_TAP_VALUES  255
93 #define TUNING_FREQ_COUNT       2
94 #define TUNING_VOLTAGES_COUNT   2
95
96 static unsigned int uhs_max_freq_MHz[] = {
97         [MMC_TIMING_UHS_SDR50] = 100,
98         [MMC_TIMING_UHS_SDR104] = 208,
99         [MMC_TIMING_MMC_HS200] = 200,
100 };
101
102 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
103 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock);
104 static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci);
105 #endif
106
107 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
108 static void tegra11x_sdhci_post_reset_init(struct sdhci_host *sdhci);
109 #endif
110
111 static unsigned int tegra_sdhost_min_freq;
112 static unsigned int tegra_sdhost_std_freq;
113
114 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
115 static unsigned int tegra3_sdhost_max_clk[4] = {
116         208000000,      104000000,      208000000,      104000000 };
117 #endif
118
119 struct tegra_sdhci_hw_ops{
120         /* Set the internal clk and card clk.*/
121         void    (*set_card_clock)(struct sdhci_host *sdhci, unsigned int clock);
122         /* Post reset vendor registers configuration */
123         void    (*sdhost_init)(struct sdhci_host *sdhci);
124 };
125
126 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
127 static struct tegra_sdhci_hw_ops tegra_2x_sdhci_ops = {
128 };
129 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
130 static struct tegra_sdhci_hw_ops tegra_3x_sdhci_ops = {
131         .set_card_clock = tegra_3x_sdhci_set_card_clock,
132         .sdhost_init = tegra3_sdhci_post_reset_init,
133 };
134 #else
135 static struct tegra_sdhci_hw_ops tegra_11x_sdhci_ops = {
136         .sdhost_init = tegra11x_sdhci_post_reset_init,
137 };
138 #endif
139
140 #define NVQUIRK_FORCE_SDHCI_SPEC_200            BIT(0)
141 #define NVQUIRK_ENABLE_BLOCK_GAP_DET            BIT(1)
142 #define NVQUIRK_DISABLE_AUTO_CALIBRATION        BIT(2)
143 #define NVQUIRK_SET_CALIBRATION_OFFSETS BIT(3)
144 #define NVQUIRK_SET_DRIVE_STRENGTH              BIT(4)
145
146 struct sdhci_tegra_soc_data {
147         struct sdhci_pltfm_data *pdata;
148         u32 nvquirks;
149 };
150
151 struct sdhci_tegra_sd_stats {
152         unsigned int data_crc_count;
153         unsigned int cmd_crc_count;
154         unsigned int data_to_count;
155         unsigned int cmd_to_count;
156 };
157
158 enum tegra_tuning_freq {
159         TUNING_LOW_FREQ,
160         TUNING_HIGH_FREQ,
161 };
162
163 struct freq_tuning_params {
164         unsigned int    freq_hz;
165         unsigned int    nr_voltages;
166         unsigned int    voltages[TUNING_VOLTAGES_COUNT];
167 };
168
169 static struct freq_tuning_params tuning_params[TUNING_FREQ_COUNT] = {
170         [TUNING_LOW_FREQ] = {
171                 .freq_hz = 82000000,
172                 .nr_voltages = 1,
173                 .voltages = {ULONG_MAX},
174         },
175         [TUNING_HIGH_FREQ] = {
176                 .freq_hz = 156000000,
177                 .nr_voltages = 2,
178                 .voltages = {ULONG_MAX, 1100000},
179         },
180 };
181
182 struct tap_window_data {
183         unsigned int    partial_win;
184         unsigned int    full_win_begin;
185         unsigned int    full_win_end;
186         unsigned int    tuning_ui;
187         unsigned int    sampling_point;
188         bool            abandon_partial_win;
189         bool            abandon_full_win;
190 };
191
192 struct tegra_tuning_data {
193         unsigned int            best_tap_value;
194         bool                    select_partial_win;
195         struct tap_window_data  *tap_data[TUNING_VOLTAGES_COUNT];
196 };
197
198 struct sdhci_tegra {
199         const struct tegra_sdhci_platform_data *plat;
200         const struct sdhci_tegra_soc_data *soc_data;
201         bool    clk_enabled;
202         struct regulator *vdd_io_reg;
203         struct regulator *vdd_slot_reg;
204         struct regulator *vcore_reg;
205         /* Pointer to the chip specific HW ops */
206         struct tegra_sdhci_hw_ops *hw_ops;
207         /* Host controller instance */
208         unsigned int instance;
209         /* vddio_min */
210         unsigned int vddio_min_uv;
211         /* vddio_max */
212         unsigned int vddio_max_uv;
213         /* max clk supported by the platform */
214         unsigned int max_clk_limit;
215         /* max ddr clk supported by the platform */
216         unsigned int ddr_clk_limit;
217         /* SD Hot Plug in Suspend State */
218         unsigned int sd_detect_in_suspend;
219         struct tegra_io_dpd *dpd;
220         bool card_present;
221         bool is_rail_enabled;
222         struct clk *emc_clk;
223         unsigned int emc_max_clk;
224         struct sdhci_tegra_sd_stats *sd_stat_head;
225         unsigned int nominal_vcore_uV;
226         /* Tuning related structures and variables */
227         /* Tuning opcode to be used */
228         unsigned int tuning_opcode;
229         /* Tuning packet size */
230         unsigned int tuning_bsize;
231         /* Tuning status */
232         unsigned int tuning_status;
233 #define TUNING_STATUS_DONE      1
234 #define TUNING_STATUS_RETUNE    2
235         /* Freq tuning information for each sampling clock freq */
236         struct tegra_tuning_data tuning_data;
237         bool is_parent_pllc;
238 };
239
240 static struct clk *pll_c;
241 static struct clk *pll_p;
242 static unsigned long pll_c_rate;
243 static unsigned long pll_p_rate;
244
245 static int show_error_stats_dump(struct seq_file *s, void *data)
246 {
247         struct sdhci_host *host = s->private;
248         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
249         struct sdhci_tegra *tegra_host = pltfm_host->priv;
250         struct sdhci_tegra_sd_stats *head;
251
252         seq_printf(s, "ErrorStatistics:\n");
253         seq_printf(s, "DataCRC\tCmdCRC\tDataTimeout\tCmdTimeout\n");
254         head = tegra_host->sd_stat_head;
255         if (head != NULL)
256                 seq_printf(s, "%d\t%d\t%d\t%d\n", head->data_crc_count,
257                         head->cmd_crc_count, head->data_to_count,
258                         head->cmd_to_count);
259         return 0;
260 }
261
262 static int sdhci_error_stats_dump(struct inode *inode, struct file *file)
263 {
264         return single_open(file, show_error_stats_dump, inode->i_private);
265 }
266
267 static const struct file_operations sdhci_host_fops = {
268         .open           = sdhci_error_stats_dump,
269         .read           = seq_read,
270         .llseek         = seq_lseek,
271         .release        = single_release,
272 };
273
274 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
275 {
276 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
277         u32 val;
278
279         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
280                 /* Use wp_gpio here instead? */
281                 val = readl(host->ioaddr + reg);
282                 return val | SDHCI_WRITE_PROTECT;
283         }
284 #endif
285         return readl(host->ioaddr + reg);
286 }
287
288 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
289 {
290 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
291         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
292         struct sdhci_tegra *tegra_host = pltfm_host->priv;
293         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
294
295         if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
296                         (reg == SDHCI_HOST_VERSION))) {
297                 /* Erratum: Version register is invalid in HW. */
298                 return SDHCI_SPEC_200;
299         }
300 #endif
301         return readw(host->ioaddr + reg);
302 }
303
304 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
305 {
306 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
307         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
308         struct sdhci_tegra *tegra_host = pltfm_host->priv;
309         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
310 #endif
311
312         /* Seems like we're getting spurious timeout and crc errors, so
313          * disable signalling of them. In case of real errors software
314          * timers should take care of eventually detecting them.
315          */
316         if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
317                 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
318
319         writel(val, host->ioaddr + reg);
320
321 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
322         if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
323                         (reg == SDHCI_INT_ENABLE))) {
324                 /* Erratum: Must enable block gap interrupt detection */
325                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
326                 if (val & SDHCI_INT_CARD_INT)
327                         gap_ctrl |= 0x8;
328                 else
329                         gap_ctrl &= ~0x8;
330                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
331         }
332 #endif
333 }
334
335 static unsigned int tegra_sdhci_get_cd(struct sdhci_host *sdhci)
336 {
337         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
338         struct sdhci_tegra *tegra_host = pltfm_host->priv;
339
340         return tegra_host->card_present;
341 }
342
343 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
344 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
345 {
346         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
347         struct sdhci_tegra *tegra_host = pltfm_host->priv;
348         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
349
350         if (!gpio_is_valid(plat->wp_gpio))
351                 return -1;
352
353         return gpio_get_value(plat->wp_gpio);
354 }
355 #endif
356
357 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
358 static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci)
359 {
360         u16 misc_ctrl;
361         u32 vendor_ctrl;
362         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
363         struct sdhci_tegra *tegra_host = pltfm_host->priv;
364         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
365
366         if (tegra_host->sd_stat_head != NULL) {
367                 tegra_host->sd_stat_head->data_crc_count = 0;
368                 tegra_host->sd_stat_head->cmd_crc_count = 0;
369                 tegra_host->sd_stat_head->data_to_count = 0;
370                 tegra_host->sd_stat_head->cmd_to_count = 0;
371         }
372         /* Set the base clock frequency */
373         vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
374         vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT);
375         vendor_ctrl |= (tegra3_sdhost_max_clk[tegra_host->instance] / 1000000) <<
376                 SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT;
377         vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
378         vendor_ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE;
379
380         /* Set tap delay */
381         if (plat->tap_delay) {
382                 vendor_ctrl &= ~(0xFF <<
383                         SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
384                 vendor_ctrl |= (plat->tap_delay <<
385                         SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
386         }
387         /* Enable frequency tuning for SDR50 mode */
388         vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDR50_TUNING;
389         sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
390
391         /* Enable SDHOST v3.0 support */
392         misc_ctrl = sdhci_readw(sdhci, SDHCI_VENDOR_MISC_CNTRL);
393         misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_SD_3_0 |
394                 SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT |
395                 SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT;
396         sdhci_writew(sdhci, misc_ctrl, SDHCI_VENDOR_MISC_CNTRL);
397 }
398 #endif
399
400 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
401 static void tegra11x_sdhci_post_reset_init(struct sdhci_host *sdhci)
402 {
403         u16 misc_ctrl;
404         u32 vendor_ctrl;
405         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
406         struct sdhci_tegra *tegra_host = pltfm_host->priv;
407         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
408         struct tegra_sdhci_platform_data *plat;
409
410         if (tegra_host->sd_stat_head != NULL) {
411                 tegra_host->sd_stat_head->data_crc_count = 0;
412                 tegra_host->sd_stat_head->cmd_crc_count = 0;
413                 tegra_host->sd_stat_head->data_to_count = 0;
414                 tegra_host->sd_stat_head->cmd_to_count = 0;
415         }
416
417         plat = pdev->dev.platform_data;
418         /* Set the base clock frequency */
419         vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
420         vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT);
421         vendor_ctrl |= (tegra3_sdhost_max_clk[tegra_host->instance] / 1000000) <<
422                 SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT;
423         vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
424         vendor_ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE;
425
426         /* Set tap delay */
427         if (plat->tap_delay) {
428                 vendor_ctrl &= ~(0xFF <<
429                         SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
430                 vendor_ctrl |= (plat->tap_delay <<
431                         SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
432         }
433
434         /* Set trim delay */
435         vendor_ctrl &= ~(0x1F <<
436                 SDHCI_VENDOR_CLOCK_CNTRL_TRIM_VALUE_SHIFT);
437         vendor_ctrl |= (plat->trim_delay <<
438                 SDHCI_VENDOR_CLOCK_CNTRL_TRIM_VALUE_SHIFT);
439         sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
440
441         /* Enable SDHOST v3.0 support */
442         misc_ctrl = sdhci_readw(sdhci, SDHCI_VENDOR_MISC_CNTRL);
443         misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT |
444                 SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT;
445         /* Enable DDR mode support only for SDMMC4 */
446         if (tegra_host->instance == 3)
447                 misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_DDR50_SUPPORT;
448         misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_INFINITE_ERASE_TIMEOUT;
449         sdhci_writew(sdhci, misc_ctrl, SDHCI_VENDOR_MISC_CNTRL);
450 }
451 #endif
452
453 static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
454                 unsigned int uhs)
455 {
456         u16 clk, ctrl_2;
457         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
458
459         /* Select Bus Speed Mode for host */
460         /* For HS200 we need to set UHS_MODE_SEL to SDR104.
461          * It works as SDR 104 in SD 4-bit mode and HS200 in eMMC 8-bit mode.
462          */
463         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
464         switch (uhs) {
465         case MMC_TIMING_UHS_SDR12:
466                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
467                 break;
468         case MMC_TIMING_UHS_SDR25:
469                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
470                 break;
471         case MMC_TIMING_UHS_SDR50:
472                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
473                 break;
474         case MMC_TIMING_UHS_SDR104:
475         case MMC_TIMING_MMC_HS200:
476                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
477                 break;
478         case MMC_TIMING_UHS_DDR50:
479                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
480                 break;
481         }
482
483         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
484
485         if (uhs == MMC_TIMING_UHS_DDR50) {
486                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
487                 clk &= ~(0xFF << SDHCI_DIVIDER_SHIFT);
488                 clk |= 1 << SDHCI_DIVIDER_SHIFT;
489                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
490         }
491         return 0;
492 }
493
494 static void tegra_sdhci_reset_exit(struct sdhci_host *sdhci, u8 mask)
495 {
496         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
497         struct sdhci_tegra *tegra_host = pltfm_host->priv;
498         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
499
500         if (mask & SDHCI_RESET_ALL) {
501                 if (tegra_host->hw_ops->sdhost_init)
502                         tegra_host->hw_ops->sdhost_init(sdhci);
503
504                 /* Mask the support for any UHS modes if specified */
505                 if (plat->uhs_mask & MMC_UHS_MASK_SDR104)
506                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR104;
507
508                 if (plat->uhs_mask & MMC_UHS_MASK_DDR50)
509                         sdhci->mmc->caps &= ~MMC_CAP_UHS_DDR50;
510
511                 if (plat->uhs_mask & MMC_UHS_MASK_SDR50)
512                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR50;
513
514                 if (plat->uhs_mask & MMC_UHS_MASK_SDR25)
515                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR25;
516
517                 if (plat->uhs_mask & MMC_UHS_MASK_SDR12)
518                         sdhci->mmc->caps &= ~MMC_CAP_UHS_SDR12;
519
520                 if (plat->uhs_mask & MMC_MASK_HS200)
521                         sdhci->mmc->caps2 &= ~MMC_CAP2_HS200;
522         }
523 }
524
525 static void sdhci_status_notify_cb(int card_present, void *dev_id)
526 {
527         struct sdhci_host *sdhci = (struct sdhci_host *)dev_id;
528         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
529         struct tegra_sdhci_platform_data *plat;
530         unsigned int status, oldstat;
531
532         pr_debug("%s: card_present %d\n", mmc_hostname(sdhci->mmc),
533                 card_present);
534
535         plat = pdev->dev.platform_data;
536         if (!plat->mmc_data.status) {
537                 mmc_detect_change(sdhci->mmc, 0);
538                 return;
539         }
540
541         status = plat->mmc_data.status(mmc_dev(sdhci->mmc));
542
543         oldstat = plat->mmc_data.card_present;
544         plat->mmc_data.card_present = status;
545         if (status ^ oldstat) {
546                 pr_debug("%s: Slot status change detected (%d -> %d)\n",
547                         mmc_hostname(sdhci->mmc), oldstat, status);
548                 if (status && !plat->mmc_data.built_in)
549                         mmc_detect_change(sdhci->mmc, (5 * HZ) / 2);
550                 else
551                         mmc_detect_change(sdhci->mmc, 0);
552         }
553 }
554
555 static irqreturn_t carddetect_irq(int irq, void *data)
556 {
557         struct sdhci_host *sdhost = (struct sdhci_host *)data;
558         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
559         struct sdhci_tegra *tegra_host = pltfm_host->priv;
560         struct platform_device *pdev = to_platform_device(mmc_dev(sdhost->mmc));
561         struct tegra_sdhci_platform_data *plat;
562
563         plat = pdev->dev.platform_data;
564
565         tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
566
567         if (tegra_host->card_present) {
568                 if (!tegra_host->is_rail_enabled) {
569                         if (tegra_host->vdd_slot_reg)
570                                 regulator_enable(tegra_host->vdd_slot_reg);
571                         if (tegra_host->vdd_io_reg)
572                                 regulator_enable(tegra_host->vdd_io_reg);
573                         tegra_host->is_rail_enabled = 1;
574                 }
575         } else {
576                 if (tegra_host->is_rail_enabled) {
577                         if (tegra_host->vdd_io_reg)
578                                 regulator_disable(tegra_host->vdd_io_reg);
579                         if (tegra_host->vdd_slot_reg)
580                                 regulator_disable(tegra_host->vdd_slot_reg);
581                         tegra_host->is_rail_enabled = 0;
582                 }
583                 /*
584                  * Set retune request as tuning should be done next time
585                  * a card is inserted.
586                  */
587                 tegra_host->tuning_status = TUNING_STATUS_RETUNE;
588         }
589
590         tasklet_schedule(&sdhost->card_tasklet);
591         return IRQ_HANDLED;
592 };
593
594 static int tegra_sdhci_8bit(struct sdhci_host *sdhci, int bus_width)
595 {
596         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
597         const struct tegra_sdhci_platform_data *plat;
598         u32 ctrl;
599
600         plat = pdev->dev.platform_data;
601
602         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL);
603         if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
604                 ctrl &= ~SDHCI_CTRL_4BITBUS;
605                 ctrl |= SDHCI_CTRL_8BITBUS;
606         } else {
607                 ctrl &= ~SDHCI_CTRL_8BITBUS;
608                 if (bus_width == MMC_BUS_WIDTH_4)
609                         ctrl |= SDHCI_CTRL_4BITBUS;
610                 else
611                         ctrl &= ~SDHCI_CTRL_4BITBUS;
612         }
613         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL);
614         return 0;
615 }
616
617 /*
618 * Calculation of nearest clock frequency for desired rate:
619 * Get the divisor value, div = p / d_rate
620 * 1. If it is nearer to ceil(p/d_rate) then increment the div value by 0.5 and
621 * nearest_rate, i.e. result = p / (div + 0.5) = (p << 1)/((div << 1) + 1).
622 * 2. If not, result = p / div
623 * As the nearest clk freq should be <= to desired_rate,
624 * 3. If result > desired_rate then increment the div by 0.5
625 * and do, (p << 1)/((div << 1) + 1)
626 * 4. Else return result
627 * Here, If condtions 1 & 3 are both satisfied then to keep track of div value,
628 * defined index variable.
629 */
630 static unsigned long get_nearest_clock_freq(unsigned long pll_rate,
631                 unsigned long desired_rate)
632 {
633         unsigned long result;
634         int div;
635         int index = 1;
636
637         div = pll_rate / desired_rate;
638         if (div > MAX_DIVISOR_VALUE) {
639                 div = MAX_DIVISOR_VALUE;
640                 result = pll_rate / div;
641         } else {
642                 if ((pll_rate % desired_rate) >= (desired_rate / 2))
643                         result = (pll_rate << 1) / ((div << 1) + index++);
644                 else
645                         result = pll_rate / div;
646
647                 if (desired_rate < result) {
648                         /*
649                         * Trying to get lower clock freq than desired clock,
650                         * by increasing the divisor value by 0.5
651                         */
652                         result = (pll_rate << 1) / ((div << 1) + index);
653                 }
654         }
655
656         return result;
657 }
658
659 static void tegra_sdhci_clock_set_parent(struct sdhci_host *host,
660                 unsigned long desired_rate)
661 {
662         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
663         struct sdhci_tegra *tegra_host = pltfm_host->priv;
664         struct clk *parent_clk;
665         unsigned long pll_c_freq;
666         unsigned long pll_p_freq;
667         int rc;
668
669         pll_c_freq = get_nearest_clock_freq(pll_c_rate, desired_rate);
670         pll_p_freq = get_nearest_clock_freq(pll_p_rate, desired_rate);
671
672         if (pll_c_freq > pll_p_freq) {
673                 if (!tegra_host->is_parent_pllc) {
674                         parent_clk = pll_c;
675                         tegra_host->is_parent_pllc = true;
676                 } else
677                         return;
678         } else if (tegra_host->is_parent_pllc) {
679                 parent_clk = pll_p;
680                 tegra_host->is_parent_pllc = false;
681         } else
682                 return;
683
684         rc = clk_set_parent(pltfm_host->clk, parent_clk);
685         if (rc)
686                 pr_err("%s: failed to set pll parent clock %d\n",
687                         mmc_hostname(host->mmc), rc);
688 }
689
690 static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci,
691         unsigned int clock)
692 {
693         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
694         struct sdhci_tegra *tegra_host = pltfm_host->priv;
695         unsigned int clk_rate;
696         unsigned int emc_clk;
697
698         if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
699                 /*
700                  * In ddr mode, tegra sdmmc controller clock frequency
701                  * should be double the card clock frequency.
702                  */
703                 if (tegra_host->ddr_clk_limit) {
704                         clk_rate = tegra_host->ddr_clk_limit * 2;
705                         if (tegra_host->emc_clk) {
706                                 emc_clk = clk_get_rate(tegra_host->emc_clk);
707                                 if (emc_clk == tegra_host->emc_max_clk)
708                                         clk_rate = clock * 2;
709                         }
710                 } else {
711                         clk_rate = clock * 2;
712                 }
713         } else  if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50) {
714                 /*
715                  * In SDR50 mode, run the sdmmc controller at freq greater than
716                  * 104MHz to ensure the core voltage is at 1.2V. If the core voltage
717                  * is below 1.2V, CRC errors would occur during data transfers.
718                  */
719                 clk_rate = clock * 2;
720         } else {
721                 if (clock <= tegra_sdhost_min_freq)
722                         clk_rate = tegra_sdhost_min_freq;
723                 else if (clock <= tegra_sdhost_std_freq)
724                         clk_rate = tegra_sdhost_std_freq;
725                 else
726                         clk_rate = clock;
727         }
728
729         if (tegra_host->max_clk_limit &&
730                 (clk_rate > tegra_host->max_clk_limit))
731                 clk_rate = tegra_host->max_clk_limit;
732
733         tegra_sdhci_clock_set_parent(sdhci, clk_rate);
734         clk_set_rate(pltfm_host->clk, clk_rate);
735         sdhci->max_clk = clk_get_rate(pltfm_host->clk);
736 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
737         /* FPGA supports 26MHz of clock for SDMMC. */
738         sdhci->max_clk = 26000000;
739 #endif
740 }
741 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
742 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock)
743 {
744         int div;
745         u16 clk;
746         unsigned long timeout;
747         u8 ctrl;
748
749         if (clock && clock == sdhci->clock)
750                 return;
751
752         /*
753          * Disable the card clock before disabling the internal
754          * clock to avoid abnormal clock waveforms.
755          */
756         clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
757         clk &= ~SDHCI_CLOCK_CARD_EN;
758         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
759         sdhci_writew(sdhci, 0, SDHCI_CLOCK_CONTROL);
760
761         if (clock == 0)
762                 goto out;
763         if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
764                 div = 1;
765                 goto set_clk;
766         }
767
768         if (sdhci->version >= SDHCI_SPEC_300) {
769                 /* Version 3.00 divisors must be a multiple of 2. */
770                 if (sdhci->max_clk <= clock) {
771                         div = 1;
772                 } else {
773                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
774                                 if ((sdhci->max_clk / div) <= clock)
775                                         break;
776                         }
777                 }
778         } else {
779                 /* Version 2.00 divisors must be a power of 2. */
780                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
781                         if ((sdhci->max_clk / div) <= clock)
782                                 break;
783                 }
784         }
785         div >>= 1;
786
787         /*
788          * Tegra3 sdmmc controller internal clock will not be stabilized when
789          * we use a clock divider value greater than 4. The WAR is as follows.
790          * - Enable internal clock.
791          * - Wait for 5 usec and do a dummy write.
792          * - Poll for clk stable.
793          */
794 set_clk:
795         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
796         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
797                 << SDHCI_DIVIDER_HI_SHIFT;
798         clk |= SDHCI_CLOCK_INT_EN;
799         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
800
801         /* Wait for 5 usec */
802         udelay(5);
803
804         /* Do a dummy write */
805         ctrl = sdhci_readb(sdhci, SDHCI_CAPABILITIES);
806         ctrl |= 1;
807         sdhci_writeb(sdhci, ctrl, SDHCI_CAPABILITIES);
808
809         /* Wait max 20 ms */
810         timeout = 20;
811         while (!((clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL))
812                 & SDHCI_CLOCK_INT_STABLE)) {
813                 if (timeout == 0) {
814                         dev_err(mmc_dev(sdhci->mmc), "Internal clock never stabilised\n");
815                         return;
816                 }
817                 timeout--;
818                 mdelay(1);
819         }
820
821         clk |= SDHCI_CLOCK_CARD_EN;
822         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
823 out:
824         sdhci->clock = clock;
825 }
826 #endif /*       #ifdef CONFIG_ARCH_TEGRA_3x_SOC */
827
828 static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock)
829 {
830         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
831         struct sdhci_tegra *tegra_host = pltfm_host->priv;
832         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
833         u8 ctrl;
834
835         pr_debug("%s %s %u enabled=%u\n", __func__,
836                 mmc_hostname(sdhci->mmc), clock, tegra_host->clk_enabled);
837
838         if (clock) {
839                 /* bring out sd instance from io dpd mode */
840                 if (tegra_host->dpd) {
841                         mutex_lock(&tegra_host->dpd->delay_lock);
842                         cancel_delayed_work_sync(&tegra_host->dpd->delay_dpd);
843                         tegra_io_dpd_disable(tegra_host->dpd);
844                         mutex_unlock(&tegra_host->dpd->delay_lock);
845                 }
846
847                 if (!tegra_host->clk_enabled) {
848                         pm_runtime_get_sync(&pdev->dev);
849                         clk_prepare_enable(pltfm_host->clk);
850                         ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
851                         ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
852                         sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
853                         tegra_host->clk_enabled = true;
854                 }
855                 tegra_sdhci_set_clk_rate(sdhci, clock);
856                 if (tegra_host->hw_ops->set_card_clock)
857                         tegra_host->hw_ops->set_card_clock(sdhci, clock);
858         } else if (!clock && tegra_host->clk_enabled) {
859                 if (tegra_host->hw_ops->set_card_clock)
860                         tegra_host->hw_ops->set_card_clock(sdhci, clock);
861                 ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
862                 ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
863                 sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
864                 clk_disable_unprepare(pltfm_host->clk);
865                 pm_runtime_put_sync(&pdev->dev);
866                 tegra_host->clk_enabled = false;
867                 /* io dpd enable call for sd instance */
868
869                 if (tegra_host->dpd) {
870                         mutex_lock(&tegra_host->dpd->delay_lock);
871                         if (tegra_host->dpd->need_delay_dpd) {
872                                 schedule_delayed_work(
873                                         &tegra_host->dpd->delay_dpd,
874                                         msecs_to_jiffies(100));
875                         } else {
876                                 tegra_io_dpd_enable(tegra_host->dpd);
877                         }
878                         mutex_unlock(&tegra_host->dpd->delay_lock);
879                 }
880         }
881 }
882 static void tegra_sdhci_do_calibration(struct sdhci_host *sdhci)
883 {
884         unsigned int val;
885         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
886         struct sdhci_tegra *tegra_host = pltfm_host->priv;
887         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
888         unsigned int timeout = 10;
889
890         /* No Calibration for sdmmc4 */
891         if (tegra_host->instance == 3)
892                 return;
893
894         /*
895          * Do not enable auto calibration if the platform doesn't
896          * support it.
897          */
898         if (unlikely(soc_data->nvquirks & NVQUIRK_DISABLE_AUTO_CALIBRATION))
899                 return;
900
901         val = sdhci_readl(sdhci, SDMMC_SDMEMCOMPPADCTRL);
902         val &= ~SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK;
903         val |= 0x7;
904         sdhci_writel(sdhci, val, SDMMC_SDMEMCOMPPADCTRL);
905
906         /* Enable Auto Calibration*/
907         val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
908         val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
909         val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
910         if (unlikely(soc_data->nvquirks & NVQUIRK_SET_CALIBRATION_OFFSETS)) {
911                 /* Program Auto cal PD offset(bits 8:14) */
912                 val &= ~(0x7F <<
913                         SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
914                 val |= (SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET <<
915                         SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
916                 /* Program Auto cal PU offset(bits 0:6) */
917                 val &= ~0x7F;
918                 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET;
919         }
920         sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
921
922         /* Wait until the calibration is done */
923         do {
924                 if (!(sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) &
925                         SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE))
926                         break;
927
928                 mdelay(1);
929                 timeout--;
930         } while (timeout);
931
932         if (!timeout)
933                 dev_err(mmc_dev(sdhci->mmc), "Auto calibration failed\n");
934
935         /* Disable Auto calibration */
936         val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
937         val &= ~SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
938         sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
939
940         if (unlikely(soc_data->nvquirks & NVQUIRK_SET_DRIVE_STRENGTH)) {
941                 unsigned int pulldown_code;
942                 unsigned int pullup_code;
943                 int pg;
944                 int err;
945
946                 pg = tegra_drive_get_pingroup(mmc_dev(sdhci->mmc));
947                 if (pg != -1) {
948                         /* Get the pull down codes from auto cal status reg */
949                         pulldown_code = (
950                                 sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) >>
951                                 SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET);
952                         /* Set the pull down in the pinmux reg */
953                         err = tegra_drive_pinmux_set_pull_down(pg,
954                                 pulldown_code);
955                         if (err)
956                                 dev_err(mmc_dev(sdhci->mmc),
957                                 "Failed to set pulldown codes %d err %d\n",
958                                 pulldown_code, err);
959
960                         /* Calculate the pull up codes */
961                         pullup_code = pulldown_code + PULLUP_ADJUSTMENT_OFFSET;
962                         if (pullup_code >= TEGRA_MAX_PULL)
963                                 pullup_code = TEGRA_MAX_PULL - 1;
964                         /* Set the pull up code in the pinmux reg */
965                         err = tegra_drive_pinmux_set_pull_up(pg, pullup_code);
966                         if (err)
967                                 dev_err(mmc_dev(sdhci->mmc),
968                                 "Failed to set pullup codes %d err %d\n",
969                                 pullup_code, err);
970                 }
971         }
972 }
973
974 static int tegra_sdhci_signal_voltage_switch(struct sdhci_host *sdhci,
975         unsigned int signal_voltage)
976 {
977         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
978         struct sdhci_tegra *tegra_host = pltfm_host->priv;
979         unsigned int min_uV = tegra_host->vddio_min_uv;
980         unsigned int max_uV = tegra_host->vddio_max_uv;
981         unsigned int rc = 0;
982         u16 clk, ctrl;
983
984
985         ctrl = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
986         if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
987                 ctrl |= SDHCI_CTRL_VDD_180;
988                 min_uV = SDHOST_LOW_VOLT_MIN;
989                 max_uV = SDHOST_LOW_VOLT_MAX;
990         } else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
991                 if (ctrl & SDHCI_CTRL_VDD_180)
992                         ctrl &= ~SDHCI_CTRL_VDD_180;
993         }
994
995         /* Check if the slot can support the required voltage */
996         if (min_uV > tegra_host->vddio_max_uv)
997                 return 0;
998
999         /* Switch OFF the card clock to prevent glitches on the clock line */
1000         clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
1001         clk &= ~SDHCI_CLOCK_CARD_EN;
1002         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
1003
1004         /* Set/clear the 1.8V signalling */
1005         sdhci_writew(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1006
1007         /* Switch the I/O rail voltage */
1008         if (tegra_host->vdd_io_reg) {
1009                 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1010                         min_uV, max_uV);
1011                 if (rc) {
1012                         dev_err(mmc_dev(sdhci->mmc), "switching to 1.8V"
1013                         "failed . Switching back to 3.3V\n");
1014                         rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1015                                 SDHOST_HIGH_VOLT_MIN,
1016                                 SDHOST_HIGH_VOLT_MAX);
1017                         if (rc)
1018                                 dev_err(mmc_dev(sdhci->mmc),
1019                                 "switching to 3.3V also failed\n");
1020                 }
1021         }
1022
1023         /* Wait for 10 msec for the voltage to be switched */
1024         mdelay(10);
1025
1026         /* Enable the card clock */
1027         clk |= SDHCI_CLOCK_CARD_EN;
1028         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
1029
1030         /* Wait for 1 msec after enabling clock */
1031         mdelay(1);
1032
1033         return rc;
1034 }
1035
1036 static void tegra_sdhci_reset(struct sdhci_host *sdhci, u8 mask)
1037 {
1038         unsigned long timeout;
1039
1040         sdhci_writeb(sdhci, mask, SDHCI_SOFTWARE_RESET);
1041
1042         /* Wait max 100 ms */
1043         timeout = 100;
1044
1045         /* hw clears the bit when it's done */
1046         while (sdhci_readb(sdhci, SDHCI_SOFTWARE_RESET) & mask) {
1047                 if (timeout == 0) {
1048                         dev_err(mmc_dev(sdhci->mmc), "Reset 0x%x never"
1049                                 "completed.\n", (int)mask);
1050                         return;
1051                 }
1052                 timeout--;
1053                 mdelay(1);
1054         }
1055
1056         tegra_sdhci_reset_exit(sdhci, mask);
1057 }
1058
1059 static void sdhci_tegra_set_tap_delay(struct sdhci_host *sdhci,
1060         unsigned int tap_delay)
1061 {
1062         u32 vendor_ctrl;
1063
1064         /* Max tap delay value is 255 */
1065         BUG_ON(tap_delay > MAX_TAP_VALUES);
1066
1067         vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
1068         vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
1069         vendor_ctrl |= (tap_delay << SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
1070         sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
1071 }
1072
1073 static int sdhci_tegra_sd_error_stats(struct sdhci_host *host, u32 int_status)
1074 {
1075         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1076         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1077         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
1078         struct sdhci_tegra_sd_stats *head;
1079
1080         if (tegra_host->sd_stat_head == NULL) {
1081                 tegra_host->sd_stat_head = devm_kzalloc(&pdev->dev, sizeof(
1082                                                 struct sdhci_tegra_sd_stats),
1083                                                 GFP_KERNEL);
1084                 if (tegra_host->sd_stat_head == NULL)
1085                         return -ENOMEM;
1086         }
1087         head = tegra_host->sd_stat_head;
1088         if (int_status & SDHCI_INT_DATA_CRC)
1089                 head->data_crc_count++;
1090         if (int_status & SDHCI_INT_CRC)
1091                 head->cmd_crc_count++;
1092         if (int_status & SDHCI_INT_TIMEOUT)
1093                 head->cmd_to_count++;
1094         if (int_status & SDHCI_INT_DATA_TIMEOUT)
1095                 head->data_to_count++;
1096         return 0;
1097 }
1098
1099 /*
1100  * Calculation of best tap value for low frequencies(82MHz).
1101  * X = Partial win, Y = Full win start, Z = Full win end.
1102  * UI = Z - X.
1103  * Full Window = Z - Y.
1104  * Taps margin = mid-point of 1/2*(curr_freq/max_frequency)*UI
1105  *                    = (1/2)*(1/2)*(82/200)*UI
1106  *                    = (0.1025)*UI
1107  * if Partial win<(0.22)*UI
1108  * best tap = Y+(0.1025*UI)
1109  * else
1110  * best tap = (X-(Z-Y))+(0.1025*UI)
1111  * If best tap<0, best tap = 0
1112  */
1113 static void calculate_low_freq_tap_value(struct sdhci_host *sdhci)
1114 {
1115         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1116         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1117         unsigned int curr_clock;
1118         unsigned int max_clock;
1119         int best_tap_value;
1120         struct tap_window_data *tap_data;
1121         struct tegra_tuning_data *tuning_data;
1122
1123         tuning_data = &tegra_host->tuning_data;
1124         tap_data = tuning_data->tap_data[0];
1125
1126         if (tap_data->abandon_full_win) {
1127                 if (tap_data->abandon_partial_win) {
1128                         tuning_data->best_tap_value = 0;
1129                         return;
1130                 } else {
1131                         tuning_data->select_partial_win = true;
1132                         goto calculate_best_tap;
1133                 }
1134         }
1135
1136         tap_data->tuning_ui = tap_data->full_win_end - tap_data->partial_win;
1137
1138         /* Calculate the sampling point */
1139         curr_clock = sdhci->max_clk / 1000000;
1140         max_clock = uhs_max_freq_MHz[sdhci->mmc->ios.timing];
1141         tap_data->sampling_point = ((tap_data->tuning_ui * curr_clock) /
1142                 max_clock);
1143         tap_data->sampling_point >>= 2;
1144
1145         /*
1146          * Check whether partial window should be used. Use partial window
1147          * if partial window > 0.22(UI).
1148          */
1149         if ((!tap_data->abandon_partial_win) &&
1150                 (tap_data->partial_win > ((22 * tap_data->tuning_ui) / 100)))
1151                         tuning_data->select_partial_win = true;
1152
1153 calculate_best_tap:
1154         if (tuning_data->select_partial_win) {
1155                 best_tap_value = (tap_data->partial_win -
1156                         (tap_data->full_win_end - tap_data->full_win_begin)) +
1157                         tap_data->sampling_point;
1158                 tuning_data->best_tap_value = (best_tap_value < 0) ? 0 :
1159                         best_tap_value;
1160         } else {
1161                 tuning_data->best_tap_value = tap_data->full_win_begin +
1162                         tap_data->sampling_point;
1163         }
1164 }
1165
1166 /*
1167  * Calculation of best tap value for high frequencies(156MHz).
1168  * Tap window data at 1.25V core voltage
1169  * X = Partial win, Y = Full win start, Z = Full win end.
1170  * Full Window = Z-Y.
1171  * UI = Z-X.
1172  * Tap_margin = (0.20375)UI
1173  *
1174  * Tap window data at 1.1V core voltage
1175  * X' = Partial win, Y' = Full win start, Z' = Full win end.
1176  * UI' = Z'-X'.
1177  * Full Window' = Z'-Y'.
1178  * Tap_margin' = (0.20375)UI'
1179  *
1180  * Full_window_tap=[(Z'-0.20375UI')+(Y+0.20375UI)]/2
1181  * Partial_window_tap=[(X'-0.20375UI')+(X-(Z-Y)+0x20375UI)]/2
1182  * if(Partial_window_tap < 0), Partial_window_tap=0
1183  *
1184  * Full_window_quality=[(Z'-0.20375UI')-(Y+0.20375UI)]/2
1185  * Partial_window_quality=(X'-0.20375UI')-Partial_window_tap
1186  * if(Full_window_quality>Partial_window_quality) choose full window,
1187  * else choose partial window.
1188  * If there is no margin window for both cases,
1189  * best tap=(Y+Z')/2.
1190  */
1191 static void calculate_high_freq_tap_value(struct sdhci_host *sdhci)
1192 {
1193         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1194         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1195         unsigned int curr_clock;
1196         unsigned int max_clock;
1197         struct tap_window_data *vmax_tap_data;
1198         struct tap_window_data *vmid_tap_data;
1199         struct tegra_tuning_data *tuning_data;
1200         unsigned int full_win_tap;
1201         int partial_win_start;
1202         int partial_win_tap;
1203         int full_win_quality;
1204         int partial_win_quality;
1205
1206         tuning_data = &tegra_host->tuning_data;
1207         vmax_tap_data = tuning_data->tap_data[0];
1208         vmid_tap_data = tuning_data->tap_data[1];
1209
1210         curr_clock = sdhci->max_clk / 1000000;
1211         max_clock = uhs_max_freq_MHz[sdhci->mmc->ios.timing];
1212
1213         /*
1214          * Calculate the tuning_ui and sampling points for tap windows found
1215          * at all core voltages.
1216          */
1217         vmax_tap_data->tuning_ui = vmax_tap_data->full_win_end -
1218                 vmax_tap_data->partial_win;
1219         vmax_tap_data->sampling_point =
1220                 (vmax_tap_data->tuning_ui * curr_clock) / max_clock;
1221         vmax_tap_data->sampling_point >>= 2;
1222
1223         vmid_tap_data->tuning_ui = vmid_tap_data->full_win_end -
1224                 vmid_tap_data->partial_win;
1225         vmid_tap_data->sampling_point =
1226                 (vmid_tap_data->tuning_ui * curr_clock) / max_clock;
1227         vmid_tap_data->sampling_point >>= 2;
1228
1229         full_win_tap = ((vmid_tap_data->full_win_end -
1230                 vmid_tap_data->sampling_point) +
1231                 (vmax_tap_data->full_win_begin +
1232                 vmax_tap_data->sampling_point));
1233         full_win_tap >>= 1;
1234         full_win_quality = (vmid_tap_data->full_win_end -
1235                 vmid_tap_data->sampling_point) -
1236                 (vmax_tap_data->full_win_begin +
1237                 vmax_tap_data->sampling_point);
1238         full_win_quality >>= 1;
1239
1240         partial_win_start = (vmax_tap_data->partial_win -
1241                 (vmax_tap_data->full_win_end -
1242                 vmax_tap_data->full_win_begin));
1243         partial_win_tap = ((vmid_tap_data->partial_win -
1244                 vmid_tap_data->sampling_point) +
1245                 (partial_win_start + vmax_tap_data->sampling_point)) / 2;
1246         if (partial_win_tap < 0)
1247                 partial_win_tap = 0;
1248         partial_win_quality = (vmid_tap_data->partial_win -
1249                 vmid_tap_data->sampling_point) - partial_win_tap;
1250
1251         if ((full_win_quality <= 0) && (partial_win_quality)) {
1252                 dev_warn(mmc_dev(sdhci->mmc),
1253                         "No margin window for both windows\n");
1254                 tuning_data->best_tap_value = vmax_tap_data->full_win_begin +
1255                         vmid_tap_data->full_win_end;
1256                 tuning_data->best_tap_value >>= 1;
1257         } else {
1258                 if (full_win_quality > partial_win_quality) {
1259                         tuning_data->best_tap_value = full_win_tap;
1260                 } else {
1261                         tuning_data->best_tap_value = partial_win_tap;
1262                         tuning_data->select_partial_win = true;
1263                 }
1264         }
1265 }
1266
1267 static int sdhci_tegra_run_frequency_tuning(struct sdhci_host *sdhci)
1268 {
1269         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1270         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1271         int err = 0;
1272         u8 ctrl;
1273         u32 mask;
1274         unsigned int timeout = 10;
1275         int flags;
1276         u32 intstatus;
1277
1278         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
1279         while (sdhci_readl(sdhci, SDHCI_PRESENT_STATE) & mask) {
1280                 if (timeout == 0) {
1281                         dev_err(mmc_dev(sdhci->mmc), "Controller never"
1282                                 "released inhibit bit(s).\n");
1283                         err = -ETIMEDOUT;
1284                         goto out;
1285                 }
1286                 timeout--;
1287                 mdelay(1);
1288         }
1289
1290         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1291         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1292         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1293
1294         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1295         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1296         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1297
1298         /*
1299          * In response to CMD19, the card sends 64 bytes of tuning
1300          * block to the Host Controller. So we set the block size
1301          * to 64 here.
1302          * In response to CMD21, the card sends 128 bytes of tuning
1303          * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
1304          * to the Host Controller. So we set the block size to 64 here.
1305          */
1306         sdhci_writew(sdhci, SDHCI_MAKE_BLKSZ(7, tegra_host->tuning_bsize),
1307                 SDHCI_BLOCK_SIZE);
1308
1309         sdhci_writeb(sdhci, 0xE, SDHCI_TIMEOUT_CONTROL);
1310
1311         sdhci_writeb(sdhci, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1312
1313         sdhci_writel(sdhci, 0x0, SDHCI_ARGUMENT);
1314
1315         /* Set the cmd flags */
1316         flags = SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_DATA;
1317         /* Issue the command */
1318         sdhci_writew(sdhci, SDHCI_MAKE_CMD(
1319                 tegra_host->tuning_opcode, flags), SDHCI_COMMAND);
1320
1321         timeout = 5;
1322         do {
1323                 timeout--;
1324                 mdelay(1);
1325                 intstatus = sdhci_readl(sdhci, SDHCI_INT_STATUS);
1326                 if (intstatus) {
1327                         sdhci_writel(sdhci, intstatus, SDHCI_INT_STATUS);
1328                         break;
1329                 }
1330         } while(timeout);
1331
1332         if ((intstatus & SDHCI_INT_DATA_AVAIL) &&
1333                 !(intstatus & SDHCI_INT_DATA_CRC)) {
1334                 err = 0;
1335                 sdhci->tuning_done = 1;
1336         } else {
1337                 tegra_sdhci_reset(sdhci, SDHCI_RESET_CMD);
1338                 tegra_sdhci_reset(sdhci, SDHCI_RESET_DATA);
1339                 err = -EIO;
1340         }
1341
1342         if (sdhci->tuning_done) {
1343                 sdhci->tuning_done = 0;
1344                 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1345                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING) &&
1346                         (ctrl & SDHCI_CTRL_TUNED_CLK))
1347                         err = 0;
1348                 else
1349                         err = -EIO;
1350         }
1351         mdelay(1);
1352 out:
1353         return err;
1354 }
1355
1356 static int sdhci_tegra_scan_tap_values(struct sdhci_host *sdhci,
1357         unsigned int starting_tap, bool expect_failure)
1358 {
1359         unsigned int tap_value = starting_tap;
1360         int err;
1361
1362         do {
1363                 /* Set the tap delay */
1364                 sdhci_tegra_set_tap_delay(sdhci, tap_value);
1365
1366                 /* Run frequency tuning */
1367                 err = sdhci_tegra_run_frequency_tuning(sdhci);
1368                 if ((expect_failure && !err) ||
1369                         (!expect_failure && err))
1370                         break;
1371                 tap_value++;
1372         } while (tap_value <= MAX_TAP_VALUES);
1373
1374         return tap_value;
1375 }
1376
1377 /*
1378  * While scanning for tap values, first get the partial window followed by the
1379  * full window. Note that, when scanning for full win start, tuning has to be
1380  * run until a passing tap value is found. Hence, failure is expected during
1381  * this process and ignored.
1382  */
1383 static int sdhci_tegra_get_tap_window_data(struct sdhci_host *sdhci,
1384         struct tap_window_data *tap_data)
1385 {
1386         unsigned int tap_value;
1387         int err = 0;
1388
1389         if (!tap_data) {
1390                 dev_err(mmc_dev(sdhci->mmc), "Invalid tap data\n");
1391                 return -ENODATA;
1392         }
1393
1394         /* Get the partial window data */
1395         tap_value = 0;
1396         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, false);
1397         if (!tap_value) {
1398                 tap_data->abandon_partial_win = true;
1399                 tap_data->partial_win = 0;
1400         } else if (tap_value > MAX_TAP_VALUES) {
1401                 /*
1402                  * If tap value is more than 0xFF, we have hit the miracle case
1403                  * of all tap values passing. Discard full window as passing
1404                  * window has covered all taps.
1405                  */
1406                 tap_data->partial_win = MAX_TAP_VALUES;
1407                 tap_data->abandon_full_win = true;
1408                 goto out;
1409         } else {
1410                 tap_data->partial_win = tap_value - 1;
1411                 if (tap_value == MAX_TAP_VALUES) {
1412                         /* All tap values exhausted. No full window */
1413                         tap_data->abandon_full_win = true;
1414                         goto out;
1415                 }
1416         }
1417
1418         /* Get the full window start */
1419         tap_value++;
1420         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, true);
1421         if (tap_value > MAX_TAP_VALUES) {
1422                 /* All tap values exhausted. No full window */
1423                 tap_data->abandon_full_win = true;
1424                 goto out;
1425         } else {
1426                 tap_data->full_win_begin = tap_value;
1427                 /*
1428                  * If full win start is 0xFF, then set that as full win end
1429                  * and exit.
1430                  */
1431                 if (tap_value == MAX_TAP_VALUES) {
1432                         tap_data->full_win_end = tap_value;
1433                         goto out;
1434                 }
1435         }
1436
1437         /* Get the full window end */
1438         tap_value++;
1439         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, false);
1440         tap_data->full_win_end = tap_value - 1;
1441         if (tap_value > MAX_TAP_VALUES)
1442                 tap_data->full_win_end = MAX_TAP_VALUES;
1443 out:
1444         /*
1445          * Mark tuning as failed if both partial and full windows are
1446          * abandoned.
1447          */
1448         if (tap_data->abandon_partial_win && tap_data->abandon_full_win)
1449                 err = -EIO;
1450         return err;
1451 }
1452
1453 static int sdhci_tegra_execute_tuning(struct sdhci_host *sdhci, u32 opcode)
1454 {
1455         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1456         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1457         struct tegra_tuning_data *tuning_data;
1458         struct tap_window_data *tap_data;
1459         int err;
1460         u16 ctrl_2;
1461         u32 ier;
1462         unsigned int freq_band;
1463         unsigned int i;
1464         unsigned int voltage;
1465
1466         /* Tuning is valid only in SDR104 and SDR50 modes */
1467         ctrl_2 = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
1468         if (!(((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1469                 (((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1470                 (sdhci->flags & SDHCI_SDR50_NEEDS_TUNING))))
1471                         return 0;
1472
1473         /* Tuning should be done only for MMC_BUS_WIDTH_8 and MMC_BUS_WIDTH_4 */
1474         if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1475                 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8;
1476         else if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1477                 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4;
1478         else
1479                 return -EINVAL;
1480
1481         /* Set the tuning command to be used */
1482         tegra_host->tuning_opcode = opcode;
1483
1484         /*
1485          * Disable all interrupts signalling.Enable interrupt status
1486          * detection for buffer read ready and data crc. We use
1487          * polling for tuning as it involves less overhead.
1488          */
1489         ier = sdhci_readl(sdhci, SDHCI_INT_ENABLE);
1490         sdhci_writel(sdhci, 0, SDHCI_SIGNAL_ENABLE);
1491         sdhci_writel(sdhci, SDHCI_INT_DATA_AVAIL |
1492                 SDHCI_INT_DATA_CRC, SDHCI_INT_ENABLE);
1493
1494         /*
1495          * If tuning is already done and retune request is not set, then skip
1496          * best tap value calculation and use the old best tap value.
1497          */
1498         if (tegra_host->tuning_status == TUNING_STATUS_DONE)
1499                 goto set_best_tap;
1500
1501         if (sdhci->max_clk > tuning_params[TUNING_LOW_FREQ].freq_hz)
1502                 freq_band = TUNING_HIGH_FREQ;
1503         else
1504                 freq_band = TUNING_LOW_FREQ;
1505
1506         /*
1507          * Run tuning and get the passing tap window info for all frequencies
1508          * and core voltages required to calculate the final tap value. The
1509          * standard driver calls this platform specific tuning callback after
1510          * holding a lock. The spinlock needs to be released when calling
1511          * non-atomic context functions like regulator calls etc.
1512          */
1513         tuning_data = &tegra_host->tuning_data;
1514         for (i = 0; i < tuning_params[freq_band].nr_voltages; i++) {
1515                 spin_unlock(&sdhci->lock);
1516                 if (!tuning_data->tap_data[i]) {
1517                         tuning_data->tap_data[i] = devm_kzalloc(
1518                                 mmc_dev(sdhci->mmc),
1519                                 sizeof(struct tap_window_data), GFP_KERNEL);
1520                         if (!tuning_data->tap_data[i]) {
1521                                 err = -ENOMEM;
1522                                 dev_err(mmc_dev(sdhci->mmc),
1523                                         "Insufficient memory for tap window info\n");
1524                                 spin_lock(&sdhci->lock);
1525                                 goto out;
1526                         }
1527                 }
1528                 tap_data = tuning_data->tap_data[i];
1529
1530                 if (tegra_host->nominal_vcore_uV) {
1531                         if (!tegra_host->vcore_reg)
1532                                 tegra_host->vcore_reg = regulator_get(
1533                                 mmc_dev(sdhci->mmc), "vdd_core");
1534                         if (IS_ERR_OR_NULL(tegra_host->vcore_reg)) {
1535                                 dev_info(mmc_dev(sdhci->mmc),
1536                                         "No vdd_core %ld. Tuning might fail.\n",
1537                                         PTR_ERR(tegra_host->vcore_reg));
1538                                 tegra_host->vcore_reg = NULL;
1539                         } else {
1540                                 voltage = tuning_params[freq_band].voltages[i];
1541                                 if (voltage > tegra_host->nominal_vcore_uV)
1542                                         voltage = tegra_host->nominal_vcore_uV;
1543                                 err = regulator_set_voltage(
1544                                         tegra_host->vcore_reg, voltage,
1545                                         voltage);
1546                                 if (err)
1547                                         dev_err(mmc_dev(sdhci->mmc),
1548                                                 "Setting nominal core voltage failed\n");
1549                         }
1550                 }
1551                 spin_lock(&sdhci->lock);
1552
1553                 /* Get the tuning window info */
1554                 err = sdhci_tegra_get_tap_window_data(sdhci, tap_data);
1555                 if (err) {
1556                         dev_err(mmc_dev(sdhci->mmc), "Failed to tuning window info\n");
1557                         goto out;
1558                 }
1559         }
1560
1561         /* Calculate best tap for current freq band */
1562         if (freq_band == TUNING_LOW_FREQ)
1563                 calculate_low_freq_tap_value(sdhci);
1564         else
1565                 calculate_high_freq_tap_value(sdhci);
1566
1567 set_best_tap:
1568         sdhci_tegra_set_tap_delay(sdhci,
1569                 tegra_host->tuning_data.best_tap_value);
1570
1571         /*
1572          * Run tuning with the best tap value. If tuning fails, set the status
1573          * for retuning next time enumeration is done.
1574          */
1575         err = sdhci_tegra_run_frequency_tuning(sdhci);
1576         if (err)
1577                 tegra_host->tuning_status = TUNING_STATUS_RETUNE;
1578         else
1579                 tegra_host->tuning_status = TUNING_STATUS_DONE;
1580
1581 out:
1582         /* Enable the full range for core voltage if vcore_reg exists */
1583         if (tegra_host->vcore_reg) {
1584                 spin_unlock(&sdhci->lock);
1585                 regulator_put(tegra_host->vcore_reg);
1586                 tegra_host->vcore_reg = NULL;
1587                 spin_lock(&sdhci->lock);
1588         }
1589
1590         /* Enable interrupts. Enable full range for core voltage */
1591         sdhci_writel(sdhci, ier, SDHCI_INT_ENABLE);
1592         sdhci_writel(sdhci, ier, SDHCI_SIGNAL_ENABLE);
1593         return err;
1594 }
1595
1596 static int tegra_sdhci_suspend(struct sdhci_host *sdhci)
1597 {
1598         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1599         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1600
1601         tegra_sdhci_set_clock(sdhci, 0);
1602
1603         /* Disable the power rails if any */
1604         if (tegra_host->card_present) {
1605                 if (tegra_host->is_rail_enabled) {
1606                         if (tegra_host->vdd_io_reg)
1607                                 regulator_disable(tegra_host->vdd_io_reg);
1608                         if (tegra_host->vdd_slot_reg)
1609                                 regulator_disable(tegra_host->vdd_slot_reg);
1610                         tegra_host->is_rail_enabled = 0;
1611                 }
1612         }
1613
1614         if (tegra_host->dpd) {
1615                 mutex_lock(&tegra_host->dpd->delay_lock);
1616                 tegra_host->dpd->need_delay_dpd = 1;
1617                 mutex_unlock(&tegra_host->dpd->delay_lock);
1618         }
1619
1620         return 0;
1621 }
1622
1623 static int tegra_sdhci_resume(struct sdhci_host *sdhci)
1624 {
1625         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1626         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1627         struct platform_device *pdev;
1628         struct tegra_sdhci_platform_data *plat;
1629
1630         pdev = to_platform_device(mmc_dev(sdhci->mmc));
1631         plat = pdev->dev.platform_data;
1632
1633         if (gpio_is_valid(plat->cd_gpio))
1634                 tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
1635
1636         /* Enable the power rails if any */
1637         if (tegra_host->card_present) {
1638                 if (!tegra_host->is_rail_enabled) {
1639                         if (tegra_host->vdd_slot_reg)
1640                                 regulator_enable(tegra_host->vdd_slot_reg);
1641                         if (tegra_host->vdd_io_reg) {
1642                                 regulator_enable(tegra_host->vdd_io_reg);
1643                                 if (plat->mmc_data.ocr_mask &
1644                                                         SDHOST_1V8_OCR_MASK)
1645                                         tegra_sdhci_signal_voltage_switch(sdhci,
1646                                                         MMC_SIGNAL_VOLTAGE_180);
1647                                 else
1648                                         tegra_sdhci_signal_voltage_switch(sdhci,
1649                                                         MMC_SIGNAL_VOLTAGE_330);
1650                         }
1651                         tegra_host->is_rail_enabled = 1;
1652                 }
1653         }
1654
1655         /* Setting the min identification clock of freq 400KHz */
1656         tegra_sdhci_set_clock(sdhci, 400000);
1657
1658         /* Reset the controller and power on if MMC_KEEP_POWER flag is set*/
1659         if (sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER) {
1660                 tegra_sdhci_reset(sdhci, SDHCI_RESET_ALL);
1661                 sdhci_writeb(sdhci, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1662                 sdhci->pwr = 0;
1663         }
1664
1665         return 0;
1666 }
1667
1668 static void tegra_sdhci_post_resume(struct sdhci_host *sdhci)
1669 {
1670         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1671         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1672
1673         if (tegra_host->card_present) {
1674                 if (tegra_host->sd_detect_in_suspend)
1675                         tasklet_schedule(&sdhci->card_tasklet);
1676         } else if (tegra_host->clk_enabled) {
1677                 /* Turn OFF the clocks if the card is not present */
1678                 tegra_sdhci_set_clock(sdhci, 0);
1679         }
1680 }
1681
1682 static void sdhci_tegra_error_stats_debugfs(struct sdhci_host *host)
1683 {
1684         struct dentry *root;
1685
1686         root = debugfs_create_dir(dev_name(mmc_dev(host->mmc)), NULL);
1687         if (IS_ERR(root))
1688                 /* Don't complain -- debugfs just isn't enabled */
1689                 return;
1690         if (!root)
1691                 /* Complain -- debugfs is enabled, but it failed to
1692                  * create the directory. */
1693                 goto err_root;
1694
1695         host->debugfs_root = root;
1696
1697         if (!debugfs_create_file("error_stats", S_IRUSR, root, host,
1698                                 &sdhci_host_fops))
1699                 goto err_node;
1700         return;
1701
1702 err_node:
1703         debugfs_remove_recursive(root);
1704         host->debugfs_root = NULL;
1705 err_root:
1706         pr_err("%s: Failed to initialize debugfs functionality\n", __func__);
1707         return;
1708 }
1709
1710 static struct sdhci_ops tegra_sdhci_ops = {
1711 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
1712         .get_ro     = tegra_sdhci_get_ro,
1713 #endif
1714         .get_cd     = tegra_sdhci_get_cd,
1715         .read_l     = tegra_sdhci_readl,
1716         .read_w     = tegra_sdhci_readw,
1717         .write_l    = tegra_sdhci_writel,
1718         .platform_8bit_width = tegra_sdhci_8bit,
1719         .set_clock              = tegra_sdhci_set_clock,
1720         .suspend                = tegra_sdhci_suspend,
1721         .resume                 = tegra_sdhci_resume,
1722         .platform_resume        = tegra_sdhci_post_resume,
1723         .platform_reset_exit    = tegra_sdhci_reset_exit,
1724         .set_uhs_signaling      = tegra_sdhci_set_uhs_signaling,
1725         .switch_signal_voltage  = tegra_sdhci_signal_voltage_switch,
1726         .switch_signal_voltage_exit = tegra_sdhci_do_calibration,
1727         .execute_freq_tuning    = sdhci_tegra_execute_tuning,
1728         .sd_error_stats         = sdhci_tegra_sd_error_stats,
1729 };
1730
1731 static struct sdhci_pltfm_data sdhci_tegra20_pdata = {
1732         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1733 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1734                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1735                   SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING |
1736                   SDHCI_QUIRK_NON_STANDARD_TUNING |
1737 #endif
1738 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1739                   SDHCI_QUIRK_NONSTANDARD_CLOCK |
1740 #endif
1741                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1742                   SDHCI_QUIRK_NO_HISPD_BIT |
1743                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1744                   SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1745                   SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO,
1746         .quirks2 = SDHCI_QUIRK2_BROKEN_PRESET_VALUES,
1747         .ops  = &tegra_sdhci_ops,
1748 };
1749
1750 static struct sdhci_tegra_soc_data soc_data_tegra20 = {
1751         .pdata = &sdhci_tegra20_pdata,
1752         .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1753 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
1754                     NVQUIRK_SET_DRIVE_STRENGTH |
1755 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
1756                     NVQUIRK_DISABLE_AUTO_CALIBRATION |
1757 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
1758                     NVQUIRK_SET_CALIBRATION_OFFSETS |
1759 #endif
1760                     NVQUIRK_ENABLE_BLOCK_GAP_DET,
1761 };
1762
1763 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1764 static struct sdhci_pltfm_data sdhci_tegra30_pdata = {
1765         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1766                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1767                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1768                   SDHCI_QUIRK_NO_HISPD_BIT |
1769                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
1770         .ops  = &tegra_sdhci_ops,
1771 };
1772
1773 static struct sdhci_tegra_soc_data soc_data_tegra30 = {
1774         .pdata = &sdhci_tegra30_pdata,
1775 };
1776 #endif
1777
1778 static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = {
1779 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1780         { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1781 #endif
1782 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1783         { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1784 #endif
1785         {}
1786 };
1787 MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
1788
1789 static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata(
1790                                                 struct platform_device *pdev)
1791 {
1792         struct tegra_sdhci_platform_data *plat;
1793         struct device_node *np = pdev->dev.of_node;
1794
1795         if (!np)
1796                 return NULL;
1797
1798         plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1799         if (!plat) {
1800                 dev_err(&pdev->dev, "Can't allocate platform data\n");
1801                 return NULL;
1802         }
1803
1804         plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1805         plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1806         plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
1807         if (of_find_property(np, "support-8bit", NULL))
1808                 plat->is_8bit = 1;
1809
1810         return plat;
1811 }
1812
1813 static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
1814 {
1815         const struct of_device_id *match;
1816         const struct sdhci_tegra_soc_data *soc_data;
1817         struct sdhci_host *host;
1818         struct sdhci_pltfm_host *pltfm_host;
1819         struct tegra_sdhci_platform_data *plat;
1820         struct sdhci_tegra *tegra_host;
1821         int rc;
1822
1823         match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
1824         if (match)
1825                 soc_data = match->data;
1826         else
1827                 soc_data = &soc_data_tegra20;
1828
1829         host = sdhci_pltfm_init(pdev, soc_data->pdata);
1830         if (IS_ERR(host))
1831                 return PTR_ERR(host);
1832
1833         pltfm_host = sdhci_priv(host);
1834
1835         plat = pdev->dev.platform_data;
1836
1837         if (plat == NULL)
1838                 plat = sdhci_tegra_dt_parse_pdata(pdev);
1839
1840         if (plat == NULL) {
1841                 dev_err(mmc_dev(host->mmc), "missing platform data\n");
1842                 rc = -ENXIO;
1843                 goto err_no_plat;
1844         }
1845
1846         tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
1847         if (!tegra_host) {
1848                 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
1849                 rc = -ENOMEM;
1850                 goto err_no_plat;
1851         }
1852
1853         tegra_host->plat = plat;
1854         tegra_host->sd_stat_head = NULL;
1855         tegra_host->soc_data = soc_data;
1856
1857         pltfm_host->priv = tegra_host;
1858
1859         pll_c = clk_get_sys(NULL, "pll_c");
1860         if (IS_ERR(pll_c)) {
1861                 rc = PTR_ERR(pll_c);
1862                 dev_err(mmc_dev(host->mmc),
1863                         "clk error in getting pll_c: %d\n", rc);
1864         }
1865
1866         pll_p = clk_get_sys(NULL, "pll_p");
1867         if (IS_ERR(pll_p)) {
1868                 rc = PTR_ERR(pll_p);
1869                 dev_err(mmc_dev(host->mmc),
1870                         "clk error in getting pll_p: %d\n", rc);
1871         }
1872
1873         pll_c_rate = clk_get_rate(pll_c);
1874         pll_p_rate = clk_get_rate(pll_p);
1875
1876 #ifdef CONFIG_MMC_EMBEDDED_SDIO
1877         if (plat->mmc_data.embedded_sdio)
1878                 mmc_set_embedded_sdio_data(host->mmc,
1879                         &plat->mmc_data.embedded_sdio->cis,
1880                         &plat->mmc_data.embedded_sdio->cccr,
1881                         plat->mmc_data.embedded_sdio->funcs,
1882                         plat->mmc_data.embedded_sdio->num_funcs);
1883 #endif
1884
1885         if (gpio_is_valid(plat->power_gpio)) {
1886                 rc = gpio_request(plat->power_gpio, "sdhci_power");
1887                 if (rc) {
1888                         dev_err(mmc_dev(host->mmc),
1889                                 "failed to allocate power gpio\n");
1890                         goto err_power_req;
1891                 }
1892                 gpio_direction_output(plat->power_gpio, 1);
1893         }
1894
1895         if (gpio_is_valid(plat->cd_gpio)) {
1896                 rc = gpio_request(plat->cd_gpio, "sdhci_cd");
1897                 if (rc) {
1898                         dev_err(mmc_dev(host->mmc),
1899                                 "failed to allocate cd gpio\n");
1900                         goto err_cd_req;
1901                 }
1902                 gpio_direction_input(plat->cd_gpio);
1903
1904                 tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0);
1905
1906                 rc = request_threaded_irq(gpio_to_irq(plat->cd_gpio), NULL,
1907                                  carddetect_irq,
1908                                  IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1909                                  mmc_hostname(host->mmc), host);
1910
1911                 if (rc) {
1912                         dev_err(mmc_dev(host->mmc), "request irq error\n");
1913                         goto err_cd_irq_req;
1914                 }
1915                 rc = enable_irq_wake(gpio_to_irq(plat->cd_gpio));
1916                 if (rc < 0)
1917                         dev_err(mmc_dev(host->mmc),
1918                                 "SD card wake-up event registration"
1919                                         "failed with eroor: %d\n", rc);
1920
1921         } else if (plat->mmc_data.register_status_notify) {
1922                 plat->mmc_data.register_status_notify(sdhci_status_notify_cb, host);
1923         }
1924
1925         if (plat->mmc_data.status) {
1926                 plat->mmc_data.card_present = plat->mmc_data.status(mmc_dev(host->mmc));
1927         }
1928
1929         if (gpio_is_valid(plat->wp_gpio)) {
1930                 rc = gpio_request(plat->wp_gpio, "sdhci_wp");
1931                 if (rc) {
1932                         dev_err(mmc_dev(host->mmc),
1933                                 "failed to allocate wp gpio\n");
1934                         goto err_wp_req;
1935                 }
1936                 gpio_direction_input(plat->wp_gpio);
1937         }
1938
1939         /*
1940          * If there is no card detect gpio, assume that the
1941          * card is always present.
1942          */
1943         if (!gpio_is_valid(plat->cd_gpio))
1944                 tegra_host->card_present = 1;
1945
1946         if (plat->mmc_data.ocr_mask & SDHOST_1V8_OCR_MASK) {
1947                 tegra_host->vddio_min_uv = SDHOST_LOW_VOLT_MIN;
1948                 tegra_host->vddio_max_uv = SDHOST_LOW_VOLT_MAX;
1949         } else if (plat->mmc_data.ocr_mask & MMC_OCR_2V8_MASK) {
1950                         tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_2V8;
1951                         tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
1952         } else {
1953                 /*
1954                  * Set the minV and maxV to default
1955                  * voltage range of 2.7V - 3.6V
1956                  */
1957                 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_MIN;
1958                 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
1959         }
1960
1961         tegra_host->vdd_io_reg = regulator_get(mmc_dev(host->mmc),
1962                                                         "vddio_sdmmc");
1963         if (IS_ERR_OR_NULL(tegra_host->vdd_io_reg)) {
1964                 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
1965                         "Assuming vddio_sdmmc is not required.\n",
1966                         "vddio_sdmmc", PTR_ERR(tegra_host->vdd_io_reg));
1967                 tegra_host->vdd_io_reg = NULL;
1968         } else {
1969                 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1970                         tegra_host->vddio_min_uv,
1971                         tegra_host->vddio_max_uv);
1972                 if (rc) {
1973                         dev_err(mmc_dev(host->mmc), "%s regulator_set_voltage failed: %d",
1974                                 "vddio_sdmmc", rc);
1975                         regulator_put(tegra_host->vdd_io_reg);
1976                         tegra_host->vdd_io_reg = NULL;
1977                 }
1978         }
1979
1980         tegra_host->vdd_slot_reg = regulator_get(mmc_dev(host->mmc),
1981                                                         "vddio_sd_slot");
1982         if (IS_ERR_OR_NULL(tegra_host->vdd_slot_reg)) {
1983                 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
1984                         " Assuming vddio_sd_slot is not required.\n",
1985                         "vddio_sd_slot", PTR_ERR(tegra_host->vdd_slot_reg));
1986                 tegra_host->vdd_slot_reg = NULL;
1987         }
1988
1989         if (tegra_host->card_present) {
1990                 if (tegra_host->vdd_slot_reg)
1991                         regulator_enable(tegra_host->vdd_slot_reg);
1992                 if (tegra_host->vdd_io_reg)
1993                         regulator_enable(tegra_host->vdd_io_reg);
1994                 tegra_host->is_rail_enabled = 1;
1995         }
1996
1997         pm_runtime_enable(&pdev->dev);
1998         pltfm_host->clk = clk_get(mmc_dev(host->mmc), NULL);
1999         if (IS_ERR(pltfm_host->clk)) {
2000                 dev_err(mmc_dev(host->mmc), "clk err\n");
2001                 rc = PTR_ERR(pltfm_host->clk);
2002                 goto err_clk_get;
2003         }
2004
2005         if (clk_get_parent(pltfm_host->clk) == pll_c)
2006                 tegra_host->is_parent_pllc = true;
2007
2008         pm_runtime_get_sync(&pdev->dev);
2009         rc = clk_prepare_enable(pltfm_host->clk);
2010         if (rc != 0)
2011                 goto err_clk_put;
2012
2013         if (!strcmp(dev_name(mmc_dev(host->mmc)), "sdhci-tegra.3")) {
2014                 tegra_host->emc_clk = clk_get(mmc_dev(host->mmc), "emc");
2015                 if (IS_ERR(tegra_host->emc_clk)) {
2016                         dev_err(mmc_dev(host->mmc), "clk err\n");
2017                         rc = PTR_ERR(tegra_host->emc_clk);
2018                         goto err_clk_put;
2019                 }
2020                 tegra_host->emc_max_clk =
2021                         clk_round_rate(tegra_host->emc_clk, ULONG_MAX);
2022         }
2023
2024         pltfm_host->priv = tegra_host;
2025         tegra_host->clk_enabled = true;
2026         tegra_host->max_clk_limit = plat->max_clk_limit;
2027         tegra_host->ddr_clk_limit = plat->ddr_clk_limit;
2028         tegra_host->sd_detect_in_suspend = plat->sd_detect_in_suspend;
2029         tegra_host->instance = pdev->id;
2030         tegra_host->dpd = tegra_io_dpd_get(mmc_dev(host->mmc));
2031
2032         host->mmc->pm_caps |= plat->pm_caps;
2033         host->mmc->pm_flags |= plat->pm_flags;
2034
2035         host->mmc->caps |= MMC_CAP_ERASE;
2036         /* enable 1/8V DDR capable */
2037         host->mmc->caps |= MMC_CAP_1_8V_DDR;
2038         if (plat->is_8bit)
2039                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
2040         host->mmc->caps |= MMC_CAP_SDIO_IRQ;
2041         host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_IGNORE_PM_NOTIFY;
2042         if (plat->mmc_data.built_in) {
2043                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
2044         }
2045         host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY;
2046
2047 #ifdef CONFIG_MMC_BKOPS
2048         host->mmc->caps2 |= MMC_CAP2_BKOPS;
2049 #endif
2050
2051         tegra_sdhost_min_freq = TEGRA_SDHOST_MIN_FREQ;
2052 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
2053         tegra_host->hw_ops = &tegra_2x_sdhci_ops;
2054         tegra_sdhost_std_freq = TEGRA2_SDHOST_STD_FREQ;
2055 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
2056         tegra_host->hw_ops = &tegra_3x_sdhci_ops;
2057         tegra_sdhost_std_freq = TEGRA3_SDHOST_STD_FREQ;
2058 #else
2059         tegra_host->hw_ops = &tegra_11x_sdhci_ops;
2060         tegra_sdhost_std_freq = TEGRA3_SDHOST_STD_FREQ;
2061 #endif
2062
2063         if (plat->nominal_vcore_uV)
2064                 tegra_host->nominal_vcore_uV = plat->nominal_vcore_uV;
2065
2066         rc = sdhci_add_host(host);
2067
2068         sdhci_tegra_error_stats_debugfs(host);
2069         if (rc)
2070                 goto err_add_host;
2071
2072         /* Enable async suspend/resume to reduce LP0 latency */
2073         device_enable_async_suspend(&pdev->dev);
2074
2075         return 0;
2076
2077 err_add_host:
2078         clk_put(tegra_host->emc_clk);
2079         clk_disable_unprepare(pltfm_host->clk);
2080         pm_runtime_put_sync(&pdev->dev);
2081 err_clk_put:
2082         clk_put(pltfm_host->clk);
2083 err_clk_get:
2084         if (gpio_is_valid(plat->wp_gpio))
2085                 gpio_free(plat->wp_gpio);
2086 err_wp_req:
2087         if (gpio_is_valid(plat->cd_gpio))
2088                 free_irq(gpio_to_irq(plat->cd_gpio), host);
2089 err_cd_irq_req:
2090         if (gpio_is_valid(plat->cd_gpio))
2091                 gpio_free(plat->cd_gpio);
2092 err_cd_req:
2093         if (gpio_is_valid(plat->power_gpio))
2094                 gpio_free(plat->power_gpio);
2095 err_power_req:
2096 err_no_plat:
2097         sdhci_pltfm_free(pdev);
2098         return rc;
2099 }
2100
2101 static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
2102 {
2103         struct sdhci_host *host = platform_get_drvdata(pdev);
2104         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2105         struct sdhci_tegra *tegra_host = pltfm_host->priv;
2106         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
2107         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
2108
2109         sdhci_remove_host(host, dead);
2110
2111         disable_irq_wake(gpio_to_irq(plat->cd_gpio));
2112
2113         if (tegra_host->vdd_slot_reg) {
2114                 regulator_disable(tegra_host->vdd_slot_reg);
2115                 regulator_put(tegra_host->vdd_slot_reg);
2116         }
2117
2118         if (tegra_host->vdd_io_reg) {
2119                 regulator_disable(tegra_host->vdd_io_reg);
2120                 regulator_put(tegra_host->vdd_io_reg);
2121         }
2122
2123         if (gpio_is_valid(plat->wp_gpio))
2124                 gpio_free(plat->wp_gpio);
2125
2126         if (gpio_is_valid(plat->cd_gpio)) {
2127                 free_irq(gpio_to_irq(plat->cd_gpio), host);
2128                 gpio_free(plat->cd_gpio);
2129         }
2130
2131         if (gpio_is_valid(plat->power_gpio))
2132                 gpio_free(plat->power_gpio);
2133
2134         if (tegra_host->clk_enabled) {
2135                 clk_disable_unprepare(pltfm_host->clk);
2136                 pm_runtime_put_sync(&pdev->dev);
2137         }
2138         clk_put(pltfm_host->clk);
2139
2140         sdhci_pltfm_free(pdev);
2141
2142         return 0;
2143 }
2144
2145 static struct platform_driver sdhci_tegra_driver = {
2146         .driver         = {
2147                 .name   = "sdhci-tegra",
2148                 .owner  = THIS_MODULE,
2149                 .of_match_table = sdhci_tegra_dt_match,
2150                 .pm     = SDHCI_PLTFM_PMOPS,
2151         },
2152         .probe          = sdhci_tegra_probe,
2153         .remove         = __devexit_p(sdhci_tegra_remove),
2154 };
2155
2156 module_platform_driver(sdhci_tegra_driver);
2157
2158 MODULE_DESCRIPTION("SDHCI driver for Tegra");
2159 MODULE_AUTHOR("Google, Inc.");
2160 MODULE_LICENSE("GPL v2");