b0c69104c863d2ef38aa643c7d53ad2c7c1d052a
[linux-2.6.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2  * drivers/mmc/host/omap_hsmmc.c
3  *
4  * Driver for OMAP2430/3430 MMC controller.
5  *
6  * Copyright (C) 2007 Texas Instruments.
7  *
8  * Authors:
9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
10  *      Madhusudhan             <madhu.cr@ti.com>
11  *      Mohit Jalori            <mjalori@ti.com>
12  *
13  * This file is licensed under the terms of the GNU General Public License
14  * version 2. This program is licensed "as is" without any warranty of any
15  * kind, whether express or implied.
16  */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/io.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <plat/dma.h>
37 #include <mach/hardware.h>
38 #include <plat/board.h>
39 #include <plat/mmc.h>
40 #include <plat/cpu.h>
41
42 /* OMAP HSMMC Host Controller Registers */
43 #define OMAP_HSMMC_SYSCONFIG    0x0010
44 #define OMAP_HSMMC_SYSSTATUS    0x0014
45 #define OMAP_HSMMC_CON          0x002C
46 #define OMAP_HSMMC_BLK          0x0104
47 #define OMAP_HSMMC_ARG          0x0108
48 #define OMAP_HSMMC_CMD          0x010C
49 #define OMAP_HSMMC_RSP10        0x0110
50 #define OMAP_HSMMC_RSP32        0x0114
51 #define OMAP_HSMMC_RSP54        0x0118
52 #define OMAP_HSMMC_RSP76        0x011C
53 #define OMAP_HSMMC_DATA         0x0120
54 #define OMAP_HSMMC_HCTL         0x0128
55 #define OMAP_HSMMC_SYSCTL       0x012C
56 #define OMAP_HSMMC_STAT         0x0130
57 #define OMAP_HSMMC_IE           0x0134
58 #define OMAP_HSMMC_ISE          0x0138
59 #define OMAP_HSMMC_CAPA         0x0140
60
61 #define VS18                    (1 << 26)
62 #define VS30                    (1 << 25)
63 #define SDVS18                  (0x5 << 9)
64 #define SDVS30                  (0x6 << 9)
65 #define SDVS33                  (0x7 << 9)
66 #define SDVS_MASK               0x00000E00
67 #define SDVSCLR                 0xFFFFF1FF
68 #define SDVSDET                 0x00000400
69 #define AUTOIDLE                0x1
70 #define SDBP                    (1 << 8)
71 #define DTO                     0xe
72 #define ICE                     0x1
73 #define ICS                     0x2
74 #define CEN                     (1 << 2)
75 #define CLKD_MASK               0x0000FFC0
76 #define CLKD_SHIFT              6
77 #define DTO_MASK                0x000F0000
78 #define DTO_SHIFT               16
79 #define INT_EN_MASK             0x307F0033
80 #define BWR_ENABLE              (1 << 4)
81 #define BRR_ENABLE              (1 << 5)
82 #define DTO_ENABLE              (1 << 20)
83 #define INIT_STREAM             (1 << 1)
84 #define DP_SELECT               (1 << 21)
85 #define DDIR                    (1 << 4)
86 #define DMA_EN                  0x1
87 #define MSBS                    (1 << 5)
88 #define BCE                     (1 << 1)
89 #define FOUR_BIT                (1 << 1)
90 #define DW8                     (1 << 5)
91 #define CC                      0x1
92 #define TC                      0x02
93 #define OD                      0x1
94 #define ERR                     (1 << 15)
95 #define CMD_TIMEOUT             (1 << 16)
96 #define DATA_TIMEOUT            (1 << 20)
97 #define CMD_CRC                 (1 << 17)
98 #define DATA_CRC                (1 << 21)
99 #define CARD_ERR                (1 << 28)
100 #define STAT_CLEAR              0xFFFFFFFF
101 #define INIT_STREAM_CMD         0x00000000
102 #define DUAL_VOLT_OCR_BIT       7
103 #define SRC                     (1 << 25)
104 #define SRD                     (1 << 26)
105 #define SOFTRESET               (1 << 1)
106 #define RESETDONE               (1 << 0)
107
108 /*
109  * FIXME: Most likely all the data using these _DEVID defines should come
110  * from the platform_data, or implemented in controller and slot specific
111  * functions.
112  */
113 #define OMAP_MMC1_DEVID         0
114 #define OMAP_MMC2_DEVID         1
115 #define OMAP_MMC3_DEVID         2
116 #define OMAP_MMC4_DEVID         3
117 #define OMAP_MMC5_DEVID         4
118
119 #define MMC_TIMEOUT_MS          20
120 #define OMAP_MMC_MASTER_CLOCK   96000000
121 #define DRIVER_NAME             "omap_hsmmc"
122
123 /* Timeouts for entering power saving states on inactivity, msec */
124 #define OMAP_MMC_DISABLED_TIMEOUT       100
125 #define OMAP_MMC_SLEEP_TIMEOUT          1000
126 #define OMAP_MMC_OFF_TIMEOUT            8000
127
128 /*
129  * One controller can have multiple slots, like on some omap boards using
130  * omap.c controller driver. Luckily this is not currently done on any known
131  * omap_hsmmc.c device.
132  */
133 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
134
135 /*
136  * MMC Host controller read/write API's
137  */
138 #define OMAP_HSMMC_READ(base, reg)      \
139         __raw_readl((base) + OMAP_HSMMC_##reg)
140
141 #define OMAP_HSMMC_WRITE(base, reg, val) \
142         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
144 struct omap_hsmmc_next {
145         unsigned int    dma_len;
146         s32             cookie;
147 };
148
149 struct omap_hsmmc_host {
150         struct  device          *dev;
151         struct  mmc_host        *mmc;
152         struct  mmc_request     *mrq;
153         struct  mmc_command     *cmd;
154         struct  mmc_data        *data;
155         struct  clk             *fclk;
156         struct  clk             *iclk;
157         struct  clk             *dbclk;
158         /*
159          * vcc == configured supply
160          * vcc_aux == optional
161          *   -  MMC1, supply for DAT4..DAT7
162          *   -  MMC2/MMC2, external level shifter voltage supply, for
163          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
164          */
165         struct  regulator       *vcc;
166         struct  regulator       *vcc_aux;
167         struct  work_struct     mmc_carddetect_work;
168         void    __iomem         *base;
169         resource_size_t         mapbase;
170         spinlock_t              irq_lock; /* Prevent races with irq handler */
171         unsigned int            id;
172         unsigned int            dma_len;
173         unsigned int            dma_sg_idx;
174         unsigned char           bus_mode;
175         unsigned char           power_mode;
176         u32                     *buffer;
177         u32                     bytesleft;
178         int                     suspended;
179         int                     irq;
180         int                     use_dma, dma_ch;
181         int                     dma_line_tx, dma_line_rx;
182         int                     slot_id;
183         int                     got_dbclk;
184         int                     response_busy;
185         int                     context_loss;
186         int                     dpm_state;
187         int                     vdd;
188         int                     protect_card;
189         int                     reqs_blocked;
190         int                     use_reg;
191         int                     req_in_progress;
192         struct omap_hsmmc_next  next_data;
193
194         struct  omap_mmc_platform_data  *pdata;
195 };
196
197 static int omap_hsmmc_card_detect(struct device *dev, int slot)
198 {
199         struct omap_mmc_platform_data *mmc = dev->platform_data;
200
201         /* NOTE: assumes card detect signal is active-low */
202         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
203 }
204
205 static int omap_hsmmc_get_wp(struct device *dev, int slot)
206 {
207         struct omap_mmc_platform_data *mmc = dev->platform_data;
208
209         /* NOTE: assumes write protect signal is active-high */
210         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
211 }
212
213 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
214 {
215         struct omap_mmc_platform_data *mmc = dev->platform_data;
216
217         /* NOTE: assumes card detect signal is active-low */
218         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
219 }
220
221 #ifdef CONFIG_PM
222
223 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
224 {
225         struct omap_mmc_platform_data *mmc = dev->platform_data;
226
227         disable_irq(mmc->slots[0].card_detect_irq);
228         return 0;
229 }
230
231 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
232 {
233         struct omap_mmc_platform_data *mmc = dev->platform_data;
234
235         enable_irq(mmc->slots[0].card_detect_irq);
236         return 0;
237 }
238
239 #else
240
241 #define omap_hsmmc_suspend_cdirq        NULL
242 #define omap_hsmmc_resume_cdirq         NULL
243
244 #endif
245
246 #ifdef CONFIG_REGULATOR
247
248 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
249                                   int vdd)
250 {
251         struct omap_hsmmc_host *host =
252                 platform_get_drvdata(to_platform_device(dev));
253         int ret;
254
255         if (mmc_slot(host).before_set_reg)
256                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
257
258         if (power_on)
259                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
260         else
261                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
262
263         if (mmc_slot(host).after_set_reg)
264                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
265
266         return ret;
267 }
268
269 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
270                                    int vdd)
271 {
272         struct omap_hsmmc_host *host =
273                 platform_get_drvdata(to_platform_device(dev));
274         int ret = 0;
275
276         /*
277          * If we don't see a Vcc regulator, assume it's a fixed
278          * voltage always-on regulator.
279          */
280         if (!host->vcc)
281                 return 0;
282
283         if (mmc_slot(host).before_set_reg)
284                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
285
286         /*
287          * Assume Vcc regulator is used only to power the card ... OMAP
288          * VDDS is used to power the pins, optionally with a transceiver to
289          * support cards using voltages other than VDDS (1.8V nominal).  When a
290          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
291          *
292          * In some cases this regulator won't support enable/disable;
293          * e.g. it's a fixed rail for a WLAN chip.
294          *
295          * In other cases vcc_aux switches interface power.  Example, for
296          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
297          * chips/cards need an interface voltage rail too.
298          */
299         if (power_on) {
300                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
301                 /* Enable interface voltage rail, if needed */
302                 if (ret == 0 && host->vcc_aux) {
303                         ret = regulator_enable(host->vcc_aux);
304                         if (ret < 0)
305                                 ret = mmc_regulator_set_ocr(host->mmc,
306                                                         host->vcc, 0);
307                 }
308         } else {
309                 /* Shut down the rail */
310                 if (host->vcc_aux)
311                         ret = regulator_disable(host->vcc_aux);
312                 if (!ret) {
313                         /* Then proceed to shut down the local regulator */
314                         ret = mmc_regulator_set_ocr(host->mmc,
315                                                 host->vcc, 0);
316                 }
317         }
318
319         if (mmc_slot(host).after_set_reg)
320                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
321
322         return ret;
323 }
324
325 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
326                                         int vdd)
327 {
328         return 0;
329 }
330
331 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
332                                   int vdd, int cardsleep)
333 {
334         struct omap_hsmmc_host *host =
335                 platform_get_drvdata(to_platform_device(dev));
336         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
337
338         return regulator_set_mode(host->vcc, mode);
339 }
340
341 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
342                                    int vdd, int cardsleep)
343 {
344         struct omap_hsmmc_host *host =
345                 platform_get_drvdata(to_platform_device(dev));
346         int err, mode;
347
348         /*
349          * If we don't see a Vcc regulator, assume it's a fixed
350          * voltage always-on regulator.
351          */
352         if (!host->vcc)
353                 return 0;
354
355         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
356
357         if (!host->vcc_aux)
358                 return regulator_set_mode(host->vcc, mode);
359
360         if (cardsleep) {
361                 /* VCC can be turned off if card is asleep */
362                 if (sleep)
363                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
364                 else
365                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
366         } else
367                 err = regulator_set_mode(host->vcc, mode);
368         if (err)
369                 return err;
370
371         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
372                 return regulator_set_mode(host->vcc_aux, mode);
373
374         if (sleep)
375                 return regulator_disable(host->vcc_aux);
376         else
377                 return regulator_enable(host->vcc_aux);
378 }
379
380 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
381                                         int vdd, int cardsleep)
382 {
383         return 0;
384 }
385
386 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
387 {
388         struct regulator *reg;
389         int ret = 0;
390         int ocr_value = 0;
391
392         switch (host->id) {
393         case OMAP_MMC1_DEVID:
394                 /* On-chip level shifting via PBIAS0/PBIAS1 */
395                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
396                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
397                 break;
398         case OMAP_MMC2_DEVID:
399         case OMAP_MMC3_DEVID:
400         case OMAP_MMC5_DEVID:
401                 /* Off-chip level shifting, or none */
402                 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
403                 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
404                 break;
405         case OMAP_MMC4_DEVID:
406                 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
407                 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
408         default:
409                 pr_err("MMC%d configuration not supported!\n", host->id);
410                 return -EINVAL;
411         }
412
413         reg = regulator_get(host->dev, "vmmc");
414         if (IS_ERR(reg)) {
415                 dev_dbg(host->dev, "vmmc regulator missing\n");
416                 /*
417                 * HACK: until fixed.c regulator is usable,
418                 * we don't require a main regulator
419                 * for MMC2 or MMC3
420                 */
421                 if (host->id == OMAP_MMC1_DEVID) {
422                         ret = PTR_ERR(reg);
423                         goto err;
424                 }
425         } else {
426                 host->vcc = reg;
427                 ocr_value = mmc_regulator_get_ocrmask(reg);
428                 if (!mmc_slot(host).ocr_mask) {
429                         mmc_slot(host).ocr_mask = ocr_value;
430                 } else {
431                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
432                                 pr_err("MMC%d ocrmask %x is not supported\n",
433                                         host->id, mmc_slot(host).ocr_mask);
434                                 mmc_slot(host).ocr_mask = 0;
435                                 return -EINVAL;
436                         }
437                 }
438
439                 /* Allow an aux regulator */
440                 reg = regulator_get(host->dev, "vmmc_aux");
441                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
442
443                 /* For eMMC do not power off when not in sleep state */
444                 if (mmc_slot(host).no_regulator_off_init)
445                         return 0;
446                 /*
447                 * UGLY HACK:  workaround regulator framework bugs.
448                 * When the bootloader leaves a supply active, it's
449                 * initialized with zero usecount ... and we can't
450                 * disable it without first enabling it.  Until the
451                 * framework is fixed, we need a workaround like this
452                 * (which is safe for MMC, but not in general).
453                 */
454                 if (regulator_is_enabled(host->vcc) > 0) {
455                         regulator_enable(host->vcc);
456                         regulator_disable(host->vcc);
457                 }
458                 if (host->vcc_aux) {
459                         if (regulator_is_enabled(reg) > 0) {
460                                 regulator_enable(reg);
461                                 regulator_disable(reg);
462                         }
463                 }
464         }
465
466         return 0;
467
468 err:
469         mmc_slot(host).set_power = NULL;
470         mmc_slot(host).set_sleep = NULL;
471         return ret;
472 }
473
474 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
475 {
476         regulator_put(host->vcc);
477         regulator_put(host->vcc_aux);
478         mmc_slot(host).set_power = NULL;
479         mmc_slot(host).set_sleep = NULL;
480 }
481
482 static inline int omap_hsmmc_have_reg(void)
483 {
484         return 1;
485 }
486
487 #else
488
489 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
490 {
491         return -EINVAL;
492 }
493
494 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
495 {
496 }
497
498 static inline int omap_hsmmc_have_reg(void)
499 {
500         return 0;
501 }
502
503 #endif
504
505 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
506 {
507         int ret;
508
509         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
510                 if (pdata->slots[0].cover)
511                         pdata->slots[0].get_cover_state =
512                                         omap_hsmmc_get_cover_state;
513                 else
514                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
515                 pdata->slots[0].card_detect_irq =
516                                 gpio_to_irq(pdata->slots[0].switch_pin);
517                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
518                 if (ret)
519                         return ret;
520                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
521                 if (ret)
522                         goto err_free_sp;
523         } else
524                 pdata->slots[0].switch_pin = -EINVAL;
525
526         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
527                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
528                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
529                 if (ret)
530                         goto err_free_cd;
531                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
532                 if (ret)
533                         goto err_free_wp;
534         } else
535                 pdata->slots[0].gpio_wp = -EINVAL;
536
537         return 0;
538
539 err_free_wp:
540         gpio_free(pdata->slots[0].gpio_wp);
541 err_free_cd:
542         if (gpio_is_valid(pdata->slots[0].switch_pin))
543 err_free_sp:
544                 gpio_free(pdata->slots[0].switch_pin);
545         return ret;
546 }
547
548 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
549 {
550         if (gpio_is_valid(pdata->slots[0].gpio_wp))
551                 gpio_free(pdata->slots[0].gpio_wp);
552         if (gpio_is_valid(pdata->slots[0].switch_pin))
553                 gpio_free(pdata->slots[0].switch_pin);
554 }
555
556 /*
557  * Stop clock to the card
558  */
559 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
560 {
561         OMAP_HSMMC_WRITE(host->base, SYSCTL,
562                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
563         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
564                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
565 }
566
567 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
568                                   struct mmc_command *cmd)
569 {
570         unsigned int irq_mask;
571
572         if (host->use_dma)
573                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
574         else
575                 irq_mask = INT_EN_MASK;
576
577         /* Disable timeout for erases */
578         if (cmd->opcode == MMC_ERASE)
579                 irq_mask &= ~DTO_ENABLE;
580
581         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
582         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
583         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
584 }
585
586 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
587 {
588         OMAP_HSMMC_WRITE(host->base, ISE, 0);
589         OMAP_HSMMC_WRITE(host->base, IE, 0);
590         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
591 }
592
593 #ifdef CONFIG_PM
594
595 /*
596  * Restore the MMC host context, if it was lost as result of a
597  * power state change.
598  */
599 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
600 {
601         struct mmc_ios *ios = &host->mmc->ios;
602         struct omap_mmc_platform_data *pdata = host->pdata;
603         int context_loss = 0;
604         u32 hctl, capa, con;
605         u16 dsor = 0;
606         unsigned long timeout;
607
608         if (pdata->get_context_loss_count) {
609                 context_loss = pdata->get_context_loss_count(host->dev);
610                 if (context_loss < 0)
611                         return 1;
612         }
613
614         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
615                 context_loss == host->context_loss ? "not " : "");
616         if (host->context_loss == context_loss)
617                 return 1;
618
619         /* Wait for hardware reset */
620         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
621         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
622                 && time_before(jiffies, timeout))
623                 ;
624
625         /* Do software reset */
626         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
627         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
628         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
629                 && time_before(jiffies, timeout))
630                 ;
631
632         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
633                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
634
635         if (host->id == OMAP_MMC1_DEVID) {
636                 if (host->power_mode != MMC_POWER_OFF &&
637                     (1 << ios->vdd) <= MMC_VDD_23_24)
638                         hctl = SDVS18;
639                 else
640                         hctl = SDVS30;
641                 capa = VS30 | VS18;
642         } else {
643                 hctl = SDVS18;
644                 capa = VS18;
645         }
646
647         OMAP_HSMMC_WRITE(host->base, HCTL,
648                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
649
650         OMAP_HSMMC_WRITE(host->base, CAPA,
651                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
652
653         OMAP_HSMMC_WRITE(host->base, HCTL,
654                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
655
656         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
657         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
658                 && time_before(jiffies, timeout))
659                 ;
660
661         omap_hsmmc_disable_irq(host);
662
663         /* Do not initialize card-specific things if the power is off */
664         if (host->power_mode == MMC_POWER_OFF)
665                 goto out;
666
667         con = OMAP_HSMMC_READ(host->base, CON);
668         switch (ios->bus_width) {
669         case MMC_BUS_WIDTH_8:
670                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
671                 break;
672         case MMC_BUS_WIDTH_4:
673                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
674                 OMAP_HSMMC_WRITE(host->base, HCTL,
675                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
676                 break;
677         case MMC_BUS_WIDTH_1:
678                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
679                 OMAP_HSMMC_WRITE(host->base, HCTL,
680                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
681                 break;
682         }
683
684         if (ios->clock) {
685                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
686                 if (dsor < 1)
687                         dsor = 1;
688
689                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
690                         dsor++;
691
692                 if (dsor > 250)
693                         dsor = 250;
694         }
695
696         OMAP_HSMMC_WRITE(host->base, SYSCTL,
697                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
698         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
699         OMAP_HSMMC_WRITE(host->base, SYSCTL,
700                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
701
702         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
703         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
704                 && time_before(jiffies, timeout))
705                 ;
706
707         OMAP_HSMMC_WRITE(host->base, SYSCTL,
708                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
709
710         con = OMAP_HSMMC_READ(host->base, CON);
711         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
712                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
713         else
714                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
715 out:
716         host->context_loss = context_loss;
717
718         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
719         return 0;
720 }
721
722 /*
723  * Save the MMC host context (store the number of power state changes so far).
724  */
725 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
726 {
727         struct omap_mmc_platform_data *pdata = host->pdata;
728         int context_loss;
729
730         if (pdata->get_context_loss_count) {
731                 context_loss = pdata->get_context_loss_count(host->dev);
732                 if (context_loss < 0)
733                         return;
734                 host->context_loss = context_loss;
735         }
736 }
737
738 #else
739
740 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
741 {
742         return 0;
743 }
744
745 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
746 {
747 }
748
749 #endif
750
751 /*
752  * Send init stream sequence to card
753  * before sending IDLE command
754  */
755 static void send_init_stream(struct omap_hsmmc_host *host)
756 {
757         int reg = 0;
758         unsigned long timeout;
759
760         if (host->protect_card)
761                 return;
762
763         disable_irq(host->irq);
764
765         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
766         OMAP_HSMMC_WRITE(host->base, CON,
767                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
768         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
769
770         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
771         while ((reg != CC) && time_before(jiffies, timeout))
772                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
773
774         OMAP_HSMMC_WRITE(host->base, CON,
775                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
776
777         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
778         OMAP_HSMMC_READ(host->base, STAT);
779
780         enable_irq(host->irq);
781 }
782
783 static inline
784 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
785 {
786         int r = 1;
787
788         if (mmc_slot(host).get_cover_state)
789                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
790         return r;
791 }
792
793 static ssize_t
794 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
795                            char *buf)
796 {
797         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
798         struct omap_hsmmc_host *host = mmc_priv(mmc);
799
800         return sprintf(buf, "%s\n",
801                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
802 }
803
804 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
805
806 static ssize_t
807 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
808                         char *buf)
809 {
810         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
811         struct omap_hsmmc_host *host = mmc_priv(mmc);
812
813         return sprintf(buf, "%s\n", mmc_slot(host).name);
814 }
815
816 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
817
818 /*
819  * Configure the response type and send the cmd.
820  */
821 static void
822 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
823         struct mmc_data *data)
824 {
825         int cmdreg = 0, resptype = 0, cmdtype = 0;
826
827         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
828                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
829         host->cmd = cmd;
830
831         omap_hsmmc_enable_irq(host, cmd);
832
833         host->response_busy = 0;
834         if (cmd->flags & MMC_RSP_PRESENT) {
835                 if (cmd->flags & MMC_RSP_136)
836                         resptype = 1;
837                 else if (cmd->flags & MMC_RSP_BUSY) {
838                         resptype = 3;
839                         host->response_busy = 1;
840                 } else
841                         resptype = 2;
842         }
843
844         /*
845          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
846          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
847          * a val of 0x3, rest 0x0.
848          */
849         if (cmd == host->mrq->stop)
850                 cmdtype = 0x3;
851
852         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
853
854         if (data) {
855                 cmdreg |= DP_SELECT | MSBS | BCE;
856                 if (data->flags & MMC_DATA_READ)
857                         cmdreg |= DDIR;
858                 else
859                         cmdreg &= ~(DDIR);
860         }
861
862         if (host->use_dma)
863                 cmdreg |= DMA_EN;
864
865         host->req_in_progress = 1;
866
867         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
868         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
869 }
870
871 static int
872 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
873 {
874         if (data->flags & MMC_DATA_WRITE)
875                 return DMA_TO_DEVICE;
876         else
877                 return DMA_FROM_DEVICE;
878 }
879
880 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
881 {
882         int dma_ch;
883
884         spin_lock(&host->irq_lock);
885         host->req_in_progress = 0;
886         dma_ch = host->dma_ch;
887         spin_unlock(&host->irq_lock);
888
889         omap_hsmmc_disable_irq(host);
890         /* Do not complete the request if DMA is still in progress */
891         if (mrq->data && host->use_dma && dma_ch != -1)
892                 return;
893         host->mrq = NULL;
894         mmc_request_done(host->mmc, mrq);
895 }
896
897 /*
898  * Notify the transfer complete to MMC core
899  */
900 static void
901 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
902 {
903         if (!data) {
904                 struct mmc_request *mrq = host->mrq;
905
906                 /* TC before CC from CMD6 - don't know why, but it happens */
907                 if (host->cmd && host->cmd->opcode == 6 &&
908                     host->response_busy) {
909                         host->response_busy = 0;
910                         return;
911                 }
912
913                 omap_hsmmc_request_done(host, mrq);
914                 return;
915         }
916
917         host->data = NULL;
918
919         if (!data->error)
920                 data->bytes_xfered += data->blocks * (data->blksz);
921         else
922                 data->bytes_xfered = 0;
923
924         if (!data->stop) {
925                 omap_hsmmc_request_done(host, data->mrq);
926                 return;
927         }
928         omap_hsmmc_start_command(host, data->stop, NULL);
929 }
930
931 /*
932  * Notify the core about command completion
933  */
934 static void
935 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
936 {
937         host->cmd = NULL;
938
939         if (cmd->flags & MMC_RSP_PRESENT) {
940                 if (cmd->flags & MMC_RSP_136) {
941                         /* response type 2 */
942                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
943                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
944                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
945                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
946                 } else {
947                         /* response types 1, 1b, 3, 4, 5, 6 */
948                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
949                 }
950         }
951         if ((host->data == NULL && !host->response_busy) || cmd->error)
952                 omap_hsmmc_request_done(host, cmd->mrq);
953 }
954
955 /*
956  * DMA clean up for command errors
957  */
958 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
959 {
960         int dma_ch;
961
962         host->data->error = errno;
963
964         spin_lock(&host->irq_lock);
965         dma_ch = host->dma_ch;
966         host->dma_ch = -1;
967         spin_unlock(&host->irq_lock);
968
969         if (host->use_dma && dma_ch != -1) {
970                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
971                         host->data->sg_len,
972                         omap_hsmmc_get_dma_dir(host, host->data));
973                 omap_free_dma(dma_ch);
974         }
975         host->data = NULL;
976 }
977
978 /*
979  * Readable error output
980  */
981 #ifdef CONFIG_MMC_DEBUG
982 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
983 {
984         /* --- means reserved bit without definition at documentation */
985         static const char *omap_hsmmc_status_bits[] = {
986                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
987                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
988                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
989                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
990         };
991         char res[256];
992         char *buf = res;
993         int len, i;
994
995         len = sprintf(buf, "MMC IRQ 0x%x :", status);
996         buf += len;
997
998         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
999                 if (status & (1 << i)) {
1000                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1001                         buf += len;
1002                 }
1003
1004         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1005 }
1006 #endif  /* CONFIG_MMC_DEBUG */
1007
1008 /*
1009  * MMC controller internal state machines reset
1010  *
1011  * Used to reset command or data internal state machines, using respectively
1012  *  SRC or SRD bit of SYSCTL register
1013  * Can be called from interrupt context
1014  */
1015 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1016                                                    unsigned long bit)
1017 {
1018         unsigned long i = 0;
1019         unsigned long limit = (loops_per_jiffy *
1020                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1021
1022         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1023                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1024
1025         /*
1026          * OMAP4 ES2 and greater has an updated reset logic.
1027          * Monitor a 0->1 transition first
1028          */
1029         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1030                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1031                                         && (i++ < limit))
1032                         cpu_relax();
1033         }
1034         i = 0;
1035
1036         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1037                 (i++ < limit))
1038                 cpu_relax();
1039
1040         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1041                 dev_err(mmc_dev(host->mmc),
1042                         "Timeout waiting on controller reset in %s\n",
1043                         __func__);
1044 }
1045
1046 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1047 {
1048         struct mmc_data *data;
1049         int end_cmd = 0, end_trans = 0;
1050
1051         if (!host->req_in_progress) {
1052                 do {
1053                         OMAP_HSMMC_WRITE(host->base, STAT, status);
1054                         /* Flush posted write */
1055                         status = OMAP_HSMMC_READ(host->base, STAT);
1056                 } while (status & INT_EN_MASK);
1057                 return;
1058         }
1059
1060         data = host->data;
1061         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1062
1063         if (status & ERR) {
1064 #ifdef CONFIG_MMC_DEBUG
1065                 omap_hsmmc_report_irq(host, status);
1066 #endif
1067                 if ((status & CMD_TIMEOUT) ||
1068                         (status & CMD_CRC)) {
1069                         if (host->cmd) {
1070                                 if (status & CMD_TIMEOUT) {
1071                                         omap_hsmmc_reset_controller_fsm(host,
1072                                                                         SRC);
1073                                         host->cmd->error = -ETIMEDOUT;
1074                                 } else {
1075                                         host->cmd->error = -EILSEQ;
1076                                 }
1077                                 end_cmd = 1;
1078                         }
1079                         if (host->data || host->response_busy) {
1080                                 if (host->data)
1081                                         omap_hsmmc_dma_cleanup(host,
1082                                                                 -ETIMEDOUT);
1083                                 host->response_busy = 0;
1084                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1085                         }
1086                 }
1087                 if ((status & DATA_TIMEOUT) ||
1088                         (status & DATA_CRC)) {
1089                         if (host->data || host->response_busy) {
1090                                 int err = (status & DATA_TIMEOUT) ?
1091                                                 -ETIMEDOUT : -EILSEQ;
1092
1093                                 if (host->data)
1094                                         omap_hsmmc_dma_cleanup(host, err);
1095                                 else
1096                                         host->mrq->cmd->error = err;
1097                                 host->response_busy = 0;
1098                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1099                                 end_trans = 1;
1100                         }
1101                 }
1102                 if (status & CARD_ERR) {
1103                         dev_dbg(mmc_dev(host->mmc),
1104                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1105                         if (host->cmd)
1106                                 end_cmd = 1;
1107                         if (host->data)
1108                                 end_trans = 1;
1109                 }
1110         }
1111
1112         OMAP_HSMMC_WRITE(host->base, STAT, status);
1113
1114         if (end_cmd || ((status & CC) && host->cmd))
1115                 omap_hsmmc_cmd_done(host, host->cmd);
1116         if ((end_trans || (status & TC)) && host->mrq)
1117                 omap_hsmmc_xfer_done(host, data);
1118 }
1119
1120 /*
1121  * MMC controller IRQ handler
1122  */
1123 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1124 {
1125         struct omap_hsmmc_host *host = dev_id;
1126         int status;
1127
1128         status = OMAP_HSMMC_READ(host->base, STAT);
1129         do {
1130                 omap_hsmmc_do_irq(host, status);
1131                 /* Flush posted write */
1132                 status = OMAP_HSMMC_READ(host->base, STAT);
1133         } while (status & INT_EN_MASK);
1134
1135         return IRQ_HANDLED;
1136 }
1137
1138 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1139 {
1140         unsigned long i;
1141
1142         OMAP_HSMMC_WRITE(host->base, HCTL,
1143                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1144         for (i = 0; i < loops_per_jiffy; i++) {
1145                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1146                         break;
1147                 cpu_relax();
1148         }
1149 }
1150
1151 /*
1152  * Switch MMC interface voltage ... only relevant for MMC1.
1153  *
1154  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1155  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1156  * Some chips, like eMMC ones, use internal transceivers.
1157  */
1158 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1159 {
1160         u32 reg_val = 0;
1161         int ret;
1162
1163         /* Disable the clocks */
1164         clk_disable(host->fclk);
1165         clk_disable(host->iclk);
1166         if (host->got_dbclk)
1167                 clk_disable(host->dbclk);
1168
1169         /* Turn the power off */
1170         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1171
1172         /* Turn the power ON with given VDD 1.8 or 3.0v */
1173         if (!ret)
1174                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1175                                                vdd);
1176         clk_enable(host->iclk);
1177         clk_enable(host->fclk);
1178         if (host->got_dbclk)
1179                 clk_enable(host->dbclk);
1180
1181         if (ret != 0)
1182                 goto err;
1183
1184         OMAP_HSMMC_WRITE(host->base, HCTL,
1185                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1186         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1187
1188         /*
1189          * If a MMC dual voltage card is detected, the set_ios fn calls
1190          * this fn with VDD bit set for 1.8V. Upon card removal from the
1191          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1192          *
1193          * Cope with a bit of slop in the range ... per data sheets:
1194          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1195          *    but recommended values are 1.71V to 1.89V
1196          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1197          *    but recommended values are 2.7V to 3.3V
1198          *
1199          * Board setup code shouldn't permit anything very out-of-range.
1200          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1201          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1202          */
1203         if ((1 << vdd) <= MMC_VDD_23_24)
1204                 reg_val |= SDVS18;
1205         else
1206                 reg_val |= SDVS30;
1207
1208         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1209         set_sd_bus_power(host);
1210
1211         return 0;
1212 err:
1213         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1214         return ret;
1215 }
1216
1217 /* Protect the card while the cover is open */
1218 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1219 {
1220         if (!mmc_slot(host).get_cover_state)
1221                 return;
1222
1223         host->reqs_blocked = 0;
1224         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1225                 if (host->protect_card) {
1226                         printk(KERN_INFO "%s: cover is closed, "
1227                                          "card is now accessible\n",
1228                                          mmc_hostname(host->mmc));
1229                         host->protect_card = 0;
1230                 }
1231         } else {
1232                 if (!host->protect_card) {
1233                         printk(KERN_INFO "%s: cover is open, "
1234                                          "card is now inaccessible\n",
1235                                          mmc_hostname(host->mmc));
1236                         host->protect_card = 1;
1237                 }
1238         }
1239 }
1240
1241 /*
1242  * Work Item to notify the core about card insertion/removal
1243  */
1244 static void omap_hsmmc_detect(struct work_struct *work)
1245 {
1246         struct omap_hsmmc_host *host =
1247                 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1248         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1249         int carddetect;
1250
1251         if (host->suspended)
1252                 return;
1253
1254         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1255
1256         if (slot->card_detect)
1257                 carddetect = slot->card_detect(host->dev, host->slot_id);
1258         else {
1259                 omap_hsmmc_protect_card(host);
1260                 carddetect = -ENOSYS;
1261         }
1262
1263         if (carddetect)
1264                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1265         else
1266                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1267 }
1268
1269 /*
1270  * ISR for handling card insertion and removal
1271  */
1272 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1273 {
1274         struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1275
1276         if (host->suspended)
1277                 return IRQ_HANDLED;
1278         schedule_work(&host->mmc_carddetect_work);
1279
1280         return IRQ_HANDLED;
1281 }
1282
1283 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1284                                      struct mmc_data *data)
1285 {
1286         int sync_dev;
1287
1288         if (data->flags & MMC_DATA_WRITE)
1289                 sync_dev = host->dma_line_tx;
1290         else
1291                 sync_dev = host->dma_line_rx;
1292         return sync_dev;
1293 }
1294
1295 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1296                                        struct mmc_data *data,
1297                                        struct scatterlist *sgl)
1298 {
1299         int blksz, nblk, dma_ch;
1300
1301         dma_ch = host->dma_ch;
1302         if (data->flags & MMC_DATA_WRITE) {
1303                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1304                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1305                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1306                         sg_dma_address(sgl), 0, 0);
1307         } else {
1308                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1309                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1310                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1311                         sg_dma_address(sgl), 0, 0);
1312         }
1313
1314         blksz = host->data->blksz;
1315         nblk = sg_dma_len(sgl) / blksz;
1316
1317         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1318                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1319                         omap_hsmmc_get_dma_sync_dev(host, data),
1320                         !(data->flags & MMC_DATA_WRITE));
1321
1322         omap_start_dma(dma_ch);
1323 }
1324
1325 /*
1326  * DMA call back function
1327  */
1328 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1329 {
1330         struct omap_hsmmc_host *host = cb_data;
1331         struct mmc_data *data = host->mrq->data;
1332         int dma_ch, req_in_progress;
1333
1334         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1335                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1336                         ch_status);
1337                 return;
1338         }
1339
1340         spin_lock(&host->irq_lock);
1341         if (host->dma_ch < 0) {
1342                 spin_unlock(&host->irq_lock);
1343                 return;
1344         }
1345
1346         host->dma_sg_idx++;
1347         if (host->dma_sg_idx < host->dma_len) {
1348                 /* Fire up the next transfer. */
1349                 omap_hsmmc_config_dma_params(host, data,
1350                                            data->sg + host->dma_sg_idx);
1351                 spin_unlock(&host->irq_lock);
1352                 return;
1353         }
1354
1355         if (!data->host_cookie)
1356                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1357                              omap_hsmmc_get_dma_dir(host, data));
1358
1359         req_in_progress = host->req_in_progress;
1360         dma_ch = host->dma_ch;
1361         host->dma_ch = -1;
1362         spin_unlock(&host->irq_lock);
1363
1364         omap_free_dma(dma_ch);
1365
1366         /* If DMA has finished after TC, complete the request */
1367         if (!req_in_progress) {
1368                 struct mmc_request *mrq = host->mrq;
1369
1370                 host->mrq = NULL;
1371                 mmc_request_done(host->mmc, mrq);
1372         }
1373 }
1374
1375 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1376                                        struct mmc_data *data,
1377                                        struct omap_hsmmc_next *next)
1378 {
1379         int dma_len;
1380
1381         if (!next && data->host_cookie &&
1382             data->host_cookie != host->next_data.cookie) {
1383                 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1384                        " host->next_data.cookie %d\n",
1385                        __func__, data->host_cookie, host->next_data.cookie);
1386                 data->host_cookie = 0;
1387         }
1388
1389         /* Check if next job is already prepared */
1390         if (next ||
1391             (!next && data->host_cookie != host->next_data.cookie)) {
1392                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1393                                      data->sg_len,
1394                                      omap_hsmmc_get_dma_dir(host, data));
1395
1396         } else {
1397                 dma_len = host->next_data.dma_len;
1398                 host->next_data.dma_len = 0;
1399         }
1400
1401
1402         if (dma_len == 0)
1403                 return -EINVAL;
1404
1405         if (next) {
1406                 next->dma_len = dma_len;
1407                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1408         } else
1409                 host->dma_len = dma_len;
1410
1411         return 0;
1412 }
1413
1414 /*
1415  * Routine to configure and start DMA for the MMC card
1416  */
1417 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1418                                         struct mmc_request *req)
1419 {
1420         int dma_ch = 0, ret = 0, i;
1421         struct mmc_data *data = req->data;
1422
1423         /* Sanity check: all the SG entries must be aligned by block size. */
1424         for (i = 0; i < data->sg_len; i++) {
1425                 struct scatterlist *sgl;
1426
1427                 sgl = data->sg + i;
1428                 if (sgl->length % data->blksz)
1429                         return -EINVAL;
1430         }
1431         if ((data->blksz % 4) != 0)
1432                 /* REVISIT: The MMC buffer increments only when MSB is written.
1433                  * Return error for blksz which is non multiple of four.
1434                  */
1435                 return -EINVAL;
1436
1437         BUG_ON(host->dma_ch != -1);
1438
1439         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1440                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1441         if (ret != 0) {
1442                 dev_err(mmc_dev(host->mmc),
1443                         "%s: omap_request_dma() failed with %d\n",
1444                         mmc_hostname(host->mmc), ret);
1445                 return ret;
1446         }
1447         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1448         if (ret)
1449                 return ret;
1450
1451         host->dma_ch = dma_ch;
1452         host->dma_sg_idx = 0;
1453
1454         omap_hsmmc_config_dma_params(host, data, data->sg);
1455
1456         return 0;
1457 }
1458
1459 static void set_data_timeout(struct omap_hsmmc_host *host,
1460                              unsigned int timeout_ns,
1461                              unsigned int timeout_clks)
1462 {
1463         unsigned int timeout, cycle_ns;
1464         uint32_t reg, clkd, dto = 0;
1465
1466         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1467         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1468         if (clkd == 0)
1469                 clkd = 1;
1470
1471         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1472         timeout = timeout_ns / cycle_ns;
1473         timeout += timeout_clks;
1474         if (timeout) {
1475                 while ((timeout & 0x80000000) == 0) {
1476                         dto += 1;
1477                         timeout <<= 1;
1478                 }
1479                 dto = 31 - dto;
1480                 timeout <<= 1;
1481                 if (timeout && dto)
1482                         dto += 1;
1483                 if (dto >= 13)
1484                         dto -= 13;
1485                 else
1486                         dto = 0;
1487                 if (dto > 14)
1488                         dto = 14;
1489         }
1490
1491         reg &= ~DTO_MASK;
1492         reg |= dto << DTO_SHIFT;
1493         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1494 }
1495
1496 /*
1497  * Configure block length for MMC/SD cards and initiate the transfer.
1498  */
1499 static int
1500 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1501 {
1502         int ret;
1503         host->data = req->data;
1504
1505         if (req->data == NULL) {
1506                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1507                 /*
1508                  * Set an arbitrary 100ms data timeout for commands with
1509                  * busy signal.
1510                  */
1511                 if (req->cmd->flags & MMC_RSP_BUSY)
1512                         set_data_timeout(host, 100000000U, 0);
1513                 return 0;
1514         }
1515
1516         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1517                                         | (req->data->blocks << 16));
1518         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1519
1520         if (host->use_dma) {
1521                 ret = omap_hsmmc_start_dma_transfer(host, req);
1522                 if (ret != 0) {
1523                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1524                         return ret;
1525                 }
1526         }
1527         return 0;
1528 }
1529
1530 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1531                                 int err)
1532 {
1533         struct omap_hsmmc_host *host = mmc_priv(mmc);
1534         struct mmc_data *data = mrq->data;
1535
1536         if (host->use_dma) {
1537                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1538                              omap_hsmmc_get_dma_dir(host, data));
1539                 data->host_cookie = 0;
1540         }
1541 }
1542
1543 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1544                                bool is_first_req)
1545 {
1546         struct omap_hsmmc_host *host = mmc_priv(mmc);
1547
1548         if (mrq->data->host_cookie) {
1549                 mrq->data->host_cookie = 0;
1550                 return ;
1551         }
1552
1553         if (host->use_dma)
1554                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1555                                                 &host->next_data))
1556                         mrq->data->host_cookie = 0;
1557 }
1558
1559 /*
1560  * Request function. for read/write operation
1561  */
1562 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1563 {
1564         struct omap_hsmmc_host *host = mmc_priv(mmc);
1565         int err;
1566
1567         BUG_ON(host->req_in_progress);
1568         BUG_ON(host->dma_ch != -1);
1569         if (host->protect_card) {
1570                 if (host->reqs_blocked < 3) {
1571                         /*
1572                          * Ensure the controller is left in a consistent
1573                          * state by resetting the command and data state
1574                          * machines.
1575                          */
1576                         omap_hsmmc_reset_controller_fsm(host, SRD);
1577                         omap_hsmmc_reset_controller_fsm(host, SRC);
1578                         host->reqs_blocked += 1;
1579                 }
1580                 req->cmd->error = -EBADF;
1581                 if (req->data)
1582                         req->data->error = -EBADF;
1583                 req->cmd->retries = 0;
1584                 mmc_request_done(mmc, req);
1585                 return;
1586         } else if (host->reqs_blocked)
1587                 host->reqs_blocked = 0;
1588         WARN_ON(host->mrq != NULL);
1589         host->mrq = req;
1590         err = omap_hsmmc_prepare_data(host, req);
1591         if (err) {
1592                 req->cmd->error = err;
1593                 if (req->data)
1594                         req->data->error = err;
1595                 host->mrq = NULL;
1596                 mmc_request_done(mmc, req);
1597                 return;
1598         }
1599
1600         omap_hsmmc_start_command(host, req->cmd, req->data);
1601 }
1602
1603 /* Routine to configure clock values. Exposed API to core */
1604 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1605 {
1606         struct omap_hsmmc_host *host = mmc_priv(mmc);
1607         u16 dsor = 0;
1608         unsigned long regval;
1609         unsigned long timeout;
1610         u32 con;
1611         int do_send_init_stream = 0;
1612
1613         mmc_host_enable(host->mmc);
1614
1615         if (ios->power_mode != host->power_mode) {
1616                 switch (ios->power_mode) {
1617                 case MMC_POWER_OFF:
1618                         mmc_slot(host).set_power(host->dev, host->slot_id,
1619                                                  0, 0);
1620                         host->vdd = 0;
1621                         break;
1622                 case MMC_POWER_UP:
1623                         mmc_slot(host).set_power(host->dev, host->slot_id,
1624                                                  1, ios->vdd);
1625                         host->vdd = ios->vdd;
1626                         break;
1627                 case MMC_POWER_ON:
1628                         do_send_init_stream = 1;
1629                         break;
1630                 }
1631                 host->power_mode = ios->power_mode;
1632         }
1633
1634         /* FIXME: set registers based only on changes to ios */
1635
1636         con = OMAP_HSMMC_READ(host->base, CON);
1637         switch (mmc->ios.bus_width) {
1638         case MMC_BUS_WIDTH_8:
1639                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1640                 break;
1641         case MMC_BUS_WIDTH_4:
1642                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1643                 OMAP_HSMMC_WRITE(host->base, HCTL,
1644                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1645                 break;
1646         case MMC_BUS_WIDTH_1:
1647                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1648                 OMAP_HSMMC_WRITE(host->base, HCTL,
1649                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1650                 break;
1651         }
1652
1653         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1654                 /* Only MMC1 can interface at 3V without some flavor
1655                  * of external transceiver; but they all handle 1.8V.
1656                  */
1657                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1658                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1659                                 /*
1660                                  * The mmc_select_voltage fn of the core does
1661                                  * not seem to set the power_mode to
1662                                  * MMC_POWER_UP upon recalculating the voltage.
1663                                  * vdd 1.8v.
1664                                  */
1665                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1666                                 dev_dbg(mmc_dev(host->mmc),
1667                                                 "Switch operation failed\n");
1668                 }
1669         }
1670
1671         if (ios->clock) {
1672                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1673                 if (dsor < 1)
1674                         dsor = 1;
1675
1676                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1677                         dsor++;
1678
1679                 if (dsor > 250)
1680                         dsor = 250;
1681         }
1682         omap_hsmmc_stop_clock(host);
1683         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1684         regval = regval & ~(CLKD_MASK);
1685         regval = regval | (dsor << 6) | (DTO << 16);
1686         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1687         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1688                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1689
1690         /* Wait till the ICS bit is set */
1691         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1692         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1693                 && time_before(jiffies, timeout))
1694                 msleep(1);
1695
1696         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1697                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1698
1699         if (do_send_init_stream)
1700                 send_init_stream(host);
1701
1702         con = OMAP_HSMMC_READ(host->base, CON);
1703         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1704                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1705         else
1706                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1707
1708         if (host->power_mode == MMC_POWER_OFF)
1709                 mmc_host_disable(host->mmc);
1710         else
1711                 mmc_host_lazy_disable(host->mmc);
1712 }
1713
1714 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1715 {
1716         struct omap_hsmmc_host *host = mmc_priv(mmc);
1717
1718         if (!mmc_slot(host).card_detect)
1719                 return -ENOSYS;
1720         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1721 }
1722
1723 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1724 {
1725         struct omap_hsmmc_host *host = mmc_priv(mmc);
1726
1727         if (!mmc_slot(host).get_ro)
1728                 return -ENOSYS;
1729         return mmc_slot(host).get_ro(host->dev, 0);
1730 }
1731
1732 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1733 {
1734         struct omap_hsmmc_host *host = mmc_priv(mmc);
1735
1736         if (mmc_slot(host).init_card)
1737                 mmc_slot(host).init_card(card);
1738 }
1739
1740 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1741 {
1742         u32 hctl, capa, value;
1743
1744         /* Only MMC1 supports 3.0V */
1745         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1746                 hctl = SDVS30;
1747                 capa = VS30 | VS18;
1748         } else {
1749                 hctl = SDVS18;
1750                 capa = VS18;
1751         }
1752
1753         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1754         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1755
1756         value = OMAP_HSMMC_READ(host->base, CAPA);
1757         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1758
1759         /* Set the controller to AUTO IDLE mode */
1760         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1761         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1762
1763         /* Set SD bus power bit */
1764         set_sd_bus_power(host);
1765 }
1766
1767 /*
1768  * Dynamic power saving handling, FSM:
1769  *   ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1770  *     ^___________|          |                      |
1771  *     |______________________|______________________|
1772  *
1773  * ENABLED:   mmc host is fully functional
1774  * DISABLED:  fclk is off
1775  * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1776  * REGSLEEP:  fclk is off, voltage regulator is asleep
1777  * OFF:       fclk is off, voltage regulator is off
1778  *
1779  * Transition handlers return the timeout for the next state transition
1780  * or negative error.
1781  */
1782
1783 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1784
1785 /* Handler for [ENABLED -> DISABLED] transition */
1786 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1787 {
1788         omap_hsmmc_context_save(host);
1789         clk_disable(host->fclk);
1790         host->dpm_state = DISABLED;
1791
1792         dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1793
1794         if (host->power_mode == MMC_POWER_OFF)
1795                 return 0;
1796
1797         return OMAP_MMC_SLEEP_TIMEOUT;
1798 }
1799
1800 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1801 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1802 {
1803         int err, new_state;
1804
1805         if (!mmc_try_claim_host(host->mmc))
1806                 return 0;
1807
1808         clk_enable(host->fclk);
1809         omap_hsmmc_context_restore(host);
1810         if (mmc_card_can_sleep(host->mmc)) {
1811                 err = mmc_card_sleep(host->mmc);
1812                 if (err < 0) {
1813                         clk_disable(host->fclk);
1814                         mmc_release_host(host->mmc);
1815                         return err;
1816                 }
1817                 new_state = CARDSLEEP;
1818         } else {
1819                 new_state = REGSLEEP;
1820         }
1821         if (mmc_slot(host).set_sleep)
1822                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1823                                          new_state == CARDSLEEP);
1824         /* FIXME: turn off bus power and perhaps interrupts too */
1825         clk_disable(host->fclk);
1826         host->dpm_state = new_state;
1827
1828         mmc_release_host(host->mmc);
1829
1830         dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1831                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1832
1833         if (mmc_slot(host).no_off)
1834                 return 0;
1835
1836         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1837             mmc_slot(host).card_detect ||
1838             (mmc_slot(host).get_cover_state &&
1839              mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1840                 return OMAP_MMC_OFF_TIMEOUT;
1841
1842         return 0;
1843 }
1844
1845 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1846 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1847 {
1848         if (!mmc_try_claim_host(host->mmc))
1849                 return 0;
1850
1851         if (mmc_slot(host).no_off)
1852                 return 0;
1853
1854         if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1855               mmc_slot(host).card_detect ||
1856               (mmc_slot(host).get_cover_state &&
1857                mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1858                 mmc_release_host(host->mmc);
1859                 return 0;
1860         }
1861
1862         mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1863         host->vdd = 0;
1864         host->power_mode = MMC_POWER_OFF;
1865
1866         dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1867                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1868
1869         host->dpm_state = OFF;
1870
1871         mmc_release_host(host->mmc);
1872
1873         return 0;
1874 }
1875
1876 /* Handler for [DISABLED -> ENABLED] transition */
1877 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1878 {
1879         int err;
1880
1881         err = clk_enable(host->fclk);
1882         if (err < 0)
1883                 return err;
1884
1885         omap_hsmmc_context_restore(host);
1886         host->dpm_state = ENABLED;
1887
1888         dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1889
1890         return 0;
1891 }
1892
1893 /* Handler for [SLEEP -> ENABLED] transition */
1894 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1895 {
1896         if (!mmc_try_claim_host(host->mmc))
1897                 return 0;
1898
1899         clk_enable(host->fclk);
1900         omap_hsmmc_context_restore(host);
1901         if (mmc_slot(host).set_sleep)
1902                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1903                          host->vdd, host->dpm_state == CARDSLEEP);
1904         if (mmc_card_can_sleep(host->mmc))
1905                 mmc_card_awake(host->mmc);
1906
1907         dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1908                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1909
1910         host->dpm_state = ENABLED;
1911
1912         mmc_release_host(host->mmc);
1913
1914         return 0;
1915 }
1916
1917 /* Handler for [OFF -> ENABLED] transition */
1918 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1919 {
1920         clk_enable(host->fclk);
1921
1922         omap_hsmmc_context_restore(host);
1923         omap_hsmmc_conf_bus_power(host);
1924         mmc_power_restore_host(host->mmc);
1925
1926         host->dpm_state = ENABLED;
1927
1928         dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1929
1930         return 0;
1931 }
1932
1933 /*
1934  * Bring MMC host to ENABLED from any other PM state.
1935  */
1936 static int omap_hsmmc_enable(struct mmc_host *mmc)
1937 {
1938         struct omap_hsmmc_host *host = mmc_priv(mmc);
1939
1940         switch (host->dpm_state) {
1941         case DISABLED:
1942                 return omap_hsmmc_disabled_to_enabled(host);
1943         case CARDSLEEP:
1944         case REGSLEEP:
1945                 return omap_hsmmc_sleep_to_enabled(host);
1946         case OFF:
1947                 return omap_hsmmc_off_to_enabled(host);
1948         default:
1949                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1950                 return -EINVAL;
1951         }
1952 }
1953
1954 /*
1955  * Bring MMC host in PM state (one level deeper).
1956  */
1957 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1958 {
1959         struct omap_hsmmc_host *host = mmc_priv(mmc);
1960
1961         switch (host->dpm_state) {
1962         case ENABLED: {
1963                 int delay;
1964
1965                 delay = omap_hsmmc_enabled_to_disabled(host);
1966                 if (lazy || delay < 0)
1967                         return delay;
1968                 return 0;
1969         }
1970         case DISABLED:
1971                 return omap_hsmmc_disabled_to_sleep(host);
1972         case CARDSLEEP:
1973         case REGSLEEP:
1974                 return omap_hsmmc_sleep_to_off(host);
1975         default:
1976                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1977                 return -EINVAL;
1978         }
1979 }
1980
1981 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1982 {
1983         struct omap_hsmmc_host *host = mmc_priv(mmc);
1984         int err;
1985
1986         err = clk_enable(host->fclk);
1987         if (err)
1988                 return err;
1989         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1990         omap_hsmmc_context_restore(host);
1991         return 0;
1992 }
1993
1994 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1995 {
1996         struct omap_hsmmc_host *host = mmc_priv(mmc);
1997
1998         omap_hsmmc_context_save(host);
1999         clk_disable(host->fclk);
2000         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
2001         return 0;
2002 }
2003
2004 static const struct mmc_host_ops omap_hsmmc_ops = {
2005         .enable = omap_hsmmc_enable_fclk,
2006         .disable = omap_hsmmc_disable_fclk,
2007         .post_req = omap_hsmmc_post_req,
2008         .pre_req = omap_hsmmc_pre_req,
2009         .request = omap_hsmmc_request,
2010         .set_ios = omap_hsmmc_set_ios,
2011         .get_cd = omap_hsmmc_get_cd,
2012         .get_ro = omap_hsmmc_get_ro,
2013         .init_card = omap_hsmmc_init_card,
2014         /* NYET -- enable_sdio_irq */
2015 };
2016
2017 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
2018         .enable = omap_hsmmc_enable,
2019         .disable = omap_hsmmc_disable,
2020         .request = omap_hsmmc_request,
2021         .set_ios = omap_hsmmc_set_ios,
2022         .get_cd = omap_hsmmc_get_cd,
2023         .get_ro = omap_hsmmc_get_ro,
2024         .init_card = omap_hsmmc_init_card,
2025         /* NYET -- enable_sdio_irq */
2026 };
2027
2028 #ifdef CONFIG_DEBUG_FS
2029
2030 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
2031 {
2032         struct mmc_host *mmc = s->private;
2033         struct omap_hsmmc_host *host = mmc_priv(mmc);
2034         int context_loss = 0;
2035
2036         if (host->pdata->get_context_loss_count)
2037                 context_loss = host->pdata->get_context_loss_count(host->dev);
2038
2039         seq_printf(s, "mmc%d:\n"
2040                         " enabled:\t%d\n"
2041                         " dpm_state:\t%d\n"
2042                         " nesting_cnt:\t%d\n"
2043                         " ctx_loss:\t%d:%d\n"
2044                         "\nregs:\n",
2045                         mmc->index, mmc->enabled ? 1 : 0,
2046                         host->dpm_state, mmc->nesting_cnt,
2047                         host->context_loss, context_loss);
2048
2049         if (host->suspended || host->dpm_state == OFF) {
2050                 seq_printf(s, "host suspended, can't read registers\n");
2051                 return 0;
2052         }
2053
2054         if (clk_enable(host->fclk) != 0) {
2055                 seq_printf(s, "can't read the regs\n");
2056                 return 0;
2057         }
2058
2059         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
2060                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
2061         seq_printf(s, "CON:\t\t0x%08x\n",
2062                         OMAP_HSMMC_READ(host->base, CON));
2063         seq_printf(s, "HCTL:\t\t0x%08x\n",
2064                         OMAP_HSMMC_READ(host->base, HCTL));
2065         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
2066                         OMAP_HSMMC_READ(host->base, SYSCTL));
2067         seq_printf(s, "IE:\t\t0x%08x\n",
2068                         OMAP_HSMMC_READ(host->base, IE));
2069         seq_printf(s, "ISE:\t\t0x%08x\n",
2070                         OMAP_HSMMC_READ(host->base, ISE));
2071         seq_printf(s, "CAPA:\t\t0x%08x\n",
2072                         OMAP_HSMMC_READ(host->base, CAPA));
2073
2074         clk_disable(host->fclk);
2075
2076         return 0;
2077 }
2078
2079 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
2080 {
2081         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
2082 }
2083
2084 static const struct file_operations mmc_regs_fops = {
2085         .open           = omap_hsmmc_regs_open,
2086         .read           = seq_read,
2087         .llseek         = seq_lseek,
2088         .release        = single_release,
2089 };
2090
2091 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
2092 {
2093         if (mmc->debugfs_root)
2094                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
2095                         mmc, &mmc_regs_fops);
2096 }
2097
2098 #else
2099
2100 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
2101 {
2102 }
2103
2104 #endif
2105
2106 static int __init omap_hsmmc_probe(struct platform_device *pdev)
2107 {
2108         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
2109         struct mmc_host *mmc;
2110         struct omap_hsmmc_host *host = NULL;
2111         struct resource *res;
2112         int ret, irq;
2113
2114         if (pdata == NULL) {
2115                 dev_err(&pdev->dev, "Platform Data is missing\n");
2116                 return -ENXIO;
2117         }
2118
2119         if (pdata->nr_slots == 0) {
2120                 dev_err(&pdev->dev, "No Slots\n");
2121                 return -ENXIO;
2122         }
2123
2124         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2125         irq = platform_get_irq(pdev, 0);
2126         if (res == NULL || irq < 0)
2127                 return -ENXIO;
2128
2129         res->start += pdata->reg_offset;
2130         res->end += pdata->reg_offset;
2131         res = request_mem_region(res->start, resource_size(res), pdev->name);
2132         if (res == NULL)
2133                 return -EBUSY;
2134
2135         ret = omap_hsmmc_gpio_init(pdata);
2136         if (ret)
2137                 goto err;
2138
2139         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2140         if (!mmc) {
2141                 ret = -ENOMEM;
2142                 goto err_alloc;
2143         }
2144
2145         host            = mmc_priv(mmc);
2146         host->mmc       = mmc;
2147         host->pdata     = pdata;
2148         host->dev       = &pdev->dev;
2149         host->use_dma   = 1;
2150         host->dev->dma_mask = &pdata->dma_mask;
2151         host->dma_ch    = -1;
2152         host->irq       = irq;
2153         host->id        = pdev->id;
2154         host->slot_id   = 0;
2155         host->mapbase   = res->start;
2156         host->base      = ioremap(host->mapbase, SZ_4K);
2157         host->power_mode = MMC_POWER_OFF;
2158         host->next_data.cookie = 1;
2159
2160         platform_set_drvdata(pdev, host);
2161         INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
2162
2163         if (mmc_slot(host).power_saving)
2164                 mmc->ops        = &omap_hsmmc_ps_ops;
2165         else
2166                 mmc->ops        = &omap_hsmmc_ops;
2167
2168         /*
2169          * If regulator_disable can only put vcc_aux to sleep then there is
2170          * no off state.
2171          */
2172         if (mmc_slot(host).vcc_aux_disable_is_sleep)
2173                 mmc_slot(host).no_off = 1;
2174
2175         mmc->f_min      = 400000;
2176         mmc->f_max      = 52000000;
2177
2178         spin_lock_init(&host->irq_lock);
2179
2180         host->iclk = clk_get(&pdev->dev, "ick");
2181         if (IS_ERR(host->iclk)) {
2182                 ret = PTR_ERR(host->iclk);
2183                 host->iclk = NULL;
2184                 goto err1;
2185         }
2186         host->fclk = clk_get(&pdev->dev, "fck");
2187         if (IS_ERR(host->fclk)) {
2188                 ret = PTR_ERR(host->fclk);
2189                 host->fclk = NULL;
2190                 clk_put(host->iclk);
2191                 goto err1;
2192         }
2193
2194         omap_hsmmc_context_save(host);
2195
2196         mmc->caps |= MMC_CAP_DISABLE;
2197         mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2198         /* we start off in DISABLED state */
2199         host->dpm_state = DISABLED;
2200
2201         if (clk_enable(host->iclk) != 0) {
2202                 clk_put(host->iclk);
2203                 clk_put(host->fclk);
2204                 goto err1;
2205         }
2206
2207         if (mmc_host_enable(host->mmc) != 0) {
2208                 clk_disable(host->iclk);
2209                 clk_put(host->iclk);
2210                 clk_put(host->fclk);
2211                 goto err1;
2212         }
2213
2214         if (cpu_is_omap2430()) {
2215                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2216                 /*
2217                  * MMC can still work without debounce clock.
2218                  */
2219                 if (IS_ERR(host->dbclk))
2220                         dev_warn(mmc_dev(host->mmc),
2221                                 "Failed to get debounce clock\n");
2222                 else
2223                         host->got_dbclk = 1;
2224
2225                 if (host->got_dbclk)
2226                         if (clk_enable(host->dbclk) != 0)
2227                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2228                                                         " clk failed\n");
2229         }
2230
2231         /* Since we do only SG emulation, we can have as many segs
2232          * as we want. */
2233         mmc->max_segs = 1024;
2234
2235         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2236         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2237         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2238         mmc->max_seg_size = mmc->max_req_size;
2239
2240         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2241                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2242
2243         mmc->caps |= mmc_slot(host).caps;
2244         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2245                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2246
2247         if (mmc_slot(host).nonremovable)
2248                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2249
2250         omap_hsmmc_conf_bus_power(host);
2251
2252         /* Select DMA lines */
2253         switch (host->id) {
2254         case OMAP_MMC1_DEVID:
2255                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2256                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2257                 break;
2258         case OMAP_MMC2_DEVID:
2259                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2260                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2261                 break;
2262         case OMAP_MMC3_DEVID:
2263                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2264                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2265                 break;
2266         case OMAP_MMC4_DEVID:
2267                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2268                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2269                 break;
2270         case OMAP_MMC5_DEVID:
2271                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2272                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2273                 break;
2274         default:
2275                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2276                 goto err_irq;
2277         }
2278
2279         /* Request IRQ for MMC operations */
2280         ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2281                         mmc_hostname(mmc), host);
2282         if (ret) {
2283                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2284                 goto err_irq;
2285         }
2286
2287         if (pdata->init != NULL) {
2288                 if (pdata->init(&pdev->dev) != 0) {
2289                         dev_dbg(mmc_dev(host->mmc),
2290                                 "Unable to configure MMC IRQs\n");
2291                         goto err_irq_cd_init;
2292                 }
2293         }
2294
2295         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2296                 ret = omap_hsmmc_reg_get(host);
2297                 if (ret)
2298                         goto err_reg;
2299                 host->use_reg = 1;
2300         }
2301
2302         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2303
2304         /* Request IRQ for card detect */
2305         if ((mmc_slot(host).card_detect_irq)) {
2306                 ret = request_irq(mmc_slot(host).card_detect_irq,
2307                                   omap_hsmmc_cd_handler,
2308                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2309                                           | IRQF_DISABLED,
2310                                   mmc_hostname(mmc), host);
2311                 if (ret) {
2312                         dev_dbg(mmc_dev(host->mmc),
2313                                 "Unable to grab MMC CD IRQ\n");
2314                         goto err_irq_cd;
2315                 }
2316                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2317                 pdata->resume = omap_hsmmc_resume_cdirq;
2318         }
2319
2320         omap_hsmmc_disable_irq(host);
2321
2322         mmc_host_lazy_disable(host->mmc);
2323
2324         omap_hsmmc_protect_card(host);
2325
2326         mmc_add_host(mmc);
2327
2328         if (mmc_slot(host).name != NULL) {
2329                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2330                 if (ret < 0)
2331                         goto err_slot_name;
2332         }
2333         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2334                 ret = device_create_file(&mmc->class_dev,
2335                                         &dev_attr_cover_switch);
2336                 if (ret < 0)
2337                         goto err_slot_name;
2338         }
2339
2340         omap_hsmmc_debugfs(mmc);
2341
2342         return 0;
2343
2344 err_slot_name:
2345         mmc_remove_host(mmc);
2346         free_irq(mmc_slot(host).card_detect_irq, host);
2347 err_irq_cd:
2348         if (host->use_reg)
2349                 omap_hsmmc_reg_put(host);
2350 err_reg:
2351         if (host->pdata->cleanup)
2352                 host->pdata->cleanup(&pdev->dev);
2353 err_irq_cd_init:
2354         free_irq(host->irq, host);
2355 err_irq:
2356         mmc_host_disable(host->mmc);
2357         clk_disable(host->iclk);
2358         clk_put(host->fclk);
2359         clk_put(host->iclk);
2360         if (host->got_dbclk) {
2361                 clk_disable(host->dbclk);
2362                 clk_put(host->dbclk);
2363         }
2364 err1:
2365         iounmap(host->base);
2366         platform_set_drvdata(pdev, NULL);
2367         mmc_free_host(mmc);
2368 err_alloc:
2369         omap_hsmmc_gpio_free(pdata);
2370 err:
2371         release_mem_region(res->start, resource_size(res));
2372         return ret;
2373 }
2374
2375 static int omap_hsmmc_remove(struct platform_device *pdev)
2376 {
2377         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2378         struct resource *res;
2379
2380         if (host) {
2381                 mmc_host_enable(host->mmc);
2382                 mmc_remove_host(host->mmc);
2383                 if (host->use_reg)
2384                         omap_hsmmc_reg_put(host);
2385                 if (host->pdata->cleanup)
2386                         host->pdata->cleanup(&pdev->dev);
2387                 free_irq(host->irq, host);
2388                 if (mmc_slot(host).card_detect_irq)
2389                         free_irq(mmc_slot(host).card_detect_irq, host);
2390                 flush_work_sync(&host->mmc_carddetect_work);
2391
2392                 mmc_host_disable(host->mmc);
2393                 clk_disable(host->iclk);
2394                 clk_put(host->fclk);
2395                 clk_put(host->iclk);
2396                 if (host->got_dbclk) {
2397                         clk_disable(host->dbclk);
2398                         clk_put(host->dbclk);
2399                 }
2400
2401                 mmc_free_host(host->mmc);
2402                 iounmap(host->base);
2403                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2404         }
2405
2406         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2407         if (res)
2408                 release_mem_region(res->start, resource_size(res));
2409         platform_set_drvdata(pdev, NULL);
2410
2411         return 0;
2412 }
2413
2414 #ifdef CONFIG_PM
2415 static int omap_hsmmc_suspend(struct device *dev)
2416 {
2417         int ret = 0;
2418         struct platform_device *pdev = to_platform_device(dev);
2419         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2420
2421         if (host && host->suspended)
2422                 return 0;
2423
2424         if (host) {
2425                 host->suspended = 1;
2426                 if (host->pdata->suspend) {
2427                         ret = host->pdata->suspend(&pdev->dev,
2428                                                         host->slot_id);
2429                         if (ret) {
2430                                 dev_dbg(mmc_dev(host->mmc),
2431                                         "Unable to handle MMC board"
2432                                         " level suspend\n");
2433                                 host->suspended = 0;
2434                                 return ret;
2435                         }
2436                 }
2437                 cancel_work_sync(&host->mmc_carddetect_work);
2438                 ret = mmc_suspend_host(host->mmc);
2439                 mmc_host_enable(host->mmc);
2440                 if (ret == 0) {
2441                         omap_hsmmc_disable_irq(host);
2442                         OMAP_HSMMC_WRITE(host->base, HCTL,
2443                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2444                         mmc_host_disable(host->mmc);
2445                         clk_disable(host->iclk);
2446                         if (host->got_dbclk)
2447                                 clk_disable(host->dbclk);
2448                 } else {
2449                         host->suspended = 0;
2450                         if (host->pdata->resume) {
2451                                 ret = host->pdata->resume(&pdev->dev,
2452                                                           host->slot_id);
2453                                 if (ret)
2454                                         dev_dbg(mmc_dev(host->mmc),
2455                                                 "Unmask interrupt failed\n");
2456                         }
2457                         mmc_host_disable(host->mmc);
2458                 }
2459
2460         }
2461         return ret;
2462 }
2463
2464 /* Routine to resume the MMC device */
2465 static int omap_hsmmc_resume(struct device *dev)
2466 {
2467         int ret = 0;
2468         struct platform_device *pdev = to_platform_device(dev);
2469         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2470
2471         if (host && !host->suspended)
2472                 return 0;
2473
2474         if (host) {
2475                 ret = clk_enable(host->iclk);
2476                 if (ret)
2477                         goto clk_en_err;
2478
2479                 if (mmc_host_enable(host->mmc) != 0) {
2480                         clk_disable(host->iclk);
2481                         goto clk_en_err;
2482                 }
2483
2484                 if (host->got_dbclk)
2485                         clk_enable(host->dbclk);
2486
2487                 omap_hsmmc_conf_bus_power(host);
2488
2489                 if (host->pdata->resume) {
2490                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2491                         if (ret)
2492                                 dev_dbg(mmc_dev(host->mmc),
2493                                         "Unmask interrupt failed\n");
2494                 }
2495
2496                 omap_hsmmc_protect_card(host);
2497
2498                 /* Notify the core to resume the host */
2499                 ret = mmc_resume_host(host->mmc);
2500                 if (ret == 0)
2501                         host->suspended = 0;
2502
2503                 mmc_host_lazy_disable(host->mmc);
2504         }
2505
2506         return ret;
2507
2508 clk_en_err:
2509         dev_dbg(mmc_dev(host->mmc),
2510                 "Failed to enable MMC clocks during resume\n");
2511         return ret;
2512 }
2513
2514 #else
2515 #define omap_hsmmc_suspend      NULL
2516 #define omap_hsmmc_resume               NULL
2517 #endif
2518
2519 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2520         .suspend        = omap_hsmmc_suspend,
2521         .resume         = omap_hsmmc_resume,
2522 };
2523
2524 static struct platform_driver omap_hsmmc_driver = {
2525         .remove         = omap_hsmmc_remove,
2526         .driver         = {
2527                 .name = DRIVER_NAME,
2528                 .owner = THIS_MODULE,
2529                 .pm = &omap_hsmmc_dev_pm_ops,
2530         },
2531 };
2532
2533 static int __init omap_hsmmc_init(void)
2534 {
2535         /* Register the MMC driver */
2536         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2537 }
2538
2539 static void __exit omap_hsmmc_cleanup(void)
2540 {
2541         /* Unregister MMC driver */
2542         platform_driver_unregister(&omap_hsmmc_driver);
2543 }
2544
2545 module_init(omap_hsmmc_init);
2546 module_exit(omap_hsmmc_cleanup);
2547
2548 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2549 MODULE_LICENSE("GPL");
2550 MODULE_ALIAS("platform:" DRIVER_NAME);
2551 MODULE_AUTHOR("Texas Instruments Inc");