mmc: omap_hsmmc: Remove unused iclk
[linux-2.6.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2  * drivers/mmc/host/omap_hsmmc.c
3  *
4  * Driver for OMAP2430/3430 MMC controller.
5  *
6  * Copyright (C) 2007 Texas Instruments.
7  *
8  * Authors:
9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
10  *      Madhusudhan             <madhu.cr@ti.com>
11  *      Mohit Jalori            <mjalori@ti.com>
12  *
13  * This file is licensed under the terms of the GNU General Public License
14  * version 2. This program is licensed "as is" without any warranty of any
15  * kind, whether express or implied.
16  */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/io.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
37 #include <plat/dma.h>
38 #include <mach/hardware.h>
39 #include <plat/board.h>
40 #include <plat/mmc.h>
41 #include <plat/cpu.h>
42
43 /* OMAP HSMMC Host Controller Registers */
44 #define OMAP_HSMMC_SYSCONFIG    0x0010
45 #define OMAP_HSMMC_SYSSTATUS    0x0014
46 #define OMAP_HSMMC_CON          0x002C
47 #define OMAP_HSMMC_BLK          0x0104
48 #define OMAP_HSMMC_ARG          0x0108
49 #define OMAP_HSMMC_CMD          0x010C
50 #define OMAP_HSMMC_RSP10        0x0110
51 #define OMAP_HSMMC_RSP32        0x0114
52 #define OMAP_HSMMC_RSP54        0x0118
53 #define OMAP_HSMMC_RSP76        0x011C
54 #define OMAP_HSMMC_DATA         0x0120
55 #define OMAP_HSMMC_HCTL         0x0128
56 #define OMAP_HSMMC_SYSCTL       0x012C
57 #define OMAP_HSMMC_STAT         0x0130
58 #define OMAP_HSMMC_IE           0x0134
59 #define OMAP_HSMMC_ISE          0x0138
60 #define OMAP_HSMMC_CAPA         0x0140
61
62 #define VS18                    (1 << 26)
63 #define VS30                    (1 << 25)
64 #define SDVS18                  (0x5 << 9)
65 #define SDVS30                  (0x6 << 9)
66 #define SDVS33                  (0x7 << 9)
67 #define SDVS_MASK               0x00000E00
68 #define SDVSCLR                 0xFFFFF1FF
69 #define SDVSDET                 0x00000400
70 #define AUTOIDLE                0x1
71 #define SDBP                    (1 << 8)
72 #define DTO                     0xe
73 #define ICE                     0x1
74 #define ICS                     0x2
75 #define CEN                     (1 << 2)
76 #define CLKD_MASK               0x0000FFC0
77 #define CLKD_SHIFT              6
78 #define DTO_MASK                0x000F0000
79 #define DTO_SHIFT               16
80 #define INT_EN_MASK             0x307F0033
81 #define BWR_ENABLE              (1 << 4)
82 #define BRR_ENABLE              (1 << 5)
83 #define DTO_ENABLE              (1 << 20)
84 #define INIT_STREAM             (1 << 1)
85 #define DP_SELECT               (1 << 21)
86 #define DDIR                    (1 << 4)
87 #define DMA_EN                  0x1
88 #define MSBS                    (1 << 5)
89 #define BCE                     (1 << 1)
90 #define FOUR_BIT                (1 << 1)
91 #define DW8                     (1 << 5)
92 #define CC                      0x1
93 #define TC                      0x02
94 #define OD                      0x1
95 #define ERR                     (1 << 15)
96 #define CMD_TIMEOUT             (1 << 16)
97 #define DATA_TIMEOUT            (1 << 20)
98 #define CMD_CRC                 (1 << 17)
99 #define DATA_CRC                (1 << 21)
100 #define CARD_ERR                (1 << 28)
101 #define STAT_CLEAR              0xFFFFFFFF
102 #define INIT_STREAM_CMD         0x00000000
103 #define DUAL_VOLT_OCR_BIT       7
104 #define SRC                     (1 << 25)
105 #define SRD                     (1 << 26)
106 #define SOFTRESET               (1 << 1)
107 #define RESETDONE               (1 << 0)
108
109 /*
110  * FIXME: Most likely all the data using these _DEVID defines should come
111  * from the platform_data, or implemented in controller and slot specific
112  * functions.
113  */
114 #define OMAP_MMC1_DEVID         0
115 #define OMAP_MMC2_DEVID         1
116 #define OMAP_MMC3_DEVID         2
117 #define OMAP_MMC4_DEVID         3
118 #define OMAP_MMC5_DEVID         4
119
120 #define MMC_AUTOSUSPEND_DELAY   100
121 #define MMC_TIMEOUT_MS          20
122 #define OMAP_MMC_MASTER_CLOCK   96000000
123 #define DRIVER_NAME             "omap_hsmmc"
124
125 /*
126  * One controller can have multiple slots, like on some omap boards using
127  * omap.c controller driver. Luckily this is not currently done on any known
128  * omap_hsmmc.c device.
129  */
130 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
131
132 /*
133  * MMC Host controller read/write API's
134  */
135 #define OMAP_HSMMC_READ(base, reg)      \
136         __raw_readl((base) + OMAP_HSMMC_##reg)
137
138 #define OMAP_HSMMC_WRITE(base, reg, val) \
139         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
140
141 struct omap_hsmmc_next {
142         unsigned int    dma_len;
143         s32             cookie;
144 };
145
146 struct omap_hsmmc_host {
147         struct  device          *dev;
148         struct  mmc_host        *mmc;
149         struct  mmc_request     *mrq;
150         struct  mmc_command     *cmd;
151         struct  mmc_data        *data;
152         struct  clk             *fclk;
153         struct  clk             *dbclk;
154         /*
155          * vcc == configured supply
156          * vcc_aux == optional
157          *   -  MMC1, supply for DAT4..DAT7
158          *   -  MMC2/MMC2, external level shifter voltage supply, for
159          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
160          */
161         struct  regulator       *vcc;
162         struct  regulator       *vcc_aux;
163         struct  work_struct     mmc_carddetect_work;
164         void    __iomem         *base;
165         resource_size_t         mapbase;
166         spinlock_t              irq_lock; /* Prevent races with irq handler */
167         unsigned int            id;
168         unsigned int            dma_len;
169         unsigned int            dma_sg_idx;
170         unsigned char           bus_mode;
171         unsigned char           power_mode;
172         u32                     *buffer;
173         u32                     bytesleft;
174         int                     suspended;
175         int                     irq;
176         int                     use_dma, dma_ch;
177         int                     dma_line_tx, dma_line_rx;
178         int                     slot_id;
179         int                     got_dbclk;
180         int                     response_busy;
181         int                     context_loss;
182         int                     dpm_state;
183         int                     vdd;
184         int                     protect_card;
185         int                     reqs_blocked;
186         int                     use_reg;
187         int                     req_in_progress;
188         struct omap_hsmmc_next  next_data;
189
190         struct  omap_mmc_platform_data  *pdata;
191 };
192
193 static int omap_hsmmc_card_detect(struct device *dev, int slot)
194 {
195         struct omap_mmc_platform_data *mmc = dev->platform_data;
196
197         /* NOTE: assumes card detect signal is active-low */
198         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
199 }
200
201 static int omap_hsmmc_get_wp(struct device *dev, int slot)
202 {
203         struct omap_mmc_platform_data *mmc = dev->platform_data;
204
205         /* NOTE: assumes write protect signal is active-high */
206         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
207 }
208
209 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
210 {
211         struct omap_mmc_platform_data *mmc = dev->platform_data;
212
213         /* NOTE: assumes card detect signal is active-low */
214         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
215 }
216
217 #ifdef CONFIG_PM
218
219 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
220 {
221         struct omap_mmc_platform_data *mmc = dev->platform_data;
222
223         disable_irq(mmc->slots[0].card_detect_irq);
224         return 0;
225 }
226
227 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
228 {
229         struct omap_mmc_platform_data *mmc = dev->platform_data;
230
231         enable_irq(mmc->slots[0].card_detect_irq);
232         return 0;
233 }
234
235 #else
236
237 #define omap_hsmmc_suspend_cdirq        NULL
238 #define omap_hsmmc_resume_cdirq         NULL
239
240 #endif
241
242 #ifdef CONFIG_REGULATOR
243
244 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
245                                   int vdd)
246 {
247         struct omap_hsmmc_host *host =
248                 platform_get_drvdata(to_platform_device(dev));
249         int ret;
250
251         if (mmc_slot(host).before_set_reg)
252                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
253
254         if (power_on)
255                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
256         else
257                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
258
259         if (mmc_slot(host).after_set_reg)
260                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
261
262         return ret;
263 }
264
265 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
266                                    int vdd)
267 {
268         struct omap_hsmmc_host *host =
269                 platform_get_drvdata(to_platform_device(dev));
270         int ret = 0;
271
272         /*
273          * If we don't see a Vcc regulator, assume it's a fixed
274          * voltage always-on regulator.
275          */
276         if (!host->vcc)
277                 return 0;
278
279         if (mmc_slot(host).before_set_reg)
280                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
281
282         /*
283          * Assume Vcc regulator is used only to power the card ... OMAP
284          * VDDS is used to power the pins, optionally with a transceiver to
285          * support cards using voltages other than VDDS (1.8V nominal).  When a
286          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
287          *
288          * In some cases this regulator won't support enable/disable;
289          * e.g. it's a fixed rail for a WLAN chip.
290          *
291          * In other cases vcc_aux switches interface power.  Example, for
292          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
293          * chips/cards need an interface voltage rail too.
294          */
295         if (power_on) {
296                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
297                 /* Enable interface voltage rail, if needed */
298                 if (ret == 0 && host->vcc_aux) {
299                         ret = regulator_enable(host->vcc_aux);
300                         if (ret < 0)
301                                 ret = mmc_regulator_set_ocr(host->mmc,
302                                                         host->vcc, 0);
303                 }
304         } else {
305                 /* Shut down the rail */
306                 if (host->vcc_aux)
307                         ret = regulator_disable(host->vcc_aux);
308                 if (!ret) {
309                         /* Then proceed to shut down the local regulator */
310                         ret = mmc_regulator_set_ocr(host->mmc,
311                                                 host->vcc, 0);
312                 }
313         }
314
315         if (mmc_slot(host).after_set_reg)
316                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
317
318         return ret;
319 }
320
321 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
322                                         int vdd)
323 {
324         return 0;
325 }
326
327 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
328                                   int vdd, int cardsleep)
329 {
330         struct omap_hsmmc_host *host =
331                 platform_get_drvdata(to_platform_device(dev));
332         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
333
334         return regulator_set_mode(host->vcc, mode);
335 }
336
337 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
338                                    int vdd, int cardsleep)
339 {
340         struct omap_hsmmc_host *host =
341                 platform_get_drvdata(to_platform_device(dev));
342         int err, mode;
343
344         /*
345          * If we don't see a Vcc regulator, assume it's a fixed
346          * voltage always-on regulator.
347          */
348         if (!host->vcc)
349                 return 0;
350
351         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
352
353         if (!host->vcc_aux)
354                 return regulator_set_mode(host->vcc, mode);
355
356         if (cardsleep) {
357                 /* VCC can be turned off if card is asleep */
358                 if (sleep)
359                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
360                 else
361                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
362         } else
363                 err = regulator_set_mode(host->vcc, mode);
364         if (err)
365                 return err;
366
367         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
368                 return regulator_set_mode(host->vcc_aux, mode);
369
370         if (sleep)
371                 return regulator_disable(host->vcc_aux);
372         else
373                 return regulator_enable(host->vcc_aux);
374 }
375
376 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
377                                         int vdd, int cardsleep)
378 {
379         return 0;
380 }
381
382 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
383 {
384         struct regulator *reg;
385         int ret = 0;
386         int ocr_value = 0;
387
388         switch (host->id) {
389         case OMAP_MMC1_DEVID:
390                 /* On-chip level shifting via PBIAS0/PBIAS1 */
391                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
392                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
393                 break;
394         case OMAP_MMC2_DEVID:
395         case OMAP_MMC3_DEVID:
396         case OMAP_MMC5_DEVID:
397                 /* Off-chip level shifting, or none */
398                 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
399                 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
400                 break;
401         case OMAP_MMC4_DEVID:
402                 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
403                 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
404         default:
405                 pr_err("MMC%d configuration not supported!\n", host->id);
406                 return -EINVAL;
407         }
408
409         reg = regulator_get(host->dev, "vmmc");
410         if (IS_ERR(reg)) {
411                 dev_dbg(host->dev, "vmmc regulator missing\n");
412                 /*
413                 * HACK: until fixed.c regulator is usable,
414                 * we don't require a main regulator
415                 * for MMC2 or MMC3
416                 */
417                 if (host->id == OMAP_MMC1_DEVID) {
418                         ret = PTR_ERR(reg);
419                         goto err;
420                 }
421         } else {
422                 host->vcc = reg;
423                 ocr_value = mmc_regulator_get_ocrmask(reg);
424                 if (!mmc_slot(host).ocr_mask) {
425                         mmc_slot(host).ocr_mask = ocr_value;
426                 } else {
427                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
428                                 pr_err("MMC%d ocrmask %x is not supported\n",
429                                         host->id, mmc_slot(host).ocr_mask);
430                                 mmc_slot(host).ocr_mask = 0;
431                                 return -EINVAL;
432                         }
433                 }
434
435                 /* Allow an aux regulator */
436                 reg = regulator_get(host->dev, "vmmc_aux");
437                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
438
439                 /* For eMMC do not power off when not in sleep state */
440                 if (mmc_slot(host).no_regulator_off_init)
441                         return 0;
442                 /*
443                 * UGLY HACK:  workaround regulator framework bugs.
444                 * When the bootloader leaves a supply active, it's
445                 * initialized with zero usecount ... and we can't
446                 * disable it without first enabling it.  Until the
447                 * framework is fixed, we need a workaround like this
448                 * (which is safe for MMC, but not in general).
449                 */
450                 if (regulator_is_enabled(host->vcc) > 0) {
451                         regulator_enable(host->vcc);
452                         regulator_disable(host->vcc);
453                 }
454                 if (host->vcc_aux) {
455                         if (regulator_is_enabled(reg) > 0) {
456                                 regulator_enable(reg);
457                                 regulator_disable(reg);
458                         }
459                 }
460         }
461
462         return 0;
463
464 err:
465         mmc_slot(host).set_power = NULL;
466         mmc_slot(host).set_sleep = NULL;
467         return ret;
468 }
469
470 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
471 {
472         regulator_put(host->vcc);
473         regulator_put(host->vcc_aux);
474         mmc_slot(host).set_power = NULL;
475         mmc_slot(host).set_sleep = NULL;
476 }
477
478 static inline int omap_hsmmc_have_reg(void)
479 {
480         return 1;
481 }
482
483 #else
484
485 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
486 {
487         return -EINVAL;
488 }
489
490 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
491 {
492 }
493
494 static inline int omap_hsmmc_have_reg(void)
495 {
496         return 0;
497 }
498
499 #endif
500
501 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
502 {
503         int ret;
504
505         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
506                 if (pdata->slots[0].cover)
507                         pdata->slots[0].get_cover_state =
508                                         omap_hsmmc_get_cover_state;
509                 else
510                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
511                 pdata->slots[0].card_detect_irq =
512                                 gpio_to_irq(pdata->slots[0].switch_pin);
513                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
514                 if (ret)
515                         return ret;
516                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
517                 if (ret)
518                         goto err_free_sp;
519         } else
520                 pdata->slots[0].switch_pin = -EINVAL;
521
522         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
523                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
524                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
525                 if (ret)
526                         goto err_free_cd;
527                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
528                 if (ret)
529                         goto err_free_wp;
530         } else
531                 pdata->slots[0].gpio_wp = -EINVAL;
532
533         return 0;
534
535 err_free_wp:
536         gpio_free(pdata->slots[0].gpio_wp);
537 err_free_cd:
538         if (gpio_is_valid(pdata->slots[0].switch_pin))
539 err_free_sp:
540                 gpio_free(pdata->slots[0].switch_pin);
541         return ret;
542 }
543
544 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
545 {
546         if (gpio_is_valid(pdata->slots[0].gpio_wp))
547                 gpio_free(pdata->slots[0].gpio_wp);
548         if (gpio_is_valid(pdata->slots[0].switch_pin))
549                 gpio_free(pdata->slots[0].switch_pin);
550 }
551
552 /*
553  * Stop clock to the card
554  */
555 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
556 {
557         OMAP_HSMMC_WRITE(host->base, SYSCTL,
558                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
559         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
560                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
561 }
562
563 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
564                                   struct mmc_command *cmd)
565 {
566         unsigned int irq_mask;
567
568         if (host->use_dma)
569                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
570         else
571                 irq_mask = INT_EN_MASK;
572
573         /* Disable timeout for erases */
574         if (cmd->opcode == MMC_ERASE)
575                 irq_mask &= ~DTO_ENABLE;
576
577         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
578         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
579         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
580 }
581
582 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
583 {
584         OMAP_HSMMC_WRITE(host->base, ISE, 0);
585         OMAP_HSMMC_WRITE(host->base, IE, 0);
586         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
587 }
588
589 #ifdef CONFIG_PM
590
591 /*
592  * Restore the MMC host context, if it was lost as result of a
593  * power state change.
594  */
595 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
596 {
597         struct mmc_ios *ios = &host->mmc->ios;
598         struct omap_mmc_platform_data *pdata = host->pdata;
599         int context_loss = 0;
600         u32 hctl, capa, con;
601         u16 dsor = 0;
602         unsigned long timeout;
603
604         if (pdata->get_context_loss_count) {
605                 context_loss = pdata->get_context_loss_count(host->dev);
606                 if (context_loss < 0)
607                         return 1;
608         }
609
610         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
611                 context_loss == host->context_loss ? "not " : "");
612         if (host->context_loss == context_loss)
613                 return 1;
614
615         /* Wait for hardware reset */
616         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
617         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
618                 && time_before(jiffies, timeout))
619                 ;
620
621         /* Do software reset */
622         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
623         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
624         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
625                 && time_before(jiffies, timeout))
626                 ;
627
628         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
629                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
630
631         if (host->id == OMAP_MMC1_DEVID) {
632                 if (host->power_mode != MMC_POWER_OFF &&
633                     (1 << ios->vdd) <= MMC_VDD_23_24)
634                         hctl = SDVS18;
635                 else
636                         hctl = SDVS30;
637                 capa = VS30 | VS18;
638         } else {
639                 hctl = SDVS18;
640                 capa = VS18;
641         }
642
643         OMAP_HSMMC_WRITE(host->base, HCTL,
644                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
645
646         OMAP_HSMMC_WRITE(host->base, CAPA,
647                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
648
649         OMAP_HSMMC_WRITE(host->base, HCTL,
650                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
651
652         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
653         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
654                 && time_before(jiffies, timeout))
655                 ;
656
657         omap_hsmmc_disable_irq(host);
658
659         /* Do not initialize card-specific things if the power is off */
660         if (host->power_mode == MMC_POWER_OFF)
661                 goto out;
662
663         con = OMAP_HSMMC_READ(host->base, CON);
664         switch (ios->bus_width) {
665         case MMC_BUS_WIDTH_8:
666                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
667                 break;
668         case MMC_BUS_WIDTH_4:
669                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
670                 OMAP_HSMMC_WRITE(host->base, HCTL,
671                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
672                 break;
673         case MMC_BUS_WIDTH_1:
674                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
675                 OMAP_HSMMC_WRITE(host->base, HCTL,
676                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
677                 break;
678         }
679
680         if (ios->clock) {
681                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
682                 if (dsor < 1)
683                         dsor = 1;
684
685                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
686                         dsor++;
687
688                 if (dsor > 250)
689                         dsor = 250;
690         }
691
692         OMAP_HSMMC_WRITE(host->base, SYSCTL,
693                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
694         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
695         OMAP_HSMMC_WRITE(host->base, SYSCTL,
696                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
697
698         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
699         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
700                 && time_before(jiffies, timeout))
701                 ;
702
703         OMAP_HSMMC_WRITE(host->base, SYSCTL,
704                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
705
706         con = OMAP_HSMMC_READ(host->base, CON);
707         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
708                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
709         else
710                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
711 out:
712         host->context_loss = context_loss;
713
714         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
715         return 0;
716 }
717
718 /*
719  * Save the MMC host context (store the number of power state changes so far).
720  */
721 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
722 {
723         struct omap_mmc_platform_data *pdata = host->pdata;
724         int context_loss;
725
726         if (pdata->get_context_loss_count) {
727                 context_loss = pdata->get_context_loss_count(host->dev);
728                 if (context_loss < 0)
729                         return;
730                 host->context_loss = context_loss;
731         }
732 }
733
734 #else
735
736 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
737 {
738         return 0;
739 }
740
741 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
742 {
743 }
744
745 #endif
746
747 /*
748  * Send init stream sequence to card
749  * before sending IDLE command
750  */
751 static void send_init_stream(struct omap_hsmmc_host *host)
752 {
753         int reg = 0;
754         unsigned long timeout;
755
756         if (host->protect_card)
757                 return;
758
759         disable_irq(host->irq);
760
761         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
762         OMAP_HSMMC_WRITE(host->base, CON,
763                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
764         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
765
766         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
767         while ((reg != CC) && time_before(jiffies, timeout))
768                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
769
770         OMAP_HSMMC_WRITE(host->base, CON,
771                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
772
773         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
774         OMAP_HSMMC_READ(host->base, STAT);
775
776         enable_irq(host->irq);
777 }
778
779 static inline
780 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
781 {
782         int r = 1;
783
784         if (mmc_slot(host).get_cover_state)
785                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
786         return r;
787 }
788
789 static ssize_t
790 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
791                            char *buf)
792 {
793         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
794         struct omap_hsmmc_host *host = mmc_priv(mmc);
795
796         return sprintf(buf, "%s\n",
797                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
798 }
799
800 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
801
802 static ssize_t
803 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
804                         char *buf)
805 {
806         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
807         struct omap_hsmmc_host *host = mmc_priv(mmc);
808
809         return sprintf(buf, "%s\n", mmc_slot(host).name);
810 }
811
812 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
813
814 /*
815  * Configure the response type and send the cmd.
816  */
817 static void
818 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
819         struct mmc_data *data)
820 {
821         int cmdreg = 0, resptype = 0, cmdtype = 0;
822
823         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
824                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
825         host->cmd = cmd;
826
827         omap_hsmmc_enable_irq(host, cmd);
828
829         host->response_busy = 0;
830         if (cmd->flags & MMC_RSP_PRESENT) {
831                 if (cmd->flags & MMC_RSP_136)
832                         resptype = 1;
833                 else if (cmd->flags & MMC_RSP_BUSY) {
834                         resptype = 3;
835                         host->response_busy = 1;
836                 } else
837                         resptype = 2;
838         }
839
840         /*
841          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
842          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
843          * a val of 0x3, rest 0x0.
844          */
845         if (cmd == host->mrq->stop)
846                 cmdtype = 0x3;
847
848         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
849
850         if (data) {
851                 cmdreg |= DP_SELECT | MSBS | BCE;
852                 if (data->flags & MMC_DATA_READ)
853                         cmdreg |= DDIR;
854                 else
855                         cmdreg &= ~(DDIR);
856         }
857
858         if (host->use_dma)
859                 cmdreg |= DMA_EN;
860
861         host->req_in_progress = 1;
862
863         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
864         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
865 }
866
867 static int
868 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
869 {
870         if (data->flags & MMC_DATA_WRITE)
871                 return DMA_TO_DEVICE;
872         else
873                 return DMA_FROM_DEVICE;
874 }
875
876 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
877 {
878         int dma_ch;
879
880         spin_lock(&host->irq_lock);
881         host->req_in_progress = 0;
882         dma_ch = host->dma_ch;
883         spin_unlock(&host->irq_lock);
884
885         omap_hsmmc_disable_irq(host);
886         /* Do not complete the request if DMA is still in progress */
887         if (mrq->data && host->use_dma && dma_ch != -1)
888                 return;
889         host->mrq = NULL;
890         mmc_request_done(host->mmc, mrq);
891 }
892
893 /*
894  * Notify the transfer complete to MMC core
895  */
896 static void
897 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
898 {
899         if (!data) {
900                 struct mmc_request *mrq = host->mrq;
901
902                 /* TC before CC from CMD6 - don't know why, but it happens */
903                 if (host->cmd && host->cmd->opcode == 6 &&
904                     host->response_busy) {
905                         host->response_busy = 0;
906                         return;
907                 }
908
909                 omap_hsmmc_request_done(host, mrq);
910                 return;
911         }
912
913         host->data = NULL;
914
915         if (!data->error)
916                 data->bytes_xfered += data->blocks * (data->blksz);
917         else
918                 data->bytes_xfered = 0;
919
920         if (!data->stop) {
921                 omap_hsmmc_request_done(host, data->mrq);
922                 return;
923         }
924         omap_hsmmc_start_command(host, data->stop, NULL);
925 }
926
927 /*
928  * Notify the core about command completion
929  */
930 static void
931 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
932 {
933         host->cmd = NULL;
934
935         if (cmd->flags & MMC_RSP_PRESENT) {
936                 if (cmd->flags & MMC_RSP_136) {
937                         /* response type 2 */
938                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
939                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
940                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
941                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
942                 } else {
943                         /* response types 1, 1b, 3, 4, 5, 6 */
944                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
945                 }
946         }
947         if ((host->data == NULL && !host->response_busy) || cmd->error)
948                 omap_hsmmc_request_done(host, cmd->mrq);
949 }
950
951 /*
952  * DMA clean up for command errors
953  */
954 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
955 {
956         int dma_ch;
957
958         host->data->error = errno;
959
960         spin_lock(&host->irq_lock);
961         dma_ch = host->dma_ch;
962         host->dma_ch = -1;
963         spin_unlock(&host->irq_lock);
964
965         if (host->use_dma && dma_ch != -1) {
966                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
967                         host->data->sg_len,
968                         omap_hsmmc_get_dma_dir(host, host->data));
969                 omap_free_dma(dma_ch);
970         }
971         host->data = NULL;
972 }
973
974 /*
975  * Readable error output
976  */
977 #ifdef CONFIG_MMC_DEBUG
978 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
979 {
980         /* --- means reserved bit without definition at documentation */
981         static const char *omap_hsmmc_status_bits[] = {
982                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
983                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
984                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
985                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
986         };
987         char res[256];
988         char *buf = res;
989         int len, i;
990
991         len = sprintf(buf, "MMC IRQ 0x%x :", status);
992         buf += len;
993
994         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
995                 if (status & (1 << i)) {
996                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
997                         buf += len;
998                 }
999
1000         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1001 }
1002 #endif  /* CONFIG_MMC_DEBUG */
1003
1004 /*
1005  * MMC controller internal state machines reset
1006  *
1007  * Used to reset command or data internal state machines, using respectively
1008  *  SRC or SRD bit of SYSCTL register
1009  * Can be called from interrupt context
1010  */
1011 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1012                                                    unsigned long bit)
1013 {
1014         unsigned long i = 0;
1015         unsigned long limit = (loops_per_jiffy *
1016                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1017
1018         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1019                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1020
1021         /*
1022          * OMAP4 ES2 and greater has an updated reset logic.
1023          * Monitor a 0->1 transition first
1024          */
1025         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1026                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1027                                         && (i++ < limit))
1028                         cpu_relax();
1029         }
1030         i = 0;
1031
1032         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1033                 (i++ < limit))
1034                 cpu_relax();
1035
1036         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1037                 dev_err(mmc_dev(host->mmc),
1038                         "Timeout waiting on controller reset in %s\n",
1039                         __func__);
1040 }
1041
1042 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1043 {
1044         struct mmc_data *data;
1045         int end_cmd = 0, end_trans = 0;
1046
1047         if (!host->req_in_progress) {
1048                 do {
1049                         OMAP_HSMMC_WRITE(host->base, STAT, status);
1050                         /* Flush posted write */
1051                         status = OMAP_HSMMC_READ(host->base, STAT);
1052                 } while (status & INT_EN_MASK);
1053                 return;
1054         }
1055
1056         data = host->data;
1057         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1058
1059         if (status & ERR) {
1060 #ifdef CONFIG_MMC_DEBUG
1061                 omap_hsmmc_report_irq(host, status);
1062 #endif
1063                 if ((status & CMD_TIMEOUT) ||
1064                         (status & CMD_CRC)) {
1065                         if (host->cmd) {
1066                                 if (status & CMD_TIMEOUT) {
1067                                         omap_hsmmc_reset_controller_fsm(host,
1068                                                                         SRC);
1069                                         host->cmd->error = -ETIMEDOUT;
1070                                 } else {
1071                                         host->cmd->error = -EILSEQ;
1072                                 }
1073                                 end_cmd = 1;
1074                         }
1075                         if (host->data || host->response_busy) {
1076                                 if (host->data)
1077                                         omap_hsmmc_dma_cleanup(host,
1078                                                                 -ETIMEDOUT);
1079                                 host->response_busy = 0;
1080                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1081                         }
1082                 }
1083                 if ((status & DATA_TIMEOUT) ||
1084                         (status & DATA_CRC)) {
1085                         if (host->data || host->response_busy) {
1086                                 int err = (status & DATA_TIMEOUT) ?
1087                                                 -ETIMEDOUT : -EILSEQ;
1088
1089                                 if (host->data)
1090                                         omap_hsmmc_dma_cleanup(host, err);
1091                                 else
1092                                         host->mrq->cmd->error = err;
1093                                 host->response_busy = 0;
1094                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1095                                 end_trans = 1;
1096                         }
1097                 }
1098                 if (status & CARD_ERR) {
1099                         dev_dbg(mmc_dev(host->mmc),
1100                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1101                         if (host->cmd)
1102                                 end_cmd = 1;
1103                         if (host->data)
1104                                 end_trans = 1;
1105                 }
1106         }
1107
1108         OMAP_HSMMC_WRITE(host->base, STAT, status);
1109
1110         if (end_cmd || ((status & CC) && host->cmd))
1111                 omap_hsmmc_cmd_done(host, host->cmd);
1112         if ((end_trans || (status & TC)) && host->mrq)
1113                 omap_hsmmc_xfer_done(host, data);
1114 }
1115
1116 /*
1117  * MMC controller IRQ handler
1118  */
1119 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1120 {
1121         struct omap_hsmmc_host *host = dev_id;
1122         int status;
1123
1124         status = OMAP_HSMMC_READ(host->base, STAT);
1125         do {
1126                 omap_hsmmc_do_irq(host, status);
1127                 /* Flush posted write */
1128                 status = OMAP_HSMMC_READ(host->base, STAT);
1129         } while (status & INT_EN_MASK);
1130
1131         return IRQ_HANDLED;
1132 }
1133
1134 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1135 {
1136         unsigned long i;
1137
1138         OMAP_HSMMC_WRITE(host->base, HCTL,
1139                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1140         for (i = 0; i < loops_per_jiffy; i++) {
1141                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1142                         break;
1143                 cpu_relax();
1144         }
1145 }
1146
1147 /*
1148  * Switch MMC interface voltage ... only relevant for MMC1.
1149  *
1150  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1151  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1152  * Some chips, like eMMC ones, use internal transceivers.
1153  */
1154 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1155 {
1156         u32 reg_val = 0;
1157         int ret;
1158
1159         /* Disable the clocks */
1160         pm_runtime_put_sync(host->dev);
1161         if (host->got_dbclk)
1162                 clk_disable(host->dbclk);
1163
1164         /* Turn the power off */
1165         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1166
1167         /* Turn the power ON with given VDD 1.8 or 3.0v */
1168         if (!ret)
1169                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1170                                                vdd);
1171         pm_runtime_get_sync(host->dev);
1172         if (host->got_dbclk)
1173                 clk_enable(host->dbclk);
1174
1175         if (ret != 0)
1176                 goto err;
1177
1178         OMAP_HSMMC_WRITE(host->base, HCTL,
1179                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1180         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1181
1182         /*
1183          * If a MMC dual voltage card is detected, the set_ios fn calls
1184          * this fn with VDD bit set for 1.8V. Upon card removal from the
1185          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1186          *
1187          * Cope with a bit of slop in the range ... per data sheets:
1188          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1189          *    but recommended values are 1.71V to 1.89V
1190          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1191          *    but recommended values are 2.7V to 3.3V
1192          *
1193          * Board setup code shouldn't permit anything very out-of-range.
1194          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1195          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1196          */
1197         if ((1 << vdd) <= MMC_VDD_23_24)
1198                 reg_val |= SDVS18;
1199         else
1200                 reg_val |= SDVS30;
1201
1202         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1203         set_sd_bus_power(host);
1204
1205         return 0;
1206 err:
1207         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1208         return ret;
1209 }
1210
1211 /* Protect the card while the cover is open */
1212 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1213 {
1214         if (!mmc_slot(host).get_cover_state)
1215                 return;
1216
1217         host->reqs_blocked = 0;
1218         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1219                 if (host->protect_card) {
1220                         printk(KERN_INFO "%s: cover is closed, "
1221                                          "card is now accessible\n",
1222                                          mmc_hostname(host->mmc));
1223                         host->protect_card = 0;
1224                 }
1225         } else {
1226                 if (!host->protect_card) {
1227                         printk(KERN_INFO "%s: cover is open, "
1228                                          "card is now inaccessible\n",
1229                                          mmc_hostname(host->mmc));
1230                         host->protect_card = 1;
1231                 }
1232         }
1233 }
1234
1235 /*
1236  * Work Item to notify the core about card insertion/removal
1237  */
1238 static void omap_hsmmc_detect(struct work_struct *work)
1239 {
1240         struct omap_hsmmc_host *host =
1241                 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1242         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1243         int carddetect;
1244
1245         if (host->suspended)
1246                 return;
1247
1248         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1249
1250         if (slot->card_detect)
1251                 carddetect = slot->card_detect(host->dev, host->slot_id);
1252         else {
1253                 omap_hsmmc_protect_card(host);
1254                 carddetect = -ENOSYS;
1255         }
1256
1257         if (carddetect)
1258                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1259         else
1260                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1261 }
1262
1263 /*
1264  * ISR for handling card insertion and removal
1265  */
1266 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1267 {
1268         struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1269
1270         if (host->suspended)
1271                 return IRQ_HANDLED;
1272         schedule_work(&host->mmc_carddetect_work);
1273
1274         return IRQ_HANDLED;
1275 }
1276
1277 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1278                                      struct mmc_data *data)
1279 {
1280         int sync_dev;
1281
1282         if (data->flags & MMC_DATA_WRITE)
1283                 sync_dev = host->dma_line_tx;
1284         else
1285                 sync_dev = host->dma_line_rx;
1286         return sync_dev;
1287 }
1288
1289 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1290                                        struct mmc_data *data,
1291                                        struct scatterlist *sgl)
1292 {
1293         int blksz, nblk, dma_ch;
1294
1295         dma_ch = host->dma_ch;
1296         if (data->flags & MMC_DATA_WRITE) {
1297                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1298                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1299                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1300                         sg_dma_address(sgl), 0, 0);
1301         } else {
1302                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1303                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1304                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1305                         sg_dma_address(sgl), 0, 0);
1306         }
1307
1308         blksz = host->data->blksz;
1309         nblk = sg_dma_len(sgl) / blksz;
1310
1311         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1312                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1313                         omap_hsmmc_get_dma_sync_dev(host, data),
1314                         !(data->flags & MMC_DATA_WRITE));
1315
1316         omap_start_dma(dma_ch);
1317 }
1318
1319 /*
1320  * DMA call back function
1321  */
1322 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1323 {
1324         struct omap_hsmmc_host *host = cb_data;
1325         struct mmc_data *data = host->mrq->data;
1326         int dma_ch, req_in_progress;
1327
1328         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1329                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1330                         ch_status);
1331                 return;
1332         }
1333
1334         spin_lock(&host->irq_lock);
1335         if (host->dma_ch < 0) {
1336                 spin_unlock(&host->irq_lock);
1337                 return;
1338         }
1339
1340         host->dma_sg_idx++;
1341         if (host->dma_sg_idx < host->dma_len) {
1342                 /* Fire up the next transfer. */
1343                 omap_hsmmc_config_dma_params(host, data,
1344                                            data->sg + host->dma_sg_idx);
1345                 spin_unlock(&host->irq_lock);
1346                 return;
1347         }
1348
1349         if (!data->host_cookie)
1350                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1351                              omap_hsmmc_get_dma_dir(host, data));
1352
1353         req_in_progress = host->req_in_progress;
1354         dma_ch = host->dma_ch;
1355         host->dma_ch = -1;
1356         spin_unlock(&host->irq_lock);
1357
1358         omap_free_dma(dma_ch);
1359
1360         /* If DMA has finished after TC, complete the request */
1361         if (!req_in_progress) {
1362                 struct mmc_request *mrq = host->mrq;
1363
1364                 host->mrq = NULL;
1365                 mmc_request_done(host->mmc, mrq);
1366         }
1367 }
1368
1369 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1370                                        struct mmc_data *data,
1371                                        struct omap_hsmmc_next *next)
1372 {
1373         int dma_len;
1374
1375         if (!next && data->host_cookie &&
1376             data->host_cookie != host->next_data.cookie) {
1377                 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1378                        " host->next_data.cookie %d\n",
1379                        __func__, data->host_cookie, host->next_data.cookie);
1380                 data->host_cookie = 0;
1381         }
1382
1383         /* Check if next job is already prepared */
1384         if (next ||
1385             (!next && data->host_cookie != host->next_data.cookie)) {
1386                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1387                                      data->sg_len,
1388                                      omap_hsmmc_get_dma_dir(host, data));
1389
1390         } else {
1391                 dma_len = host->next_data.dma_len;
1392                 host->next_data.dma_len = 0;
1393         }
1394
1395
1396         if (dma_len == 0)
1397                 return -EINVAL;
1398
1399         if (next) {
1400                 next->dma_len = dma_len;
1401                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1402         } else
1403                 host->dma_len = dma_len;
1404
1405         return 0;
1406 }
1407
1408 /*
1409  * Routine to configure and start DMA for the MMC card
1410  */
1411 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1412                                         struct mmc_request *req)
1413 {
1414         int dma_ch = 0, ret = 0, i;
1415         struct mmc_data *data = req->data;
1416
1417         /* Sanity check: all the SG entries must be aligned by block size. */
1418         for (i = 0; i < data->sg_len; i++) {
1419                 struct scatterlist *sgl;
1420
1421                 sgl = data->sg + i;
1422                 if (sgl->length % data->blksz)
1423                         return -EINVAL;
1424         }
1425         if ((data->blksz % 4) != 0)
1426                 /* REVISIT: The MMC buffer increments only when MSB is written.
1427                  * Return error for blksz which is non multiple of four.
1428                  */
1429                 return -EINVAL;
1430
1431         BUG_ON(host->dma_ch != -1);
1432
1433         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1434                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1435         if (ret != 0) {
1436                 dev_err(mmc_dev(host->mmc),
1437                         "%s: omap_request_dma() failed with %d\n",
1438                         mmc_hostname(host->mmc), ret);
1439                 return ret;
1440         }
1441         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1442         if (ret)
1443                 return ret;
1444
1445         host->dma_ch = dma_ch;
1446         host->dma_sg_idx = 0;
1447
1448         omap_hsmmc_config_dma_params(host, data, data->sg);
1449
1450         return 0;
1451 }
1452
1453 static void set_data_timeout(struct omap_hsmmc_host *host,
1454                              unsigned int timeout_ns,
1455                              unsigned int timeout_clks)
1456 {
1457         unsigned int timeout, cycle_ns;
1458         uint32_t reg, clkd, dto = 0;
1459
1460         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1461         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1462         if (clkd == 0)
1463                 clkd = 1;
1464
1465         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1466         timeout = timeout_ns / cycle_ns;
1467         timeout += timeout_clks;
1468         if (timeout) {
1469                 while ((timeout & 0x80000000) == 0) {
1470                         dto += 1;
1471                         timeout <<= 1;
1472                 }
1473                 dto = 31 - dto;
1474                 timeout <<= 1;
1475                 if (timeout && dto)
1476                         dto += 1;
1477                 if (dto >= 13)
1478                         dto -= 13;
1479                 else
1480                         dto = 0;
1481                 if (dto > 14)
1482                         dto = 14;
1483         }
1484
1485         reg &= ~DTO_MASK;
1486         reg |= dto << DTO_SHIFT;
1487         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1488 }
1489
1490 /*
1491  * Configure block length for MMC/SD cards and initiate the transfer.
1492  */
1493 static int
1494 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1495 {
1496         int ret;
1497         host->data = req->data;
1498
1499         if (req->data == NULL) {
1500                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1501                 /*
1502                  * Set an arbitrary 100ms data timeout for commands with
1503                  * busy signal.
1504                  */
1505                 if (req->cmd->flags & MMC_RSP_BUSY)
1506                         set_data_timeout(host, 100000000U, 0);
1507                 return 0;
1508         }
1509
1510         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1511                                         | (req->data->blocks << 16));
1512         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1513
1514         if (host->use_dma) {
1515                 ret = omap_hsmmc_start_dma_transfer(host, req);
1516                 if (ret != 0) {
1517                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1518                         return ret;
1519                 }
1520         }
1521         return 0;
1522 }
1523
1524 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1525                                 int err)
1526 {
1527         struct omap_hsmmc_host *host = mmc_priv(mmc);
1528         struct mmc_data *data = mrq->data;
1529
1530         if (host->use_dma) {
1531                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1532                              omap_hsmmc_get_dma_dir(host, data));
1533                 data->host_cookie = 0;
1534         }
1535 }
1536
1537 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1538                                bool is_first_req)
1539 {
1540         struct omap_hsmmc_host *host = mmc_priv(mmc);
1541
1542         if (mrq->data->host_cookie) {
1543                 mrq->data->host_cookie = 0;
1544                 return ;
1545         }
1546
1547         if (host->use_dma)
1548                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1549                                                 &host->next_data))
1550                         mrq->data->host_cookie = 0;
1551 }
1552
1553 /*
1554  * Request function. for read/write operation
1555  */
1556 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1557 {
1558         struct omap_hsmmc_host *host = mmc_priv(mmc);
1559         int err;
1560
1561         BUG_ON(host->req_in_progress);
1562         BUG_ON(host->dma_ch != -1);
1563         if (host->protect_card) {
1564                 if (host->reqs_blocked < 3) {
1565                         /*
1566                          * Ensure the controller is left in a consistent
1567                          * state by resetting the command and data state
1568                          * machines.
1569                          */
1570                         omap_hsmmc_reset_controller_fsm(host, SRD);
1571                         omap_hsmmc_reset_controller_fsm(host, SRC);
1572                         host->reqs_blocked += 1;
1573                 }
1574                 req->cmd->error = -EBADF;
1575                 if (req->data)
1576                         req->data->error = -EBADF;
1577                 req->cmd->retries = 0;
1578                 mmc_request_done(mmc, req);
1579                 return;
1580         } else if (host->reqs_blocked)
1581                 host->reqs_blocked = 0;
1582         WARN_ON(host->mrq != NULL);
1583         host->mrq = req;
1584         err = omap_hsmmc_prepare_data(host, req);
1585         if (err) {
1586                 req->cmd->error = err;
1587                 if (req->data)
1588                         req->data->error = err;
1589                 host->mrq = NULL;
1590                 mmc_request_done(mmc, req);
1591                 return;
1592         }
1593
1594         omap_hsmmc_start_command(host, req->cmd, req->data);
1595 }
1596
1597 /* Routine to configure clock values. Exposed API to core */
1598 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1599 {
1600         struct omap_hsmmc_host *host = mmc_priv(mmc);
1601         u16 dsor = 0;
1602         unsigned long regval;
1603         unsigned long timeout;
1604         u32 con;
1605         int do_send_init_stream = 0;
1606
1607         pm_runtime_get_sync(host->dev);
1608
1609         if (ios->power_mode != host->power_mode) {
1610                 switch (ios->power_mode) {
1611                 case MMC_POWER_OFF:
1612                         mmc_slot(host).set_power(host->dev, host->slot_id,
1613                                                  0, 0);
1614                         host->vdd = 0;
1615                         break;
1616                 case MMC_POWER_UP:
1617                         mmc_slot(host).set_power(host->dev, host->slot_id,
1618                                                  1, ios->vdd);
1619                         host->vdd = ios->vdd;
1620                         break;
1621                 case MMC_POWER_ON:
1622                         do_send_init_stream = 1;
1623                         break;
1624                 }
1625                 host->power_mode = ios->power_mode;
1626         }
1627
1628         /* FIXME: set registers based only on changes to ios */
1629
1630         con = OMAP_HSMMC_READ(host->base, CON);
1631         switch (mmc->ios.bus_width) {
1632         case MMC_BUS_WIDTH_8:
1633                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1634                 break;
1635         case MMC_BUS_WIDTH_4:
1636                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1637                 OMAP_HSMMC_WRITE(host->base, HCTL,
1638                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1639                 break;
1640         case MMC_BUS_WIDTH_1:
1641                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1642                 OMAP_HSMMC_WRITE(host->base, HCTL,
1643                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1644                 break;
1645         }
1646
1647         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1648                 /* Only MMC1 can interface at 3V without some flavor
1649                  * of external transceiver; but they all handle 1.8V.
1650                  */
1651                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1652                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1653                                 /*
1654                                  * The mmc_select_voltage fn of the core does
1655                                  * not seem to set the power_mode to
1656                                  * MMC_POWER_UP upon recalculating the voltage.
1657                                  * vdd 1.8v.
1658                                  */
1659                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1660                                 dev_dbg(mmc_dev(host->mmc),
1661                                                 "Switch operation failed\n");
1662                 }
1663         }
1664
1665         if (ios->clock) {
1666                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1667                 if (dsor < 1)
1668                         dsor = 1;
1669
1670                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1671                         dsor++;
1672
1673                 if (dsor > 250)
1674                         dsor = 250;
1675         }
1676         omap_hsmmc_stop_clock(host);
1677         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1678         regval = regval & ~(CLKD_MASK);
1679         regval = regval | (dsor << 6) | (DTO << 16);
1680         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1681         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1682                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1683
1684         /* Wait till the ICS bit is set */
1685         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1686         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1687                 && time_before(jiffies, timeout))
1688                 msleep(1);
1689
1690         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1691                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1692
1693         if (do_send_init_stream)
1694                 send_init_stream(host);
1695
1696         con = OMAP_HSMMC_READ(host->base, CON);
1697         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1698                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1699         else
1700                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1701
1702         pm_runtime_put_autosuspend(host->dev);
1703 }
1704
1705 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1706 {
1707         struct omap_hsmmc_host *host = mmc_priv(mmc);
1708
1709         if (!mmc_slot(host).card_detect)
1710                 return -ENOSYS;
1711         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1712 }
1713
1714 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1715 {
1716         struct omap_hsmmc_host *host = mmc_priv(mmc);
1717
1718         if (!mmc_slot(host).get_ro)
1719                 return -ENOSYS;
1720         return mmc_slot(host).get_ro(host->dev, 0);
1721 }
1722
1723 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1724 {
1725         struct omap_hsmmc_host *host = mmc_priv(mmc);
1726
1727         if (mmc_slot(host).init_card)
1728                 mmc_slot(host).init_card(card);
1729 }
1730
1731 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1732 {
1733         u32 hctl, capa, value;
1734
1735         /* Only MMC1 supports 3.0V */
1736         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1737                 hctl = SDVS30;
1738                 capa = VS30 | VS18;
1739         } else {
1740                 hctl = SDVS18;
1741                 capa = VS18;
1742         }
1743
1744         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1745         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1746
1747         value = OMAP_HSMMC_READ(host->base, CAPA);
1748         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1749
1750         /* Set the controller to AUTO IDLE mode */
1751         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1752         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1753
1754         /* Set SD bus power bit */
1755         set_sd_bus_power(host);
1756 }
1757
1758 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1759 {
1760         struct omap_hsmmc_host *host = mmc_priv(mmc);
1761
1762         pm_runtime_get_sync(host->dev);
1763
1764         return 0;
1765 }
1766
1767 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1768 {
1769         struct omap_hsmmc_host *host = mmc_priv(mmc);
1770
1771         pm_runtime_mark_last_busy(host->dev);
1772         pm_runtime_put_autosuspend(host->dev);
1773
1774         return 0;
1775 }
1776
1777 static const struct mmc_host_ops omap_hsmmc_ops = {
1778         .enable = omap_hsmmc_enable_fclk,
1779         .disable = omap_hsmmc_disable_fclk,
1780         .post_req = omap_hsmmc_post_req,
1781         .pre_req = omap_hsmmc_pre_req,
1782         .request = omap_hsmmc_request,
1783         .set_ios = omap_hsmmc_set_ios,
1784         .get_cd = omap_hsmmc_get_cd,
1785         .get_ro = omap_hsmmc_get_ro,
1786         .init_card = omap_hsmmc_init_card,
1787         /* NYET -- enable_sdio_irq */
1788 };
1789
1790 #ifdef CONFIG_DEBUG_FS
1791
1792 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1793 {
1794         struct mmc_host *mmc = s->private;
1795         struct omap_hsmmc_host *host = mmc_priv(mmc);
1796         int context_loss = 0;
1797
1798         if (host->pdata->get_context_loss_count)
1799                 context_loss = host->pdata->get_context_loss_count(host->dev);
1800
1801         seq_printf(s, "mmc%d:\n"
1802                         " enabled:\t%d\n"
1803                         " dpm_state:\t%d\n"
1804                         " nesting_cnt:\t%d\n"
1805                         " ctx_loss:\t%d:%d\n"
1806                         "\nregs:\n",
1807                         mmc->index, mmc->enabled ? 1 : 0,
1808                         host->dpm_state, mmc->nesting_cnt,
1809                         host->context_loss, context_loss);
1810
1811         if (host->suspended) {
1812                 seq_printf(s, "host suspended, can't read registers\n");
1813                 return 0;
1814         }
1815
1816         pm_runtime_get_sync(host->dev);
1817
1818         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1819                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1820         seq_printf(s, "CON:\t\t0x%08x\n",
1821                         OMAP_HSMMC_READ(host->base, CON));
1822         seq_printf(s, "HCTL:\t\t0x%08x\n",
1823                         OMAP_HSMMC_READ(host->base, HCTL));
1824         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1825                         OMAP_HSMMC_READ(host->base, SYSCTL));
1826         seq_printf(s, "IE:\t\t0x%08x\n",
1827                         OMAP_HSMMC_READ(host->base, IE));
1828         seq_printf(s, "ISE:\t\t0x%08x\n",
1829                         OMAP_HSMMC_READ(host->base, ISE));
1830         seq_printf(s, "CAPA:\t\t0x%08x\n",
1831                         OMAP_HSMMC_READ(host->base, CAPA));
1832
1833         pm_runtime_mark_last_busy(host->dev);
1834         pm_runtime_put_autosuspend(host->dev);
1835
1836         return 0;
1837 }
1838
1839 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1840 {
1841         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1842 }
1843
1844 static const struct file_operations mmc_regs_fops = {
1845         .open           = omap_hsmmc_regs_open,
1846         .read           = seq_read,
1847         .llseek         = seq_lseek,
1848         .release        = single_release,
1849 };
1850
1851 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1852 {
1853         if (mmc->debugfs_root)
1854                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1855                         mmc, &mmc_regs_fops);
1856 }
1857
1858 #else
1859
1860 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1861 {
1862 }
1863
1864 #endif
1865
1866 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1867 {
1868         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1869         struct mmc_host *mmc;
1870         struct omap_hsmmc_host *host = NULL;
1871         struct resource *res;
1872         int ret, irq;
1873
1874         if (pdata == NULL) {
1875                 dev_err(&pdev->dev, "Platform Data is missing\n");
1876                 return -ENXIO;
1877         }
1878
1879         if (pdata->nr_slots == 0) {
1880                 dev_err(&pdev->dev, "No Slots\n");
1881                 return -ENXIO;
1882         }
1883
1884         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1885         irq = platform_get_irq(pdev, 0);
1886         if (res == NULL || irq < 0)
1887                 return -ENXIO;
1888
1889         res->start += pdata->reg_offset;
1890         res->end += pdata->reg_offset;
1891         res = request_mem_region(res->start, resource_size(res), pdev->name);
1892         if (res == NULL)
1893                 return -EBUSY;
1894
1895         ret = omap_hsmmc_gpio_init(pdata);
1896         if (ret)
1897                 goto err;
1898
1899         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1900         if (!mmc) {
1901                 ret = -ENOMEM;
1902                 goto err_alloc;
1903         }
1904
1905         host            = mmc_priv(mmc);
1906         host->mmc       = mmc;
1907         host->pdata     = pdata;
1908         host->dev       = &pdev->dev;
1909         host->use_dma   = 1;
1910         host->dev->dma_mask = &pdata->dma_mask;
1911         host->dma_ch    = -1;
1912         host->irq       = irq;
1913         host->id        = pdev->id;
1914         host->slot_id   = 0;
1915         host->mapbase   = res->start;
1916         host->base      = ioremap(host->mapbase, SZ_4K);
1917         host->power_mode = MMC_POWER_OFF;
1918         host->next_data.cookie = 1;
1919
1920         platform_set_drvdata(pdev, host);
1921         INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1922
1923         mmc->ops        = &omap_hsmmc_ops;
1924
1925         /*
1926          * If regulator_disable can only put vcc_aux to sleep then there is
1927          * no off state.
1928          */
1929         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1930                 mmc_slot(host).no_off = 1;
1931
1932         mmc->f_min      = 400000;
1933         mmc->f_max      = 52000000;
1934
1935         spin_lock_init(&host->irq_lock);
1936
1937         host->fclk = clk_get(&pdev->dev, "fck");
1938         if (IS_ERR(host->fclk)) {
1939                 ret = PTR_ERR(host->fclk);
1940                 host->fclk = NULL;
1941                 goto err1;
1942         }
1943
1944         omap_hsmmc_context_save(host);
1945
1946         mmc->caps |= MMC_CAP_DISABLE;
1947
1948         pm_runtime_enable(host->dev);
1949         pm_runtime_get_sync(host->dev);
1950         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1951         pm_runtime_use_autosuspend(host->dev);
1952
1953         if (cpu_is_omap2430()) {
1954                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1955                 /*
1956                  * MMC can still work without debounce clock.
1957                  */
1958                 if (IS_ERR(host->dbclk))
1959                         dev_warn(mmc_dev(host->mmc),
1960                                 "Failed to get debounce clock\n");
1961                 else
1962                         host->got_dbclk = 1;
1963
1964                 if (host->got_dbclk)
1965                         if (clk_enable(host->dbclk) != 0)
1966                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1967                                                         " clk failed\n");
1968         }
1969
1970         /* Since we do only SG emulation, we can have as many segs
1971          * as we want. */
1972         mmc->max_segs = 1024;
1973
1974         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1975         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1976         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1977         mmc->max_seg_size = mmc->max_req_size;
1978
1979         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1980                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1981
1982         mmc->caps |= mmc_slot(host).caps;
1983         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1984                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1985
1986         if (mmc_slot(host).nonremovable)
1987                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1988
1989         omap_hsmmc_conf_bus_power(host);
1990
1991         /* Select DMA lines */
1992         switch (host->id) {
1993         case OMAP_MMC1_DEVID:
1994                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1995                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1996                 break;
1997         case OMAP_MMC2_DEVID:
1998                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1999                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2000                 break;
2001         case OMAP_MMC3_DEVID:
2002                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2003                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2004                 break;
2005         case OMAP_MMC4_DEVID:
2006                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2007                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2008                 break;
2009         case OMAP_MMC5_DEVID:
2010                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2011                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2012                 break;
2013         default:
2014                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2015                 goto err_irq;
2016         }
2017
2018         /* Request IRQ for MMC operations */
2019         ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2020                         mmc_hostname(mmc), host);
2021         if (ret) {
2022                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2023                 goto err_irq;
2024         }
2025
2026         if (pdata->init != NULL) {
2027                 if (pdata->init(&pdev->dev) != 0) {
2028                         dev_dbg(mmc_dev(host->mmc),
2029                                 "Unable to configure MMC IRQs\n");
2030                         goto err_irq_cd_init;
2031                 }
2032         }
2033
2034         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2035                 ret = omap_hsmmc_reg_get(host);
2036                 if (ret)
2037                         goto err_reg;
2038                 host->use_reg = 1;
2039         }
2040
2041         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2042
2043         /* Request IRQ for card detect */
2044         if ((mmc_slot(host).card_detect_irq)) {
2045                 ret = request_irq(mmc_slot(host).card_detect_irq,
2046                                   omap_hsmmc_cd_handler,
2047                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2048                                           | IRQF_DISABLED,
2049                                   mmc_hostname(mmc), host);
2050                 if (ret) {
2051                         dev_dbg(mmc_dev(host->mmc),
2052                                 "Unable to grab MMC CD IRQ\n");
2053                         goto err_irq_cd;
2054                 }
2055                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2056                 pdata->resume = omap_hsmmc_resume_cdirq;
2057         }
2058
2059         omap_hsmmc_disable_irq(host);
2060
2061         omap_hsmmc_protect_card(host);
2062
2063         mmc_add_host(mmc);
2064
2065         if (mmc_slot(host).name != NULL) {
2066                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2067                 if (ret < 0)
2068                         goto err_slot_name;
2069         }
2070         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2071                 ret = device_create_file(&mmc->class_dev,
2072                                         &dev_attr_cover_switch);
2073                 if (ret < 0)
2074                         goto err_slot_name;
2075         }
2076
2077         omap_hsmmc_debugfs(mmc);
2078         pm_runtime_mark_last_busy(host->dev);
2079         pm_runtime_put_autosuspend(host->dev);
2080
2081         return 0;
2082
2083 err_slot_name:
2084         mmc_remove_host(mmc);
2085         free_irq(mmc_slot(host).card_detect_irq, host);
2086 err_irq_cd:
2087         if (host->use_reg)
2088                 omap_hsmmc_reg_put(host);
2089 err_reg:
2090         if (host->pdata->cleanup)
2091                 host->pdata->cleanup(&pdev->dev);
2092 err_irq_cd_init:
2093         free_irq(host->irq, host);
2094 err_irq:
2095         pm_runtime_mark_last_busy(host->dev);
2096         pm_runtime_put_autosuspend(host->dev);
2097         clk_put(host->fclk);
2098         if (host->got_dbclk) {
2099                 clk_disable(host->dbclk);
2100                 clk_put(host->dbclk);
2101         }
2102 err1:
2103         iounmap(host->base);
2104         platform_set_drvdata(pdev, NULL);
2105         mmc_free_host(mmc);
2106 err_alloc:
2107         omap_hsmmc_gpio_free(pdata);
2108 err:
2109         release_mem_region(res->start, resource_size(res));
2110         return ret;
2111 }
2112
2113 static int omap_hsmmc_remove(struct platform_device *pdev)
2114 {
2115         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2116         struct resource *res;
2117
2118         if (host) {
2119                 pm_runtime_get_sync(host->dev);
2120                 mmc_remove_host(host->mmc);
2121                 if (host->use_reg)
2122                         omap_hsmmc_reg_put(host);
2123                 if (host->pdata->cleanup)
2124                         host->pdata->cleanup(&pdev->dev);
2125                 free_irq(host->irq, host);
2126                 if (mmc_slot(host).card_detect_irq)
2127                         free_irq(mmc_slot(host).card_detect_irq, host);
2128                 flush_work_sync(&host->mmc_carddetect_work);
2129
2130                 pm_runtime_put_sync(host->dev);
2131                 pm_runtime_disable(host->dev);
2132                 clk_put(host->fclk);
2133                 if (host->got_dbclk) {
2134                         clk_disable(host->dbclk);
2135                         clk_put(host->dbclk);
2136                 }
2137
2138                 mmc_free_host(host->mmc);
2139                 iounmap(host->base);
2140                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2141         }
2142
2143         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2144         if (res)
2145                 release_mem_region(res->start, resource_size(res));
2146         platform_set_drvdata(pdev, NULL);
2147
2148         return 0;
2149 }
2150
2151 #ifdef CONFIG_PM
2152 static int omap_hsmmc_suspend(struct device *dev)
2153 {
2154         int ret = 0;
2155         struct platform_device *pdev = to_platform_device(dev);
2156         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2157
2158         if (host && host->suspended)
2159                 return 0;
2160
2161         if (host) {
2162                 pm_runtime_get_sync(host->dev);
2163                 host->suspended = 1;
2164                 if (host->pdata->suspend) {
2165                         ret = host->pdata->suspend(&pdev->dev,
2166                                                         host->slot_id);
2167                         if (ret) {
2168                                 dev_dbg(mmc_dev(host->mmc),
2169                                         "Unable to handle MMC board"
2170                                         " level suspend\n");
2171                                 host->suspended = 0;
2172                                 return ret;
2173                         }
2174                 }
2175                 cancel_work_sync(&host->mmc_carddetect_work);
2176                 ret = mmc_suspend_host(host->mmc);
2177
2178                 if (ret == 0) {
2179                         omap_hsmmc_disable_irq(host);
2180                         OMAP_HSMMC_WRITE(host->base, HCTL,
2181                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2182                         if (host->got_dbclk)
2183                                 clk_disable(host->dbclk);
2184                 } else {
2185                         host->suspended = 0;
2186                         if (host->pdata->resume) {
2187                                 ret = host->pdata->resume(&pdev->dev,
2188                                                           host->slot_id);
2189                                 if (ret)
2190                                         dev_dbg(mmc_dev(host->mmc),
2191                                                 "Unmask interrupt failed\n");
2192                         }
2193                 }
2194                 pm_runtime_put_sync(host->dev);
2195         }
2196         return ret;
2197 }
2198
2199 /* Routine to resume the MMC device */
2200 static int omap_hsmmc_resume(struct device *dev)
2201 {
2202         int ret = 0;
2203         struct platform_device *pdev = to_platform_device(dev);
2204         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2205
2206         if (host && !host->suspended)
2207                 return 0;
2208
2209         if (host) {
2210                 pm_runtime_get_sync(host->dev);
2211
2212                 if (host->got_dbclk)
2213                         clk_enable(host->dbclk);
2214
2215                 omap_hsmmc_conf_bus_power(host);
2216
2217                 if (host->pdata->resume) {
2218                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2219                         if (ret)
2220                                 dev_dbg(mmc_dev(host->mmc),
2221                                         "Unmask interrupt failed\n");
2222                 }
2223
2224                 omap_hsmmc_protect_card(host);
2225
2226                 /* Notify the core to resume the host */
2227                 ret = mmc_resume_host(host->mmc);
2228                 if (ret == 0)
2229                         host->suspended = 0;
2230
2231                 pm_runtime_mark_last_busy(host->dev);
2232                 pm_runtime_put_autosuspend(host->dev);
2233         }
2234
2235         return ret;
2236
2237 }
2238
2239 #else
2240 #define omap_hsmmc_suspend      NULL
2241 #define omap_hsmmc_resume               NULL
2242 #endif
2243
2244 static int omap_hsmmc_runtime_suspend(struct device *dev)
2245 {
2246         struct omap_hsmmc_host *host;
2247
2248         host = platform_get_drvdata(to_platform_device(dev));
2249         omap_hsmmc_context_save(host);
2250         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2251
2252         return 0;
2253 }
2254
2255 static int omap_hsmmc_runtime_resume(struct device *dev)
2256 {
2257         struct omap_hsmmc_host *host;
2258
2259         host = platform_get_drvdata(to_platform_device(dev));
2260         omap_hsmmc_context_restore(host);
2261         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2262
2263         return 0;
2264 }
2265
2266 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2267         .suspend        = omap_hsmmc_suspend,
2268         .resume         = omap_hsmmc_resume,
2269         .runtime_suspend = omap_hsmmc_runtime_suspend,
2270         .runtime_resume = omap_hsmmc_runtime_resume,
2271 };
2272
2273 static struct platform_driver omap_hsmmc_driver = {
2274         .remove         = omap_hsmmc_remove,
2275         .driver         = {
2276                 .name = DRIVER_NAME,
2277                 .owner = THIS_MODULE,
2278                 .pm = &omap_hsmmc_dev_pm_ops,
2279         },
2280 };
2281
2282 static int __init omap_hsmmc_init(void)
2283 {
2284         /* Register the MMC driver */
2285         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2286 }
2287
2288 static void __exit omap_hsmmc_cleanup(void)
2289 {
2290         /* Unregister MMC driver */
2291         platform_driver_unregister(&omap_hsmmc_driver);
2292 }
2293
2294 module_init(omap_hsmmc_init);
2295 module_exit(omap_hsmmc_cleanup);
2296
2297 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2298 MODULE_LICENSE("GPL");
2299 MODULE_ALIAS("platform:" DRIVER_NAME);
2300 MODULE_AUTHOR("Texas Instruments Inc");