mmc: dw_mmc: handle "no CRC status" error
[linux-2.6.git] / drivers / mmc / host / dw_mmc.c
1 /*
2  * Synopsys DesignWare Multimedia Card Interface driver
3  *  (Based on NXP driver for lpc 31xx)
4  *
5  * Copyright (C) 2009 NXP Semiconductors
6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/seq_file.h>
27 #include <linux/slab.h>
28 #include <linux/stat.h>
29 #include <linux/delay.h>
30 #include <linux/irq.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/dw_mmc.h>
34 #include <linux/bitops.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/workqueue.h>
37
38 #include "dw_mmc.h"
39
40 /* Common flag combinations */
41 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
42                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
43                                  SDMMC_INT_EBE)
44 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
45                                  SDMMC_INT_RESP_ERR)
46 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
47                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
48 #define DW_MCI_SEND_STATUS      1
49 #define DW_MCI_RECV_STATUS      2
50 #define DW_MCI_DMA_THRESHOLD    16
51
52 #ifdef CONFIG_MMC_DW_IDMAC
53 struct idmac_desc {
54         u32             des0;   /* Control Descriptor */
55 #define IDMAC_DES0_DIC  BIT(1)
56 #define IDMAC_DES0_LD   BIT(2)
57 #define IDMAC_DES0_FD   BIT(3)
58 #define IDMAC_DES0_CH   BIT(4)
59 #define IDMAC_DES0_ER   BIT(5)
60 #define IDMAC_DES0_CES  BIT(30)
61 #define IDMAC_DES0_OWN  BIT(31)
62
63         u32             des1;   /* Buffer sizes */
64 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
65         ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
66
67         u32             des2;   /* buffer 1 physical address */
68
69         u32             des3;   /* buffer 2 physical address */
70 };
71 #endif /* CONFIG_MMC_DW_IDMAC */
72
73 /**
74  * struct dw_mci_slot - MMC slot state
75  * @mmc: The mmc_host representing this slot.
76  * @host: The MMC controller this slot is using.
77  * @ctype: Card type for this slot.
78  * @mrq: mmc_request currently being processed or waiting to be
79  *      processed, or NULL when the slot is idle.
80  * @queue_node: List node for placing this node in the @queue list of
81  *      &struct dw_mci.
82  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
83  * @flags: Random state bits associated with the slot.
84  * @id: Number of this slot.
85  * @last_detect_state: Most recently observed card detect state.
86  */
87 struct dw_mci_slot {
88         struct mmc_host         *mmc;
89         struct dw_mci           *host;
90
91         u32                     ctype;
92
93         struct mmc_request      *mrq;
94         struct list_head        queue_node;
95
96         unsigned int            clock;
97         unsigned long           flags;
98 #define DW_MMC_CARD_PRESENT     0
99 #define DW_MMC_CARD_NEED_INIT   1
100         int                     id;
101         int                     last_detect_state;
102 };
103
104 static struct workqueue_struct *dw_mci_card_workqueue;
105
106 #if defined(CONFIG_DEBUG_FS)
107 static int dw_mci_req_show(struct seq_file *s, void *v)
108 {
109         struct dw_mci_slot *slot = s->private;
110         struct mmc_request *mrq;
111         struct mmc_command *cmd;
112         struct mmc_command *stop;
113         struct mmc_data *data;
114
115         /* Make sure we get a consistent snapshot */
116         spin_lock_bh(&slot->host->lock);
117         mrq = slot->mrq;
118
119         if (mrq) {
120                 cmd = mrq->cmd;
121                 data = mrq->data;
122                 stop = mrq->stop;
123
124                 if (cmd)
125                         seq_printf(s,
126                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
127                                    cmd->opcode, cmd->arg, cmd->flags,
128                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
129                                    cmd->resp[2], cmd->error);
130                 if (data)
131                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
132                                    data->bytes_xfered, data->blocks,
133                                    data->blksz, data->flags, data->error);
134                 if (stop)
135                         seq_printf(s,
136                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
137                                    stop->opcode, stop->arg, stop->flags,
138                                    stop->resp[0], stop->resp[1], stop->resp[2],
139                                    stop->resp[2], stop->error);
140         }
141
142         spin_unlock_bh(&slot->host->lock);
143
144         return 0;
145 }
146
147 static int dw_mci_req_open(struct inode *inode, struct file *file)
148 {
149         return single_open(file, dw_mci_req_show, inode->i_private);
150 }
151
152 static const struct file_operations dw_mci_req_fops = {
153         .owner          = THIS_MODULE,
154         .open           = dw_mci_req_open,
155         .read           = seq_read,
156         .llseek         = seq_lseek,
157         .release        = single_release,
158 };
159
160 static int dw_mci_regs_show(struct seq_file *s, void *v)
161 {
162         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
163         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
164         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
165         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
166         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
167         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
168
169         return 0;
170 }
171
172 static int dw_mci_regs_open(struct inode *inode, struct file *file)
173 {
174         return single_open(file, dw_mci_regs_show, inode->i_private);
175 }
176
177 static const struct file_operations dw_mci_regs_fops = {
178         .owner          = THIS_MODULE,
179         .open           = dw_mci_regs_open,
180         .read           = seq_read,
181         .llseek         = seq_lseek,
182         .release        = single_release,
183 };
184
185 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
186 {
187         struct mmc_host *mmc = slot->mmc;
188         struct dw_mci *host = slot->host;
189         struct dentry *root;
190         struct dentry *node;
191
192         root = mmc->debugfs_root;
193         if (!root)
194                 return;
195
196         node = debugfs_create_file("regs", S_IRUSR, root, host,
197                                    &dw_mci_regs_fops);
198         if (!node)
199                 goto err;
200
201         node = debugfs_create_file("req", S_IRUSR, root, slot,
202                                    &dw_mci_req_fops);
203         if (!node)
204                 goto err;
205
206         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
207         if (!node)
208                 goto err;
209
210         node = debugfs_create_x32("pending_events", S_IRUSR, root,
211                                   (u32 *)&host->pending_events);
212         if (!node)
213                 goto err;
214
215         node = debugfs_create_x32("completed_events", S_IRUSR, root,
216                                   (u32 *)&host->completed_events);
217         if (!node)
218                 goto err;
219
220         return;
221
222 err:
223         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
224 }
225 #endif /* defined(CONFIG_DEBUG_FS) */
226
227 static void dw_mci_set_timeout(struct dw_mci *host)
228 {
229         /* timeout (maximum) */
230         mci_writel(host, TMOUT, 0xffffffff);
231 }
232
233 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
234 {
235         struct mmc_data *data;
236         u32 cmdr;
237         cmd->error = -EINPROGRESS;
238
239         cmdr = cmd->opcode;
240
241         if (cmdr == MMC_STOP_TRANSMISSION)
242                 cmdr |= SDMMC_CMD_STOP;
243         else
244                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
245
246         if (cmd->flags & MMC_RSP_PRESENT) {
247                 /* We expect a response, so set this bit */
248                 cmdr |= SDMMC_CMD_RESP_EXP;
249                 if (cmd->flags & MMC_RSP_136)
250                         cmdr |= SDMMC_CMD_RESP_LONG;
251         }
252
253         if (cmd->flags & MMC_RSP_CRC)
254                 cmdr |= SDMMC_CMD_RESP_CRC;
255
256         data = cmd->data;
257         if (data) {
258                 cmdr |= SDMMC_CMD_DAT_EXP;
259                 if (data->flags & MMC_DATA_STREAM)
260                         cmdr |= SDMMC_CMD_STRM_MODE;
261                 if (data->flags & MMC_DATA_WRITE)
262                         cmdr |= SDMMC_CMD_DAT_WR;
263         }
264
265         return cmdr;
266 }
267
268 static void dw_mci_start_command(struct dw_mci *host,
269                                  struct mmc_command *cmd, u32 cmd_flags)
270 {
271         host->cmd = cmd;
272         dev_vdbg(&host->pdev->dev,
273                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
274                  cmd->arg, cmd_flags);
275
276         mci_writel(host, CMDARG, cmd->arg);
277         wmb();
278
279         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
280 }
281
282 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
283 {
284         dw_mci_start_command(host, data->stop, host->stop_cmdr);
285 }
286
287 /* DMA interface functions */
288 static void dw_mci_stop_dma(struct dw_mci *host)
289 {
290         if (host->using_dma) {
291                 host->dma_ops->stop(host);
292                 host->dma_ops->cleanup(host);
293         } else {
294                 /* Data transfer was stopped by the interrupt handler */
295                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
296         }
297 }
298
299 #ifdef CONFIG_MMC_DW_IDMAC
300 static void dw_mci_dma_cleanup(struct dw_mci *host)
301 {
302         struct mmc_data *data = host->data;
303
304         if (data)
305                 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
306                              ((data->flags & MMC_DATA_WRITE)
307                               ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
308 }
309
310 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
311 {
312         u32 temp;
313
314         /* Disable and reset the IDMAC interface */
315         temp = mci_readl(host, CTRL);
316         temp &= ~SDMMC_CTRL_USE_IDMAC;
317         temp |= SDMMC_CTRL_DMA_RESET;
318         mci_writel(host, CTRL, temp);
319
320         /* Stop the IDMAC running */
321         temp = mci_readl(host, BMOD);
322         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
323         mci_writel(host, BMOD, temp);
324 }
325
326 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
327 {
328         struct mmc_data *data = host->data;
329
330         dev_vdbg(&host->pdev->dev, "DMA complete\n");
331
332         host->dma_ops->cleanup(host);
333
334         /*
335          * If the card was removed, data will be NULL. No point in trying to
336          * send the stop command or waiting for NBUSY in this case.
337          */
338         if (data) {
339                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
340                 tasklet_schedule(&host->tasklet);
341         }
342 }
343
344 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
345                                     unsigned int sg_len)
346 {
347         int i;
348         struct idmac_desc *desc = host->sg_cpu;
349
350         for (i = 0; i < sg_len; i++, desc++) {
351                 unsigned int length = sg_dma_len(&data->sg[i]);
352                 u32 mem_addr = sg_dma_address(&data->sg[i]);
353
354                 /* Set the OWN bit and disable interrupts for this descriptor */
355                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
356
357                 /* Buffer length */
358                 IDMAC_SET_BUFFER1_SIZE(desc, length);
359
360                 /* Physical address to DMA to/from */
361                 desc->des2 = mem_addr;
362         }
363
364         /* Set first descriptor */
365         desc = host->sg_cpu;
366         desc->des0 |= IDMAC_DES0_FD;
367
368         /* Set last descriptor */
369         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
370         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
371         desc->des0 |= IDMAC_DES0_LD;
372
373         wmb();
374 }
375
376 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
377 {
378         u32 temp;
379
380         dw_mci_translate_sglist(host, host->data, sg_len);
381
382         /* Select IDMAC interface */
383         temp = mci_readl(host, CTRL);
384         temp |= SDMMC_CTRL_USE_IDMAC;
385         mci_writel(host, CTRL, temp);
386
387         wmb();
388
389         /* Enable the IDMAC */
390         temp = mci_readl(host, BMOD);
391         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
392         mci_writel(host, BMOD, temp);
393
394         /* Start it running */
395         mci_writel(host, PLDMND, 1);
396 }
397
398 static int dw_mci_idmac_init(struct dw_mci *host)
399 {
400         struct idmac_desc *p;
401         int i;
402
403         /* Number of descriptors in the ring buffer */
404         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
405
406         /* Forward link the descriptor list */
407         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
408                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
409
410         /* Set the last descriptor as the end-of-ring descriptor */
411         p->des3 = host->sg_dma;
412         p->des0 = IDMAC_DES0_ER;
413
414         /* Mask out interrupts - get Tx & Rx complete only */
415         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
416                    SDMMC_IDMAC_INT_TI);
417
418         /* Set the descriptor base address */
419         mci_writel(host, DBADDR, host->sg_dma);
420         return 0;
421 }
422
423 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
424         .init = dw_mci_idmac_init,
425         .start = dw_mci_idmac_start_dma,
426         .stop = dw_mci_idmac_stop_dma,
427         .complete = dw_mci_idmac_complete_dma,
428         .cleanup = dw_mci_dma_cleanup,
429 };
430 #endif /* CONFIG_MMC_DW_IDMAC */
431
432 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
433 {
434         struct scatterlist *sg;
435         unsigned int i, direction, sg_len;
436         u32 temp;
437
438         host->using_dma = 0;
439
440         /* If we don't have a channel, we can't do DMA */
441         if (!host->use_dma)
442                 return -ENODEV;
443
444         /*
445          * We don't do DMA on "complex" transfers, i.e. with
446          * non-word-aligned buffers or lengths. Also, we don't bother
447          * with all the DMA setup overhead for short transfers.
448          */
449         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
450                 return -EINVAL;
451         if (data->blksz & 3)
452                 return -EINVAL;
453
454         for_each_sg(data->sg, sg, data->sg_len, i) {
455                 if (sg->offset & 3 || sg->length & 3)
456                         return -EINVAL;
457         }
458
459         host->using_dma = 1;
460
461         if (data->flags & MMC_DATA_READ)
462                 direction = DMA_FROM_DEVICE;
463         else
464                 direction = DMA_TO_DEVICE;
465
466         sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
467                             direction);
468
469         dev_vdbg(&host->pdev->dev,
470                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
471                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
472                  sg_len);
473
474         /* Enable the DMA interface */
475         temp = mci_readl(host, CTRL);
476         temp |= SDMMC_CTRL_DMA_ENABLE;
477         mci_writel(host, CTRL, temp);
478
479         /* Disable RX/TX IRQs, let DMA handle it */
480         temp = mci_readl(host, INTMASK);
481         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
482         mci_writel(host, INTMASK, temp);
483
484         host->dma_ops->start(host, sg_len);
485
486         return 0;
487 }
488
489 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
490 {
491         u32 temp;
492
493         data->error = -EINPROGRESS;
494
495         WARN_ON(host->data);
496         host->sg = NULL;
497         host->data = data;
498
499         if (data->flags & MMC_DATA_READ)
500                 host->dir_status = DW_MCI_RECV_STATUS;
501         else
502                 host->dir_status = DW_MCI_SEND_STATUS;
503
504         if (dw_mci_submit_data_dma(host, data)) {
505                 host->sg = data->sg;
506                 host->pio_offset = 0;
507                 host->part_buf_start = 0;
508                 host->part_buf_count = 0;
509
510                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
511                 temp = mci_readl(host, INTMASK);
512                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
513                 mci_writel(host, INTMASK, temp);
514
515                 temp = mci_readl(host, CTRL);
516                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
517                 mci_writel(host, CTRL, temp);
518         }
519 }
520
521 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
522 {
523         struct dw_mci *host = slot->host;
524         unsigned long timeout = jiffies + msecs_to_jiffies(500);
525         unsigned int cmd_status = 0;
526
527         mci_writel(host, CMDARG, arg);
528         wmb();
529         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
530
531         while (time_before(jiffies, timeout)) {
532                 cmd_status = mci_readl(host, CMD);
533                 if (!(cmd_status & SDMMC_CMD_START))
534                         return;
535         }
536         dev_err(&slot->mmc->class_dev,
537                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
538                 cmd, arg, cmd_status);
539 }
540
541 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
542 {
543         struct dw_mci *host = slot->host;
544         u32 div;
545
546         if (slot->clock != host->current_speed) {
547                 if (host->bus_hz % slot->clock)
548                         /*
549                          * move the + 1 after the divide to prevent
550                          * over-clocking the card.
551                          */
552                         div = ((host->bus_hz / slot->clock) >> 1) + 1;
553                 else
554                         div = (host->bus_hz  / slot->clock) >> 1;
555
556                 dev_info(&slot->mmc->class_dev,
557                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
558                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
559                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
560
561                 /* disable clock */
562                 mci_writel(host, CLKENA, 0);
563                 mci_writel(host, CLKSRC, 0);
564
565                 /* inform CIU */
566                 mci_send_cmd(slot,
567                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
568
569                 /* set clock to desired speed */
570                 mci_writel(host, CLKDIV, div);
571
572                 /* inform CIU */
573                 mci_send_cmd(slot,
574                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
575
576                 /* enable clock */
577                 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
578                            SDMMC_CLKEN_LOW_PWR);
579
580                 /* inform CIU */
581                 mci_send_cmd(slot,
582                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
583
584                 host->current_speed = slot->clock;
585         }
586
587         /* Set the current slot bus width */
588         mci_writel(host, CTYPE, (slot->ctype << slot->id));
589 }
590
591 static void dw_mci_start_request(struct dw_mci *host,
592                                  struct dw_mci_slot *slot)
593 {
594         struct mmc_request *mrq;
595         struct mmc_command *cmd;
596         struct mmc_data *data;
597         u32 cmdflags;
598
599         mrq = slot->mrq;
600         if (host->pdata->select_slot)
601                 host->pdata->select_slot(slot->id);
602
603         /* Slot specific timing and width adjustment */
604         dw_mci_setup_bus(slot);
605
606         host->cur_slot = slot;
607         host->mrq = mrq;
608
609         host->pending_events = 0;
610         host->completed_events = 0;
611         host->data_status = 0;
612
613         data = mrq->data;
614         if (data) {
615                 dw_mci_set_timeout(host);
616                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
617                 mci_writel(host, BLKSIZ, data->blksz);
618         }
619
620         cmd = mrq->cmd;
621         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
622
623         /* this is the first command, send the initialization clock */
624         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
625                 cmdflags |= SDMMC_CMD_INIT;
626
627         if (data) {
628                 dw_mci_submit_data(host, data);
629                 wmb();
630         }
631
632         dw_mci_start_command(host, cmd, cmdflags);
633
634         if (mrq->stop)
635                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
636 }
637
638 /* must be called with host->lock held */
639 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
640                                  struct mmc_request *mrq)
641 {
642         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
643                  host->state);
644
645         slot->mrq = mrq;
646
647         if (host->state == STATE_IDLE) {
648                 host->state = STATE_SENDING_CMD;
649                 dw_mci_start_request(host, slot);
650         } else {
651                 list_add_tail(&slot->queue_node, &host->queue);
652         }
653 }
654
655 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
656 {
657         struct dw_mci_slot *slot = mmc_priv(mmc);
658         struct dw_mci *host = slot->host;
659
660         WARN_ON(slot->mrq);
661
662         /*
663          * The check for card presence and queueing of the request must be
664          * atomic, otherwise the card could be removed in between and the
665          * request wouldn't fail until another card was inserted.
666          */
667         spin_lock_bh(&host->lock);
668
669         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
670                 spin_unlock_bh(&host->lock);
671                 mrq->cmd->error = -ENOMEDIUM;
672                 mmc_request_done(mmc, mrq);
673                 return;
674         }
675
676         dw_mci_queue_request(host, slot, mrq);
677
678         spin_unlock_bh(&host->lock);
679 }
680
681 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
682 {
683         struct dw_mci_slot *slot = mmc_priv(mmc);
684         u32 regs;
685
686         /* set default 1 bit mode */
687         slot->ctype = SDMMC_CTYPE_1BIT;
688
689         switch (ios->bus_width) {
690         case MMC_BUS_WIDTH_1:
691                 slot->ctype = SDMMC_CTYPE_1BIT;
692                 break;
693         case MMC_BUS_WIDTH_4:
694                 slot->ctype = SDMMC_CTYPE_4BIT;
695                 break;
696         case MMC_BUS_WIDTH_8:
697                 slot->ctype = SDMMC_CTYPE_8BIT;
698                 break;
699         }
700
701         /* DDR mode set */
702         if (ios->ddr) {
703                 regs = mci_readl(slot->host, UHS_REG);
704                 regs |= (0x1 << slot->id) << 16;
705                 mci_writel(slot->host, UHS_REG, regs);
706         }
707
708         if (ios->clock) {
709                 /*
710                  * Use mirror of ios->clock to prevent race with mmc
711                  * core ios update when finding the minimum.
712                  */
713                 slot->clock = ios->clock;
714         }
715
716         switch (ios->power_mode) {
717         case MMC_POWER_UP:
718                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
719                 break;
720         default:
721                 break;
722         }
723 }
724
725 static int dw_mci_get_ro(struct mmc_host *mmc)
726 {
727         int read_only;
728         struct dw_mci_slot *slot = mmc_priv(mmc);
729         struct dw_mci_board *brd = slot->host->pdata;
730
731         /* Use platform get_ro function, else try on board write protect */
732         if (brd->get_ro)
733                 read_only = brd->get_ro(slot->id);
734         else
735                 read_only =
736                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
737
738         dev_dbg(&mmc->class_dev, "card is %s\n",
739                 read_only ? "read-only" : "read-write");
740
741         return read_only;
742 }
743
744 static int dw_mci_get_cd(struct mmc_host *mmc)
745 {
746         int present;
747         struct dw_mci_slot *slot = mmc_priv(mmc);
748         struct dw_mci_board *brd = slot->host->pdata;
749
750         /* Use platform get_cd function, else try onboard card detect */
751         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
752                 present = 1;
753         else if (brd->get_cd)
754                 present = !brd->get_cd(slot->id);
755         else
756                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
757                         == 0 ? 1 : 0;
758
759         if (present)
760                 dev_dbg(&mmc->class_dev, "card is present\n");
761         else
762                 dev_dbg(&mmc->class_dev, "card is not present\n");
763
764         return present;
765 }
766
767 static const struct mmc_host_ops dw_mci_ops = {
768         .request        = dw_mci_request,
769         .set_ios        = dw_mci_set_ios,
770         .get_ro         = dw_mci_get_ro,
771         .get_cd         = dw_mci_get_cd,
772 };
773
774 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
775         __releases(&host->lock)
776         __acquires(&host->lock)
777 {
778         struct dw_mci_slot *slot;
779         struct mmc_host *prev_mmc = host->cur_slot->mmc;
780
781         WARN_ON(host->cmd || host->data);
782
783         host->cur_slot->mrq = NULL;
784         host->mrq = NULL;
785         if (!list_empty(&host->queue)) {
786                 slot = list_entry(host->queue.next,
787                                   struct dw_mci_slot, queue_node);
788                 list_del(&slot->queue_node);
789                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
790                          mmc_hostname(slot->mmc));
791                 host->state = STATE_SENDING_CMD;
792                 dw_mci_start_request(host, slot);
793         } else {
794                 dev_vdbg(&host->pdev->dev, "list empty\n");
795                 host->state = STATE_IDLE;
796         }
797
798         spin_unlock(&host->lock);
799         mmc_request_done(prev_mmc, mrq);
800         spin_lock(&host->lock);
801 }
802
803 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
804 {
805         u32 status = host->cmd_status;
806
807         host->cmd_status = 0;
808
809         /* Read the response from the card (up to 16 bytes) */
810         if (cmd->flags & MMC_RSP_PRESENT) {
811                 if (cmd->flags & MMC_RSP_136) {
812                         cmd->resp[3] = mci_readl(host, RESP0);
813                         cmd->resp[2] = mci_readl(host, RESP1);
814                         cmd->resp[1] = mci_readl(host, RESP2);
815                         cmd->resp[0] = mci_readl(host, RESP3);
816                 } else {
817                         cmd->resp[0] = mci_readl(host, RESP0);
818                         cmd->resp[1] = 0;
819                         cmd->resp[2] = 0;
820                         cmd->resp[3] = 0;
821                 }
822         }
823
824         if (status & SDMMC_INT_RTO)
825                 cmd->error = -ETIMEDOUT;
826         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
827                 cmd->error = -EILSEQ;
828         else if (status & SDMMC_INT_RESP_ERR)
829                 cmd->error = -EIO;
830         else
831                 cmd->error = 0;
832
833         if (cmd->error) {
834                 /* newer ip versions need a delay between retries */
835                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
836                         mdelay(20);
837
838                 if (cmd->data) {
839                         host->data = NULL;
840                         dw_mci_stop_dma(host);
841                 }
842         }
843 }
844
845 static void dw_mci_tasklet_func(unsigned long priv)
846 {
847         struct dw_mci *host = (struct dw_mci *)priv;
848         struct mmc_data *data;
849         struct mmc_command *cmd;
850         enum dw_mci_state state;
851         enum dw_mci_state prev_state;
852         u32 status;
853
854         spin_lock(&host->lock);
855
856         state = host->state;
857         data = host->data;
858
859         do {
860                 prev_state = state;
861
862                 switch (state) {
863                 case STATE_IDLE:
864                         break;
865
866                 case STATE_SENDING_CMD:
867                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
868                                                 &host->pending_events))
869                                 break;
870
871                         cmd = host->cmd;
872                         host->cmd = NULL;
873                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
874                         dw_mci_command_complete(host, host->mrq->cmd);
875                         if (!host->mrq->data || cmd->error) {
876                                 dw_mci_request_end(host, host->mrq);
877                                 goto unlock;
878                         }
879
880                         prev_state = state = STATE_SENDING_DATA;
881                         /* fall through */
882
883                 case STATE_SENDING_DATA:
884                         if (test_and_clear_bit(EVENT_DATA_ERROR,
885                                                &host->pending_events)) {
886                                 dw_mci_stop_dma(host);
887                                 if (data->stop)
888                                         send_stop_cmd(host, data);
889                                 state = STATE_DATA_ERROR;
890                                 break;
891                         }
892
893                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
894                                                 &host->pending_events))
895                                 break;
896
897                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
898                         prev_state = state = STATE_DATA_BUSY;
899                         /* fall through */
900
901                 case STATE_DATA_BUSY:
902                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
903                                                 &host->pending_events))
904                                 break;
905
906                         host->data = NULL;
907                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
908                         status = host->data_status;
909
910                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
911                                 if (status & SDMMC_INT_DTO) {
912                                         data->error = -ETIMEDOUT;
913                                 } else if (status & SDMMC_INT_DCRC) {
914                                         data->error = -EILSEQ;
915                                 } else if (status & SDMMC_INT_EBE &&
916                                            host->dir_status ==
917                                                         DW_MCI_SEND_STATUS) {
918                                         /*
919                                          * No data CRC status was returned.
920                                          * The number of bytes transferred will
921                                          * be exaggerated in PIO mode.
922                                          */
923                                         data->bytes_xfered = 0;
924                                         data->error = -ETIMEDOUT;
925                                 } else {
926                                         dev_err(&host->pdev->dev,
927                                                 "data FIFO error "
928                                                 "(status=%08x)\n",
929                                                 status);
930                                         data->error = -EIO;
931                                 }
932                         } else {
933                                 data->bytes_xfered = data->blocks * data->blksz;
934                                 data->error = 0;
935                         }
936
937                         if (!data->stop) {
938                                 dw_mci_request_end(host, host->mrq);
939                                 goto unlock;
940                         }
941
942                         prev_state = state = STATE_SENDING_STOP;
943                         if (!data->error)
944                                 send_stop_cmd(host, data);
945                         /* fall through */
946
947                 case STATE_SENDING_STOP:
948                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
949                                                 &host->pending_events))
950                                 break;
951
952                         host->cmd = NULL;
953                         dw_mci_command_complete(host, host->mrq->stop);
954                         dw_mci_request_end(host, host->mrq);
955                         goto unlock;
956
957                 case STATE_DATA_ERROR:
958                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
959                                                 &host->pending_events))
960                                 break;
961
962                         state = STATE_DATA_BUSY;
963                         break;
964                 }
965         } while (state != prev_state);
966
967         host->state = state;
968 unlock:
969         spin_unlock(&host->lock);
970
971 }
972
973 /* push final bytes to part_buf, only use during push */
974 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
975 {
976         memcpy((void *)&host->part_buf, buf, cnt);
977         host->part_buf_count = cnt;
978 }
979
980 /* append bytes to part_buf, only use during push */
981 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
982 {
983         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
984         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
985         host->part_buf_count += cnt;
986         return cnt;
987 }
988
989 /* pull first bytes from part_buf, only use during pull */
990 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
991 {
992         cnt = min(cnt, (int)host->part_buf_count);
993         if (cnt) {
994                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
995                        cnt);
996                 host->part_buf_count -= cnt;
997                 host->part_buf_start += cnt;
998         }
999         return cnt;
1000 }
1001
1002 /* pull final bytes from the part_buf, assuming it's just been filled */
1003 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1004 {
1005         memcpy(buf, &host->part_buf, cnt);
1006         host->part_buf_start = cnt;
1007         host->part_buf_count = (1 << host->data_shift) - cnt;
1008 }
1009
1010 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1011 {
1012         /* try and push anything in the part_buf */
1013         if (unlikely(host->part_buf_count)) {
1014                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1015                 buf += len;
1016                 cnt -= len;
1017                 if (!sg_next(host->sg) || host->part_buf_count == 2) {
1018                         mci_writew(host, DATA, host->part_buf16);
1019                         host->part_buf_count = 0;
1020                 }
1021         }
1022 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1023         if (unlikely((unsigned long)buf & 0x1)) {
1024                 while (cnt >= 2) {
1025                         u16 aligned_buf[64];
1026                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1027                         int items = len >> 1;
1028                         int i;
1029                         /* memcpy from input buffer into aligned buffer */
1030                         memcpy(aligned_buf, buf, len);
1031                         buf += len;
1032                         cnt -= len;
1033                         /* push data from aligned buffer into fifo */
1034                         for (i = 0; i < items; ++i)
1035                                 mci_writew(host, DATA, aligned_buf[i]);
1036                 }
1037         } else
1038 #endif
1039         {
1040                 u16 *pdata = buf;
1041                 for (; cnt >= 2; cnt -= 2)
1042                         mci_writew(host, DATA, *pdata++);
1043                 buf = pdata;
1044         }
1045         /* put anything remaining in the part_buf */
1046         if (cnt) {
1047                 dw_mci_set_part_bytes(host, buf, cnt);
1048                 if (!sg_next(host->sg))
1049                         mci_writew(host, DATA, host->part_buf16);
1050         }
1051 }
1052
1053 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1054 {
1055 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1056         if (unlikely((unsigned long)buf & 0x1)) {
1057                 while (cnt >= 2) {
1058                         /* pull data from fifo into aligned buffer */
1059                         u16 aligned_buf[64];
1060                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1061                         int items = len >> 1;
1062                         int i;
1063                         for (i = 0; i < items; ++i)
1064                                 aligned_buf[i] = mci_readw(host, DATA);
1065                         /* memcpy from aligned buffer into output buffer */
1066                         memcpy(buf, aligned_buf, len);
1067                         buf += len;
1068                         cnt -= len;
1069                 }
1070         } else
1071 #endif
1072         {
1073                 u16 *pdata = buf;
1074                 for (; cnt >= 2; cnt -= 2)
1075                         *pdata++ = mci_readw(host, DATA);
1076                 buf = pdata;
1077         }
1078         if (cnt) {
1079                 host->part_buf16 = mci_readw(host, DATA);
1080                 dw_mci_pull_final_bytes(host, buf, cnt);
1081         }
1082 }
1083
1084 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1085 {
1086         /* try and push anything in the part_buf */
1087         if (unlikely(host->part_buf_count)) {
1088                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1089                 buf += len;
1090                 cnt -= len;
1091                 if (!sg_next(host->sg) || host->part_buf_count == 4) {
1092                         mci_writel(host, DATA, host->part_buf32);
1093                         host->part_buf_count = 0;
1094                 }
1095         }
1096 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1097         if (unlikely((unsigned long)buf & 0x3)) {
1098                 while (cnt >= 4) {
1099                         u32 aligned_buf[32];
1100                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1101                         int items = len >> 2;
1102                         int i;
1103                         /* memcpy from input buffer into aligned buffer */
1104                         memcpy(aligned_buf, buf, len);
1105                         buf += len;
1106                         cnt -= len;
1107                         /* push data from aligned buffer into fifo */
1108                         for (i = 0; i < items; ++i)
1109                                 mci_writel(host, DATA, aligned_buf[i]);
1110                 }
1111         } else
1112 #endif
1113         {
1114                 u32 *pdata = buf;
1115                 for (; cnt >= 4; cnt -= 4)
1116                         mci_writel(host, DATA, *pdata++);
1117                 buf = pdata;
1118         }
1119         /* put anything remaining in the part_buf */
1120         if (cnt) {
1121                 dw_mci_set_part_bytes(host, buf, cnt);
1122                 if (!sg_next(host->sg))
1123                         mci_writel(host, DATA, host->part_buf32);
1124         }
1125 }
1126
1127 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1128 {
1129 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1130         if (unlikely((unsigned long)buf & 0x3)) {
1131                 while (cnt >= 4) {
1132                         /* pull data from fifo into aligned buffer */
1133                         u32 aligned_buf[32];
1134                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1135                         int items = len >> 2;
1136                         int i;
1137                         for (i = 0; i < items; ++i)
1138                                 aligned_buf[i] = mci_readl(host, DATA);
1139                         /* memcpy from aligned buffer into output buffer */
1140                         memcpy(buf, aligned_buf, len);
1141                         buf += len;
1142                         cnt -= len;
1143                 }
1144         } else
1145 #endif
1146         {
1147                 u32 *pdata = buf;
1148                 for (; cnt >= 4; cnt -= 4)
1149                         *pdata++ = mci_readl(host, DATA);
1150                 buf = pdata;
1151         }
1152         if (cnt) {
1153                 host->part_buf32 = mci_readl(host, DATA);
1154                 dw_mci_pull_final_bytes(host, buf, cnt);
1155         }
1156 }
1157
1158 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1159 {
1160         /* try and push anything in the part_buf */
1161         if (unlikely(host->part_buf_count)) {
1162                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1163                 buf += len;
1164                 cnt -= len;
1165                 if (!sg_next(host->sg) || host->part_buf_count == 8) {
1166                         mci_writew(host, DATA, host->part_buf);
1167                         host->part_buf_count = 0;
1168                 }
1169         }
1170 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1171         if (unlikely((unsigned long)buf & 0x7)) {
1172                 while (cnt >= 8) {
1173                         u64 aligned_buf[16];
1174                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1175                         int items = len >> 3;
1176                         int i;
1177                         /* memcpy from input buffer into aligned buffer */
1178                         memcpy(aligned_buf, buf, len);
1179                         buf += len;
1180                         cnt -= len;
1181                         /* push data from aligned buffer into fifo */
1182                         for (i = 0; i < items; ++i)
1183                                 mci_writeq(host, DATA, aligned_buf[i]);
1184                 }
1185         } else
1186 #endif
1187         {
1188                 u64 *pdata = buf;
1189                 for (; cnt >= 8; cnt -= 8)
1190                         mci_writeq(host, DATA, *pdata++);
1191                 buf = pdata;
1192         }
1193         /* put anything remaining in the part_buf */
1194         if (cnt) {
1195                 dw_mci_set_part_bytes(host, buf, cnt);
1196                 if (!sg_next(host->sg))
1197                         mci_writeq(host, DATA, host->part_buf);
1198         }
1199 }
1200
1201 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1202 {
1203 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1204         if (unlikely((unsigned long)buf & 0x7)) {
1205                 while (cnt >= 8) {
1206                         /* pull data from fifo into aligned buffer */
1207                         u64 aligned_buf[16];
1208                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1209                         int items = len >> 3;
1210                         int i;
1211                         for (i = 0; i < items; ++i)
1212                                 aligned_buf[i] = mci_readq(host, DATA);
1213                         /* memcpy from aligned buffer into output buffer */
1214                         memcpy(buf, aligned_buf, len);
1215                         buf += len;
1216                         cnt -= len;
1217                 }
1218         } else
1219 #endif
1220         {
1221                 u64 *pdata = buf;
1222                 for (; cnt >= 8; cnt -= 8)
1223                         *pdata++ = mci_readq(host, DATA);
1224                 buf = pdata;
1225         }
1226         if (cnt) {
1227                 host->part_buf = mci_readq(host, DATA);
1228                 dw_mci_pull_final_bytes(host, buf, cnt);
1229         }
1230 }
1231
1232 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1233 {
1234         int len;
1235
1236         /* get remaining partial bytes */
1237         len = dw_mci_pull_part_bytes(host, buf, cnt);
1238         if (unlikely(len == cnt))
1239                 return;
1240         buf += len;
1241         cnt -= len;
1242
1243         /* get the rest of the data */
1244         host->pull_data(host, buf, cnt);
1245 }
1246
1247 static void dw_mci_read_data_pio(struct dw_mci *host)
1248 {
1249         struct scatterlist *sg = host->sg;
1250         void *buf = sg_virt(sg);
1251         unsigned int offset = host->pio_offset;
1252         struct mmc_data *data = host->data;
1253         int shift = host->data_shift;
1254         u32 status;
1255         unsigned int nbytes = 0, len;
1256
1257         do {
1258                 len = host->part_buf_count +
1259                         (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1260                 if (offset + len <= sg->length) {
1261                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1262
1263                         offset += len;
1264                         nbytes += len;
1265
1266                         if (offset == sg->length) {
1267                                 flush_dcache_page(sg_page(sg));
1268                                 host->sg = sg = sg_next(sg);
1269                                 if (!sg)
1270                                         goto done;
1271
1272                                 offset = 0;
1273                                 buf = sg_virt(sg);
1274                         }
1275                 } else {
1276                         unsigned int remaining = sg->length - offset;
1277                         dw_mci_pull_data(host, (void *)(buf + offset),
1278                                          remaining);
1279                         nbytes += remaining;
1280
1281                         flush_dcache_page(sg_page(sg));
1282                         host->sg = sg = sg_next(sg);
1283                         if (!sg)
1284                                 goto done;
1285
1286                         offset = len - remaining;
1287                         buf = sg_virt(sg);
1288                         dw_mci_pull_data(host, buf, offset);
1289                         nbytes += offset;
1290                 }
1291
1292                 status = mci_readl(host, MINTSTS);
1293                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1294                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1295                         host->data_status = status;
1296                         data->bytes_xfered += nbytes;
1297                         smp_wmb();
1298
1299                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1300
1301                         tasklet_schedule(&host->tasklet);
1302                         return;
1303                 }
1304         } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1305         host->pio_offset = offset;
1306         data->bytes_xfered += nbytes;
1307         return;
1308
1309 done:
1310         data->bytes_xfered += nbytes;
1311         smp_wmb();
1312         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1313 }
1314
1315 static void dw_mci_write_data_pio(struct dw_mci *host)
1316 {
1317         struct scatterlist *sg = host->sg;
1318         void *buf = sg_virt(sg);
1319         unsigned int offset = host->pio_offset;
1320         struct mmc_data *data = host->data;
1321         int shift = host->data_shift;
1322         u32 status;
1323         unsigned int nbytes = 0, len;
1324
1325         do {
1326                 len = ((host->fifo_depth -
1327                         SDMMC_GET_FCNT(mci_readl(host, STATUS))) << shift)
1328                         - host->part_buf_count;
1329                 if (offset + len <= sg->length) {
1330                         host->push_data(host, (void *)(buf + offset), len);
1331
1332                         offset += len;
1333                         nbytes += len;
1334                         if (offset == sg->length) {
1335                                 host->sg = sg = sg_next(sg);
1336                                 if (!sg)
1337                                         goto done;
1338
1339                                 offset = 0;
1340                                 buf = sg_virt(sg);
1341                         }
1342                 } else {
1343                         unsigned int remaining = sg->length - offset;
1344
1345                         host->push_data(host, (void *)(buf + offset),
1346                                         remaining);
1347                         nbytes += remaining;
1348
1349                         host->sg = sg = sg_next(sg);
1350                         if (!sg)
1351                                 goto done;
1352
1353                         offset = len - remaining;
1354                         buf = sg_virt(sg);
1355                         host->push_data(host, (void *)buf, offset);
1356                         nbytes += offset;
1357                 }
1358
1359                 status = mci_readl(host, MINTSTS);
1360                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1361                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1362                         host->data_status = status;
1363                         data->bytes_xfered += nbytes;
1364
1365                         smp_wmb();
1366
1367                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1368
1369                         tasklet_schedule(&host->tasklet);
1370                         return;
1371                 }
1372         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1373         host->pio_offset = offset;
1374         data->bytes_xfered += nbytes;
1375         return;
1376
1377 done:
1378         data->bytes_xfered += nbytes;
1379         smp_wmb();
1380         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1381 }
1382
1383 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1384 {
1385         if (!host->cmd_status)
1386                 host->cmd_status = status;
1387
1388         smp_wmb();
1389
1390         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1391         tasklet_schedule(&host->tasklet);
1392 }
1393
1394 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1395 {
1396         struct dw_mci *host = dev_id;
1397         u32 status, pending;
1398         unsigned int pass_count = 0;
1399
1400         do {
1401                 status = mci_readl(host, RINTSTS);
1402                 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1403
1404                 /*
1405                  * DTO fix - version 2.10a and below, and only if internal DMA
1406                  * is configured.
1407                  */
1408                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1409                         if (!pending &&
1410                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1411                                 pending |= SDMMC_INT_DATA_OVER;
1412                 }
1413
1414                 if (!pending)
1415                         break;
1416
1417                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1418                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1419                         host->cmd_status = status;
1420                         smp_wmb();
1421                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1422                 }
1423
1424                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1425                         /* if there is an error report DATA_ERROR */
1426                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1427                         host->data_status = status;
1428                         smp_wmb();
1429                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1430                         if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1431                                          SDMMC_INT_SBE | SDMMC_INT_EBE)))
1432                                 tasklet_schedule(&host->tasklet);
1433                 }
1434
1435                 if (pending & SDMMC_INT_DATA_OVER) {
1436                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1437                         if (!host->data_status)
1438                                 host->data_status = status;
1439                         smp_wmb();
1440                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1441                                 if (host->sg != NULL)
1442                                         dw_mci_read_data_pio(host);
1443                         }
1444                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1445                         tasklet_schedule(&host->tasklet);
1446                 }
1447
1448                 if (pending & SDMMC_INT_RXDR) {
1449                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1450                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1451                                 dw_mci_read_data_pio(host);
1452                 }
1453
1454                 if (pending & SDMMC_INT_TXDR) {
1455                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1456                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1457                                 dw_mci_write_data_pio(host);
1458                 }
1459
1460                 if (pending & SDMMC_INT_CMD_DONE) {
1461                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1462                         dw_mci_cmd_interrupt(host, status);
1463                 }
1464
1465                 if (pending & SDMMC_INT_CD) {
1466                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1467                         queue_work(dw_mci_card_workqueue, &host->card_work);
1468                 }
1469
1470         } while (pass_count++ < 5);
1471
1472 #ifdef CONFIG_MMC_DW_IDMAC
1473         /* Handle DMA interrupts */
1474         pending = mci_readl(host, IDSTS);
1475         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1476                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1477                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1478                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1479                 host->dma_ops->complete(host);
1480         }
1481 #endif
1482
1483         return IRQ_HANDLED;
1484 }
1485
1486 static void dw_mci_work_routine_card(struct work_struct *work)
1487 {
1488         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1489         int i;
1490
1491         for (i = 0; i < host->num_slots; i++) {
1492                 struct dw_mci_slot *slot = host->slot[i];
1493                 struct mmc_host *mmc = slot->mmc;
1494                 struct mmc_request *mrq;
1495                 int present;
1496                 u32 ctrl;
1497
1498                 present = dw_mci_get_cd(mmc);
1499                 while (present != slot->last_detect_state) {
1500                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1501                                 present ? "inserted" : "removed");
1502
1503                         /* Power up slot (before spin_lock, may sleep) */
1504                         if (present != 0 && host->pdata->setpower)
1505                                 host->pdata->setpower(slot->id, mmc->ocr_avail);
1506
1507                         spin_lock_bh(&host->lock);
1508
1509                         /* Card change detected */
1510                         slot->last_detect_state = present;
1511
1512                         /* Mark card as present if applicable */
1513                         if (present != 0)
1514                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1515
1516                         /* Clean up queue if present */
1517                         mrq = slot->mrq;
1518                         if (mrq) {
1519                                 if (mrq == host->mrq) {
1520                                         host->data = NULL;
1521                                         host->cmd = NULL;
1522
1523                                         switch (host->state) {
1524                                         case STATE_IDLE:
1525                                                 break;
1526                                         case STATE_SENDING_CMD:
1527                                                 mrq->cmd->error = -ENOMEDIUM;
1528                                                 if (!mrq->data)
1529                                                         break;
1530                                                 /* fall through */
1531                                         case STATE_SENDING_DATA:
1532                                                 mrq->data->error = -ENOMEDIUM;
1533                                                 dw_mci_stop_dma(host);
1534                                                 break;
1535                                         case STATE_DATA_BUSY:
1536                                         case STATE_DATA_ERROR:
1537                                                 if (mrq->data->error == -EINPROGRESS)
1538                                                         mrq->data->error = -ENOMEDIUM;
1539                                                 if (!mrq->stop)
1540                                                         break;
1541                                                 /* fall through */
1542                                         case STATE_SENDING_STOP:
1543                                                 mrq->stop->error = -ENOMEDIUM;
1544                                                 break;
1545                                         }
1546
1547                                         dw_mci_request_end(host, mrq);
1548                                 } else {
1549                                         list_del(&slot->queue_node);
1550                                         mrq->cmd->error = -ENOMEDIUM;
1551                                         if (mrq->data)
1552                                                 mrq->data->error = -ENOMEDIUM;
1553                                         if (mrq->stop)
1554                                                 mrq->stop->error = -ENOMEDIUM;
1555
1556                                         spin_unlock(&host->lock);
1557                                         mmc_request_done(slot->mmc, mrq);
1558                                         spin_lock(&host->lock);
1559                                 }
1560                         }
1561
1562                         /* Power down slot */
1563                         if (present == 0) {
1564                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1565
1566                                 /*
1567                                  * Clear down the FIFO - doing so generates a
1568                                  * block interrupt, hence setting the
1569                                  * scatter-gather pointer to NULL.
1570                                  */
1571                                 host->sg = NULL;
1572
1573                                 ctrl = mci_readl(host, CTRL);
1574                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1575                                 mci_writel(host, CTRL, ctrl);
1576
1577 #ifdef CONFIG_MMC_DW_IDMAC
1578                                 ctrl = mci_readl(host, BMOD);
1579                                 ctrl |= 0x01; /* Software reset of DMA */
1580                                 mci_writel(host, BMOD, ctrl);
1581 #endif
1582
1583                         }
1584
1585                         spin_unlock_bh(&host->lock);
1586
1587                         /* Power down slot (after spin_unlock, may sleep) */
1588                         if (present == 0 && host->pdata->setpower)
1589                                 host->pdata->setpower(slot->id, 0);
1590
1591                         present = dw_mci_get_cd(mmc);
1592                 }
1593
1594                 mmc_detect_change(slot->mmc,
1595                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1596         }
1597 }
1598
1599 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1600 {
1601         struct mmc_host *mmc;
1602         struct dw_mci_slot *slot;
1603
1604         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1605         if (!mmc)
1606                 return -ENOMEM;
1607
1608         slot = mmc_priv(mmc);
1609         slot->id = id;
1610         slot->mmc = mmc;
1611         slot->host = host;
1612
1613         mmc->ops = &dw_mci_ops;
1614         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1615         mmc->f_max = host->bus_hz;
1616
1617         if (host->pdata->get_ocr)
1618                 mmc->ocr_avail = host->pdata->get_ocr(id);
1619         else
1620                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1621
1622         /*
1623          * Start with slot power disabled, it will be enabled when a card
1624          * is detected.
1625          */
1626         if (host->pdata->setpower)
1627                 host->pdata->setpower(id, 0);
1628
1629         if (host->pdata->caps)
1630                 mmc->caps = host->pdata->caps;
1631         else
1632                 mmc->caps = 0;
1633
1634         if (host->pdata->get_bus_wd)
1635                 if (host->pdata->get_bus_wd(slot->id) >= 4)
1636                         mmc->caps |= MMC_CAP_4_BIT_DATA;
1637
1638         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1639                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1640
1641 #ifdef CONFIG_MMC_DW_IDMAC
1642         mmc->max_segs = host->ring_size;
1643         mmc->max_blk_size = 65536;
1644         mmc->max_blk_count = host->ring_size;
1645         mmc->max_seg_size = 0x1000;
1646         mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1647 #else
1648         if (host->pdata->blk_settings) {
1649                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1650                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1651                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1652                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1653                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1654         } else {
1655                 /* Useful defaults if platform data is unset. */
1656                 mmc->max_segs = 64;
1657                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1658                 mmc->max_blk_count = 512;
1659                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1660                 mmc->max_seg_size = mmc->max_req_size;
1661         }
1662 #endif /* CONFIG_MMC_DW_IDMAC */
1663
1664         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1665         if (IS_ERR(host->vmmc)) {
1666                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1667                 host->vmmc = NULL;
1668         } else
1669                 regulator_enable(host->vmmc);
1670
1671         if (dw_mci_get_cd(mmc))
1672                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1673         else
1674                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1675
1676         host->slot[id] = slot;
1677         mmc_add_host(mmc);
1678
1679 #if defined(CONFIG_DEBUG_FS)
1680         dw_mci_init_debugfs(slot);
1681 #endif
1682
1683         /* Card initially undetected */
1684         slot->last_detect_state = 0;
1685
1686         /*
1687          * Card may have been plugged in prior to boot so we
1688          * need to run the detect tasklet
1689          */
1690         queue_work(dw_mci_card_workqueue, &host->card_work);
1691
1692         return 0;
1693 }
1694
1695 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1696 {
1697         /* Shutdown detect IRQ */
1698         if (slot->host->pdata->exit)
1699                 slot->host->pdata->exit(id);
1700
1701         /* Debugfs stuff is cleaned up by mmc core */
1702         mmc_remove_host(slot->mmc);
1703         slot->host->slot[id] = NULL;
1704         mmc_free_host(slot->mmc);
1705 }
1706
1707 static void dw_mci_init_dma(struct dw_mci *host)
1708 {
1709         /* Alloc memory for sg translation */
1710         host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1711                                           &host->sg_dma, GFP_KERNEL);
1712         if (!host->sg_cpu) {
1713                 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1714                         __func__);
1715                 goto no_dma;
1716         }
1717
1718         /* Determine which DMA interface to use */
1719 #ifdef CONFIG_MMC_DW_IDMAC
1720         host->dma_ops = &dw_mci_idmac_ops;
1721         dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1722 #endif
1723
1724         if (!host->dma_ops)
1725                 goto no_dma;
1726
1727         if (host->dma_ops->init) {
1728                 if (host->dma_ops->init(host)) {
1729                         dev_err(&host->pdev->dev, "%s: Unable to initialize "
1730                                 "DMA Controller.\n", __func__);
1731                         goto no_dma;
1732                 }
1733         } else {
1734                 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1735                 goto no_dma;
1736         }
1737
1738         host->use_dma = 1;
1739         return;
1740
1741 no_dma:
1742         dev_info(&host->pdev->dev, "Using PIO mode.\n");
1743         host->use_dma = 0;
1744         return;
1745 }
1746
1747 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1748 {
1749         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1750         unsigned int ctrl;
1751
1752         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1753                                 SDMMC_CTRL_DMA_RESET));
1754
1755         /* wait till resets clear */
1756         do {
1757                 ctrl = mci_readl(host, CTRL);
1758                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1759                               SDMMC_CTRL_DMA_RESET)))
1760                         return true;
1761         } while (time_before(jiffies, timeout));
1762
1763         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1764
1765         return false;
1766 }
1767
1768 static int dw_mci_probe(struct platform_device *pdev)
1769 {
1770         struct dw_mci *host;
1771         struct resource *regs;
1772         struct dw_mci_board *pdata;
1773         int irq, ret, i, width;
1774         u32 fifo_size;
1775
1776         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1777         if (!regs)
1778                 return -ENXIO;
1779
1780         irq = platform_get_irq(pdev, 0);
1781         if (irq < 0)
1782                 return irq;
1783
1784         host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1785         if (!host)
1786                 return -ENOMEM;
1787
1788         host->pdev = pdev;
1789         host->pdata = pdata = pdev->dev.platform_data;
1790         if (!pdata || !pdata->init) {
1791                 dev_err(&pdev->dev,
1792                         "Platform data must supply init function\n");
1793                 ret = -ENODEV;
1794                 goto err_freehost;
1795         }
1796
1797         if (!pdata->select_slot && pdata->num_slots > 1) {
1798                 dev_err(&pdev->dev,
1799                         "Platform data must supply select_slot function\n");
1800                 ret = -ENODEV;
1801                 goto err_freehost;
1802         }
1803
1804         if (!pdata->bus_hz) {
1805                 dev_err(&pdev->dev,
1806                         "Platform data must supply bus speed\n");
1807                 ret = -ENODEV;
1808                 goto err_freehost;
1809         }
1810
1811         host->bus_hz = pdata->bus_hz;
1812         host->quirks = pdata->quirks;
1813
1814         spin_lock_init(&host->lock);
1815         INIT_LIST_HEAD(&host->queue);
1816
1817         ret = -ENOMEM;
1818         host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1819         if (!host->regs)
1820                 goto err_freehost;
1821
1822         host->dma_ops = pdata->dma_ops;
1823         dw_mci_init_dma(host);
1824
1825         /*
1826          * Get the host data width - this assumes that HCON has been set with
1827          * the correct values.
1828          */
1829         i = (mci_readl(host, HCON) >> 7) & 0x7;
1830         if (!i) {
1831                 host->push_data = dw_mci_push_data16;
1832                 host->pull_data = dw_mci_pull_data16;
1833                 width = 16;
1834                 host->data_shift = 1;
1835         } else if (i == 2) {
1836                 host->push_data = dw_mci_push_data64;
1837                 host->pull_data = dw_mci_pull_data64;
1838                 width = 64;
1839                 host->data_shift = 3;
1840         } else {
1841                 /* Check for a reserved value, and warn if it is */
1842                 WARN((i != 1),
1843                      "HCON reports a reserved host data width!\n"
1844                      "Defaulting to 32-bit access.\n");
1845                 host->push_data = dw_mci_push_data32;
1846                 host->pull_data = dw_mci_pull_data32;
1847                 width = 32;
1848                 host->data_shift = 2;
1849         }
1850
1851         /* Reset all blocks */
1852         if (!mci_wait_reset(&pdev->dev, host)) {
1853                 ret = -ENODEV;
1854                 goto err_dmaunmap;
1855         }
1856
1857         /* Clear the interrupts for the host controller */
1858         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1859         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1860
1861         /* Put in max timeout */
1862         mci_writel(host, TMOUT, 0xFFFFFFFF);
1863
1864         /*
1865          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
1866          *                          Tx Mark = fifo_size / 2 DMA Size = 8
1867          */
1868         if (!host->pdata->fifo_depth) {
1869                 /*
1870                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
1871                  * have been overwritten by the bootloader, just like we're
1872                  * about to do, so if you know the value for your hardware, you
1873                  * should put it in the platform data.
1874                  */
1875                 fifo_size = mci_readl(host, FIFOTH);
1876                 fifo_size = 1 + ((fifo_size >> 16) & 0x7ff);
1877         } else {
1878                 fifo_size = host->pdata->fifo_depth;
1879         }
1880         host->fifo_depth = fifo_size;
1881         host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1882                         ((fifo_size/2) << 0));
1883         mci_writel(host, FIFOTH, host->fifoth_val);
1884
1885         /* disable clock to CIU */
1886         mci_writel(host, CLKENA, 0);
1887         mci_writel(host, CLKSRC, 0);
1888
1889         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1890         dw_mci_card_workqueue = alloc_workqueue("dw-mci-card",
1891                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
1892         if (!dw_mci_card_workqueue)
1893                 goto err_dmaunmap;
1894         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
1895
1896         ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1897         if (ret)
1898                 goto err_workqueue;
1899
1900         platform_set_drvdata(pdev, host);
1901
1902         if (host->pdata->num_slots)
1903                 host->num_slots = host->pdata->num_slots;
1904         else
1905                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1906
1907         /* We need at least one slot to succeed */
1908         for (i = 0; i < host->num_slots; i++) {
1909                 ret = dw_mci_init_slot(host, i);
1910                 if (ret) {
1911                         ret = -ENODEV;
1912                         goto err_init_slot;
1913                 }
1914         }
1915
1916         /*
1917          * Enable interrupts for command done, data over, data empty, card det,
1918          * receive ready and error such as transmit, receive timeout, crc error
1919          */
1920         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1921         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1922                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1923                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1924         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1925
1926         dev_info(&pdev->dev, "DW MMC controller at irq %d, "
1927                  "%d bit host data width, "
1928                  "%u deep fifo\n",
1929                  irq, width, fifo_size);
1930         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1931                 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1932
1933         return 0;
1934
1935 err_init_slot:
1936         /* De-init any initialized slots */
1937         while (i > 0) {
1938                 if (host->slot[i])
1939                         dw_mci_cleanup_slot(host->slot[i], i);
1940                 i--;
1941         }
1942         free_irq(irq, host);
1943
1944 err_workqueue:
1945         destroy_workqueue(dw_mci_card_workqueue);
1946
1947 err_dmaunmap:
1948         if (host->use_dma && host->dma_ops->exit)
1949                 host->dma_ops->exit(host);
1950         dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1951                           host->sg_cpu, host->sg_dma);
1952         iounmap(host->regs);
1953
1954         if (host->vmmc) {
1955                 regulator_disable(host->vmmc);
1956                 regulator_put(host->vmmc);
1957         }
1958
1959
1960 err_freehost:
1961         kfree(host);
1962         return ret;
1963 }
1964
1965 static int __exit dw_mci_remove(struct platform_device *pdev)
1966 {
1967         struct dw_mci *host = platform_get_drvdata(pdev);
1968         int i;
1969
1970         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1971         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1972
1973         platform_set_drvdata(pdev, NULL);
1974
1975         for (i = 0; i < host->num_slots; i++) {
1976                 dev_dbg(&pdev->dev, "remove slot %d\n", i);
1977                 if (host->slot[i])
1978                         dw_mci_cleanup_slot(host->slot[i], i);
1979         }
1980
1981         /* disable clock to CIU */
1982         mci_writel(host, CLKENA, 0);
1983         mci_writel(host, CLKSRC, 0);
1984
1985         free_irq(platform_get_irq(pdev, 0), host);
1986         destroy_workqueue(dw_mci_card_workqueue);
1987         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1988
1989         if (host->use_dma && host->dma_ops->exit)
1990                 host->dma_ops->exit(host);
1991
1992         if (host->vmmc) {
1993                 regulator_disable(host->vmmc);
1994                 regulator_put(host->vmmc);
1995         }
1996
1997         iounmap(host->regs);
1998
1999         kfree(host);
2000         return 0;
2001 }
2002
2003 #ifdef CONFIG_PM
2004 /*
2005  * TODO: we should probably disable the clock to the card in the suspend path.
2006  */
2007 static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
2008 {
2009         int i, ret;
2010         struct dw_mci *host = platform_get_drvdata(pdev);
2011
2012         for (i = 0; i < host->num_slots; i++) {
2013                 struct dw_mci_slot *slot = host->slot[i];
2014                 if (!slot)
2015                         continue;
2016                 ret = mmc_suspend_host(slot->mmc);
2017                 if (ret < 0) {
2018                         while (--i >= 0) {
2019                                 slot = host->slot[i];
2020                                 if (slot)
2021                                         mmc_resume_host(host->slot[i]->mmc);
2022                         }
2023                         return ret;
2024                 }
2025         }
2026
2027         if (host->vmmc)
2028                 regulator_disable(host->vmmc);
2029
2030         return 0;
2031 }
2032
2033 static int dw_mci_resume(struct platform_device *pdev)
2034 {
2035         int i, ret;
2036         struct dw_mci *host = platform_get_drvdata(pdev);
2037
2038         if (host->vmmc)
2039                 regulator_enable(host->vmmc);
2040
2041         if (host->dma_ops->init)
2042                 host->dma_ops->init(host);
2043
2044         if (!mci_wait_reset(&pdev->dev, host)) {
2045                 ret = -ENODEV;
2046                 return ret;
2047         }
2048
2049         /* Restore the old value at FIFOTH register */
2050         mci_writel(host, FIFOTH, host->fifoth_val);
2051
2052         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2053         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2054                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2055                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2056         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2057
2058         for (i = 0; i < host->num_slots; i++) {
2059                 struct dw_mci_slot *slot = host->slot[i];
2060                 if (!slot)
2061                         continue;
2062                 ret = mmc_resume_host(host->slot[i]->mmc);
2063                 if (ret < 0)
2064                         return ret;
2065         }
2066
2067         return 0;
2068 }
2069 #else
2070 #define dw_mci_suspend  NULL
2071 #define dw_mci_resume   NULL
2072 #endif /* CONFIG_PM */
2073
2074 static struct platform_driver dw_mci_driver = {
2075         .remove         = __exit_p(dw_mci_remove),
2076         .suspend        = dw_mci_suspend,
2077         .resume         = dw_mci_resume,
2078         .driver         = {
2079                 .name           = "dw_mmc",
2080         },
2081 };
2082
2083 static int __init dw_mci_init(void)
2084 {
2085         return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
2086 }
2087
2088 static void __exit dw_mci_exit(void)
2089 {
2090         platform_driver_unregister(&dw_mci_driver);
2091 }
2092
2093 module_init(dw_mci_init);
2094 module_exit(dw_mci_exit);
2095
2096 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2097 MODULE_AUTHOR("NXP Semiconductor VietNam");
2098 MODULE_AUTHOR("Imagination Technologies Ltd");
2099 MODULE_LICENSE("GPL v2");