Au1[12]00 mmc driver. Only tested on the Au1200 at this point though
[linux-2.6.git] / drivers / mmc / au1xmmc.c
1 /*
2  * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
3  *
4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
5  *
6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
7  *  the following copyright notices:
8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
9  *     Portions Copyright (C) 2002 Embedix, Inc
10  *     Copyright 2002 Hewlett-Packard Company
11
12  *  2.6 version of this driver inspired by:
13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14  *     All Rights Reserved.
15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16  *     All Rights Reserved.
17  *
18
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License version 2 as
21  * published by the Free Software Foundation.
22  */
23
24 /* Why is a timer used to detect insert events?
25  *
26  * From the AU1100 MMC application guide:
27  * If the Au1100-based design is intended to support both MultiMediaCards
28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30  * In doing so, a MMC card never enters SPI-mode communications,
31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32  * (the low to high transition will not occur).
33  *
34  * So we use the timer to check the status manually.
35  */
36
37 #include <linux/config.h>
38 #include <linux/module.h>
39 #include <linux/init.h>
40 #include <linux/device.h>
41 #include <linux/mm.h>
42 #include <linux/interrupt.h>
43 #include <linux/dma-mapping.h>
44
45 #include <linux/mmc/host.h>
46 #include <linux/mmc/protocol.h>
47 #include <asm/io.h>
48 #include <asm/mach-au1x00/au1000.h>
49 #include <asm/mach-au1x00/au1xxx_dbdma.h>
50 #include <asm/mach-au1x00/au1100_mmc.h>
51 #include <asm/scatterlist.h>
52
53 #include <au1xxx.h>
54 #include "au1xmmc.h"
55
56 #define DRIVER_NAME "au1xxx-mmc"
57
58 /* Set this to enable special debugging macros */
59 /* #define MMC_DEBUG */
60
61 #ifdef MMC_DEBUG
62 #define DEBUG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
63 #else
64 #define DEBUG(fmt, idx, args...)
65 #endif
66
67 const struct {
68         u32 iobase;
69         u32 tx_devid, rx_devid;
70         u16 bcsrpwr;
71         u16 bcsrstatus;
72         u16 wpstatus;
73 } au1xmmc_card_table[] = {
74         { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
75           BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
76 #ifndef CONFIG_MIPS_DB1200
77         { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
78           BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
79 #endif
80 };
81
82 #define AU1XMMC_CONTROLLER_COUNT \
83         (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
84
85 /* This array stores pointers for the hosts (used by the IRQ handler) */
86 struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
87 static int dma = 1;
88
89 #ifdef MODULE
90 MODULE_PARM(dma, "i");
91 MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
92 #endif
93
94 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
95 {
96         u32 val = au_readl(HOST_CONFIG(host));
97         val |= mask;
98         au_writel(val, HOST_CONFIG(host));
99         au_sync();
100 }
101
102 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
103 {
104         u32 val = au_readl(HOST_CONFIG2(host));
105
106         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
107         au_sync_delay(1);
108
109         /* SEND_STOP will turn off clock control - this re-enables it */
110         val &= ~SD_CONFIG2_DF;
111
112         au_writel(val, HOST_CONFIG2(host));
113         au_sync();
114 }
115
116 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
117 {
118         u32 val = au_readl(HOST_CONFIG(host));
119         val &= ~mask;
120         au_writel(val, HOST_CONFIG(host));
121         au_sync();
122 }
123
124 static inline void SEND_STOP(struct au1xmmc_host *host)
125 {
126
127         /* We know the value of CONFIG2, so avoid a read we don't need */
128         u32 mask = SD_CONFIG2_EN;
129
130         WARN_ON(host->status != HOST_S_DATA);
131         host->status = HOST_S_STOP;
132
133         au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
134         au_sync();
135
136         /* Send the stop commmand */
137         au_writel(STOP_CMD, HOST_CMD(host));
138 }
139
140 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
141 {
142
143         u32 val = au1xmmc_card_table[host->id].bcsrpwr;
144
145         bcsr->board &= ~val;
146         if (state) bcsr->board |= val;
147
148         au_sync_delay(1);
149 }
150
151 static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
152 {
153         return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
154                 ? 1 : 0;
155 }
156
157 static inline int au1xmmc_card_readonly(struct au1xmmc_host *host)
158 {
159         return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
160                 ? 1 : 0;
161 }
162
163 static void au1xmmc_finish_request(struct au1xmmc_host *host)
164 {
165
166         struct mmc_request *mrq = host->mrq;
167
168         host->mrq = NULL;
169         host->flags &= HOST_F_ACTIVE;
170
171         host->dma.len = 0;
172         host->dma.dir = 0;
173
174         host->pio.index  = 0;
175         host->pio.offset = 0;
176         host->pio.len = 0;
177
178         host->status = HOST_S_IDLE;
179
180         bcsr->disk_leds |= (1 << 8);
181
182         mmc_request_done(host->mmc, mrq);
183 }
184
185 static void au1xmmc_tasklet_finish(unsigned long param)
186 {
187         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
188         au1xmmc_finish_request(host);
189 }
190
191 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
192                                 struct mmc_command *cmd)
193 {
194
195         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
196
197         switch(cmd->flags) {
198         case MMC_RSP_R1:
199                 mmccmd |= SD_CMD_RT_1;
200                 break;
201         case MMC_RSP_R1B:
202                 mmccmd |= SD_CMD_RT_1B;
203                 break;
204         case MMC_RSP_R2:
205                 mmccmd |= SD_CMD_RT_2;
206                 break;
207         case MMC_RSP_R3:
208                 mmccmd |= SD_CMD_RT_3;
209                 break;
210         }
211
212         switch(cmd->opcode) {
213         case MMC_READ_SINGLE_BLOCK:
214         case SD_APP_SEND_SCR:
215                 mmccmd |= SD_CMD_CT_2;
216                 break;
217         case MMC_READ_MULTIPLE_BLOCK:
218                 mmccmd |= SD_CMD_CT_4;
219                 break;
220         case MMC_WRITE_BLOCK:
221                 mmccmd |= SD_CMD_CT_1;
222                 break;
223
224         case MMC_WRITE_MULTIPLE_BLOCK:
225                 mmccmd |= SD_CMD_CT_3;
226                 break;
227         case MMC_STOP_TRANSMISSION:
228                 mmccmd |= SD_CMD_CT_7;
229                 break;
230         }
231
232         au_writel(cmd->arg, HOST_CMDARG(host));
233         au_sync();
234
235         if (wait)
236                 IRQ_OFF(host, SD_CONFIG_CR);
237
238         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
239         au_sync();
240
241         /* Wait for the command to go on the line */
242
243         while(1) {
244                 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
245                         break;
246         }
247
248         /* Wait for the command to come back */
249
250         if (wait) {
251                 u32 status = au_readl(HOST_STATUS(host));
252
253                 while(!(status & SD_STATUS_CR))
254                         status = au_readl(HOST_STATUS(host));
255
256                 /* Clear the CR status */
257                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
258
259                 IRQ_ON(host, SD_CONFIG_CR);
260         }
261
262         return MMC_ERR_NONE;
263 }
264
265 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
266 {
267
268         struct mmc_request *mrq = host->mrq;
269         struct mmc_data *data;
270         u32 crc;
271
272         WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
273
274         if (host->mrq == NULL)
275                 return;
276
277         data = mrq->cmd->data;
278
279         if (status == 0)
280                 status = au_readl(HOST_STATUS(host));
281
282         /* The transaction is really over when the SD_STATUS_DB bit is clear */
283
284         while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
285                 status = au_readl(HOST_STATUS(host));
286
287         data->error = MMC_ERR_NONE;
288         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
289
290         /* Process any errors */
291
292         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
293         if (host->flags & HOST_F_XMIT)
294                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
295
296         if (crc)
297                 data->error = MMC_ERR_BADCRC;
298
299         /* Clear the CRC bits */
300         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
301
302         data->bytes_xfered = 0;
303
304         if (data->error == MMC_ERR_NONE) {
305                 if (host->flags & HOST_F_DMA) {
306                         u32 chan = DMA_CHANNEL(host);
307
308                         chan_tab_t *c = *((chan_tab_t **) chan);
309                         au1x_dma_chan_t *cp = c->chan_ptr;
310                         data->bytes_xfered = cp->ddma_bytecnt;
311                 }
312                 else
313                         data->bytes_xfered =
314                                 (data->blocks * (1 << data->blksz_bits)) -
315                                 host->pio.len;
316         }
317
318         au1xmmc_finish_request(host);
319 }
320
321 static void au1xmmc_tasklet_data(unsigned long param)
322 {
323         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
324
325         u32 status = au_readl(HOST_STATUS(host));
326         au1xmmc_data_complete(host, status);
327 }
328
329 #define AU1XMMC_MAX_TRANSFER 8
330
331 static void au1xmmc_send_pio(struct au1xmmc_host *host)
332 {
333
334         struct mmc_data *data = 0;
335         int sg_len, max, count = 0;
336         unsigned char *sg_ptr;
337         u32 status = 0;
338         struct scatterlist *sg;
339
340         data = host->mrq->data;
341
342         if (!(host->flags & HOST_F_XMIT))
343                 return;
344
345         /* This is the pointer to the data buffer */
346         sg = &data->sg[host->pio.index];
347         sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
348
349         /* This is the space left inside the buffer */
350         sg_len = data->sg[host->pio.index].length - host->pio.offset;
351
352         /* Check to if we need less then the size of the sg_buffer */
353
354         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
355         if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
356
357         for(count = 0; count < max; count++ ) {
358                 unsigned char val;
359
360                 status = au_readl(HOST_STATUS(host));
361
362                 if (!(status & SD_STATUS_TH))
363                         break;
364
365                 val = *sg_ptr++;
366
367                 au_writel((unsigned long) val, HOST_TXPORT(host));
368                 au_sync();
369         }
370
371         host->pio.len -= count;
372         host->pio.offset += count;
373
374         if (count == sg_len) {
375                 host->pio.index++;
376                 host->pio.offset = 0;
377         }
378
379         if (host->pio.len == 0) {
380                 IRQ_OFF(host, SD_CONFIG_TH);
381
382                 if (host->flags & HOST_F_STOP)
383                         SEND_STOP(host);
384
385                 tasklet_schedule(&host->data_task);
386         }
387 }
388
389 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
390 {
391
392         struct mmc_data *data = 0;
393         int sg_len = 0, max = 0, count = 0;
394         unsigned char *sg_ptr = 0;
395         u32 status = 0;
396         struct scatterlist *sg;
397
398         data = host->mrq->data;
399
400         if (!(host->flags & HOST_F_RECV))
401                 return;
402
403         max = host->pio.len;
404
405         if (host->pio.index < host->dma.len) {
406                 sg = &data->sg[host->pio.index];
407                 sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
408
409                 /* This is the space left inside the buffer */
410                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
411
412                 /* Check to if we need less then the size of the sg_buffer */
413                 if (sg_len < max) max = sg_len;
414         }
415
416         if (max > AU1XMMC_MAX_TRANSFER)
417                 max = AU1XMMC_MAX_TRANSFER;
418
419         for(count = 0; count < max; count++ ) {
420                 u32 val;
421                 status = au_readl(HOST_STATUS(host));
422
423                 if (!(status & SD_STATUS_NE))
424                         break;
425
426                 if (status & SD_STATUS_RC) {
427                         DEBUG("RX CRC Error [%d + %d].\n", host->id,
428                                         host->pio.len, count);
429                         break;
430                 }
431
432                 if (status & SD_STATUS_RO) {
433                         DEBUG("RX Overrun [%d + %d]\n", host->id,
434                                         host->pio.len, count);
435                         break;
436                 }
437                 else if (status & SD_STATUS_RU) {
438                         DEBUG("RX Underrun [%d + %d]\n", host->id,
439                                         host->pio.len,  count);
440                         break;
441                 }
442
443                 val = au_readl(HOST_RXPORT(host));
444
445                 if (sg_ptr)
446                         *sg_ptr++ = (unsigned char) (val & 0xFF);
447         }
448
449         host->pio.len -= count;
450         host->pio.offset += count;
451
452         if (sg_len && count == sg_len) {
453                 host->pio.index++;
454                 host->pio.offset = 0;
455         }
456
457         if (host->pio.len == 0) {
458                 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
459                 IRQ_OFF(host, SD_CONFIG_NE);
460
461                 if (host->flags & HOST_F_STOP)
462                         SEND_STOP(host);
463
464                 tasklet_schedule(&host->data_task);
465         }
466 }
467
468 /* static void au1xmmc_cmd_complete
469    This is called when a command has been completed - grab the response
470    and check for errors.  Then start the data transfer if it is indicated.
471 */
472
473 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
474 {
475
476         struct mmc_request *mrq = host->mrq;
477         struct mmc_command *cmd;
478         int trans;
479
480         if (!host->mrq)
481                 return;
482
483         cmd = mrq->cmd;
484         cmd->error = MMC_ERR_NONE;
485
486         if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_SHORT) {
487
488                 /* Techincally, we should be getting all 48 bits of the response
489                  * (SD_RESP1 + SD_RESP2), but because our response omits the CRC,
490                  * our data ends up being shifted 8 bits to the right.  In this case,
491                  * that means that the OSR data starts at bit 31, so we can just
492                  * read RESP0 and return that
493                  */
494
495                 cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
496         }
497         else if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_LONG) {
498                 u32 r[4];
499                 int i;
500
501                 r[0] = au_readl(host->iobase + SD_RESP3);
502                 r[1] = au_readl(host->iobase + SD_RESP2);
503                 r[2] = au_readl(host->iobase + SD_RESP1);
504                 r[3] = au_readl(host->iobase + SD_RESP0);
505
506                 /* The CRC is omitted from the response, so really we only got
507                  * 120 bytes, but the engine expects 128 bits, so we have to shift
508                  * things up
509                  */
510
511                 for(i = 0; i < 4; i++) {
512                         cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
513                         if (i != 3) cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
514                 }
515         }
516
517         /* Figure out errors */
518
519         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
520                 cmd->error = MMC_ERR_BADCRC;
521
522         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
523
524         if (!trans || cmd->error != MMC_ERR_NONE) {
525
526                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
527                 tasklet_schedule(&host->finish_task);
528                 return;
529         }
530
531         host->status = HOST_S_DATA;
532
533         if (host->flags & HOST_F_DMA) {
534                 u32 channel = DMA_CHANNEL(host);
535
536                 /* Start the DMA as soon as the buffer gets something in it */
537
538                 if (host->flags & HOST_F_RECV) {
539                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
540
541                         while((status & mask) != mask)
542                                 status = au_readl(HOST_STATUS(host));
543                 }
544
545                 au1xxx_dbdma_start(channel);
546         }
547 }
548
549 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
550 {
551
552         unsigned int pbus = get_au1x00_speed();
553         unsigned int divisor;
554         u32 config;
555
556         /* From databook:
557            divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
558         */
559
560         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
561         pbus /= 2;
562
563         divisor = ((pbus / rate) / 2) - 1;
564
565         config = au_readl(HOST_CONFIG(host));
566
567         config &= ~(SD_CONFIG_DIV);
568         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
569
570         au_writel(config, HOST_CONFIG(host));
571         au_sync();
572 }
573
574 static int
575 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
576 {
577
578         int datalen = data->blocks * (1 << data->blksz_bits);
579
580         if (dma != 0)
581                 host->flags |= HOST_F_DMA;
582
583         if (data->flags & MMC_DATA_READ)
584                 host->flags |= HOST_F_RECV;
585         else
586                 host->flags |= HOST_F_XMIT;
587
588         if (host->mrq->stop)
589                 host->flags |= HOST_F_STOP;
590
591         host->dma.dir = DMA_BIDIRECTIONAL;
592
593         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
594                                    data->sg_len, host->dma.dir);
595
596         if (host->dma.len == 0)
597                 return MMC_ERR_TIMEOUT;
598
599         au_writel((1 << data->blksz_bits) - 1, HOST_BLKSIZE(host));
600
601         if (host->flags & HOST_F_DMA) {
602                 int i;
603                 u32 channel = DMA_CHANNEL(host);
604
605                 au1xxx_dbdma_stop(channel);
606
607                 for(i = 0; i < host->dma.len; i++) {
608                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
609                         struct scatterlist *sg = &data->sg[i];
610                         int sg_len = sg->length;
611
612                         int len = (datalen > sg_len) ? sg_len : datalen;
613
614                         if (i == host->dma.len - 1)
615                                 flags = DDMA_FLAGS_IE;
616
617                         if (host->flags & HOST_F_XMIT){
618                                 ret = au1xxx_dbdma_put_source_flags(channel,
619                                         (void *) (page_address(sg->page) +
620                                                   sg->offset),
621                                         len, flags);
622                         }
623                         else {
624                                 ret = au1xxx_dbdma_put_dest_flags(channel,
625                                         (void *) (page_address(sg->page) +
626                                                   sg->offset),
627                                         len, flags);
628                         }
629
630                         if (!ret)
631                                 goto dataerr;
632
633                         datalen -= len;
634                 }
635         }
636         else {
637                 host->pio.index = 0;
638                 host->pio.offset = 0;
639                 host->pio.len = datalen;
640
641                 if (host->flags & HOST_F_XMIT)
642                         IRQ_ON(host, SD_CONFIG_TH);
643                 else
644                         IRQ_ON(host, SD_CONFIG_NE);
645                         //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
646         }
647
648         return MMC_ERR_NONE;
649
650  dataerr:
651         dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
652         return MMC_ERR_TIMEOUT;
653 }
654
655 /* static void au1xmmc_request
656    This actually starts a command or data transaction
657 */
658
659 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
660 {
661
662         struct au1xmmc_host *host = mmc_priv(mmc);
663         int ret = MMC_ERR_NONE;
664
665         WARN_ON(irqs_disabled());
666         WARN_ON(host->status != HOST_S_IDLE);
667
668         host->mrq = mrq;
669         host->status = HOST_S_CMD;
670
671         bcsr->disk_leds &= ~(1 << 8);
672
673         if (mrq->data) {
674                 FLUSH_FIFO(host);
675                 ret = au1xmmc_prepare_data(host, mrq->data);
676         }
677
678         if (ret == MMC_ERR_NONE)
679                 ret = au1xmmc_send_command(host, 0, mrq->cmd);
680
681         if (ret != MMC_ERR_NONE) {
682                 mrq->cmd->error = ret;
683                 au1xmmc_finish_request(host);
684         }
685 }
686
687 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
688 {
689
690         /* Apply the clock */
691         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
692         au_sync_delay(1);
693
694         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
695         au_sync_delay(5);
696
697         au_writel(~0, HOST_STATUS(host));
698         au_sync();
699
700         au_writel(0, HOST_BLKSIZE(host));
701         au_writel(0x001fffff, HOST_TIMEOUT(host));
702         au_sync();
703
704         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
705         au_sync();
706
707         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
708         au_sync_delay(1);
709
710         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
711         au_sync();
712
713         /* Configure interrupts */
714         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
715         au_sync();
716 }
717
718
719 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
720 {
721         struct au1xmmc_host *host = mmc_priv(mmc);
722
723         DEBUG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n",
724               host->id, ios->power_mode, ios->clock, ios->vdd,
725               ios->bus_mode);
726
727         if (ios->power_mode == MMC_POWER_OFF)
728                 au1xmmc_set_power(host, 0);
729         else if (ios->power_mode == MMC_POWER_ON) {
730                 au1xmmc_set_power(host, 1);
731         }
732
733         if (ios->clock && ios->clock != host->clock) {
734                 au1xmmc_set_clock(host, ios->clock);
735                 host->clock = ios->clock;
736         }
737 }
738
739 static void au1xmmc_dma_callback(int irq, void *dev_id, struct pt_regs *regs)
740 {
741         struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
742         u32 status;
743
744         /* Avoid spurious interrupts */
745
746         if (!host->mrq)
747                 return;
748
749         if (host->flags & HOST_F_STOP)
750                 SEND_STOP(host);
751
752         tasklet_schedule(&host->data_task);
753 }
754
755 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
756 #define STATUS_DATA_IN  (SD_STATUS_NE)
757 #define STATUS_DATA_OUT (SD_STATUS_TH)
758
759 static irqreturn_t au1xmmc_irq(int irq, void *dev_id, struct pt_regs *regs)
760 {
761
762         u32 status;
763         int i, ret = 0;
764
765         disable_irq(AU1100_SD_IRQ);
766
767         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
768                 struct au1xmmc_host * host = au1xmmc_hosts[i];
769                 u32 handled = 1;
770
771                 status = au_readl(HOST_STATUS(host));
772
773                 if (host->mrq && (status & STATUS_TIMEOUT)) {
774                         if (status & SD_STATUS_RAT)
775                                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
776
777                         else if (status & SD_STATUS_DT)
778                                 host->mrq->data->error = MMC_ERR_TIMEOUT;
779
780                         /* In PIO mode, interrupts might still be enabled */
781                         IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
782
783                         //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
784                         tasklet_schedule(&host->finish_task);
785                 }
786 #if 0
787                 else if (status & SD_STATUS_DD) {
788
789                         /* Sometimes we get a DD before a NE in PIO mode */
790
791                         if (!(host->flags & HOST_F_DMA) &&
792                                         (status & SD_STATUS_NE))
793                                 au1xmmc_receive_pio(host);
794                         else {
795                                 au1xmmc_data_complete(host, status);
796                                 //tasklet_schedule(&host->data_task);
797                         }
798                 }
799 #endif
800                 else if (status & (SD_STATUS_CR)) {
801                         if (host->status == HOST_S_CMD)
802                                 au1xmmc_cmd_complete(host,status);
803                 }
804                 else if (!(host->flags & HOST_F_DMA)) {
805                         if ((host->flags & HOST_F_XMIT) &&
806                             (status & STATUS_DATA_OUT))
807                                 au1xmmc_send_pio(host);
808                         else if ((host->flags & HOST_F_RECV) &&
809                             (status & STATUS_DATA_IN))
810                                 au1xmmc_receive_pio(host);
811                 }
812                 else if (status & 0x203FBC70) {
813                         DEBUG("Unhandled status %8.8x\n", host->id, status);
814                         handled = 0;
815                 }
816
817                 au_writel(status, HOST_STATUS(host));
818                 au_sync();
819
820                 ret |= handled;
821         }
822
823         enable_irq(AU1100_SD_IRQ);
824         return ret;
825 }
826
827 static void au1xmmc_poll_event(unsigned long arg)
828 {
829         struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
830
831         int card = au1xmmc_card_inserted(host);
832         int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
833
834         if (card != controller) {
835                 host->flags &= ~HOST_F_ACTIVE;
836                 if (card) host->flags |= HOST_F_ACTIVE;
837                 mmc_detect_change(host->mmc, 0);
838         }
839
840         if (host->mrq != NULL) {
841                 u32 status = au_readl(HOST_STATUS(host));
842                 DEBUG("PENDING - %8.8x\n", host->id, status);
843         }
844
845         mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
846 }
847
848 static dbdev_tab_t au1xmmc_mem_dbdev =
849 {
850         DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
851 };
852
853 static void au1xmmc_init_dma(struct au1xmmc_host *host)
854 {
855
856         u32 rxchan, txchan;
857
858         int txid = au1xmmc_card_table[host->id].tx_devid;
859         int rxid = au1xmmc_card_table[host->id].rx_devid;
860
861         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
862            of 8 bits.  And since devices are shared, we need to create
863            our own to avoid freaking out other devices
864         */
865
866         int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
867
868         txchan = au1xxx_dbdma_chan_alloc(memid, txid,
869                                          au1xmmc_dma_callback, (void *) host);
870
871         rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
872                                          au1xmmc_dma_callback, (void *) host);
873
874         au1xxx_dbdma_set_devwidth(txchan, 8);
875         au1xxx_dbdma_set_devwidth(rxchan, 8);
876
877         au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
878         au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
879
880         host->tx_chan = txchan;
881         host->rx_chan = rxchan;
882 }
883
884 struct mmc_host_ops au1xmmc_ops = {
885         .request        = au1xmmc_request,
886         .set_ios        = au1xmmc_set_ios,
887 };
888
889 static int au1xmmc_probe(struct device *dev)
890 {
891
892         int i, ret = 0;
893
894         /* THe interrupt is shared among all controllers */
895         ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, SA_INTERRUPT, "MMC", 0);
896
897         if (ret) {
898                 printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
899                                 AU1100_SD_IRQ, ret);
900                 return -ENXIO;
901         }
902
903         disable_irq(AU1100_SD_IRQ);
904
905         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
906                 struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), dev);
907                 struct au1xmmc_host *host = 0;
908
909                 if (!mmc) {
910                         printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
911                         au1xmmc_hosts[i] = 0;
912                         continue;
913                 }
914
915                 mmc->ops = &au1xmmc_ops;
916
917                 mmc->f_min =   450000;
918                 mmc->f_max = 24000000;
919
920                 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
921                 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
922
923                 mmc->ocr_avail = AU1XMMC_OCR;
924
925                 host = mmc_priv(mmc);
926                 host->mmc = mmc;
927
928                 host->id = i;
929                 host->iobase = au1xmmc_card_table[host->id].iobase;
930                 host->clock = 0;
931                 host->power_mode = MMC_POWER_OFF;
932
933                 host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
934                 host->status = HOST_S_IDLE;
935
936                 init_timer(&host->timer);
937
938                 host->timer.function = au1xmmc_poll_event;
939                 host->timer.data = (unsigned long) host;
940                 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
941
942                 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
943                                 (unsigned long) host);
944
945                 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
946                                 (unsigned long) host);
947
948                 spin_lock_init(&host->lock);
949
950                 if (dma != 0)
951                         au1xmmc_init_dma(host);
952
953                 au1xmmc_reset_controller(host);
954
955                 mmc_add_host(mmc);
956                 au1xmmc_hosts[i] = host;
957
958                 add_timer(&host->timer);
959
960                 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
961                        host->id, host->iobase, dma ? "dma" : "pio");
962         }
963
964         enable_irq(AU1100_SD_IRQ);
965
966         return 0;
967 }
968
969 static int au1xmmc_remove(struct device *dev)
970 {
971
972         int i;
973
974         disable_irq(AU1100_SD_IRQ);
975
976         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
977                 struct au1xmmc_host *host = au1xmmc_hosts[i];
978                 if (!host) continue;
979
980                 tasklet_kill(&host->data_task);
981                 tasklet_kill(&host->finish_task);
982
983                 del_timer_sync(&host->timer);
984                 au1xmmc_set_power(host, 0);
985
986                 mmc_remove_host(host->mmc);
987
988                 au1xxx_dbdma_chan_free(host->tx_chan);
989                 au1xxx_dbdma_chan_free(host->rx_chan);
990
991                 au_writel(0x0, HOST_ENABLE(host));
992                 au_sync();
993         }
994
995         free_irq(AU1100_SD_IRQ, 0);
996         return 0;
997 }
998
999 static struct device_driver au1xmmc_driver = {
1000         .name          = DRIVER_NAME,
1001         .bus           = &platform_bus_type,
1002         .probe         = au1xmmc_probe,
1003         .remove        = au1xmmc_remove,
1004         .suspend       = NULL,
1005         .resume        = NULL
1006 };
1007
1008 static int __init au1xmmc_init(void)
1009 {
1010         return driver_register(&au1xmmc_driver);
1011 }
1012
1013 static void __exit au1xmmc_exit(void)
1014 {
1015         driver_unregister(&au1xmmc_driver);
1016 }
1017
1018 module_init(au1xmmc_init);
1019 module_exit(au1xmmc_exit);
1020
1021 #ifdef MODULE
1022 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1023 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1024 MODULE_LICENSE("GPL");
1025 #endif
1026