ARM: tegra: Add Tegra Profiler
[linux-2.6.git] / drivers / misc / tegra-profiler / armv7_pmu.h
1 /*
2  * drivers/misc/tegra-profiler/armv7_pmu.h
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  */
16
17 #ifndef __ARMV7_PMU_H
18 #define __ARMV7_PMU_H
19
20 #define QUADD_ARM_CPU_IMPLEMENTER 0x41
21
22 enum {
23         QUADD_ARM_CPU_TYPE_UNKNOWN,
24         QUADD_ARM_CPU_TYPE_CORTEX_A5,
25         QUADD_ARM_CPU_TYPE_CORTEX_A8,
26         QUADD_ARM_CPU_TYPE_CORTEX_A9,
27         QUADD_ARM_CPU_TYPE_CORTEX_A15,
28 };
29
30 #define QUADD_ARM_CPU_PART_NUMBER_CORTEX_A5     0xC050
31 #define QUADD_ARM_CPU_PART_NUMBER_CORTEX_A8     0xC080
32 #define QUADD_ARM_CPU_PART_NUMBER_CORTEX_A9     0xC090
33 #define QUADD_ARM_CPU_PART_NUMBER_CORTEX_A15    0xC0F0
34
35
36 #define QUADD_MAX_PMU_COUNTERS  32
37
38 struct quadd_pmu_event_info {
39         int quadd_event_id;
40         int hw_value;
41         int counter_idx;
42 };
43
44 struct armv7_pmu_ctx {
45         int arch;
46         char arch_name[32];
47
48         int nr_counters;
49         u32 counters_mask;
50
51         struct quadd_pmu_event_info pmu_events[QUADD_MAX_PMU_COUNTERS];
52         int nr_used_counters;
53
54         int l1_cache_rw;
55         int *current_map;
56 };
57
58 struct quadd_event_source_interface;
59
60 extern struct quadd_event_source_interface *quadd_armv7_pmu_init(void);
61
62 /*
63  * PMNC Register
64  */
65
66  /* 0/1: disables/enables all counters, including CCNT */
67 #define QUADD_ARMV7_PMNC_E              (1 << 0)
68 /* 1: Resets all performance counters to zero. */
69 #define QUADD_ARMV7_PMNC_P              (1 << 1)
70 /* 1: Resets cycle counter, CCNT, to zero. */
71 #define QUADD_ARMV7_PMNC_C              (1 << 2)
72 /* 0: counts every processor clock cycle, reset value. 1:
73    counts every 64th processor clock cycle. */
74 #define QUADD_ARMV7_PMNC_D              (1 << 3)
75 /* 0/1: Export to ETM disabled/enabled */
76 #define QUADD_ARMV7_PMNC_X              (1 << 4)
77 /* 0/1: count is disabled/enabled in regions where
78    non-invasive debug is prohibited */
79 #define QUADD_ARMV7_PMNC_DP             (1 << 5)
80 /* Mask for writable bits */
81 #define QUADD_ARMV7_PMNC_MASK           0x3f
82
83
84 #define QUADD_ARMV7_CCNT                (1 << 31)       /* Cycle counter */
85
86 #define QUADD_ARMV7_CYCLE_COUNTER       -1
87
88 /*
89  * CNTENS: counters enable reg
90  */
91 #define QUADD_ARMV7_CNTENS_P(i)         (1 << i)
92 #define QUADD_ARMV7_CNTENS_C            (1 << QUADD_ARMV7_CCNT)
93
94 /*
95  * CNTENC: counters disable reg
96  */
97 #define QUADD_ARMV7_CNTENC_P(i) (1 << i)
98 #define QUADD_ARMV7_CNTENC_C    (1 << QUADD_ARMV7_CCNT)
99
100 /*
101  * Performance Counter Selection Register mask
102  */
103 #define QUADD_ARMV7_SELECT_MASK 0x1f
104
105 /*
106  * EVTSEL Register mask
107  */
108 #define QUADD_ARMV7_EVTSEL_MASK 0xff
109
110 #define QUADD_ARMV7_COUNTERS_MASK_CORTEX_A5             0x03
111 #define QUADD_ARMV7_COUNTERS_MASK_CORTEX_A8             0x0f
112 #define QUADD_ARMV7_COUNTERS_MASK_CORTEX_A9             0x3f
113 #define QUADD_ARMV7_COUNTERS_MASK_CORTEX_A15            0x3f
114
115 enum quadd_armv7_common_events {
116         QUADD_ARMV7_HW_EVENT_PMNC_SW_INCR               = 0x00,
117         QUADD_ARMV7_HW_EVENT_IFETCH_MISS                = 0x01,
118         QUADD_ARMV7_HW_EVENT_ITLB_MISS                  = 0x02,
119         QUADD_ARMV7_HW_EVENT_DCACHE_REFILL              = 0x03,
120         QUADD_ARMV7_HW_EVENT_DCACHE_ACCESS              = 0x04,
121         QUADD_ARMV7_HW_EVENT_DTLB_REFILL                = 0x05,
122         QUADD_ARMV7_HW_EVENT_DREAD                      = 0x06,
123         QUADD_ARMV7_HW_EVENT_DWRITE                     = 0x07,
124         QUADD_ARMV7_HW_EVENT_INSTR_EXECUTED             = 0x08,
125         QUADD_ARMV7_HW_EVENT_EXC_TAKEN                  = 0x09,
126         QUADD_ARMV7_HW_EVENT_EXC_EXECUTED               = 0x0A,
127         QUADD_ARMV7_HW_EVENT_CID_WRITE                  = 0x0B,
128         QUADD_ARMV7_HW_EVENT_PC_WRITE                   = 0x0C,
129         QUADD_ARMV7_HW_EVENT_PC_IMM_BRANCH              = 0x0D,
130         QUADD_ARMV7_HW_EVENT_PC_PROC_RETURN             = 0x0E,
131         QUADD_ARMV7_HW_EVENT_UNALIGNED_ACCESS           = 0x0F,
132
133         QUADD_ARMV7_HW_EVENT_PC_BRANCH_MIS_PRED         = 0x10,
134         QUADD_ARMV7_HW_EVENT_CLOCK_CYCLES               = 0x11,
135         QUADD_ARMV7_HW_EVENT_PC_BRANCH_PRED             = 0x12,
136         QUADD_ARMV7_HW_EVENT_MEM_ACCESS                 = 0x13,
137         QUADD_ARMV7_HW_EVENT_L1_ICACHE_ACCESS           = 0x14,
138         QUADD_ARMV7_HW_EVENT_L1_DCACHE_WB               = 0x15,
139         QUADD_ARMV7_HW_EVENT_L2_DCACHE_ACCESS           = 0x16,
140         QUADD_ARMV7_HW_EVENT_L2_DCACHE_REFILL           = 0x17,
141         QUADD_ARMV7_HW_EVENT_L2_DCACHE_WB               = 0x18,
142         QUADD_ARMV7_HW_EVENT_BUS_ACCESS                 = 0x19,
143         QUADD_ARMV7_HW_EVENT_MEMORY_ERROR               = 0x1A,
144         QUADD_ARMV7_HW_EVENT_INSTR_SPEC                 = 0x1B,
145         QUADD_ARMV7_HW_EVENT_TTBR_WRITE                 = 0x1C,
146         QUADD_ARMV7_HW_EVENT_BUS_CYCLES                 = 0x1D,
147 };
148
149 enum quadd_armv7_a8_specific_events {
150         QUADD_ARMV7_A8_HW_EVENT_WRITE_BUFFER_FULL                       = 0x40,
151         QUADD_ARMV7_A8_HW_EVENT_L2_STORE_MERGED                         = 0x41,
152         QUADD_ARMV7_A8_HW_EVENT_L2_STORE_BUFF                           = 0x42,
153         QUADD_ARMV7_A8_HW_EVENT_L2_ACCESS                               = 0x43,
154         QUADD_ARMV7_A8_HW_EVENT_L2_CACH_MISS                            = 0x44,
155         QUADD_ARMV7_A8_HW_EVENT_AXI_READ_CYCLES                         = 0x45,
156         QUADD_ARMV7_A8_HW_EVENT_AXI_WRITE_CYCLES                        = 0x46,
157         QUADD_ARMV7_A8_HW_EVENT_MEMORY_REPLAY                           = 0x47,
158         QUADD_ARMV7_A8_HW_EVENT_UNALIGNED_ACCESS_REPLAY                 = 0x48,
159         QUADD_ARMV7_A8_HW_EVENT_L1_DATA_MISS                            = 0x49,
160         QUADD_ARMV7_A8_HW_EVENT_L1_INST_MISS                            = 0x4A,
161         QUADD_ARMV7_A8_HW_EVENT_L1_DATA_COLORING                        = 0x4B,
162         QUADD_ARMV7_A8_HW_EVENT_L1_NEON_DATA                            = 0x4C,
163         QUADD_ARMV7_A8_HW_EVENT_L1_NEON_CACH_DATA                       = 0x4D,
164         QUADD_ARMV7_A8_HW_EVENT_L2_NEON                                 = 0x4E,
165         QUADD_ARMV7_A8_HW_EVENT_L2_NEON_HIT                             = 0x4F,
166         QUADD_ARMV7_A8_HW_EVENT_L1_INST                                 = 0x50,
167         QUADD_ARMV7_A8_HW_EVENT_PC_RETURN_MIS_PRED                      = 0x51,
168         QUADD_ARMV7_A8_HW_EVENT_PC_BRANCH_FAILED                        = 0x52,
169         QUADD_ARMV7_A8_HW_EVENT_PC_BRANCH_TAKEN                         = 0x53,
170         QUADD_ARMV7_A8_HW_EVENT_PC_BRANCH_EXECUTED                      = 0x54,
171         QUADD_ARMV7_A8_HW_EVENT_OP_EXECUTED                             = 0x55,
172         QUADD_ARMV7_A8_HW_EVENT_CYCLES_INST_STALL                       = 0x56,
173         QUADD_ARMV7_A8_HW_EVENT_CYCLES_INST                             = 0x57,
174         QUADD_ARMV7_A8_HW_EVENT_CYCLES_NEON_DATA_STALL                  = 0x58,
175         QUADD_ARMV7_A8_HW_EVENT_CYCLES_NEON_INST_STALL                  = 0x59,
176         QUADD_ARMV7_A8_HW_EVENT_NEON_CYCLES                             = 0x5A,
177
178         QUADD_ARMV7_A8_HW_EVENT_PMU0_EVENTS                             = 0x70,
179         QUADD_ARMV7_A8_HW_EVENT_PMU1_EVENTS                             = 0x71,
180         QUADD_ARMV7_A8_HW_EVENT_PMU_EVENTS                              = 0x72,
181 };
182
183 enum quadd_armv7_a9_specific_events {
184         QUADD_ARMV7_A9_HW_EVENT_JAVA_HW_BYTECODE_EXEC                   = 0x40,
185         QUADD_ARMV7_A9_HW_EVENT_JAVA_SW_BYTECODE_EXEC                   = 0x41,
186         QUADD_ARMV7_A9_HW_EVENT_JAZELLE_BRANCH_EXEC                     = 0x42,
187
188         QUADD_ARMV7_A9_HW_EVENT_COHERENT_LINE_MISS                      = 0x50,
189         QUADD_ARMV7_A9_HW_EVENT_COHERENT_LINE_HIT                       = 0x51,
190
191         QUADD_ARMV7_A9_HW_EVENT_ICACHE_DEP_STALL_CYCLES                 = 0x60,
192         QUADD_ARMV7_A9_HW_EVENT_DCACHE_DEP_STALL_CYCLES                 = 0x61,
193         QUADD_ARMV7_A9_HW_EVENT_TLB_MISS_DEP_STALL_CYCLES               = 0x62,
194         QUADD_ARMV7_A9_HW_EVENT_STREX_EXECUTED_PASSED                   = 0x63,
195         QUADD_ARMV7_A9_HW_EVENT_STREX_EXECUTED_FAILED                   = 0x64,
196         QUADD_ARMV7_A9_HW_EVENT_DATA_EVICTION                           = 0x65,
197         QUADD_ARMV7_A9_HW_EVENT_ISSUE_STAGE_NO_INST                     = 0x66,
198         QUADD_ARMV7_A9_HW_EVENT_ISSUE_STAGE_EMPTY                       = 0x67,
199         QUADD_ARMV7_A9_HW_EVENT_INST_OUT_OF_RENAME_STAGE                = 0x68,
200
201         QUADD_ARMV7_A9_HW_EVENT_PREDICTABLE_FUNCT_RETURNS               = 0x6E,
202
203         QUADD_ARMV7_A9_HW_EVENT_MAIN_UNIT_EXECUTED_INST                 = 0x70,
204         QUADD_ARMV7_A9_HW_EVENT_SECOND_UNIT_EXECUTED_INST               = 0x71,
205         QUADD_ARMV7_A9_HW_EVENT_LD_ST_UNIT_EXECUTED_INST                = 0x72,
206         QUADD_ARMV7_A9_HW_EVENT_FP_EXECUTED_INST                        = 0x73,
207         QUADD_ARMV7_A9_HW_EVENT_NEON_EXECUTED_INST                      = 0x74,
208
209         QUADD_ARMV7_A9_HW_EVENT_PLD_FULL_DEP_STALL_CYCLES               = 0x80,
210         QUADD_ARMV7_A9_HW_EVENT_DATA_WR_DEP_STALL_CYCLES                = 0x81,
211         QUADD_ARMV7_A9_HW_EVENT_ITLB_MISS_DEP_STALL_CYCLES              = 0x82,
212         QUADD_ARMV7_A9_HW_EVENT_DTLB_MISS_DEP_STALL_CYCLES              = 0x83,
213         QUADD_ARMV7_A9_HW_EVENT_MICRO_ITLB_MISS_DEP_STALL_CYCLES        = 0x84,
214         QUADD_ARMV7_A9_HW_EVENT_MICRO_DTLB_MISS_DEP_STALL_CYCLES        = 0x85,
215         QUADD_ARMV7_A9_HW_EVENT_DMB_DEP_STALL_CYCLES                    = 0x86,
216
217         QUADD_ARMV7_A9_HW_EVENT_INTGR_CLK_ENABLED_CYCLES                = 0x8A,
218         QUADD_ARMV7_A9_HW_EVENT_DATA_ENGINE_CLK_EN_CYCLES               = 0x8B,
219
220         QUADD_ARMV7_A9_HW_EVENT_ISB_INST                                = 0x90,
221         QUADD_ARMV7_A9_HW_EVENT_DSB_INST                                = 0x91,
222         QUADD_ARMV7_A9_HW_EVENT_DMB_INST                                = 0x92,
223         QUADD_ARMV7_A9_HW_EVENT_EXT_INTERRUPTS                          = 0x93,
224
225         QUADD_ARMV7_A9_HW_EVENT_PLE_CACHE_LINE_RQST_COMPLETED           = 0xA0,
226         QUADD_ARMV7_A9_HW_EVENT_PLE_CACHE_LINE_RQST_SKIPPED             = 0xA1,
227         QUADD_ARMV7_A9_HW_EVENT_PLE_FIFO_FLUSH                          = 0xA2,
228         QUADD_ARMV7_A9_HW_EVENT_PLE_RQST_COMPLETED                      = 0xA3,
229         QUADD_ARMV7_A9_HW_EVENT_PLE_FIFO_OVERFLOW                       = 0xA4,
230         QUADD_ARMV7_A9_HW_EVENT_PLE_RQST_PROG                           = 0xA5
231 };
232
233 enum quadd_armv7_a5_specific_events {
234         QUADD_ARMV7_A5_HW_EVENT_IRQ_TAKEN                               = 0x86,
235         QUADD_ARMV7_A5_HW_EVENT_FIQ_TAKEN                               = 0x87,
236
237         QUADD_ARMV7_A5_HW_EVENT_EXT_MEM_RQST                            = 0xc0,
238         QUADD_ARMV7_A5_HW_EVENT_NC_EXT_MEM_RQST                         = 0xc1,
239         QUADD_ARMV7_A5_HW_EVENT_PREFETCH_LINEFILL                       = 0xc2,
240         QUADD_ARMV7_A5_HW_EVENT_PREFETCH_LINEFILL_DROP                  = 0xc3,
241         QUADD_ARMV7_A5_HW_EVENT_ENTER_READ_ALLOC                        = 0xc4,
242         QUADD_ARMV7_A5_HW_EVENT_READ_ALLOC                              = 0xc5,
243
244         QUADD_ARMV7_A5_HW_EVENT_STALL_SB_FULL                           = 0xc9,
245 };
246
247 enum quadd_armv7_a15_specific_events {
248         QUADD_ARMV7_A15_HW_EVENT_L1_DCACHE_READ_ACCESS  = 0x40,
249         QUADD_ARMV7_A15_HW_EVENT_L1_DCACHE_WRITE_ACCESS = 0x41,
250         QUADD_ARMV7_A15_HW_EVENT_L1_DCACHE_READ_REFILL  = 0x42,
251         QUADD_ARMV7_A15_HW_EVENT_L1_DCACHE_WRITE_REFILL = 0x43,
252
253         QUADD_ARMV7_A15_HW_EVENT_L1_DTLB_READ_REFILL    = 0x4C,
254         QUADD_ARMV7_A15_HW_EVENT_L1_DTLB_WRITE_REFILL   = 0x4D,
255
256         QUADD_ARMV7_A15_HW_EVENT_L2_DCACHE_READ_ACCESS  = 0x50,
257         QUADD_ARMV7_A15_HW_EVENT_L2_DCACHE_WRITE_ACCESS = 0x51,
258         QUADD_ARMV7_A15_HW_EVENT_L2_DCACHE_READ_REFILL  = 0x52,
259         QUADD_ARMV7_A15_HW_EVENT_L2_DCACHE_WRITE_REFILL = 0x53,
260
261         QUADD_ARMV7_A15_HW_EVENT_SPEC_PC_WRITE          = 0x76,
262 };
263
264 #define QUADD_ARMV7_UNSUPPORTED_EVENT   0xff00
265 #define QUADD_ARMV7_CPU_CYCLE_EVENT     0xffff
266
267 void quadd_pmu_test(void);
268
269 #endif  /* __ARMV7_PMU_H */