d06cf2f47742046ec5f8da875f21d718811729b2
[linux-2.6.git] / drivers / misc / pch_phub.c
1 /*
2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; version 2 of the License.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
16  */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/fs.h>
22 #include <linux/uaccess.h>
23 #include <linux/string.h>
24 #include <linux/pci.h>
25 #include <linux/io.h>
26 #include <linux/delay.h>
27 #include <linux/mutex.h>
28 #include <linux/if_ether.h>
29 #include <linux/ctype.h>
30 #include <linux/dmi.h>
31
32 #define PHUB_STATUS 0x00                /* Status Register offset */
33 #define PHUB_CONTROL 0x04               /* Control Register offset */
34 #define PHUB_TIMEOUT 0x05               /* Time out value for Status Register */
35 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01  /* Enabling for writing ROM */
36 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
37 #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14  /* MAC data area start address
38                                                offset */
39 #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C  /* MAC data area start address
40                                                  offset */
41 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
42                                               (Intel EG20T PCH)*/
43 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
44                                                 offset(OKI SEMICONDUCTOR ML7213)
45                                               */
46 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
47                                                 offset(OKI SEMICONDUCTOR ML7223)
48                                               */
49
50 /* MAX number of INT_REDUCE_CONTROL registers */
51 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128
52 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801
53 #define PCH_MINOR_NOS 1
54 #define CLKCFG_CAN_50MHZ 0x12000000
55 #define CLKCFG_CANCLK_MASK 0xFF000000
56 #define CLKCFG_UART_MASK                        0xFFFFFF
57
58 /* CM-iTC */
59 #define CLKCFG_UART_48MHZ                       (1 << 16)
60 #define CLKCFG_BAUDDIV                          (2 << 20)
61 #define CLKCFG_PLL2VCO                          (8 << 9)
62 #define CLKCFG_UARTCLKSEL                       (1 << 18)
63
64 /* Macros for ML7213 */
65 #define PCI_VENDOR_ID_ROHM                      0x10db
66 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
67
68 /* Macros for ML7213 */
69 #define PCI_VENDOR_ID_ROHM                      0x10db
70 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
71
72 /* Macros for ML7223 */
73 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
74 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
75
76 /* SROM ACCESS Macro */
77 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
78
79 /* Registers address offset */
80 #define PCH_PHUB_ID_REG                         0x0000
81 #define PCH_PHUB_QUEUE_PRI_VAL_REG              0x0004
82 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG           0x0008
83 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG          0x000C
84 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG          0x0010
85 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG          0x0014
86 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG        0x0018
87 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0        0x0020
88 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1        0x0024
89 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2        0x0028
90 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3        0x002C
91 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE    0x0040
92 #define CLKCFG_REG_OFFSET                       0x500
93
94 #define PCH_PHUB_OROM_SIZE 15360
95
96 /**
97  * struct pch_phub_reg - PHUB register structure
98  * @phub_id_reg:                        PHUB_ID register val
99  * @q_pri_val_reg:                      QUEUE_PRI_VAL register val
100  * @rc_q_maxsize_reg:                   RC_QUEUE_MAXSIZE register val
101  * @bri_q_maxsize_reg:                  BRI_QUEUE_MAXSIZE register val
102  * @comp_resp_timeout_reg:              COMP_RESP_TIMEOUT register val
103  * @bus_slave_control_reg:              BUS_SLAVE_CONTROL_REG register val
104  * @deadlock_avoid_type_reg:            DEADLOCK_AVOID_TYPE register val
105  * @intpin_reg_wpermit_reg0:            INTPIN_REG_WPERMIT register 0 val
106  * @intpin_reg_wpermit_reg1:            INTPIN_REG_WPERMIT register 1 val
107  * @intpin_reg_wpermit_reg2:            INTPIN_REG_WPERMIT register 2 val
108  * @intpin_reg_wpermit_reg3:            INTPIN_REG_WPERMIT register 3 val
109  * @int_reduce_control_reg:             INT_REDUCE_CONTROL registers val
110  * @clkcfg_reg:                         CLK CFG register val
111  * @pch_phub_base_address:              Register base address
112  * @pch_phub_extrom_base_address:       external rom base address
113  * @pch_mac_start_address:              MAC address area start address
114  * @pch_opt_rom_start_address:          Option ROM start address
115  * @ioh_type:                           Save IOH type
116  */
117 struct pch_phub_reg {
118         u32 phub_id_reg;
119         u32 q_pri_val_reg;
120         u32 rc_q_maxsize_reg;
121         u32 bri_q_maxsize_reg;
122         u32 comp_resp_timeout_reg;
123         u32 bus_slave_control_reg;
124         u32 deadlock_avoid_type_reg;
125         u32 intpin_reg_wpermit_reg0;
126         u32 intpin_reg_wpermit_reg1;
127         u32 intpin_reg_wpermit_reg2;
128         u32 intpin_reg_wpermit_reg3;
129         u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
130         u32 clkcfg_reg;
131         void __iomem *pch_phub_base_address;
132         void __iomem *pch_phub_extrom_base_address;
133         u32 pch_mac_start_address;
134         u32 pch_opt_rom_start_address;
135         int ioh_type;
136 };
137
138 /* SROM SPEC for MAC address assignment offset */
139 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
140
141 static DEFINE_MUTEX(pch_phub_mutex);
142
143 /**
144  * pch_phub_read_modify_write_reg() - Reading modifying and writing register
145  * @reg_addr_offset:    Register offset address value.
146  * @data:               Writing value.
147  * @mask:               Mask value.
148  */
149 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
150                                            unsigned int reg_addr_offset,
151                                            unsigned int data, unsigned int mask)
152 {
153         void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
154         iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
155 }
156
157 /* pch_phub_save_reg_conf - saves register configuration */
158 static void pch_phub_save_reg_conf(struct pci_dev *pdev)
159 {
160         unsigned int i;
161         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
162
163         void __iomem *p = chip->pch_phub_base_address;
164
165         chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
166         chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
167         chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
168         chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
169         chip->comp_resp_timeout_reg =
170                                 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
171         chip->bus_slave_control_reg =
172                                 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
173         chip->deadlock_avoid_type_reg =
174                                 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
175         chip->intpin_reg_wpermit_reg0 =
176                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
177         chip->intpin_reg_wpermit_reg1 =
178                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
179         chip->intpin_reg_wpermit_reg2 =
180                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
181         chip->intpin_reg_wpermit_reg3 =
182                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
183         dev_dbg(&pdev->dev, "%s : "
184                 "chip->phub_id_reg=%x, "
185                 "chip->q_pri_val_reg=%x, "
186                 "chip->rc_q_maxsize_reg=%x, "
187                 "chip->bri_q_maxsize_reg=%x, "
188                 "chip->comp_resp_timeout_reg=%x, "
189                 "chip->bus_slave_control_reg=%x, "
190                 "chip->deadlock_avoid_type_reg=%x, "
191                 "chip->intpin_reg_wpermit_reg0=%x, "
192                 "chip->intpin_reg_wpermit_reg1=%x, "
193                 "chip->intpin_reg_wpermit_reg2=%x, "
194                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
195                 chip->phub_id_reg,
196                 chip->q_pri_val_reg,
197                 chip->rc_q_maxsize_reg,
198                 chip->bri_q_maxsize_reg,
199                 chip->comp_resp_timeout_reg,
200                 chip->bus_slave_control_reg,
201                 chip->deadlock_avoid_type_reg,
202                 chip->intpin_reg_wpermit_reg0,
203                 chip->intpin_reg_wpermit_reg1,
204                 chip->intpin_reg_wpermit_reg2,
205                 chip->intpin_reg_wpermit_reg3);
206         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
207                 chip->int_reduce_control_reg[i] =
208                     ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
209                 dev_dbg(&pdev->dev, "%s : "
210                         "chip->int_reduce_control_reg[%d]=%x\n",
211                         __func__, i, chip->int_reduce_control_reg[i]);
212         }
213         chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
214 }
215
216 /* pch_phub_restore_reg_conf - restore register configuration */
217 static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
218 {
219         unsigned int i;
220         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
221         void __iomem *p;
222         p = chip->pch_phub_base_address;
223
224         iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
225         iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
226         iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
227         iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
228         iowrite32(chip->comp_resp_timeout_reg,
229                                         p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
230         iowrite32(chip->bus_slave_control_reg,
231                                         p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
232         iowrite32(chip->deadlock_avoid_type_reg,
233                                         p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
234         iowrite32(chip->intpin_reg_wpermit_reg0,
235                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
236         iowrite32(chip->intpin_reg_wpermit_reg1,
237                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
238         iowrite32(chip->intpin_reg_wpermit_reg2,
239                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
240         iowrite32(chip->intpin_reg_wpermit_reg3,
241                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
242         dev_dbg(&pdev->dev, "%s : "
243                 "chip->phub_id_reg=%x, "
244                 "chip->q_pri_val_reg=%x, "
245                 "chip->rc_q_maxsize_reg=%x, "
246                 "chip->bri_q_maxsize_reg=%x, "
247                 "chip->comp_resp_timeout_reg=%x, "
248                 "chip->bus_slave_control_reg=%x, "
249                 "chip->deadlock_avoid_type_reg=%x, "
250                 "chip->intpin_reg_wpermit_reg0=%x, "
251                 "chip->intpin_reg_wpermit_reg1=%x, "
252                 "chip->intpin_reg_wpermit_reg2=%x, "
253                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
254                 chip->phub_id_reg,
255                 chip->q_pri_val_reg,
256                 chip->rc_q_maxsize_reg,
257                 chip->bri_q_maxsize_reg,
258                 chip->comp_resp_timeout_reg,
259                 chip->bus_slave_control_reg,
260                 chip->deadlock_avoid_type_reg,
261                 chip->intpin_reg_wpermit_reg0,
262                 chip->intpin_reg_wpermit_reg1,
263                 chip->intpin_reg_wpermit_reg2,
264                 chip->intpin_reg_wpermit_reg3);
265         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
266                 iowrite32(chip->int_reduce_control_reg[i],
267                         p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
268                 dev_dbg(&pdev->dev, "%s : "
269                         "chip->int_reduce_control_reg[%d]=%x\n",
270                         __func__, i, chip->int_reduce_control_reg[i]);
271         }
272
273         iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
274 }
275
276 /**
277  * pch_phub_read_serial_rom() - Reading Serial ROM
278  * @offset_address:     Serial ROM offset address to read.
279  * @data:               Read buffer for specified Serial ROM value.
280  */
281 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
282                                      unsigned int offset_address, u8 *data)
283 {
284         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
285                                                                 offset_address;
286
287         *data = ioread8(mem_addr);
288 }
289
290 /**
291  * pch_phub_write_serial_rom() - Writing Serial ROM
292  * @offset_address:     Serial ROM offset address.
293  * @data:               Serial ROM value to write.
294  */
295 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
296                                      unsigned int offset_address, u8 data)
297 {
298         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
299                                         (offset_address & PCH_WORD_ADDR_MASK);
300         int i;
301         unsigned int word_data;
302         unsigned int pos;
303         unsigned int mask;
304         pos = (offset_address % 4) * 8;
305         mask = ~(0xFF << pos);
306
307         iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
308                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
309
310         word_data = ioread32(mem_addr);
311         iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
312
313         i = 0;
314         while (ioread8(chip->pch_phub_extrom_base_address +
315                                                 PHUB_STATUS) != 0x00) {
316                 msleep(1);
317                 if (i == PHUB_TIMEOUT)
318                         return -ETIMEDOUT;
319                 i++;
320         }
321
322         iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
323                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
324
325         return 0;
326 }
327
328 /**
329  * pch_phub_read_serial_rom_val() - Read Serial ROM value
330  * @offset_address:     Serial ROM address offset value.
331  * @data:               Serial ROM value to read.
332  */
333 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
334                                          unsigned int offset_address, u8 *data)
335 {
336         unsigned int mem_addr;
337
338         mem_addr = chip->pch_mac_start_address +
339                         pch_phub_mac_offset[offset_address];
340
341         pch_phub_read_serial_rom(chip, mem_addr, data);
342 }
343
344 /**
345  * pch_phub_write_serial_rom_val() - writing Serial ROM value
346  * @offset_address:     Serial ROM address offset value.
347  * @data:               Serial ROM value.
348  */
349 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
350                                          unsigned int offset_address, u8 data)
351 {
352         int retval;
353         unsigned int mem_addr;
354
355         mem_addr = chip->pch_mac_start_address +
356                         pch_phub_mac_offset[offset_address];
357
358         retval = pch_phub_write_serial_rom(chip, mem_addr, data);
359
360         return retval;
361 }
362
363 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
364  * for Gigabit Ethernet MAC address
365  */
366 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
367 {
368         int retval;
369
370         retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
371         retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
372         retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
373         retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
374
375         retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
376         retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
377         retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
378         retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
379
380         retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
381         retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
382         retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
383         retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
384
385         retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
386         retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
387         retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
388         retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
389
390         retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
391         retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
392         retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
393         retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
394
395         retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
396         retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
397         retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
398         retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
399
400         return retval;
401 }
402
403 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
404  * for Gigabit Ethernet MAC address
405  */
406 static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
407 {
408         int retval;
409         u32 offset_addr;
410
411         offset_addr = 0x200;
412         retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
413         retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
414         retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
415         retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
416
417         retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
418         retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
419         retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
420         retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
421
422         retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
423         retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
424         retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
425         retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
426
427         retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
428         retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
429         retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
430         retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
431
432         retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
433         retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
434         retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
435         retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
436
437         retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
438         retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
439         retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
440         retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
441
442         return retval;
443 }
444
445 /**
446  * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
447  * @offset_address:     Gigabit Ethernet MAC address offset value.
448  * @data:               Buffer of the Gigabit Ethernet MAC address value.
449  */
450 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
451 {
452         int i;
453         for (i = 0; i < ETH_ALEN; i++)
454                 pch_phub_read_serial_rom_val(chip, i, &data[i]);
455 }
456
457 /**
458  * pch_phub_write_gbe_mac_addr() - Write MAC address
459  * @offset_address:     Gigabit Ethernet MAC address offset value.
460  * @data:               Gigabit Ethernet MAC address value.
461  */
462 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
463 {
464         int retval;
465         int i;
466
467         if (chip->ioh_type == 1) /* EG20T */
468                 retval = pch_phub_gbe_serial_rom_conf(chip);
469         else    /* ML7223 */
470                 retval = pch_phub_gbe_serial_rom_conf_mp(chip);
471         if (retval)
472                 return retval;
473
474         for (i = 0; i < ETH_ALEN; i++) {
475                 retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
476                 if (retval)
477                         return retval;
478         }
479
480         return retval;
481 }
482
483 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
484                                  struct bin_attribute *attr, char *buf,
485                                  loff_t off, size_t count)
486 {
487         unsigned int rom_signature;
488         unsigned char rom_length;
489         unsigned int tmp;
490         unsigned int addr_offset;
491         unsigned int orom_size;
492         int ret;
493         int err;
494
495         struct pch_phub_reg *chip =
496                 dev_get_drvdata(container_of(kobj, struct device, kobj));
497
498         ret = mutex_lock_interruptible(&pch_phub_mutex);
499         if (ret) {
500                 err = -ERESTARTSYS;
501                 goto return_err_nomutex;
502         }
503
504         /* Get Rom signature */
505         pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
506                                 (unsigned char *)&rom_signature);
507         rom_signature &= 0xff;
508         pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
509                                 (unsigned char *)&tmp);
510         rom_signature |= (tmp & 0xff) << 8;
511         if (rom_signature == 0xAA55) {
512                 pch_phub_read_serial_rom(chip,
513                                          chip->pch_opt_rom_start_address + 2,
514                                          &rom_length);
515                 orom_size = rom_length * 512;
516                 if (orom_size < off) {
517                         addr_offset = 0;
518                         goto return_ok;
519                 }
520                 if (orom_size < count) {
521                         addr_offset = 0;
522                         goto return_ok;
523                 }
524
525                 for (addr_offset = 0; addr_offset < count; addr_offset++) {
526                         pch_phub_read_serial_rom(chip,
527                             chip->pch_opt_rom_start_address + addr_offset + off,
528                             &buf[addr_offset]);
529                 }
530         } else {
531                 err = -ENODATA;
532                 goto return_err;
533         }
534 return_ok:
535         mutex_unlock(&pch_phub_mutex);
536         return addr_offset;
537
538 return_err:
539         mutex_unlock(&pch_phub_mutex);
540 return_err_nomutex:
541         return err;
542 }
543
544 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
545                                   struct bin_attribute *attr,
546                                   char *buf, loff_t off, size_t count)
547 {
548         int err;
549         unsigned int addr_offset;
550         int ret;
551         struct pch_phub_reg *chip =
552                 dev_get_drvdata(container_of(kobj, struct device, kobj));
553
554         ret = mutex_lock_interruptible(&pch_phub_mutex);
555         if (ret)
556                 return -ERESTARTSYS;
557
558         if (off > PCH_PHUB_OROM_SIZE) {
559                 addr_offset = 0;
560                 goto return_ok;
561         }
562         if (count > PCH_PHUB_OROM_SIZE) {
563                 addr_offset = 0;
564                 goto return_ok;
565         }
566
567         for (addr_offset = 0; addr_offset < count; addr_offset++) {
568                 if (PCH_PHUB_OROM_SIZE < off + addr_offset)
569                         goto return_ok;
570
571                 ret = pch_phub_write_serial_rom(chip,
572                             chip->pch_opt_rom_start_address + addr_offset + off,
573                             buf[addr_offset]);
574                 if (ret) {
575                         err = ret;
576                         goto return_err;
577                 }
578         }
579
580 return_ok:
581         mutex_unlock(&pch_phub_mutex);
582         return addr_offset;
583
584 return_err:
585         mutex_unlock(&pch_phub_mutex);
586         return err;
587 }
588
589 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
590                             char *buf)
591 {
592         u8 mac[8];
593         struct pch_phub_reg *chip = dev_get_drvdata(dev);
594
595         pch_phub_read_gbe_mac_addr(chip, mac);
596
597         return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n",
598                                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
599 }
600
601 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
602                              const char *buf, size_t count)
603 {
604         u8 mac[6];
605         struct pch_phub_reg *chip = dev_get_drvdata(dev);
606
607         if (count != 18)
608                 return -EINVAL;
609
610         sscanf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
611                 (u32 *)&mac[0], (u32 *)&mac[1], (u32 *)&mac[2], (u32 *)&mac[3],
612                 (u32 *)&mac[4], (u32 *)&mac[5]);
613
614         pch_phub_write_gbe_mac_addr(chip, mac);
615
616         return count;
617 }
618
619 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
620
621 static struct bin_attribute pch_bin_attr = {
622         .attr = {
623                 .name = "pch_firmware",
624                 .mode = S_IRUGO | S_IWUSR,
625         },
626         .size = PCH_PHUB_OROM_SIZE + 1,
627         .read = pch_phub_bin_read,
628         .write = pch_phub_bin_write,
629 };
630
631 static int __devinit pch_phub_probe(struct pci_dev *pdev,
632                                     const struct pci_device_id *id)
633 {
634         int retval;
635
636         int ret;
637         ssize_t rom_size;
638         struct pch_phub_reg *chip;
639
640         chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
641         if (chip == NULL)
642                 return -ENOMEM;
643
644         ret = pci_enable_device(pdev);
645         if (ret) {
646                 dev_err(&pdev->dev,
647                 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
648                 goto err_pci_enable_dev;
649         }
650         dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
651                 ret);
652
653         ret = pci_request_regions(pdev, KBUILD_MODNAME);
654         if (ret) {
655                 dev_err(&pdev->dev,
656                 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
657                 goto err_req_regions;
658         }
659         dev_dbg(&pdev->dev, "%s : "
660                 "pci_request_regions returns %d\n", __func__, ret);
661
662         chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
663
664
665         if (chip->pch_phub_base_address == 0) {
666                 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
667                 ret = -ENOMEM;
668                 goto err_pci_iomap;
669         }
670         dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
671                 "in pch_phub_base_address variable is %p\n", __func__,
672                 chip->pch_phub_base_address);
673
674         if (id->driver_data != 3) {
675                 chip->pch_phub_extrom_base_address =\
676                                                    pci_map_rom(pdev, &rom_size);
677                 if (chip->pch_phub_extrom_base_address == 0) {
678                         dev_err(&pdev->dev, "%s: pci_map_rom FAILED", __func__);
679                         ret = -ENOMEM;
680                         goto err_pci_map;
681                 }
682                 dev_dbg(&pdev->dev, "%s : "
683                         "pci_map_rom SUCCESS and value in "
684                         "pch_phub_extrom_base_address variable is %p\n",
685                         __func__, chip->pch_phub_extrom_base_address);
686         }
687
688         if (id->driver_data == 1) { /* EG20T PCH */
689                 retval = sysfs_create_file(&pdev->dev.kobj,
690                                            &dev_attr_pch_mac.attr);
691                 if (retval)
692                         goto err_sysfs_create;
693
694                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
695                 if (retval)
696                         goto exit_bin_attr;
697
698                 pch_phub_read_modify_write_reg(chip,
699                                                (unsigned int)CLKCFG_REG_OFFSET,
700                                                CLKCFG_CAN_50MHZ,
701                                                CLKCFG_CANCLK_MASK);
702
703                 /* quirk for CM-iTC board */
704                 if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
705                         pch_phub_read_modify_write_reg(chip,
706                                                 (unsigned int)CLKCFG_REG_OFFSET,
707                                                 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
708                                                 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
709                                                 CLKCFG_UART_MASK);
710
711                 /* set the prefech value */
712                 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
713                 /* set the interrupt delay value */
714                 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
715                 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
716                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
717         } else if (id->driver_data == 2) { /* ML7213 IOH */
718                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
719                 if (retval)
720                         goto err_sysfs_create;
721                 /* set the prefech value
722                  * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
723                  * Device4(SDIO #0,1,2):f
724                  * Device6(SATA 2):f
725                  * Device8(USB OHCI #0/ USB EHCI #0):a
726                  */
727                 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
728                 chip->pch_opt_rom_start_address =\
729                                                  PCH_PHUB_ROM_START_ADDR_ML7213;
730         } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
731                 /* set the prefech value
732                  * Device8(GbE)
733                  */
734                 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
735                 /* set the interrupt delay value */
736                 iowrite32(0x25, chip->pch_phub_base_address + 0x140);
737                 chip->pch_opt_rom_start_address =\
738                                                  PCH_PHUB_ROM_START_ADDR_ML7223;
739                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
740         } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
741                 retval = sysfs_create_file(&pdev->dev.kobj,
742                                            &dev_attr_pch_mac.attr);
743                 if (retval)
744                         goto err_sysfs_create;
745                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
746                 if (retval)
747                         goto exit_bin_attr;
748                 /* set the prefech value
749                  * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
750                  * Device4(SDIO #0,1):f
751                  * Device6(SATA 2):f
752                  */
753                 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
754                 chip->pch_opt_rom_start_address =\
755                                                  PCH_PHUB_ROM_START_ADDR_ML7223;
756                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
757         }
758
759         chip->ioh_type = id->driver_data;
760         pci_set_drvdata(pdev, chip);
761
762         return 0;
763 exit_bin_attr:
764         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
765
766 err_sysfs_create:
767         pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address);
768 err_pci_map:
769         pci_iounmap(pdev, chip->pch_phub_base_address);
770 err_pci_iomap:
771         pci_release_regions(pdev);
772 err_req_regions:
773         pci_disable_device(pdev);
774 err_pci_enable_dev:
775         kfree(chip);
776         dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
777         return ret;
778 }
779
780 static void __devexit pch_phub_remove(struct pci_dev *pdev)
781 {
782         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
783
784         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
785         sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
786         pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address);
787         pci_iounmap(pdev, chip->pch_phub_base_address);
788         pci_release_regions(pdev);
789         pci_disable_device(pdev);
790         kfree(chip);
791 }
792
793 #ifdef CONFIG_PM
794
795 static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state)
796 {
797         int ret;
798
799         pch_phub_save_reg_conf(pdev);
800         ret = pci_save_state(pdev);
801         if (ret) {
802                 dev_err(&pdev->dev,
803                         " %s -pci_save_state returns %d\n", __func__, ret);
804                 return ret;
805         }
806         pci_enable_wake(pdev, PCI_D3hot, 0);
807         pci_disable_device(pdev);
808         pci_set_power_state(pdev, pci_choose_state(pdev, state));
809
810         return 0;
811 }
812
813 static int pch_phub_resume(struct pci_dev *pdev)
814 {
815         int ret;
816
817         pci_set_power_state(pdev, PCI_D0);
818         pci_restore_state(pdev);
819         ret = pci_enable_device(pdev);
820         if (ret) {
821                 dev_err(&pdev->dev,
822                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
823                 return ret;
824         }
825
826         pci_enable_wake(pdev, PCI_D3hot, 0);
827         pch_phub_restore_reg_conf(pdev);
828
829         return 0;
830 }
831 #else
832 #define pch_phub_suspend NULL
833 #define pch_phub_resume NULL
834 #endif /* CONFIG_PM */
835
836 static struct pci_device_id pch_phub_pcidev_id[] = {
837         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB),       1,  },
838         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2,  },
839         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3,  },
840         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4,  },
841         { }
842 };
843 MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
844
845 static struct pci_driver pch_phub_driver = {
846         .name = "pch_phub",
847         .id_table = pch_phub_pcidev_id,
848         .probe = pch_phub_probe,
849         .remove = __devexit_p(pch_phub_remove),
850         .suspend = pch_phub_suspend,
851         .resume = pch_phub_resume
852 };
853
854 static int __init pch_phub_pci_init(void)
855 {
856         return pci_register_driver(&pch_phub_driver);
857 }
858
859 static void __exit pch_phub_pci_exit(void)
860 {
861         pci_unregister_driver(&pch_phub_driver);
862 }
863
864 module_init(pch_phub_pci_init);
865 module_exit(pch_phub_pci_exit);
866
867 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR IOH(ML7213/ML7223) PHUB");
868 MODULE_LICENSE("GPL");