misc: nct1008: error handling change
[linux-2.6.git] / drivers / misc / pch_phub.c
1 /*
2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; version 2 of the License.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
16  */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/fs.h>
22 #include <linux/uaccess.h>
23 #include <linux/string.h>
24 #include <linux/pci.h>
25 #include <linux/io.h>
26 #include <linux/delay.h>
27 #include <linux/mutex.h>
28 #include <linux/if_ether.h>
29 #include <linux/ctype.h>
30 #include <linux/dmi.h>
31
32 #define PHUB_STATUS 0x00                /* Status Register offset */
33 #define PHUB_CONTROL 0x04               /* Control Register offset */
34 #define PHUB_TIMEOUT 0x05               /* Time out value for Status Register */
35 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01  /* Enabling for writing ROM */
36 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
37 #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14  /* MAC data area start address
38                                                offset */
39 #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C  /* MAC data area start address
40                                                  offset */
41 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
42                                               (Intel EG20T PCH)*/
43 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
44                                                 offset(OKI SEMICONDUCTOR ML7213)
45                                               */
46 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
47                                                 offset(OKI SEMICONDUCTOR ML7223)
48                                               */
49
50 /* MAX number of INT_REDUCE_CONTROL registers */
51 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128
52 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801
53 #define PCH_MINOR_NOS 1
54 #define CLKCFG_CAN_50MHZ 0x12000000
55 #define CLKCFG_CANCLK_MASK 0xFF000000
56 #define CLKCFG_UART_MASK                        0xFFFFFF
57
58 /* CM-iTC */
59 #define CLKCFG_UART_48MHZ                       (1 << 16)
60 #define CLKCFG_BAUDDIV                          (2 << 20)
61 #define CLKCFG_PLL2VCO                          (8 << 9)
62 #define CLKCFG_UARTCLKSEL                       (1 << 18)
63
64 /* Macros for ML7213 */
65 #define PCI_VENDOR_ID_ROHM                      0x10db
66 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
67
68 /* Macros for ML7213 */
69 #define PCI_VENDOR_ID_ROHM                      0x10db
70 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
71
72 /* Macros for ML7223 */
73 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
74 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
75
76 /* Macros for ML7831 */
77 #define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801
78
79 /* SROM ACCESS Macro */
80 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
81
82 /* Registers address offset */
83 #define PCH_PHUB_ID_REG                         0x0000
84 #define PCH_PHUB_QUEUE_PRI_VAL_REG              0x0004
85 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG           0x0008
86 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG          0x000C
87 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG          0x0010
88 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG          0x0014
89 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG        0x0018
90 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0        0x0020
91 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1        0x0024
92 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2        0x0028
93 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3        0x002C
94 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE    0x0040
95 #define CLKCFG_REG_OFFSET                       0x500
96
97 #define PCH_PHUB_OROM_SIZE 15360
98
99 /**
100  * struct pch_phub_reg - PHUB register structure
101  * @phub_id_reg:                        PHUB_ID register val
102  * @q_pri_val_reg:                      QUEUE_PRI_VAL register val
103  * @rc_q_maxsize_reg:                   RC_QUEUE_MAXSIZE register val
104  * @bri_q_maxsize_reg:                  BRI_QUEUE_MAXSIZE register val
105  * @comp_resp_timeout_reg:              COMP_RESP_TIMEOUT register val
106  * @bus_slave_control_reg:              BUS_SLAVE_CONTROL_REG register val
107  * @deadlock_avoid_type_reg:            DEADLOCK_AVOID_TYPE register val
108  * @intpin_reg_wpermit_reg0:            INTPIN_REG_WPERMIT register 0 val
109  * @intpin_reg_wpermit_reg1:            INTPIN_REG_WPERMIT register 1 val
110  * @intpin_reg_wpermit_reg2:            INTPIN_REG_WPERMIT register 2 val
111  * @intpin_reg_wpermit_reg3:            INTPIN_REG_WPERMIT register 3 val
112  * @int_reduce_control_reg:             INT_REDUCE_CONTROL registers val
113  * @clkcfg_reg:                         CLK CFG register val
114  * @pch_phub_base_address:              Register base address
115  * @pch_phub_extrom_base_address:       external rom base address
116  * @pch_mac_start_address:              MAC address area start address
117  * @pch_opt_rom_start_address:          Option ROM start address
118  * @ioh_type:                           Save IOH type
119  */
120 struct pch_phub_reg {
121         u32 phub_id_reg;
122         u32 q_pri_val_reg;
123         u32 rc_q_maxsize_reg;
124         u32 bri_q_maxsize_reg;
125         u32 comp_resp_timeout_reg;
126         u32 bus_slave_control_reg;
127         u32 deadlock_avoid_type_reg;
128         u32 intpin_reg_wpermit_reg0;
129         u32 intpin_reg_wpermit_reg1;
130         u32 intpin_reg_wpermit_reg2;
131         u32 intpin_reg_wpermit_reg3;
132         u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
133         u32 clkcfg_reg;
134         void __iomem *pch_phub_base_address;
135         void __iomem *pch_phub_extrom_base_address;
136         u32 pch_mac_start_address;
137         u32 pch_opt_rom_start_address;
138         int ioh_type;
139 };
140
141 /* SROM SPEC for MAC address assignment offset */
142 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
143
144 static DEFINE_MUTEX(pch_phub_mutex);
145
146 /**
147  * pch_phub_read_modify_write_reg() - Reading modifying and writing register
148  * @reg_addr_offset:    Register offset address value.
149  * @data:               Writing value.
150  * @mask:               Mask value.
151  */
152 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
153                                            unsigned int reg_addr_offset,
154                                            unsigned int data, unsigned int mask)
155 {
156         void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
157         iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
158 }
159
160 /* pch_phub_save_reg_conf - saves register configuration */
161 static void pch_phub_save_reg_conf(struct pci_dev *pdev)
162 {
163         unsigned int i;
164         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
165
166         void __iomem *p = chip->pch_phub_base_address;
167
168         chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
169         chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
170         chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
171         chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
172         chip->comp_resp_timeout_reg =
173                                 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
174         chip->bus_slave_control_reg =
175                                 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
176         chip->deadlock_avoid_type_reg =
177                                 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
178         chip->intpin_reg_wpermit_reg0 =
179                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
180         chip->intpin_reg_wpermit_reg1 =
181                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
182         chip->intpin_reg_wpermit_reg2 =
183                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
184         chip->intpin_reg_wpermit_reg3 =
185                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
186         dev_dbg(&pdev->dev, "%s : "
187                 "chip->phub_id_reg=%x, "
188                 "chip->q_pri_val_reg=%x, "
189                 "chip->rc_q_maxsize_reg=%x, "
190                 "chip->bri_q_maxsize_reg=%x, "
191                 "chip->comp_resp_timeout_reg=%x, "
192                 "chip->bus_slave_control_reg=%x, "
193                 "chip->deadlock_avoid_type_reg=%x, "
194                 "chip->intpin_reg_wpermit_reg0=%x, "
195                 "chip->intpin_reg_wpermit_reg1=%x, "
196                 "chip->intpin_reg_wpermit_reg2=%x, "
197                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
198                 chip->phub_id_reg,
199                 chip->q_pri_val_reg,
200                 chip->rc_q_maxsize_reg,
201                 chip->bri_q_maxsize_reg,
202                 chip->comp_resp_timeout_reg,
203                 chip->bus_slave_control_reg,
204                 chip->deadlock_avoid_type_reg,
205                 chip->intpin_reg_wpermit_reg0,
206                 chip->intpin_reg_wpermit_reg1,
207                 chip->intpin_reg_wpermit_reg2,
208                 chip->intpin_reg_wpermit_reg3);
209         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
210                 chip->int_reduce_control_reg[i] =
211                     ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
212                 dev_dbg(&pdev->dev, "%s : "
213                         "chip->int_reduce_control_reg[%d]=%x\n",
214                         __func__, i, chip->int_reduce_control_reg[i]);
215         }
216         chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
217 }
218
219 /* pch_phub_restore_reg_conf - restore register configuration */
220 static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
221 {
222         unsigned int i;
223         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
224         void __iomem *p;
225         p = chip->pch_phub_base_address;
226
227         iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
228         iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
229         iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
230         iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
231         iowrite32(chip->comp_resp_timeout_reg,
232                                         p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
233         iowrite32(chip->bus_slave_control_reg,
234                                         p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
235         iowrite32(chip->deadlock_avoid_type_reg,
236                                         p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
237         iowrite32(chip->intpin_reg_wpermit_reg0,
238                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
239         iowrite32(chip->intpin_reg_wpermit_reg1,
240                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
241         iowrite32(chip->intpin_reg_wpermit_reg2,
242                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
243         iowrite32(chip->intpin_reg_wpermit_reg3,
244                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
245         dev_dbg(&pdev->dev, "%s : "
246                 "chip->phub_id_reg=%x, "
247                 "chip->q_pri_val_reg=%x, "
248                 "chip->rc_q_maxsize_reg=%x, "
249                 "chip->bri_q_maxsize_reg=%x, "
250                 "chip->comp_resp_timeout_reg=%x, "
251                 "chip->bus_slave_control_reg=%x, "
252                 "chip->deadlock_avoid_type_reg=%x, "
253                 "chip->intpin_reg_wpermit_reg0=%x, "
254                 "chip->intpin_reg_wpermit_reg1=%x, "
255                 "chip->intpin_reg_wpermit_reg2=%x, "
256                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
257                 chip->phub_id_reg,
258                 chip->q_pri_val_reg,
259                 chip->rc_q_maxsize_reg,
260                 chip->bri_q_maxsize_reg,
261                 chip->comp_resp_timeout_reg,
262                 chip->bus_slave_control_reg,
263                 chip->deadlock_avoid_type_reg,
264                 chip->intpin_reg_wpermit_reg0,
265                 chip->intpin_reg_wpermit_reg1,
266                 chip->intpin_reg_wpermit_reg2,
267                 chip->intpin_reg_wpermit_reg3);
268         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
269                 iowrite32(chip->int_reduce_control_reg[i],
270                         p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
271                 dev_dbg(&pdev->dev, "%s : "
272                         "chip->int_reduce_control_reg[%d]=%x\n",
273                         __func__, i, chip->int_reduce_control_reg[i]);
274         }
275
276         iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
277 }
278
279 /**
280  * pch_phub_read_serial_rom() - Reading Serial ROM
281  * @offset_address:     Serial ROM offset address to read.
282  * @data:               Read buffer for specified Serial ROM value.
283  */
284 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
285                                      unsigned int offset_address, u8 *data)
286 {
287         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
288                                                                 offset_address;
289
290         *data = ioread8(mem_addr);
291 }
292
293 /**
294  * pch_phub_write_serial_rom() - Writing Serial ROM
295  * @offset_address:     Serial ROM offset address.
296  * @data:               Serial ROM value to write.
297  */
298 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
299                                      unsigned int offset_address, u8 data)
300 {
301         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
302                                         (offset_address & PCH_WORD_ADDR_MASK);
303         int i;
304         unsigned int word_data;
305         unsigned int pos;
306         unsigned int mask;
307         pos = (offset_address % 4) * 8;
308         mask = ~(0xFF << pos);
309
310         iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
311                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
312
313         word_data = ioread32(mem_addr);
314         iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
315
316         i = 0;
317         while (ioread8(chip->pch_phub_extrom_base_address +
318                                                 PHUB_STATUS) != 0x00) {
319                 msleep(1);
320                 if (i == PHUB_TIMEOUT)
321                         return -ETIMEDOUT;
322                 i++;
323         }
324
325         iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
326                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
327
328         return 0;
329 }
330
331 /**
332  * pch_phub_read_serial_rom_val() - Read Serial ROM value
333  * @offset_address:     Serial ROM address offset value.
334  * @data:               Serial ROM value to read.
335  */
336 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
337                                          unsigned int offset_address, u8 *data)
338 {
339         unsigned int mem_addr;
340
341         mem_addr = chip->pch_mac_start_address +
342                         pch_phub_mac_offset[offset_address];
343
344         pch_phub_read_serial_rom(chip, mem_addr, data);
345 }
346
347 /**
348  * pch_phub_write_serial_rom_val() - writing Serial ROM value
349  * @offset_address:     Serial ROM address offset value.
350  * @data:               Serial ROM value.
351  */
352 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
353                                          unsigned int offset_address, u8 data)
354 {
355         int retval;
356         unsigned int mem_addr;
357
358         mem_addr = chip->pch_mac_start_address +
359                         pch_phub_mac_offset[offset_address];
360
361         retval = pch_phub_write_serial_rom(chip, mem_addr, data);
362
363         return retval;
364 }
365
366 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
367  * for Gigabit Ethernet MAC address
368  */
369 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
370 {
371         int retval;
372
373         retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
374         retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
375         retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
376         retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
377
378         retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
379         retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
380         retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
381         retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
382
383         retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
384         retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
385         retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
386         retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
387
388         retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
389         retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
390         retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
391         retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
392
393         retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
394         retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
395         retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
396         retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
397
398         retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
399         retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
400         retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
401         retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
402
403         return retval;
404 }
405
406 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
407  * for Gigabit Ethernet MAC address
408  */
409 static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
410 {
411         int retval;
412         u32 offset_addr;
413
414         offset_addr = 0x200;
415         retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
416         retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
417         retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
418         retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
419
420         retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
421         retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
422         retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
423         retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
424
425         retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
426         retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
427         retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
428         retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
429
430         retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
431         retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
432         retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
433         retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
434
435         retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
436         retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
437         retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
438         retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
439
440         retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
441         retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
442         retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
443         retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
444
445         return retval;
446 }
447
448 /**
449  * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
450  * @offset_address:     Gigabit Ethernet MAC address offset value.
451  * @data:               Buffer of the Gigabit Ethernet MAC address value.
452  */
453 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
454 {
455         int i;
456         for (i = 0; i < ETH_ALEN; i++)
457                 pch_phub_read_serial_rom_val(chip, i, &data[i]);
458 }
459
460 /**
461  * pch_phub_write_gbe_mac_addr() - Write MAC address
462  * @offset_address:     Gigabit Ethernet MAC address offset value.
463  * @data:               Gigabit Ethernet MAC address value.
464  */
465 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
466 {
467         int retval;
468         int i;
469
470         if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
471                 retval = pch_phub_gbe_serial_rom_conf(chip);
472         else    /* ML7223 */
473                 retval = pch_phub_gbe_serial_rom_conf_mp(chip);
474         if (retval)
475                 return retval;
476
477         for (i = 0; i < ETH_ALEN; i++) {
478                 retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
479                 if (retval)
480                         return retval;
481         }
482
483         return retval;
484 }
485
486 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
487                                  struct bin_attribute *attr, char *buf,
488                                  loff_t off, size_t count)
489 {
490         unsigned int rom_signature;
491         unsigned char rom_length;
492         unsigned int tmp;
493         unsigned int addr_offset;
494         unsigned int orom_size;
495         int ret;
496         int err;
497
498         struct pch_phub_reg *chip =
499                 dev_get_drvdata(container_of(kobj, struct device, kobj));
500
501         ret = mutex_lock_interruptible(&pch_phub_mutex);
502         if (ret) {
503                 err = -ERESTARTSYS;
504                 goto return_err_nomutex;
505         }
506
507         /* Get Rom signature */
508         pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
509                                 (unsigned char *)&rom_signature);
510         rom_signature &= 0xff;
511         pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
512                                 (unsigned char *)&tmp);
513         rom_signature |= (tmp & 0xff) << 8;
514         if (rom_signature == 0xAA55) {
515                 pch_phub_read_serial_rom(chip,
516                                          chip->pch_opt_rom_start_address + 2,
517                                          &rom_length);
518                 orom_size = rom_length * 512;
519                 if (orom_size < off) {
520                         addr_offset = 0;
521                         goto return_ok;
522                 }
523                 if (orom_size < count) {
524                         addr_offset = 0;
525                         goto return_ok;
526                 }
527
528                 for (addr_offset = 0; addr_offset < count; addr_offset++) {
529                         pch_phub_read_serial_rom(chip,
530                             chip->pch_opt_rom_start_address + addr_offset + off,
531                             &buf[addr_offset]);
532                 }
533         } else {
534                 err = -ENODATA;
535                 goto return_err;
536         }
537 return_ok:
538         mutex_unlock(&pch_phub_mutex);
539         return addr_offset;
540
541 return_err:
542         mutex_unlock(&pch_phub_mutex);
543 return_err_nomutex:
544         return err;
545 }
546
547 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
548                                   struct bin_attribute *attr,
549                                   char *buf, loff_t off, size_t count)
550 {
551         int err;
552         unsigned int addr_offset;
553         int ret;
554         struct pch_phub_reg *chip =
555                 dev_get_drvdata(container_of(kobj, struct device, kobj));
556
557         ret = mutex_lock_interruptible(&pch_phub_mutex);
558         if (ret)
559                 return -ERESTARTSYS;
560
561         if (off > PCH_PHUB_OROM_SIZE) {
562                 addr_offset = 0;
563                 goto return_ok;
564         }
565         if (count > PCH_PHUB_OROM_SIZE) {
566                 addr_offset = 0;
567                 goto return_ok;
568         }
569
570         for (addr_offset = 0; addr_offset < count; addr_offset++) {
571                 if (PCH_PHUB_OROM_SIZE < off + addr_offset)
572                         goto return_ok;
573
574                 ret = pch_phub_write_serial_rom(chip,
575                             chip->pch_opt_rom_start_address + addr_offset + off,
576                             buf[addr_offset]);
577                 if (ret) {
578                         err = ret;
579                         goto return_err;
580                 }
581         }
582
583 return_ok:
584         mutex_unlock(&pch_phub_mutex);
585         return addr_offset;
586
587 return_err:
588         mutex_unlock(&pch_phub_mutex);
589         return err;
590 }
591
592 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
593                             char *buf)
594 {
595         u8 mac[8];
596         struct pch_phub_reg *chip = dev_get_drvdata(dev);
597
598         pch_phub_read_gbe_mac_addr(chip, mac);
599
600         return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n",
601                                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
602 }
603
604 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
605                              const char *buf, size_t count)
606 {
607         u8 mac[6];
608         struct pch_phub_reg *chip = dev_get_drvdata(dev);
609
610         if (count != 18)
611                 return -EINVAL;
612
613         sscanf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
614                 (u32 *)&mac[0], (u32 *)&mac[1], (u32 *)&mac[2], (u32 *)&mac[3],
615                 (u32 *)&mac[4], (u32 *)&mac[5]);
616
617         pch_phub_write_gbe_mac_addr(chip, mac);
618
619         return count;
620 }
621
622 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
623
624 static struct bin_attribute pch_bin_attr = {
625         .attr = {
626                 .name = "pch_firmware",
627                 .mode = S_IRUGO | S_IWUSR,
628         },
629         .size = PCH_PHUB_OROM_SIZE + 1,
630         .read = pch_phub_bin_read,
631         .write = pch_phub_bin_write,
632 };
633
634 static int __devinit pch_phub_probe(struct pci_dev *pdev,
635                                     const struct pci_device_id *id)
636 {
637         int retval;
638
639         int ret;
640         ssize_t rom_size;
641         struct pch_phub_reg *chip;
642
643         chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
644         if (chip == NULL)
645                 return -ENOMEM;
646
647         ret = pci_enable_device(pdev);
648         if (ret) {
649                 dev_err(&pdev->dev,
650                 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
651                 goto err_pci_enable_dev;
652         }
653         dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
654                 ret);
655
656         ret = pci_request_regions(pdev, KBUILD_MODNAME);
657         if (ret) {
658                 dev_err(&pdev->dev,
659                 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
660                 goto err_req_regions;
661         }
662         dev_dbg(&pdev->dev, "%s : "
663                 "pci_request_regions returns %d\n", __func__, ret);
664
665         chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
666
667
668         if (chip->pch_phub_base_address == 0) {
669                 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
670                 ret = -ENOMEM;
671                 goto err_pci_iomap;
672         }
673         dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
674                 "in pch_phub_base_address variable is %p\n", __func__,
675                 chip->pch_phub_base_address);
676
677         if (id->driver_data != 3) {
678                 chip->pch_phub_extrom_base_address =\
679                                                    pci_map_rom(pdev, &rom_size);
680                 if (chip->pch_phub_extrom_base_address == 0) {
681                         dev_err(&pdev->dev, "%s: pci_map_rom FAILED", __func__);
682                         ret = -ENOMEM;
683                         goto err_pci_map;
684                 }
685                 dev_dbg(&pdev->dev, "%s : "
686                         "pci_map_rom SUCCESS and value in "
687                         "pch_phub_extrom_base_address variable is %p\n",
688                         __func__, chip->pch_phub_extrom_base_address);
689         }
690
691         if (id->driver_data == 1) { /* EG20T PCH */
692                 const char *board_name;
693
694                 retval = sysfs_create_file(&pdev->dev.kobj,
695                                            &dev_attr_pch_mac.attr);
696                 if (retval)
697                         goto err_sysfs_create;
698
699                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
700                 if (retval)
701                         goto exit_bin_attr;
702
703                 pch_phub_read_modify_write_reg(chip,
704                                                (unsigned int)CLKCFG_REG_OFFSET,
705                                                CLKCFG_CAN_50MHZ,
706                                                CLKCFG_CANCLK_MASK);
707
708                 /* quirk for CM-iTC board */
709                 board_name = dmi_get_system_info(DMI_BOARD_NAME);
710                 if (board_name && strstr(board_name, "CM-iTC"))
711                         pch_phub_read_modify_write_reg(chip,
712                                                 (unsigned int)CLKCFG_REG_OFFSET,
713                                                 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
714                                                 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
715                                                 CLKCFG_UART_MASK);
716
717                 /* set the prefech value */
718                 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
719                 /* set the interrupt delay value */
720                 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
721                 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
722                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
723         } else if (id->driver_data == 2) { /* ML7213 IOH */
724                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
725                 if (retval)
726                         goto err_sysfs_create;
727                 /* set the prefech value
728                  * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
729                  * Device4(SDIO #0,1,2):f
730                  * Device6(SATA 2):f
731                  * Device8(USB OHCI #0/ USB EHCI #0):a
732                  */
733                 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
734                 chip->pch_opt_rom_start_address =\
735                                                  PCH_PHUB_ROM_START_ADDR_ML7213;
736         } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
737                 /* set the prefech value
738                  * Device8(GbE)
739                  */
740                 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
741                 /* set the interrupt delay value */
742                 iowrite32(0x25, chip->pch_phub_base_address + 0x140);
743                 chip->pch_opt_rom_start_address =\
744                                                  PCH_PHUB_ROM_START_ADDR_ML7223;
745                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
746         } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
747                 retval = sysfs_create_file(&pdev->dev.kobj,
748                                            &dev_attr_pch_mac.attr);
749                 if (retval)
750                         goto err_sysfs_create;
751                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
752                 if (retval)
753                         goto exit_bin_attr;
754                 /* set the prefech value
755                  * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
756                  * Device4(SDIO #0,1):f
757                  * Device6(SATA 2):f
758                  */
759                 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
760                 chip->pch_opt_rom_start_address =\
761                                                  PCH_PHUB_ROM_START_ADDR_ML7223;
762                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
763         } else if (id->driver_data == 5) { /* ML7831 */
764                 retval = sysfs_create_file(&pdev->dev.kobj,
765                                            &dev_attr_pch_mac.attr);
766                 if (retval)
767                         goto err_sysfs_create;
768
769                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
770                 if (retval)
771                         goto exit_bin_attr;
772
773                 /* set the prefech value */
774                 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
775                 /* set the interrupt delay value */
776                 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
777                 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
778                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
779         }
780
781         chip->ioh_type = id->driver_data;
782         pci_set_drvdata(pdev, chip);
783
784         return 0;
785 exit_bin_attr:
786         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
787
788 err_sysfs_create:
789         pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address);
790 err_pci_map:
791         pci_iounmap(pdev, chip->pch_phub_base_address);
792 err_pci_iomap:
793         pci_release_regions(pdev);
794 err_req_regions:
795         pci_disable_device(pdev);
796 err_pci_enable_dev:
797         kfree(chip);
798         dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
799         return ret;
800 }
801
802 static void __devexit pch_phub_remove(struct pci_dev *pdev)
803 {
804         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
805
806         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
807         sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
808         pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address);
809         pci_iounmap(pdev, chip->pch_phub_base_address);
810         pci_release_regions(pdev);
811         pci_disable_device(pdev);
812         kfree(chip);
813 }
814
815 #ifdef CONFIG_PM
816
817 static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state)
818 {
819         int ret;
820
821         pch_phub_save_reg_conf(pdev);
822         ret = pci_save_state(pdev);
823         if (ret) {
824                 dev_err(&pdev->dev,
825                         " %s -pci_save_state returns %d\n", __func__, ret);
826                 return ret;
827         }
828         pci_enable_wake(pdev, PCI_D3hot, 0);
829         pci_disable_device(pdev);
830         pci_set_power_state(pdev, pci_choose_state(pdev, state));
831
832         return 0;
833 }
834
835 static int pch_phub_resume(struct pci_dev *pdev)
836 {
837         int ret;
838
839         pci_set_power_state(pdev, PCI_D0);
840         pci_restore_state(pdev);
841         ret = pci_enable_device(pdev);
842         if (ret) {
843                 dev_err(&pdev->dev,
844                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
845                 return ret;
846         }
847
848         pci_enable_wake(pdev, PCI_D3hot, 0);
849         pch_phub_restore_reg_conf(pdev);
850
851         return 0;
852 }
853 #else
854 #define pch_phub_suspend NULL
855 #define pch_phub_resume NULL
856 #endif /* CONFIG_PM */
857
858 static struct pci_device_id pch_phub_pcidev_id[] = {
859         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB),       1,  },
860         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2,  },
861         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3,  },
862         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4,  },
863         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5,  },
864         { }
865 };
866 MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
867
868 static struct pci_driver pch_phub_driver = {
869         .name = "pch_phub",
870         .id_table = pch_phub_pcidev_id,
871         .probe = pch_phub_probe,
872         .remove = __devexit_p(pch_phub_remove),
873         .suspend = pch_phub_suspend,
874         .resume = pch_phub_resume
875 };
876
877 static int __init pch_phub_pci_init(void)
878 {
879         return pci_register_driver(&pch_phub_driver);
880 }
881
882 static void __exit pch_phub_pci_exit(void)
883 {
884         pci_unregister_driver(&pch_phub_driver);
885 }
886
887 module_init(pch_phub_pci_init);
888 module_exit(pch_phub_pci_exit);
889
890 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR IOH(ML7213/ML7223) PHUB");
891 MODULE_LICENSE("GPL");