pch_uart: reference clock on CM-iTC
[linux-2.6.git] / drivers / misc / pch_phub.c
1 /*
2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; version 2 of the License.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
16  */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/fs.h>
22 #include <linux/uaccess.h>
23 #include <linux/string.h>
24 #include <linux/pci.h>
25 #include <linux/io.h>
26 #include <linux/delay.h>
27 #include <linux/mutex.h>
28 #include <linux/if_ether.h>
29 #include <linux/ctype.h>
30 #include <linux/dmi.h>
31
32 #define PHUB_STATUS 0x00                /* Status Register offset */
33 #define PHUB_CONTROL 0x04               /* Control Register offset */
34 #define PHUB_TIMEOUT 0x05               /* Time out value for Status Register */
35 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01  /* Enabling for writing ROM */
36 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
37 #define PCH_PHUB_MAC_START_ADDR 0x20C  /* MAC data area start address offset */
38 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x14 /* ROM data area start address offset
39                                               (Intel EG20T PCH)*/
40 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
41                                                 offset(OKI SEMICONDUCTOR ML7213)
42                                               */
43
44 /* MAX number of INT_REDUCE_CONTROL registers */
45 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128
46 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801
47 #define PCH_MINOR_NOS 1
48 #define CLKCFG_CAN_50MHZ 0x12000000
49 #define CLKCFG_CANCLK_MASK 0xFF000000
50 #define CLKCFG_UART_MASK                        0xFFFFFF
51
52 /* CM-iTC */
53 #define CLKCFG_UART_48MHZ                       (1 << 16)
54 #define CLKCFG_BAUDDIV                          (2 << 20)
55 #define CLKCFG_PLL2VCO                          (8 << 9)
56 #define CLKCFG_UARTCLKSEL                       (1 << 18)
57
58 /* Macros for ML7213 */
59 #define PCI_VENDOR_ID_ROHM                      0x10db
60 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
61
62 /* SROM ACCESS Macro */
63 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
64
65 /* Registers address offset */
66 #define PCH_PHUB_ID_REG                         0x0000
67 #define PCH_PHUB_QUEUE_PRI_VAL_REG              0x0004
68 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG           0x0008
69 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG          0x000C
70 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG          0x0010
71 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG          0x0014
72 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG        0x0018
73 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0        0x0020
74 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1        0x0024
75 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2        0x0028
76 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3        0x002C
77 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE    0x0040
78 #define CLKCFG_REG_OFFSET                       0x500
79
80 #define PCH_PHUB_OROM_SIZE 15360
81
82 /**
83  * struct pch_phub_reg - PHUB register structure
84  * @phub_id_reg:                        PHUB_ID register val
85  * @q_pri_val_reg:                      QUEUE_PRI_VAL register val
86  * @rc_q_maxsize_reg:                   RC_QUEUE_MAXSIZE register val
87  * @bri_q_maxsize_reg:                  BRI_QUEUE_MAXSIZE register val
88  * @comp_resp_timeout_reg:              COMP_RESP_TIMEOUT register val
89  * @bus_slave_control_reg:              BUS_SLAVE_CONTROL_REG register val
90  * @deadlock_avoid_type_reg:            DEADLOCK_AVOID_TYPE register val
91  * @intpin_reg_wpermit_reg0:            INTPIN_REG_WPERMIT register 0 val
92  * @intpin_reg_wpermit_reg1:            INTPIN_REG_WPERMIT register 1 val
93  * @intpin_reg_wpermit_reg2:            INTPIN_REG_WPERMIT register 2 val
94  * @intpin_reg_wpermit_reg3:            INTPIN_REG_WPERMIT register 3 val
95  * @int_reduce_control_reg:             INT_REDUCE_CONTROL registers val
96  * @clkcfg_reg:                         CLK CFG register val
97  * @pch_phub_base_address:              Register base address
98  * @pch_phub_extrom_base_address:       external rom base address
99  */
100 struct pch_phub_reg {
101         u32 phub_id_reg;
102         u32 q_pri_val_reg;
103         u32 rc_q_maxsize_reg;
104         u32 bri_q_maxsize_reg;
105         u32 comp_resp_timeout_reg;
106         u32 bus_slave_control_reg;
107         u32 deadlock_avoid_type_reg;
108         u32 intpin_reg_wpermit_reg0;
109         u32 intpin_reg_wpermit_reg1;
110         u32 intpin_reg_wpermit_reg2;
111         u32 intpin_reg_wpermit_reg3;
112         u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
113         u32 clkcfg_reg;
114         void __iomem *pch_phub_base_address;
115         void __iomem *pch_phub_extrom_base_address;
116 };
117
118 /* SROM SPEC for MAC address assignment offset */
119 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
120
121 static DEFINE_MUTEX(pch_phub_mutex);
122
123 /**
124  * pch_phub_read_modify_write_reg() - Reading modifying and writing register
125  * @reg_addr_offset:    Register offset address value.
126  * @data:               Writing value.
127  * @mask:               Mask value.
128  */
129 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
130                                            unsigned int reg_addr_offset,
131                                            unsigned int data, unsigned int mask)
132 {
133         void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
134         iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
135 }
136
137 /* pch_phub_save_reg_conf - saves register configuration */
138 static void pch_phub_save_reg_conf(struct pci_dev *pdev)
139 {
140         unsigned int i;
141         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
142
143         void __iomem *p = chip->pch_phub_base_address;
144
145         chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
146         chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
147         chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
148         chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
149         chip->comp_resp_timeout_reg =
150                                 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
151         chip->bus_slave_control_reg =
152                                 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
153         chip->deadlock_avoid_type_reg =
154                                 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
155         chip->intpin_reg_wpermit_reg0 =
156                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
157         chip->intpin_reg_wpermit_reg1 =
158                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
159         chip->intpin_reg_wpermit_reg2 =
160                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
161         chip->intpin_reg_wpermit_reg3 =
162                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
163         dev_dbg(&pdev->dev, "%s : "
164                 "chip->phub_id_reg=%x, "
165                 "chip->q_pri_val_reg=%x, "
166                 "chip->rc_q_maxsize_reg=%x, "
167                 "chip->bri_q_maxsize_reg=%x, "
168                 "chip->comp_resp_timeout_reg=%x, "
169                 "chip->bus_slave_control_reg=%x, "
170                 "chip->deadlock_avoid_type_reg=%x, "
171                 "chip->intpin_reg_wpermit_reg0=%x, "
172                 "chip->intpin_reg_wpermit_reg1=%x, "
173                 "chip->intpin_reg_wpermit_reg2=%x, "
174                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
175                 chip->phub_id_reg,
176                 chip->q_pri_val_reg,
177                 chip->rc_q_maxsize_reg,
178                 chip->bri_q_maxsize_reg,
179                 chip->comp_resp_timeout_reg,
180                 chip->bus_slave_control_reg,
181                 chip->deadlock_avoid_type_reg,
182                 chip->intpin_reg_wpermit_reg0,
183                 chip->intpin_reg_wpermit_reg1,
184                 chip->intpin_reg_wpermit_reg2,
185                 chip->intpin_reg_wpermit_reg3);
186         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
187                 chip->int_reduce_control_reg[i] =
188                     ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
189                 dev_dbg(&pdev->dev, "%s : "
190                         "chip->int_reduce_control_reg[%d]=%x\n",
191                         __func__, i, chip->int_reduce_control_reg[i]);
192         }
193         chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
194 }
195
196 /* pch_phub_restore_reg_conf - restore register configuration */
197 static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
198 {
199         unsigned int i;
200         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
201         void __iomem *p;
202         p = chip->pch_phub_base_address;
203
204         iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
205         iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
206         iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
207         iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
208         iowrite32(chip->comp_resp_timeout_reg,
209                                         p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
210         iowrite32(chip->bus_slave_control_reg,
211                                         p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
212         iowrite32(chip->deadlock_avoid_type_reg,
213                                         p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
214         iowrite32(chip->intpin_reg_wpermit_reg0,
215                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
216         iowrite32(chip->intpin_reg_wpermit_reg1,
217                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
218         iowrite32(chip->intpin_reg_wpermit_reg2,
219                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
220         iowrite32(chip->intpin_reg_wpermit_reg3,
221                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
222         dev_dbg(&pdev->dev, "%s : "
223                 "chip->phub_id_reg=%x, "
224                 "chip->q_pri_val_reg=%x, "
225                 "chip->rc_q_maxsize_reg=%x, "
226                 "chip->bri_q_maxsize_reg=%x, "
227                 "chip->comp_resp_timeout_reg=%x, "
228                 "chip->bus_slave_control_reg=%x, "
229                 "chip->deadlock_avoid_type_reg=%x, "
230                 "chip->intpin_reg_wpermit_reg0=%x, "
231                 "chip->intpin_reg_wpermit_reg1=%x, "
232                 "chip->intpin_reg_wpermit_reg2=%x, "
233                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
234                 chip->phub_id_reg,
235                 chip->q_pri_val_reg,
236                 chip->rc_q_maxsize_reg,
237                 chip->bri_q_maxsize_reg,
238                 chip->comp_resp_timeout_reg,
239                 chip->bus_slave_control_reg,
240                 chip->deadlock_avoid_type_reg,
241                 chip->intpin_reg_wpermit_reg0,
242                 chip->intpin_reg_wpermit_reg1,
243                 chip->intpin_reg_wpermit_reg2,
244                 chip->intpin_reg_wpermit_reg3);
245         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
246                 iowrite32(chip->int_reduce_control_reg[i],
247                         p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
248                 dev_dbg(&pdev->dev, "%s : "
249                         "chip->int_reduce_control_reg[%d]=%x\n",
250                         __func__, i, chip->int_reduce_control_reg[i]);
251         }
252
253         iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
254 }
255
256 /**
257  * pch_phub_read_serial_rom() - Reading Serial ROM
258  * @offset_address:     Serial ROM offset address to read.
259  * @data:               Read buffer for specified Serial ROM value.
260  */
261 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
262                                      unsigned int offset_address, u8 *data)
263 {
264         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
265                                                                 offset_address;
266
267         *data = ioread8(mem_addr);
268 }
269
270 /**
271  * pch_phub_write_serial_rom() - Writing Serial ROM
272  * @offset_address:     Serial ROM offset address.
273  * @data:               Serial ROM value to write.
274  */
275 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
276                                      unsigned int offset_address, u8 data)
277 {
278         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
279                                         (offset_address & PCH_WORD_ADDR_MASK);
280         int i;
281         unsigned int word_data;
282         unsigned int pos;
283         unsigned int mask;
284         pos = (offset_address % 4) * 8;
285         mask = ~(0xFF << pos);
286
287         iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
288                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
289
290         word_data = ioread32(mem_addr);
291         iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
292
293         i = 0;
294         while (ioread8(chip->pch_phub_extrom_base_address +
295                                                 PHUB_STATUS) != 0x00) {
296                 msleep(1);
297                 if (i == PHUB_TIMEOUT)
298                         return -ETIMEDOUT;
299                 i++;
300         }
301
302         iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
303                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
304
305         return 0;
306 }
307
308 /**
309  * pch_phub_read_serial_rom_val() - Read Serial ROM value
310  * @offset_address:     Serial ROM address offset value.
311  * @data:               Serial ROM value to read.
312  */
313 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
314                                          unsigned int offset_address, u8 *data)
315 {
316         unsigned int mem_addr;
317
318         mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
319                         pch_phub_mac_offset[offset_address];
320
321         pch_phub_read_serial_rom(chip, mem_addr, data);
322 }
323
324 /**
325  * pch_phub_write_serial_rom_val() - writing Serial ROM value
326  * @offset_address:     Serial ROM address offset value.
327  * @data:               Serial ROM value.
328  */
329 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
330                                          unsigned int offset_address, u8 data)
331 {
332         int retval;
333         unsigned int mem_addr;
334
335         mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
336                         pch_phub_mac_offset[offset_address];
337
338         retval = pch_phub_write_serial_rom(chip, mem_addr, data);
339
340         return retval;
341 }
342
343 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
344  * for Gigabit Ethernet MAC address
345  */
346 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
347 {
348         int retval;
349
350         retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
351         retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
352         retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
353         retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
354
355         retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
356         retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
357         retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
358         retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
359
360         retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
361         retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
362         retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
363         retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
364
365         retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
366         retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
367         retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
368         retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
369
370         retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
371         retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
372         retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
373         retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
374
375         retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
376         retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
377         retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
378         retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
379
380         return retval;
381 }
382
383 /**
384  * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
385  * @offset_address:     Gigabit Ethernet MAC address offset value.
386  * @data:               Buffer of the Gigabit Ethernet MAC address value.
387  */
388 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
389 {
390         int i;
391         for (i = 0; i < ETH_ALEN; i++)
392                 pch_phub_read_serial_rom_val(chip, i, &data[i]);
393 }
394
395 /**
396  * pch_phub_write_gbe_mac_addr() - Write MAC address
397  * @offset_address:     Gigabit Ethernet MAC address offset value.
398  * @data:               Gigabit Ethernet MAC address value.
399  */
400 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
401 {
402         int retval;
403         int i;
404
405         retval = pch_phub_gbe_serial_rom_conf(chip);
406         if (retval)
407                 return retval;
408
409         for (i = 0; i < ETH_ALEN; i++) {
410                 retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
411                 if (retval)
412                         return retval;
413         }
414
415         return retval;
416 }
417
418 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
419                                  struct bin_attribute *attr, char *buf,
420                                  loff_t off, size_t count)
421 {
422         unsigned int rom_signature;
423         unsigned char rom_length;
424         unsigned int tmp;
425         unsigned int addr_offset;
426         unsigned int orom_size;
427         int ret;
428         int err;
429
430         struct pch_phub_reg *chip =
431                 dev_get_drvdata(container_of(kobj, struct device, kobj));
432
433         ret = mutex_lock_interruptible(&pch_phub_mutex);
434         if (ret) {
435                 err = -ERESTARTSYS;
436                 goto return_err_nomutex;
437         }
438
439         /* Get Rom signature */
440         pch_phub_read_serial_rom(chip, 0x80, (unsigned char *)&rom_signature);
441         rom_signature &= 0xff;
442         pch_phub_read_serial_rom(chip, 0x81, (unsigned char *)&tmp);
443         rom_signature |= (tmp & 0xff) << 8;
444         if (rom_signature == 0xAA55) {
445                 pch_phub_read_serial_rom(chip, 0x82, &rom_length);
446                 orom_size = rom_length * 512;
447                 if (orom_size < off) {
448                         addr_offset = 0;
449                         goto return_ok;
450                 }
451                 if (orom_size < count) {
452                         addr_offset = 0;
453                         goto return_ok;
454                 }
455
456                 for (addr_offset = 0; addr_offset < count; addr_offset++) {
457                         pch_phub_read_serial_rom(chip, 0x80 + addr_offset + off,
458                                                          &buf[addr_offset]);
459                 }
460         } else {
461                 err = -ENODATA;
462                 goto return_err;
463         }
464 return_ok:
465         mutex_unlock(&pch_phub_mutex);
466         return addr_offset;
467
468 return_err:
469         mutex_unlock(&pch_phub_mutex);
470 return_err_nomutex:
471         return err;
472 }
473
474 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
475                                   struct bin_attribute *attr,
476                                   char *buf, loff_t off, size_t count)
477 {
478         int err;
479         unsigned int addr_offset;
480         int ret;
481         struct pch_phub_reg *chip =
482                 dev_get_drvdata(container_of(kobj, struct device, kobj));
483
484         ret = mutex_lock_interruptible(&pch_phub_mutex);
485         if (ret)
486                 return -ERESTARTSYS;
487
488         if (off > PCH_PHUB_OROM_SIZE) {
489                 addr_offset = 0;
490                 goto return_ok;
491         }
492         if (count > PCH_PHUB_OROM_SIZE) {
493                 addr_offset = 0;
494                 goto return_ok;
495         }
496
497         for (addr_offset = 0; addr_offset < count; addr_offset++) {
498                 if (PCH_PHUB_OROM_SIZE < off + addr_offset)
499                         goto return_ok;
500
501                 ret = pch_phub_write_serial_rom(chip, 0x80 + addr_offset + off,
502                                                        buf[addr_offset]);
503                 if (ret) {
504                         err = ret;
505                         goto return_err;
506                 }
507         }
508
509 return_ok:
510         mutex_unlock(&pch_phub_mutex);
511         return addr_offset;
512
513 return_err:
514         mutex_unlock(&pch_phub_mutex);
515         return err;
516 }
517
518 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
519                             char *buf)
520 {
521         u8 mac[8];
522         struct pch_phub_reg *chip = dev_get_drvdata(dev);
523
524         pch_phub_read_gbe_mac_addr(chip, mac);
525
526         return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n",
527                                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
528 }
529
530 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
531                              const char *buf, size_t count)
532 {
533         u8 mac[6];
534         struct pch_phub_reg *chip = dev_get_drvdata(dev);
535
536         if (count != 18)
537                 return -EINVAL;
538
539         sscanf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
540                 (u32 *)&mac[0], (u32 *)&mac[1], (u32 *)&mac[2], (u32 *)&mac[3],
541                 (u32 *)&mac[4], (u32 *)&mac[5]);
542
543         pch_phub_write_gbe_mac_addr(chip, mac);
544
545         return count;
546 }
547
548 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
549
550 static struct bin_attribute pch_bin_attr = {
551         .attr = {
552                 .name = "pch_firmware",
553                 .mode = S_IRUGO | S_IWUSR,
554         },
555         .size = PCH_PHUB_OROM_SIZE + 1,
556         .read = pch_phub_bin_read,
557         .write = pch_phub_bin_write,
558 };
559
560 static int __devinit pch_phub_probe(struct pci_dev *pdev,
561                                     const struct pci_device_id *id)
562 {
563         int retval;
564
565         int ret;
566         ssize_t rom_size;
567         struct pch_phub_reg *chip;
568
569         chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
570         if (chip == NULL)
571                 return -ENOMEM;
572
573         ret = pci_enable_device(pdev);
574         if (ret) {
575                 dev_err(&pdev->dev,
576                 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
577                 goto err_pci_enable_dev;
578         }
579         dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
580                 ret);
581
582         ret = pci_request_regions(pdev, KBUILD_MODNAME);
583         if (ret) {
584                 dev_err(&pdev->dev,
585                 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
586                 goto err_req_regions;
587         }
588         dev_dbg(&pdev->dev, "%s : "
589                 "pci_request_regions returns %d\n", __func__, ret);
590
591         chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
592
593
594         if (chip->pch_phub_base_address == 0) {
595                 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
596                 ret = -ENOMEM;
597                 goto err_pci_iomap;
598         }
599         dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
600                 "in pch_phub_base_address variable is %p\n", __func__,
601                 chip->pch_phub_base_address);
602         chip->pch_phub_extrom_base_address = pci_map_rom(pdev, &rom_size);
603
604         if (chip->pch_phub_extrom_base_address == 0) {
605                 dev_err(&pdev->dev, "%s : pci_map_rom FAILED", __func__);
606                 ret = -ENOMEM;
607                 goto err_pci_map;
608         }
609         dev_dbg(&pdev->dev, "%s : "
610                 "pci_map_rom SUCCESS and value in "
611                 "pch_phub_extrom_base_address variable is %p\n", __func__,
612                 chip->pch_phub_extrom_base_address);
613
614         if (id->driver_data == 1) {
615                 retval = sysfs_create_file(&pdev->dev.kobj,
616                                            &dev_attr_pch_mac.attr);
617                 if (retval)
618                         goto err_sysfs_create;
619
620                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
621                 if (retval)
622                         goto exit_bin_attr;
623
624                 pch_phub_read_modify_write_reg(chip,
625                                                (unsigned int)CLKCFG_REG_OFFSET,
626                                                CLKCFG_CAN_50MHZ,
627                                                CLKCFG_CANCLK_MASK);
628
629                 /* quirk for CM-iTC board */
630                 if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
631                         pch_phub_read_modify_write_reg(chip,
632                                                 (unsigned int)CLKCFG_REG_OFFSET,
633                                                 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
634                                                 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
635                                                 CLKCFG_UART_MASK);
636
637                 /* set the prefech value */
638                 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
639                 /* set the interrupt delay value */
640                 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
641         } else if (id->driver_data == 2) {
642                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
643                 if (retval)
644                         goto err_sysfs_create;
645                 /* set the prefech value
646                  * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
647                  * Device4(SDIO #0,1,2):f
648                  * Device6(SATA 2):f
649                  * Device8(USB OHCI #0/ USB EHCI #0):a
650                  */
651                 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
652         }
653         pci_set_drvdata(pdev, chip);
654
655         return 0;
656 exit_bin_attr:
657         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
658
659 err_sysfs_create:
660         pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address);
661 err_pci_map:
662         pci_iounmap(pdev, chip->pch_phub_base_address);
663 err_pci_iomap:
664         pci_release_regions(pdev);
665 err_req_regions:
666         pci_disable_device(pdev);
667 err_pci_enable_dev:
668         kfree(chip);
669         dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
670         return ret;
671 }
672
673 static void __devexit pch_phub_remove(struct pci_dev *pdev)
674 {
675         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
676
677         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
678         sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
679         pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address);
680         pci_iounmap(pdev, chip->pch_phub_base_address);
681         pci_release_regions(pdev);
682         pci_disable_device(pdev);
683         kfree(chip);
684 }
685
686 #ifdef CONFIG_PM
687
688 static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state)
689 {
690         int ret;
691
692         pch_phub_save_reg_conf(pdev);
693         ret = pci_save_state(pdev);
694         if (ret) {
695                 dev_err(&pdev->dev,
696                         " %s -pci_save_state returns %d\n", __func__, ret);
697                 return ret;
698         }
699         pci_enable_wake(pdev, PCI_D3hot, 0);
700         pci_disable_device(pdev);
701         pci_set_power_state(pdev, pci_choose_state(pdev, state));
702
703         return 0;
704 }
705
706 static int pch_phub_resume(struct pci_dev *pdev)
707 {
708         int ret;
709
710         pci_set_power_state(pdev, PCI_D0);
711         pci_restore_state(pdev);
712         ret = pci_enable_device(pdev);
713         if (ret) {
714                 dev_err(&pdev->dev,
715                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
716                 return ret;
717         }
718
719         pci_enable_wake(pdev, PCI_D3hot, 0);
720         pch_phub_restore_reg_conf(pdev);
721
722         return 0;
723 }
724 #else
725 #define pch_phub_suspend NULL
726 #define pch_phub_resume NULL
727 #endif /* CONFIG_PM */
728
729 static struct pci_device_id pch_phub_pcidev_id[] = {
730         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB),       1,  },
731         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2,  },
732         { }
733 };
734
735 static struct pci_driver pch_phub_driver = {
736         .name = "pch_phub",
737         .id_table = pch_phub_pcidev_id,
738         .probe = pch_phub_probe,
739         .remove = __devexit_p(pch_phub_remove),
740         .suspend = pch_phub_suspend,
741         .resume = pch_phub_resume
742 };
743
744 static int __init pch_phub_pci_init(void)
745 {
746         return pci_register_driver(&pch_phub_driver);
747 }
748
749 static void __exit pch_phub_pci_exit(void)
750 {
751         pci_unregister_driver(&pch_phub_driver);
752 }
753
754 module_init(pch_phub_pci_init);
755 module_exit(pch_phub_pci_exit);
756
757 MODULE_DESCRIPTION("PCH Packet Hub PCI Driver");
758 MODULE_LICENSE("GPL");