Merge branch 'tty-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6
[linux-2.6.git] / drivers / misc / pch_phub.c
1 /*
2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; version 2 of the License.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
16  */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/fs.h>
22 #include <linux/uaccess.h>
23 #include <linux/string.h>
24 #include <linux/pci.h>
25 #include <linux/io.h>
26 #include <linux/delay.h>
27 #include <linux/mutex.h>
28 #include <linux/if_ether.h>
29 #include <linux/ctype.h>
30 #include <linux/dmi.h>
31
32 #define PHUB_STATUS 0x00                /* Status Register offset */
33 #define PHUB_CONTROL 0x04               /* Control Register offset */
34 #define PHUB_TIMEOUT 0x05               /* Time out value for Status Register */
35 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01  /* Enabling for writing ROM */
36 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
37 #define PCH_PHUB_MAC_START_ADDR 0x20C  /* MAC data area start address offset */
38 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x14 /* ROM data area start address offset
39                                               (Intel EG20T PCH)*/
40 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
41                                                 offset(OKI SEMICONDUCTOR ML7213)
42                                               */
43
44 /* MAX number of INT_REDUCE_CONTROL registers */
45 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128
46 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801
47 #define PCH_MINOR_NOS 1
48 #define CLKCFG_CAN_50MHZ 0x12000000
49 #define CLKCFG_CANCLK_MASK 0xFF000000
50 #define CLKCFG_UART_MASK                        0xFFFFFF
51
52 /* CM-iTC */
53 #define CLKCFG_UART_48MHZ                       (1 << 16)
54 #define CLKCFG_BAUDDIV                          (2 << 20)
55 #define CLKCFG_PLL2VCO                          (8 << 9)
56 #define CLKCFG_UARTCLKSEL                       (1 << 18)
57
58 /* Macros for ML7213 */
59 #define PCI_VENDOR_ID_ROHM                      0x10db
60 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
61
62 /* Macros for ML7213 */
63 #define PCI_VENDOR_ID_ROHM                      0x10db
64 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
65
66 /* SROM ACCESS Macro */
67 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
68
69 /* Registers address offset */
70 #define PCH_PHUB_ID_REG                         0x0000
71 #define PCH_PHUB_QUEUE_PRI_VAL_REG              0x0004
72 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG           0x0008
73 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG          0x000C
74 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG          0x0010
75 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG          0x0014
76 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG        0x0018
77 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0        0x0020
78 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1        0x0024
79 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2        0x0028
80 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3        0x002C
81 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE    0x0040
82 #define CLKCFG_REG_OFFSET                       0x500
83
84 #define PCH_PHUB_OROM_SIZE 15360
85
86 /**
87  * struct pch_phub_reg - PHUB register structure
88  * @phub_id_reg:                        PHUB_ID register val
89  * @q_pri_val_reg:                      QUEUE_PRI_VAL register val
90  * @rc_q_maxsize_reg:                   RC_QUEUE_MAXSIZE register val
91  * @bri_q_maxsize_reg:                  BRI_QUEUE_MAXSIZE register val
92  * @comp_resp_timeout_reg:              COMP_RESP_TIMEOUT register val
93  * @bus_slave_control_reg:              BUS_SLAVE_CONTROL_REG register val
94  * @deadlock_avoid_type_reg:            DEADLOCK_AVOID_TYPE register val
95  * @intpin_reg_wpermit_reg0:            INTPIN_REG_WPERMIT register 0 val
96  * @intpin_reg_wpermit_reg1:            INTPIN_REG_WPERMIT register 1 val
97  * @intpin_reg_wpermit_reg2:            INTPIN_REG_WPERMIT register 2 val
98  * @intpin_reg_wpermit_reg3:            INTPIN_REG_WPERMIT register 3 val
99  * @int_reduce_control_reg:             INT_REDUCE_CONTROL registers val
100  * @clkcfg_reg:                         CLK CFG register val
101  * @pch_phub_base_address:              Register base address
102  * @pch_phub_extrom_base_address:       external rom base address
103  */
104 struct pch_phub_reg {
105         u32 phub_id_reg;
106         u32 q_pri_val_reg;
107         u32 rc_q_maxsize_reg;
108         u32 bri_q_maxsize_reg;
109         u32 comp_resp_timeout_reg;
110         u32 bus_slave_control_reg;
111         u32 deadlock_avoid_type_reg;
112         u32 intpin_reg_wpermit_reg0;
113         u32 intpin_reg_wpermit_reg1;
114         u32 intpin_reg_wpermit_reg2;
115         u32 intpin_reg_wpermit_reg3;
116         u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
117         u32 clkcfg_reg;
118         void __iomem *pch_phub_base_address;
119         void __iomem *pch_phub_extrom_base_address;
120 };
121
122 /* SROM SPEC for MAC address assignment offset */
123 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
124
125 static DEFINE_MUTEX(pch_phub_mutex);
126
127 /**
128  * pch_phub_read_modify_write_reg() - Reading modifying and writing register
129  * @reg_addr_offset:    Register offset address value.
130  * @data:               Writing value.
131  * @mask:               Mask value.
132  */
133 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
134                                            unsigned int reg_addr_offset,
135                                            unsigned int data, unsigned int mask)
136 {
137         void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
138         iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
139 }
140
141 /* pch_phub_save_reg_conf - saves register configuration */
142 static void pch_phub_save_reg_conf(struct pci_dev *pdev)
143 {
144         unsigned int i;
145         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
146
147         void __iomem *p = chip->pch_phub_base_address;
148
149         chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
150         chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
151         chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
152         chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
153         chip->comp_resp_timeout_reg =
154                                 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
155         chip->bus_slave_control_reg =
156                                 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
157         chip->deadlock_avoid_type_reg =
158                                 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
159         chip->intpin_reg_wpermit_reg0 =
160                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
161         chip->intpin_reg_wpermit_reg1 =
162                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
163         chip->intpin_reg_wpermit_reg2 =
164                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
165         chip->intpin_reg_wpermit_reg3 =
166                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
167         dev_dbg(&pdev->dev, "%s : "
168                 "chip->phub_id_reg=%x, "
169                 "chip->q_pri_val_reg=%x, "
170                 "chip->rc_q_maxsize_reg=%x, "
171                 "chip->bri_q_maxsize_reg=%x, "
172                 "chip->comp_resp_timeout_reg=%x, "
173                 "chip->bus_slave_control_reg=%x, "
174                 "chip->deadlock_avoid_type_reg=%x, "
175                 "chip->intpin_reg_wpermit_reg0=%x, "
176                 "chip->intpin_reg_wpermit_reg1=%x, "
177                 "chip->intpin_reg_wpermit_reg2=%x, "
178                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
179                 chip->phub_id_reg,
180                 chip->q_pri_val_reg,
181                 chip->rc_q_maxsize_reg,
182                 chip->bri_q_maxsize_reg,
183                 chip->comp_resp_timeout_reg,
184                 chip->bus_slave_control_reg,
185                 chip->deadlock_avoid_type_reg,
186                 chip->intpin_reg_wpermit_reg0,
187                 chip->intpin_reg_wpermit_reg1,
188                 chip->intpin_reg_wpermit_reg2,
189                 chip->intpin_reg_wpermit_reg3);
190         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
191                 chip->int_reduce_control_reg[i] =
192                     ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
193                 dev_dbg(&pdev->dev, "%s : "
194                         "chip->int_reduce_control_reg[%d]=%x\n",
195                         __func__, i, chip->int_reduce_control_reg[i]);
196         }
197         chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
198 }
199
200 /* pch_phub_restore_reg_conf - restore register configuration */
201 static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
202 {
203         unsigned int i;
204         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
205         void __iomem *p;
206         p = chip->pch_phub_base_address;
207
208         iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
209         iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
210         iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
211         iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
212         iowrite32(chip->comp_resp_timeout_reg,
213                                         p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
214         iowrite32(chip->bus_slave_control_reg,
215                                         p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
216         iowrite32(chip->deadlock_avoid_type_reg,
217                                         p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
218         iowrite32(chip->intpin_reg_wpermit_reg0,
219                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
220         iowrite32(chip->intpin_reg_wpermit_reg1,
221                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
222         iowrite32(chip->intpin_reg_wpermit_reg2,
223                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
224         iowrite32(chip->intpin_reg_wpermit_reg3,
225                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
226         dev_dbg(&pdev->dev, "%s : "
227                 "chip->phub_id_reg=%x, "
228                 "chip->q_pri_val_reg=%x, "
229                 "chip->rc_q_maxsize_reg=%x, "
230                 "chip->bri_q_maxsize_reg=%x, "
231                 "chip->comp_resp_timeout_reg=%x, "
232                 "chip->bus_slave_control_reg=%x, "
233                 "chip->deadlock_avoid_type_reg=%x, "
234                 "chip->intpin_reg_wpermit_reg0=%x, "
235                 "chip->intpin_reg_wpermit_reg1=%x, "
236                 "chip->intpin_reg_wpermit_reg2=%x, "
237                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
238                 chip->phub_id_reg,
239                 chip->q_pri_val_reg,
240                 chip->rc_q_maxsize_reg,
241                 chip->bri_q_maxsize_reg,
242                 chip->comp_resp_timeout_reg,
243                 chip->bus_slave_control_reg,
244                 chip->deadlock_avoid_type_reg,
245                 chip->intpin_reg_wpermit_reg0,
246                 chip->intpin_reg_wpermit_reg1,
247                 chip->intpin_reg_wpermit_reg2,
248                 chip->intpin_reg_wpermit_reg3);
249         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
250                 iowrite32(chip->int_reduce_control_reg[i],
251                         p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
252                 dev_dbg(&pdev->dev, "%s : "
253                         "chip->int_reduce_control_reg[%d]=%x\n",
254                         __func__, i, chip->int_reduce_control_reg[i]);
255         }
256
257         iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
258 }
259
260 /**
261  * pch_phub_read_serial_rom() - Reading Serial ROM
262  * @offset_address:     Serial ROM offset address to read.
263  * @data:               Read buffer for specified Serial ROM value.
264  */
265 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
266                                      unsigned int offset_address, u8 *data)
267 {
268         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
269                                                                 offset_address;
270
271         *data = ioread8(mem_addr);
272 }
273
274 /**
275  * pch_phub_write_serial_rom() - Writing Serial ROM
276  * @offset_address:     Serial ROM offset address.
277  * @data:               Serial ROM value to write.
278  */
279 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
280                                      unsigned int offset_address, u8 data)
281 {
282         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
283                                         (offset_address & PCH_WORD_ADDR_MASK);
284         int i;
285         unsigned int word_data;
286         unsigned int pos;
287         unsigned int mask;
288         pos = (offset_address % 4) * 8;
289         mask = ~(0xFF << pos);
290
291         iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
292                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
293
294         word_data = ioread32(mem_addr);
295         iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
296
297         i = 0;
298         while (ioread8(chip->pch_phub_extrom_base_address +
299                                                 PHUB_STATUS) != 0x00) {
300                 msleep(1);
301                 if (i == PHUB_TIMEOUT)
302                         return -ETIMEDOUT;
303                 i++;
304         }
305
306         iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
307                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
308
309         return 0;
310 }
311
312 /**
313  * pch_phub_read_serial_rom_val() - Read Serial ROM value
314  * @offset_address:     Serial ROM address offset value.
315  * @data:               Serial ROM value to read.
316  */
317 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
318                                          unsigned int offset_address, u8 *data)
319 {
320         unsigned int mem_addr;
321
322         mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
323                         pch_phub_mac_offset[offset_address];
324
325         pch_phub_read_serial_rom(chip, mem_addr, data);
326 }
327
328 /**
329  * pch_phub_write_serial_rom_val() - writing Serial ROM value
330  * @offset_address:     Serial ROM address offset value.
331  * @data:               Serial ROM value.
332  */
333 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
334                                          unsigned int offset_address, u8 data)
335 {
336         int retval;
337         unsigned int mem_addr;
338
339         mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
340                         pch_phub_mac_offset[offset_address];
341
342         retval = pch_phub_write_serial_rom(chip, mem_addr, data);
343
344         return retval;
345 }
346
347 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
348  * for Gigabit Ethernet MAC address
349  */
350 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
351 {
352         int retval;
353
354         retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
355         retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
356         retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
357         retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
358
359         retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
360         retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
361         retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
362         retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
363
364         retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
365         retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
366         retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
367         retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
368
369         retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
370         retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
371         retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
372         retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
373
374         retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
375         retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
376         retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
377         retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
378
379         retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
380         retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
381         retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
382         retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
383
384         return retval;
385 }
386
387 /**
388  * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
389  * @offset_address:     Gigabit Ethernet MAC address offset value.
390  * @data:               Buffer of the Gigabit Ethernet MAC address value.
391  */
392 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
393 {
394         int i;
395         for (i = 0; i < ETH_ALEN; i++)
396                 pch_phub_read_serial_rom_val(chip, i, &data[i]);
397 }
398
399 /**
400  * pch_phub_write_gbe_mac_addr() - Write MAC address
401  * @offset_address:     Gigabit Ethernet MAC address offset value.
402  * @data:               Gigabit Ethernet MAC address value.
403  */
404 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
405 {
406         int retval;
407         int i;
408
409         retval = pch_phub_gbe_serial_rom_conf(chip);
410         if (retval)
411                 return retval;
412
413         for (i = 0; i < ETH_ALEN; i++) {
414                 retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
415                 if (retval)
416                         return retval;
417         }
418
419         return retval;
420 }
421
422 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
423                                  struct bin_attribute *attr, char *buf,
424                                  loff_t off, size_t count)
425 {
426         unsigned int rom_signature;
427         unsigned char rom_length;
428         unsigned int tmp;
429         unsigned int addr_offset;
430         unsigned int orom_size;
431         int ret;
432         int err;
433
434         struct pch_phub_reg *chip =
435                 dev_get_drvdata(container_of(kobj, struct device, kobj));
436
437         ret = mutex_lock_interruptible(&pch_phub_mutex);
438         if (ret) {
439                 err = -ERESTARTSYS;
440                 goto return_err_nomutex;
441         }
442
443         /* Get Rom signature */
444         pch_phub_read_serial_rom(chip, 0x80, (unsigned char *)&rom_signature);
445         rom_signature &= 0xff;
446         pch_phub_read_serial_rom(chip, 0x81, (unsigned char *)&tmp);
447         rom_signature |= (tmp & 0xff) << 8;
448         if (rom_signature == 0xAA55) {
449                 pch_phub_read_serial_rom(chip, 0x82, &rom_length);
450                 orom_size = rom_length * 512;
451                 if (orom_size < off) {
452                         addr_offset = 0;
453                         goto return_ok;
454                 }
455                 if (orom_size < count) {
456                         addr_offset = 0;
457                         goto return_ok;
458                 }
459
460                 for (addr_offset = 0; addr_offset < count; addr_offset++) {
461                         pch_phub_read_serial_rom(chip, 0x80 + addr_offset + off,
462                                                          &buf[addr_offset]);
463                 }
464         } else {
465                 err = -ENODATA;
466                 goto return_err;
467         }
468 return_ok:
469         mutex_unlock(&pch_phub_mutex);
470         return addr_offset;
471
472 return_err:
473         mutex_unlock(&pch_phub_mutex);
474 return_err_nomutex:
475         return err;
476 }
477
478 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
479                                   struct bin_attribute *attr,
480                                   char *buf, loff_t off, size_t count)
481 {
482         int err;
483         unsigned int addr_offset;
484         int ret;
485         struct pch_phub_reg *chip =
486                 dev_get_drvdata(container_of(kobj, struct device, kobj));
487
488         ret = mutex_lock_interruptible(&pch_phub_mutex);
489         if (ret)
490                 return -ERESTARTSYS;
491
492         if (off > PCH_PHUB_OROM_SIZE) {
493                 addr_offset = 0;
494                 goto return_ok;
495         }
496         if (count > PCH_PHUB_OROM_SIZE) {
497                 addr_offset = 0;
498                 goto return_ok;
499         }
500
501         for (addr_offset = 0; addr_offset < count; addr_offset++) {
502                 if (PCH_PHUB_OROM_SIZE < off + addr_offset)
503                         goto return_ok;
504
505                 ret = pch_phub_write_serial_rom(chip, 0x80 + addr_offset + off,
506                                                        buf[addr_offset]);
507                 if (ret) {
508                         err = ret;
509                         goto return_err;
510                 }
511         }
512
513 return_ok:
514         mutex_unlock(&pch_phub_mutex);
515         return addr_offset;
516
517 return_err:
518         mutex_unlock(&pch_phub_mutex);
519         return err;
520 }
521
522 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
523                             char *buf)
524 {
525         u8 mac[8];
526         struct pch_phub_reg *chip = dev_get_drvdata(dev);
527
528         pch_phub_read_gbe_mac_addr(chip, mac);
529
530         return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n",
531                                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
532 }
533
534 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
535                              const char *buf, size_t count)
536 {
537         u8 mac[6];
538         struct pch_phub_reg *chip = dev_get_drvdata(dev);
539
540         if (count != 18)
541                 return -EINVAL;
542
543         sscanf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
544                 (u32 *)&mac[0], (u32 *)&mac[1], (u32 *)&mac[2], (u32 *)&mac[3],
545                 (u32 *)&mac[4], (u32 *)&mac[5]);
546
547         pch_phub_write_gbe_mac_addr(chip, mac);
548
549         return count;
550 }
551
552 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
553
554 static struct bin_attribute pch_bin_attr = {
555         .attr = {
556                 .name = "pch_firmware",
557                 .mode = S_IRUGO | S_IWUSR,
558         },
559         .size = PCH_PHUB_OROM_SIZE + 1,
560         .read = pch_phub_bin_read,
561         .write = pch_phub_bin_write,
562 };
563
564 static int __devinit pch_phub_probe(struct pci_dev *pdev,
565                                     const struct pci_device_id *id)
566 {
567         int retval;
568
569         int ret;
570         ssize_t rom_size;
571         struct pch_phub_reg *chip;
572
573         chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
574         if (chip == NULL)
575                 return -ENOMEM;
576
577         ret = pci_enable_device(pdev);
578         if (ret) {
579                 dev_err(&pdev->dev,
580                 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
581                 goto err_pci_enable_dev;
582         }
583         dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
584                 ret);
585
586         ret = pci_request_regions(pdev, KBUILD_MODNAME);
587         if (ret) {
588                 dev_err(&pdev->dev,
589                 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
590                 goto err_req_regions;
591         }
592         dev_dbg(&pdev->dev, "%s : "
593                 "pci_request_regions returns %d\n", __func__, ret);
594
595         chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
596
597
598         if (chip->pch_phub_base_address == 0) {
599                 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
600                 ret = -ENOMEM;
601                 goto err_pci_iomap;
602         }
603         dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
604                 "in pch_phub_base_address variable is %p\n", __func__,
605                 chip->pch_phub_base_address);
606         chip->pch_phub_extrom_base_address = pci_map_rom(pdev, &rom_size);
607
608         if (chip->pch_phub_extrom_base_address == 0) {
609                 dev_err(&pdev->dev, "%s : pci_map_rom FAILED", __func__);
610                 ret = -ENOMEM;
611                 goto err_pci_map;
612         }
613         dev_dbg(&pdev->dev, "%s : "
614                 "pci_map_rom SUCCESS and value in "
615                 "pch_phub_extrom_base_address variable is %p\n", __func__,
616                 chip->pch_phub_extrom_base_address);
617
618         if (id->driver_data == 1) {
619                 retval = sysfs_create_file(&pdev->dev.kobj,
620                                            &dev_attr_pch_mac.attr);
621                 if (retval)
622                         goto err_sysfs_create;
623
624                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
625                 if (retval)
626                         goto exit_bin_attr;
627
628                 pch_phub_read_modify_write_reg(chip,
629                                                (unsigned int)CLKCFG_REG_OFFSET,
630                                                CLKCFG_CAN_50MHZ,
631                                                CLKCFG_CANCLK_MASK);
632
633                 /* quirk for CM-iTC board */
634                 if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
635                         pch_phub_read_modify_write_reg(chip,
636                                                 (unsigned int)CLKCFG_REG_OFFSET,
637                                                 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
638                                                 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
639                                                 CLKCFG_UART_MASK);
640
641                 /* set the prefech value */
642                 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
643                 /* set the interrupt delay value */
644                 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
645         } else if (id->driver_data == 2) {
646                 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
647                 if (retval)
648                         goto err_sysfs_create;
649                 /* set the prefech value
650                  * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
651                  * Device4(SDIO #0,1,2):f
652                  * Device6(SATA 2):f
653                  * Device8(USB OHCI #0/ USB EHCI #0):a
654                  */
655                 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
656         }
657         pci_set_drvdata(pdev, chip);
658
659         return 0;
660 exit_bin_attr:
661         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
662
663 err_sysfs_create:
664         pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address);
665 err_pci_map:
666         pci_iounmap(pdev, chip->pch_phub_base_address);
667 err_pci_iomap:
668         pci_release_regions(pdev);
669 err_req_regions:
670         pci_disable_device(pdev);
671 err_pci_enable_dev:
672         kfree(chip);
673         dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
674         return ret;
675 }
676
677 static void __devexit pch_phub_remove(struct pci_dev *pdev)
678 {
679         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
680
681         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
682         sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
683         pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address);
684         pci_iounmap(pdev, chip->pch_phub_base_address);
685         pci_release_regions(pdev);
686         pci_disable_device(pdev);
687         kfree(chip);
688 }
689
690 #ifdef CONFIG_PM
691
692 static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state)
693 {
694         int ret;
695
696         pch_phub_save_reg_conf(pdev);
697         ret = pci_save_state(pdev);
698         if (ret) {
699                 dev_err(&pdev->dev,
700                         " %s -pci_save_state returns %d\n", __func__, ret);
701                 return ret;
702         }
703         pci_enable_wake(pdev, PCI_D3hot, 0);
704         pci_disable_device(pdev);
705         pci_set_power_state(pdev, pci_choose_state(pdev, state));
706
707         return 0;
708 }
709
710 static int pch_phub_resume(struct pci_dev *pdev)
711 {
712         int ret;
713
714         pci_set_power_state(pdev, PCI_D0);
715         pci_restore_state(pdev);
716         ret = pci_enable_device(pdev);
717         if (ret) {
718                 dev_err(&pdev->dev,
719                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
720                 return ret;
721         }
722
723         pci_enable_wake(pdev, PCI_D3hot, 0);
724         pch_phub_restore_reg_conf(pdev);
725
726         return 0;
727 }
728 #else
729 #define pch_phub_suspend NULL
730 #define pch_phub_resume NULL
731 #endif /* CONFIG_PM */
732
733 static struct pci_device_id pch_phub_pcidev_id[] = {
734         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB),       1,  },
735         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2,  },
736         { }
737 };
738
739 static struct pci_driver pch_phub_driver = {
740         .name = "pch_phub",
741         .id_table = pch_phub_pcidev_id,
742         .probe = pch_phub_probe,
743         .remove = __devexit_p(pch_phub_remove),
744         .suspend = pch_phub_suspend,
745         .resume = pch_phub_resume
746 };
747
748 static int __init pch_phub_pci_init(void)
749 {
750         return pci_register_driver(&pch_phub_driver);
751 }
752
753 static void __exit pch_phub_pci_exit(void)
754 {
755         pci_unregister_driver(&pch_phub_driver);
756 }
757
758 module_init(pch_phub_pci_init);
759 module_exit(pch_phub_pci_exit);
760
761 MODULE_DESCRIPTION("PCH Packet Hub PCI Driver");
762 MODULE_LICENSE("GPL");