mfd: tps80031: Support sleep configuration through platform data
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32
33 #include <linux/mfd/core.h>
34 #include <linux/mfd/tps80031.h>
35
36 /* interrupt related registers */
37 #define TPS80031_INT_STS_A              0xD0
38 #define TPS80031_INT_STS_B              0xD1
39 #define TPS80031_INT_STS_C              0xD2
40 #define TPS80031_INT_MSK_LINE_A         0xD3
41 #define TPS80031_INT_MSK_LINE_B         0xD4
42 #define TPS80031_INT_MSK_LINE_C         0xD5
43 #define TPS80031_INT_MSK_STS_A          0xD6
44 #define TPS80031_INT_MSK_STS_B          0xD7
45 #define TPS80031_INT_MSK_STS_C          0xD8
46
47 #define TPS80031_CONTROLLER_STAT1               0xE3
48 #define CONTROLLER_STAT1_BAT_TEMP               0
49 #define CONTROLLER_STAT1_BAT_REMOVED            1
50 #define CONTROLLER_STAT1_VBUS_DET               2
51 #define CONTROLLER_STAT1_VAC_DET                3
52 #define CONTROLLER_STAT1_FAULT_WDG              4
53 #define CONTROLLER_STAT1_LINCH_GATED            6
54
55 #define TPS80031_CONTROLLER_INT_MASK            0xE0
56 #define CONTROLLER_INT_MASK_MVAC_DET            0
57 #define CONTROLLER_INT_MASK_MVBUS_DET           1
58 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
59 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
60 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
61 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
62
63 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
64
65 /* Version number related register */
66 #define TPS80031_JTAGVERNUM             0x87
67 /* Epprom version */
68 #define TPS80031_EPROM_REV              0xDF
69
70 /* External control register */
71 #define REGEN1_BASE_ADD         0xAE
72 #define REGEN2_BASE_ADD         0xB1
73 #define SYSEN_BASE_ADD          0xB4
74
75 /* device control registers */
76 #define TPS80031_PHOENIX_DEV_ON 0x25
77 #define DEVOFF  1
78
79 #define CLK32KAO_BASE_ADD       0xBA
80 #define CLK32KG_BASE_ADD        0xBD
81 #define CLK32KAUDIO_BASE_ADD    0xC0
82
83 #define EXT_CONTROL_CFG_TRANS 0
84 #define EXT_CONTROL_CFG_STATE 1
85
86 #define STATE_OFF       0x00
87 #define STATE_ON        0x01
88 #define STATE_MASK      0x03
89
90 #define TRANS_SLEEP_OFF         0x00
91 #define TRANS_SLEEP_ON          0x04
92 #define TRANS_SLEEP_MASK        0x0C
93
94 #define TPS_NUM_SLAVES  4
95 #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \
96                 PWR_REQ_INPUT_PREQ3)
97 #define TPS80031_PREQ1_RES_ASS_A        0xD7
98 #define TPS80031_PREQ2_RES_ASS_A        0xDA
99 #define TPS80031_PREQ3_RES_ASS_A        0xDD
100 #define TPS80031_PHOENIX_MSK_TRANSITION 0x20
101
102
103 static u8 pmc_ext_control_base[] = {
104         REGEN1_BASE_ADD,
105         REGEN2_BASE_ADD,
106         SYSEN_BASE_ADD,
107 };
108
109 static u8 pmc_clk32k_control_base[] = {
110         CLK32KAO_BASE_ADD,
111         CLK32KG_BASE_ADD,
112         CLK32KAUDIO_BASE_ADD,
113 };
114 struct tps80031_irq_data {
115         u8      mask_reg;
116         u8      mask_mask;
117         u8      is_sec_int;
118         u8      parent_int;
119         u8      mask_sec_int_reg;
120         u8      int_mask_bit;
121         u8      int_sec_sts_reg;
122         u8      int_sts_bit;
123 };
124
125 #define TPS80031_IRQ(_reg, _mask)       \
126         {                                                       \
127                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
128                                 TPS80031_INT_MSK_LINE_A,        \
129                 .mask_mask = (_mask),                           \
130         }
131
132 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
133         {                                                               \
134                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
135                                 TPS80031_INT_MSK_LINE_A,                \
136                 .mask_mask = (_mask),                                   \
137                 .is_sec_int = true,                                     \
138                 .parent_int = TPS80031_INT_##_pint,                     \
139                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
140                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
141                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
142                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
143         }
144
145 static const struct tps80031_irq_data tps80031_irqs[] = {
146
147         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
148         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
149         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
150         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
151         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
152         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
153         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
154         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
155         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
156         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
157         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
158         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
159         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
160         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
161         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
162         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
163         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
164         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
165         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
166         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
167         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
168         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
169         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
170         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
171         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
172                                                 MBAT_TEMP,      BAT_TEMP),
173         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
174                                                 MBAT_REMOVED,   BAT_REMOVED),
175         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
176                                                 MVBUS_DET,      VBUS_DET),
177         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
178                                                 MVAC_DET,       VAC_DET),
179         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
180                                                 MFAULT_WDG,     FAULT_WDG),
181         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
182                                                 MLINCH_GATED,   LINCH_GATED),
183 };
184
185 static const int controller_stat1_irq_nr[] = {
186         TPS80031_INT_BAT_TEMP_OVRANGE,
187         TPS80031_INT_BAT_REMOVED,
188         TPS80031_INT_VBUS_DET,
189         TPS80031_INT_VAC_DET,
190         TPS80031_INT_FAULT_WDG,
191         0,
192         TPS80031_INT_LINCH_GATED,
193         0
194 };
195
196 /* Structure for TPS80031 Slaves */
197 struct tps80031_client {
198         struct i2c_client *client;
199         struct mutex lock;
200         u8 addr;
201 };
202
203 struct tps80031 {
204         struct device           *dev;
205         unsigned long           chip_info;
206         int                     es_version;
207
208         struct gpio_chip        gpio;
209         struct irq_chip         irq_chip;
210         struct mutex            irq_lock;
211         int                     irq_base;
212         u32                     irq_en;
213         u8                      mask_cache[3];
214         u8                      mask_reg[3];
215         u8                      cont_int_mask_reg;
216         u8                      cont_int_mask_cache;
217         u8                      cont_int_en;
218         u8                      prev_cont_stat1;
219         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
220 };
221
222 static inline int __tps80031_read(struct i2c_client *client,
223                                   int reg, uint8_t *val)
224 {
225         int ret;
226
227         ret = i2c_smbus_read_byte_data(client, reg);
228         if (ret < 0) {
229                 dev_err(&client->dev,
230                         "failed reading from addr 0x%02x, reg 0x%02x\n",
231                         client->addr, reg);
232                 return ret;
233         }
234
235         *val = (uint8_t)ret;
236
237         return 0;
238 }
239
240 static inline int __tps80031_reads(struct i2c_client *client, int reg,
241                                 int len, uint8_t *val)
242 {
243         int ret;
244
245         ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
246         if (ret < 0) {
247                 dev_err(&client->dev,
248                         "failed reading from addr 0x%02x, reg   0x%02x\n",
249                          client->addr, reg);
250                 return ret;
251         }
252
253         return 0;
254 }
255
256 static inline int __tps80031_write(struct i2c_client *client,
257                                  int reg, uint8_t val)
258 {
259         int ret;
260         ret = i2c_smbus_write_byte_data(client, reg, val);
261         if (ret < 0) {
262                 dev_err(&client->dev,
263                         "failed writing 0x%02x to 0x%02x\n", val, reg);
264                 return ret;
265         }
266
267         return 0;
268 }
269
270 static inline int __tps80031_writes(struct i2c_client *client, int reg,
271                                   int len, uint8_t *val)
272 {
273         int ret;
274
275         ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
276         if (ret < 0) {
277                 dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
278                 return ret;
279         }
280
281         return 0;
282 }
283
284 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
285 {
286         struct tps80031 *tps80031 = dev_get_drvdata(dev);
287         struct tps80031_client *tps = &tps80031->tps_clients[sid];
288         int ret;
289
290         mutex_lock(&tps->lock);
291         ret = __tps80031_write(tps->client, reg, val);
292         mutex_unlock(&tps->lock);
293
294         return ret;
295 }
296 EXPORT_SYMBOL_GPL(tps80031_write);
297
298 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
299 {
300         struct tps80031 *tps80031 = dev_get_drvdata(dev);
301         struct tps80031_client *tps = &tps80031->tps_clients[sid];
302         int ret;
303
304         mutex_lock(&tps->lock);
305         ret = __tps80031_writes(tps->client, reg, len, val);
306         mutex_unlock(&tps->lock);
307
308         return ret;
309 }
310 EXPORT_SYMBOL_GPL(tps80031_writes);
311
312 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
313 {
314         struct tps80031 *tps80031 = dev_get_drvdata(dev);
315         struct tps80031_client *tps = &tps80031->tps_clients[sid];
316
317         return __tps80031_read(tps->client, reg, val);
318 }
319 EXPORT_SYMBOL_GPL(tps80031_read);
320
321 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
322 {
323         struct tps80031 *tps80031 = dev_get_drvdata(dev);
324         struct tps80031_client *tps = &tps80031->tps_clients[sid];
325
326         return __tps80031_reads(tps->client, reg, len, val);
327 }
328 EXPORT_SYMBOL_GPL(tps80031_reads);
329
330 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
331 {
332         struct tps80031 *tps80031 = dev_get_drvdata(dev);
333         struct tps80031_client *tps = &tps80031->tps_clients[sid];
334         uint8_t reg_val;
335         int ret = 0;
336
337         mutex_lock(&tps->lock);
338
339         ret = __tps80031_read(tps->client, reg, &reg_val);
340         if (ret)
341                 goto out;
342
343         if ((reg_val & bit_mask) != bit_mask) {
344                 reg_val |= bit_mask;
345                 ret = __tps80031_write(tps->client, reg, reg_val);
346         }
347 out:
348         mutex_unlock(&tps->lock);
349         return ret;
350 }
351 EXPORT_SYMBOL_GPL(tps80031_set_bits);
352
353 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
354 {
355         struct tps80031 *tps80031 = dev_get_drvdata(dev);
356         struct tps80031_client *tps = &tps80031->tps_clients[sid];
357         uint8_t reg_val;
358         int ret = 0;
359
360         mutex_lock(&tps->lock);
361
362         ret = __tps80031_read(tps->client, reg, &reg_val);
363         if (ret)
364                 goto out;
365
366         if (reg_val & bit_mask) {
367                 reg_val &= ~bit_mask;
368                 ret = __tps80031_write(tps->client, reg, reg_val);
369         }
370 out:
371         mutex_unlock(&tps->lock);
372         return ret;
373 }
374 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
375
376 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
377                 uint8_t mask)
378 {
379         struct tps80031 *tps80031 = dev_get_drvdata(dev);
380         struct tps80031_client *tps = &tps80031->tps_clients[sid];
381         uint8_t reg_val;
382         int ret = 0;
383
384         mutex_lock(&tps->lock);
385
386         ret = __tps80031_read(tps->client, reg, &reg_val);
387         if (ret)
388                 goto out;
389
390         if ((reg_val & mask) != val) {
391                 reg_val = (reg_val & ~mask) | (val & mask);
392                 ret = __tps80031_write(tps->client, reg, reg_val);
393         }
394 out:
395         mutex_unlock(&tps->lock);
396         return ret;
397 }
398 EXPORT_SYMBOL_GPL(tps80031_update);
399
400 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
401                           uint8_t mask)
402 {
403         struct tps80031 *tps80031 = dev_get_drvdata(dev);
404         struct tps80031_client *tps = &tps80031->tps_clients[sid];
405         uint8_t reg_val;
406         int ret = 0;
407
408         mutex_lock(&tps->lock);
409
410         ret = __tps80031_read(tps->client, reg, &reg_val);
411         if (ret)
412                 goto out;
413
414         reg_val = (reg_val & ~mask) | (val & mask);
415         ret = __tps80031_write(tps->client, reg, reg_val);
416
417 out:
418         mutex_unlock(&tps->lock);
419         return ret;
420 }
421 EXPORT_SYMBOL_GPL(tps80031_force_update);
422
423 int tps80031_ext_power_req_config(struct device *dev,
424                 unsigned long ext_ctrl_flag, int preq_bit,
425                 int state_reg_add, int trans_reg_add)
426 {
427         u8 res_ass_reg = 0;
428         int preq_mask_bit = 0;
429         int ret;
430
431         if (!(ext_ctrl_flag & EXT_PWR_REQ))
432                 return 0;
433
434         if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ1) {
435                 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
436                 preq_mask_bit = 5;
437         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ2) {
438                 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
439                 preq_mask_bit = 6;
440         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ3) {
441                 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
442                 preq_mask_bit = 7;
443         }
444
445         /* Configure REQ_ASS registers */
446         ret = tps80031_set_bits(dev, SLAVE_ID1, res_ass_reg,
447                                         BIT(preq_bit & 0x7));
448         if (ret < 0) {
449                 dev_err(dev, "%s() Not able to set bit %d of "
450                         "reg %d error %d\n",
451                         __func__, preq_bit, res_ass_reg, ret);
452                 return ret;
453         }
454
455         /* Unmask the PREQ */
456         ret = tps80031_clr_bits(dev, SLAVE_ID1,
457                         TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
458         if (ret < 0) {
459                 dev_err(dev, "%s() Not able to clear bit %d of "
460                         "reg %d error %d\n",
461                          __func__, preq_mask_bit,
462                         TPS80031_PHOENIX_MSK_TRANSITION, ret);
463                 return ret;
464         }
465
466         /* Switch regulator control to resource now */
467         if (ext_ctrl_flag & (PWR_REQ_INPUT_PREQ2 | PWR_REQ_INPUT_PREQ3)) {
468                 ret = tps80031_update(dev, SLAVE_ID1, state_reg_add, 0x0,
469                                                 STATE_MASK);
470                 if (ret < 0)
471                         dev_err(dev, "%s() Error in writing the STATE "
472                                 "register %d error %d\n", __func__,
473                                 state_reg_add, ret);
474         } else {
475                 ret = tps80031_update(dev, SLAVE_ID1, trans_reg_add,
476                                 TRANS_SLEEP_OFF, TRANS_SLEEP_MASK);
477                 if (ret < 0)
478                         dev_err(dev, "%s() Error in writing the TRANS "
479                                 "register %d error %d\n", __func__,
480                                 trans_reg_add, ret);
481         }
482         return ret;
483 }
484 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
485
486 unsigned long tps80031_get_chip_info(struct device *dev)
487 {
488         struct tps80031 *tps80031 = dev_get_drvdata(dev);
489         return tps80031->chip_info;
490 }
491 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
492
493 int tps80031_get_pmu_version(struct device *dev)
494 {
495         struct tps80031 *tps80031 = dev_get_drvdata(dev);
496         return tps80031->es_version;
497 }
498 EXPORT_SYMBOL_GPL(tps80031_get_pmu_version);
499
500 static struct tps80031 *tps80031_dev;
501 int tps80031_power_off(void)
502 {
503         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
504
505         if (!tps->client)
506                 return -EINVAL;
507         dev_info(&tps->client->dev, "switching off PMU\n");
508         return __tps80031_write(tps->client, TPS80031_PHOENIX_DEV_ON, DEVOFF);
509 }
510
511 static void tps80031_init_ext_control(struct tps80031 *tps80031,
512                         struct tps80031_platform_data *pdata) {
513         int ret;
514         int i;
515
516         /* Clear all external control for this rail */
517         for (i = 0; i < 9; ++i) {
518                 tps80031_write(tps80031->dev, SLAVE_ID1,
519                                 TPS80031_PREQ1_RES_ASS_A + i, 0);
520                 if (ret < 0)
521                         dev_err(tps80031->dev, "%s() Error in clearing "
522                                 "register %02x\n", __func__,
523                                 TPS80031_PREQ1_RES_ASS_A + i);
524         }
525
526         /* Mask the PREQ */
527         ret = tps80031_set_bits(tps80031->dev, SLAVE_ID1,
528                         TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
529         if (ret < 0)
530                 dev_err(tps80031->dev, "%s() Not able to mask register "
531                         "0x%02x\n", __func__, TPS80031_PHOENIX_MSK_TRANSITION);
532 }
533
534 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
535 {
536         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
537         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
538         uint8_t state;
539         uint8_t trans;
540         int ret;
541
542         ret = __tps80031_read(tps->client,
543                         pmc_ext_control_base[offset] +
544                                 EXT_CONTROL_CFG_STATE, &state);
545         if (ret)
546                 return ret;
547
548         if (state != 0) {
549                 ret = __tps80031_read(tps->client,
550                                 pmc_ext_control_base[offset] +
551                                         EXT_CONTROL_CFG_TRANS, &trans);
552                 if (ret)
553                         return ret;
554                 return trans & 0x1;
555         }
556         return 0;
557 }
558
559 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
560                         int value)
561 {
562         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
563
564         tps80031_update(tps80031->dev, SLAVE_ID1,
565                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
566                         value, 0x1);
567 }
568
569 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
570 {
571         return -EIO;
572 }
573
574 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
575                                 int value)
576 {
577         tps80031_gpio_set(gc, offset, value);
578         return 0;
579 }
580
581 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
582 {
583         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
584         int ret;
585
586         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
587                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
588                                                 STATE_ON, STATE_MASK);
589         if (ret)
590                 return ret;
591
592         return tps80031_write(tps80031->dev, SLAVE_ID1,
593                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
594 }
595
596 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
597 {
598         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
599         tps80031_update(tps80031->dev, SLAVE_ID1,
600                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
601                                                 STATE_OFF, STATE_MASK);
602 }
603
604 static void tps80031_gpio_init(struct tps80031 *tps80031,
605                         struct tps80031_platform_data *pdata)
606 {
607         int ret;
608         int gpio_base = pdata->gpio_base;
609         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
610         struct tps80031_gpio_init_data *gpio_init_data = pdata->gpio_init_data;
611         int data_size = pdata->gpio_init_data_size;
612         static int preq_bit_pos[TPS80031_GPIO_NR] = {16, 17, 18};
613         int base_add;
614         int i;
615
616         if (gpio_base <= 0)
617                 return;
618
619         /* Configure the external request mode */
620         for (i = 0; i < data_size; ++i) {
621                 struct tps80031_gpio_init_data *gpio_pd = &gpio_init_data[i];
622                 base_add = pmc_ext_control_base[gpio_pd->gpio_nr];
623
624                 if (gpio_pd->ext_ctrl_flag & EXT_PWR_REQ) {
625                         ret = tps80031_ext_power_req_config(tps80031->dev,
626                                 gpio_pd->ext_ctrl_flag,
627                                 preq_bit_pos[gpio_pd->gpio_nr],
628                                 base_add + EXT_CONTROL_CFG_STATE,
629                                 base_add + EXT_CONTROL_CFG_TRANS);
630                         if (ret < 0)
631                                 dev_warn(tps80031->dev, "Ext pwrreq GPIO "
632                                         "sleep control fails\n");
633                 }
634
635                 if (gpio_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
636                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
637                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
638                         if (ret < 0)
639                                 dev_warn(tps80031->dev, "GPIO OFF on sleep "
640                                         "control fails\n");
641                 }
642
643                 if (gpio_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
644                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
645                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
646                         if (ret < 0)
647                                 dev_warn(tps80031->dev, "GPIO ON on sleep "
648                                         "control fails\n");
649                 }
650         }
651
652         tps80031->gpio.owner            = THIS_MODULE;
653         tps80031->gpio.label            = tps->client->name;
654         tps80031->gpio.dev              = tps80031->dev;
655         tps80031->gpio.base             = gpio_base;
656         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
657         tps80031->gpio.can_sleep        = 1;
658
659         tps80031->gpio.request          = tps80031_gpio_enable;
660         tps80031->gpio.free             = tps80031_gpio_disable;
661         tps80031->gpio.direction_input  = tps80031_gpio_input;
662         tps80031->gpio.direction_output = tps80031_gpio_output;
663         tps80031->gpio.set              = tps80031_gpio_set;
664         tps80031->gpio.get              = tps80031_gpio_get;
665
666         ret = gpiochip_add(&tps80031->gpio);
667         if (ret)
668                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
669 }
670
671 static int __remove_subdev(struct device *dev, void *unused)
672 {
673         platform_device_unregister(to_platform_device(dev));
674         return 0;
675 }
676
677 static int tps80031_remove_subdevs(struct tps80031 *tps80031)
678 {
679         return device_for_each_child(tps80031->dev, NULL, __remove_subdev);
680 }
681
682 static void tps80031_irq_lock(struct irq_data *data)
683 {
684         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
685
686         mutex_lock(&tps80031->irq_lock);
687 }
688
689 static void tps80031_irq_enable(struct irq_data *data)
690 {
691         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
692         unsigned int __irq = data->irq - tps80031->irq_base;
693         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
694
695         if (irq_data->is_sec_int) {
696                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
697                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
698                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
699                 tps80031->irq_en |= (1 << irq_data->parent_int);
700         } else
701                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
702
703         tps80031->irq_en |= (1 << __irq);
704 }
705
706 static void tps80031_irq_disable(struct irq_data *data)
707 {
708         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
709
710         unsigned int __irq = data->irq - tps80031->irq_base;
711         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
712
713         if (irq_data->is_sec_int) {
714                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
715                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
716                 if (!tps80031->cont_int_en) {
717                         tps80031->mask_reg[irq_data->mask_reg] |=
718                                                 (1 << irq_data->mask_mask);
719                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
720                 }
721                 tps80031->irq_en &= ~(1 << __irq);
722         } else
723                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
724
725         tps80031->irq_en &= ~(1 << __irq);
726 }
727
728 static void tps80031_irq_sync_unlock(struct irq_data *data)
729 {
730         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
731         int i;
732
733         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
734                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
735                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
736                                                 TPS80031_INT_MSK_LINE_A + i,
737                                                 tps80031->mask_reg[i])))
738                                 if (!WARN_ON(tps80031_write(tps80031->dev,
739                                                 SLAVE_ID2,
740                                                 TPS80031_INT_MSK_STS_A + i,
741                                                 tps80031->mask_reg[i])))
742                                         tps80031->mask_cache[i] =
743                                                         tps80031->mask_reg[i];
744                 }
745         }
746
747         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
748                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
749                                 TPS80031_CONTROLLER_INT_MASK,
750                                 tps80031->cont_int_mask_reg)))
751                         tps80031->cont_int_mask_cache =
752                                                 tps80031->cont_int_mask_reg;
753         }
754
755         mutex_unlock(&tps80031->irq_lock);
756 }
757
758 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
759 {
760         struct tps80031 *tps80031 = data;
761         int ret = 0;
762         int i;
763         u8 cont_sts;
764         u8 org_sts;
765         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
766                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
767                                         __func__, irq);
768                 return IRQ_NONE;
769         }
770
771         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
772                         TPS80031_CONTROLLER_STAT1, &org_sts);
773         if (ret < 0) {
774                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
775                                 "status %d\n", __func__, ret);
776                 return IRQ_NONE;
777         }
778
779         /* Get change from last interrupt and mask for interested interrupt
780          * for charge control interrupt */
781         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
782         tps80031->prev_cont_stat1 = org_sts;
783         /* Clear watchdog timer state */
784         tps80031->prev_cont_stat1 &= ~(1 << 4);
785         cont_sts &= 0x5F;
786
787         for (i = 0; i < 8; ++i) {
788                 if (!controller_stat1_irq_nr[i])
789                         continue;
790
791                 if ((cont_sts & BIT(i)) &&
792                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
793                         handle_nested_irq(tps80031->irq_base +
794                                                 controller_stat1_irq_nr[i]);
795                 cont_sts &= ~BIT(i);
796         }
797         return IRQ_HANDLED;
798 }
799
800 static irqreturn_t tps80031_irq(int irq, void *data)
801 {
802         struct tps80031 *tps80031 = data;
803         int ret = 0;
804         u8 tmp[3];
805         u32 acks;
806         int i;
807
808         for (i = 0; i < 3; i++) {
809                 ret = tps80031_read(tps80031->dev, SLAVE_ID2,
810                         TPS80031_INT_STS_A + i, &tmp[i]);
811                 if (ret < 0) {
812                         dev_err(tps80031->dev, "failed to read interrupt "
813                                                         "status\n");
814                         return IRQ_NONE;
815                 }
816                 if (tmp[i]) {
817                         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
818                                         TPS80031_INT_STS_A + i, tmp[i]);
819                         if (ret < 0) {
820                                 dev_err(tps80031->dev, "failed to write "
821                                                         "interrupt status\n");
822                                 return IRQ_NONE;
823                         }
824                 }
825         }
826         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
827         while (acks) {
828                 i = __ffs(acks);
829                 if (tps80031->irq_en & (1 << i))
830                         handle_nested_irq(tps80031->irq_base + i);
831                 acks &= ~(1 << i);
832         }
833         return IRQ_HANDLED;
834 }
835
836 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
837                                 int irq_base)
838 {
839         int i, ret;
840
841         if (!irq_base) {
842                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
843                 return -EINVAL;
844         }
845
846         mutex_init(&tps80031->irq_lock);
847
848         for (i = 0; i < 3; i++) {
849                 tps80031->mask_reg[i] = 0xFF;
850                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
851                 tps80031_write(tps80031->dev, SLAVE_ID2,
852                                         TPS80031_INT_MSK_LINE_A + i,
853                                         tps80031->mask_cache[i]);
854                 tps80031_write(tps80031->dev, SLAVE_ID2,
855                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
856                 tps80031_write(tps80031->dev, SLAVE_ID2,
857                                         TPS80031_INT_STS_A + i, 0xFF);
858         }
859
860         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
861                                 TPS80031_CONTROLLER_INT_MASK,
862                                 &tps80031->cont_int_mask_reg);
863         if (ret < 0) {
864                 dev_err(tps80031->dev, "Error in reading the controller_mask "
865                                         "register %d\n", ret);
866                 return ret;
867         }
868
869         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
870         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
871         tps80031->cont_int_en = 0;
872         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
873                                 TPS80031_CONTROLLER_INT_MASK,
874                                 tps80031->cont_int_mask_reg);
875         if (ret < 0) {
876                 dev_err(tps80031->dev, "Error in writing the controller_mask "
877                                         "register %d\n", ret);
878                 return ret;
879         }
880
881         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
882                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
883         if (ret < 0) {
884                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
885                                 "status %d\n", __func__, ret);
886                 return ret;
887         }
888
889         /* Clear watch dog interrupt status in status */
890         tps80031->prev_cont_stat1 &= ~(1 << 4);
891
892         tps80031->irq_base = irq_base;
893
894         tps80031->irq_chip.name = "tps80031";
895         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
896         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
897         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
898         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
899
900         for (i = 0; i < TPS80031_INT_NR; i++) {
901                 int __irq = i + tps80031->irq_base;
902                 irq_set_chip_data(__irq, tps80031);
903                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
904                                          handle_simple_irq);
905                 irq_set_nested_thread(__irq, 1);
906 #ifdef CONFIG_ARM
907                 set_irq_flags(__irq, IRQF_VALID);
908 #endif
909         }
910
911         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
912                                 "tps80031", tps80031);
913         /* register the isr for the secondary interrupt */
914         if (!ret)
915                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
916                                 NULL, tps80031_charge_control_irq,
917                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
918         if (!ret) {
919
920                 device_init_wakeup(tps80031->dev, 1);
921                 enable_irq_wake(irq);
922         }
923
924         return ret;
925 }
926
927 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
928 {
929         int ret;
930         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
931                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
932         if (!ret)
933                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
934                                 base_add + EXT_CONTROL_CFG_TRANS,
935                                 STATE_ON, STATE_MASK);
936         if (ret < 0)
937                 dev_err(tps80031->dev, "Error in updating clock register\n");
938 }
939
940 static void tps80031_clk32k_init(struct tps80031 *tps80031,
941                         struct tps80031_platform_data *pdata)
942 {
943         int ret;
944         struct tps80031_clk32k_init_data *clk32_idata = pdata->clk32k_init_data;
945         int data_size = pdata->clk32k_init_data_size;
946         static int clk32k_preq_bit_pos[TPS80031_CLOCK32K_NR] = {-1, 20, 19};
947         int base_add;
948         int i;
949
950         if (!clk32_idata || !data_size)
951                 return;
952
953         /* Configure the external request mode */
954         for (i = 0; i < data_size; ++i) {
955                 struct tps80031_clk32k_init_data *clk32_pd =  &clk32_idata[i];
956                 base_add = pmc_clk32k_control_base[clk32_pd->clk32k_nr];
957                 if (clk32_pd->enable)
958                         tps80031_clk32k_enable(tps80031, base_add);
959
960                 if ((clk32_pd->ext_ctrl_flag & EXT_PWR_REQ) &&
961                          (clk32k_preq_bit_pos[clk32_pd->clk32k_nr] != -1)) {
962                         ret = tps80031_ext_power_req_config(tps80031->dev,
963                                 clk32_pd->ext_ctrl_flag,
964                                 clk32k_preq_bit_pos[clk32_pd->clk32k_nr],
965                                 base_add + EXT_CONTROL_CFG_STATE,
966                                 base_add + EXT_CONTROL_CFG_TRANS);
967                         if (ret < 0)
968                                 dev_warn(tps80031->dev, "Clk32 ext control "
969                                         "fails\n");
970                 }
971
972                 if (clk32_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
973                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
974                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
975                         if (ret < 0)
976                                 dev_warn(tps80031->dev, "clk OFF on sleep "
977                                         "control fails\n");
978                 }
979
980                 if (clk32_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
981                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
982                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
983                         if (ret < 0)
984                                 dev_warn(tps80031->dev, "clk ON sleep "
985                                         "control fails\n");
986                 }
987         }
988 }
989
990 static int __devinit tps80031_add_subdevs(struct tps80031 *tps80031,
991                                           struct tps80031_platform_data *pdata)
992 {
993         struct tps80031_subdev_info *subdev;
994         struct platform_device *pdev;
995         int i, ret = 0;
996
997         for (i = 0; i < pdata->num_subdevs; i++) {
998                 subdev = &pdata->subdevs[i];
999
1000                 pdev = platform_device_alloc(subdev->name, subdev->id);
1001
1002                 pdev->dev.parent = tps80031->dev;
1003                 pdev->dev.platform_data = subdev->platform_data;
1004
1005                 ret = platform_device_add(pdev);
1006                 if (ret)
1007                         goto failed;
1008         }
1009         return 0;
1010
1011 failed:
1012         tps80031_remove_subdevs(tps80031);
1013         return ret;
1014 }
1015
1016 #ifdef CONFIG_DEBUG_FS
1017 #include <linux/debugfs.h>
1018 #include <linux/seq_file.h>
1019 static void print_regs(const char *header, struct seq_file *s,
1020                 int sid, int start_offset, int end_offset)
1021 {
1022         struct tps80031 *tps80031 = s->private;
1023         struct tps80031_client *tps = &tps80031->tps_clients[sid];
1024         uint8_t reg_val;
1025         int i;
1026         int ret;
1027
1028         seq_printf(s, "%s\n", header);
1029         for (i = start_offset; i <= end_offset; ++i) {
1030                 ret = __tps80031_read(tps->client, i, &reg_val);
1031                 if (ret >= 0)
1032                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
1033                                                 tps->client->addr, i, reg_val);
1034         }
1035         seq_printf(s, "------------------\n");
1036 }
1037
1038 static int dbg_tps_show(struct seq_file *s, void *unused)
1039 {
1040         seq_printf(s, "TPS80031 Registers\n");
1041         seq_printf(s, "------------------\n");
1042         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
1043         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
1044         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
1045         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
1046         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
1047         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
1048         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
1049         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
1050         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
1051         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
1052         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
1053         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
1054         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
1055         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
1056         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
1057         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
1058         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
1059         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
1060         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
1061         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
1062         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
1063         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
1064         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
1065         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
1066         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
1067         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
1068         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
1069         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
1070         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
1071         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
1072         print_regs("PMC MISC Regs",  s, SLAVE_ID1, 0xE0, 0xEF);
1073         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
1074         print_regs("VERNUM Regs",    s, SLAVE_ID3, 0x87, 0x87);
1075         print_regs("EEPROM Regs",    s, SLAVE_ID3, 0xDF, 0xDF);
1076         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
1077         return 0;
1078 }
1079
1080 static int dbg_tps_open(struct inode *inode, struct file *file)
1081 {
1082         return single_open(file, dbg_tps_show, inode->i_private);
1083 }
1084
1085 static const struct file_operations debug_fops = {
1086         .open           = dbg_tps_open,
1087         .read           = seq_read,
1088         .llseek         = seq_lseek,
1089         .release        = single_release,
1090 };
1091
1092 static void __init tps80031_debuginit(struct tps80031 *tps)
1093 {
1094         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
1095                         tps, &debug_fops);
1096 }
1097 #else
1098 static void __init tps80031_debuginit(struct tps80031 *tpsi)
1099 {
1100         return;
1101 }
1102 #endif
1103
1104 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
1105 {
1106         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1107         int i;
1108
1109         if (client->irq)
1110                 free_irq(client->irq, tps80031);
1111
1112         if (tps80031->gpio.owner != NULL)
1113                 if (gpiochip_remove(&tps80031->gpio) < 0)
1114                         dev_err(&client->dev, "Error in removing the gpio driver\n");
1115
1116         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1117                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1118                 if (tps->client && tps->client != client)
1119                         i2c_unregister_device(tps->client);
1120                 tps80031->tps_clients[i].client = NULL;
1121                 mutex_destroy(&tps->lock);
1122         }
1123
1124         kfree(tps80031);
1125         return 0;
1126 }
1127
1128 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
1129                                         const struct i2c_device_id *id)
1130 {
1131         struct tps80031_platform_data *pdata = client->dev.platform_data;
1132         struct tps80031 *tps80031;
1133         struct tps80031_client *tps;
1134         int ret;
1135         int jtag_ver;
1136         int ep_ver;
1137         int i;
1138
1139         if (!pdata) {
1140                 dev_err(&client->dev, "tps80031 requires platform data\n");
1141                 return -ENOTSUPP;
1142         }
1143
1144         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
1145         if (jtag_ver < 0) {
1146                 dev_err(&client->dev, "Silicon version number read"
1147                                 " failed: %d\n", jtag_ver);
1148                 return -EIO;
1149         }
1150
1151         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
1152         if (ep_ver < 0) {
1153                 dev_err(&client->dev, "Silicon eeprom version read"
1154                                 " failed: %d\n", ep_ver);
1155                 return -EIO;
1156         }
1157
1158         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
1159                                                 jtag_ver, ep_ver);
1160
1161         tps80031 = kzalloc(sizeof(struct tps80031), GFP_KERNEL);
1162         if (tps80031 == NULL)
1163                 return -ENOMEM;
1164
1165         tps80031->es_version = jtag_ver;
1166         tps80031->dev = &client->dev;
1167         i2c_set_clientdata(client, tps80031);
1168         tps80031->chip_info = id->driver_data;
1169
1170         /* Set up slaves */
1171         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
1172         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
1173         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
1174         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
1175         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1176                 tps = &tps80031->tps_clients[i];
1177                 if (tps->addr == client->addr)
1178                         tps->client = client;
1179                 else
1180                         tps->client = i2c_new_dummy(client->adapter,
1181                                                 tps->addr);
1182                 if (!tps->client) {
1183                         dev_err(&client->dev, "can't attach client %d\n", i);
1184                         ret = -ENOMEM;
1185                         goto fail;
1186                 }
1187                 i2c_set_clientdata(tps->client, tps80031);
1188                 mutex_init(&tps->lock);
1189         }
1190
1191         if (client->irq) {
1192                 ret = tps80031_irq_init(tps80031, client->irq,
1193                                         pdata->irq_base);
1194                 if (ret) {
1195                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1196                         goto fail;
1197                 }
1198         }
1199         tps80031_init_ext_control(tps80031, pdata);
1200
1201         ret = tps80031_add_subdevs(tps80031, pdata);
1202         if (ret) {
1203                 dev_err(&client->dev, "add devices failed: %d\n", ret);
1204                 goto fail;
1205         }
1206
1207         tps80031_gpio_init(tps80031, pdata);
1208
1209         tps80031_clk32k_init(tps80031, pdata);
1210
1211         tps80031_debuginit(tps80031);
1212
1213         tps80031_dev = tps80031;
1214
1215         return 0;
1216
1217 fail:
1218         tps80031_i2c_remove(client);
1219         return ret;
1220 }
1221
1222 #ifdef CONFIG_PM
1223 static int tps80031_i2c_suspend(struct i2c_client *client, pm_message_t state)
1224 {
1225         if (client->irq)
1226                 disable_irq(client->irq);
1227         return 0;
1228 }
1229
1230 static int tps80031_i2c_resume(struct i2c_client *client)
1231 {
1232         if (client->irq)
1233                 enable_irq(client->irq);
1234         return 0;
1235 }
1236 #endif
1237
1238
1239 static const struct i2c_device_id tps80031_id_table[] = {
1240         { "tps80031", TPS80031 },
1241         { "tps80032", TPS80032 },
1242 };
1243 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1244
1245 static struct i2c_driver tps80031_driver = {
1246         .driver = {
1247                 .name   = "tps80031",
1248                 .owner  = THIS_MODULE,
1249         },
1250         .probe          = tps80031_i2c_probe,
1251         .remove         = __devexit_p(tps80031_i2c_remove),
1252 #ifdef CONFIG_PM
1253         .suspend        = tps80031_i2c_suspend,
1254         .resume         = tps80031_i2c_resume,
1255 #endif
1256         .id_table       = tps80031_id_table,
1257 };
1258
1259 static int __init tps80031_init(void)
1260 {
1261         return i2c_add_driver(&tps80031_driver);
1262 }
1263 subsys_initcall(tps80031_init);
1264
1265 static void __exit tps80031_exit(void)
1266 {
1267         i2c_del_driver(&tps80031_driver);
1268 }
1269 module_exit(tps80031_exit);
1270
1271 MODULE_DESCRIPTION("TPS80031 core driver");
1272 MODULE_LICENSE("GPL");