regulator: tps80031: Check configuraton for LDO2-Track mode
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32
33 #include <linux/mfd/core.h>
34 #include <linux/mfd/tps80031.h>
35
36 /* interrupt related registers */
37 #define TPS80031_INT_STS_A              0xD0
38 #define TPS80031_INT_STS_B              0xD1
39 #define TPS80031_INT_STS_C              0xD2
40 #define TPS80031_INT_MSK_LINE_A         0xD3
41 #define TPS80031_INT_MSK_LINE_B         0xD4
42 #define TPS80031_INT_MSK_LINE_C         0xD5
43 #define TPS80031_INT_MSK_STS_A          0xD6
44 #define TPS80031_INT_MSK_STS_B          0xD7
45 #define TPS80031_INT_MSK_STS_C          0xD8
46
47 #define TPS80031_CONTROLLER_STAT1               0xE3
48 #define CONTROLLER_STAT1_BAT_TEMP               0
49 #define CONTROLLER_STAT1_BAT_REMOVED            1
50 #define CONTROLLER_STAT1_VBUS_DET               2
51 #define CONTROLLER_STAT1_VAC_DET                3
52 #define CONTROLLER_STAT1_FAULT_WDG              4
53 #define CONTROLLER_STAT1_LINCH_GATED            6
54
55 #define TPS80031_CONTROLLER_INT_MASK            0xE0
56 #define CONTROLLER_INT_MASK_MVAC_DET            0
57 #define CONTROLLER_INT_MASK_MVBUS_DET           1
58 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
59 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
60 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
61 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
62
63 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
64
65 /* Version number related register */
66 #define TPS80031_JTAGVERNUM             0x87
67 /* Epprom version */
68 #define TPS80031_EPROM_REV              0xDF
69
70 /* External control register */
71 #define REGEN1_BASE_ADD         0xAE
72 #define REGEN2_BASE_ADD         0xB1
73 #define SYSEN_BASE_ADD          0xB4
74
75 /* device control registers */
76 #define TPS80031_PHOENIX_DEV_ON 0x25
77 #define DEVOFF  1
78
79 #define CLK32KAO_BASE_ADD       0xBA
80 #define CLK32KG_BASE_ADD        0xBD
81 #define CLK32KAUDIO_BASE_ADD    0xC0
82
83 #define EXT_CONTROL_CFG_TRANS 0
84 #define EXT_CONTROL_CFG_STATE 1
85
86 #define STATE_OFF       0x00
87 #define STATE_ON        0x01
88 #define STATE_MASK      0x03
89
90 #define TRANS_SLEEP_OFF         0x00
91 #define TRANS_SLEEP_ON          0x04
92 #define TRANS_SLEEP_MASK        0x0C
93
94 #define TPS_NUM_SLAVES  4
95 #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \
96                 PWR_REQ_INPUT_PREQ3)
97 #define TPS80031_PREQ1_RES_ASS_A        0xD7
98 #define TPS80031_PREQ2_RES_ASS_A        0xDA
99 #define TPS80031_PREQ3_RES_ASS_A        0xDD
100 #define TPS80031_PHOENIX_MSK_TRANSITION 0x20
101
102
103 static u8 pmc_ext_control_base[] = {
104         REGEN1_BASE_ADD,
105         REGEN2_BASE_ADD,
106         SYSEN_BASE_ADD,
107 };
108
109 struct tps80031_irq_data {
110         u8      mask_reg;
111         u8      mask_mask;
112         u8      is_sec_int;
113         u8      parent_int;
114         u8      mask_sec_int_reg;
115         u8      int_mask_bit;
116         u8      int_sec_sts_reg;
117         u8      int_sts_bit;
118 };
119
120 #define TPS80031_IRQ(_reg, _mask)       \
121         {                                                       \
122                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
123                                 TPS80031_INT_MSK_LINE_A,        \
124                 .mask_mask = (_mask),                           \
125         }
126
127 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
128         {                                                               \
129                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
130                                 TPS80031_INT_MSK_LINE_A,                \
131                 .mask_mask = (_mask),                                   \
132                 .is_sec_int = true,                                     \
133                 .parent_int = TPS80031_INT_##_pint,                     \
134                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
135                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
136                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
137                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
138         }
139
140 static const struct tps80031_irq_data tps80031_irqs[] = {
141
142         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
143         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
144         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
145         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
146         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
147         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
148         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
149         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
150         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
151         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
152         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
153         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
154         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
155         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
156         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
157         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
158         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
159         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
160         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
161         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
162         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
163         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
164         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
165         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
166         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
167                                                 MBAT_TEMP,      BAT_TEMP),
168         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
169                                                 MBAT_REMOVED,   BAT_REMOVED),
170         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
171                                                 MVBUS_DET,      VBUS_DET),
172         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
173                                                 MVAC_DET,       VAC_DET),
174         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
175                                                 MFAULT_WDG,     FAULT_WDG),
176         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
177                                                 MLINCH_GATED,   LINCH_GATED),
178 };
179
180 static const int controller_stat1_irq_nr[] = {
181         TPS80031_INT_BAT_TEMP_OVRANGE,
182         TPS80031_INT_BAT_REMOVED,
183         TPS80031_INT_VBUS_DET,
184         TPS80031_INT_VAC_DET,
185         TPS80031_INT_FAULT_WDG,
186         0,
187         TPS80031_INT_LINCH_GATED,
188         0
189 };
190
191 /* Structure for TPS80031 Slaves */
192 struct tps80031_client {
193         struct i2c_client *client;
194         struct mutex lock;
195         u8 addr;
196 };
197
198 struct tps80031 {
199         struct device           *dev;
200         unsigned long           chip_info;
201         int                     es_version;
202
203         struct gpio_chip        gpio;
204         struct irq_chip         irq_chip;
205         struct mutex            irq_lock;
206         int                     irq_base;
207         u32                     irq_en;
208         u8                      mask_cache[3];
209         u8                      mask_reg[3];
210         u8                      cont_int_mask_reg;
211         u8                      cont_int_mask_cache;
212         u8                      cont_int_en;
213         u8                      prev_cont_stat1;
214         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
215 };
216
217 static inline int __tps80031_read(struct i2c_client *client,
218                                   int reg, uint8_t *val)
219 {
220         int ret;
221
222         ret = i2c_smbus_read_byte_data(client, reg);
223         if (ret < 0) {
224                 dev_err(&client->dev,
225                         "failed reading from addr 0x%02x, reg 0x%02x\n",
226                         client->addr, reg);
227                 return ret;
228         }
229
230         *val = (uint8_t)ret;
231
232         return 0;
233 }
234
235 static inline int __tps80031_reads(struct i2c_client *client, int reg,
236                                 int len, uint8_t *val)
237 {
238         int ret;
239
240         ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
241         if (ret < 0) {
242                 dev_err(&client->dev,
243                         "failed reading from addr 0x%02x, reg   0x%02x\n",
244                          client->addr, reg);
245                 return ret;
246         }
247
248         return 0;
249 }
250
251 static inline int __tps80031_write(struct i2c_client *client,
252                                  int reg, uint8_t val)
253 {
254         int ret;
255         ret = i2c_smbus_write_byte_data(client, reg, val);
256         if (ret < 0) {
257                 dev_err(&client->dev,
258                         "failed writing 0x%02x to 0x%02x\n", val, reg);
259                 return ret;
260         }
261
262         return 0;
263 }
264
265 static inline int __tps80031_writes(struct i2c_client *client, int reg,
266                                   int len, uint8_t *val)
267 {
268         int ret;
269
270         ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
271         if (ret < 0) {
272                 dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
273                 return ret;
274         }
275
276         return 0;
277 }
278
279 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
280 {
281         struct tps80031 *tps80031 = dev_get_drvdata(dev);
282         struct tps80031_client *tps = &tps80031->tps_clients[sid];
283         int ret;
284
285         mutex_lock(&tps->lock);
286         ret = __tps80031_write(tps->client, reg, val);
287         mutex_unlock(&tps->lock);
288
289         return ret;
290 }
291 EXPORT_SYMBOL_GPL(tps80031_write);
292
293 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
294 {
295         struct tps80031 *tps80031 = dev_get_drvdata(dev);
296         struct tps80031_client *tps = &tps80031->tps_clients[sid];
297         int ret;
298
299         mutex_lock(&tps->lock);
300         ret = __tps80031_writes(tps->client, reg, len, val);
301         mutex_unlock(&tps->lock);
302
303         return ret;
304 }
305 EXPORT_SYMBOL_GPL(tps80031_writes);
306
307 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
308 {
309         struct tps80031 *tps80031 = dev_get_drvdata(dev);
310         struct tps80031_client *tps = &tps80031->tps_clients[sid];
311
312         return __tps80031_read(tps->client, reg, val);
313 }
314 EXPORT_SYMBOL_GPL(tps80031_read);
315
316 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
317 {
318         struct tps80031 *tps80031 = dev_get_drvdata(dev);
319         struct tps80031_client *tps = &tps80031->tps_clients[sid];
320
321         return __tps80031_reads(tps->client, reg, len, val);
322 }
323 EXPORT_SYMBOL_GPL(tps80031_reads);
324
325 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
326 {
327         struct tps80031 *tps80031 = dev_get_drvdata(dev);
328         struct tps80031_client *tps = &tps80031->tps_clients[sid];
329         uint8_t reg_val;
330         int ret = 0;
331
332         mutex_lock(&tps->lock);
333
334         ret = __tps80031_read(tps->client, reg, &reg_val);
335         if (ret)
336                 goto out;
337
338         if ((reg_val & bit_mask) != bit_mask) {
339                 reg_val |= bit_mask;
340                 ret = __tps80031_write(tps->client, reg, reg_val);
341         }
342 out:
343         mutex_unlock(&tps->lock);
344         return ret;
345 }
346 EXPORT_SYMBOL_GPL(tps80031_set_bits);
347
348 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
349 {
350         struct tps80031 *tps80031 = dev_get_drvdata(dev);
351         struct tps80031_client *tps = &tps80031->tps_clients[sid];
352         uint8_t reg_val;
353         int ret = 0;
354
355         mutex_lock(&tps->lock);
356
357         ret = __tps80031_read(tps->client, reg, &reg_val);
358         if (ret)
359                 goto out;
360
361         if (reg_val & bit_mask) {
362                 reg_val &= ~bit_mask;
363                 ret = __tps80031_write(tps->client, reg, reg_val);
364         }
365 out:
366         mutex_unlock(&tps->lock);
367         return ret;
368 }
369 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
370
371 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
372                 uint8_t mask)
373 {
374         struct tps80031 *tps80031 = dev_get_drvdata(dev);
375         struct tps80031_client *tps = &tps80031->tps_clients[sid];
376         uint8_t reg_val;
377         int ret = 0;
378
379         mutex_lock(&tps->lock);
380
381         ret = __tps80031_read(tps->client, reg, &reg_val);
382         if (ret)
383                 goto out;
384
385         if ((reg_val & mask) != val) {
386                 reg_val = (reg_val & ~mask) | (val & mask);
387                 ret = __tps80031_write(tps->client, reg, reg_val);
388         }
389 out:
390         mutex_unlock(&tps->lock);
391         return ret;
392 }
393 EXPORT_SYMBOL_GPL(tps80031_update);
394
395 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
396                           uint8_t mask)
397 {
398         struct tps80031 *tps80031 = dev_get_drvdata(dev);
399         struct tps80031_client *tps = &tps80031->tps_clients[sid];
400         uint8_t reg_val;
401         int ret = 0;
402
403         mutex_lock(&tps->lock);
404
405         ret = __tps80031_read(tps->client, reg, &reg_val);
406         if (ret)
407                 goto out;
408
409         reg_val = (reg_val & ~mask) | (val & mask);
410         ret = __tps80031_write(tps->client, reg, reg_val);
411
412 out:
413         mutex_unlock(&tps->lock);
414         return ret;
415 }
416 EXPORT_SYMBOL_GPL(tps80031_force_update);
417
418 int tps80031_ext_power_req_config(struct device *dev,
419                 enum tps80031_ext_control ext_pwr_ctrl, int preq_bit,
420                 int state_reg_add, int trans_reg_add)
421 {
422         u8 res_ass_reg = 0;
423         int preq_mask_bit = 0;
424         int ret;
425
426         if (!(ext_pwr_ctrl & EXT_PWR_REQ))
427                 return 0;
428
429         if (ext_pwr_ctrl & PWR_REQ_INPUT_PREQ1) {
430                 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
431                 preq_mask_bit = 5;
432         } else if (ext_pwr_ctrl & PWR_REQ_INPUT_PREQ2) {
433                 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
434                 preq_mask_bit = 6;
435         } else if (ext_pwr_ctrl & PWR_REQ_INPUT_PREQ3) {
436                 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
437                 preq_mask_bit = 7;
438         }
439
440         /* Configure REQ_ASS registers */
441         ret = tps80031_set_bits(dev, SLAVE_ID1, res_ass_reg,
442                                         BIT(preq_bit & 0x7));
443         if (ret < 0) {
444                 dev_err(dev, "%s() Not able to set bit %d of "
445                         "reg %d error %d\n",
446                         __func__, preq_bit, res_ass_reg, ret);
447                 return ret;
448         }
449
450         /* Unmask the PREQ */
451         ret = tps80031_clr_bits(dev, SLAVE_ID1,
452                         TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
453         if (ret < 0) {
454                 dev_err(dev, "%s() Not able to clear bit %d of "
455                         "reg %d error %d\n",
456                          __func__, preq_mask_bit,
457                         TPS80031_PHOENIX_MSK_TRANSITION, ret);
458                 return ret;
459         }
460
461         /* Switch regulator control to resource now */
462         if (ext_pwr_ctrl &  (PWR_REQ_INPUT_PREQ2 | PWR_REQ_INPUT_PREQ3)) {
463                 ret = tps80031_update(dev, SLAVE_ID1, state_reg_add, 0x0,
464                                                 STATE_MASK);
465                 if (ret < 0)
466                         dev_err(dev, "%s() Error in writing the STATE "
467                                 "register %d error %d\n", __func__,
468                                 state_reg_add, ret);
469         } else {
470                 ret = tps80031_update(dev, SLAVE_ID1, trans_reg_add,
471                                 TRANS_SLEEP_OFF, TRANS_SLEEP_MASK);
472                 if (ret < 0)
473                         dev_err(dev, "%s() Error in writing the TRANS "
474                                 "register %d error %d\n", __func__,
475                                 trans_reg_add, ret);
476         }
477         return ret;
478 }
479 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
480
481 unsigned long tps80031_get_chip_info(struct device *dev)
482 {
483         struct tps80031 *tps80031 = dev_get_drvdata(dev);
484         return tps80031->chip_info;
485 }
486 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
487
488 int tps80031_get_pmu_version(struct device *dev)
489 {
490         struct tps80031 *tps80031 = dev_get_drvdata(dev);
491         return tps80031->es_version;
492 }
493 EXPORT_SYMBOL_GPL(tps80031_get_pmu_version);
494
495 static struct tps80031 *tps80031_dev;
496 int tps80031_power_off(void)
497 {
498         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
499
500         if (!tps->client)
501                 return -EINVAL;
502         dev_info(&tps->client->dev, "switching off PMU\n");
503         return __tps80031_write(tps->client, TPS80031_PHOENIX_DEV_ON, DEVOFF);
504 }
505
506 static void tps80031_init_ext_control(struct tps80031 *tps80031,
507                         struct tps80031_platform_data *pdata) {
508         int ret;
509         int i;
510
511         /* Clear all external control for this rail */
512         for (i = 0; i < 9; ++i) {
513                 tps80031_write(tps80031->dev, SLAVE_ID1,
514                                 TPS80031_PREQ1_RES_ASS_A + i, 0);
515                 if (ret < 0)
516                         dev_err(tps80031->dev, "%s() Error in clearing "
517                                 "register %02x\n", __func__,
518                                 TPS80031_PREQ1_RES_ASS_A + i);
519         }
520
521         /* Mask the PREQ */
522         ret = tps80031_set_bits(tps80031->dev, SLAVE_ID1,
523                         TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
524         if (ret < 0)
525                 dev_err(tps80031->dev, "%s() Not able to mask register "
526                         "0x%02x\n", __func__, TPS80031_PHOENIX_MSK_TRANSITION);
527 }
528
529 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
530 {
531         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
532         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
533         uint8_t state;
534         uint8_t trans;
535         int ret;
536
537         ret = __tps80031_read(tps->client,
538                         pmc_ext_control_base[offset] +
539                                 EXT_CONTROL_CFG_STATE, &state);
540         if (ret)
541                 return ret;
542
543         if (state != 0) {
544                 ret = __tps80031_read(tps->client,
545                                 pmc_ext_control_base[offset] +
546                                         EXT_CONTROL_CFG_TRANS, &trans);
547                 if (ret)
548                         return ret;
549                 return trans & 0x1;
550         }
551         return 0;
552 }
553
554 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
555                         int value)
556 {
557         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
558
559         tps80031_update(tps80031->dev, SLAVE_ID1,
560                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
561                         value, 0x1);
562 }
563
564 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
565 {
566         return -EIO;
567 }
568
569 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
570                                 int value)
571 {
572         tps80031_gpio_set(gc, offset, value);
573         return 0;
574 }
575
576 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
577 {
578         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
579         int ret;
580
581         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
582                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
583                                                 STATE_ON, STATE_MASK);
584         if (ret)
585                 return ret;
586
587         return tps80031_write(tps80031->dev, SLAVE_ID1,
588                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
589 }
590
591 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
592 {
593         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
594         tps80031_update(tps80031->dev, SLAVE_ID1,
595                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
596                                                 STATE_OFF, STATE_MASK);
597 }
598
599
600 static void tps80031_gpio_init(struct tps80031 *tps80031,
601                         struct tps80031_platform_data *pdata)
602 {
603         int ret;
604         int gpio_base = pdata->gpio_base;
605         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
606         struct tps80031_gpio_init_data *gpio_init_data = pdata->gpio_init_data;
607         int data_size = pdata->gpio_init_data_size;
608         static int preq_bit_pos[TPS80031_GPIO_NR] = {16, 17, 18};
609         int base_add;
610         int i;
611
612         if (gpio_base <= 0)
613                 return;
614
615         /* Configure the external request mode */
616         for (i = 0; i < data_size; ++i) {
617                 if (!(gpio_init_data[i].ext_control & EXT_PWR_REQ))
618                         continue;
619                 base_add = pmc_ext_control_base[gpio_init_data[i].gpio_nr];
620                 ret = tps80031_ext_power_req_config(tps80031->dev,
621                         gpio_init_data[i].ext_control,
622                         preq_bit_pos[gpio_init_data[i].gpio_nr],
623                         base_add + EXT_CONTROL_CFG_STATE,
624                         base_add + EXT_CONTROL_CFG_TRANS);
625                 if (!ret)
626                         dev_warn(tps80031->dev, "GPIO sleep control fails\n");
627         }
628
629         tps80031->gpio.owner            = THIS_MODULE;
630         tps80031->gpio.label            = tps->client->name;
631         tps80031->gpio.dev              = tps80031->dev;
632         tps80031->gpio.base             = gpio_base;
633         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
634         tps80031->gpio.can_sleep        = 1;
635
636         tps80031->gpio.request          = tps80031_gpio_enable;
637         tps80031->gpio.free             = tps80031_gpio_disable;
638         tps80031->gpio.direction_input  = tps80031_gpio_input;
639         tps80031->gpio.direction_output = tps80031_gpio_output;
640         tps80031->gpio.set              = tps80031_gpio_set;
641         tps80031->gpio.get              = tps80031_gpio_get;
642
643         ret = gpiochip_add(&tps80031->gpio);
644         if (ret)
645                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
646 }
647
648 static int __remove_subdev(struct device *dev, void *unused)
649 {
650         platform_device_unregister(to_platform_device(dev));
651         return 0;
652 }
653
654 static int tps80031_remove_subdevs(struct tps80031 *tps80031)
655 {
656         return device_for_each_child(tps80031->dev, NULL, __remove_subdev);
657 }
658
659 static void tps80031_irq_lock(struct irq_data *data)
660 {
661         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
662
663         mutex_lock(&tps80031->irq_lock);
664 }
665
666 static void tps80031_irq_enable(struct irq_data *data)
667 {
668         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
669         unsigned int __irq = data->irq - tps80031->irq_base;
670         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
671
672         if (irq_data->is_sec_int) {
673                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
674                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
675                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
676                 tps80031->irq_en |= (1 << irq_data->parent_int);
677         } else
678                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
679
680         tps80031->irq_en |= (1 << __irq);
681 }
682
683 static void tps80031_irq_disable(struct irq_data *data)
684 {
685         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
686
687         unsigned int __irq = data->irq - tps80031->irq_base;
688         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
689
690         if (irq_data->is_sec_int) {
691                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
692                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
693                 if (!tps80031->cont_int_en) {
694                         tps80031->mask_reg[irq_data->mask_reg] |=
695                                                 (1 << irq_data->mask_mask);
696                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
697                 }
698                 tps80031->irq_en &= ~(1 << __irq);
699         } else
700                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
701
702         tps80031->irq_en &= ~(1 << __irq);
703 }
704
705 static void tps80031_irq_sync_unlock(struct irq_data *data)
706 {
707         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
708         int i;
709
710         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
711                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
712                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
713                                                 TPS80031_INT_MSK_LINE_A + i,
714                                                 tps80031->mask_reg[i])))
715                                 if (!WARN_ON(tps80031_write(tps80031->dev,
716                                                 SLAVE_ID2,
717                                                 TPS80031_INT_MSK_STS_A + i,
718                                                 tps80031->mask_reg[i])))
719                                         tps80031->mask_cache[i] =
720                                                         tps80031->mask_reg[i];
721                 }
722         }
723
724         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
725                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
726                                 TPS80031_CONTROLLER_INT_MASK,
727                                 tps80031->cont_int_mask_reg)))
728                         tps80031->cont_int_mask_cache =
729                                                 tps80031->cont_int_mask_reg;
730         }
731
732         mutex_unlock(&tps80031->irq_lock);
733 }
734
735 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
736 {
737         struct tps80031 *tps80031 = data;
738         int ret = 0;
739         int i;
740         u8 cont_sts;
741         u8 org_sts;
742         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
743                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
744                                         __func__, irq);
745                 return IRQ_NONE;
746         }
747
748         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
749                         TPS80031_CONTROLLER_STAT1, &org_sts);
750         if (ret < 0) {
751                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
752                                 "status %d\n", __func__, ret);
753                 return IRQ_NONE;
754         }
755
756         /* Get change from last interrupt and mask for interested interrupt
757          * for charge control interrupt */
758         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
759         tps80031->prev_cont_stat1 = org_sts;
760         /* Clear watchdog timer state */
761         tps80031->prev_cont_stat1 &= ~(1 << 4);
762         cont_sts &= 0x5F;
763
764         for (i = 0; i < 8; ++i) {
765                 if (!controller_stat1_irq_nr[i])
766                         continue;
767
768                 if ((cont_sts & BIT(i)) &&
769                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
770                         handle_nested_irq(tps80031->irq_base +
771                                                 controller_stat1_irq_nr[i]);
772                 cont_sts &= ~BIT(i);
773         }
774         return IRQ_HANDLED;
775 }
776
777 static irqreturn_t tps80031_irq(int irq, void *data)
778 {
779         struct tps80031 *tps80031 = data;
780         int ret = 0;
781         u8 tmp[3];
782         u32 acks;
783         int i;
784
785         for (i = 0; i < 3; i++) {
786                 ret = tps80031_read(tps80031->dev, SLAVE_ID2,
787                         TPS80031_INT_STS_A + i, &tmp[i]);
788                 if (ret < 0) {
789                         dev_err(tps80031->dev, "failed to read interrupt "
790                                                         "status\n");
791                         return IRQ_NONE;
792                 }
793                 if (tmp[i]) {
794                         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
795                                         TPS80031_INT_STS_A + i, tmp[i]);
796                         if (ret < 0) {
797                                 dev_err(tps80031->dev, "failed to write "
798                                                         "interrupt status\n");
799                                 return IRQ_NONE;
800                         }
801                 }
802         }
803         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
804         while (acks) {
805                 i = __ffs(acks);
806                 if (tps80031->irq_en & (1 << i))
807                         handle_nested_irq(tps80031->irq_base + i);
808                 acks &= ~(1 << i);
809         }
810         return IRQ_HANDLED;
811 }
812
813 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
814                                 int irq_base)
815 {
816         int i, ret;
817
818         if (!irq_base) {
819                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
820                 return -EINVAL;
821         }
822
823         mutex_init(&tps80031->irq_lock);
824
825         for (i = 0; i < 3; i++) {
826                 tps80031->mask_reg[i] = 0xFF;
827                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
828                 tps80031_write(tps80031->dev, SLAVE_ID2,
829                                         TPS80031_INT_MSK_LINE_A + i,
830                                         tps80031->mask_cache[i]);
831                 tps80031_write(tps80031->dev, SLAVE_ID2,
832                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
833                 tps80031_write(tps80031->dev, SLAVE_ID2,
834                                         TPS80031_INT_STS_A + i, 0xFF);
835         }
836
837         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
838                                 TPS80031_CONTROLLER_INT_MASK,
839                                 &tps80031->cont_int_mask_reg);
840         if (ret < 0) {
841                 dev_err(tps80031->dev, "Error in reading the controller_mask "
842                                         "register %d\n", ret);
843                 return ret;
844         }
845
846         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
847         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
848         tps80031->cont_int_en = 0;
849         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
850                                 TPS80031_CONTROLLER_INT_MASK,
851                                 tps80031->cont_int_mask_reg);
852         if (ret < 0) {
853                 dev_err(tps80031->dev, "Error in writing the controller_mask "
854                                         "register %d\n", ret);
855                 return ret;
856         }
857
858         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
859                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
860         if (ret < 0) {
861                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
862                                 "status %d\n", __func__, ret);
863                 return ret;
864         }
865
866         /* Clear watch dog interrupt status in status */
867         tps80031->prev_cont_stat1 &= ~(1 << 4);
868
869         tps80031->irq_base = irq_base;
870
871         tps80031->irq_chip.name = "tps80031";
872         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
873         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
874         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
875         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
876
877         for (i = 0; i < TPS80031_INT_NR; i++) {
878                 int __irq = i + tps80031->irq_base;
879                 irq_set_chip_data(__irq, tps80031);
880                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
881                                          handle_simple_irq);
882                 irq_set_nested_thread(__irq, 1);
883 #ifdef CONFIG_ARM
884                 set_irq_flags(__irq, IRQF_VALID);
885 #endif
886         }
887
888         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
889                                 "tps80031", tps80031);
890         /* register the isr for the secondary interrupt */
891         if (!ret)
892                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
893                                 NULL, tps80031_charge_control_irq,
894                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
895         if (!ret) {
896
897                 device_init_wakeup(tps80031->dev, 1);
898                 enable_irq_wake(irq);
899         }
900
901         return ret;
902 }
903
904 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
905 {
906         int ret;
907         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
908                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
909         if (!ret)
910                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
911                                 base_add + EXT_CONTROL_CFG_TRANS,
912                                 STATE_ON, STATE_MASK);
913         if (ret < 0)
914                 dev_err(tps80031->dev, "Error in updating clock register\n");
915 }
916
917 static void tps80031_clk32k_init(struct tps80031 *tps80031,
918                         struct tps80031_platform_data *pdata)
919 {
920         struct tps80031_32kclock_plat_data *clk32k_pdata;
921
922         if (!(pdata && pdata->clk32k_pdata))
923                 return;
924
925         clk32k_pdata = pdata->clk32k_pdata;
926         if (clk32k_pdata->en_clk32kao)
927                 tps80031_clk32k_enable(tps80031, CLK32KAO_BASE_ADD);
928
929         if (clk32k_pdata->en_clk32kg)
930                 tps80031_clk32k_enable(tps80031, CLK32KG_BASE_ADD);
931
932         if (clk32k_pdata->en_clk32kaudio)
933                 tps80031_clk32k_enable(tps80031, CLK32KAUDIO_BASE_ADD);
934 }
935
936 static int __devinit tps80031_add_subdevs(struct tps80031 *tps80031,
937                                           struct tps80031_platform_data *pdata)
938 {
939         struct tps80031_subdev_info *subdev;
940         struct platform_device *pdev;
941         int i, ret = 0;
942
943         for (i = 0; i < pdata->num_subdevs; i++) {
944                 subdev = &pdata->subdevs[i];
945
946                 pdev = platform_device_alloc(subdev->name, subdev->id);
947
948                 pdev->dev.parent = tps80031->dev;
949                 pdev->dev.platform_data = subdev->platform_data;
950
951                 ret = platform_device_add(pdev);
952                 if (ret)
953                         goto failed;
954         }
955         return 0;
956
957 failed:
958         tps80031_remove_subdevs(tps80031);
959         return ret;
960 }
961
962 #ifdef CONFIG_DEBUG_FS
963 #include <linux/debugfs.h>
964 #include <linux/seq_file.h>
965 static void print_regs(const char *header, struct seq_file *s,
966                 int sid, int start_offset, int end_offset)
967 {
968         struct tps80031 *tps80031 = s->private;
969         struct tps80031_client *tps = &tps80031->tps_clients[sid];
970         uint8_t reg_val;
971         int i;
972         int ret;
973
974         seq_printf(s, "%s\n", header);
975         for (i = start_offset; i <= end_offset; ++i) {
976                 ret = __tps80031_read(tps->client, i, &reg_val);
977                 if (ret >= 0)
978                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
979                                                 tps->client->addr, i, reg_val);
980         }
981         seq_printf(s, "------------------\n");
982 }
983
984 static int dbg_tps_show(struct seq_file *s, void *unused)
985 {
986         seq_printf(s, "TPS80031 Registers\n");
987         seq_printf(s, "------------------\n");
988         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
989         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
990         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
991         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
992         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
993         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
994         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
995         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
996         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
997         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
998         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
999         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
1000         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
1001         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
1002         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
1003         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
1004         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
1005         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
1006         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
1007         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
1008         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
1009         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
1010         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
1011         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
1012         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
1013         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
1014         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
1015         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
1016         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
1017         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
1018         print_regs("PMC MISC Regs",  s, SLAVE_ID1, 0xE0, 0xEF);
1019         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
1020         print_regs("VERNUM Regs",    s, SLAVE_ID3, 0x87, 0x87);
1021         print_regs("EEPROM Regs",    s, SLAVE_ID3, 0xDF, 0xDF);
1022         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
1023         return 0;
1024 }
1025
1026 static int dbg_tps_open(struct inode *inode, struct file *file)
1027 {
1028         return single_open(file, dbg_tps_show, inode->i_private);
1029 }
1030
1031 static const struct file_operations debug_fops = {
1032         .open           = dbg_tps_open,
1033         .read           = seq_read,
1034         .llseek         = seq_lseek,
1035         .release        = single_release,
1036 };
1037
1038 static void __init tps80031_debuginit(struct tps80031 *tps)
1039 {
1040         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
1041                         tps, &debug_fops);
1042 }
1043 #else
1044 static void __init tps80031_debuginit(struct tps80031 *tpsi)
1045 {
1046         return;
1047 }
1048 #endif
1049
1050 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
1051 {
1052         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1053         int i;
1054
1055         if (client->irq)
1056                 free_irq(client->irq, tps80031);
1057
1058         if (tps80031->gpio.owner != NULL)
1059                 if (gpiochip_remove(&tps80031->gpio) < 0)
1060                         dev_err(&client->dev, "Error in removing the gpio driver\n");
1061
1062         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1063                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1064                 if (tps->client && tps->client != client)
1065                         i2c_unregister_device(tps->client);
1066                 tps80031->tps_clients[i].client = NULL;
1067                 mutex_destroy(&tps->lock);
1068         }
1069
1070         kfree(tps80031);
1071         return 0;
1072 }
1073
1074 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
1075                                         const struct i2c_device_id *id)
1076 {
1077         struct tps80031_platform_data *pdata = client->dev.platform_data;
1078         struct tps80031 *tps80031;
1079         struct tps80031_client *tps;
1080         int ret;
1081         int jtag_ver;
1082         int ep_ver;
1083         int i;
1084
1085         if (!pdata) {
1086                 dev_err(&client->dev, "tps80031 requires platform data\n");
1087                 return -ENOTSUPP;
1088         }
1089
1090         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
1091         if (jtag_ver < 0) {
1092                 dev_err(&client->dev, "Silicon version number read"
1093                                 " failed: %d\n", jtag_ver);
1094                 return -EIO;
1095         }
1096
1097         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
1098         if (ep_ver < 0) {
1099                 dev_err(&client->dev, "Silicon eeprom version read"
1100                                 " failed: %d\n", ep_ver);
1101                 return -EIO;
1102         }
1103
1104         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
1105                                                 jtag_ver, ep_ver);
1106
1107         tps80031 = kzalloc(sizeof(struct tps80031), GFP_KERNEL);
1108         if (tps80031 == NULL)
1109                 return -ENOMEM;
1110
1111         tps80031->es_version = jtag_ver;
1112         tps80031->dev = &client->dev;
1113         i2c_set_clientdata(client, tps80031);
1114         tps80031->chip_info = id->driver_data;
1115
1116         /* Set up slaves */
1117         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
1118         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
1119         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
1120         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
1121         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1122                 tps = &tps80031->tps_clients[i];
1123                 if (tps->addr == client->addr)
1124                         tps->client = client;
1125                 else
1126                         tps->client = i2c_new_dummy(client->adapter,
1127                                                 tps->addr);
1128                 if (!tps->client) {
1129                         dev_err(&client->dev, "can't attach client %d\n", i);
1130                         ret = -ENOMEM;
1131                         goto fail;
1132                 }
1133                 i2c_set_clientdata(tps->client, tps80031);
1134                 mutex_init(&tps->lock);
1135         }
1136
1137         if (client->irq) {
1138                 ret = tps80031_irq_init(tps80031, client->irq,
1139                                         pdata->irq_base);
1140                 if (ret) {
1141                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1142                         goto fail;
1143                 }
1144         }
1145         tps80031_init_ext_control(tps80031, pdata);
1146
1147         ret = tps80031_add_subdevs(tps80031, pdata);
1148         if (ret) {
1149                 dev_err(&client->dev, "add devices failed: %d\n", ret);
1150                 goto fail;
1151         }
1152
1153         tps80031_gpio_init(tps80031, pdata);
1154
1155         tps80031_clk32k_init(tps80031, pdata);
1156
1157         tps80031_debuginit(tps80031);
1158
1159         tps80031_dev = tps80031;
1160
1161         return 0;
1162
1163 fail:
1164         tps80031_i2c_remove(client);
1165         return ret;
1166 }
1167
1168 #ifdef CONFIG_PM
1169 static int tps80031_i2c_suspend(struct i2c_client *client, pm_message_t state)
1170 {
1171         if (client->irq)
1172                 disable_irq(client->irq);
1173         return 0;
1174 }
1175
1176 static int tps80031_i2c_resume(struct i2c_client *client)
1177 {
1178         if (client->irq)
1179                 enable_irq(client->irq);
1180         return 0;
1181 }
1182 #endif
1183
1184
1185 static const struct i2c_device_id tps80031_id_table[] = {
1186         { "tps80031", TPS80031 },
1187         { "tps80032", TPS80032 },
1188 };
1189 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1190
1191 static struct i2c_driver tps80031_driver = {
1192         .driver = {
1193                 .name   = "tps80031",
1194                 .owner  = THIS_MODULE,
1195         },
1196         .probe          = tps80031_i2c_probe,
1197         .remove         = __devexit_p(tps80031_i2c_remove),
1198 #ifdef CONFIG_PM
1199         .suspend        = tps80031_i2c_suspend,
1200         .resume         = tps80031_i2c_resume,
1201 #endif
1202         .id_table       = tps80031_id_table,
1203 };
1204
1205 static int __init tps80031_init(void)
1206 {
1207         return i2c_add_driver(&tps80031_driver);
1208 }
1209 subsys_initcall(tps80031_init);
1210
1211 static void __exit tps80031_exit(void)
1212 {
1213         i2c_del_driver(&tps80031_driver);
1214 }
1215 module_exit(tps80031_exit);
1216
1217 MODULE_DESCRIPTION("TPS80031 core driver");
1218 MODULE_LICENSE("GPL");