mfd: tps80031: Move external pwr req to core driver
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32
33 #include <linux/mfd/core.h>
34 #include <linux/mfd/tps80031.h>
35
36 /* interrupt related registers */
37 #define TPS80031_INT_STS_A              0xD0
38 #define TPS80031_INT_STS_B              0xD1
39 #define TPS80031_INT_STS_C              0xD2
40 #define TPS80031_INT_MSK_LINE_A         0xD3
41 #define TPS80031_INT_MSK_LINE_B         0xD4
42 #define TPS80031_INT_MSK_LINE_C         0xD5
43 #define TPS80031_INT_MSK_STS_A          0xD6
44 #define TPS80031_INT_MSK_STS_B          0xD7
45 #define TPS80031_INT_MSK_STS_C          0xD8
46
47 #define TPS80031_CONTROLLER_STAT1               0xE3
48 #define CONTROLLER_STAT1_BAT_TEMP               0
49 #define CONTROLLER_STAT1_BAT_REMOVED            1
50 #define CONTROLLER_STAT1_VBUS_DET               2
51 #define CONTROLLER_STAT1_VAC_DET                3
52 #define CONTROLLER_STAT1_FAULT_WDG              4
53 #define CONTROLLER_STAT1_LINCH_GATED            6
54
55 #define TPS80031_CONTROLLER_INT_MASK            0xE0
56 #define CONTROLLER_INT_MASK_MVAC_DET            0
57 #define CONTROLLER_INT_MASK_MVBUS_DET           1
58 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
59 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
60 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
61 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
62
63 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
64
65 /* Version number related register */
66 #define TPS80031_JTAGVERNUM             0x87
67 /* Epprom version */
68 #define TPS80031_EPROM_REV              0xDF
69
70 /* External control register */
71 #define REGEN1_BASE_ADD         0xAE
72 #define REGEN2_BASE_ADD         0xB1
73 #define SYSEN_BASE_ADD          0xB4
74
75 /* device control registers */
76 #define TPS80031_PHOENIX_DEV_ON 0x25
77 #define DEVOFF  1
78
79 #define CLK32KAO_BASE_ADD       0xBA
80 #define CLK32KG_BASE_ADD        0xBD
81 #define CLK32KAUDIO_BASE_ADD    0xC0
82
83 #define EXT_CONTROL_CFG_TRANS 0
84 #define EXT_CONTROL_CFG_STATE 1
85
86 #define STATE_OFF       0x00
87 #define STATE_ON        0x01
88 #define STATE_MASK      0x03
89
90 #define TRANS_SLEEP_OFF         0x00
91 #define TRANS_SLEEP_ON          0x04
92 #define TRANS_SLEEP_MASK        0x0C
93
94 #define TPS_NUM_SLAVES  4
95 #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \
96                 PWR_REQ_INPUT_PREQ3)
97 #define TPS80031_PREQ1_RES_ASS_A        0xD7
98 #define TPS80031_PREQ2_RES_ASS_A        0xDA
99 #define TPS80031_PREQ3_RES_ASS_A        0xDD
100 #define TPS80031_PHOENIX_MSK_TRANSITION 0x20
101
102
103 static u8 pmc_ext_control_base[] = {
104         REGEN1_BASE_ADD,
105         REGEN2_BASE_ADD,
106         SYSEN_BASE_ADD,
107 };
108
109 struct tps80031_irq_data {
110         u8      mask_reg;
111         u8      mask_mask;
112         u8      is_sec_int;
113         u8      parent_int;
114         u8      mask_sec_int_reg;
115         u8      int_mask_bit;
116         u8      int_sec_sts_reg;
117         u8      int_sts_bit;
118 };
119
120 #define TPS80031_IRQ(_reg, _mask)       \
121         {                                                       \
122                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
123                                 TPS80031_INT_MSK_LINE_A,        \
124                 .mask_mask = (_mask),                           \
125         }
126
127 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
128         {                                                               \
129                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
130                                 TPS80031_INT_MSK_LINE_A,                \
131                 .mask_mask = (_mask),                                   \
132                 .is_sec_int = true,                                     \
133                 .parent_int = TPS80031_INT_##_pint,                     \
134                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
135                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
136                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
137                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
138         }
139
140 static const struct tps80031_irq_data tps80031_irqs[] = {
141
142         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
143         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
144         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
145         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
146         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
147         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
148         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
149         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
150         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
151         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
152         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
153         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
154         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
155         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
156         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
157         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
158         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
159         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
160         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
161         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
162         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
163         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
164         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
165         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
166         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
167                                                 MBAT_TEMP,      BAT_TEMP),
168         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
169                                                 MBAT_REMOVED,   BAT_REMOVED),
170         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
171                                                 MVBUS_DET,      VBUS_DET),
172         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
173                                                 MVAC_DET,       VAC_DET),
174         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
175                                                 MFAULT_WDG,     FAULT_WDG),
176         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
177                                                 MLINCH_GATED,   LINCH_GATED),
178 };
179
180 static const int controller_stat1_irq_nr[] = {
181         TPS80031_INT_BAT_TEMP_OVRANGE,
182         TPS80031_INT_BAT_REMOVED,
183         TPS80031_INT_VBUS_DET,
184         TPS80031_INT_VAC_DET,
185         TPS80031_INT_FAULT_WDG,
186         0,
187         TPS80031_INT_LINCH_GATED,
188         0
189 };
190
191 /* Structure for TPS80031 Slaves */
192 struct tps80031_client {
193         struct i2c_client *client;
194         struct mutex lock;
195         u8 addr;
196 };
197
198 struct tps80031 {
199         struct device           *dev;
200         unsigned long           chip_info;
201
202         struct gpio_chip        gpio;
203         struct irq_chip         irq_chip;
204         struct mutex            irq_lock;
205         int                     irq_base;
206         u32                     irq_en;
207         u8                      mask_cache[3];
208         u8                      mask_reg[3];
209         u8                      cont_int_mask_reg;
210         u8                      cont_int_mask_cache;
211         u8                      cont_int_en;
212         u8                      prev_cont_stat1;
213         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
214 };
215
216 static inline int __tps80031_read(struct i2c_client *client,
217                                   int reg, uint8_t *val)
218 {
219         int ret;
220
221         ret = i2c_smbus_read_byte_data(client, reg);
222         if (ret < 0) {
223                 dev_err(&client->dev,
224                         "failed reading from addr 0x%02x, reg 0x%02x\n",
225                         client->addr, reg);
226                 return ret;
227         }
228
229         *val = (uint8_t)ret;
230
231         return 0;
232 }
233
234 static inline int __tps80031_reads(struct i2c_client *client, int reg,
235                                 int len, uint8_t *val)
236 {
237         int ret;
238
239         ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
240         if (ret < 0) {
241                 dev_err(&client->dev,
242                         "failed reading from addr 0x%02x, reg   0x%02x\n",
243                          client->addr, reg);
244                 return ret;
245         }
246
247         return 0;
248 }
249
250 static inline int __tps80031_write(struct i2c_client *client,
251                                  int reg, uint8_t val)
252 {
253         int ret;
254         ret = i2c_smbus_write_byte_data(client, reg, val);
255         if (ret < 0) {
256                 dev_err(&client->dev,
257                         "failed writing 0x%02x to 0x%02x\n", val, reg);
258                 return ret;
259         }
260
261         return 0;
262 }
263
264 static inline int __tps80031_writes(struct i2c_client *client, int reg,
265                                   int len, uint8_t *val)
266 {
267         int ret;
268
269         ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
270         if (ret < 0) {
271                 dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
272                 return ret;
273         }
274
275         return 0;
276 }
277
278 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
279 {
280         struct tps80031 *tps80031 = dev_get_drvdata(dev);
281         struct tps80031_client *tps = &tps80031->tps_clients[sid];
282         int ret;
283
284         mutex_lock(&tps->lock);
285         ret = __tps80031_write(tps->client, reg, val);
286         mutex_unlock(&tps->lock);
287
288         return ret;
289 }
290 EXPORT_SYMBOL_GPL(tps80031_write);
291
292 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
293 {
294         struct tps80031 *tps80031 = dev_get_drvdata(dev);
295         struct tps80031_client *tps = &tps80031->tps_clients[sid];
296         int ret;
297
298         mutex_lock(&tps->lock);
299         ret = __tps80031_writes(tps->client, reg, len, val);
300         mutex_unlock(&tps->lock);
301
302         return ret;
303 }
304 EXPORT_SYMBOL_GPL(tps80031_writes);
305
306 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
307 {
308         struct tps80031 *tps80031 = dev_get_drvdata(dev);
309         struct tps80031_client *tps = &tps80031->tps_clients[sid];
310
311         return __tps80031_read(tps->client, reg, val);
312 }
313 EXPORT_SYMBOL_GPL(tps80031_read);
314
315 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
316 {
317         struct tps80031 *tps80031 = dev_get_drvdata(dev);
318         struct tps80031_client *tps = &tps80031->tps_clients[sid];
319
320         return __tps80031_reads(tps->client, reg, len, val);
321 }
322 EXPORT_SYMBOL_GPL(tps80031_reads);
323
324 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
325 {
326         struct tps80031 *tps80031 = dev_get_drvdata(dev);
327         struct tps80031_client *tps = &tps80031->tps_clients[sid];
328         uint8_t reg_val;
329         int ret = 0;
330
331         mutex_lock(&tps->lock);
332
333         ret = __tps80031_read(tps->client, reg, &reg_val);
334         if (ret)
335                 goto out;
336
337         if ((reg_val & bit_mask) != bit_mask) {
338                 reg_val |= bit_mask;
339                 ret = __tps80031_write(tps->client, reg, reg_val);
340         }
341 out:
342         mutex_unlock(&tps->lock);
343         return ret;
344 }
345 EXPORT_SYMBOL_GPL(tps80031_set_bits);
346
347 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
348 {
349         struct tps80031 *tps80031 = dev_get_drvdata(dev);
350         struct tps80031_client *tps = &tps80031->tps_clients[sid];
351         uint8_t reg_val;
352         int ret = 0;
353
354         mutex_lock(&tps->lock);
355
356         ret = __tps80031_read(tps->client, reg, &reg_val);
357         if (ret)
358                 goto out;
359
360         if (reg_val & bit_mask) {
361                 reg_val &= ~bit_mask;
362                 ret = __tps80031_write(tps->client, reg, reg_val);
363         }
364 out:
365         mutex_unlock(&tps->lock);
366         return ret;
367 }
368 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
369
370 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
371                 uint8_t mask)
372 {
373         struct tps80031 *tps80031 = dev_get_drvdata(dev);
374         struct tps80031_client *tps = &tps80031->tps_clients[sid];
375         uint8_t reg_val;
376         int ret = 0;
377
378         mutex_lock(&tps->lock);
379
380         ret = __tps80031_read(tps->client, reg, &reg_val);
381         if (ret)
382                 goto out;
383
384         if ((reg_val & mask) != val) {
385                 reg_val = (reg_val & ~mask) | (val & mask);
386                 ret = __tps80031_write(tps->client, reg, reg_val);
387         }
388 out:
389         mutex_unlock(&tps->lock);
390         return ret;
391 }
392 EXPORT_SYMBOL_GPL(tps80031_update);
393
394 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
395                           uint8_t mask)
396 {
397         struct tps80031 *tps80031 = dev_get_drvdata(dev);
398         struct tps80031_client *tps = &tps80031->tps_clients[sid];
399         uint8_t reg_val;
400         int ret = 0;
401
402         mutex_lock(&tps->lock);
403
404         ret = __tps80031_read(tps->client, reg, &reg_val);
405         if (ret)
406                 goto out;
407
408         reg_val = (reg_val & ~mask) | (val & mask);
409         ret = __tps80031_write(tps->client, reg, reg_val);
410
411 out:
412         mutex_unlock(&tps->lock);
413         return ret;
414 }
415 EXPORT_SYMBOL_GPL(tps80031_force_update);
416
417 int tps80031_ext_power_req_config(struct device *dev,
418                 enum tps80031_ext_control ext_pwr_ctrl, int preq_bit,
419                 int state_reg_add, int trans_reg_add)
420 {
421         u8 res_ass_reg = 0;
422         int preq_mask_bit = 0;
423         int ret;
424
425         if (!(ext_pwr_ctrl & EXT_PWR_REQ))
426                 return 0;
427
428         if (ext_pwr_ctrl & PWR_REQ_INPUT_PREQ1) {
429                 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
430                 preq_mask_bit = 5;
431         } else if (ext_pwr_ctrl & PWR_REQ_INPUT_PREQ2) {
432                 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
433                 preq_mask_bit = 6;
434         } else if (ext_pwr_ctrl & PWR_REQ_INPUT_PREQ3) {
435                 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
436                 preq_mask_bit = 7;
437         }
438
439         /* Configure REQ_ASS registers */
440         ret = tps80031_set_bits(dev, SLAVE_ID1, res_ass_reg,
441                                         BIT(preq_bit & 0x7));
442         if (ret < 0) {
443                 dev_err(dev, "%s() Not able to set bit %d of "
444                         "reg %d error %d\n",
445                         __func__, preq_bit, res_ass_reg, ret);
446                 return ret;
447         }
448
449         /* Unmask the PREQ */
450         ret = tps80031_clr_bits(dev, SLAVE_ID1,
451                         TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
452         if (ret < 0) {
453                 dev_err(dev, "%s() Not able to clear bit %d of "
454                         "reg %d error %d\n",
455                          __func__, preq_mask_bit,
456                         TPS80031_PHOENIX_MSK_TRANSITION, ret);
457                 return ret;
458         }
459
460         /* Switch regulator control to resource now */
461         if (ext_pwr_ctrl &  (PWR_REQ_INPUT_PREQ2 | PWR_REQ_INPUT_PREQ3)) {
462                 ret = tps80031_update(dev, SLAVE_ID1, state_reg_add, 0x0,
463                                                 STATE_MASK);
464                 if (ret < 0)
465                         dev_err(dev, "%s() Error in writing the STATE "
466                                 "register %d error %d\n", __func__,
467                                 state_reg_add, ret);
468         } else {
469                 ret = tps80031_update(dev, SLAVE_ID1, trans_reg_add,
470                                 TRANS_SLEEP_OFF, TRANS_SLEEP_MASK);
471                 if (ret < 0)
472                         dev_err(dev, "%s() Error in writing the TRANS "
473                                 "register %d error %d\n", __func__,
474                                 trans_reg_add, ret);
475         }
476         return ret;
477 }
478 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
479
480 unsigned long tps80031_get_chip_info(struct device *dev)
481 {
482         struct tps80031 *tps80031 = dev_get_drvdata(dev);
483         return tps80031->chip_info;
484 }
485 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
486
487 static struct tps80031 *tps80031_dev;
488 int tps80031_power_off(void)
489 {
490         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
491
492         if (!tps->client)
493                 return -EINVAL;
494         dev_info(&tps->client->dev, "switching off PMU\n");
495         return __tps80031_write(tps->client, TPS80031_PHOENIX_DEV_ON, DEVOFF);
496 }
497
498 static void tps80031_init_ext_control(struct tps80031 *tps80031,
499                         struct tps80031_platform_data *pdata) {
500         int ret;
501         int i;
502
503         /* Clear all external control for this rail */
504         for (i = 0; i < 9; ++i) {
505                 tps80031_write(tps80031->dev, SLAVE_ID1,
506                                 TPS80031_PREQ1_RES_ASS_A + i, 0);
507                 if (ret < 0)
508                         dev_err(tps80031->dev, "%s() Error in clearing "
509                                 "register %02x\n", __func__,
510                                 TPS80031_PREQ1_RES_ASS_A + i);
511         }
512
513         /* Mask the PREQ */
514         ret = tps80031_set_bits(tps80031->dev, SLAVE_ID1,
515                         TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
516         if (ret < 0)
517                 dev_err(tps80031->dev, "%s() Not able to mask register "
518                         "0x%02x\n", __func__, TPS80031_PHOENIX_MSK_TRANSITION);
519 }
520
521 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
522 {
523         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
524         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
525         uint8_t state;
526         uint8_t trans;
527         int ret;
528
529         ret = __tps80031_read(tps->client,
530                         pmc_ext_control_base[offset] +
531                                 EXT_CONTROL_CFG_STATE, &state);
532         if (ret)
533                 return ret;
534
535         if (state != 0) {
536                 ret = __tps80031_read(tps->client,
537                                 pmc_ext_control_base[offset] +
538                                         EXT_CONTROL_CFG_TRANS, &trans);
539                 if (ret)
540                         return ret;
541                 return trans & 0x1;
542         }
543         return 0;
544 }
545
546 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
547                         int value)
548 {
549         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
550
551         tps80031_update(tps80031->dev, SLAVE_ID1,
552                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
553                         value, 0x1);
554 }
555
556 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
557 {
558         return -EIO;
559 }
560
561 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
562                                 int value)
563 {
564         tps80031_gpio_set(gc, offset, value);
565         return 0;
566 }
567
568 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
569 {
570         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
571         int ret;
572
573         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
574                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
575                                                 STATE_ON, STATE_MASK);
576         if (ret)
577                 return ret;
578
579         return tps80031_write(tps80031->dev, SLAVE_ID1,
580                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
581 }
582
583 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
584 {
585         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
586         tps80031_update(tps80031->dev, SLAVE_ID1,
587                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
588                                                 STATE_OFF, STATE_MASK);
589 }
590
591
592 static void tps80031_gpio_init(struct tps80031 *tps80031,
593                         struct tps80031_platform_data *pdata)
594 {
595         int ret;
596         int gpio_base = pdata->gpio_base;
597         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
598         struct tps80031_gpio_init_data *gpio_init_data = pdata->gpio_init_data;
599         int data_size = pdata->gpio_init_data_size;
600         static int preq_bit_pos[TPS80031_GPIO_NR] = {16, 17, 18};
601         int base_add;
602         int i;
603
604         if (gpio_base <= 0)
605                 return;
606
607         /* Configure the external request mode */
608         for (i = 0; i < data_size; ++i) {
609                 if (!(gpio_init_data[i].ext_control & EXT_PWR_REQ))
610                         continue;
611                 base_add = pmc_ext_control_base[gpio_init_data[i].gpio_nr];
612                 ret = tps80031_ext_power_req_config(tps80031->dev,
613                         gpio_init_data[i].ext_control,
614                         preq_bit_pos[gpio_init_data[i].gpio_nr],
615                         base_add + EXT_CONTROL_CFG_STATE,
616                         base_add + EXT_CONTROL_CFG_TRANS);
617                 if (!ret)
618                         dev_warn(tps80031->dev, "GPIO sleep control fails\n");
619         }
620
621         tps80031->gpio.owner            = THIS_MODULE;
622         tps80031->gpio.label            = tps->client->name;
623         tps80031->gpio.dev              = tps80031->dev;
624         tps80031->gpio.base             = gpio_base;
625         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
626         tps80031->gpio.can_sleep        = 1;
627
628         tps80031->gpio.request          = tps80031_gpio_enable;
629         tps80031->gpio.free             = tps80031_gpio_disable;
630         tps80031->gpio.direction_input  = tps80031_gpio_input;
631         tps80031->gpio.direction_output = tps80031_gpio_output;
632         tps80031->gpio.set              = tps80031_gpio_set;
633         tps80031->gpio.get              = tps80031_gpio_get;
634
635         ret = gpiochip_add(&tps80031->gpio);
636         if (ret)
637                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
638 }
639
640 static int __remove_subdev(struct device *dev, void *unused)
641 {
642         platform_device_unregister(to_platform_device(dev));
643         return 0;
644 }
645
646 static int tps80031_remove_subdevs(struct tps80031 *tps80031)
647 {
648         return device_for_each_child(tps80031->dev, NULL, __remove_subdev);
649 }
650
651 static void tps80031_irq_lock(struct irq_data *data)
652 {
653         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
654
655         mutex_lock(&tps80031->irq_lock);
656 }
657
658 static void tps80031_irq_enable(struct irq_data *data)
659 {
660         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
661         unsigned int __irq = data->irq - tps80031->irq_base;
662         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
663
664         if (irq_data->is_sec_int) {
665                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
666                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
667                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
668                 tps80031->irq_en |= (1 << irq_data->parent_int);
669         } else
670                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
671
672         tps80031->irq_en |= (1 << __irq);
673 }
674
675 static void tps80031_irq_disable(struct irq_data *data)
676 {
677         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
678
679         unsigned int __irq = data->irq - tps80031->irq_base;
680         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
681
682         if (irq_data->is_sec_int) {
683                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
684                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
685                 if (!tps80031->cont_int_en) {
686                         tps80031->mask_reg[irq_data->mask_reg] |=
687                                                 (1 << irq_data->mask_mask);
688                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
689                 }
690                 tps80031->irq_en &= ~(1 << __irq);
691         } else
692                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
693
694         tps80031->irq_en &= ~(1 << __irq);
695 }
696
697 static void tps80031_irq_sync_unlock(struct irq_data *data)
698 {
699         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
700         int i;
701
702         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
703                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
704                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
705                                                 TPS80031_INT_MSK_LINE_A + i,
706                                                 tps80031->mask_reg[i])))
707                                 if (!WARN_ON(tps80031_write(tps80031->dev,
708                                                 SLAVE_ID2,
709                                                 TPS80031_INT_MSK_STS_A + i,
710                                                 tps80031->mask_reg[i])))
711                                         tps80031->mask_cache[i] =
712                                                         tps80031->mask_reg[i];
713                 }
714         }
715
716         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
717                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
718                                 TPS80031_CONTROLLER_INT_MASK,
719                                 tps80031->cont_int_mask_reg)))
720                         tps80031->cont_int_mask_cache =
721                                                 tps80031->cont_int_mask_reg;
722         }
723
724         mutex_unlock(&tps80031->irq_lock);
725 }
726
727 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
728 {
729         struct tps80031 *tps80031 = data;
730         int ret = 0;
731         int i;
732         u8 cont_sts;
733         u8 org_sts;
734         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
735                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
736                                         __func__, irq);
737                 return IRQ_NONE;
738         }
739
740         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
741                         TPS80031_CONTROLLER_STAT1, &org_sts);
742         if (ret < 0) {
743                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
744                                 "status %d\n", __func__, ret);
745                 return IRQ_NONE;
746         }
747
748         /* Get change from last interrupt and mask for interested interrupt
749          * for charge control interrupt */
750         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
751         tps80031->prev_cont_stat1 = org_sts;
752         /* Clear watchdog timer state */
753         tps80031->prev_cont_stat1 &= ~(1 << 4);
754         cont_sts &= 0x5F;
755
756         for (i = 0; i < 8; ++i) {
757                 if (!controller_stat1_irq_nr[i])
758                         continue;
759
760                 if ((cont_sts & BIT(i)) &&
761                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
762                         handle_nested_irq(tps80031->irq_base +
763                                                 controller_stat1_irq_nr[i]);
764                 cont_sts &= ~BIT(i);
765         }
766         return IRQ_HANDLED;
767 }
768
769 static irqreturn_t tps80031_irq(int irq, void *data)
770 {
771         struct tps80031 *tps80031 = data;
772         int ret = 0;
773         u8 tmp[3];
774         u32 acks;
775         int i;
776
777         for (i = 0; i < 3; i++) {
778                 ret = tps80031_read(tps80031->dev, SLAVE_ID2,
779                         TPS80031_INT_STS_A + i, &tmp[i]);
780                 if (ret < 0) {
781                         dev_err(tps80031->dev, "failed to read interrupt "
782                                                         "status\n");
783                         return IRQ_NONE;
784                 }
785                 if (tmp[i]) {
786                         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
787                                         TPS80031_INT_STS_A + i, tmp[i]);
788                         if (ret < 0) {
789                                 dev_err(tps80031->dev, "failed to write "
790                                                         "interrupt status\n");
791                                 return IRQ_NONE;
792                         }
793                 }
794         }
795         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
796         while (acks) {
797                 i = __ffs(acks);
798                 if (tps80031->irq_en & (1 << i))
799                         handle_nested_irq(tps80031->irq_base + i);
800                 acks &= ~(1 << i);
801         }
802         return IRQ_HANDLED;
803 }
804
805 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
806                                 int irq_base)
807 {
808         int i, ret;
809
810         if (!irq_base) {
811                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
812                 return -EINVAL;
813         }
814
815         mutex_init(&tps80031->irq_lock);
816
817         for (i = 0; i < 3; i++) {
818                 tps80031->mask_reg[i] = 0xFF;
819                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
820                 tps80031_write(tps80031->dev, SLAVE_ID2,
821                                         TPS80031_INT_MSK_LINE_A + i,
822                                         tps80031->mask_cache[i]);
823                 tps80031_write(tps80031->dev, SLAVE_ID2,
824                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
825                 tps80031_write(tps80031->dev, SLAVE_ID2,
826                                         TPS80031_INT_STS_A + i, 0xFF);
827         }
828
829         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
830                                 TPS80031_CONTROLLER_INT_MASK,
831                                 &tps80031->cont_int_mask_reg);
832         if (ret < 0) {
833                 dev_err(tps80031->dev, "Error in reading the controller_mask "
834                                         "register %d\n", ret);
835                 return ret;
836         }
837
838         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
839         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
840         tps80031->cont_int_en = 0;
841         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
842                                 TPS80031_CONTROLLER_INT_MASK,
843                                 tps80031->cont_int_mask_reg);
844         if (ret < 0) {
845                 dev_err(tps80031->dev, "Error in writing the controller_mask "
846                                         "register %d\n", ret);
847                 return ret;
848         }
849
850         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
851                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
852         if (ret < 0) {
853                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
854                                 "status %d\n", __func__, ret);
855                 return ret;
856         }
857
858         /* Clear watch dog interrupt status in status */
859         tps80031->prev_cont_stat1 &= ~(1 << 4);
860
861         tps80031->irq_base = irq_base;
862
863         tps80031->irq_chip.name = "tps80031";
864         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
865         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
866         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
867         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
868
869         for (i = 0; i < TPS80031_INT_NR; i++) {
870                 int __irq = i + tps80031->irq_base;
871                 irq_set_chip_data(__irq, tps80031);
872                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
873                                          handle_simple_irq);
874                 irq_set_nested_thread(__irq, 1);
875 #ifdef CONFIG_ARM
876                 set_irq_flags(__irq, IRQF_VALID);
877 #endif
878         }
879
880         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
881                                 "tps80031", tps80031);
882         /* register the isr for the secondary interrupt */
883         if (!ret)
884                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
885                                 NULL, tps80031_charge_control_irq,
886                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
887         if (!ret) {
888
889                 device_init_wakeup(tps80031->dev, 1);
890                 enable_irq_wake(irq);
891         }
892
893         return ret;
894 }
895
896 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
897 {
898         int ret;
899         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
900                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
901         if (!ret)
902                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
903                                 base_add + EXT_CONTROL_CFG_TRANS,
904                                 STATE_ON, STATE_MASK);
905         if (ret < 0)
906                 dev_err(tps80031->dev, "Error in updating clock register\n");
907 }
908
909 static void tps80031_clk32k_init(struct tps80031 *tps80031,
910                         struct tps80031_platform_data *pdata)
911 {
912         struct tps80031_32kclock_plat_data *clk32k_pdata;
913
914         if (!(pdata && pdata->clk32k_pdata))
915                 return;
916
917         clk32k_pdata = pdata->clk32k_pdata;
918         if (clk32k_pdata->en_clk32kao)
919                 tps80031_clk32k_enable(tps80031, CLK32KAO_BASE_ADD);
920
921         if (clk32k_pdata->en_clk32kg)
922                 tps80031_clk32k_enable(tps80031, CLK32KG_BASE_ADD);
923
924         if (clk32k_pdata->en_clk32kaudio)
925                 tps80031_clk32k_enable(tps80031, CLK32KAUDIO_BASE_ADD);
926 }
927
928 static int __devinit tps80031_add_subdevs(struct tps80031 *tps80031,
929                                           struct tps80031_platform_data *pdata)
930 {
931         struct tps80031_subdev_info *subdev;
932         struct platform_device *pdev;
933         int i, ret = 0;
934
935         for (i = 0; i < pdata->num_subdevs; i++) {
936                 subdev = &pdata->subdevs[i];
937
938                 pdev = platform_device_alloc(subdev->name, subdev->id);
939
940                 pdev->dev.parent = tps80031->dev;
941                 pdev->dev.platform_data = subdev->platform_data;
942
943                 ret = platform_device_add(pdev);
944                 if (ret)
945                         goto failed;
946         }
947         return 0;
948
949 failed:
950         tps80031_remove_subdevs(tps80031);
951         return ret;
952 }
953
954 #ifdef CONFIG_DEBUG_FS
955 #include <linux/debugfs.h>
956 #include <linux/seq_file.h>
957 static void print_regs(const char *header, struct seq_file *s,
958                 int sid, int start_offset, int end_offset)
959 {
960         struct tps80031 *tps80031 = s->private;
961         struct tps80031_client *tps = &tps80031->tps_clients[sid];
962         uint8_t reg_val;
963         int i;
964         int ret;
965
966         seq_printf(s, "%s\n", header);
967         for (i = start_offset; i <= end_offset; ++i) {
968                 ret = __tps80031_read(tps->client, i, &reg_val);
969                 if (ret >= 0)
970                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
971                                                 tps->client->addr, i, reg_val);
972         }
973         seq_printf(s, "------------------\n");
974 }
975
976 static int dbg_tps_show(struct seq_file *s, void *unused)
977 {
978         seq_printf(s, "TPS80031 Registers\n");
979         seq_printf(s, "------------------\n");
980         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
981         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
982         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
983         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
984         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
985         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
986         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
987         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
988         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
989         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
990         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
991         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
992         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
993         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
994         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
995         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
996         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
997         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
998         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
999         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
1000         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
1001         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
1002         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
1003         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
1004         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
1005         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
1006         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
1007         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
1008         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
1009         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
1010         print_regs("PMC MISC Regs",  s, SLAVE_ID1, 0xE0, 0xEF);
1011         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
1012         print_regs("VERNUM Regs",    s, SLAVE_ID1, 0x87, 0x87);
1013         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
1014         return 0;
1015 }
1016
1017 static int dbg_tps_open(struct inode *inode, struct file *file)
1018 {
1019         return single_open(file, dbg_tps_show, inode->i_private);
1020 }
1021
1022 static const struct file_operations debug_fops = {
1023         .open           = dbg_tps_open,
1024         .read           = seq_read,
1025         .llseek         = seq_lseek,
1026         .release        = single_release,
1027 };
1028
1029 static void __init tps80031_debuginit(struct tps80031 *tps)
1030 {
1031         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
1032                         tps, &debug_fops);
1033 }
1034 #else
1035 static void __init tps80031_debuginit(struct tps80031 *tpsi)
1036 {
1037         return;
1038 }
1039 #endif
1040
1041 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
1042 {
1043         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1044         int i;
1045
1046         if (client->irq)
1047                 free_irq(client->irq, tps80031);
1048
1049         if (tps80031->gpio.owner != NULL)
1050                 if (gpiochip_remove(&tps80031->gpio) < 0)
1051                         dev_err(&client->dev, "Error in removing the gpio driver\n");
1052
1053         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1054                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1055                 if (tps->client && tps->client != client)
1056                         i2c_unregister_device(tps->client);
1057                 tps80031->tps_clients[i].client = NULL;
1058                 mutex_destroy(&tps->lock);
1059         }
1060
1061         kfree(tps80031);
1062         return 0;
1063 }
1064
1065 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
1066                                         const struct i2c_device_id *id)
1067 {
1068         struct tps80031_platform_data *pdata = client->dev.platform_data;
1069         struct tps80031 *tps80031;
1070         struct tps80031_client *tps;
1071         int ret;
1072         int jtag_ver;
1073         int ep_ver;
1074         int i;
1075
1076         if (!pdata) {
1077                 dev_err(&client->dev, "tps80031 requires platform data\n");
1078                 return -ENOTSUPP;
1079         }
1080
1081         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
1082         if (jtag_ver < 0) {
1083                 dev_err(&client->dev, "Silicon version number read"
1084                                 " failed: %d\n", jtag_ver);
1085                 return -EIO;
1086         }
1087
1088         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
1089         if (ep_ver < 0) {
1090                 dev_err(&client->dev, "Silicon eeprom version read"
1091                                 " failed: %d\n", ep_ver);
1092                 return -EIO;
1093         }
1094
1095         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
1096                                                 jtag_ver, ep_ver);
1097
1098         tps80031 = kzalloc(sizeof(struct tps80031), GFP_KERNEL);
1099         if (tps80031 == NULL)
1100                 return -ENOMEM;
1101
1102         tps80031->dev = &client->dev;
1103         i2c_set_clientdata(client, tps80031);
1104         tps80031->chip_info = id->driver_data;
1105
1106         /* Set up slaves */
1107         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
1108         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
1109         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
1110         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
1111         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1112                 tps = &tps80031->tps_clients[i];
1113                 if (tps->addr == client->addr)
1114                         tps->client = client;
1115                 else
1116                         tps->client = i2c_new_dummy(client->adapter,
1117                                                 tps->addr);
1118                 if (!tps->client) {
1119                         dev_err(&client->dev, "can't attach client %d\n", i);
1120                         ret = -ENOMEM;
1121                         goto fail;
1122                 }
1123                 i2c_set_clientdata(tps->client, tps80031);
1124                 mutex_init(&tps->lock);
1125         }
1126
1127         if (client->irq) {
1128                 ret = tps80031_irq_init(tps80031, client->irq,
1129                                         pdata->irq_base);
1130                 if (ret) {
1131                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1132                         goto fail;
1133                 }
1134         }
1135         tps80031_init_ext_control(tps80031, pdata);
1136
1137         ret = tps80031_add_subdevs(tps80031, pdata);
1138         if (ret) {
1139                 dev_err(&client->dev, "add devices failed: %d\n", ret);
1140                 goto fail;
1141         }
1142
1143         tps80031_gpio_init(tps80031, pdata);
1144
1145         tps80031_clk32k_init(tps80031, pdata);
1146
1147         tps80031_debuginit(tps80031);
1148
1149         tps80031_dev = tps80031;
1150
1151         return 0;
1152
1153 fail:
1154         tps80031_i2c_remove(client);
1155         return ret;
1156 }
1157
1158 #ifdef CONFIG_PM
1159 static int tps80031_i2c_suspend(struct i2c_client *client, pm_message_t state)
1160 {
1161         if (client->irq)
1162                 disable_irq(client->irq);
1163         return 0;
1164 }
1165
1166 static int tps80031_i2c_resume(struct i2c_client *client)
1167 {
1168         if (client->irq)
1169                 enable_irq(client->irq);
1170         return 0;
1171 }
1172 #endif
1173
1174
1175 static const struct i2c_device_id tps80031_id_table[] = {
1176         { "tps80031", TPS80031 },
1177         { "tps80032", TPS80032 },
1178 };
1179 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1180
1181 static struct i2c_driver tps80031_driver = {
1182         .driver = {
1183                 .name   = "tps80031",
1184                 .owner  = THIS_MODULE,
1185         },
1186         .probe          = tps80031_i2c_probe,
1187         .remove         = __devexit_p(tps80031_i2c_remove),
1188 #ifdef CONFIG_PM
1189         .suspend        = tps80031_i2c_suspend,
1190         .resume         = tps80031_i2c_resume,
1191 #endif
1192         .id_table       = tps80031_id_table,
1193 };
1194
1195 static int __init tps80031_init(void)
1196 {
1197         return i2c_add_driver(&tps80031_driver);
1198 }
1199 subsys_initcall(tps80031_init);
1200
1201 static void __exit tps80031_exit(void)
1202 {
1203         i2c_del_driver(&tps80031_driver);
1204 }
1205 module_exit(tps80031_exit);
1206
1207 MODULE_DESCRIPTION("TPS80031 core driver");
1208 MODULE_LICENSE("GPL");